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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
c27a02cd | 35 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
b67bfe0d | 39 | #include <linux/rculist.h> |
c27a02cd YP |
40 | #include <linux/if_ether.h> |
41 | #include <linux/if_vlan.h> | |
42 | #include <linux/vmalloc.h> | |
43 | ||
44 | #include "mlx4_en.h" | |
45 | ||
51151a16 ED |
46 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
47 | struct mlx4_en_rx_alloc *page_alloc, | |
48 | const struct mlx4_en_frag_info *frag_info, | |
49 | gfp_t _gfp) | |
50 | { | |
51 | int order; | |
52 | struct page *page; | |
53 | dma_addr_t dma; | |
54 | ||
55 | for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { | |
56 | gfp_t gfp = _gfp; | |
57 | ||
58 | if (order) | |
59 | gfp |= __GFP_COMP | __GFP_NOWARN; | |
60 | page = alloc_pages(gfp, order); | |
61 | if (likely(page)) | |
62 | break; | |
63 | if (--order < 0 || | |
64 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
65 | return -ENOMEM; | |
66 | } | |
67 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
68 | PCI_DMA_FROMDEVICE); | |
69 | if (dma_mapping_error(priv->ddev, dma)) { | |
70 | put_page(page); | |
71 | return -ENOMEM; | |
72 | } | |
70fbe079 | 73 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
74 | page_alloc->page = page; |
75 | page_alloc->dma = dma; | |
70fbe079 | 76 | page_alloc->page_offset = frag_info->frag_align; |
51151a16 ED |
77 | /* Not doing get_page() for each frag is a big win |
78 | * on asymetric workloads. | |
79 | */ | |
70fbe079 AV |
80 | atomic_set(&page->_count, |
81 | page_alloc->page_size / frag_info->frag_stride); | |
51151a16 ED |
82 | return 0; |
83 | } | |
84 | ||
4cce66cd TLSC |
85 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
86 | struct mlx4_en_rx_desc *rx_desc, | |
87 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
88 | struct mlx4_en_rx_alloc *ring_alloc, |
89 | gfp_t gfp) | |
c27a02cd | 90 | { |
4cce66cd | 91 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 92 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd YP |
93 | struct page *page; |
94 | dma_addr_t dma; | |
4cce66cd | 95 | int i; |
c27a02cd | 96 | |
4cce66cd TLSC |
97 | for (i = 0; i < priv->num_frags; i++) { |
98 | frag_info = &priv->frag_info[i]; | |
51151a16 | 99 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
100 | page_alloc[i].page_offset += frag_info->frag_stride; |
101 | ||
102 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
103 | ring_alloc[i].page_size) | |
51151a16 | 104 | continue; |
70fbe079 | 105 | |
51151a16 ED |
106 | if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) |
107 | goto out; | |
4cce66cd | 108 | } |
c27a02cd | 109 | |
4cce66cd TLSC |
110 | for (i = 0; i < priv->num_frags; i++) { |
111 | frags[i] = ring_alloc[i]; | |
70fbe079 | 112 | dma = ring_alloc[i].dma + ring_alloc[i].page_offset; |
4cce66cd TLSC |
113 | ring_alloc[i] = page_alloc[i]; |
114 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 115 | } |
4cce66cd | 116 | |
c27a02cd | 117 | return 0; |
4cce66cd | 118 | |
4cce66cd TLSC |
119 | out: |
120 | while (i--) { | |
121 | frag_info = &priv->frag_info[i]; | |
51151a16 | 122 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 123 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
70fbe079 | 124 | page_alloc[i].page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
125 | page = page_alloc[i].page; |
126 | atomic_set(&page->_count, 1); | |
127 | put_page(page); | |
128 | } | |
4cce66cd TLSC |
129 | } |
130 | return -ENOMEM; | |
131 | } | |
132 | ||
133 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
134 | struct mlx4_en_rx_alloc *frags, | |
135 | int i) | |
136 | { | |
51151a16 | 137 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
4cce66cd | 138 | |
70fbe079 AV |
139 | if (frags[i].page_offset + frag_info->frag_stride > |
140 | frags[i].page_size) | |
141 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, | |
142 | PCI_DMA_FROMDEVICE); | |
51151a16 | 143 | |
4cce66cd TLSC |
144 | if (frags[i].page) |
145 | put_page(frags[i].page); | |
c27a02cd YP |
146 | } |
147 | ||
148 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
149 | struct mlx4_en_rx_ring *ring) | |
150 | { | |
c27a02cd | 151 | int i; |
51151a16 | 152 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
153 | |
154 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 155 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 156 | |
51151a16 ED |
157 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
158 | frag_info, GFP_KERNEL)) | |
4cce66cd | 159 | goto out; |
c27a02cd YP |
160 | } |
161 | return 0; | |
162 | ||
163 | out: | |
164 | while (i--) { | |
51151a16 ED |
165 | struct page *page; |
166 | ||
c27a02cd | 167 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 168 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 | 169 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
170 | page = page_alloc->page; |
171 | atomic_set(&page->_count, 1); | |
172 | put_page(page); | |
c27a02cd YP |
173 | page_alloc->page = NULL; |
174 | } | |
175 | return -ENOMEM; | |
176 | } | |
177 | ||
178 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
179 | struct mlx4_en_rx_ring *ring) | |
180 | { | |
181 | struct mlx4_en_rx_alloc *page_alloc; | |
182 | int i; | |
183 | ||
184 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
185 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
186 | ||
c27a02cd | 187 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
188 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
189 | i, page_count(page_alloc->page)); | |
c27a02cd | 190 | |
4cce66cd | 191 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 AV |
192 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
193 | while (page_alloc->page_offset + frag_info->frag_stride < | |
194 | page_alloc->page_size) { | |
51151a16 | 195 | put_page(page_alloc->page); |
70fbe079 | 196 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 197 | } |
c27a02cd YP |
198 | page_alloc->page = NULL; |
199 | } | |
200 | } | |
201 | ||
c27a02cd YP |
202 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
203 | struct mlx4_en_rx_ring *ring, int index) | |
204 | { | |
205 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
206 | int possible_frags; |
207 | int i; | |
208 | ||
c27a02cd YP |
209 | /* Set size and memtype fields */ |
210 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
211 | rx_desc->data[i].byte_count = |
212 | cpu_to_be32(priv->frag_info[i].frag_size); | |
213 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
214 | } | |
215 | ||
216 | /* If the number of used fragments does not fill up the ring stride, | |
217 | * remaining (unused) fragments must be padded with null address/size | |
218 | * and a special memory key */ | |
219 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
220 | for (i = priv->num_frags; i < possible_frags; i++) { | |
221 | rx_desc->data[i].byte_count = 0; | |
222 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
223 | rx_desc->data[i].addr = 0; | |
224 | } | |
225 | } | |
226 | ||
c27a02cd | 227 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
228 | struct mlx4_en_rx_ring *ring, int index, |
229 | gfp_t gfp) | |
c27a02cd YP |
230 | { |
231 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
232 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
233 | (index << priv->log_rx_info); | |
c27a02cd | 234 | |
51151a16 | 235 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
236 | } |
237 | ||
238 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) | |
239 | { | |
240 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
241 | } | |
242 | ||
38aab07c YP |
243 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
244 | struct mlx4_en_rx_ring *ring, | |
245 | int index) | |
246 | { | |
4cce66cd | 247 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
248 | int nr; |
249 | ||
4cce66cd | 250 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 251 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 252 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 253 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
254 | } |
255 | } | |
256 | ||
c27a02cd YP |
257 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
258 | { | |
c27a02cd YP |
259 | struct mlx4_en_rx_ring *ring; |
260 | int ring_ind; | |
261 | int buf_ind; | |
38aab07c | 262 | int new_size; |
c27a02cd YP |
263 | |
264 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
265 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
266 | ring = &priv->rx_ring[ring_ind]; | |
267 | ||
268 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 ED |
269 | ring->actual_size, |
270 | GFP_KERNEL)) { | |
c27a02cd | 271 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
453a6082 YP |
272 | en_err(priv, "Failed to allocate " |
273 | "enough rx buffers\n"); | |
c27a02cd YP |
274 | return -ENOMEM; |
275 | } else { | |
38aab07c | 276 | new_size = rounddown_pow_of_two(ring->actual_size); |
453a6082 YP |
277 | en_warn(priv, "Only %d buffers allocated " |
278 | "reducing ring size to %d", | |
279 | ring->actual_size, new_size); | |
38aab07c | 280 | goto reduce_rings; |
c27a02cd YP |
281 | } |
282 | } | |
283 | ring->actual_size++; | |
284 | ring->prod++; | |
285 | } | |
286 | } | |
38aab07c YP |
287 | return 0; |
288 | ||
289 | reduce_rings: | |
290 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
291 | ring = &priv->rx_ring[ring_ind]; | |
292 | while (ring->actual_size > new_size) { | |
293 | ring->actual_size--; | |
294 | ring->prod--; | |
295 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
296 | } | |
38aab07c YP |
297 | } |
298 | ||
c27a02cd YP |
299 | return 0; |
300 | } | |
301 | ||
c27a02cd YP |
302 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
303 | struct mlx4_en_rx_ring *ring) | |
304 | { | |
c27a02cd | 305 | int index; |
c27a02cd | 306 | |
453a6082 YP |
307 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
308 | ring->cons, ring->prod); | |
c27a02cd YP |
309 | |
310 | /* Unmap and free Rx buffers */ | |
38aab07c | 311 | BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); |
c27a02cd YP |
312 | while (ring->cons != ring->prod) { |
313 | index = ring->cons & ring->size_mask; | |
453a6082 | 314 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 315 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
316 | ++ring->cons; |
317 | } | |
318 | } | |
319 | ||
c27a02cd YP |
320 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
321 | struct mlx4_en_rx_ring *ring, u32 size, u16 stride) | |
322 | { | |
323 | struct mlx4_en_dev *mdev = priv->mdev; | |
4cce66cd | 324 | int err = -ENOMEM; |
c27a02cd YP |
325 | int tmp; |
326 | ||
c27a02cd YP |
327 | ring->prod = 0; |
328 | ring->cons = 0; | |
329 | ring->size = size; | |
330 | ring->size_mask = size - 1; | |
331 | ring->stride = stride; | |
332 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 333 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
334 | |
335 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 336 | sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 337 | ring->rx_info = vmalloc(tmp); |
e404decb | 338 | if (!ring->rx_info) |
c27a02cd | 339 | return -ENOMEM; |
e404decb | 340 | |
453a6082 | 341 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
342 | ring->rx_info, tmp); |
343 | ||
344 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, | |
345 | ring->buf_size, 2 * PAGE_SIZE); | |
346 | if (err) | |
347 | goto err_ring; | |
348 | ||
349 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
350 | if (err) { | |
453a6082 | 351 | en_err(priv, "Failed to map RX buffer\n"); |
c27a02cd YP |
352 | goto err_hwq; |
353 | } | |
354 | ring->buf = ring->wqres.buf.direct.buf; | |
355 | ||
ec693d47 AV |
356 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
357 | ||
c27a02cd YP |
358 | return 0; |
359 | ||
c27a02cd YP |
360 | err_hwq: |
361 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
362 | err_ring: | |
363 | vfree(ring->rx_info); | |
364 | ring->rx_info = NULL; | |
365 | return err; | |
366 | } | |
367 | ||
368 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
369 | { | |
c27a02cd YP |
370 | struct mlx4_en_rx_ring *ring; |
371 | int i; | |
372 | int ring_ind; | |
373 | int err; | |
374 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
375 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
376 | |
377 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
378 | ring = &priv->rx_ring[ring_ind]; | |
379 | ||
380 | ring->prod = 0; | |
381 | ring->cons = 0; | |
382 | ring->actual_size = 0; | |
383 | ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; | |
384 | ||
385 | ring->stride = stride; | |
9f519f68 YP |
386 | if (ring->stride <= TXBB_SIZE) |
387 | ring->buf += TXBB_SIZE; | |
388 | ||
c27a02cd YP |
389 | ring->log_stride = ffs(ring->stride) - 1; |
390 | ring->buf_size = ring->size * ring->stride; | |
391 | ||
392 | memset(ring->buf, 0, ring->buf_size); | |
393 | mlx4_en_update_rx_prod_db(ring); | |
394 | ||
4cce66cd | 395 | /* Initialize all descriptors */ |
c27a02cd YP |
396 | for (i = 0; i < ring->size; i++) |
397 | mlx4_en_init_rx_desc(priv, ring, i); | |
398 | ||
399 | /* Initialize page allocators */ | |
400 | err = mlx4_en_init_allocator(priv, ring); | |
401 | if (err) { | |
453a6082 | 402 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
403 | if (ring->stride <= TXBB_SIZE) |
404 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
405 | ring_ind--; |
406 | goto err_allocator; | |
c27a02cd | 407 | } |
c27a02cd | 408 | } |
b58515be IM |
409 | err = mlx4_en_fill_rx_buffers(priv); |
410 | if (err) | |
c27a02cd YP |
411 | goto err_buffers; |
412 | ||
413 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
414 | ring = &priv->rx_ring[ring_ind]; | |
415 | ||
00d7d7bc | 416 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 417 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
418 | } |
419 | ||
420 | return 0; | |
421 | ||
c27a02cd YP |
422 | err_buffers: |
423 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
424 | mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); | |
425 | ||
426 | ring_ind = priv->rx_ring_num - 1; | |
427 | err_allocator: | |
428 | while (ring_ind >= 0) { | |
60b1809f YP |
429 | if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE) |
430 | priv->rx_ring[ring_ind].buf -= TXBB_SIZE; | |
c27a02cd YP |
431 | mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); |
432 | ring_ind--; | |
433 | } | |
434 | return err; | |
435 | } | |
436 | ||
437 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, | |
68355f71 | 438 | struct mlx4_en_rx_ring *ring, u32 size, u16 stride) |
c27a02cd YP |
439 | { |
440 | struct mlx4_en_dev *mdev = priv->mdev; | |
441 | ||
c27a02cd | 442 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
68355f71 | 443 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
444 | vfree(ring->rx_info); |
445 | ring->rx_info = NULL; | |
1eb8c695 AV |
446 | #ifdef CONFIG_RFS_ACCEL |
447 | mlx4_en_cleanup_filters(priv, ring); | |
448 | #endif | |
c27a02cd YP |
449 | } |
450 | ||
451 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
452 | struct mlx4_en_rx_ring *ring) | |
453 | { | |
c27a02cd | 454 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
455 | if (ring->stride <= TXBB_SIZE) |
456 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
457 | mlx4_en_destroy_allocator(priv, ring); |
458 | } | |
459 | ||
460 | ||
c27a02cd YP |
461 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
462 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 463 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 464 | struct sk_buff *skb, |
c27a02cd YP |
465 | int length) |
466 | { | |
90278c9f | 467 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
468 | struct mlx4_en_frag_info *frag_info; |
469 | int nr; | |
470 | dma_addr_t dma; | |
471 | ||
4cce66cd | 472 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
473 | for (nr = 0; nr < priv->num_frags; nr++) { |
474 | frag_info = &priv->frag_info[nr]; | |
475 | if (length <= frag_info->frag_prefix_size) | |
476 | break; | |
4cce66cd TLSC |
477 | if (!frags[nr].page) |
478 | goto fail; | |
c27a02cd | 479 | |
c27a02cd | 480 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
481 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
482 | DMA_FROM_DEVICE); | |
c27a02cd | 483 | |
4cce66cd | 484 | /* Save page reference in skb */ |
4cce66cd TLSC |
485 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
486 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 487 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 488 | skb->truesize += frag_info->frag_stride; |
51151a16 | 489 | frags[nr].page = NULL; |
c27a02cd YP |
490 | } |
491 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 492 | if (nr > 0) |
9e903e08 ED |
493 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
494 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
495 | return nr; |
496 | ||
497 | fail: | |
c27a02cd YP |
498 | while (nr > 0) { |
499 | nr--; | |
311761c8 | 500 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
501 | } |
502 | return 0; | |
503 | } | |
504 | ||
505 | ||
506 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
507 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 508 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
509 | unsigned int length) |
510 | { | |
c27a02cd YP |
511 | struct sk_buff *skb; |
512 | void *va; | |
513 | int used_frags; | |
514 | dma_addr_t dma; | |
515 | ||
c056b734 | 516 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 517 | if (!skb) { |
453a6082 | 518 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
519 | return NULL; |
520 | } | |
c27a02cd YP |
521 | skb_reserve(skb, NET_IP_ALIGN); |
522 | skb->len = length; | |
c27a02cd YP |
523 | |
524 | /* Get pointer to first fragment so we could copy the headers into the | |
525 | * (linear part of the) skb */ | |
70fbe079 | 526 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
527 | |
528 | if (length <= SMALL_PACKET_SIZE) { | |
529 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 530 | * sync buffers for the copy */ |
c27a02cd | 531 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 532 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 533 | DMA_FROM_DEVICE); |
c27a02cd | 534 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
535 | skb->tail += length; |
536 | } else { | |
c27a02cd | 537 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
538 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
539 | skb, length); | |
785a0982 YP |
540 | if (unlikely(!used_frags)) { |
541 | kfree_skb(skb); | |
542 | return NULL; | |
543 | } | |
c27a02cd YP |
544 | skb_shinfo(skb)->nr_frags = used_frags; |
545 | ||
546 | /* Copy headers into the skb linear buffer */ | |
547 | memcpy(skb->data, va, HEADER_COPY_SIZE); | |
548 | skb->tail += HEADER_COPY_SIZE; | |
549 | ||
550 | /* Skip headers in first fragment */ | |
551 | skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; | |
552 | ||
553 | /* Adjust size of first fragment */ | |
9e903e08 | 554 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE); |
c27a02cd YP |
555 | skb->data_len = length - HEADER_COPY_SIZE; |
556 | } | |
557 | return skb; | |
558 | } | |
559 | ||
e7c1c2c4 YP |
560 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
561 | { | |
562 | int i; | |
563 | int offset = ETH_HLEN; | |
564 | ||
565 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
566 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
567 | goto out_loopback; | |
568 | } | |
569 | /* Loopback found */ | |
570 | priv->loopback_ok = 1; | |
571 | ||
572 | out_loopback: | |
573 | dev_kfree_skb_any(skb); | |
574 | } | |
c27a02cd | 575 | |
4cce66cd TLSC |
576 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
577 | struct mlx4_en_rx_ring *ring) | |
578 | { | |
579 | int index = ring->prod & ring->size_mask; | |
580 | ||
581 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
51151a16 | 582 | if (mlx4_en_prepare_rx_desc(priv, ring, index, GFP_ATOMIC)) |
4cce66cd TLSC |
583 | break; |
584 | ring->prod++; | |
585 | index = ring->prod & ring->size_mask; | |
586 | } | |
587 | } | |
588 | ||
c27a02cd YP |
589 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
590 | { | |
591 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 592 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd YP |
593 | struct mlx4_cqe *cqe; |
594 | struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; | |
4cce66cd | 595 | struct mlx4_en_rx_alloc *frags; |
c27a02cd YP |
596 | struct mlx4_en_rx_desc *rx_desc; |
597 | struct sk_buff *skb; | |
598 | int index; | |
599 | int nr; | |
600 | unsigned int length; | |
601 | int polled = 0; | |
602 | int ip_summed; | |
08ff3235 | 603 | int factor = priv->cqe_factor; |
ec693d47 | 604 | u64 timestamp; |
c27a02cd YP |
605 | |
606 | if (!priv->port_up) | |
607 | return 0; | |
608 | ||
609 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx | |
610 | * descriptor offset can be deduced from the CQE index instead of | |
611 | * reading 'cqe->index' */ | |
612 | index = cq->mcq.cons_index & ring->size_mask; | |
08ff3235 | 613 | cqe = &cq->buf[(index << factor) + factor]; |
c27a02cd YP |
614 | |
615 | /* Process all completed CQEs */ | |
616 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
617 | cq->mcq.cons_index & cq->size)) { | |
618 | ||
4cce66cd | 619 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
620 | rx_desc = ring->buf + (index << ring->log_stride); |
621 | ||
622 | /* | |
623 | * make sure we read the CQE after we read the ownership bit | |
624 | */ | |
625 | rmb(); | |
626 | ||
627 | /* Drop packet on bad receive or bad checksum */ | |
628 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
629 | MLX4_CQE_OPCODE_ERROR)) { | |
453a6082 | 630 | en_err(priv, "CQE completed in error - vendor " |
c27a02cd YP |
631 | "syndrom:%d syndrom:%d\n", |
632 | ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome, | |
633 | ((struct mlx4_err_cqe *) cqe)->syndrome); | |
634 | goto next; | |
635 | } | |
636 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 637 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
638 | goto next; |
639 | } | |
640 | ||
79aeaccd YB |
641 | /* Check if we need to drop the packet if SRIOV is not enabled |
642 | * and not performing the selftest or flb disabled | |
643 | */ | |
644 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
645 | struct ethhdr *ethh; | |
646 | dma_addr_t dma; | |
79aeaccd YB |
647 | /* Get pointer to first fragment since we haven't |
648 | * skb yet and cast it to ethhdr struct | |
649 | */ | |
650 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
651 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
652 | DMA_FROM_DEVICE); | |
653 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 654 | frags[0].page_offset); |
79aeaccd | 655 | |
c07cb4b0 YB |
656 | if (is_multicast_ether_addr(ethh->h_dest)) { |
657 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
658 | struct hlist_head *bucket; |
659 | unsigned int mac_hash; | |
660 | ||
661 | /* Drop the packet, since HW loopback-ed it */ | |
662 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
663 | bucket = &priv->mac_hash[mac_hash]; | |
664 | rcu_read_lock(); | |
b67bfe0d | 665 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 YB |
666 | if (ether_addr_equal_64bits(entry->mac, |
667 | ethh->h_source)) { | |
668 | rcu_read_unlock(); | |
669 | goto next; | |
670 | } | |
671 | } | |
672 | rcu_read_unlock(); | |
673 | } | |
79aeaccd | 674 | } |
5b4c4d36 | 675 | |
c27a02cd YP |
676 | /* |
677 | * Packet is OK - process it. | |
678 | */ | |
679 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 680 | length -= ring->fcs_del; |
c27a02cd YP |
681 | ring->bytes += length; |
682 | ring->packets++; | |
683 | ||
c8c64cff | 684 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
c27a02cd YP |
685 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && |
686 | (cqe->checksum == cpu_to_be16(0xffff))) { | |
ad04378c | 687 | ring->csum_ok++; |
f1d29a3f | 688 | /* This packet is eligible for GRO if it is: |
c27a02cd YP |
689 | * - DIX Ethernet (type interpretation) |
690 | * - TCP/IP (v4) | |
691 | * - without IP options | |
9e77a2b8 AV |
692 | * - not an IP fragment |
693 | * - no LLS polling in progress | |
694 | */ | |
695 | if (!mlx4_en_cq_ll_polling(cq) && | |
696 | (dev->features & NETIF_F_GRO)) { | |
fa37a958 | 697 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); |
ebc872c7 YP |
698 | if (!gro_skb) |
699 | goto next; | |
c27a02cd | 700 | |
4cce66cd TLSC |
701 | nr = mlx4_en_complete_rx_desc(priv, |
702 | rx_desc, frags, gro_skb, | |
703 | length); | |
c27a02cd YP |
704 | if (!nr) |
705 | goto next; | |
706 | ||
fa37a958 YP |
707 | skb_shinfo(gro_skb)->nr_frags = nr; |
708 | gro_skb->len = length; | |
709 | gro_skb->data_len = length; | |
fa37a958 YP |
710 | gro_skb->ip_summed = CHECKSUM_UNNECESSARY; |
711 | ||
ec693d47 AV |
712 | if ((cqe->vlan_my_qpn & |
713 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) && | |
714 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
f1b553fb JP |
715 | u16 vid = be16_to_cpu(cqe->sl_vid); |
716 | ||
86a9bad3 | 717 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); |
f1b553fb JP |
718 | } |
719 | ||
ad86107f YP |
720 | if (dev->features & NETIF_F_RXHASH) |
721 | gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); | |
722 | ||
3b61008d | 723 | skb_record_rx_queue(gro_skb, cq->ring); |
c27a02cd | 724 | |
ec693d47 AV |
725 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
726 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
727 | mlx4_en_fill_hwtstamps(mdev, | |
728 | skb_hwtstamps(gro_skb), | |
729 | timestamp); | |
730 | } | |
731 | ||
732 | napi_gro_frags(&cq->napi); | |
c27a02cd YP |
733 | goto next; |
734 | } | |
735 | ||
f1d29a3f | 736 | /* GRO not possible, complete processing here */ |
c27a02cd | 737 | ip_summed = CHECKSUM_UNNECESSARY; |
c27a02cd YP |
738 | } else { |
739 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 740 | ring->csum_none++; |
c27a02cd YP |
741 | } |
742 | } else { | |
743 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 744 | ring->csum_none++; |
c27a02cd YP |
745 | } |
746 | ||
4cce66cd | 747 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
c27a02cd YP |
748 | if (!skb) { |
749 | priv->stats.rx_dropped++; | |
750 | goto next; | |
751 | } | |
752 | ||
e7c1c2c4 YP |
753 | if (unlikely(priv->validate_loopback)) { |
754 | validate_loopback(priv, skb); | |
755 | goto next; | |
756 | } | |
757 | ||
c27a02cd YP |
758 | skb->ip_summed = ip_summed; |
759 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 760 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 761 | |
ad86107f YP |
762 | if (dev->features & NETIF_F_RXHASH) |
763 | skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); | |
764 | ||
ec693d47 AV |
765 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
766 | MLX4_CQE_VLAN_PRESENT_MASK) && | |
767 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) | |
86a9bad3 | 768 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
f1b553fb | 769 | |
ec693d47 AV |
770 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
771 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
772 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
773 | timestamp); | |
774 | } | |
775 | ||
8b80cda5 | 776 | skb_mark_napi_id(skb, &cq->napi); |
9e77a2b8 | 777 | |
c27a02cd | 778 | /* Push it up the stack */ |
f1b553fb | 779 | netif_receive_skb(skb); |
c27a02cd | 780 | |
c27a02cd | 781 | next: |
4cce66cd TLSC |
782 | for (nr = 0; nr < priv->num_frags; nr++) |
783 | mlx4_en_free_frag(priv, frags, nr); | |
784 | ||
c27a02cd YP |
785 | ++cq->mcq.cons_index; |
786 | index = (cq->mcq.cons_index) & ring->size_mask; | |
08ff3235 | 787 | cqe = &cq->buf[(index << factor) + factor]; |
f1d29a3f | 788 | if (++polled == budget) |
c27a02cd | 789 | goto out; |
c27a02cd YP |
790 | } |
791 | ||
c27a02cd YP |
792 | out: |
793 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
794 | mlx4_cq_set_ci(&cq->mcq); | |
795 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
796 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 797 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
798 | mlx4_en_update_rx_prod_db(ring); |
799 | return polled; | |
800 | } | |
801 | ||
802 | ||
803 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
804 | { | |
805 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
806 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
807 | ||
808 | if (priv->port_up) | |
288379f0 | 809 | napi_schedule(&cq->napi); |
c27a02cd YP |
810 | else |
811 | mlx4_en_arm_cq(priv, cq); | |
812 | } | |
813 | ||
814 | /* Rx CQ polling - called by NAPI */ | |
815 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
816 | { | |
817 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
818 | struct net_device *dev = cq->dev; | |
819 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
820 | int done; | |
821 | ||
9e77a2b8 AV |
822 | if (!mlx4_en_cq_lock_napi(cq)) |
823 | return budget; | |
824 | ||
c27a02cd YP |
825 | done = mlx4_en_process_rx_cq(dev, cq, budget); |
826 | ||
9e77a2b8 AV |
827 | mlx4_en_cq_unlock_napi(cq); |
828 | ||
c27a02cd YP |
829 | /* If we used up all the quota - we're probably not done yet... */ |
830 | if (done == budget) | |
831 | INC_PERF_COUNTER(priv->pstats.napi_quota); | |
832 | else { | |
833 | /* Done for now */ | |
288379f0 | 834 | napi_complete(napi); |
c27a02cd YP |
835 | mlx4_en_arm_cq(priv, cq); |
836 | } | |
837 | return done; | |
838 | } | |
839 | ||
51151a16 | 840 | static const int frag_sizes[] = { |
c27a02cd YP |
841 | FRAG_SZ0, |
842 | FRAG_SZ1, | |
843 | FRAG_SZ2, | |
844 | FRAG_SZ3 | |
845 | }; | |
846 | ||
847 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
848 | { | |
849 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
850 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; | |
851 | int buf_size = 0; | |
852 | int i = 0; | |
853 | ||
854 | while (buf_size < eff_mtu) { | |
855 | priv->frag_info[i].frag_size = | |
856 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
857 | frag_sizes[i] : eff_mtu - buf_size; | |
858 | priv->frag_info[i].frag_prefix_size = buf_size; | |
859 | if (!i) { | |
860 | priv->frag_info[i].frag_align = NET_IP_ALIGN; | |
861 | priv->frag_info[i].frag_stride = | |
862 | ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); | |
863 | } else { | |
864 | priv->frag_info[i].frag_align = 0; | |
865 | priv->frag_info[i].frag_stride = | |
866 | ALIGN(frag_sizes[i], SMP_CACHE_BYTES); | |
867 | } | |
c27a02cd YP |
868 | buf_size += priv->frag_info[i].frag_size; |
869 | i++; | |
870 | } | |
871 | ||
872 | priv->num_frags = i; | |
873 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 874 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 875 | |
453a6082 | 876 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d " |
c27a02cd YP |
877 | "num_frags:%d):\n", eff_mtu, priv->num_frags); |
878 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
879 | en_err(priv, |
880 | " frag:%d - size:%d prefix:%d align:%d stride:%d\n", | |
881 | i, | |
882 | priv->frag_info[i].frag_size, | |
883 | priv->frag_info[i].frag_prefix_size, | |
884 | priv->frag_info[i].frag_align, | |
885 | priv->frag_info[i].frag_stride); | |
c27a02cd YP |
886 | } |
887 | } | |
888 | ||
889 | /* RSS related functions */ | |
890 | ||
9f519f68 YP |
891 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
892 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
893 | enum mlx4_qp_state *state, |
894 | struct mlx4_qp *qp) | |
895 | { | |
896 | struct mlx4_en_dev *mdev = priv->mdev; | |
897 | struct mlx4_qp_context *context; | |
898 | int err = 0; | |
899 | ||
14f8dc49 JP |
900 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
901 | if (!context) | |
c27a02cd | 902 | return -ENOMEM; |
c27a02cd YP |
903 | |
904 | err = mlx4_qp_alloc(mdev->dev, qpn, qp); | |
905 | if (err) { | |
453a6082 | 906 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 907 | goto out; |
c27a02cd YP |
908 | } |
909 | qp->event = mlx4_en_sqp_event; | |
910 | ||
911 | memset(context, 0, sizeof *context); | |
00d7d7bc | 912 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 913 | qpn, ring->cqn, -1, context); |
9f519f68 | 914 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 915 | |
f3a9d1f2 | 916 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 917 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 918 | context->param3 |= cpu_to_be32(1 << 29); |
4a5f4dd8 YP |
919 | ring->fcs_del = ETH_FCS_LEN; |
920 | } else | |
921 | ring->fcs_del = 0; | |
f3a9d1f2 | 922 | |
9f519f68 | 923 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
924 | if (err) { |
925 | mlx4_qp_remove(mdev->dev, qp); | |
926 | mlx4_qp_free(mdev->dev, qp); | |
927 | } | |
9f519f68 | 928 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
929 | out: |
930 | kfree(context); | |
931 | return err; | |
932 | } | |
933 | ||
cabdc8ee HHZ |
934 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
935 | { | |
936 | int err; | |
937 | u32 qpn; | |
938 | ||
939 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn); | |
940 | if (err) { | |
941 | en_err(priv, "Failed reserving drop qpn\n"); | |
942 | return err; | |
943 | } | |
944 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp); | |
945 | if (err) { | |
946 | en_err(priv, "Failed allocating drop qp\n"); | |
947 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
948 | return err; | |
949 | } | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
954 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
955 | { | |
956 | u32 qpn; | |
957 | ||
958 | qpn = priv->drop_qp.qpn; | |
959 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
960 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
961 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
962 | } | |
963 | ||
c27a02cd YP |
964 | /* Allocate rx qp's and configure them according to rss map */ |
965 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
966 | { | |
967 | struct mlx4_en_dev *mdev = priv->mdev; | |
968 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
969 | struct mlx4_qp_context context; | |
876f6e67 | 970 | struct mlx4_rss_context *rss_context; |
93d3e367 | 971 | int rss_rings; |
c27a02cd | 972 | void *ptr; |
876f6e67 | 973 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 974 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 975 | int i, qpn; |
c27a02cd YP |
976 | int err = 0; |
977 | int good_qps = 0; | |
ad86107f YP |
978 | static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC, |
979 | 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD, | |
980 | 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; | |
c27a02cd | 981 | |
453a6082 | 982 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
983 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
984 | priv->rx_ring_num, | |
985 | &rss_map->base_qpn); | |
c27a02cd | 986 | if (err) { |
b6b912e0 | 987 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
988 | return err; |
989 | } | |
990 | ||
b6b912e0 | 991 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 992 | qpn = rss_map->base_qpn + i; |
9f519f68 | 993 | err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i], |
c27a02cd YP |
994 | &rss_map->state[i], |
995 | &rss_map->qps[i]); | |
996 | if (err) | |
997 | goto rss_err; | |
998 | ||
999 | ++good_qps; | |
1000 | } | |
1001 | ||
1002 | /* Configure RSS indirection qp */ | |
c27a02cd YP |
1003 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp); |
1004 | if (err) { | |
453a6082 | 1005 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1006 | goto rss_err; |
c27a02cd YP |
1007 | } |
1008 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1009 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
0e98b523 | 1010 | priv->rx_ring[0].cqn, -1, &context); |
c27a02cd | 1011 | |
93d3e367 YP |
1012 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1013 | rss_rings = priv->rx_ring_num; | |
1014 | else | |
1015 | rss_rings = priv->prof->rss_rings; | |
1016 | ||
876f6e67 OG |
1017 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1018 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1019 | rss_context = ptr; |
93d3e367 | 1020 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1021 | (rss_map->base_qpn)); |
89efea25 | 1022 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1023 | if (priv->mdev->profile.udp_rss) { |
1024 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1025 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1026 | } | |
0533943c | 1027 | rss_context->flags = rss_mask; |
876f6e67 | 1028 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
ad86107f | 1029 | for (i = 0; i < 10; i++) |
39b2c4eb | 1030 | rss_context->rss_key[i] = cpu_to_be32(rsskey[i]); |
c27a02cd YP |
1031 | |
1032 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, | |
1033 | &rss_map->indir_qp, &rss_map->indir_state); | |
1034 | if (err) | |
1035 | goto indir_err; | |
1036 | ||
1037 | return 0; | |
1038 | ||
1039 | indir_err: | |
1040 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1041 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1042 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1043 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1044 | rss_err: |
1045 | for (i = 0; i < good_qps; i++) { | |
1046 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1047 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1048 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1049 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1050 | } | |
b6b912e0 | 1051 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1052 | return err; |
1053 | } | |
1054 | ||
1055 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1056 | { | |
1057 | struct mlx4_en_dev *mdev = priv->mdev; | |
1058 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1059 | int i; | |
1060 | ||
1061 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1062 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1063 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1064 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1065 | |
b6b912e0 | 1066 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1067 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1068 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1069 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1070 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1071 | } | |
b6b912e0 | 1072 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1073 | } |