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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
c27a02cd | 35 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
b67bfe0d | 39 | #include <linux/rculist.h> |
c27a02cd YP |
40 | #include <linux/if_ether.h> |
41 | #include <linux/if_vlan.h> | |
42 | #include <linux/vmalloc.h> | |
35f6f453 | 43 | #include <linux/irq.h> |
c27a02cd | 44 | |
f8c6455b SM |
45 | #if IS_ENABLED(CONFIG_IPV6) |
46 | #include <net/ip6_checksum.h> | |
47 | #endif | |
48 | ||
c27a02cd YP |
49 | #include "mlx4_en.h" |
50 | ||
51151a16 ED |
51 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
52 | struct mlx4_en_rx_alloc *page_alloc, | |
53 | const struct mlx4_en_frag_info *frag_info, | |
54 | gfp_t _gfp) | |
55 | { | |
56 | int order; | |
57 | struct page *page; | |
58 | dma_addr_t dma; | |
59 | ||
60 | for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { | |
61 | gfp_t gfp = _gfp; | |
62 | ||
63 | if (order) | |
64 | gfp |= __GFP_COMP | __GFP_NOWARN; | |
65 | page = alloc_pages(gfp, order); | |
66 | if (likely(page)) | |
67 | break; | |
68 | if (--order < 0 || | |
69 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
70 | return -ENOMEM; | |
71 | } | |
72 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
73 | PCI_DMA_FROMDEVICE); | |
74 | if (dma_mapping_error(priv->ddev, dma)) { | |
75 | put_page(page); | |
76 | return -ENOMEM; | |
77 | } | |
70fbe079 | 78 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
79 | page_alloc->page = page; |
80 | page_alloc->dma = dma; | |
5f6e9800 | 81 | page_alloc->page_offset = 0; |
51151a16 | 82 | /* Not doing get_page() for each frag is a big win |
98226208 | 83 | * on asymetric workloads. Note we can not use atomic_set(). |
51151a16 | 84 | */ |
98226208 ED |
85 | atomic_add(page_alloc->page_size / frag_info->frag_stride - 1, |
86 | &page->_count); | |
51151a16 ED |
87 | return 0; |
88 | } | |
89 | ||
4cce66cd TLSC |
90 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
91 | struct mlx4_en_rx_desc *rx_desc, | |
92 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
93 | struct mlx4_en_rx_alloc *ring_alloc, |
94 | gfp_t gfp) | |
c27a02cd | 95 | { |
4cce66cd | 96 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 97 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd YP |
98 | struct page *page; |
99 | dma_addr_t dma; | |
4cce66cd | 100 | int i; |
c27a02cd | 101 | |
4cce66cd TLSC |
102 | for (i = 0; i < priv->num_frags; i++) { |
103 | frag_info = &priv->frag_info[i]; | |
51151a16 | 104 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
105 | page_alloc[i].page_offset += frag_info->frag_stride; |
106 | ||
107 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
108 | ring_alloc[i].page_size) | |
51151a16 | 109 | continue; |
70fbe079 | 110 | |
51151a16 ED |
111 | if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) |
112 | goto out; | |
4cce66cd | 113 | } |
c27a02cd | 114 | |
4cce66cd TLSC |
115 | for (i = 0; i < priv->num_frags; i++) { |
116 | frags[i] = ring_alloc[i]; | |
70fbe079 | 117 | dma = ring_alloc[i].dma + ring_alloc[i].page_offset; |
4cce66cd TLSC |
118 | ring_alloc[i] = page_alloc[i]; |
119 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 120 | } |
4cce66cd | 121 | |
c27a02cd | 122 | return 0; |
4cce66cd | 123 | |
4cce66cd TLSC |
124 | out: |
125 | while (i--) { | |
51151a16 | 126 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 127 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
70fbe079 | 128 | page_alloc[i].page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
129 | page = page_alloc[i].page; |
130 | atomic_set(&page->_count, 1); | |
131 | put_page(page); | |
132 | } | |
4cce66cd TLSC |
133 | } |
134 | return -ENOMEM; | |
135 | } | |
136 | ||
137 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
138 | struct mlx4_en_rx_alloc *frags, | |
139 | int i) | |
140 | { | |
51151a16 | 141 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
021f1107 | 142 | u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; |
4cce66cd | 143 | |
021f1107 AV |
144 | |
145 | if (next_frag_end > frags[i].page_size) | |
70fbe079 AV |
146 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, |
147 | PCI_DMA_FROMDEVICE); | |
51151a16 | 148 | |
4cce66cd TLSC |
149 | if (frags[i].page) |
150 | put_page(frags[i].page); | |
c27a02cd YP |
151 | } |
152 | ||
153 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
154 | struct mlx4_en_rx_ring *ring) | |
155 | { | |
c27a02cd | 156 | int i; |
51151a16 | 157 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
158 | |
159 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 160 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 161 | |
51151a16 | 162 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
1ab25f86 | 163 | frag_info, GFP_KERNEL | __GFP_COLD)) |
4cce66cd | 164 | goto out; |
c27a02cd YP |
165 | } |
166 | return 0; | |
167 | ||
168 | out: | |
169 | while (i--) { | |
51151a16 ED |
170 | struct page *page; |
171 | ||
c27a02cd | 172 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 173 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 | 174 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
175 | page = page_alloc->page; |
176 | atomic_set(&page->_count, 1); | |
177 | put_page(page); | |
c27a02cd YP |
178 | page_alloc->page = NULL; |
179 | } | |
180 | return -ENOMEM; | |
181 | } | |
182 | ||
183 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
184 | struct mlx4_en_rx_ring *ring) | |
185 | { | |
186 | struct mlx4_en_rx_alloc *page_alloc; | |
187 | int i; | |
188 | ||
189 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
190 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
191 | ||
c27a02cd | 192 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
193 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
194 | i, page_count(page_alloc->page)); | |
c27a02cd | 195 | |
4cce66cd | 196 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 AV |
197 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
198 | while (page_alloc->page_offset + frag_info->frag_stride < | |
199 | page_alloc->page_size) { | |
51151a16 | 200 | put_page(page_alloc->page); |
70fbe079 | 201 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 202 | } |
c27a02cd YP |
203 | page_alloc->page = NULL; |
204 | } | |
205 | } | |
206 | ||
c27a02cd YP |
207 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
208 | struct mlx4_en_rx_ring *ring, int index) | |
209 | { | |
210 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
211 | int possible_frags; |
212 | int i; | |
213 | ||
c27a02cd YP |
214 | /* Set size and memtype fields */ |
215 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
216 | rx_desc->data[i].byte_count = |
217 | cpu_to_be32(priv->frag_info[i].frag_size); | |
218 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
219 | } | |
220 | ||
221 | /* If the number of used fragments does not fill up the ring stride, | |
222 | * remaining (unused) fragments must be padded with null address/size | |
223 | * and a special memory key */ | |
224 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
225 | for (i = priv->num_frags; i < possible_frags; i++) { | |
226 | rx_desc->data[i].byte_count = 0; | |
227 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
228 | rx_desc->data[i].addr = 0; | |
229 | } | |
230 | } | |
231 | ||
c27a02cd | 232 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
233 | struct mlx4_en_rx_ring *ring, int index, |
234 | gfp_t gfp) | |
c27a02cd YP |
235 | { |
236 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
237 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
238 | (index << priv->log_rx_info); | |
c27a02cd | 239 | |
51151a16 | 240 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
241 | } |
242 | ||
243 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) | |
244 | { | |
245 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
246 | } | |
247 | ||
38aab07c YP |
248 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
249 | struct mlx4_en_rx_ring *ring, | |
250 | int index) | |
251 | { | |
4cce66cd | 252 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
253 | int nr; |
254 | ||
4cce66cd | 255 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 256 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 257 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 258 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
259 | } |
260 | } | |
261 | ||
c27a02cd YP |
262 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
263 | { | |
c27a02cd YP |
264 | struct mlx4_en_rx_ring *ring; |
265 | int ring_ind; | |
266 | int buf_ind; | |
38aab07c | 267 | int new_size; |
c27a02cd YP |
268 | |
269 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
270 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 271 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
272 | |
273 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 | 274 | ring->actual_size, |
1ab25f86 | 275 | GFP_KERNEL | __GFP_COLD)) { |
c27a02cd | 276 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
1a91de28 | 277 | en_err(priv, "Failed to allocate enough rx buffers\n"); |
c27a02cd YP |
278 | return -ENOMEM; |
279 | } else { | |
38aab07c | 280 | new_size = rounddown_pow_of_two(ring->actual_size); |
1a91de28 | 281 | en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", |
453a6082 | 282 | ring->actual_size, new_size); |
38aab07c | 283 | goto reduce_rings; |
c27a02cd YP |
284 | } |
285 | } | |
286 | ring->actual_size++; | |
287 | ring->prod++; | |
288 | } | |
289 | } | |
38aab07c YP |
290 | return 0; |
291 | ||
292 | reduce_rings: | |
293 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 294 | ring = priv->rx_ring[ring_ind]; |
38aab07c YP |
295 | while (ring->actual_size > new_size) { |
296 | ring->actual_size--; | |
297 | ring->prod--; | |
298 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
299 | } | |
38aab07c YP |
300 | } |
301 | ||
c27a02cd YP |
302 | return 0; |
303 | } | |
304 | ||
c27a02cd YP |
305 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
306 | struct mlx4_en_rx_ring *ring) | |
307 | { | |
c27a02cd | 308 | int index; |
c27a02cd | 309 | |
453a6082 YP |
310 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
311 | ring->cons, ring->prod); | |
c27a02cd YP |
312 | |
313 | /* Unmap and free Rx buffers */ | |
38aab07c | 314 | BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); |
c27a02cd YP |
315 | while (ring->cons != ring->prod) { |
316 | index = ring->cons & ring->size_mask; | |
453a6082 | 317 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 318 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
319 | ++ring->cons; |
320 | } | |
321 | } | |
322 | ||
02512482 IS |
323 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) |
324 | { | |
325 | int i; | |
326 | int num_of_eqs; | |
bb2146bc | 327 | int num_rx_rings; |
02512482 IS |
328 | struct mlx4_dev *dev = mdev->dev; |
329 | ||
330 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
331 | if (!dev->caps.comp_pool) | |
332 | num_of_eqs = max_t(int, MIN_RX_RINGS, | |
333 | min_t(int, | |
334 | dev->caps.num_comp_vectors, | |
335 | DEF_RX_RINGS)); | |
336 | else | |
337 | num_of_eqs = min_t(int, MAX_MSIX_P_PORT, | |
338 | dev->caps.comp_pool/ | |
339 | dev->caps.num_ports) - 1; | |
340 | ||
ea1c1af1 AV |
341 | num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : |
342 | min_t(int, num_of_eqs, | |
343 | netif_get_num_default_rss_queues()); | |
02512482 | 344 | mdev->profile.prof[i].rx_ring_num = |
bb2146bc | 345 | rounddown_pow_of_two(num_rx_rings); |
02512482 IS |
346 | } |
347 | } | |
348 | ||
c27a02cd | 349 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 350 | struct mlx4_en_rx_ring **pring, |
163561a4 | 351 | u32 size, u16 stride, int node) |
c27a02cd YP |
352 | { |
353 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 354 | struct mlx4_en_rx_ring *ring; |
4cce66cd | 355 | int err = -ENOMEM; |
c27a02cd YP |
356 | int tmp; |
357 | ||
163561a4 | 358 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 359 | if (!ring) { |
163561a4 EE |
360 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
361 | if (!ring) { | |
362 | en_err(priv, "Failed to allocate RX ring structure\n"); | |
363 | return -ENOMEM; | |
364 | } | |
41d942d5 EE |
365 | } |
366 | ||
c27a02cd YP |
367 | ring->prod = 0; |
368 | ring->cons = 0; | |
369 | ring->size = size; | |
370 | ring->size_mask = size - 1; | |
371 | ring->stride = stride; | |
372 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 373 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
374 | |
375 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 376 | sizeof(struct mlx4_en_rx_alloc)); |
163561a4 | 377 | ring->rx_info = vmalloc_node(tmp, node); |
41d942d5 | 378 | if (!ring->rx_info) { |
163561a4 EE |
379 | ring->rx_info = vmalloc(tmp); |
380 | if (!ring->rx_info) { | |
381 | err = -ENOMEM; | |
382 | goto err_ring; | |
383 | } | |
41d942d5 | 384 | } |
e404decb | 385 | |
453a6082 | 386 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
387 | ring->rx_info, tmp); |
388 | ||
163561a4 EE |
389 | /* Allocate HW buffers on provided NUMA node */ |
390 | set_dev_node(&mdev->dev->pdev->dev, node); | |
c27a02cd YP |
391 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, |
392 | ring->buf_size, 2 * PAGE_SIZE); | |
163561a4 | 393 | set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 394 | if (err) |
41d942d5 | 395 | goto err_info; |
c27a02cd YP |
396 | |
397 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
398 | if (err) { | |
453a6082 | 399 | en_err(priv, "Failed to map RX buffer\n"); |
c27a02cd YP |
400 | goto err_hwq; |
401 | } | |
402 | ring->buf = ring->wqres.buf.direct.buf; | |
403 | ||
ec693d47 AV |
404 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
405 | ||
41d942d5 | 406 | *pring = ring; |
c27a02cd YP |
407 | return 0; |
408 | ||
c27a02cd YP |
409 | err_hwq: |
410 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
41d942d5 | 411 | err_info: |
c27a02cd YP |
412 | vfree(ring->rx_info); |
413 | ring->rx_info = NULL; | |
41d942d5 EE |
414 | err_ring: |
415 | kfree(ring); | |
416 | *pring = NULL; | |
417 | ||
c27a02cd YP |
418 | return err; |
419 | } | |
420 | ||
421 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
422 | { | |
c27a02cd YP |
423 | struct mlx4_en_rx_ring *ring; |
424 | int i; | |
425 | int ring_ind; | |
426 | int err; | |
427 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
428 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
429 | |
430 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 431 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
432 | |
433 | ring->prod = 0; | |
434 | ring->cons = 0; | |
435 | ring->actual_size = 0; | |
41d942d5 | 436 | ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
c27a02cd YP |
437 | |
438 | ring->stride = stride; | |
9f519f68 YP |
439 | if (ring->stride <= TXBB_SIZE) |
440 | ring->buf += TXBB_SIZE; | |
441 | ||
c27a02cd YP |
442 | ring->log_stride = ffs(ring->stride) - 1; |
443 | ring->buf_size = ring->size * ring->stride; | |
444 | ||
445 | memset(ring->buf, 0, ring->buf_size); | |
446 | mlx4_en_update_rx_prod_db(ring); | |
447 | ||
4cce66cd | 448 | /* Initialize all descriptors */ |
c27a02cd YP |
449 | for (i = 0; i < ring->size; i++) |
450 | mlx4_en_init_rx_desc(priv, ring, i); | |
451 | ||
452 | /* Initialize page allocators */ | |
453 | err = mlx4_en_init_allocator(priv, ring); | |
454 | if (err) { | |
453a6082 | 455 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
456 | if (ring->stride <= TXBB_SIZE) |
457 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
458 | ring_ind--; |
459 | goto err_allocator; | |
c27a02cd | 460 | } |
c27a02cd | 461 | } |
b58515be IM |
462 | err = mlx4_en_fill_rx_buffers(priv); |
463 | if (err) | |
c27a02cd YP |
464 | goto err_buffers; |
465 | ||
466 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 467 | ring = priv->rx_ring[ring_ind]; |
c27a02cd | 468 | |
00d7d7bc | 469 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 470 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
471 | } |
472 | ||
473 | return 0; | |
474 | ||
c27a02cd YP |
475 | err_buffers: |
476 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
41d942d5 | 477 | mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); |
c27a02cd YP |
478 | |
479 | ring_ind = priv->rx_ring_num - 1; | |
480 | err_allocator: | |
481 | while (ring_ind >= 0) { | |
41d942d5 EE |
482 | if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) |
483 | priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; | |
484 | mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); | |
c27a02cd YP |
485 | ring_ind--; |
486 | } | |
487 | return err; | |
488 | } | |
489 | ||
490 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, | |
41d942d5 EE |
491 | struct mlx4_en_rx_ring **pring, |
492 | u32 size, u16 stride) | |
c27a02cd YP |
493 | { |
494 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 495 | struct mlx4_en_rx_ring *ring = *pring; |
c27a02cd | 496 | |
c27a02cd | 497 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
68355f71 | 498 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
499 | vfree(ring->rx_info); |
500 | ring->rx_info = NULL; | |
41d942d5 EE |
501 | kfree(ring); |
502 | *pring = NULL; | |
1eb8c695 | 503 | #ifdef CONFIG_RFS_ACCEL |
41d942d5 | 504 | mlx4_en_cleanup_filters(priv); |
1eb8c695 | 505 | #endif |
c27a02cd YP |
506 | } |
507 | ||
508 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
509 | struct mlx4_en_rx_ring *ring) | |
510 | { | |
c27a02cd | 511 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
512 | if (ring->stride <= TXBB_SIZE) |
513 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
514 | mlx4_en_destroy_allocator(priv, ring); |
515 | } | |
516 | ||
517 | ||
c27a02cd YP |
518 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
519 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 520 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 521 | struct sk_buff *skb, |
c27a02cd YP |
522 | int length) |
523 | { | |
90278c9f | 524 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
525 | struct mlx4_en_frag_info *frag_info; |
526 | int nr; | |
527 | dma_addr_t dma; | |
528 | ||
4cce66cd | 529 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
530 | for (nr = 0; nr < priv->num_frags; nr++) { |
531 | frag_info = &priv->frag_info[nr]; | |
532 | if (length <= frag_info->frag_prefix_size) | |
533 | break; | |
4cce66cd TLSC |
534 | if (!frags[nr].page) |
535 | goto fail; | |
c27a02cd | 536 | |
c27a02cd | 537 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
538 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
539 | DMA_FROM_DEVICE); | |
c27a02cd | 540 | |
4cce66cd | 541 | /* Save page reference in skb */ |
4cce66cd TLSC |
542 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
543 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 544 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 545 | skb->truesize += frag_info->frag_stride; |
51151a16 | 546 | frags[nr].page = NULL; |
c27a02cd YP |
547 | } |
548 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 549 | if (nr > 0) |
9e903e08 ED |
550 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
551 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
552 | return nr; |
553 | ||
554 | fail: | |
c27a02cd YP |
555 | while (nr > 0) { |
556 | nr--; | |
311761c8 | 557 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
558 | } |
559 | return 0; | |
560 | } | |
561 | ||
562 | ||
563 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
564 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 565 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
566 | unsigned int length) |
567 | { | |
c27a02cd YP |
568 | struct sk_buff *skb; |
569 | void *va; | |
570 | int used_frags; | |
571 | dma_addr_t dma; | |
572 | ||
c056b734 | 573 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 574 | if (!skb) { |
453a6082 | 575 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
576 | return NULL; |
577 | } | |
c27a02cd YP |
578 | skb_reserve(skb, NET_IP_ALIGN); |
579 | skb->len = length; | |
c27a02cd YP |
580 | |
581 | /* Get pointer to first fragment so we could copy the headers into the | |
582 | * (linear part of the) skb */ | |
70fbe079 | 583 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
584 | |
585 | if (length <= SMALL_PACKET_SIZE) { | |
586 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 587 | * sync buffers for the copy */ |
c27a02cd | 588 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 589 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 590 | DMA_FROM_DEVICE); |
c27a02cd | 591 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
592 | skb->tail += length; |
593 | } else { | |
cfecec56 ED |
594 | unsigned int pull_len; |
595 | ||
c27a02cd | 596 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
597 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
598 | skb, length); | |
785a0982 YP |
599 | if (unlikely(!used_frags)) { |
600 | kfree_skb(skb); | |
601 | return NULL; | |
602 | } | |
c27a02cd YP |
603 | skb_shinfo(skb)->nr_frags = used_frags; |
604 | ||
cfecec56 | 605 | pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); |
c27a02cd | 606 | /* Copy headers into the skb linear buffer */ |
cfecec56 ED |
607 | memcpy(skb->data, va, pull_len); |
608 | skb->tail += pull_len; | |
c27a02cd YP |
609 | |
610 | /* Skip headers in first fragment */ | |
cfecec56 | 611 | skb_shinfo(skb)->frags[0].page_offset += pull_len; |
c27a02cd YP |
612 | |
613 | /* Adjust size of first fragment */ | |
cfecec56 ED |
614 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); |
615 | skb->data_len = length - pull_len; | |
c27a02cd YP |
616 | } |
617 | return skb; | |
618 | } | |
619 | ||
e7c1c2c4 YP |
620 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
621 | { | |
622 | int i; | |
623 | int offset = ETH_HLEN; | |
624 | ||
625 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
626 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
627 | goto out_loopback; | |
628 | } | |
629 | /* Loopback found */ | |
630 | priv->loopback_ok = 1; | |
631 | ||
632 | out_loopback: | |
633 | dev_kfree_skb_any(skb); | |
634 | } | |
c27a02cd | 635 | |
4cce66cd TLSC |
636 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
637 | struct mlx4_en_rx_ring *ring) | |
638 | { | |
639 | int index = ring->prod & ring->size_mask; | |
640 | ||
641 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
1ab25f86 IS |
642 | if (mlx4_en_prepare_rx_desc(priv, ring, index, |
643 | GFP_ATOMIC | __GFP_COLD)) | |
4cce66cd TLSC |
644 | break; |
645 | ring->prod++; | |
646 | index = ring->prod & ring->size_mask; | |
647 | } | |
648 | } | |
649 | ||
f8c6455b SM |
650 | /* When hardware doesn't strip the vlan, we need to calculate the checksum |
651 | * over it and add it to the hardware's checksum calculation | |
652 | */ | |
653 | static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, | |
654 | struct vlan_hdr *vlanh) | |
655 | { | |
656 | return csum_add(hw_checksum, *(__wsum *)vlanh); | |
657 | } | |
658 | ||
659 | /* Although the stack expects checksum which doesn't include the pseudo | |
660 | * header, the HW adds it. To address that, we are subtracting the pseudo | |
661 | * header checksum from the checksum value provided by the HW. | |
662 | */ | |
663 | static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, | |
664 | struct iphdr *iph) | |
665 | { | |
666 | __u16 length_for_csum = 0; | |
667 | __wsum csum_pseudo_header = 0; | |
668 | ||
669 | length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); | |
670 | csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, | |
671 | length_for_csum, iph->protocol, 0); | |
672 | skb->csum = csum_sub(hw_checksum, csum_pseudo_header); | |
673 | } | |
674 | ||
675 | #if IS_ENABLED(CONFIG_IPV6) | |
676 | /* In IPv6 packets, besides subtracting the pseudo header checksum, | |
677 | * we also compute/add the IP header checksum which | |
678 | * is not added by the HW. | |
679 | */ | |
680 | static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, | |
681 | struct ipv6hdr *ipv6h) | |
682 | { | |
683 | __wsum csum_pseudo_hdr = 0; | |
684 | ||
685 | if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS) | |
686 | return -1; | |
687 | hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8)); | |
688 | ||
689 | csum_pseudo_hdr = csum_partial(&ipv6h->saddr, | |
690 | sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); | |
691 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); | |
692 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); | |
693 | ||
694 | skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); | |
695 | skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); | |
696 | return 0; | |
697 | } | |
698 | #endif | |
699 | static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, | |
700 | int hwtstamp_rx_filter) | |
701 | { | |
702 | __wsum hw_checksum = 0; | |
703 | ||
704 | void *hdr = (u8 *)va + sizeof(struct ethhdr); | |
705 | ||
706 | hw_checksum = csum_unfold((__force __sum16)cqe->checksum); | |
707 | ||
708 | if (((struct ethhdr *)va)->h_proto == htons(ETH_P_8021Q) && | |
709 | hwtstamp_rx_filter != HWTSTAMP_FILTER_NONE) { | |
710 | /* next protocol non IPv4 or IPv6 */ | |
711 | if (((struct vlan_hdr *)hdr)->h_vlan_encapsulated_proto | |
712 | != htons(ETH_P_IP) && | |
713 | ((struct vlan_hdr *)hdr)->h_vlan_encapsulated_proto | |
714 | != htons(ETH_P_IPV6)) | |
715 | return -1; | |
716 | hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); | |
717 | hdr += sizeof(struct vlan_hdr); | |
718 | } | |
719 | ||
720 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) | |
721 | get_fixed_ipv4_csum(hw_checksum, skb, hdr); | |
722 | #if IS_ENABLED(CONFIG_IPV6) | |
723 | else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) | |
724 | if (get_fixed_ipv6_csum(hw_checksum, skb, hdr)) | |
725 | return -1; | |
726 | #endif | |
727 | return 0; | |
728 | } | |
729 | ||
c27a02cd YP |
730 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
731 | { | |
732 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 733 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd | 734 | struct mlx4_cqe *cqe; |
41d942d5 | 735 | struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; |
4cce66cd | 736 | struct mlx4_en_rx_alloc *frags; |
c27a02cd YP |
737 | struct mlx4_en_rx_desc *rx_desc; |
738 | struct sk_buff *skb; | |
739 | int index; | |
740 | int nr; | |
741 | unsigned int length; | |
742 | int polled = 0; | |
743 | int ip_summed; | |
08ff3235 | 744 | int factor = priv->cqe_factor; |
ec693d47 | 745 | u64 timestamp; |
837052d0 | 746 | bool l2_tunnel; |
c27a02cd YP |
747 | |
748 | if (!priv->port_up) | |
749 | return 0; | |
750 | ||
38be0a34 EB |
751 | if (budget <= 0) |
752 | return polled; | |
753 | ||
c27a02cd YP |
754 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx |
755 | * descriptor offset can be deduced from the CQE index instead of | |
756 | * reading 'cqe->index' */ | |
757 | index = cq->mcq.cons_index & ring->size_mask; | |
b1b6b4da | 758 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
c27a02cd YP |
759 | |
760 | /* Process all completed CQEs */ | |
761 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
762 | cq->mcq.cons_index & cq->size)) { | |
763 | ||
4cce66cd | 764 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
765 | rx_desc = ring->buf + (index << ring->log_stride); |
766 | ||
767 | /* | |
768 | * make sure we read the CQE after we read the ownership bit | |
769 | */ | |
770 | rmb(); | |
771 | ||
772 | /* Drop packet on bad receive or bad checksum */ | |
773 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
774 | MLX4_CQE_OPCODE_ERROR)) { | |
1a91de28 JP |
775 | en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", |
776 | ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, | |
777 | ((struct mlx4_err_cqe *)cqe)->syndrome); | |
c27a02cd YP |
778 | goto next; |
779 | } | |
780 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 781 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
782 | goto next; |
783 | } | |
784 | ||
79aeaccd YB |
785 | /* Check if we need to drop the packet if SRIOV is not enabled |
786 | * and not performing the selftest or flb disabled | |
787 | */ | |
788 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
789 | struct ethhdr *ethh; | |
790 | dma_addr_t dma; | |
79aeaccd YB |
791 | /* Get pointer to first fragment since we haven't |
792 | * skb yet and cast it to ethhdr struct | |
793 | */ | |
794 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
795 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
796 | DMA_FROM_DEVICE); | |
797 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 798 | frags[0].page_offset); |
79aeaccd | 799 | |
c07cb4b0 YB |
800 | if (is_multicast_ether_addr(ethh->h_dest)) { |
801 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
802 | struct hlist_head *bucket; |
803 | unsigned int mac_hash; | |
804 | ||
805 | /* Drop the packet, since HW loopback-ed it */ | |
806 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
807 | bucket = &priv->mac_hash[mac_hash]; | |
808 | rcu_read_lock(); | |
b67bfe0d | 809 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 YB |
810 | if (ether_addr_equal_64bits(entry->mac, |
811 | ethh->h_source)) { | |
812 | rcu_read_unlock(); | |
813 | goto next; | |
814 | } | |
815 | } | |
816 | rcu_read_unlock(); | |
817 | } | |
79aeaccd | 818 | } |
5b4c4d36 | 819 | |
c27a02cd YP |
820 | /* |
821 | * Packet is OK - process it. | |
822 | */ | |
823 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 824 | length -= ring->fcs_del; |
c27a02cd YP |
825 | ring->bytes += length; |
826 | ring->packets++; | |
837052d0 OG |
827 | l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && |
828 | (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); | |
c27a02cd | 829 | |
c8c64cff | 830 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
f8c6455b SM |
831 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | |
832 | MLX4_CQE_STATUS_UDP)) { | |
833 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && | |
834 | cqe->checksum == cpu_to_be16(0xffff)) { | |
835 | ip_summed = CHECKSUM_UNNECESSARY; | |
836 | ring->csum_ok++; | |
837 | } else { | |
838 | ip_summed = CHECKSUM_NONE; | |
839 | ring->csum_none++; | |
840 | } | |
c27a02cd | 841 | } else { |
f8c6455b SM |
842 | if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && |
843 | (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | | |
844 | MLX4_CQE_STATUS_IPV6))) { | |
845 | ip_summed = CHECKSUM_COMPLETE; | |
846 | ring->csum_complete++; | |
847 | } else { | |
848 | ip_summed = CHECKSUM_NONE; | |
849 | ring->csum_none++; | |
850 | } | |
c27a02cd YP |
851 | } |
852 | } else { | |
853 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 854 | ring->csum_none++; |
c27a02cd YP |
855 | } |
856 | ||
dd65beac SM |
857 | /* This packet is eligible for GRO if it is: |
858 | * - DIX Ethernet (type interpretation) | |
859 | * - TCP/IP (v4) | |
860 | * - without IP options | |
861 | * - not an IP fragment | |
862 | * - no LLS polling in progress | |
863 | */ | |
864 | if (!mlx4_en_cq_busy_polling(cq) && | |
865 | (dev->features & NETIF_F_GRO)) { | |
866 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); | |
867 | if (!gro_skb) | |
868 | goto next; | |
869 | ||
870 | nr = mlx4_en_complete_rx_desc(priv, | |
871 | rx_desc, frags, gro_skb, | |
872 | length); | |
873 | if (!nr) | |
874 | goto next; | |
875 | ||
f8c6455b SM |
876 | if (ip_summed == CHECKSUM_COMPLETE) { |
877 | void *va = skb_frag_address(skb_shinfo(gro_skb)->frags); | |
878 | if (check_csum(cqe, gro_skb, va, ring->hwtstamp_rx_filter)) { | |
879 | ip_summed = CHECKSUM_NONE; | |
880 | ring->csum_none++; | |
881 | ring->csum_complete--; | |
882 | } | |
883 | } | |
884 | ||
dd65beac SM |
885 | skb_shinfo(gro_skb)->nr_frags = nr; |
886 | gro_skb->len = length; | |
887 | gro_skb->data_len = length; | |
888 | gro_skb->ip_summed = ip_summed; | |
889 | ||
890 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) | |
c58942f2 OG |
891 | gro_skb->csum_level = 1; |
892 | ||
dd65beac SM |
893 | if ((cqe->vlan_my_qpn & |
894 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) && | |
895 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
896 | u16 vid = be16_to_cpu(cqe->sl_vid); | |
897 | ||
898 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); | |
899 | } | |
900 | ||
901 | if (dev->features & NETIF_F_RXHASH) | |
902 | skb_set_hash(gro_skb, | |
903 | be32_to_cpu(cqe->immed_rss_invalid), | |
904 | PKT_HASH_TYPE_L3); | |
905 | ||
906 | skb_record_rx_queue(gro_skb, cq->ring); | |
907 | skb_mark_napi_id(gro_skb, &cq->napi); | |
908 | ||
909 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { | |
910 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
911 | mlx4_en_fill_hwtstamps(mdev, | |
912 | skb_hwtstamps(gro_skb), | |
913 | timestamp); | |
914 | } | |
915 | ||
916 | napi_gro_frags(&cq->napi); | |
917 | goto next; | |
918 | } | |
919 | ||
920 | /* GRO not possible, complete processing here */ | |
4cce66cd | 921 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
c27a02cd YP |
922 | if (!skb) { |
923 | priv->stats.rx_dropped++; | |
924 | goto next; | |
925 | } | |
926 | ||
e7c1c2c4 YP |
927 | if (unlikely(priv->validate_loopback)) { |
928 | validate_loopback(priv, skb); | |
929 | goto next; | |
930 | } | |
931 | ||
f8c6455b SM |
932 | if (ip_summed == CHECKSUM_COMPLETE) { |
933 | if (check_csum(cqe, skb, skb->data, ring->hwtstamp_rx_filter)) { | |
934 | ip_summed = CHECKSUM_NONE; | |
935 | ring->csum_complete--; | |
936 | ring->csum_none++; | |
937 | } | |
938 | } | |
939 | ||
c27a02cd YP |
940 | skb->ip_summed = ip_summed; |
941 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 942 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 943 | |
9ca8600e TH |
944 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) |
945 | skb->csum_level = 1; | |
837052d0 | 946 | |
ad86107f | 947 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
948 | skb_set_hash(skb, |
949 | be32_to_cpu(cqe->immed_rss_invalid), | |
950 | PKT_HASH_TYPE_L3); | |
ad86107f | 951 | |
ec693d47 AV |
952 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
953 | MLX4_CQE_VLAN_PRESENT_MASK) && | |
954 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) | |
86a9bad3 | 955 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
f1b553fb | 956 | |
ec693d47 AV |
957 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
958 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
959 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
960 | timestamp); | |
961 | } | |
962 | ||
8b80cda5 | 963 | skb_mark_napi_id(skb, &cq->napi); |
9e77a2b8 | 964 | |
e6a76758 ED |
965 | if (!mlx4_en_cq_busy_polling(cq)) |
966 | napi_gro_receive(&cq->napi, skb); | |
967 | else | |
968 | netif_receive_skb(skb); | |
c27a02cd | 969 | |
c27a02cd | 970 | next: |
4cce66cd TLSC |
971 | for (nr = 0; nr < priv->num_frags; nr++) |
972 | mlx4_en_free_frag(priv, frags, nr); | |
973 | ||
c27a02cd YP |
974 | ++cq->mcq.cons_index; |
975 | index = (cq->mcq.cons_index) & ring->size_mask; | |
b1b6b4da | 976 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
f1d29a3f | 977 | if (++polled == budget) |
c27a02cd | 978 | goto out; |
c27a02cd YP |
979 | } |
980 | ||
c27a02cd YP |
981 | out: |
982 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
983 | mlx4_cq_set_ci(&cq->mcq); | |
984 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
985 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 986 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
987 | mlx4_en_update_rx_prod_db(ring); |
988 | return polled; | |
989 | } | |
990 | ||
991 | ||
992 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
993 | { | |
994 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
995 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
996 | ||
477b35b4 ED |
997 | if (likely(priv->port_up)) |
998 | napi_schedule_irqoff(&cq->napi); | |
c27a02cd YP |
999 | else |
1000 | mlx4_en_arm_cq(priv, cq); | |
1001 | } | |
1002 | ||
1003 | /* Rx CQ polling - called by NAPI */ | |
1004 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
1005 | { | |
1006 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
1007 | struct net_device *dev = cq->dev; | |
1008 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1009 | int done; | |
1010 | ||
9e77a2b8 AV |
1011 | if (!mlx4_en_cq_lock_napi(cq)) |
1012 | return budget; | |
1013 | ||
c27a02cd YP |
1014 | done = mlx4_en_process_rx_cq(dev, cq, budget); |
1015 | ||
9e77a2b8 AV |
1016 | mlx4_en_cq_unlock_napi(cq); |
1017 | ||
c27a02cd | 1018 | /* If we used up all the quota - we're probably not done yet... */ |
2eacc23c | 1019 | if (done == budget) { |
35f6f453 AV |
1020 | int cpu_curr; |
1021 | const struct cpumask *aff; | |
1022 | ||
c27a02cd | 1023 | INC_PERF_COUNTER(priv->pstats.napi_quota); |
35f6f453 AV |
1024 | |
1025 | cpu_curr = smp_processor_id(); | |
1026 | aff = irq_desc_get_irq_data(cq->irq_desc)->affinity; | |
1027 | ||
2e1af7d7 ED |
1028 | if (likely(cpumask_test_cpu(cpu_curr, aff))) |
1029 | return budget; | |
1030 | ||
1031 | /* Current cpu is not according to smp_irq_affinity - | |
1032 | * probably affinity changed. need to stop this NAPI | |
1033 | * poll, and restart it on the right CPU | |
1034 | */ | |
1035 | done = 0; | |
c27a02cd | 1036 | } |
1a288172 ED |
1037 | /* Done for now */ |
1038 | napi_complete_done(napi, done); | |
1039 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
1040 | return done; |
1041 | } | |
1042 | ||
51151a16 | 1043 | static const int frag_sizes[] = { |
c27a02cd YP |
1044 | FRAG_SZ0, |
1045 | FRAG_SZ1, | |
1046 | FRAG_SZ2, | |
1047 | FRAG_SZ3 | |
1048 | }; | |
1049 | ||
1050 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
1051 | { | |
1052 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
d5b8dff0 | 1053 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN; |
c27a02cd YP |
1054 | int buf_size = 0; |
1055 | int i = 0; | |
1056 | ||
1057 | while (buf_size < eff_mtu) { | |
1058 | priv->frag_info[i].frag_size = | |
1059 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
1060 | frag_sizes[i] : eff_mtu - buf_size; | |
1061 | priv->frag_info[i].frag_prefix_size = buf_size; | |
5f6e9800 IS |
1062 | priv->frag_info[i].frag_stride = ALIGN(frag_sizes[i], |
1063 | SMP_CACHE_BYTES); | |
c27a02cd YP |
1064 | buf_size += priv->frag_info[i].frag_size; |
1065 | i++; | |
1066 | } | |
1067 | ||
1068 | priv->num_frags = i; | |
1069 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 1070 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 1071 | |
1a91de28 JP |
1072 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", |
1073 | eff_mtu, priv->num_frags); | |
c27a02cd | 1074 | for (i = 0; i < priv->num_frags; i++) { |
51151a16 | 1075 | en_err(priv, |
5f6e9800 | 1076 | " frag:%d - size:%d prefix:%d stride:%d\n", |
51151a16 ED |
1077 | i, |
1078 | priv->frag_info[i].frag_size, | |
1079 | priv->frag_info[i].frag_prefix_size, | |
51151a16 | 1080 | priv->frag_info[i].frag_stride); |
c27a02cd YP |
1081 | } |
1082 | } | |
1083 | ||
1084 | /* RSS related functions */ | |
1085 | ||
9f519f68 YP |
1086 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
1087 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
1088 | enum mlx4_qp_state *state, |
1089 | struct mlx4_qp *qp) | |
1090 | { | |
1091 | struct mlx4_en_dev *mdev = priv->mdev; | |
1092 | struct mlx4_qp_context *context; | |
1093 | int err = 0; | |
1094 | ||
14f8dc49 JP |
1095 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
1096 | if (!context) | |
c27a02cd | 1097 | return -ENOMEM; |
c27a02cd | 1098 | |
40f2287b | 1099 | err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); |
c27a02cd | 1100 | if (err) { |
453a6082 | 1101 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 1102 | goto out; |
c27a02cd YP |
1103 | } |
1104 | qp->event = mlx4_en_sqp_event; | |
1105 | ||
1106 | memset(context, 0, sizeof *context); | |
00d7d7bc | 1107 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 1108 | qpn, ring->cqn, -1, context); |
9f519f68 | 1109 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 1110 | |
f3a9d1f2 | 1111 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 1112 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 1113 | context->param3 |= cpu_to_be32(1 << 29); |
4a5f4dd8 YP |
1114 | ring->fcs_del = ETH_FCS_LEN; |
1115 | } else | |
1116 | ring->fcs_del = 0; | |
f3a9d1f2 | 1117 | |
9f519f68 | 1118 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
1119 | if (err) { |
1120 | mlx4_qp_remove(mdev->dev, qp); | |
1121 | mlx4_qp_free(mdev->dev, qp); | |
1122 | } | |
9f519f68 | 1123 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
1124 | out: |
1125 | kfree(context); | |
1126 | return err; | |
1127 | } | |
1128 | ||
cabdc8ee HHZ |
1129 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
1130 | { | |
1131 | int err; | |
1132 | u32 qpn; | |
1133 | ||
d57febe1 MB |
1134 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, |
1135 | MLX4_RESERVE_A0_QP); | |
cabdc8ee HHZ |
1136 | if (err) { |
1137 | en_err(priv, "Failed reserving drop qpn\n"); | |
1138 | return err; | |
1139 | } | |
40f2287b | 1140 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); |
cabdc8ee HHZ |
1141 | if (err) { |
1142 | en_err(priv, "Failed allocating drop qp\n"); | |
1143 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1144 | return err; | |
1145 | } | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
1151 | { | |
1152 | u32 qpn; | |
1153 | ||
1154 | qpn = priv->drop_qp.qpn; | |
1155 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
1156 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
1157 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1158 | } | |
1159 | ||
c27a02cd YP |
1160 | /* Allocate rx qp's and configure them according to rss map */ |
1161 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
1162 | { | |
1163 | struct mlx4_en_dev *mdev = priv->mdev; | |
1164 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1165 | struct mlx4_qp_context context; | |
876f6e67 | 1166 | struct mlx4_rss_context *rss_context; |
93d3e367 | 1167 | int rss_rings; |
c27a02cd | 1168 | void *ptr; |
876f6e67 | 1169 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 1170 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 1171 | int i, qpn; |
c27a02cd YP |
1172 | int err = 0; |
1173 | int good_qps = 0; | |
1174 | ||
453a6082 | 1175 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
1176 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
1177 | priv->rx_ring_num, | |
ddae0349 | 1178 | &rss_map->base_qpn, 0); |
c27a02cd | 1179 | if (err) { |
b6b912e0 | 1180 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
1181 | return err; |
1182 | } | |
1183 | ||
b6b912e0 | 1184 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 1185 | qpn = rss_map->base_qpn + i; |
41d942d5 | 1186 | err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], |
c27a02cd YP |
1187 | &rss_map->state[i], |
1188 | &rss_map->qps[i]); | |
1189 | if (err) | |
1190 | goto rss_err; | |
1191 | ||
1192 | ++good_qps; | |
1193 | } | |
1194 | ||
1195 | /* Configure RSS indirection qp */ | |
40f2287b | 1196 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); |
c27a02cd | 1197 | if (err) { |
453a6082 | 1198 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1199 | goto rss_err; |
c27a02cd YP |
1200 | } |
1201 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1202 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
41d942d5 | 1203 | priv->rx_ring[0]->cqn, -1, &context); |
c27a02cd | 1204 | |
93d3e367 YP |
1205 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1206 | rss_rings = priv->rx_ring_num; | |
1207 | else | |
1208 | rss_rings = priv->prof->rss_rings; | |
1209 | ||
876f6e67 OG |
1210 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1211 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1212 | rss_context = ptr; |
93d3e367 | 1213 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1214 | (rss_map->base_qpn)); |
89efea25 | 1215 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1216 | if (priv->mdev->profile.udp_rss) { |
1217 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1218 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1219 | } | |
837052d0 OG |
1220 | |
1221 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { | |
1222 | en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); | |
1223 | rss_mask |= MLX4_RSS_BY_INNER_HEADERS; | |
1224 | } | |
1225 | ||
0533943c | 1226 | rss_context->flags = rss_mask; |
876f6e67 | 1227 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
947cbb0a EP |
1228 | if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { |
1229 | rss_context->hash_fn = MLX4_RSS_HASH_XOR; | |
1230 | } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { | |
1231 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; | |
1232 | memcpy(rss_context->rss_key, priv->rss_key, | |
1233 | MLX4_EN_RSS_KEY_SIZE); | |
1234 | netdev_rss_key_fill(rss_context->rss_key, | |
1235 | MLX4_EN_RSS_KEY_SIZE); | |
1236 | } else { | |
1237 | en_err(priv, "Unknown RSS hash function requested\n"); | |
1238 | err = -EINVAL; | |
1239 | goto indir_err; | |
1240 | } | |
c27a02cd YP |
1241 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, |
1242 | &rss_map->indir_qp, &rss_map->indir_state); | |
1243 | if (err) | |
1244 | goto indir_err; | |
1245 | ||
1246 | return 0; | |
1247 | ||
1248 | indir_err: | |
1249 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1250 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1251 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1252 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1253 | rss_err: |
1254 | for (i = 0; i < good_qps; i++) { | |
1255 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1256 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1257 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1258 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1259 | } | |
b6b912e0 | 1260 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1261 | return err; |
1262 | } | |
1263 | ||
1264 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1265 | { | |
1266 | struct mlx4_en_dev *mdev = priv->mdev; | |
1267 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1268 | int i; | |
1269 | ||
1270 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1271 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1272 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1273 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1274 | |
b6b912e0 | 1275 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1276 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1277 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1278 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1279 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1280 | } | |
b6b912e0 | 1281 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1282 | } |