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net/mlx5e: Reduce number of heap allocated buffers for update stats
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
b3f63c3d 42#include "vxlan.h"
f62b8bb8
AV		 43
44struct mlx5e_rq_param {
cb3c7fd4
GR		 45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
9908aa29 58 u8 cq_period_mode;
f62b8bb8
AV		 59};
60
61struct mlx5e_channel_param {
62 struct mlx5e_rq_param rq;
63 struct mlx5e_sq_param sq;
b5503b99 64 struct mlx5e_sq_param xdp_sq;
d3c9bc27 65 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
d3c9bc27 68 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 69};
70
2fc4bfb7
SM		 71static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
72{
73 return MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
76}
77
6a9764ef
SM		 78void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
79 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 80{
6a9764ef
SM		 81 params->rq_wq_type = rq_type;
82 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
83 switch (params->rq_wq_type) {
2fc4bfb7 84 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 85 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 86 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
87 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 88 params->mpwqe_log_stride_sz =
89 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
90 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
91 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
92 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
93 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 94 break;
95 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 96 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 97 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
98 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
4078e637
TT		 99
100 /* Extra room needed for build_skb */
6a9764ef 101 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
4078e637 102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 103 }
2fc4bfb7 104
6a9764ef
SM		 105 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(params->log_rq_size),
108 BIT(params->mpwqe_log_stride_sz),
109 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 110}
111
6a9764ef 112static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 113{
6a9764ef
SM		 114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
115 !params->xdp_prog ?
2fc4bfb7
SM		 116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 118 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 119}
120
f62b8bb8
AV		 121static void mlx5e_update_carrier(struct mlx5e_priv *priv)
122{
123 struct mlx5_core_dev *mdev = priv->mdev;
124 u8 port_state;
125
126 port_state = mlx5_query_vport_state(mdev,
e53eef63
OG		 127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
128 0);
f62b8bb8 129
87424ad5
SD		 130 if (port_state == VPORT_STATE_UP) {
131 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 132 netif_carrier_on(priv->netdev);
87424ad5
SD		 133 } else {
134 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 135 netif_carrier_off(priv->netdev);
87424ad5 136 }
f62b8bb8
AV		 137}
138
139static void mlx5e_update_carrier_work(struct work_struct *work)
140{
141 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
142 update_carrier_work);
143
144 mutex_lock(&priv->state_lock);
145 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
146 mlx5e_update_carrier(priv);
147 mutex_unlock(&priv->state_lock);
148}
149
3947ca18
DJ		 150static void mlx5e_tx_timeout_work(struct work_struct *work)
151{
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 tx_timeout_work);
154 int err;
155
156 rtnl_lock();
157 mutex_lock(&priv->state_lock);
158 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
159 goto unlock;
160 mlx5e_close_locked(priv->netdev);
161 err = mlx5e_open_locked(priv->netdev);
162 if (err)
163 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
164 err);
165unlock:
166 mutex_unlock(&priv->state_lock);
167 rtnl_unlock();
168}
169
9218b44d 170static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 171{
1510d728 172 struct mlx5e_sw_stats temp, *s = &temp;
f62b8bb8
AV		 173 struct mlx5e_rq_stats *rq_stats;
174 struct mlx5e_sq_stats *sq_stats;
9218b44d 175 u64 tx_offload_none = 0;
f62b8bb8
AV		 176 int i, j;
177
9218b44d 178 memset(s, 0, sizeof(*s));
ff9c852f
SM		 179 for (i = 0; i < priv->channels.num; i++) {
180 struct mlx5e_channel *c = priv->channels.c[i];
181
182 rq_stats = &c->rq.stats;
f62b8bb8 183
faf4478b
GP		 184 s->rx_packets += rq_stats->packets;
185 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 186 s->rx_lro_packets += rq_stats->lro_packets;
187 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 188 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 189 s->rx_csum_complete += rq_stats->csum_complete;
190 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 191 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 192 s->rx_xdp_tx += rq_stats->xdp_tx;
193 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 194 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 195 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 196 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 197 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
198 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 199 s->rx_cache_reuse += rq_stats->cache_reuse;
200 s->rx_cache_full += rq_stats->cache_full;
201 s->rx_cache_empty += rq_stats->cache_empty;
202 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 203
6a9764ef 204 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 205 sq_stats = &c->sq[j].stats;
f62b8bb8 206
faf4478b
GP		 207 s->tx_packets += sq_stats->packets;
208 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 209 s->tx_tso_packets += sq_stats->tso_packets;
210 s->tx_tso_bytes += sq_stats->tso_bytes;
211 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
212 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 213 s->tx_queue_stopped += sq_stats->stopped;
214 s->tx_queue_wake += sq_stats->wake;
215 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 216 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 217 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
218 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 219 }
220 }
221
9218b44d 222 /* Update calculated offload counters */
bfe6d8d1
GP		 223 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
224 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 225
bfe6d8d1 226 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 227 priv->stats.pport.phy_counters,
228 counter_set.phys_layer_cntrs.link_down_events);
1510d728 229 memcpy(&priv->stats.sw, s, sizeof(*s));
9218b44d
GP		 230}
231
232static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
233{
234 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
235 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 236 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 237 struct mlx5_core_dev *mdev = priv->mdev;
238
f62b8bb8
AV		 239 MLX5_SET(query_vport_counter_in, in, opcode,
240 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
241 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
242 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
243
9218b44d
GP		 244 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
245}
246
247static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
248{
249 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
250 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 251 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
9218b44d 252 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 253 int prio;
9218b44d 254 void *out;
f62b8bb8 255
9218b44d 256 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 257
9218b44d
GP		 258 out = pstats->IEEE_802_3_counters;
259 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
260 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 261
9218b44d
GP		 262 out = pstats->RFC_2863_counters;
263 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
264 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
265
266 out = pstats->RFC_2819_counters;
267 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
268 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 269
121fcdc8
GP		 270 out = pstats->phy_counters;
271 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
272 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
273
5db0a4f6
GP		 274 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
275 out = pstats->phy_statistical_counters;
276 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
277 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
278 }
279
cf678570
GP		 280 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
281 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
282 out = pstats->per_prio_counters[prio];
283 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
284 mlx5_core_access_reg(mdev, in, sz, out, sz,
285 MLX5_REG_PPCNT, 0, 0);
286 }
9218b44d
GP		 287}
288
289static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
290{
291 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
292
293 if (!priv->q_counter)
294 return;
295
296 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
297 &qcnt->rx_out_of_buffer);
298}
299
0f7f3481
GP		 300static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
301{
302 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
303 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 304 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
0f7f3481
GP		 305 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
306 void *out;
0f7f3481
GP		 307
308 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
309 return;
310
0f7f3481
GP		 311 out = pcie_stats->pcie_perf_counters;
312 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
313 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
0f7f3481
GP		 314}
315
9218b44d
GP		 316void mlx5e_update_stats(struct mlx5e_priv *priv)
317{
3dd69e3d 318 mlx5e_update_pcie_counters(priv);
9218b44d 319 mlx5e_update_pport_counters(priv);
3dd69e3d
SM		 320 mlx5e_update_vport_counters(priv);
321 mlx5e_update_q_counter(priv);
121fcdc8 322 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 323}
324
cb67b832 325void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 326{
327 struct delayed_work *dwork = to_delayed_work(work);
328 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
329 update_stats_work);
330 mutex_lock(&priv->state_lock);
331 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 332 priv->profile->update_stats(priv);
7bb29755
MF		 333 queue_delayed_work(priv->wq, dwork,
334 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 335 }
336 mutex_unlock(&priv->state_lock);
337}
338
daa21560
TT		 339static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
340 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 341{
daa21560 342 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 343 struct ptp_clock_event ptp_event;
344 struct mlx5_eqe *eqe = NULL;
daa21560 345
e0f46eb9 346 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 347 return;
348
f62b8bb8
AV		 349 switch (event) {
350 case MLX5_DEV_EVENT_PORT_UP:
351 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 352 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 353 break;
ee7f1220
EE		 354 case MLX5_DEV_EVENT_PPS:
355 eqe = (struct mlx5_eqe *)param;
356 ptp_event.type = PTP_CLOCK_EXTTS;
357 ptp_event.index = eqe->data.pps.pin;
358 ptp_event.timestamp =
359 timecounter_cyc2time(&priv->tstamp.clock,
360 be64_to_cpu(eqe->data.pps.time_stamp));
361 mlx5e_pps_event_handler(vpriv, &ptp_event);
362 break;
f62b8bb8
AV		 363 default:
364 break;
365 }
366}
367
f62b8bb8
AV		 368static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
369{
e0f46eb9 370 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 371}
372
373static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
374{
e0f46eb9 375 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 376 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 377}
378
7e426671
TT		 379static inline int mlx5e_get_wqe_mtt_sz(void)
380{
381 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
382 * To avoid copying garbage after the mtt array, we allocate
383 * a little more.
384 */
385 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
386 MLX5_UMR_MTT_ALIGNMENT);
387}
388
31391048
SM		 389static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
390 struct mlx5e_icosq *sq,
391 struct mlx5e_umr_wqe *wqe,
392 u16 ix)
7e426671
TT		 393{
394 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
395 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
396 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 397 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 398 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
399 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
400
401 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
402 ds_cnt);
403 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
404 cseg->imm = rq->mkey_be;
405
406 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 407 ucseg->xlt_octowords =
7e426671
TT		 408 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
409 ucseg->bsf_octowords =
410 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
411 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
412
413 dseg->lkey = sq->mkey_be;
414 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
415}
416
417static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
418 struct mlx5e_channel *c)
419{
420 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
421 int mtt_sz = mlx5e_get_wqe_mtt_sz();
422 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
423 int i;
424
21c59685
SM		 425 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
426 GFP_KERNEL, cpu_to_node(c->cpu));
427 if (!rq->mpwqe.info)
7e426671
TT		 428 goto err_out;
429
430 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 431 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 432 cpu_to_node(c->cpu));
21c59685 433 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 434 goto err_free_wqe_info;
435
436 for (i = 0; i < wq_sz; i++) {
21c59685 437 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 438
21c59685 439 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 440 MLX5_UMR_ALIGN);
441 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
442 PCI_DMA_TODEVICE);
443 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
444 goto err_unmap_mtts;
445
446 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
447 }
448
449 return 0;
450
451err_unmap_mtts:
452 while (--i >= 0) {
21c59685 453 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 454
455 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
456 PCI_DMA_TODEVICE);
457 }
21c59685 458 kfree(rq->mpwqe.mtt_no_align);
7e426671 459err_free_wqe_info:
21c59685 460 kfree(rq->mpwqe.info);
7e426671
TT		 461
462err_out:
463 return -ENOMEM;
464}
465
466static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
467{
468 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
469 int mtt_sz = mlx5e_get_wqe_mtt_sz();
470 int i;
471
472 for (i = 0; i < wq_sz; i++) {
21c59685 473 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 474
475 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
476 PCI_DMA_TODEVICE);
477 }
21c59685
SM		 478 kfree(rq->mpwqe.mtt_no_align);
479 kfree(rq->mpwqe.info);
7e426671
TT		 480}
481
a43b25da 482static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 483 u64 npages, u8 page_shift,
484 struct mlx5_core_mkey *umr_mkey)
3608ae77 485{
3608ae77
TT		 486 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
487 void *mkc;
488 u32 *in;
489 int err;
490
ec8b9981
TT		 491 if (!MLX5E_VALID_NUM_MTTS(npages))
492 return -EINVAL;
493
1b9a07ee 494 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 495 if (!in)
496 return -ENOMEM;
497
498 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
499
3608ae77
TT		 500 MLX5_SET(mkc, mkc, free, 1);
501 MLX5_SET(mkc, mkc, umr_en, 1);
502 MLX5_SET(mkc, mkc, lw, 1);
503 MLX5_SET(mkc, mkc, lr, 1);
504 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
505
506 MLX5_SET(mkc, mkc, qpn, 0xffffff);
507 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 508 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 509 MLX5_SET(mkc, mkc, translations_octword_size,
510 MLX5_MTT_OCTW(npages));
ec8b9981 511 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 512
ec8b9981 513 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 514
515 kvfree(in);
516 return err;
517}
518
a43b25da 519static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 520{
6a9764ef 521 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 522
a43b25da 523 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 524}
525
3b77235b 526static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 527 struct mlx5e_params *params,
528 struct mlx5e_rq_param *rqp,
3b77235b 529 struct mlx5e_rq *rq)
f62b8bb8 530{
a43b25da 531 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 532 void *rqc = rqp->rqc;
f62b8bb8 533 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 534 u32 byte_count;
1bfecfca
SM		 535 u32 frag_sz;
536 int npages;
f62b8bb8
AV		 537 int wq_sz;
538 int err;
539 int i;
540
6a9764ef 541 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 542
6a9764ef 543 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 544 &rq->wq_ctrl);
545 if (err)
546 return err;
547
548 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
549
550 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 551
6a9764ef 552 rq->wq_type = params->rq_wq_type;
7e426671
TT		 553 rq->pdev = c->pdev;
554 rq->netdev = c->netdev;
a43b25da 555 rq->tstamp = c->tstamp;
7e426671
TT		 556 rq->channel = c;
557 rq->ix = c->ix;
a43b25da 558 rq->mdev = mdev;
97bc402d 559
6a9764ef 560 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 561 if (IS_ERR(rq->xdp_prog)) {
562 err = PTR_ERR(rq->xdp_prog);
563 rq->xdp_prog = NULL;
564 goto err_rq_wq_destroy;
565 }
7e426671 566
d8bec2b2 567 if (rq->xdp_prog) {
b5503b99 568 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 569 rq->rx_headroom = XDP_PACKET_HEADROOM;
570 } else {
571 rq->buff.map_dir = DMA_FROM_DEVICE;
572 rq->rx_headroom = MLX5_RX_HEADROOM;
573 }
b5503b99 574
6a9764ef 575 switch (rq->wq_type) {
461017cb 576 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 577
461017cb 578 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 579 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 580
20fd0c19
SM		 581 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
582 if (!rq->handle_rx_cqe) {
583 err = -EINVAL;
584 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
585 goto err_rq_wq_destroy;
586 }
587
6a9764ef
SM		 588 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
589 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca
SM		 590
591 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
592 byte_count = rq->buff.wqe_sz;
ec8b9981 593
a43b25da 594 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 595 if (err)
596 goto err_rq_wq_destroy;
ec8b9981
TT		 597 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
598
599 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
600 if (err)
601 goto err_destroy_umr_mkey;
461017cb
TT		 602 break;
603 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 604 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
605 GFP_KERNEL, cpu_to_node(c->cpu));
606 if (!rq->dma_info) {
461017cb
TT		 607 err = -ENOMEM;
608 goto err_rq_wq_destroy;
609 }
461017cb 610 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 611 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 612
20fd0c19
SM		 613 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
614 if (!rq->handle_rx_cqe) {
615 kfree(rq->dma_info);
616 err = -EINVAL;
617 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
618 goto err_rq_wq_destroy;
619 }
620
6a9764ef
SM		 621 rq->buff.wqe_sz = params->lro_en ?
622 params->lro_wqe_sz :
a43b25da 623 MLX5E_SW2HW_MTU(c->netdev->mtu);
1bfecfca
SM		 624 byte_count = rq->buff.wqe_sz;
625
626 /* calc the required page order */
d8bec2b2 627 frag_sz = rq->rx_headroom +
1bfecfca
SM		 628 byte_count /* packet data */ +
629 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
630 frag_sz = SKB_DATA_ALIGN(frag_sz);
631
632 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
633 rq->buff.page_order = order_base_2(npages);
634
461017cb 635 byte_count |= MLX5_HW_START_PADDING;
7e426671 636 rq->mkey_be = c->mkey_be;
461017cb 637 }
f62b8bb8
AV		 638
639 for (i = 0; i < wq_sz; i++) {
640 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
641
461017cb 642 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 643 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 644 }
645
cb3c7fd4 646 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
6a9764ef 647 rq->am.mode = params->rx_cq_period_mode;
4415a031
TT		 648 rq->page_cache.head = 0;
649 rq->page_cache.tail = 0;
650
f62b8bb8
AV		 651 return 0;
652
ec8b9981
TT		 653err_destroy_umr_mkey:
654 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
655
f62b8bb8 656err_rq_wq_destroy:
97bc402d
DB		 657 if (rq->xdp_prog)
658 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 659 mlx5_wq_destroy(&rq->wq_ctrl);
660
661 return err;
662}
663
3b77235b 664static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 665{
4415a031
TT		 666 int i;
667
86994156
RS		 668 if (rq->xdp_prog)
669 bpf_prog_put(rq->xdp_prog);
670
461017cb
TT		 671 switch (rq->wq_type) {
672 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 673 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 674 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 675 break;
676 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 677 kfree(rq->dma_info);
461017cb
TT		 678 }
679
4415a031
TT		 680 for (i = rq->page_cache.head; i != rq->page_cache.tail;
681 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
682 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
683
684 mlx5e_page_release(rq, dma_info, false);
685 }
f62b8bb8
AV		 686 mlx5_wq_destroy(&rq->wq_ctrl);
687}
688
6a9764ef
SM		 689static int mlx5e_create_rq(struct mlx5e_rq *rq,
690 struct mlx5e_rq_param *param)
f62b8bb8 691{
a43b25da 692 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 693
694 void *in;
695 void *rqc;
696 void *wq;
697 int inlen;
698 int err;
699
700 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
701 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 702 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 703 if (!in)
704 return -ENOMEM;
705
706 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
707 wq = MLX5_ADDR_OF(rqc, rqc, wq);
708
709 memcpy(rqc, param->rqc, sizeof(param->rqc));
710
97de9f31 711 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 712 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 713 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 714 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 715 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
716
717 mlx5_fill_page_array(&rq->wq_ctrl.buf,
718 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
719
7db22ffb 720 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 721
722 kvfree(in);
723
724 return err;
725}
726
36350114
GP		 727static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
728 int next_state)
f62b8bb8
AV		 729{
730 struct mlx5e_channel *c = rq->channel;
a43b25da 731 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 732
733 void *in;
734 void *rqc;
735 int inlen;
736 int err;
737
738 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 739 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 740 if (!in)
741 return -ENOMEM;
742
743 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
744
745 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
746 MLX5_SET(rqc, rqc, state, next_state);
747
7db22ffb 748 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 749
750 kvfree(in);
751
752 return err;
753}
754
102722fc
GE		 755static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
756{
757 struct mlx5e_channel *c = rq->channel;
758 struct mlx5e_priv *priv = c->priv;
759 struct mlx5_core_dev *mdev = priv->mdev;
760
761 void *in;
762 void *rqc;
763 int inlen;
764 int err;
765
766 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 767 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 768 if (!in)
769 return -ENOMEM;
770
771 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
772
773 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
774 MLX5_SET64(modify_rq_in, in, modify_bitmask,
775 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
776 MLX5_SET(rqc, rqc, scatter_fcs, enable);
777 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
778
779 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
780
781 kvfree(in);
782
783 return err;
784}
785
36350114
GP		 786static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
787{
788 struct mlx5e_channel *c = rq->channel;
a43b25da 789 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 790 void *in;
791 void *rqc;
792 int inlen;
793 int err;
794
795 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 796 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 797 if (!in)
798 return -ENOMEM;
799
800 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
801
802 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 803 MLX5_SET64(modify_rq_in, in, modify_bitmask,
804 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 805 MLX5_SET(rqc, rqc, vsd, vsd);
806 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
807
808 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
809
810 kvfree(in);
811
812 return err;
813}
814
3b77235b 815static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 816{
a43b25da 817 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 818}
819
820static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
821{
01c196a2 822 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 823 struct mlx5e_channel *c = rq->channel;
a43b25da 824
f62b8bb8 825 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 826 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 827
01c196a2 828 while (time_before(jiffies, exp_time)) {
6a9764ef 829 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 830 return 0;
831
832 msleep(20);
833 }
834
a43b25da 835 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 836 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 837 return -ETIMEDOUT;
838}
839
f2fde18c
SM		 840static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
841{
842 struct mlx5_wq_ll *wq = &rq->wq;
843 struct mlx5e_rx_wqe *wqe;
844 __be16 wqe_ix_be;
845 u16 wqe_ix;
846
8484f9ed
SM		 847 /* UMR WQE (if in progress) is always at wq->head */
848 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 849 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 850
f2fde18c
SM		 851 while (!mlx5_wq_ll_is_empty(wq)) {
852 wqe_ix_be = *wq->tail_next;
853 wqe_ix = be16_to_cpu(wqe_ix_be);
854 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
855 rq->dealloc_wqe(rq, wqe_ix);
856 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
857 &wqe->next.next_wqe_index);
858 }
859}
860
f62b8bb8 861static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 862 struct mlx5e_params *params,
f62b8bb8
AV		 863 struct mlx5e_rq_param *param,
864 struct mlx5e_rq *rq)
865{
866 int err;
867
6a9764ef 868 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 869 if (err)
870 return err;
871
3b77235b 872 err = mlx5e_create_rq(rq, param);
f62b8bb8 873 if (err)
3b77235b 874 goto err_free_rq;
f62b8bb8 875
36350114 876 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 877 if (err)
3b77235b 878 goto err_destroy_rq;
f62b8bb8 879
6a9764ef 880 if (params->rx_am_enabled)
cb3c7fd4
GR		 881 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
882
f62b8bb8
AV		 883 return 0;
884
f62b8bb8
AV		 885err_destroy_rq:
886 mlx5e_destroy_rq(rq);
3b77235b
SM		 887err_free_rq:
888 mlx5e_free_rq(rq);
f62b8bb8
AV		 889
890 return err;
891}
892
acc6c595
SM		 893static void mlx5e_activate_rq(struct mlx5e_rq *rq)
894{
895 struct mlx5e_icosq *sq = &rq->channel->icosq;
896 u16 pi = sq->pc & sq->wq.sz_m1;
897 struct mlx5e_tx_wqe *nopwqe;
898
899 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
900 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
901 sq->db.ico_wqe[pi].num_wqebbs = 1;
902 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
903 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
904}
905
906static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 907{
c0f1147d 908 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 909 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 910}
cb3c7fd4 911
acc6c595
SM		 912static void mlx5e_close_rq(struct mlx5e_rq *rq)
913{
914 cancel_work_sync(&rq->am.work);
f62b8bb8 915 mlx5e_destroy_rq(rq);
3b77235b
SM		 916 mlx5e_free_rx_descs(rq);
917 mlx5e_free_rq(rq);
f62b8bb8
AV		 918}
919
31391048 920static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 921{
31391048 922 kfree(sq->db.di);
b5503b99
SM		 923}
924
31391048 925static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 926{
927 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
928
31391048 929 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 930 GFP_KERNEL, numa);
31391048
SM		 931 if (!sq->db.di) {
932 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 933 return -ENOMEM;
934 }
935
936 return 0;
937}
938
31391048 939static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 940 struct mlx5e_params *params,
31391048
SM		 941 struct mlx5e_sq_param *param,
942 struct mlx5e_xdpsq *sq)
943{
944 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 945 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 946 int err;
947
948 sq->pdev = c->pdev;
949 sq->mkey_be = c->mkey_be;
950 sq->channel = c;
951 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 952 sq->min_inline_mode = params->tx_min_inline_mode;
31391048
SM		 953
954 param->wq.db_numa_node = cpu_to_node(c->cpu);
955 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
956 if (err)
957 return err;
958 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
959
960 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
961 if (err)
962 goto err_sq_wq_destroy;
963
964 return 0;
965
966err_sq_wq_destroy:
967 mlx5_wq_destroy(&sq->wq_ctrl);
968
969 return err;
970}
971
972static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
973{
974 mlx5e_free_xdpsq_db(sq);
975 mlx5_wq_destroy(&sq->wq_ctrl);
976}
977
978static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 979{
f10b7cc7 980 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 981}
982
31391048 983static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 984{
985 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
986
987 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
988 GFP_KERNEL, numa);
989 if (!sq->db.ico_wqe)
990 return -ENOMEM;
991
992 return 0;
993}
994
31391048 995static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 996 struct mlx5e_sq_param *param,
997 struct mlx5e_icosq *sq)
f10b7cc7 998{
31391048 999 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1000 struct mlx5_core_dev *mdev = c->mdev;
31391048 1001 int err;
f10b7cc7 1002
31391048
SM		 1003 sq->pdev = c->pdev;
1004 sq->mkey_be = c->mkey_be;
1005 sq->channel = c;
1006 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1007
31391048
SM		 1008 param->wq.db_numa_node = cpu_to_node(c->cpu);
1009 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1010 if (err)
1011 return err;
1012 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1013
31391048
SM		 1014 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1015 if (err)
1016 goto err_sq_wq_destroy;
1017
1018 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1019
1020 return 0;
31391048
SM		 1021
1022err_sq_wq_destroy:
1023 mlx5_wq_destroy(&sq->wq_ctrl);
1024
1025 return err;
f62b8bb8
AV		 1026}
1027
31391048 1028static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1029{
31391048
SM		 1030 mlx5e_free_icosq_db(sq);
1031 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1032}
1033
31391048 1034static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1035{
31391048
SM		 1036 kfree(sq->db.wqe_info);
1037 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 1038}
1039
31391048 1040static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1041{
31391048
SM		 1042 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1043 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1044
31391048
SM		 1045 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1046 GFP_KERNEL, numa);
1047 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1048 GFP_KERNEL, numa);
77bdf895 1049 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1050 mlx5e_free_txqsq_db(sq);
1051 return -ENOMEM;
b5503b99 1052 }
31391048
SM		 1053
1054 sq->dma_fifo_mask = df_sz - 1;
1055
1056 return 0;
b5503b99
SM		 1057}
1058
31391048 1059static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1060 int txq_ix,
6a9764ef 1061 struct mlx5e_params *params,
31391048
SM		 1062 struct mlx5e_sq_param *param,
1063 struct mlx5e_txqsq *sq)
f62b8bb8 1064{
31391048 1065 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1066 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1067 int err;
1068
f10b7cc7 1069 sq->pdev = c->pdev;
a43b25da 1070 sq->tstamp = c->tstamp;
f10b7cc7
SM		 1071 sq->mkey_be = c->mkey_be;
1072 sq->channel = c;
acc6c595 1073 sq->txq_ix = txq_ix;
aff26157 1074 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1075 sq->max_inline = params->tx_max_inline;
1076 sq->min_inline_mode = params->tx_min_inline_mode;
f10b7cc7 1077
311c7c71 1078 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1079 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1080 if (err)
aff26157 1081 return err;
31391048 1082 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1083
31391048 1084 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1085 if (err)
f62b8bb8
AV		 1086 goto err_sq_wq_destroy;
1087
31391048 1088 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1089
1090 return 0;
1091
1092err_sq_wq_destroy:
1093 mlx5_wq_destroy(&sq->wq_ctrl);
1094
f62b8bb8
AV		 1095 return err;
1096}
1097
31391048 1098static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1099{
31391048 1100 mlx5e_free_txqsq_db(sq);
f62b8bb8 1101 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1102}
1103
33ad9711
SM		 1104struct mlx5e_create_sq_param {
1105 struct mlx5_wq_ctrl *wq_ctrl;
1106 u32 cqn;
1107 u32 tisn;
1108 u8 tis_lst_sz;
1109 u8 min_inline_mode;
1110};
1111
a43b25da 1112static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1113 struct mlx5e_sq_param *param,
1114 struct mlx5e_create_sq_param *csp,
1115 u32 *sqn)
f62b8bb8 1116{
f62b8bb8
AV		 1117 void *in;
1118 void *sqc;
1119 void *wq;
1120 int inlen;
1121 int err;
1122
1123 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1124 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1125 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1126 if (!in)
1127 return -ENOMEM;
1128
1129 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1130 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1131
1132 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1133 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1134 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1135 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1136
1137 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1138 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1139
33ad9711 1140 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1141
1142 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1143 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1144 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1145 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1146 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1147
33ad9711 1148 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1149
33ad9711 1150 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1151
1152 kvfree(in);
1153
1154 return err;
1155}
1156
33ad9711
SM		 1157struct mlx5e_modify_sq_param {
1158 int curr_state;
1159 int next_state;
1160 bool rl_update;
1161 int rl_index;
1162};
1163
a43b25da 1164static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1165 struct mlx5e_modify_sq_param *p)
f62b8bb8 1166{
f62b8bb8
AV		 1167 void *in;
1168 void *sqc;
1169 int inlen;
1170 int err;
1171
1172 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1173 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1174 if (!in)
1175 return -ENOMEM;
1176
1177 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1178
33ad9711
SM		 1179 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1180 MLX5_SET(sqc, sqc, state, p->next_state);
1181 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1182 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1183 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1184 }
f62b8bb8 1185
33ad9711 1186 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1187
1188 kvfree(in);
1189
1190 return err;
1191}
1192
a43b25da 1193static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1194{
a43b25da 1195 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1196}
1197
a43b25da 1198static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1199 struct mlx5e_sq_param *param,
1200 struct mlx5e_create_sq_param *csp,
1201 u32 *sqn)
f62b8bb8 1202{
33ad9711 1203 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1204 int err;
1205
a43b25da 1206 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1207 if (err)
1208 return err;
1209
1210 msp.curr_state = MLX5_SQC_STATE_RST;
1211 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1212 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1213 if (err)
a43b25da 1214 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1215
1216 return err;
1217}
1218
7f859ecf
SM		 1219static int mlx5e_set_sq_maxrate(struct net_device *dev,
1220 struct mlx5e_txqsq *sq, u32 rate);
1221
31391048 1222static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1223 u32 tisn,
acc6c595 1224 int txq_ix,
6a9764ef 1225 struct mlx5e_params *params,
31391048
SM		 1226 struct mlx5e_sq_param *param,
1227 struct mlx5e_txqsq *sq)
1228{
1229 struct mlx5e_create_sq_param csp = {};
7f859ecf 1230 u32 tx_rate;
f62b8bb8
AV		 1231 int err;
1232
6a9764ef 1233 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1234 if (err)
1235 return err;
1236
a43b25da 1237 csp.tisn = tisn;
31391048 1238 csp.tis_lst_sz = 1;
33ad9711
SM		 1239 csp.cqn = sq->cq.mcq.cqn;
1240 csp.wq_ctrl = &sq->wq_ctrl;
1241 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1242 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1243 if (err)
31391048 1244 goto err_free_txqsq;
f62b8bb8 1245
a43b25da 1246 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1247 if (tx_rate)
a43b25da 1248 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1249
f62b8bb8
AV		 1250 return 0;
1251
31391048 1252err_free_txqsq:
3b77235b 1253 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1254 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1255
1256 return err;
1257}
1258
acc6c595
SM		 1259static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1260{
a43b25da 1261 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1262 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1263 netdev_tx_reset_queue(sq->txq);
1264 netif_tx_start_queue(sq->txq);
1265}
1266
f62b8bb8
AV		 1267static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1268{
1269 __netif_tx_lock_bh(txq);
1270 netif_tx_stop_queue(txq);
1271 __netif_tx_unlock_bh(txq);
1272}
1273
acc6c595 1274static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1275{
33ad9711 1276 struct mlx5e_channel *c = sq->channel;
33ad9711 1277
c0f1147d 1278 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1279 /* prevent netif_tx_wake_queue */
33ad9711 1280 napi_synchronize(&c->napi);
29429f33 1281
31391048 1282 netif_tx_disable_queue(sq->txq);
f62b8bb8 1283
31391048
SM		 1284 /* last doorbell out, godspeed .. */
1285 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1286 struct mlx5e_tx_wqe *nop;
864b2d71 1287
77bdf895 1288 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1289 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1290 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1291 }
acc6c595
SM		 1292}
1293
1294static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1295{
1296 struct mlx5e_channel *c = sq->channel;
a43b25da 1297 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1298
a43b25da 1299 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1300 if (sq->rate_limit)
1301 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1302 mlx5e_free_txqsq_descs(sq);
1303 mlx5e_free_txqsq(sq);
1304}
1305
1306static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1307 struct mlx5e_params *params,
31391048
SM		 1308 struct mlx5e_sq_param *param,
1309 struct mlx5e_icosq *sq)
1310{
1311 struct mlx5e_create_sq_param csp = {};
1312 int err;
1313
6a9764ef 1314 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1315 if (err)
1316 return err;
1317
1318 csp.cqn = sq->cq.mcq.cqn;
1319 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1320 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1321 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1322 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1323 if (err)
1324 goto err_free_icosq;
1325
1326 return 0;
1327
1328err_free_icosq:
1329 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1330 mlx5e_free_icosq(sq);
1331
1332 return err;
1333}
1334
1335static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1336{
1337 struct mlx5e_channel *c = sq->channel;
1338
1339 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1340 napi_synchronize(&c->napi);
1341
a43b25da 1342 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1343 mlx5e_free_icosq(sq);
1344}
1345
1346static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1347 struct mlx5e_params *params,
31391048
SM		 1348 struct mlx5e_sq_param *param,
1349 struct mlx5e_xdpsq *sq)
1350{
1351 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1352 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1353 unsigned int inline_hdr_sz = 0;
1354 int err;
1355 int i;
1356
6a9764ef 1357 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1358 if (err)
1359 return err;
1360
1361 csp.tis_lst_sz = 1;
a43b25da 1362 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1363 csp.cqn = sq->cq.mcq.cqn;
1364 csp.wq_ctrl = &sq->wq_ctrl;
1365 csp.min_inline_mode = sq->min_inline_mode;
1366 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1367 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1368 if (err)
1369 goto err_free_xdpsq;
1370
1371 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1372 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1373 ds_cnt++;
1374 }
1375
1376 /* Pre initialize fixed WQE fields */
1377 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1378 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1379 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1380 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1381 struct mlx5_wqe_data_seg *dseg;
1382
1383 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1384 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1385
1386 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1387 dseg->lkey = sq->mkey_be;
1388 }
1389
1390 return 0;
1391
1392err_free_xdpsq:
1393 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1394 mlx5e_free_xdpsq(sq);
1395
1396 return err;
1397}
1398
1399static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1400{
1401 struct mlx5e_channel *c = sq->channel;
1402
1403 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1404 napi_synchronize(&c->napi);
1405
a43b25da 1406 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1407 mlx5e_free_xdpsq_descs(sq);
1408 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1409}
1410
95b6c6a5
EBE		 1411static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1412 struct mlx5e_cq_param *param,
1413 struct mlx5e_cq *cq)
f62b8bb8 1414{
f62b8bb8
AV		 1415 struct mlx5_core_cq *mcq = &cq->mcq;
1416 int eqn_not_used;
0b6e26ce 1417 unsigned int irqn;
f62b8bb8
AV		 1418 int err;
1419 u32 i;
1420
f62b8bb8
AV		 1421 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1422 &cq->wq_ctrl);
1423 if (err)
1424 return err;
1425
1426 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1427
f62b8bb8
AV		 1428 mcq->cqe_sz = 64;
1429 mcq->set_ci_db = cq->wq_ctrl.db.db;
1430 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1431 *mcq->set_ci_db = 0;
1432 *mcq->arm_db = 0;
1433 mcq->vector = param->eq_ix;
1434 mcq->comp = mlx5e_completion_event;
1435 mcq->event = mlx5e_cq_error_event;
1436 mcq->irqn = irqn;
f62b8bb8
AV		 1437
1438 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1439 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1440
1441 cqe->op_own = 0xf1;
1442 }
1443
a43b25da 1444 cq->mdev = mdev;
f62b8bb8
AV		 1445
1446 return 0;
1447}
1448
95b6c6a5
EBE		 1449static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1450 struct mlx5e_cq_param *param,
1451 struct mlx5e_cq *cq)
1452{
1453 struct mlx5_core_dev *mdev = c->priv->mdev;
1454 int err;
1455
1456 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1457 param->wq.db_numa_node = cpu_to_node(c->cpu);
1458 param->eq_ix = c->ix;
1459
1460 err = mlx5e_alloc_cq_common(mdev, param, cq);
1461
1462 cq->napi = &c->napi;
1463 cq->channel = c;
1464
1465 return err;
1466}
1467
3b77235b 1468static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1469{
1c1b5228 1470 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1471}
1472
3b77235b 1473static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1474{
a43b25da 1475 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1476 struct mlx5_core_cq *mcq = &cq->mcq;
1477
1478 void *in;
1479 void *cqc;
1480 int inlen;
0b6e26ce 1481 unsigned int irqn_not_used;
f62b8bb8
AV		 1482 int eqn;
1483 int err;
1484
1485 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1486 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1487 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1488 if (!in)
1489 return -ENOMEM;
1490
1491 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1492
1493 memcpy(cqc, param->cqc, sizeof(param->cqc));
1494
1c1b5228
TT		 1495 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1496 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1497
1498 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1499
9908aa29 1500 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1501 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1502 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1503 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1504 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1505 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1506
1507 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1508
1509 kvfree(in);
1510
1511 if (err)
1512 return err;
1513
1514 mlx5e_cq_arm(cq);
1515
1516 return 0;
1517}
1518
3b77235b 1519static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1520{
a43b25da 1521 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1522}
1523
1524static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1525 struct mlx5e_cq_moder moder,
f62b8bb8 1526 struct mlx5e_cq_param *param,
6a9764ef 1527 struct mlx5e_cq *cq)
f62b8bb8 1528{
a43b25da 1529 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1530 int err;
f62b8bb8 1531
3b77235b 1532 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1533 if (err)
1534 return err;
1535
3b77235b 1536 err = mlx5e_create_cq(cq, param);
f62b8bb8 1537 if (err)
3b77235b 1538 goto err_free_cq;
f62b8bb8 1539
7524a5d8 1540 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1541 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1542 return 0;
1543
3b77235b
SM		 1544err_free_cq:
1545 mlx5e_free_cq(cq);
f62b8bb8
AV		 1546
1547 return err;
1548}
1549
1550static void mlx5e_close_cq(struct mlx5e_cq *cq)
1551{
f62b8bb8 1552 mlx5e_destroy_cq(cq);
3b77235b 1553 mlx5e_free_cq(cq);
f62b8bb8
AV		 1554}
1555
1556static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1557{
1558 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1559}
1560
1561static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1562 struct mlx5e_params *params,
f62b8bb8
AV		 1563 struct mlx5e_channel_param *cparam)
1564{
f62b8bb8
AV		 1565 int err;
1566 int tc;
1567
1568 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1569 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1570 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1571 if (err)
1572 goto err_close_tx_cqs;
f62b8bb8
AV		 1573 }
1574
1575 return 0;
1576
1577err_close_tx_cqs:
1578 for (tc--; tc >= 0; tc--)
1579 mlx5e_close_cq(&c->sq[tc].cq);
1580
1581 return err;
1582}
1583
1584static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1585{
1586 int tc;
1587
1588 for (tc = 0; tc < c->num_tc; tc++)
1589 mlx5e_close_cq(&c->sq[tc].cq);
1590}
1591
1592static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1593 struct mlx5e_params *params,
f62b8bb8
AV		 1594 struct mlx5e_channel_param *cparam)
1595{
1596 int err;
1597 int tc;
1598
6a9764ef
SM		 1599 for (tc = 0; tc < params->num_tc; tc++) {
1600 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1601
a43b25da
SM		 1602 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1603 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1604 if (err)
1605 goto err_close_sqs;
1606 }
1607
1608 return 0;
1609
1610err_close_sqs:
1611 for (tc--; tc >= 0; tc--)
31391048 1612 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1613
1614 return err;
1615}
1616
1617static void mlx5e_close_sqs(struct mlx5e_channel *c)
1618{
1619 int tc;
1620
1621 for (tc = 0; tc < c->num_tc; tc++)
31391048 1622 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1623}
1624
507f0c81 1625static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1626 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1627{
1628 struct mlx5e_priv *priv = netdev_priv(dev);
1629 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1630 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1631 u16 rl_index = 0;
1632 int err;
1633
1634 if (rate == sq->rate_limit)
1635 /* nothing to do */
1636 return 0;
1637
1638 if (sq->rate_limit)
1639 /* remove current rl index to free space to next ones */
1640 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1641
1642 sq->rate_limit = 0;
1643
1644 if (rate) {
1645 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1646 if (err) {
1647 netdev_err(dev, "Failed configuring rate %u: %d\n",
1648 rate, err);
1649 return err;
1650 }
1651 }
1652
33ad9711
SM		 1653 msp.curr_state = MLX5_SQC_STATE_RDY;
1654 msp.next_state = MLX5_SQC_STATE_RDY;
1655 msp.rl_index = rl_index;
1656 msp.rl_update = true;
a43b25da 1657 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1658 if (err) {
1659 netdev_err(dev, "Failed configuring rate %u: %d\n",
1660 rate, err);
1661 /* remove the rate from the table */
1662 if (rate)
1663 mlx5_rl_remove_rate(mdev, rate);
1664 return err;
1665 }
1666
1667 sq->rate_limit = rate;
1668 return 0;
1669}
1670
1671static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1672{
1673 struct mlx5e_priv *priv = netdev_priv(dev);
1674 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1675 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1676 int err = 0;
1677
1678 if (!mlx5_rl_is_supported(mdev)) {
1679 netdev_err(dev, "Rate limiting is not supported on this device\n");
1680 return -EINVAL;
1681 }
1682
1683 /* rate is given in Mb/sec, HW config is in Kb/sec */
1684 rate = rate << 10;
1685
1686 /* Check whether rate in valid range, 0 is always valid */
1687 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1688 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1689 return -ERANGE;
1690 }
1691
1692 mutex_lock(&priv->state_lock);
1693 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1694 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1695 if (!err)
1696 priv->tx_rates[index] = rate;
1697 mutex_unlock(&priv->state_lock);
1698
1699 return err;
1700}
1701
f62b8bb8 1702static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1703 struct mlx5e_params *params,
f62b8bb8
AV		 1704 struct mlx5e_channel_param *cparam,
1705 struct mlx5e_channel **cp)
1706{
6a9764ef 1707 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8
AV		 1708 struct net_device *netdev = priv->netdev;
1709 int cpu = mlx5e_get_cpu(priv, ix);
1710 struct mlx5e_channel *c;
1711 int err;
1712
1713 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1714 if (!c)
1715 return -ENOMEM;
1716
1717 c->priv = priv;
a43b25da
SM		 1718 c->mdev = priv->mdev;
1719 c->tstamp = &priv->tstamp;
f62b8bb8
AV		 1720 c->ix = ix;
1721 c->cpu = cpu;
1722 c->pdev = &priv->mdev->pdev->dev;
1723 c->netdev = priv->netdev;
b50d292b 1724 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1725 c->num_tc = params->num_tc;
1726 c->xdp = !!params->xdp_prog;
cb3c7fd4 1727
f62b8bb8
AV		 1728 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1729
6a9764ef 1730 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1731 if (err)
1732 goto err_napi_del;
1733
6a9764ef 1734 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1735 if (err)
1736 goto err_close_icosq_cq;
1737
6a9764ef 1738 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1739 if (err)
1740 goto err_close_tx_cqs;
f62b8bb8 1741
d7a0ecab 1742 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1743 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1744 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1745 if (err)
1746 goto err_close_rx_cq;
1747
f62b8bb8
AV		 1748 napi_enable(&c->napi);
1749
6a9764ef 1750 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1751 if (err)
1752 goto err_disable_napi;
1753
6a9764ef 1754 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1755 if (err)
1756 goto err_close_icosq;
1757
6a9764ef 1758 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1759 if (err)
1760 goto err_close_sqs;
b5503b99 1761
6a9764ef 1762 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1763 if (err)
b5503b99 1764 goto err_close_xdp_sq;
f62b8bb8 1765
f62b8bb8
AV		 1766 *cp = c;
1767
1768 return 0;
b5503b99 1769err_close_xdp_sq:
d7a0ecab 1770 if (c->xdp)
31391048 1771 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1772
1773err_close_sqs:
1774 mlx5e_close_sqs(c);
1775
d3c9bc27 1776err_close_icosq:
31391048 1777 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1778
f62b8bb8
AV		 1779err_disable_napi:
1780 napi_disable(&c->napi);
d7a0ecab 1781 if (c->xdp)
31871f87 1782 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1783
1784err_close_rx_cq:
f62b8bb8
AV		 1785 mlx5e_close_cq(&c->rq.cq);
1786
1787err_close_tx_cqs:
1788 mlx5e_close_tx_cqs(c);
1789
d3c9bc27
TT		 1790err_close_icosq_cq:
1791 mlx5e_close_cq(&c->icosq.cq);
1792
f62b8bb8
AV		 1793err_napi_del:
1794 netif_napi_del(&c->napi);
1795 kfree(c);
1796
1797 return err;
1798}
1799
acc6c595
SM		 1800static void mlx5e_activate_channel(struct mlx5e_channel *c)
1801{
1802 int tc;
1803
1804 for (tc = 0; tc < c->num_tc; tc++)
1805 mlx5e_activate_txqsq(&c->sq[tc]);
1806 mlx5e_activate_rq(&c->rq);
a43b25da 1807 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1808}
1809
1810static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1811{
1812 int tc;
1813
1814 mlx5e_deactivate_rq(&c->rq);
1815 for (tc = 0; tc < c->num_tc; tc++)
1816 mlx5e_deactivate_txqsq(&c->sq[tc]);
1817}
1818
f62b8bb8
AV		 1819static void mlx5e_close_channel(struct mlx5e_channel *c)
1820{
1821 mlx5e_close_rq(&c->rq);
b5503b99 1822 if (c->xdp)
31391048 1823 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1824 mlx5e_close_sqs(c);
31391048 1825 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1826 napi_disable(&c->napi);
b5503b99 1827 if (c->xdp)
31871f87 1828 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1829 mlx5e_close_cq(&c->rq.cq);
1830 mlx5e_close_tx_cqs(c);
d3c9bc27 1831 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1832 netif_napi_del(&c->napi);
7ae92ae5 1833
f62b8bb8
AV		 1834 kfree(c);
1835}
1836
1837static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1838 struct mlx5e_params *params,
f62b8bb8
AV		 1839 struct mlx5e_rq_param *param)
1840{
1841 void *rqc = param->rqc;
1842 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1843
6a9764ef 1844 switch (params->rq_wq_type) {
461017cb 1845 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1846 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1847 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1848 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1849 break;
1850 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1851 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1852 }
1853
f62b8bb8
AV		 1854 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1855 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1856 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1857 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1858 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1859 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1860 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1861
311c7c71 1862 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1863 param->wq.linear = 1;
1864}
1865
556dd1b9
TT		 1866static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1867{
1868 void *rqc = param->rqc;
1869 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1870
1871 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1872 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1873}
1874
d3c9bc27
TT		 1875static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1876 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1877{
1878 void *sqc = param->sqc;
1879 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1880
f62b8bb8 1881 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1882 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1883
311c7c71 1884 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1885}
1886
1887static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1888 struct mlx5e_params *params,
d3c9bc27
TT		 1889 struct mlx5e_sq_param *param)
1890{
1891 void *sqc = param->sqc;
1892 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1893
1894 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1895 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
f62b8bb8
AV		 1896}
1897
1898static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1899 struct mlx5e_cq_param *param)
1900{
1901 void *cqc = param->cqc;
1902
30aa60b3 1903 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1904}
1905
1906static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1907 struct mlx5e_params *params,
f62b8bb8
AV		 1908 struct mlx5e_cq_param *param)
1909{
1910 void *cqc = param->cqc;
461017cb 1911 u8 log_cq_size;
f62b8bb8 1912
6a9764ef 1913 switch (params->rq_wq_type) {
461017cb 1914 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1915 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1916 break;
1917 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1918 log_cq_size = params->log_rq_size;
461017cb
TT		 1919 }
1920
1921 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1922 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1923 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1924 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1925 }
f62b8bb8
AV		 1926
1927 mlx5e_build_common_cq_param(priv, param);
1928}
1929
1930static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1931 struct mlx5e_params *params,
f62b8bb8
AV		 1932 struct mlx5e_cq_param *param)
1933{
1934 void *cqc = param->cqc;
1935
6a9764ef 1936 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1937
1938 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1939
1940 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1941}
1942
d3c9bc27 1943static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1944 u8 log_wq_size,
1945 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1946{
1947 void *cqc = param->cqc;
1948
1949 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1950
1951 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1952
1953 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1954}
1955
1956static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1957 u8 log_wq_size,
1958 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1959{
1960 void *sqc = param->sqc;
1961 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1962
1963 mlx5e_build_sq_param_common(priv, param);
1964
1965 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1966 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1967}
1968
b5503b99 1969static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1970 struct mlx5e_params *params,
b5503b99
SM		 1971 struct mlx5e_sq_param *param)
1972{
1973 void *sqc = param->sqc;
1974 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1975
1976 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1977 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1978}
1979
6a9764ef
SM		 1980static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1981 struct mlx5e_params *params,
1982 struct mlx5e_channel_param *cparam)
f62b8bb8 1983{
bc77b240 1984 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1985
6a9764ef
SM		 1986 mlx5e_build_rq_param(priv, params, &cparam->rq);
1987 mlx5e_build_sq_param(priv, params, &cparam->sq);
1988 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
1989 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
1990 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
1991 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
1992 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 1993}
1994
55c2503d
SM		 1995int mlx5e_open_channels(struct mlx5e_priv *priv,
1996 struct mlx5e_channels *chs)
f62b8bb8 1997{
6b87663f 1998 struct mlx5e_channel_param *cparam;
03289b88 1999 int err = -ENOMEM;
f62b8bb8 2000 int i;
f62b8bb8 2001
6a9764ef 2002 chs->num = chs->params.num_channels;
03289b88 2003
ff9c852f 2004 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2005 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2006 if (!chs->c || !cparam)
2007 goto err_free;
f62b8bb8 2008
6a9764ef 2009 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2010 for (i = 0; i < chs->num; i++) {
6a9764ef 2011 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2012 if (err)
2013 goto err_close_channels;
2014 }
2015
6b87663f 2016 kfree(cparam);
f62b8bb8
AV		 2017 return 0;
2018
2019err_close_channels:
2020 for (i--; i >= 0; i--)
ff9c852f 2021 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2022
acc6c595 2023err_free:
ff9c852f 2024 kfree(chs->c);
6b87663f 2025 kfree(cparam);
ff9c852f 2026 chs->num = 0;
f62b8bb8
AV		 2027 return err;
2028}
2029
acc6c595 2030static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2031{
2032 int i;
2033
acc6c595
SM		 2034 for (i = 0; i < chs->num; i++)
2035 mlx5e_activate_channel(chs->c[i]);
2036}
2037
2038static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2039{
2040 int err = 0;
2041 int i;
2042
2043 for (i = 0; i < chs->num; i++) {
2044 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2045 if (err)
2046 break;
2047 }
2048
2049 return err;
2050}
2051
2052static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2053{
2054 int i;
2055
2056 for (i = 0; i < chs->num; i++)
2057 mlx5e_deactivate_channel(chs->c[i]);
2058}
2059
55c2503d 2060void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2061{
2062 int i;
c3b7c5c9 2063
ff9c852f
SM		 2064 for (i = 0; i < chs->num; i++)
2065 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2066
ff9c852f
SM		 2067 kfree(chs->c);
2068 chs->num = 0;
f62b8bb8
AV		 2069}
2070
a5f97fee
SM		 2071static int
2072mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2073{
2074 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2075 void *rqtc;
2076 int inlen;
2077 int err;
1da36696 2078 u32 *in;
a5f97fee 2079 int i;
f62b8bb8 2080
f62b8bb8 2081 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2082 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2083 if (!in)
2084 return -ENOMEM;
2085
2086 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2087
2088 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2089 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2090
a5f97fee
SM		 2091 for (i = 0; i < sz; i++)
2092 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2093
398f3351
HHZ		 2094 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2095 if (!err)
2096 rqt->enabled = true;
f62b8bb8
AV		 2097
2098 kvfree(in);
1da36696
TT		 2099 return err;
2100}
2101
cb67b832 2102void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2103{
398f3351
HHZ		 2104 rqt->enabled = false;
2105 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2106}
2107
8f493ffd 2108int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2109{
2110 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2111 int err;
6bfd390b 2112
8f493ffd
SM		 2113 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2114 if (err)
2115 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2116 return err;
6bfd390b
HHZ		 2117}
2118
cb67b832 2119int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2120{
398f3351 2121 struct mlx5e_rqt *rqt;
1da36696
TT		 2122 int err;
2123 int ix;
2124
6bfd390b 2125 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2126 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2127 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2128 if (err)
2129 goto err_destroy_rqts;
2130 }
2131
2132 return 0;
2133
2134err_destroy_rqts:
8f493ffd 2135 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2136 for (ix--; ix >= 0; ix--)
398f3351 2137 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2138
f62b8bb8
AV		 2139 return err;
2140}
2141
8f493ffd
SM		 2142void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2143{
2144 int i;
2145
2146 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2147 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2148}
2149
a5f97fee
SM		 2150static int mlx5e_rx_hash_fn(int hfunc)
2151{
2152 return (hfunc == ETH_RSS_HASH_TOP) ?
2153 MLX5_RX_HASH_FN_TOEPLITZ :
2154 MLX5_RX_HASH_FN_INVERTED_XOR8;
2155}
2156
2157static int mlx5e_bits_invert(unsigned long a, int size)
2158{
2159 int inv = 0;
2160 int i;
2161
2162 for (i = 0; i < size; i++)
2163 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2164
2165 return inv;
2166}
2167
2168static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2169 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2170{
2171 int i;
2172
2173 for (i = 0; i < sz; i++) {
2174 u32 rqn;
2175
2176 if (rrp.is_rss) {
2177 int ix = i;
2178
2179 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2180 ix = mlx5e_bits_invert(i, ilog2(sz));
2181
6a9764ef 2182 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2183 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2184 } else {
2185 rqn = rrp.rqn;
2186 }
2187 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2188 }
2189}
2190
2191int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2192 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2193{
2194 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2195 void *rqtc;
2196 int inlen;
1da36696 2197 u32 *in;
5c50368f
AS		 2198 int err;
2199
5c50368f 2200 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2201 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2202 if (!in)
2203 return -ENOMEM;
2204
2205 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2206
2207 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2208 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2209 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2210 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2211
2212 kvfree(in);
5c50368f
AS		 2213 return err;
2214}
2215
a5f97fee
SM		 2216static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2217 struct mlx5e_redirect_rqt_param rrp)
2218{
2219 if (!rrp.is_rss)
2220 return rrp.rqn;
2221
2222 if (ix >= rrp.rss.channels->num)
2223 return priv->drop_rq.rqn;
2224
2225 return rrp.rss.channels->c[ix]->rq.rqn;
2226}
2227
2228static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2229 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2230{
1da36696
TT		 2231 u32 rqtn;
2232 int ix;
2233
398f3351 2234 if (priv->indir_rqt.enabled) {
a5f97fee 2235 /* RSS RQ table */
398f3351 2236 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2237 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2238 }
2239
a5f97fee
SM		 2240 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2241 struct mlx5e_redirect_rqt_param direct_rrp = {
2242 .is_rss = false,
95632791
AM		 2243 {
2244 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2245 },
a5f97fee
SM		 2246 };
2247
2248 /* Direct RQ Tables */
398f3351
HHZ		 2249 if (!priv->direct_tir[ix].rqt.enabled)
2250 continue;
a5f97fee 2251
398f3351 2252 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2253 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2254 }
40ab6a6e
AS		 2255}
2256
a5f97fee
SM		 2257static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2258 struct mlx5e_channels *chs)
2259{
2260 struct mlx5e_redirect_rqt_param rrp = {
2261 .is_rss = true,
95632791
AM		 2262 {
2263 .rss = {
2264 .channels = chs,
2265 .hfunc = chs->params.rss_hfunc,
2266 }
2267 },
a5f97fee
SM		 2268 };
2269
2270 mlx5e_redirect_rqts(priv, rrp);
2271}
2272
2273static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2274{
2275 struct mlx5e_redirect_rqt_param drop_rrp = {
2276 .is_rss = false,
95632791
AM		 2277 {
2278 .rqn = priv->drop_rq.rqn,
2279 },
a5f97fee
SM		 2280 };
2281
2282 mlx5e_redirect_rqts(priv, drop_rrp);
2283}
2284
6a9764ef 2285static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2286{
6a9764ef 2287 if (!params->lro_en)
5c50368f
AS		 2288 return;
2289
2290#define ROUGH_MAX_L2_L3_HDR_SZ 256
2291
2292 MLX5_SET(tirc, tirc, lro_enable_mask,
2293 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2294 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2295 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2296 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2297 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2298}
2299
6a9764ef
SM		 2300void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2301 enum mlx5e_traffic_types tt,
2302 void *tirc)
bdfc028d 2303{
a100ff3e
GP		 2304 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2305
2306#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2307 MLX5_HASH_FIELD_SEL_DST_IP)
2308
2309#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2310 MLX5_HASH_FIELD_SEL_DST_IP |\
2311 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2312 MLX5_HASH_FIELD_SEL_L4_DPORT)
2313
2314#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2315 MLX5_HASH_FIELD_SEL_DST_IP |\
2316 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2317
6a9764ef
SM		 2318 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2319 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2320 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2321 rx_hash_toeplitz_key);
2322 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2323 rx_hash_toeplitz_key);
2324
2325 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2326 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2327 }
a100ff3e
GP		 2328
2329 switch (tt) {
2330 case MLX5E_TT_IPV4_TCP:
2331 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2332 MLX5_L3_PROT_TYPE_IPV4);
2333 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2334 MLX5_L4_PROT_TYPE_TCP);
2335 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2336 MLX5_HASH_IP_L4PORTS);
2337 break;
2338
2339 case MLX5E_TT_IPV6_TCP:
2340 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2341 MLX5_L3_PROT_TYPE_IPV6);
2342 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2343 MLX5_L4_PROT_TYPE_TCP);
2344 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2345 MLX5_HASH_IP_L4PORTS);
2346 break;
2347
2348 case MLX5E_TT_IPV4_UDP:
2349 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2350 MLX5_L3_PROT_TYPE_IPV4);
2351 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2352 MLX5_L4_PROT_TYPE_UDP);
2353 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2354 MLX5_HASH_IP_L4PORTS);
2355 break;
2356
2357 case MLX5E_TT_IPV6_UDP:
2358 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2359 MLX5_L3_PROT_TYPE_IPV6);
2360 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2361 MLX5_L4_PROT_TYPE_UDP);
2362 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2363 MLX5_HASH_IP_L4PORTS);
2364 break;
2365
2366 case MLX5E_TT_IPV4_IPSEC_AH:
2367 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2368 MLX5_L3_PROT_TYPE_IPV4);
2369 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2370 MLX5_HASH_IP_IPSEC_SPI);
2371 break;
2372
2373 case MLX5E_TT_IPV6_IPSEC_AH:
2374 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2375 MLX5_L3_PROT_TYPE_IPV6);
2376 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2377 MLX5_HASH_IP_IPSEC_SPI);
2378 break;
2379
2380 case MLX5E_TT_IPV4_IPSEC_ESP:
2381 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2382 MLX5_L3_PROT_TYPE_IPV4);
2383 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2384 MLX5_HASH_IP_IPSEC_SPI);
2385 break;
2386
2387 case MLX5E_TT_IPV6_IPSEC_ESP:
2388 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2389 MLX5_L3_PROT_TYPE_IPV6);
2390 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2391 MLX5_HASH_IP_IPSEC_SPI);
2392 break;
2393
2394 case MLX5E_TT_IPV4:
2395 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2396 MLX5_L3_PROT_TYPE_IPV4);
2397 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2398 MLX5_HASH_IP);
2399 break;
2400
2401 case MLX5E_TT_IPV6:
2402 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2403 MLX5_L3_PROT_TYPE_IPV6);
2404 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2405 MLX5_HASH_IP);
2406 break;
2407 default:
2408 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2409 }
bdfc028d
TT		 2410}
2411
ab0394fe 2412static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2413{
2414 struct mlx5_core_dev *mdev = priv->mdev;
2415
2416 void *in;
2417 void *tirc;
2418 int inlen;
2419 int err;
ab0394fe 2420 int tt;
1da36696 2421 int ix;
5c50368f
AS		 2422
2423 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2424 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2425 if (!in)
2426 return -ENOMEM;
2427
2428 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2429 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2430
6a9764ef 2431 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2432
1da36696 2433 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2434 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2435 inlen);
ab0394fe 2436 if (err)
1da36696 2437 goto free_in;
ab0394fe 2438 }
5c50368f 2439
6bfd390b 2440 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2441 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2442 in, inlen);
2443 if (err)
2444 goto free_in;
2445 }
2446
2447free_in:
5c50368f
AS		 2448 kvfree(in);
2449
2450 return err;
2451}
2452
cd255eff 2453static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2454{
40ab6a6e 2455 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2456 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2457 int err;
2458
cd255eff 2459 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2460 if (err)
2461 return err;
2462
cd255eff
SM		 2463 /* Update vport context MTU */
2464 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2465 return 0;
2466}
40ab6a6e 2467
cd255eff
SM		 2468static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2469{
2470 struct mlx5_core_dev *mdev = priv->mdev;
2471 u16 hw_mtu = 0;
2472 int err;
40ab6a6e 2473
cd255eff
SM		 2474 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2475 if (err || !hw_mtu) /* fallback to port oper mtu */
2476 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2477
2478 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2479}
2480
2e20a151 2481static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2482{
2e20a151 2483 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2484 u16 mtu;
2485 int err;
2486
2487 err = mlx5e_set_mtu(priv, netdev->mtu);
2488 if (err)
2489 return err;
40ab6a6e 2490
cd255eff
SM		 2491 mlx5e_query_mtu(priv, &mtu);
2492 if (mtu != netdev->mtu)
2493 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2494 __func__, mtu, netdev->mtu);
40ab6a6e 2495
cd255eff 2496 netdev->mtu = mtu;
40ab6a6e
AS		 2497 return 0;
2498}
2499
08fb1dac
SM		 2500static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2501{
2502 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2503 int nch = priv->channels.params.num_channels;
2504 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2505 int tc;
2506
2507 netdev_reset_tc(netdev);
2508
2509 if (ntc == 1)
2510 return;
2511
2512 netdev_set_num_tc(netdev, ntc);
2513
7ccdd084
RS		 2514 /* Map netdev TCs to offset 0
2515 * We have our own UP to TXQ mapping for QoS
2516 */
08fb1dac 2517 for (tc = 0; tc < ntc; tc++)
7ccdd084 2518 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2519}
2520
acc6c595
SM		 2521static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2522{
2523 struct mlx5e_channel *c;
2524 struct mlx5e_txqsq *sq;
2525 int i, tc;
2526
2527 for (i = 0; i < priv->channels.num; i++)
2528 for (tc = 0; tc < priv->profile->max_tc; tc++)
2529 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2530
2531 for (i = 0; i < priv->channels.num; i++) {
2532 c = priv->channels.c[i];
2533 for (tc = 0; tc < c->num_tc; tc++) {
2534 sq = &c->sq[tc];
2535 priv->txq2sq[sq->txq_ix] = sq;
2536 }
2537 }
2538}
2539
955bc480
SM		 2540static bool mlx5e_is_eswitch_vport_mngr(struct mlx5_core_dev *mdev)
2541{
2542 return (MLX5_CAP_GEN(mdev, vport_group_manager) &&
2543 MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH);
2544}
2545
603f4a45 2546void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2547{
9008ae07
SM		 2548 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2549 struct net_device *netdev = priv->netdev;
2550
2551 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2552 netif_set_real_num_tx_queues(netdev, num_txqs);
2553 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2554
acc6c595
SM		 2555 mlx5e_build_channels_tx_maps(priv);
2556 mlx5e_activate_channels(&priv->channels);
2557 netif_tx_start_all_queues(priv->netdev);
9008ae07 2558
955bc480 2559 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
9008ae07
SM		 2560 mlx5e_add_sqs_fwd_rules(priv);
2561
acc6c595 2562 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2563 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2564}
2565
603f4a45 2566void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2567{
9008ae07
SM		 2568 mlx5e_redirect_rqts_to_drop(priv);
2569
955bc480 2570 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
9008ae07
SM		 2571 mlx5e_remove_sqs_fwd_rules(priv);
2572
acc6c595
SM		 2573 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2574 * polling for inactive tx queues.
2575 */
2576 netif_tx_stop_all_queues(priv->netdev);
2577 netif_tx_disable(priv->netdev);
2578 mlx5e_deactivate_channels(&priv->channels);
2579}
2580
55c2503d 2581void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2582 struct mlx5e_channels *new_chs,
2583 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2584{
2585 struct net_device *netdev = priv->netdev;
2586 int new_num_txqs;
2587
2588 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2589
2590 netif_carrier_off(netdev);
2591
2592 if (new_num_txqs < netdev->real_num_tx_queues)
2593 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2594
2595 mlx5e_deactivate_priv_channels(priv);
2596 mlx5e_close_channels(&priv->channels);
2597
2598 priv->channels = *new_chs;
2599
2e20a151
SM		 2600 /* New channels are ready to roll, modify HW settings if needed */
2601 if (hw_modify)
2602 hw_modify(priv);
2603
55c2503d
SM		 2604 mlx5e_refresh_tirs(priv, false);
2605 mlx5e_activate_priv_channels(priv);
2606
2607 mlx5e_update_carrier(priv);
2608}
2609
40ab6a6e
AS		 2610int mlx5e_open_locked(struct net_device *netdev)
2611{
2612 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2613 int err;
2614
2615 set_bit(MLX5E_STATE_OPENED, &priv->state);
2616
ff9c852f 2617 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2618 if (err)
343b29f3 2619 goto err_clear_state_opened_flag;
40ab6a6e 2620
b676f653 2621 mlx5e_refresh_tirs(priv, false);
acc6c595 2622 mlx5e_activate_priv_channels(priv);
ce89ef36 2623 mlx5e_update_carrier(priv);
ef9814de 2624 mlx5e_timestamp_init(priv);
be4891af 2625
cb67b832
HHZ		 2626 if (priv->profile->update_stats)
2627 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2628
9b37b07f 2629 return 0;
343b29f3
AS		 2630
2631err_clear_state_opened_flag:
2632 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2633 return err;
40ab6a6e
AS		 2634}
2635
cb67b832 2636int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2637{
2638 struct mlx5e_priv *priv = netdev_priv(netdev);
2639 int err;
2640
2641 mutex_lock(&priv->state_lock);
2642 err = mlx5e_open_locked(netdev);
2643 mutex_unlock(&priv->state_lock);
2644
2645 return err;
2646}
2647
2648int mlx5e_close_locked(struct net_device *netdev)
2649{
2650 struct mlx5e_priv *priv = netdev_priv(netdev);
2651
a1985740
AS		 2652 /* May already be CLOSED in case a previous configuration operation
2653 * (e.g RX/TX queue size change) that involves close&open failed.
2654 */
2655 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2656 return 0;
2657
40ab6a6e
AS		 2658 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2659
ef9814de 2660 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2661 netif_carrier_off(priv->netdev);
acc6c595
SM		 2662 mlx5e_deactivate_priv_channels(priv);
2663 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2664
2665 return 0;
2666}
2667
cb67b832 2668int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2669{
2670 struct mlx5e_priv *priv = netdev_priv(netdev);
2671 int err;
2672
26e59d80
MHY		 2673 if (!netif_device_present(netdev))
2674 return -ENODEV;
2675
40ab6a6e
AS		 2676 mutex_lock(&priv->state_lock);
2677 err = mlx5e_close_locked(netdev);
2678 mutex_unlock(&priv->state_lock);
2679
2680 return err;
2681}
2682
a43b25da 2683static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2684 struct mlx5e_rq *rq,
2685 struct mlx5e_rq_param *param)
40ab6a6e 2686{
40ab6a6e
AS		 2687 void *rqc = param->rqc;
2688 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2689 int err;
2690
2691 param->wq.db_numa_node = param->wq.buf_numa_node;
2692
2693 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2694 &rq->wq_ctrl);
2695 if (err)
2696 return err;
2697
a43b25da 2698 rq->mdev = mdev;
40ab6a6e
AS		 2699
2700 return 0;
2701}
2702
a43b25da 2703static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2704 struct mlx5e_cq *cq,
2705 struct mlx5e_cq_param *param)
40ab6a6e 2706{
95b6c6a5 2707 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2708}
2709
a43b25da
SM		 2710static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2711 struct mlx5e_rq *drop_rq)
40ab6a6e 2712{
a43b25da
SM		 2713 struct mlx5e_cq_param cq_param = {};
2714 struct mlx5e_rq_param rq_param = {};
2715 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2716 int err;
2717
556dd1b9 2718 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2719
a43b25da 2720 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2721 if (err)
2722 return err;
2723
3b77235b 2724 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2725 if (err)
3b77235b 2726 goto err_free_cq;
40ab6a6e 2727
a43b25da 2728 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2729 if (err)
3b77235b 2730 goto err_destroy_cq;
40ab6a6e 2731
a43b25da 2732 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2733 if (err)
3b77235b 2734 goto err_free_rq;
40ab6a6e
AS		 2735
2736 return 0;
2737
3b77235b 2738err_free_rq:
a43b25da 2739 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2740
2741err_destroy_cq:
a43b25da 2742 mlx5e_destroy_cq(cq);
40ab6a6e 2743
3b77235b 2744err_free_cq:
a43b25da 2745 mlx5e_free_cq(cq);
3b77235b 2746
40ab6a6e
AS		 2747 return err;
2748}
2749
a43b25da 2750static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2751{
a43b25da
SM		 2752 mlx5e_destroy_rq(drop_rq);
2753 mlx5e_free_rq(drop_rq);
2754 mlx5e_destroy_cq(&drop_rq->cq);
2755 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2756}
2757
5426a0b2
SM		 2758int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2759 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2760{
c4f287c4 2761 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2762 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2763
08fb1dac 2764 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2765 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2766 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2767
2768 if (mlx5_lag_is_lacp_owner(mdev))
2769 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2770
5426a0b2 2771 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2772}
2773
5426a0b2 2774void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2775{
5426a0b2 2776 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2777}
2778
cb67b832 2779int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2780{
2781 int err;
2782 int tc;
2783
6bfd390b 2784 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2785 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2786 if (err)
2787 goto err_close_tises;
2788 }
2789
2790 return 0;
2791
2792err_close_tises:
2793 for (tc--; tc >= 0; tc--)
5426a0b2 2794 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2795
2796 return err;
2797}
2798
cb67b832 2799void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2800{
2801 int tc;
2802
6bfd390b 2803 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2804 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2805}
2806
6a9764ef
SM		 2807static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2808 enum mlx5e_traffic_types tt,
2809 u32 *tirc)
f62b8bb8 2810{
b50d292b 2811 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2812
6a9764ef 2813 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2814
4cbeaff5 2815 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2816 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
6a9764ef 2817 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
f62b8bb8
AV		 2818}
2819
6a9764ef 2820static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2821{
b50d292b 2822 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2823
6a9764ef 2824 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2825
2826 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2827 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2828 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2829}
2830
8f493ffd 2831int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2832{
724b2aa1 2833 struct mlx5e_tir *tir;
f62b8bb8
AV		 2834 void *tirc;
2835 int inlen;
2836 int err;
1da36696 2837 u32 *in;
1da36696 2838 int tt;
f62b8bb8
AV		 2839
2840 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2841 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2842 if (!in)
2843 return -ENOMEM;
2844
1da36696
TT		 2845 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2846 memset(in, 0, inlen);
724b2aa1 2847 tir = &priv->indir_tir[tt];
1da36696 2848 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2849 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2850 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2851 if (err)
40ab6a6e 2852 goto err_destroy_tirs;
f62b8bb8
AV		 2853 }
2854
6bfd390b
HHZ		 2855 kvfree(in);
2856
2857 return 0;
2858
2859err_destroy_tirs:
8f493ffd 2860 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
6bfd390b
HHZ		 2861 for (tt--; tt >= 0; tt--)
2862 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2863
2864 kvfree(in);
2865
2866 return err;
2867}
2868
cb67b832 2869int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2870{
2871 int nch = priv->profile->max_nch(priv->mdev);
2872 struct mlx5e_tir *tir;
2873 void *tirc;
2874 int inlen;
2875 int err;
2876 u32 *in;
2877 int ix;
2878
2879 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2880 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2881 if (!in)
2882 return -ENOMEM;
2883
1da36696
TT		 2884 for (ix = 0; ix < nch; ix++) {
2885 memset(in, 0, inlen);
724b2aa1 2886 tir = &priv->direct_tir[ix];
1da36696 2887 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2888 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2889 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2890 if (err)
2891 goto err_destroy_ch_tirs;
2892 }
2893
2894 kvfree(in);
2895
f62b8bb8
AV		 2896 return 0;
2897
1da36696 2898err_destroy_ch_tirs:
8f493ffd 2899 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 2900 for (ix--; ix >= 0; ix--)
724b2aa1 2901 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2902
1da36696 2903 kvfree(in);
f62b8bb8
AV		 2904
2905 return err;
2906}
2907
8f493ffd 2908void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2909{
2910 int i;
2911
1da36696 2912 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2913 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2914}
2915
cb67b832 2916void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2917{
2918 int nch = priv->profile->max_nch(priv->mdev);
2919 int i;
2920
2921 for (i = 0; i < nch; i++)
2922 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2923}
2924
102722fc
GE		 2925static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2926{
2927 int err = 0;
2928 int i;
2929
2930 for (i = 0; i < chs->num; i++) {
2931 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2932 if (err)
2933 return err;
2934 }
2935
2936 return 0;
2937}
2938
f6d96a20 2939static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2940{
2941 int err = 0;
2942 int i;
2943
ff9c852f
SM		 2944 for (i = 0; i < chs->num; i++) {
2945 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2946 if (err)
2947 return err;
2948 }
2949
2950 return 0;
2951}
2952
08fb1dac
SM		 2953static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2954{
2955 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 2956 struct mlx5e_channels new_channels = {};
08fb1dac
SM		 2957 int err = 0;
2958
2959 if (tc && tc != MLX5E_MAX_NUM_TC)
2960 return -EINVAL;
2961
2962 mutex_lock(&priv->state_lock);
2963
6f9485af
SM		 2964 new_channels.params = priv->channels.params;
2965 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 2966
20b6a1c7 2967 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 2968 priv->channels.params = new_channels.params;
2969 goto out;
2970 }
08fb1dac 2971
6f9485af
SM		 2972 err = mlx5e_open_channels(priv, &new_channels);
2973 if (err)
2974 goto out;
08fb1dac 2975
2e20a151 2976 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 2977out:
08fb1dac 2978 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 2979 return err;
2980}
2981
2982static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
a5fcf8a6
JP		 2983 u32 chain_index, __be16 proto,
2984 struct tc_to_netdev *tc)
08fb1dac 2985{
e8f887ac
AV		 2986 struct mlx5e_priv *priv = netdev_priv(dev);
2987
2988 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2989 goto mqprio;
2990
a5fcf8a6
JP		 2991 if (chain_index)
2992 return -EOPNOTSUPP;
2993
e8f887ac 2994 switch (tc->type) {
e3a2b7ed
AV		 2995 case TC_SETUP_CLSFLOWER:
2996 switch (tc->cls_flower->command) {
2997 case TC_CLSFLOWER_REPLACE:
2998 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2999 case TC_CLSFLOWER_DESTROY:
3000 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 3001 case TC_CLSFLOWER_STATS:
3002 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 3003 }
e8f887ac
AV		 3004 default:
3005 return -EOPNOTSUPP;
3006 }
3007
3008mqprio:
67ba422e 3009 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 3010 return -EINVAL;
3011
56f36acd
AN		 3012 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3013
3014 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
08fb1dac
SM		 3015}
3016
bc1f4470 3017static void
f62b8bb8
AV		 3018mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3019{
3020 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3021 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3022 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3023 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3024
370bad0f
OG		 3025 if (mlx5e_is_uplink_rep(priv)) {
3026 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3027 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3028 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3029 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3030 } else {
3031 stats->rx_packets = sstats->rx_packets;
3032 stats->rx_bytes = sstats->rx_bytes;
3033 stats->tx_packets = sstats->tx_packets;
3034 stats->tx_bytes = sstats->tx_bytes;
3035 stats->tx_dropped = sstats->tx_queue_dropped;
3036 }
269e6b3a
GP		 3037
3038 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3039
3040 stats->rx_length_errors =
9218b44d
GP		 3041 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3042 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3043 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3044 stats->rx_crc_errors =
9218b44d
GP		 3045 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3046 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3047 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 3048 stats->tx_carrier_errors =
9218b44d 3049 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 3050 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3051 stats->rx_frame_errors;
3052 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3053
3054 /* vport multicast also counts packets that are dropped due to steering
3055 * or rx out of buffer
3056 */
9218b44d
GP		 3057 stats->multicast =
3058 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3059}
3060
3061static void mlx5e_set_rx_mode(struct net_device *dev)
3062{
3063 struct mlx5e_priv *priv = netdev_priv(dev);
3064
7bb29755 3065 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3066}
3067
3068static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3069{
3070 struct mlx5e_priv *priv = netdev_priv(netdev);
3071 struct sockaddr *saddr = addr;
3072
3073 if (!is_valid_ether_addr(saddr->sa_data))
3074 return -EADDRNOTAVAIL;
3075
3076 netif_addr_lock_bh(netdev);
3077 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3078 netif_addr_unlock_bh(netdev);
3079
7bb29755 3080 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3081
3082 return 0;
3083}
3084
0e405443
GP		 3085#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3086 do { \
3087 if (enable) \
3088 netdev->features |= feature; \
3089 else \
3090 netdev->features &= ~feature; \
3091 } while (0)
3092
3093typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3094
3095static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3096{
3097 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3098 struct mlx5e_channels new_channels = {};
3099 int err = 0;
3100 bool reset;
f62b8bb8
AV		 3101
3102 mutex_lock(&priv->state_lock);
f62b8bb8 3103
2e20a151
SM		 3104 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3105 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3106
2e20a151
SM		 3107 new_channels.params = priv->channels.params;
3108 new_channels.params.lro_en = enable;
3109
3110 if (!reset) {
3111 priv->channels.params = new_channels.params;
3112 err = mlx5e_modify_tirs_lro(priv);
3113 goto out;
98e81b0a 3114 }
f62b8bb8 3115
2e20a151
SM		 3116 err = mlx5e_open_channels(priv, &new_channels);
3117 if (err)
3118 goto out;
0e405443 3119
2e20a151
SM		 3120 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3121out:
9b37b07f 3122 mutex_unlock(&priv->state_lock);
0e405443
GP		 3123 return err;
3124}
3125
3126static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3127{
3128 struct mlx5e_priv *priv = netdev_priv(netdev);
3129
3130 if (enable)
3131 mlx5e_enable_vlan_filter(priv);
3132 else
3133 mlx5e_disable_vlan_filter(priv);
3134
3135 return 0;
3136}
3137
3138static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3139{
3140 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3141
0e405443 3142 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3143 netdev_err(netdev,
3144 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3145 return -EINVAL;
3146 }
3147
0e405443
GP		 3148 return 0;
3149}
3150
94cb1ebb
EBE		 3151static int set_feature_rx_all(struct net_device *netdev, bool enable)
3152{
3153 struct mlx5e_priv *priv = netdev_priv(netdev);
3154 struct mlx5_core_dev *mdev = priv->mdev;
3155
3156 return mlx5_set_port_fcs(mdev, !enable);
3157}
3158
102722fc
GE		 3159static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3160{
3161 struct mlx5e_priv *priv = netdev_priv(netdev);
3162 int err;
3163
3164 mutex_lock(&priv->state_lock);
3165
3166 priv->channels.params.scatter_fcs_en = enable;
3167 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3168 if (err)
3169 priv->channels.params.scatter_fcs_en = !enable;
3170
3171 mutex_unlock(&priv->state_lock);
3172
3173 return err;
3174}
3175
36350114
GP		 3176static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3177{
3178 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3179 int err = 0;
36350114
GP		 3180
3181 mutex_lock(&priv->state_lock);
3182
6a9764ef 3183 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3184 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3185 goto unlock;
3186
3187 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3188 if (err)
6a9764ef 3189 priv->channels.params.vlan_strip_disable = enable;
36350114 3190
ff9c852f 3191unlock:
36350114
GP		 3192 mutex_unlock(&priv->state_lock);
3193
3194 return err;
3195}
3196
45bf454a
MG		 3197#ifdef CONFIG_RFS_ACCEL
3198static int set_feature_arfs(struct net_device *netdev, bool enable)
3199{
3200 struct mlx5e_priv *priv = netdev_priv(netdev);
3201 int err;
3202
3203 if (enable)
3204 err = mlx5e_arfs_enable(priv);
3205 else
3206 err = mlx5e_arfs_disable(priv);
3207
3208 return err;
3209}
3210#endif
3211
0e405443
GP		 3212static int mlx5e_handle_feature(struct net_device *netdev,
3213 netdev_features_t wanted_features,
3214 netdev_features_t feature,
3215 mlx5e_feature_handler feature_handler)
3216{
3217 netdev_features_t changes = wanted_features ^ netdev->features;
3218 bool enable = !!(wanted_features & feature);
3219 int err;
3220
3221 if (!(changes & feature))
3222 return 0;
3223
3224 err = feature_handler(netdev, enable);
3225 if (err) {
3226 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3227 enable ? "Enable" : "Disable", feature, err);
3228 return err;
3229 }
3230
3231 MLX5E_SET_FEATURE(netdev, feature, enable);
3232 return 0;
3233}
3234
3235static int mlx5e_set_features(struct net_device *netdev,
3236 netdev_features_t features)
3237{
3238 int err;
3239
3240 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3241 set_feature_lro);
3242 err |= mlx5e_handle_feature(netdev, features,
3243 NETIF_F_HW_VLAN_CTAG_FILTER,
3244 set_feature_vlan_filter);
3245 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3246 set_feature_tc_num_filters);
94cb1ebb
EBE		 3247 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3248 set_feature_rx_all);
102722fc
GE		 3249 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3250 set_feature_rx_fcs);
36350114
GP		 3251 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3252 set_feature_rx_vlan);
45bf454a
MG		 3253#ifdef CONFIG_RFS_ACCEL
3254 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3255 set_feature_arfs);
3256#endif
0e405443
GP		 3257
3258 return err ? -EINVAL : 0;
f62b8bb8
AV		 3259}
3260
3261static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3262{
3263 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3264 struct mlx5e_channels new_channels = {};
3265 int curr_mtu;
98e81b0a 3266 int err = 0;
506753b0 3267 bool reset;
f62b8bb8 3268
f62b8bb8 3269 mutex_lock(&priv->state_lock);
98e81b0a 3270
6a9764ef
SM		 3271 reset = !priv->channels.params.lro_en &&
3272 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3273 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3274
2e20a151 3275 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3276
2e20a151 3277 curr_mtu = netdev->mtu;
f62b8bb8 3278 netdev->mtu = new_mtu;
98e81b0a 3279
2e20a151
SM		 3280 if (!reset) {
3281 mlx5e_set_dev_port_mtu(priv);
3282 goto out;
3283 }
98e81b0a 3284
2e20a151
SM		 3285 new_channels.params = priv->channels.params;
3286 err = mlx5e_open_channels(priv, &new_channels);
3287 if (err) {
3288 netdev->mtu = curr_mtu;
3289 goto out;
3290 }
3291
3292 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3293
2e20a151
SM		 3294out:
3295 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3296 return err;
3297}
3298
ef9814de
EBE		 3299static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3300{
3301 switch (cmd) {
3302 case SIOCSHWTSTAMP:
3303 return mlx5e_hwstamp_set(dev, ifr);
3304 case SIOCGHWTSTAMP:
3305 return mlx5e_hwstamp_get(dev, ifr);
3306 default:
3307 return -EOPNOTSUPP;
3308 }
3309}
3310
66e49ded
SM		 3311static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3312{
3313 struct mlx5e_priv *priv = netdev_priv(dev);
3314 struct mlx5_core_dev *mdev = priv->mdev;
3315
3316 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3317}
3318
79aab093
MS		 3319static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3320 __be16 vlan_proto)
66e49ded
SM		 3321{
3322 struct mlx5e_priv *priv = netdev_priv(dev);
3323 struct mlx5_core_dev *mdev = priv->mdev;
3324
79aab093
MS		 3325 if (vlan_proto != htons(ETH_P_8021Q))
3326 return -EPROTONOSUPPORT;
3327
66e49ded
SM		 3328 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3329 vlan, qos);
3330}
3331
f942380c
MHY		 3332static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3333{
3334 struct mlx5e_priv *priv = netdev_priv(dev);
3335 struct mlx5_core_dev *mdev = priv->mdev;
3336
3337 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3338}
3339
1edc57e2
MHY		 3340static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3341{
3342 struct mlx5e_priv *priv = netdev_priv(dev);
3343 struct mlx5_core_dev *mdev = priv->mdev;
3344
3345 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3346}
bd77bf1c
MHY		 3347
3348static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3349 int max_tx_rate)
3350{
3351 struct mlx5e_priv *priv = netdev_priv(dev);
3352 struct mlx5_core_dev *mdev = priv->mdev;
3353
bd77bf1c 3354 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3355 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3356}
3357
66e49ded
SM		 3358static int mlx5_vport_link2ifla(u8 esw_link)
3359{
3360 switch (esw_link) {
3361 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3362 return IFLA_VF_LINK_STATE_DISABLE;
3363 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3364 return IFLA_VF_LINK_STATE_ENABLE;
3365 }
3366 return IFLA_VF_LINK_STATE_AUTO;
3367}
3368
3369static int mlx5_ifla_link2vport(u8 ifla_link)
3370{
3371 switch (ifla_link) {
3372 case IFLA_VF_LINK_STATE_DISABLE:
3373 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3374 case IFLA_VF_LINK_STATE_ENABLE:
3375 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3376 }
3377 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3378}
3379
3380static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3381 int link_state)
3382{
3383 struct mlx5e_priv *priv = netdev_priv(dev);
3384 struct mlx5_core_dev *mdev = priv->mdev;
3385
3386 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3387 mlx5_ifla_link2vport(link_state));
3388}
3389
3390static int mlx5e_get_vf_config(struct net_device *dev,
3391 int vf, struct ifla_vf_info *ivi)
3392{
3393 struct mlx5e_priv *priv = netdev_priv(dev);
3394 struct mlx5_core_dev *mdev = priv->mdev;
3395 int err;
3396
3397 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3398 if (err)
3399 return err;
3400 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3401 return 0;
3402}
3403
3404static int mlx5e_get_vf_stats(struct net_device *dev,
3405 int vf, struct ifla_vf_stats *vf_stats)
3406{
3407 struct mlx5e_priv *priv = netdev_priv(dev);
3408 struct mlx5_core_dev *mdev = priv->mdev;
3409
3410 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3411 vf_stats);
3412}
3413
1ad9a00a
PB		 3414static void mlx5e_add_vxlan_port(struct net_device *netdev,
3415 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3416{
3417 struct mlx5e_priv *priv = netdev_priv(netdev);
3418
974c3f30
AD		 3419 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3420 return;
3421
b3f63c3d
MF		 3422 if (!mlx5e_vxlan_allowed(priv->mdev))
3423 return;
3424
974c3f30 3425 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3426}
3427
1ad9a00a
PB		 3428static void mlx5e_del_vxlan_port(struct net_device *netdev,
3429 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3430{
3431 struct mlx5e_priv *priv = netdev_priv(netdev);
3432
974c3f30
AD		 3433 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3434 return;
3435
b3f63c3d
MF		 3436 if (!mlx5e_vxlan_allowed(priv->mdev))
3437 return;
3438
974c3f30 3439 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3440}
3441
3442static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3443 struct sk_buff *skb,
3444 netdev_features_t features)
3445{
3446 struct udphdr *udph;
3447 u16 proto;
3448 u16 port = 0;
3449
3450 switch (vlan_get_protocol(skb)) {
3451 case htons(ETH_P_IP):
3452 proto = ip_hdr(skb)->protocol;
3453 break;
3454 case htons(ETH_P_IPV6):
3455 proto = ipv6_hdr(skb)->nexthdr;
3456 break;
3457 default:
3458 goto out;
3459 }
3460
3461 if (proto == IPPROTO_UDP) {
3462 udph = udp_hdr(skb);
3463 port = be16_to_cpu(udph->dest);
3464 }
3465
3466 /* Verify if UDP port is being offloaded by HW */
3467 if (port && mlx5e_vxlan_lookup_port(priv, port))
3468 return features;
3469
3470out:
3471 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3472 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3473}
3474
3475static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3476 struct net_device *netdev,
3477 netdev_features_t features)
3478{
3479 struct mlx5e_priv *priv = netdev_priv(netdev);
3480
3481 features = vlan_features_check(skb, features);
3482 features = vxlan_features_check(skb, features);
3483
3484 /* Validate if the tunneled packet is being offloaded by HW */
3485 if (skb->encapsulation &&
3486 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3487 return mlx5e_vxlan_features_check(priv, skb, features);
3488
3489 return features;
3490}
3491
3947ca18
DJ		 3492static void mlx5e_tx_timeout(struct net_device *dev)
3493{
3494 struct mlx5e_priv *priv = netdev_priv(dev);
3495 bool sched_work = false;
3496 int i;
3497
3498 netdev_err(dev, "TX timeout detected\n");
3499
6a9764ef 3500 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3501 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3502
2c1ccc99 3503 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3504 continue;
3505 sched_work = true;
c0f1147d 3506 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3507 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3508 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3509 }
3510
3511 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3512 schedule_work(&priv->tx_timeout_work);
3513}
3514
86994156
RS		 3515static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3516{
3517 struct mlx5e_priv *priv = netdev_priv(netdev);
3518 struct bpf_prog *old_prog;
3519 int err = 0;
3520 bool reset, was_opened;
3521 int i;
3522
3523 mutex_lock(&priv->state_lock);
3524
3525 if ((netdev->features & NETIF_F_LRO) && prog) {
3526 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3527 err = -EINVAL;
3528 goto unlock;
3529 }
3530
3531 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3532 /* no need for full reset when exchanging programs */
6a9764ef 3533 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3534
3535 if (was_opened && reset)
3536 mlx5e_close_locked(netdev);
c54c0629
DB		 3537 if (was_opened && !reset) {
3538 /* num_channels is invariant here, so we can take the
3539 * batched reference right upfront.
3540 */
6a9764ef 3541 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3542 if (IS_ERR(prog)) {
3543 err = PTR_ERR(prog);
3544 goto unlock;
3545 }
3546 }
86994156 3547
c54c0629
DB		 3548 /* exchange programs, extra prog reference we got from caller
3549 * as long as we don't fail from this point onwards.
3550 */
6a9764ef 3551 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3552 if (old_prog)
3553 bpf_prog_put(old_prog);
3554
3555 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3556 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3557
3558 if (was_opened && reset)
3559 mlx5e_open_locked(netdev);
3560
3561 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3562 goto unlock;
3563
3564 /* exchanging programs w/o reset, we update ref counts on behalf
3565 * of the channels RQs here.
3566 */
ff9c852f
SM		 3567 for (i = 0; i < priv->channels.num; i++) {
3568 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3569
c0f1147d 3570 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3571 napi_synchronize(&c->napi);
3572 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3573
3574 old_prog = xchg(&c->rq.xdp_prog, prog);
3575
c0f1147d 3576 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3577 /* napi_schedule in case we have missed anything */
3578 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3579 napi_schedule(&c->napi);
3580
3581 if (old_prog)
3582 bpf_prog_put(old_prog);
3583 }
3584
3585unlock:
3586 mutex_unlock(&priv->state_lock);
3587 return err;
3588}
3589
3590static bool mlx5e_xdp_attached(struct net_device *dev)
3591{
3592 struct mlx5e_priv *priv = netdev_priv(dev);
3593
6a9764ef 3594 return !!priv->channels.params.xdp_prog;
86994156
RS		 3595}
3596
3597static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3598{
3599 switch (xdp->command) {
3600 case XDP_SETUP_PROG:
3601 return mlx5e_xdp_set(dev, xdp->prog);
3602 case XDP_QUERY_PROG:
3603 xdp->prog_attached = mlx5e_xdp_attached(dev);
3604 return 0;
3605 default:
3606 return -EINVAL;
3607 }
3608}
3609
80378384
CO		 3610#ifdef CONFIG_NET_POLL_CONTROLLER
3611/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3612 * reenabling interrupts.
3613 */
3614static void mlx5e_netpoll(struct net_device *dev)
3615{
3616 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3617 struct mlx5e_channels *chs = &priv->channels;
3618
80378384
CO		 3619 int i;
3620
ff9c852f
SM		 3621 for (i = 0; i < chs->num; i++)
3622 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3623}
3624#endif
3625
b0eed40e 3626static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3627 .ndo_open = mlx5e_open,
3628 .ndo_stop = mlx5e_close,
3629 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3630 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3631 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3632 .ndo_get_stats64 = mlx5e_get_stats,
3633 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3634 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3635 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3636 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3637 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3638 .ndo_change_mtu = mlx5e_change_mtu,
3639 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3640 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3641#ifdef CONFIG_RFS_ACCEL
3642 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3643#endif
3947ca18 3644 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3645 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3646#ifdef CONFIG_NET_POLL_CONTROLLER
3647 .ndo_poll_controller = mlx5e_netpoll,
3648#endif
b0eed40e
SM		 3649};
3650
3651static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3652 .ndo_open = mlx5e_open,
3653 .ndo_stop = mlx5e_close,
3654 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3655 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3656 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3657 .ndo_get_stats64 = mlx5e_get_stats,
3658 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3659 .ndo_set_mac_address = mlx5e_set_mac,
3660 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3661 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3662 .ndo_set_features = mlx5e_set_features,
3663 .ndo_change_mtu = mlx5e_change_mtu,
3664 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3665 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3666 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3667 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3668 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3669#ifdef CONFIG_RFS_ACCEL
3670 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3671#endif
b0eed40e
SM		 3672 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3673 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3674 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3675 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3676 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3677 .ndo_get_vf_config = mlx5e_get_vf_config,
3678 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3679 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3680 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3681 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3682#ifdef CONFIG_NET_POLL_CONTROLLER
3683 .ndo_poll_controller = mlx5e_netpoll,
3684#endif
370bad0f
OG		 3685 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3686 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3687};
3688
3689static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3690{
3691 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3692 return -EOPNOTSUPP;
f62b8bb8
AV		 3693 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3694 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3695 !MLX5_CAP_ETH(mdev, csum_cap) ||
3696 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3697 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3698 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3699 MLX5_CAP_FLOWTABLE(mdev,
3700 flow_table_properties_nic_receive.max_ft_level)
3701 < 3) {
f62b8bb8
AV		 3702 mlx5_core_warn(mdev,
3703 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3704 return -EOPNOTSUPP;
f62b8bb8 3705 }
66189961
TT		 3706 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3707 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 3708 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 3709 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 3710
f62b8bb8
AV		 3711 return 0;
3712}
3713
58d52291
AS		 3714u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3715{
3716 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3717
3718 return bf_buf_size -
3719 sizeof(struct mlx5e_tx_wqe) +
3720 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3721}
3722
d8c9660d
TT		 3723void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3724 u32 *indirection_rqt, int len,
85082dba
TT		 3725 int num_channels)
3726{
d8c9660d
TT		 3727 int node = mdev->priv.numa_node;
3728 int node_num_of_cores;
85082dba
TT		 3729 int i;
3730
d8c9660d
TT		 3731 if (node == -1)
3732 node = first_online_node;
3733
3734 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3735
3736 if (node_num_of_cores)
3737 num_channels = min_t(int, num_channels, node_num_of_cores);
3738
85082dba
TT		 3739 for (i = 0; i < len; i++)
3740 indirection_rqt[i] = i % num_channels;
3741}
3742
b797a684
SM		 3743static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3744{
3745 enum pcie_link_width width;
3746 enum pci_bus_speed speed;
3747 int err = 0;
3748
3749 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3750 if (err)
3751 return err;
3752
3753 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3754 return -EINVAL;
3755
3756 switch (speed) {
3757 case PCIE_SPEED_2_5GT:
3758 *pci_bw = 2500 * width;
3759 break;
3760 case PCIE_SPEED_5_0GT:
3761 *pci_bw = 5000 * width;
3762 break;
3763 case PCIE_SPEED_8_0GT:
3764 *pci_bw = 8000 * width;
3765 break;
3766 default:
3767 return -EINVAL;
3768 }
3769
3770 return 0;
3771}
3772
3773static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3774{
3775 return (link_speed && pci_bw &&
3776 (pci_bw < 40000) && (pci_bw < link_speed));
3777}
3778
0f6e4cf6
EBE		 3779static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3780{
3781 return !(link_speed && pci_bw &&
3782 (pci_bw <= 16000) && (pci_bw < link_speed));
3783}
3784
9908aa29
TT		 3785void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3786{
3787 params->rx_cq_period_mode = cq_period_mode;
3788
3789 params->rx_cq_moderation.pkts =
3790 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3791 params->rx_cq_moderation.usec =
3792 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3793
3794 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3795 params->rx_cq_moderation.usec =
3796 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 3797
457fcd8a
SM		 3798 if (params->rx_am_enabled)
3799 params->rx_cq_moderation =
3800 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3801
6a9764ef
SM		 3802 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3803 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3804}
3805
2b029556
SM		 3806u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3807{
3808 int i;
3809
3810 /* The supported periods are organized in ascending order */
3811 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3812 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3813 break;
3814
3815 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3816}
3817
8f493ffd
SM		 3818void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3819 struct mlx5e_params *params,
3820 u16 max_channels)
f62b8bb8 3821{
6a9764ef 3822 u8 cq_period_mode = 0;
b797a684
SM		 3823 u32 link_speed = 0;
3824 u32 pci_bw = 0;
2fc4bfb7 3825
6a9764ef
SM		 3826 params->num_channels = max_channels;
3827 params->num_tc = 1;
2b029556 3828
0f6e4cf6
EBE		 3829 mlx5e_get_max_linkspeed(mdev, &link_speed);
3830 mlx5e_get_pci_bw(mdev, &pci_bw);
3831 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3832 link_speed, pci_bw);
3833
6a9764ef
SM		 3834 /* SQ */
3835 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3836 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3837 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3838
b797a684 3839 /* set CQE compression */
6a9764ef 3840 params->rx_cqe_compress_def = false;
b797a684 3841 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 3842 MLX5_CAP_GEN(mdev, vport_group_manager))
6a9764ef 3843 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
0f6e4cf6 3844
6a9764ef
SM		 3845 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3846
3847 /* RQ */
3848 mlx5e_set_rq_params(mdev, params);
b797a684 3849
6a9764ef 3850 /* HW LRO */
5426a0b2 3851 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 3852 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0f6e4cf6 3853 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
6a9764ef 3854 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 3855
6a9764ef
SM		 3856 /* CQ moderation params */
3857 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3858 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3859 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3860 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3861 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
9908aa29 3862
6a9764ef
SM		 3863 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3864 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
9908aa29 3865
6a9764ef
SM		 3866 /* TX inline */
3867 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3868 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3869 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
a6f402e4 3870 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
6a9764ef 3871 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
a6f402e4 3872
6a9764ef
SM		 3873 /* RSS */
3874 params->rss_hfunc = ETH_RSS_HASH_XOR;
3875 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3876 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3877 MLX5E_INDIR_RQT_SIZE, max_channels);
3878}
f62b8bb8 3879
6a9764ef
SM		 3880static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3881 struct net_device *netdev,
3882 const struct mlx5e_profile *profile,
3883 void *ppriv)
3884{
3885 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 3886
6a9764ef
SM		 3887 priv->mdev = mdev;
3888 priv->netdev = netdev;
3889 priv->profile = profile;
3890 priv->ppriv = ppriv;
2d75b2bc 3891
6a9764ef 3892 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 3893
f62b8bb8
AV		 3894 mutex_init(&priv->state_lock);
3895
3896 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3897 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3898 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3899 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3900}
3901
3902static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3903{
3904 struct mlx5e_priv *priv = netdev_priv(netdev);
3905
e1d7d349 3906 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3907 if (is_zero_ether_addr(netdev->dev_addr) &&
3908 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3909 eth_hw_addr_random(netdev);
3910 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3911 }
f62b8bb8
AV		 3912}
3913
cb67b832
HHZ		 3914static const struct switchdev_ops mlx5e_switchdev_ops = {
3915 .switchdev_port_attr_get = mlx5e_attr_get,
3916};
3917
6bfd390b 3918static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3919{
3920 struct mlx5e_priv *priv = netdev_priv(netdev);
3921 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3922 bool fcs_supported;
3923 bool fcs_enabled;
f62b8bb8
AV		 3924
3925 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3926
08fb1dac 3927 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3928 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3929#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3930 if (MLX5_CAP_GEN(mdev, qos))
3931 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3932#endif
3933 } else {
b0eed40e 3934 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3935 }
66e49ded 3936
f62b8bb8
AV		 3937 netdev->watchdog_timeo = 15 * HZ;
3938
3939 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3940
12be4b21 3941 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3942 netdev->vlan_features |= NETIF_F_IP_CSUM;
3943 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3944 netdev->vlan_features |= NETIF_F_GRO;
3945 netdev->vlan_features |= NETIF_F_TSO;
3946 netdev->vlan_features |= NETIF_F_TSO6;
3947 netdev->vlan_features |= NETIF_F_RXCSUM;
3948 netdev->vlan_features |= NETIF_F_RXHASH;
3949
3950 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3951 netdev->vlan_features |= NETIF_F_LRO;
3952
3953 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3954 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3955 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3956 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3957
b3f63c3d 3958 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3959 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3960 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3961 NETIF_F_GSO_PARTIAL;
b3f63c3d 3962 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3963 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3964 netdev->hw_enc_features |= NETIF_F_TSO;
3965 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3966 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3967 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3968 NETIF_F_GSO_PARTIAL;
3969 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3970 }
3971
94cb1ebb
EBE		 3972 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3973
3974 if (fcs_supported)
3975 netdev->hw_features |= NETIF_F_RXALL;
3976
102722fc
GE		 3977 if (MLX5_CAP_ETH(mdev, scatter_fcs))
3978 netdev->hw_features |= NETIF_F_RXFCS;
3979
f62b8bb8 3980 netdev->features = netdev->hw_features;
6a9764ef 3981 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 3982 netdev->features &= ~NETIF_F_LRO;
3983
94cb1ebb
EBE		 3984 if (fcs_enabled)
3985 netdev->features &= ~NETIF_F_RXALL;
3986
102722fc
GE		 3987 if (!priv->channels.params.scatter_fcs_en)
3988 netdev->features &= ~NETIF_F_RXFCS;
3989
e8f887ac
AV		 3990#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3991 if (FT_CAP(flow_modify_en) &&
3992 FT_CAP(modify_root) &&
3993 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3994 FT_CAP(flow_table_modify)) {
3995 netdev->hw_features |= NETIF_F_HW_TC;
3996#ifdef CONFIG_RFS_ACCEL
3997 netdev->hw_features |= NETIF_F_NTUPLE;
3998#endif
3999 }
e8f887ac 4000
f62b8bb8
AV		 4001 netdev->features |= NETIF_F_HIGHDMA;
4002
4003 netdev->priv_flags |= IFF_UNICAST_FLT;
4004
4005 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 4006
4007#ifdef CONFIG_NET_SWITCHDEV
4008 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4009 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4010#endif
f62b8bb8
AV		 4011}
4012
593cf338
RS		 4013static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4014{
4015 struct mlx5_core_dev *mdev = priv->mdev;
4016 int err;
4017
4018 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4019 if (err) {
4020 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4021 priv->q_counter = 0;
4022 }
4023}
4024
4025static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4026{
4027 if (!priv->q_counter)
4028 return;
4029
4030 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4031}
4032
6bfd390b
HHZ		 4033static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4034 struct net_device *netdev,
127ea380
HHZ		 4035 const struct mlx5e_profile *profile,
4036 void *ppriv)
6bfd390b
HHZ		 4037{
4038 struct mlx5e_priv *priv = netdev_priv(netdev);
4039
127ea380 4040 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 4041 mlx5e_build_nic_netdev(netdev);
4042 mlx5e_vxlan_init(priv);
4043}
4044
4045static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4046{
4047 mlx5e_vxlan_cleanup(priv);
127ea380 4048
6a9764ef
SM		 4049 if (priv->channels.params.xdp_prog)
4050 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 4051}
4052
4053static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4054{
4055 struct mlx5_core_dev *mdev = priv->mdev;
4056 int err;
6bfd390b 4057
8f493ffd
SM		 4058 err = mlx5e_create_indirect_rqt(priv);
4059 if (err)
6bfd390b 4060 return err;
6bfd390b
HHZ		 4061
4062 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4063 if (err)
6bfd390b 4064 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4065
4066 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4067 if (err)
6bfd390b 4068 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4069
4070 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4071 if (err)
6bfd390b 4072 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4073
4074 err = mlx5e_create_flow_steering(priv);
4075 if (err) {
4076 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4077 goto err_destroy_direct_tirs;
4078 }
4079
4080 err = mlx5e_tc_init(priv);
4081 if (err)
4082 goto err_destroy_flow_steering;
4083
4084 return 0;
4085
4086err_destroy_flow_steering:
4087 mlx5e_destroy_flow_steering(priv);
4088err_destroy_direct_tirs:
4089 mlx5e_destroy_direct_tirs(priv);
4090err_destroy_indirect_tirs:
4091 mlx5e_destroy_indirect_tirs(priv);
4092err_destroy_direct_rqts:
8f493ffd 4093 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4094err_destroy_indirect_rqts:
4095 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4096 return err;
4097}
4098
4099static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4100{
6bfd390b
HHZ		 4101 mlx5e_tc_cleanup(priv);
4102 mlx5e_destroy_flow_steering(priv);
4103 mlx5e_destroy_direct_tirs(priv);
4104 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4105 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4106 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4107}
4108
4109static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4110{
4111 int err;
4112
4113 err = mlx5e_create_tises(priv);
4114 if (err) {
4115 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4116 return err;
4117 }
4118
4119#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4120 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4121#endif
4122 return 0;
4123}
4124
4125static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4126{
4127 struct net_device *netdev = priv->netdev;
4128 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4129 u16 max_mtu;
4130
4131 mlx5e_init_l2_addr(priv);
4132
4133 /* MTU range: 68 - hw-specific max */
4134 netdev->min_mtu = ETH_MIN_MTU;
4135 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4136 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4137 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4138
7907f23a
AH		 4139 mlx5_lag_add(mdev, netdev);
4140
6bfd390b 4141 mlx5e_enable_async_events(priv);
127ea380 4142
1d447a39
SM		 4143 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4144 mlx5e_register_vport_reps(priv);
2c3b5bee 4145
610e89e0
SM		 4146 if (netdev->reg_state != NETREG_REGISTERED)
4147 return;
4148
4149 /* Device already registered: sync netdev system state */
4150 if (mlx5e_vxlan_allowed(mdev)) {
4151 rtnl_lock();
4152 udp_tunnel_get_rx_info(netdev);
4153 rtnl_unlock();
4154 }
4155
4156 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4157
4158 rtnl_lock();
4159 if (netif_running(netdev))
4160 mlx5e_open(netdev);
4161 netif_device_attach(netdev);
4162 rtnl_unlock();
6bfd390b
HHZ		 4163}
4164
4165static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4166{
3deef8ce 4167 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4168
2c3b5bee
SM		 4169 rtnl_lock();
4170 if (netif_running(priv->netdev))
4171 mlx5e_close(priv->netdev);
4172 netif_device_detach(priv->netdev);
4173 rtnl_unlock();
4174
6bfd390b 4175 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4176
3deef8ce 4177 if (MLX5_CAP_GEN(mdev, vport_group_manager))
1d447a39
SM		 4178 mlx5e_unregister_vport_reps(priv);
4179
6bfd390b 4180 mlx5e_disable_async_events(priv);
3deef8ce 4181 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4182}
4183
4184static const struct mlx5e_profile mlx5e_nic_profile = {
4185 .init = mlx5e_nic_init,
4186 .cleanup = mlx5e_nic_cleanup,
4187 .init_rx = mlx5e_init_nic_rx,
4188 .cleanup_rx = mlx5e_cleanup_nic_rx,
4189 .init_tx = mlx5e_init_nic_tx,
4190 .cleanup_tx = mlx5e_cleanup_nic_tx,
4191 .enable = mlx5e_nic_enable,
4192 .disable = mlx5e_nic_disable,
4193 .update_stats = mlx5e_update_stats,
4194 .max_nch = mlx5e_get_max_num_channels,
20fd0c19
SM		 4195 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4196 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4197 .max_tc = MLX5E_MAX_NUM_TC,
4198};
4199
2c3b5bee
SM		 4200/* mlx5e generic netdev management API (move to en_common.c) */
4201
26e59d80
MHY		 4202struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4203 const struct mlx5e_profile *profile,
4204 void *ppriv)
f62b8bb8 4205{
26e59d80 4206 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4207 struct net_device *netdev;
4208 struct mlx5e_priv *priv;
f62b8bb8 4209
08fb1dac 4210 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4211 nch * profile->max_tc,
08fb1dac 4212 nch);
f62b8bb8
AV		 4213 if (!netdev) {
4214 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4215 return NULL;
4216 }
4217
be4891af
SM		 4218#ifdef CONFIG_RFS_ACCEL
4219 netdev->rx_cpu_rmap = mdev->rmap;
4220#endif
4221
127ea380 4222 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4223
4224 netif_carrier_off(netdev);
4225
4226 priv = netdev_priv(netdev);
4227
7bb29755
MF		 4228 priv->wq = create_singlethread_workqueue("mlx5e");
4229 if (!priv->wq)
26e59d80
MHY		 4230 goto err_cleanup_nic;
4231
4232 return netdev;
4233
4234err_cleanup_nic:
4235 profile->cleanup(priv);
4236 free_netdev(netdev);
4237
4238 return NULL;
4239}
4240
2c3b5bee 4241int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4242{
2c3b5bee 4243 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4244 const struct mlx5e_profile *profile;
26e59d80
MHY		 4245 int err;
4246
26e59d80
MHY		 4247 profile = priv->profile;
4248 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4249
6bfd390b
HHZ		 4250 err = profile->init_tx(priv);
4251 if (err)
ec8b9981 4252 goto out;
5c50368f 4253
a43b25da 4254 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4255 if (err) {
4256 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4257 goto err_cleanup_tx;
5c50368f
AS		 4258 }
4259
6bfd390b
HHZ		 4260 err = profile->init_rx(priv);
4261 if (err)
5c50368f 4262 goto err_close_drop_rq;
5c50368f 4263
593cf338
RS		 4264 mlx5e_create_q_counter(priv);
4265
6bfd390b
HHZ		 4266 if (profile->enable)
4267 profile->enable(priv);
f62b8bb8 4268
26e59d80 4269 return 0;
5c50368f
AS		 4270
4271err_close_drop_rq:
a43b25da 4272 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4273
6bfd390b
HHZ		 4274err_cleanup_tx:
4275 profile->cleanup_tx(priv);
5c50368f 4276
26e59d80
MHY		 4277out:
4278 return err;
f62b8bb8
AV		 4279}
4280
2c3b5bee 4281void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4282{
26e59d80
MHY		 4283 const struct mlx5e_profile *profile = priv->profile;
4284
4285 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4286
37f304d1
SM		 4287 if (profile->disable)
4288 profile->disable(priv);
4289 flush_workqueue(priv->wq);
4290
26e59d80
MHY		 4291 mlx5e_destroy_q_counter(priv);
4292 profile->cleanup_rx(priv);
a43b25da 4293 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4294 profile->cleanup_tx(priv);
26e59d80
MHY		 4295 cancel_delayed_work_sync(&priv->update_stats_work);
4296}
4297
2c3b5bee
SM		 4298void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4299{
4300 const struct mlx5e_profile *profile = priv->profile;
4301 struct net_device *netdev = priv->netdev;
4302
4303 destroy_workqueue(priv->wq);
4304 if (profile->cleanup)
4305 profile->cleanup(priv);
4306 free_netdev(netdev);
4307}
4308
26e59d80
MHY		 4309/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4310 * hardware contexts and to connect it to the current netdev.
4311 */
4312static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4313{
4314 struct mlx5e_priv *priv = vpriv;
4315 struct net_device *netdev = priv->netdev;
4316 int err;
4317
4318 if (netif_device_present(netdev))
4319 return 0;
4320
4321 err = mlx5e_create_mdev_resources(mdev);
4322 if (err)
4323 return err;
4324
2c3b5bee 4325 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4326 if (err) {
4327 mlx5e_destroy_mdev_resources(mdev);
4328 return err;
4329 }
4330
4331 return 0;
4332}
4333
4334static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4335{
4336 struct mlx5e_priv *priv = vpriv;
4337 struct net_device *netdev = priv->netdev;
4338
4339 if (!netif_device_present(netdev))
4340 return;
4341
2c3b5bee 4342 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4343 mlx5e_destroy_mdev_resources(mdev);
4344}
4345
b50d292b
HHZ		 4346static void *mlx5e_add(struct mlx5_core_dev *mdev)
4347{
127ea380 4348 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4349 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
1d447a39 4350 struct mlx5e_rep_priv *rpriv = NULL;
26e59d80
MHY		 4351 void *priv;
4352 int vport;
4353 int err;
4354 struct net_device *netdev;
b50d292b 4355
26e59d80
MHY		 4356 err = mlx5e_check_required_hca_cap(mdev);
4357 if (err)
b50d292b
HHZ		 4358 return NULL;
4359
1d447a39
SM		 4360 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
4361 rpriv = kzalloc(sizeof(*rpriv), GFP_KERNEL);
4362 if (!rpriv) {
4363 mlx5_core_warn(mdev,
4364 "Not creating net device, Failed to alloc rep priv data\n");
4365 return NULL;
4366 }
4367 rpriv->rep = &esw->offloads.vport_reps[0];
4368 }
127ea380 4369
1d447a39 4370 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4371 if (!netdev) {
4372 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4373 goto err_unregister_reps;
4374 }
4375
4376 priv = netdev_priv(netdev);
4377
4378 err = mlx5e_attach(mdev, priv);
4379 if (err) {
4380 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4381 goto err_destroy_netdev;
4382 }
4383
4384 err = register_netdev(netdev);
4385 if (err) {
4386 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4387 goto err_detach;
b50d292b 4388 }
26e59d80
MHY		 4389
4390 return priv;
4391
4392err_detach:
4393 mlx5e_detach(mdev, priv);
4394
4395err_destroy_netdev:
2c3b5bee 4396 mlx5e_destroy_netdev(priv);
26e59d80
MHY		 4397
4398err_unregister_reps:
4399 for (vport = 1; vport < total_vfs; vport++)
4400 mlx5_eswitch_unregister_vport_rep(esw, vport);
4401
1d447a39 4402 kfree(rpriv);
26e59d80 4403 return NULL;
b50d292b
HHZ		 4404}
4405
b50d292b
HHZ		 4406static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4407{
4408 struct mlx5e_priv *priv = vpriv;
1d447a39 4409 void *ppriv = priv->ppriv;
127ea380 4410
5e1e93c7 4411 unregister_netdev(priv->netdev);
26e59d80 4412 mlx5e_detach(mdev, vpriv);
2c3b5bee 4413 mlx5e_destroy_netdev(priv);
1d447a39 4414 kfree(ppriv);
b50d292b
HHZ		 4415}
4416
f62b8bb8
AV		 4417static void *mlx5e_get_netdev(void *vpriv)
4418{
4419 struct mlx5e_priv *priv = vpriv;
4420
4421 return priv->netdev;
4422}
4423
4424static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4425 .add = mlx5e_add,
4426 .remove = mlx5e_remove,
26e59d80
MHY		 4427 .attach = mlx5e_attach,
4428 .detach = mlx5e_detach,
f62b8bb8
AV		 4429 .event = mlx5e_async_event,
4430 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4431 .get_dev = mlx5e_get_netdev,
4432};
4433
4434void mlx5e_init(void)
4435{
665bc539 4436 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4437 mlx5_register_interface(&mlx5e_interface);
4438}
4439
4440void mlx5e_cleanup(void)
4441{
4442 mlx5_unregister_interface(&mlx5e_interface);
4443}
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