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net/mlx5e: Add support for RXFCS feature flag
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac 33#include <net/tc_act/tc_gact.h>
b4e029da 34#include <linux/crash_dump.h>
e8f887ac 35#include <net/pkt_cls.h>
86d722ad 36#include <linux/mlx5/fs.h>
b3f63c3d 37#include <net/vxlan.h>
86994156 38#include <linux/bpf.h>
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
66e49ded 41#include "eswitch.h"
b3f63c3d 42#include "vxlan.h"
f62b8bb8
AV		 43
44struct mlx5e_rq_param {
cb3c7fd4
GR		 45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
9908aa29 58 u8 cq_period_mode;
f62b8bb8
AV		 59};
60
61struct mlx5e_channel_param {
62 struct mlx5e_rq_param rq;
63 struct mlx5e_sq_param sq;
b5503b99 64 struct mlx5e_sq_param xdp_sq;
d3c9bc27 65 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
d3c9bc27 68 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 69};
70
2fc4bfb7
SM		 71static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
72{
73 return MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
76}
77
6a9764ef
SM		 78void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
79 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 80{
6a9764ef
SM		 81 params->rq_wq_type = rq_type;
82 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
83 switch (params->rq_wq_type) {
2fc4bfb7 84 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 85 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 86 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
87 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 88 params->mpwqe_log_stride_sz =
89 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
90 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
91 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
92 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
93 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 94 break;
95 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 96 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 97 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
98 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
4078e637
TT		 99
100 /* Extra room needed for build_skb */
6a9764ef 101 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
4078e637 102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 103 }
2fc4bfb7 104
6a9764ef
SM		 105 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(params->log_rq_size),
108 BIT(params->mpwqe_log_stride_sz),
109 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 110}
111
6a9764ef 112static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 113{
6a9764ef
SM		 114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
115 !params->xdp_prog ?
2fc4bfb7
SM		 116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 118 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 119}
120
f62b8bb8
AV		 121static void mlx5e_update_carrier(struct mlx5e_priv *priv)
122{
123 struct mlx5_core_dev *mdev = priv->mdev;
124 u8 port_state;
125
126 port_state = mlx5_query_vport_state(mdev,
e7546514 127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 128
87424ad5
SD		 129 if (port_state == VPORT_STATE_UP) {
130 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 131 netif_carrier_on(priv->netdev);
87424ad5
SD		 132 } else {
133 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 134 netif_carrier_off(priv->netdev);
87424ad5 135 }
f62b8bb8
AV		 136}
137
138static void mlx5e_update_carrier_work(struct work_struct *work)
139{
140 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
141 update_carrier_work);
142
143 mutex_lock(&priv->state_lock);
144 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
145 mlx5e_update_carrier(priv);
146 mutex_unlock(&priv->state_lock);
147}
148
3947ca18
DJ		 149static void mlx5e_tx_timeout_work(struct work_struct *work)
150{
151 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
152 tx_timeout_work);
153 int err;
154
155 rtnl_lock();
156 mutex_lock(&priv->state_lock);
157 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
158 goto unlock;
159 mlx5e_close_locked(priv->netdev);
160 err = mlx5e_open_locked(priv->netdev);
161 if (err)
162 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
163 err);
164unlock:
165 mutex_unlock(&priv->state_lock);
166 rtnl_unlock();
167}
168
9218b44d 169static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 170{
9218b44d 171 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 172 struct mlx5e_rq_stats *rq_stats;
173 struct mlx5e_sq_stats *sq_stats;
9218b44d 174 u64 tx_offload_none = 0;
f62b8bb8
AV		 175 int i, j;
176
9218b44d 177 memset(s, 0, sizeof(*s));
ff9c852f
SM		 178 for (i = 0; i < priv->channels.num; i++) {
179 struct mlx5e_channel *c = priv->channels.c[i];
180
181 rq_stats = &c->rq.stats;
f62b8bb8 182
faf4478b
GP		 183 s->rx_packets += rq_stats->packets;
184 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 185 s->rx_lro_packets += rq_stats->lro_packets;
186 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 187 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 188 s->rx_csum_complete += rq_stats->csum_complete;
189 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 190 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 191 s->rx_xdp_tx += rq_stats->xdp_tx;
192 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 193 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 194 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 195 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 196 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
197 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 198 s->rx_cache_reuse += rq_stats->cache_reuse;
199 s->rx_cache_full += rq_stats->cache_full;
200 s->rx_cache_empty += rq_stats->cache_empty;
201 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 202
6a9764ef 203 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 204 sq_stats = &c->sq[j].stats;
f62b8bb8 205
faf4478b
GP		 206 s->tx_packets += sq_stats->packets;
207 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 208 s->tx_tso_packets += sq_stats->tso_packets;
209 s->tx_tso_bytes += sq_stats->tso_bytes;
210 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
211 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 212 s->tx_queue_stopped += sq_stats->stopped;
213 s->tx_queue_wake += sq_stats->wake;
214 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 215 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 216 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
217 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 218 }
219 }
220
9218b44d 221 /* Update calculated offload counters */
bfe6d8d1
GP		 222 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
223 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 224
bfe6d8d1 225 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 226 priv->stats.pport.phy_counters,
227 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 228}
229
230static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
231{
232 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
233 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 234 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 235 struct mlx5_core_dev *mdev = priv->mdev;
236
f62b8bb8
AV		 237 MLX5_SET(query_vport_counter_in, in, opcode,
238 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
239 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
240 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
241
242 memset(out, 0, outlen);
9218b44d
GP		 243 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
244}
245
246static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
247{
248 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
249 struct mlx5_core_dev *mdev = priv->mdev;
250 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 251 int prio;
9218b44d
GP		 252 void *out;
253 u32 *in;
254
255 in = mlx5_vzalloc(sz);
256 if (!in)
f62b8bb8
AV		 257 goto free_out;
258
9218b44d 259 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 260
9218b44d
GP		 261 out = pstats->IEEE_802_3_counters;
262 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
263 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 264
9218b44d
GP		 265 out = pstats->RFC_2863_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
268
269 out = pstats->RFC_2819_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 272
121fcdc8
GP		 273 out = pstats->phy_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276
5db0a4f6
GP		 277 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
278 out = pstats->phy_statistical_counters;
279 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
280 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
281 }
282
cf678570
GP		 283 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
284 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
285 out = pstats->per_prio_counters[prio];
286 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
287 mlx5_core_access_reg(mdev, in, sz, out, sz,
288 MLX5_REG_PPCNT, 0, 0);
289 }
290
f62b8bb8 291free_out:
9218b44d
GP		 292 kvfree(in);
293}
294
295static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
296{
297 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
298
299 if (!priv->q_counter)
300 return;
301
302 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
303 &qcnt->rx_out_of_buffer);
304}
305
0f7f3481
GP		 306static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
307{
308 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
309 struct mlx5_core_dev *mdev = priv->mdev;
310 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
311 void *out;
312 u32 *in;
313
314 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
315 return;
316
317 in = mlx5_vzalloc(sz);
318 if (!in)
319 return;
320
321 out = pcie_stats->pcie_perf_counters;
322 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
323 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
324
325 kvfree(in);
326}
327
9218b44d
GP		 328void mlx5e_update_stats(struct mlx5e_priv *priv)
329{
3dd69e3d 330 mlx5e_update_pcie_counters(priv);
9218b44d 331 mlx5e_update_pport_counters(priv);
3dd69e3d
SM		 332 mlx5e_update_vport_counters(priv);
333 mlx5e_update_q_counter(priv);
121fcdc8 334 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 335}
336
cb67b832 337void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 338{
339 struct delayed_work *dwork = to_delayed_work(work);
340 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
341 update_stats_work);
342 mutex_lock(&priv->state_lock);
343 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 344 priv->profile->update_stats(priv);
7bb29755
MF		 345 queue_delayed_work(priv->wq, dwork,
346 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 347 }
348 mutex_unlock(&priv->state_lock);
349}
350
daa21560
TT		 351static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
352 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 353{
daa21560 354 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 355 struct ptp_clock_event ptp_event;
356 struct mlx5_eqe *eqe = NULL;
daa21560 357
e0f46eb9 358 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 359 return;
360
f62b8bb8
AV		 361 switch (event) {
362 case MLX5_DEV_EVENT_PORT_UP:
363 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 364 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 365 break;
ee7f1220
EE		 366 case MLX5_DEV_EVENT_PPS:
367 eqe = (struct mlx5_eqe *)param;
368 ptp_event.type = PTP_CLOCK_EXTTS;
369 ptp_event.index = eqe->data.pps.pin;
370 ptp_event.timestamp =
371 timecounter_cyc2time(&priv->tstamp.clock,
372 be64_to_cpu(eqe->data.pps.time_stamp));
373 mlx5e_pps_event_handler(vpriv, &ptp_event);
374 break;
f62b8bb8
AV		 375 default:
376 break;
377 }
378}
379
f62b8bb8
AV		 380static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
381{
e0f46eb9 382 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 383}
384
385static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
386{
e0f46eb9 387 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 388 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 389}
390
7e426671
TT		 391static inline int mlx5e_get_wqe_mtt_sz(void)
392{
393 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
394 * To avoid copying garbage after the mtt array, we allocate
395 * a little more.
396 */
397 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
398 MLX5_UMR_MTT_ALIGNMENT);
399}
400
31391048
SM		 401static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
402 struct mlx5e_icosq *sq,
403 struct mlx5e_umr_wqe *wqe,
404 u16 ix)
7e426671
TT		 405{
406 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
407 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
408 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 409 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 410 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
411 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
412
413 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
414 ds_cnt);
415 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
416 cseg->imm = rq->mkey_be;
417
418 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 419 ucseg->xlt_octowords =
7e426671
TT		 420 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
421 ucseg->bsf_octowords =
422 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
423 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
424
425 dseg->lkey = sq->mkey_be;
426 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
427}
428
429static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
430 struct mlx5e_channel *c)
431{
432 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
433 int mtt_sz = mlx5e_get_wqe_mtt_sz();
434 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
435 int i;
436
21c59685
SM		 437 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
438 GFP_KERNEL, cpu_to_node(c->cpu));
439 if (!rq->mpwqe.info)
7e426671
TT		 440 goto err_out;
441
442 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 443 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 444 cpu_to_node(c->cpu));
21c59685 445 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 446 goto err_free_wqe_info;
447
448 for (i = 0; i < wq_sz; i++) {
21c59685 449 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 450
21c59685 451 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 452 MLX5_UMR_ALIGN);
453 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
454 PCI_DMA_TODEVICE);
455 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
456 goto err_unmap_mtts;
457
458 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
459 }
460
461 return 0;
462
463err_unmap_mtts:
464 while (--i >= 0) {
21c59685 465 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 466
467 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
468 PCI_DMA_TODEVICE);
469 }
21c59685 470 kfree(rq->mpwqe.mtt_no_align);
7e426671 471err_free_wqe_info:
21c59685 472 kfree(rq->mpwqe.info);
7e426671
TT		 473
474err_out:
475 return -ENOMEM;
476}
477
478static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
479{
480 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
481 int mtt_sz = mlx5e_get_wqe_mtt_sz();
482 int i;
483
484 for (i = 0; i < wq_sz; i++) {
21c59685 485 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 486
487 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
488 PCI_DMA_TODEVICE);
489 }
21c59685
SM		 490 kfree(rq->mpwqe.mtt_no_align);
491 kfree(rq->mpwqe.info);
7e426671
TT		 492}
493
a43b25da 494static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 495 u64 npages, u8 page_shift,
496 struct mlx5_core_mkey *umr_mkey)
3608ae77 497{
3608ae77
TT		 498 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
499 void *mkc;
500 u32 *in;
501 int err;
502
ec8b9981
TT		 503 if (!MLX5E_VALID_NUM_MTTS(npages))
504 return -EINVAL;
505
3608ae77
TT		 506 in = mlx5_vzalloc(inlen);
507 if (!in)
508 return -ENOMEM;
509
510 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
511
3608ae77
TT		 512 MLX5_SET(mkc, mkc, free, 1);
513 MLX5_SET(mkc, mkc, umr_en, 1);
514 MLX5_SET(mkc, mkc, lw, 1);
515 MLX5_SET(mkc, mkc, lr, 1);
516 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
517
518 MLX5_SET(mkc, mkc, qpn, 0xffffff);
519 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 520 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 521 MLX5_SET(mkc, mkc, translations_octword_size,
522 MLX5_MTT_OCTW(npages));
ec8b9981 523 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 524
ec8b9981 525 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 526
527 kvfree(in);
528 return err;
529}
530
a43b25da 531static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 532{
6a9764ef 533 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 534
a43b25da 535 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 536}
537
3b77235b 538static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 539 struct mlx5e_params *params,
540 struct mlx5e_rq_param *rqp,
3b77235b 541 struct mlx5e_rq *rq)
f62b8bb8 542{
a43b25da 543 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 544 void *rqc = rqp->rqc;
f62b8bb8 545 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 546 u32 byte_count;
1bfecfca
SM		 547 u32 frag_sz;
548 int npages;
f62b8bb8
AV		 549 int wq_sz;
550 int err;
551 int i;
552
6a9764ef 553 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 554
6a9764ef 555 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 556 &rq->wq_ctrl);
557 if (err)
558 return err;
559
560 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
561
562 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 563
6a9764ef 564 rq->wq_type = params->rq_wq_type;
7e426671
TT		 565 rq->pdev = c->pdev;
566 rq->netdev = c->netdev;
a43b25da 567 rq->tstamp = c->tstamp;
7e426671
TT		 568 rq->channel = c;
569 rq->ix = c->ix;
a43b25da 570 rq->mdev = mdev;
97bc402d 571
6a9764ef 572 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 573 if (IS_ERR(rq->xdp_prog)) {
574 err = PTR_ERR(rq->xdp_prog);
575 rq->xdp_prog = NULL;
576 goto err_rq_wq_destroy;
577 }
7e426671 578
d8bec2b2 579 if (rq->xdp_prog) {
b5503b99 580 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 581 rq->rx_headroom = XDP_PACKET_HEADROOM;
582 } else {
583 rq->buff.map_dir = DMA_FROM_DEVICE;
584 rq->rx_headroom = MLX5_RX_HEADROOM;
585 }
b5503b99 586
6a9764ef 587 switch (rq->wq_type) {
461017cb 588 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
a43b25da 589 if (mlx5e_is_vf_vport_rep(c->priv)) {
f5f82476
OG		 590 err = -EINVAL;
591 goto err_rq_wq_destroy;
592 }
593
461017cb
TT		 594 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
595 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 596 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 597
6a9764ef
SM		 598 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
599 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca
SM		 600
601 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
602 byte_count = rq->buff.wqe_sz;
ec8b9981 603
a43b25da 604 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 605 if (err)
606 goto err_rq_wq_destroy;
ec8b9981
TT		 607 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
608
609 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
610 if (err)
611 goto err_destroy_umr_mkey;
461017cb
TT		 612 break;
613 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 614 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
615 GFP_KERNEL, cpu_to_node(c->cpu));
616 if (!rq->dma_info) {
461017cb
TT		 617 err = -ENOMEM;
618 goto err_rq_wq_destroy;
619 }
1bfecfca 620
a43b25da 621 if (mlx5e_is_vf_vport_rep(c->priv))
f5f82476
OG		 622 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
623 else
624 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
625
461017cb 626 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 627 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 628
6a9764ef
SM		 629 rq->buff.wqe_sz = params->lro_en ?
630 params->lro_wqe_sz :
a43b25da 631 MLX5E_SW2HW_MTU(c->netdev->mtu);
1bfecfca
SM		 632 byte_count = rq->buff.wqe_sz;
633
634 /* calc the required page order */
d8bec2b2 635 frag_sz = rq->rx_headroom +
1bfecfca
SM		 636 byte_count /* packet data */ +
637 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
638 frag_sz = SKB_DATA_ALIGN(frag_sz);
639
640 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
641 rq->buff.page_order = order_base_2(npages);
642
461017cb 643 byte_count |= MLX5_HW_START_PADDING;
7e426671 644 rq->mkey_be = c->mkey_be;
461017cb 645 }
f62b8bb8
AV		 646
647 for (i = 0; i < wq_sz; i++) {
648 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
649
461017cb 650 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 651 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 652 }
653
cb3c7fd4 654 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
6a9764ef 655 rq->am.mode = params->rx_cq_period_mode;
4415a031
TT		 656 rq->page_cache.head = 0;
657 rq->page_cache.tail = 0;
658
f62b8bb8
AV		 659 return 0;
660
ec8b9981
TT		 661err_destroy_umr_mkey:
662 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
663
f62b8bb8 664err_rq_wq_destroy:
97bc402d
DB		 665 if (rq->xdp_prog)
666 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 667 mlx5_wq_destroy(&rq->wq_ctrl);
668
669 return err;
670}
671
3b77235b 672static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 673{
4415a031
TT		 674 int i;
675
86994156
RS		 676 if (rq->xdp_prog)
677 bpf_prog_put(rq->xdp_prog);
678
461017cb
TT		 679 switch (rq->wq_type) {
680 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 681 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 682 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 683 break;
684 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 685 kfree(rq->dma_info);
461017cb
TT		 686 }
687
4415a031
TT		 688 for (i = rq->page_cache.head; i != rq->page_cache.tail;
689 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
690 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
691
692 mlx5e_page_release(rq, dma_info, false);
693 }
f62b8bb8
AV		 694 mlx5_wq_destroy(&rq->wq_ctrl);
695}
696
6a9764ef
SM		 697static int mlx5e_create_rq(struct mlx5e_rq *rq,
698 struct mlx5e_rq_param *param)
f62b8bb8 699{
a43b25da 700 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 701
702 void *in;
703 void *rqc;
704 void *wq;
705 int inlen;
706 int err;
707
708 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
709 sizeof(u64) * rq->wq_ctrl.buf.npages;
710 in = mlx5_vzalloc(inlen);
711 if (!in)
712 return -ENOMEM;
713
714 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
715 wq = MLX5_ADDR_OF(rqc, rqc, wq);
716
717 memcpy(rqc, param->rqc, sizeof(param->rqc));
718
97de9f31 719 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 720 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 721 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 722 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 723 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
724
725 mlx5_fill_page_array(&rq->wq_ctrl.buf,
726 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
727
7db22ffb 728 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 729
730 kvfree(in);
731
732 return err;
733}
734
36350114
GP		 735static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
736 int next_state)
f62b8bb8
AV		 737{
738 struct mlx5e_channel *c = rq->channel;
a43b25da 739 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 740
741 void *in;
742 void *rqc;
743 int inlen;
744 int err;
745
746 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
747 in = mlx5_vzalloc(inlen);
748 if (!in)
749 return -ENOMEM;
750
751 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
752
753 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
754 MLX5_SET(rqc, rqc, state, next_state);
755
7db22ffb 756 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 757
758 kvfree(in);
759
760 return err;
761}
762
102722fc
GE		 763static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
764{
765 struct mlx5e_channel *c = rq->channel;
766 struct mlx5e_priv *priv = c->priv;
767 struct mlx5_core_dev *mdev = priv->mdev;
768
769 void *in;
770 void *rqc;
771 int inlen;
772 int err;
773
774 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
775 in = mlx5_vzalloc(inlen);
776 if (!in)
777 return -ENOMEM;
778
779 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
780
781 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
782 MLX5_SET64(modify_rq_in, in, modify_bitmask,
783 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
784 MLX5_SET(rqc, rqc, scatter_fcs, enable);
785 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
786
787 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
788
789 kvfree(in);
790
791 return err;
792}
793
36350114
GP		 794static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
795{
796 struct mlx5e_channel *c = rq->channel;
a43b25da 797 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 798 void *in;
799 void *rqc;
800 int inlen;
801 int err;
802
803 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
804 in = mlx5_vzalloc(inlen);
805 if (!in)
806 return -ENOMEM;
807
808 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
809
810 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 811 MLX5_SET64(modify_rq_in, in, modify_bitmask,
812 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 813 MLX5_SET(rqc, rqc, vsd, vsd);
814 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
815
816 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
817
818 kvfree(in);
819
820 return err;
821}
822
3b77235b 823static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 824{
a43b25da 825 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 826}
827
828static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
829{
01c196a2 830 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 831 struct mlx5e_channel *c = rq->channel;
a43b25da 832
f62b8bb8 833 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 834 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 835
01c196a2 836 while (time_before(jiffies, exp_time)) {
6a9764ef 837 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 838 return 0;
839
840 msleep(20);
841 }
842
a43b25da 843 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 844 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 845 return -ETIMEDOUT;
846}
847
f2fde18c
SM		 848static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
849{
850 struct mlx5_wq_ll *wq = &rq->wq;
851 struct mlx5e_rx_wqe *wqe;
852 __be16 wqe_ix_be;
853 u16 wqe_ix;
854
8484f9ed
SM		 855 /* UMR WQE (if in progress) is always at wq->head */
856 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 857 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 858
f2fde18c
SM		 859 while (!mlx5_wq_ll_is_empty(wq)) {
860 wqe_ix_be = *wq->tail_next;
861 wqe_ix = be16_to_cpu(wqe_ix_be);
862 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
863 rq->dealloc_wqe(rq, wqe_ix);
864 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
865 &wqe->next.next_wqe_index);
866 }
867}
868
f62b8bb8 869static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 870 struct mlx5e_params *params,
f62b8bb8
AV		 871 struct mlx5e_rq_param *param,
872 struct mlx5e_rq *rq)
873{
874 int err;
875
6a9764ef 876 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 877 if (err)
878 return err;
879
3b77235b 880 err = mlx5e_create_rq(rq, param);
f62b8bb8 881 if (err)
3b77235b 882 goto err_free_rq;
f62b8bb8 883
36350114 884 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 885 if (err)
3b77235b 886 goto err_destroy_rq;
f62b8bb8 887
6a9764ef 888 if (params->rx_am_enabled)
cb3c7fd4
GR		 889 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
890
f62b8bb8
AV		 891 return 0;
892
f62b8bb8
AV		 893err_destroy_rq:
894 mlx5e_destroy_rq(rq);
3b77235b
SM		 895err_free_rq:
896 mlx5e_free_rq(rq);
f62b8bb8
AV		 897
898 return err;
899}
900
acc6c595
SM		 901static void mlx5e_activate_rq(struct mlx5e_rq *rq)
902{
903 struct mlx5e_icosq *sq = &rq->channel->icosq;
904 u16 pi = sq->pc & sq->wq.sz_m1;
905 struct mlx5e_tx_wqe *nopwqe;
906
907 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
908 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
909 sq->db.ico_wqe[pi].num_wqebbs = 1;
910 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
911 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
912}
913
914static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 915{
c0f1147d 916 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 917 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 918}
cb3c7fd4 919
acc6c595
SM		 920static void mlx5e_close_rq(struct mlx5e_rq *rq)
921{
922 cancel_work_sync(&rq->am.work);
f62b8bb8 923 mlx5e_destroy_rq(rq);
3b77235b
SM		 924 mlx5e_free_rx_descs(rq);
925 mlx5e_free_rq(rq);
f62b8bb8
AV		 926}
927
31391048 928static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 929{
31391048 930 kfree(sq->db.di);
b5503b99
SM		 931}
932
31391048 933static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 934{
935 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
936
31391048 937 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 938 GFP_KERNEL, numa);
31391048
SM		 939 if (!sq->db.di) {
940 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 941 return -ENOMEM;
942 }
943
944 return 0;
945}
946
31391048 947static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 948 struct mlx5e_params *params,
31391048
SM		 949 struct mlx5e_sq_param *param,
950 struct mlx5e_xdpsq *sq)
951{
952 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 953 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 954 int err;
955
956 sq->pdev = c->pdev;
957 sq->mkey_be = c->mkey_be;
958 sq->channel = c;
959 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 960 sq->min_inline_mode = params->tx_min_inline_mode;
31391048
SM		 961
962 param->wq.db_numa_node = cpu_to_node(c->cpu);
963 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
964 if (err)
965 return err;
966 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
967
968 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
969 if (err)
970 goto err_sq_wq_destroy;
971
972 return 0;
973
974err_sq_wq_destroy:
975 mlx5_wq_destroy(&sq->wq_ctrl);
976
977 return err;
978}
979
980static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
981{
982 mlx5e_free_xdpsq_db(sq);
983 mlx5_wq_destroy(&sq->wq_ctrl);
984}
985
986static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 987{
f10b7cc7 988 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 989}
990
31391048 991static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 992{
993 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
994
995 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
996 GFP_KERNEL, numa);
997 if (!sq->db.ico_wqe)
998 return -ENOMEM;
999
1000 return 0;
1001}
1002
31391048 1003static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1004 struct mlx5e_sq_param *param,
1005 struct mlx5e_icosq *sq)
f10b7cc7 1006{
31391048 1007 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1008 struct mlx5_core_dev *mdev = c->mdev;
31391048 1009 int err;
f10b7cc7 1010
31391048
SM		 1011 sq->pdev = c->pdev;
1012 sq->mkey_be = c->mkey_be;
1013 sq->channel = c;
1014 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1015
31391048
SM		 1016 param->wq.db_numa_node = cpu_to_node(c->cpu);
1017 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1018 if (err)
1019 return err;
1020 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1021
31391048
SM		 1022 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1023 if (err)
1024 goto err_sq_wq_destroy;
1025
1026 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1027
1028 return 0;
31391048
SM		 1029
1030err_sq_wq_destroy:
1031 mlx5_wq_destroy(&sq->wq_ctrl);
1032
1033 return err;
f62b8bb8
AV		 1034}
1035
31391048 1036static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1037{
31391048
SM		 1038 mlx5e_free_icosq_db(sq);
1039 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1040}
1041
31391048 1042static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1043{
31391048
SM		 1044 kfree(sq->db.wqe_info);
1045 kfree(sq->db.dma_fifo);
1046 kfree(sq->db.skb);
f10b7cc7
SM		 1047}
1048
31391048 1049static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1050{
31391048
SM		 1051 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1052 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1053
1054 sq->db.skb = kzalloc_node(wq_sz * sizeof(*sq->db.skb),
1055 GFP_KERNEL, numa);
1056 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1057 GFP_KERNEL, numa);
1058 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1059 GFP_KERNEL, numa);
1060 if (!sq->db.skb || !sq->db.dma_fifo || !sq->db.wqe_info) {
1061 mlx5e_free_txqsq_db(sq);
1062 return -ENOMEM;
b5503b99 1063 }
31391048
SM		 1064
1065 sq->dma_fifo_mask = df_sz - 1;
1066
1067 return 0;
b5503b99
SM		 1068}
1069
31391048 1070static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1071 int txq_ix,
6a9764ef 1072 struct mlx5e_params *params,
31391048
SM		 1073 struct mlx5e_sq_param *param,
1074 struct mlx5e_txqsq *sq)
f62b8bb8 1075{
31391048 1076 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1077 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1078 int err;
1079
f10b7cc7 1080 sq->pdev = c->pdev;
a43b25da 1081 sq->tstamp = c->tstamp;
f10b7cc7
SM		 1082 sq->mkey_be = c->mkey_be;
1083 sq->channel = c;
acc6c595 1084 sq->txq_ix = txq_ix;
aff26157 1085 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1086 sq->max_inline = params->tx_max_inline;
1087 sq->min_inline_mode = params->tx_min_inline_mode;
f10b7cc7 1088
311c7c71 1089 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1090 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1091 if (err)
aff26157 1092 return err;
31391048 1093 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1094
31391048 1095 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1096 if (err)
f62b8bb8
AV		 1097 goto err_sq_wq_destroy;
1098
31391048 1099 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1100
1101 return 0;
1102
1103err_sq_wq_destroy:
1104 mlx5_wq_destroy(&sq->wq_ctrl);
1105
f62b8bb8
AV		 1106 return err;
1107}
1108
31391048 1109static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1110{
31391048 1111 mlx5e_free_txqsq_db(sq);
f62b8bb8 1112 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1113}
1114
33ad9711
SM		 1115struct mlx5e_create_sq_param {
1116 struct mlx5_wq_ctrl *wq_ctrl;
1117 u32 cqn;
1118 u32 tisn;
1119 u8 tis_lst_sz;
1120 u8 min_inline_mode;
1121};
1122
a43b25da 1123static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1124 struct mlx5e_sq_param *param,
1125 struct mlx5e_create_sq_param *csp,
1126 u32 *sqn)
f62b8bb8 1127{
f62b8bb8
AV		 1128 void *in;
1129 void *sqc;
1130 void *wq;
1131 int inlen;
1132 int err;
1133
1134 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1135 sizeof(u64) * csp->wq_ctrl->buf.npages;
f62b8bb8
AV		 1136 in = mlx5_vzalloc(inlen);
1137 if (!in)
1138 return -ENOMEM;
1139
1140 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1141 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1142
1143 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1144 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1145 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1146 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1147
1148 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1149 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1150
33ad9711 1151 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1152
1153 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1154 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1155 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1156 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1157 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1158
33ad9711 1159 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1160
33ad9711 1161 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1162
1163 kvfree(in);
1164
1165 return err;
1166}
1167
33ad9711
SM		 1168struct mlx5e_modify_sq_param {
1169 int curr_state;
1170 int next_state;
1171 bool rl_update;
1172 int rl_index;
1173};
1174
a43b25da 1175static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1176 struct mlx5e_modify_sq_param *p)
f62b8bb8 1177{
f62b8bb8
AV		 1178 void *in;
1179 void *sqc;
1180 int inlen;
1181 int err;
1182
1183 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1184 in = mlx5_vzalloc(inlen);
1185 if (!in)
1186 return -ENOMEM;
1187
1188 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1189
33ad9711
SM		 1190 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1191 MLX5_SET(sqc, sqc, state, p->next_state);
1192 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1193 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1194 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1195 }
f62b8bb8 1196
33ad9711 1197 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1198
1199 kvfree(in);
1200
1201 return err;
1202}
1203
a43b25da 1204static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1205{
a43b25da 1206 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1207}
1208
a43b25da 1209static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1210 struct mlx5e_sq_param *param,
1211 struct mlx5e_create_sq_param *csp,
1212 u32 *sqn)
f62b8bb8 1213{
33ad9711 1214 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1215 int err;
1216
a43b25da 1217 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1218 if (err)
1219 return err;
1220
1221 msp.curr_state = MLX5_SQC_STATE_RST;
1222 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1223 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1224 if (err)
a43b25da 1225 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1226
1227 return err;
1228}
1229
7f859ecf
SM		 1230static int mlx5e_set_sq_maxrate(struct net_device *dev,
1231 struct mlx5e_txqsq *sq, u32 rate);
1232
31391048 1233static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1234 u32 tisn,
acc6c595 1235 int txq_ix,
6a9764ef 1236 struct mlx5e_params *params,
31391048
SM		 1237 struct mlx5e_sq_param *param,
1238 struct mlx5e_txqsq *sq)
1239{
1240 struct mlx5e_create_sq_param csp = {};
7f859ecf 1241 u32 tx_rate;
f62b8bb8
AV		 1242 int err;
1243
6a9764ef 1244 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1245 if (err)
1246 return err;
1247
a43b25da 1248 csp.tisn = tisn;
31391048 1249 csp.tis_lst_sz = 1;
33ad9711
SM		 1250 csp.cqn = sq->cq.mcq.cqn;
1251 csp.wq_ctrl = &sq->wq_ctrl;
1252 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1253 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1254 if (err)
31391048 1255 goto err_free_txqsq;
f62b8bb8 1256
a43b25da 1257 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1258 if (tx_rate)
a43b25da 1259 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1260
f62b8bb8
AV		 1261 return 0;
1262
31391048 1263err_free_txqsq:
3b77235b 1264 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1265 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1266
1267 return err;
1268}
1269
acc6c595
SM		 1270static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1271{
a43b25da 1272 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1273 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1274 netdev_tx_reset_queue(sq->txq);
1275 netif_tx_start_queue(sq->txq);
1276}
1277
f62b8bb8
AV		 1278static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1279{
1280 __netif_tx_lock_bh(txq);
1281 netif_tx_stop_queue(txq);
1282 __netif_tx_unlock_bh(txq);
1283}
1284
acc6c595 1285static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1286{
33ad9711 1287 struct mlx5e_channel *c = sq->channel;
33ad9711 1288
c0f1147d 1289 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1290 /* prevent netif_tx_wake_queue */
33ad9711 1291 napi_synchronize(&c->napi);
29429f33 1292
31391048 1293 netif_tx_disable_queue(sq->txq);
f62b8bb8 1294
31391048
SM		 1295 /* last doorbell out, godspeed .. */
1296 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1297 struct mlx5e_tx_wqe *nop;
864b2d71 1298
31391048
SM		 1299 sq->db.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1300 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1301 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1302 }
acc6c595
SM		 1303}
1304
1305static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1306{
1307 struct mlx5e_channel *c = sq->channel;
a43b25da 1308 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1309
a43b25da 1310 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1311 if (sq->rate_limit)
1312 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1313 mlx5e_free_txqsq_descs(sq);
1314 mlx5e_free_txqsq(sq);
1315}
1316
1317static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1318 struct mlx5e_params *params,
31391048
SM		 1319 struct mlx5e_sq_param *param,
1320 struct mlx5e_icosq *sq)
1321{
1322 struct mlx5e_create_sq_param csp = {};
1323 int err;
1324
6a9764ef 1325 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1326 if (err)
1327 return err;
1328
1329 csp.cqn = sq->cq.mcq.cqn;
1330 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1331 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1332 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1333 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1334 if (err)
1335 goto err_free_icosq;
1336
1337 return 0;
1338
1339err_free_icosq:
1340 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1341 mlx5e_free_icosq(sq);
1342
1343 return err;
1344}
1345
1346static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1347{
1348 struct mlx5e_channel *c = sq->channel;
1349
1350 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351 napi_synchronize(&c->napi);
1352
a43b25da 1353 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1354 mlx5e_free_icosq(sq);
1355}
1356
1357static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1358 struct mlx5e_params *params,
31391048
SM		 1359 struct mlx5e_sq_param *param,
1360 struct mlx5e_xdpsq *sq)
1361{
1362 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1363 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1364 unsigned int inline_hdr_sz = 0;
1365 int err;
1366 int i;
1367
6a9764ef 1368 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1369 if (err)
1370 return err;
1371
1372 csp.tis_lst_sz = 1;
a43b25da 1373 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1374 csp.cqn = sq->cq.mcq.cqn;
1375 csp.wq_ctrl = &sq->wq_ctrl;
1376 csp.min_inline_mode = sq->min_inline_mode;
1377 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1378 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1379 if (err)
1380 goto err_free_xdpsq;
1381
1382 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1383 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1384 ds_cnt++;
1385 }
1386
1387 /* Pre initialize fixed WQE fields */
1388 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1389 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1390 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1391 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1392 struct mlx5_wqe_data_seg *dseg;
1393
1394 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1395 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1396
1397 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1398 dseg->lkey = sq->mkey_be;
1399 }
1400
1401 return 0;
1402
1403err_free_xdpsq:
1404 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1405 mlx5e_free_xdpsq(sq);
1406
1407 return err;
1408}
1409
1410static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1411{
1412 struct mlx5e_channel *c = sq->channel;
1413
1414 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1415 napi_synchronize(&c->napi);
1416
a43b25da 1417 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1418 mlx5e_free_xdpsq_descs(sq);
1419 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1420}
1421
3b77235b
SM		 1422static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1423 struct mlx5e_cq_param *param,
1424 struct mlx5e_cq *cq)
f62b8bb8 1425{
a43b25da 1426 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1427 struct mlx5_core_cq *mcq = &cq->mcq;
1428 int eqn_not_used;
0b6e26ce 1429 unsigned int irqn;
f62b8bb8
AV		 1430 int err;
1431 u32 i;
1432
311c7c71
SM		 1433 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1434 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1435 param->eq_ix = c->ix;
1436
1437 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1438 &cq->wq_ctrl);
1439 if (err)
1440 return err;
1441
1442 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1443
1444 cq->napi = &c->napi;
1445
1446 mcq->cqe_sz = 64;
1447 mcq->set_ci_db = cq->wq_ctrl.db.db;
1448 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1449 *mcq->set_ci_db = 0;
1450 *mcq->arm_db = 0;
1451 mcq->vector = param->eq_ix;
1452 mcq->comp = mlx5e_completion_event;
1453 mcq->event = mlx5e_cq_error_event;
1454 mcq->irqn = irqn;
f62b8bb8
AV		 1455
1456 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1457 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1458
1459 cqe->op_own = 0xf1;
1460 }
1461
1462 cq->channel = c;
a43b25da 1463 cq->mdev = mdev;
f62b8bb8
AV		 1464
1465 return 0;
1466}
1467
3b77235b 1468static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1469{
1c1b5228 1470 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1471}
1472
3b77235b 1473static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1474{
a43b25da 1475 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1476 struct mlx5_core_cq *mcq = &cq->mcq;
1477
1478 void *in;
1479 void *cqc;
1480 int inlen;
0b6e26ce 1481 unsigned int irqn_not_used;
f62b8bb8
AV		 1482 int eqn;
1483 int err;
1484
1485 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1486 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1487 in = mlx5_vzalloc(inlen);
1488 if (!in)
1489 return -ENOMEM;
1490
1491 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1492
1493 memcpy(cqc, param->cqc, sizeof(param->cqc));
1494
1c1b5228
TT		 1495 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1496 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1497
1498 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1499
9908aa29 1500 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1501 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1502 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1503 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1504 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1505 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1506
1507 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1508
1509 kvfree(in);
1510
1511 if (err)
1512 return err;
1513
1514 mlx5e_cq_arm(cq);
1515
1516 return 0;
1517}
1518
3b77235b 1519static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1520{
a43b25da 1521 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1522}
1523
1524static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1525 struct mlx5e_cq_moder moder,
f62b8bb8 1526 struct mlx5e_cq_param *param,
6a9764ef 1527 struct mlx5e_cq *cq)
f62b8bb8 1528{
a43b25da 1529 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1530 int err;
f62b8bb8 1531
3b77235b 1532 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1533 if (err)
1534 return err;
1535
3b77235b 1536 err = mlx5e_create_cq(cq, param);
f62b8bb8 1537 if (err)
3b77235b 1538 goto err_free_cq;
f62b8bb8 1539
7524a5d8 1540 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1541 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1542 return 0;
1543
3b77235b
SM		 1544err_free_cq:
1545 mlx5e_free_cq(cq);
f62b8bb8
AV		 1546
1547 return err;
1548}
1549
1550static void mlx5e_close_cq(struct mlx5e_cq *cq)
1551{
f62b8bb8 1552 mlx5e_destroy_cq(cq);
3b77235b 1553 mlx5e_free_cq(cq);
f62b8bb8
AV		 1554}
1555
1556static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1557{
1558 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1559}
1560
1561static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1562 struct mlx5e_params *params,
f62b8bb8
AV		 1563 struct mlx5e_channel_param *cparam)
1564{
f62b8bb8
AV		 1565 int err;
1566 int tc;
1567
1568 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1569 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1570 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1571 if (err)
1572 goto err_close_tx_cqs;
f62b8bb8
AV		 1573 }
1574
1575 return 0;
1576
1577err_close_tx_cqs:
1578 for (tc--; tc >= 0; tc--)
1579 mlx5e_close_cq(&c->sq[tc].cq);
1580
1581 return err;
1582}
1583
1584static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1585{
1586 int tc;
1587
1588 for (tc = 0; tc < c->num_tc; tc++)
1589 mlx5e_close_cq(&c->sq[tc].cq);
1590}
1591
1592static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1593 struct mlx5e_params *params,
f62b8bb8
AV		 1594 struct mlx5e_channel_param *cparam)
1595{
1596 int err;
1597 int tc;
1598
6a9764ef
SM		 1599 for (tc = 0; tc < params->num_tc; tc++) {
1600 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1601
a43b25da
SM		 1602 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1603 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1604 if (err)
1605 goto err_close_sqs;
1606 }
1607
1608 return 0;
1609
1610err_close_sqs:
1611 for (tc--; tc >= 0; tc--)
31391048 1612 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1613
1614 return err;
1615}
1616
1617static void mlx5e_close_sqs(struct mlx5e_channel *c)
1618{
1619 int tc;
1620
1621 for (tc = 0; tc < c->num_tc; tc++)
31391048 1622 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1623}
1624
507f0c81 1625static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1626 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1627{
1628 struct mlx5e_priv *priv = netdev_priv(dev);
1629 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1630 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1631 u16 rl_index = 0;
1632 int err;
1633
1634 if (rate == sq->rate_limit)
1635 /* nothing to do */
1636 return 0;
1637
1638 if (sq->rate_limit)
1639 /* remove current rl index to free space to next ones */
1640 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1641
1642 sq->rate_limit = 0;
1643
1644 if (rate) {
1645 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1646 if (err) {
1647 netdev_err(dev, "Failed configuring rate %u: %d\n",
1648 rate, err);
1649 return err;
1650 }
1651 }
1652
33ad9711
SM		 1653 msp.curr_state = MLX5_SQC_STATE_RDY;
1654 msp.next_state = MLX5_SQC_STATE_RDY;
1655 msp.rl_index = rl_index;
1656 msp.rl_update = true;
a43b25da 1657 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1658 if (err) {
1659 netdev_err(dev, "Failed configuring rate %u: %d\n",
1660 rate, err);
1661 /* remove the rate from the table */
1662 if (rate)
1663 mlx5_rl_remove_rate(mdev, rate);
1664 return err;
1665 }
1666
1667 sq->rate_limit = rate;
1668 return 0;
1669}
1670
1671static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1672{
1673 struct mlx5e_priv *priv = netdev_priv(dev);
1674 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1675 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1676 int err = 0;
1677
1678 if (!mlx5_rl_is_supported(mdev)) {
1679 netdev_err(dev, "Rate limiting is not supported on this device\n");
1680 return -EINVAL;
1681 }
1682
1683 /* rate is given in Mb/sec, HW config is in Kb/sec */
1684 rate = rate << 10;
1685
1686 /* Check whether rate in valid range, 0 is always valid */
1687 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1688 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1689 return -ERANGE;
1690 }
1691
1692 mutex_lock(&priv->state_lock);
1693 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1694 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1695 if (!err)
1696 priv->tx_rates[index] = rate;
1697 mutex_unlock(&priv->state_lock);
1698
1699 return err;
1700}
1701
b4e029da
KH		 1702static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
1703{
1704 return is_kdump_kernel() ?
1705 MLX5E_MIN_NUM_CHANNELS :
1706 min_t(int, mdev->priv.eq_table.num_comp_vectors,
1707 MLX5E_MAX_NUM_CHANNELS);
1708}
1709
f62b8bb8 1710static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1711 struct mlx5e_params *params,
f62b8bb8
AV		 1712 struct mlx5e_channel_param *cparam,
1713 struct mlx5e_channel **cp)
1714{
6a9764ef 1715 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8
AV		 1716 struct net_device *netdev = priv->netdev;
1717 int cpu = mlx5e_get_cpu(priv, ix);
1718 struct mlx5e_channel *c;
1719 int err;
1720
1721 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1722 if (!c)
1723 return -ENOMEM;
1724
1725 c->priv = priv;
a43b25da
SM		 1726 c->mdev = priv->mdev;
1727 c->tstamp = &priv->tstamp;
f62b8bb8
AV		 1728 c->ix = ix;
1729 c->cpu = cpu;
1730 c->pdev = &priv->mdev->pdev->dev;
1731 c->netdev = priv->netdev;
b50d292b 1732 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1733 c->num_tc = params->num_tc;
1734 c->xdp = !!params->xdp_prog;
cb3c7fd4 1735
f62b8bb8
AV		 1736 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1737
6a9764ef 1738 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1739 if (err)
1740 goto err_napi_del;
1741
6a9764ef 1742 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1743 if (err)
1744 goto err_close_icosq_cq;
1745
6a9764ef 1746 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1747 if (err)
1748 goto err_close_tx_cqs;
f62b8bb8 1749
d7a0ecab 1750 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1751 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1752 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1753 if (err)
1754 goto err_close_rx_cq;
1755
f62b8bb8
AV		 1756 napi_enable(&c->napi);
1757
6a9764ef 1758 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1759 if (err)
1760 goto err_disable_napi;
1761
6a9764ef 1762 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1763 if (err)
1764 goto err_close_icosq;
1765
6a9764ef 1766 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1767 if (err)
1768 goto err_close_sqs;
b5503b99 1769
6a9764ef 1770 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1771 if (err)
b5503b99 1772 goto err_close_xdp_sq;
f62b8bb8 1773
f62b8bb8
AV		 1774 *cp = c;
1775
1776 return 0;
b5503b99 1777err_close_xdp_sq:
d7a0ecab 1778 if (c->xdp)
31391048 1779 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1780
1781err_close_sqs:
1782 mlx5e_close_sqs(c);
1783
d3c9bc27 1784err_close_icosq:
31391048 1785 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1786
f62b8bb8
AV		 1787err_disable_napi:
1788 napi_disable(&c->napi);
d7a0ecab 1789 if (c->xdp)
31871f87 1790 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1791
1792err_close_rx_cq:
f62b8bb8
AV		 1793 mlx5e_close_cq(&c->rq.cq);
1794
1795err_close_tx_cqs:
1796 mlx5e_close_tx_cqs(c);
1797
d3c9bc27
TT		 1798err_close_icosq_cq:
1799 mlx5e_close_cq(&c->icosq.cq);
1800
f62b8bb8
AV		 1801err_napi_del:
1802 netif_napi_del(&c->napi);
1803 kfree(c);
1804
1805 return err;
1806}
1807
acc6c595
SM		 1808static void mlx5e_activate_channel(struct mlx5e_channel *c)
1809{
1810 int tc;
1811
1812 for (tc = 0; tc < c->num_tc; tc++)
1813 mlx5e_activate_txqsq(&c->sq[tc]);
1814 mlx5e_activate_rq(&c->rq);
a43b25da 1815 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1816}
1817
1818static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1819{
1820 int tc;
1821
1822 mlx5e_deactivate_rq(&c->rq);
1823 for (tc = 0; tc < c->num_tc; tc++)
1824 mlx5e_deactivate_txqsq(&c->sq[tc]);
1825}
1826
f62b8bb8
AV		 1827static void mlx5e_close_channel(struct mlx5e_channel *c)
1828{
1829 mlx5e_close_rq(&c->rq);
b5503b99 1830 if (c->xdp)
31391048 1831 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1832 mlx5e_close_sqs(c);
31391048 1833 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1834 napi_disable(&c->napi);
b5503b99 1835 if (c->xdp)
31871f87 1836 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1837 mlx5e_close_cq(&c->rq.cq);
1838 mlx5e_close_tx_cqs(c);
d3c9bc27 1839 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1840 netif_napi_del(&c->napi);
7ae92ae5 1841
f62b8bb8
AV		 1842 kfree(c);
1843}
1844
1845static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1846 struct mlx5e_params *params,
f62b8bb8
AV		 1847 struct mlx5e_rq_param *param)
1848{
1849 void *rqc = param->rqc;
1850 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1851
6a9764ef 1852 switch (params->rq_wq_type) {
461017cb 1853 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1854 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1855 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1856 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1857 break;
1858 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1859 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1860 }
1861
f62b8bb8
AV		 1862 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1863 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1864 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1865 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1866 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1867 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1868 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1869
311c7c71 1870 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1871 param->wq.linear = 1;
1872}
1873
556dd1b9
TT		 1874static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1875{
1876 void *rqc = param->rqc;
1877 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1878
1879 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1880 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1881}
1882
d3c9bc27
TT		 1883static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1884 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1885{
1886 void *sqc = param->sqc;
1887 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1888
f62b8bb8 1889 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1890 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1891
311c7c71 1892 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1893}
1894
1895static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1896 struct mlx5e_params *params,
d3c9bc27
TT		 1897 struct mlx5e_sq_param *param)
1898{
1899 void *sqc = param->sqc;
1900 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1901
1902 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1903 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
f62b8bb8
AV		 1904}
1905
1906static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1907 struct mlx5e_cq_param *param)
1908{
1909 void *cqc = param->cqc;
1910
30aa60b3 1911 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1912}
1913
1914static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1915 struct mlx5e_params *params,
f62b8bb8
AV		 1916 struct mlx5e_cq_param *param)
1917{
1918 void *cqc = param->cqc;
461017cb 1919 u8 log_cq_size;
f62b8bb8 1920
6a9764ef 1921 switch (params->rq_wq_type) {
461017cb 1922 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1923 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1924 break;
1925 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1926 log_cq_size = params->log_rq_size;
461017cb
TT		 1927 }
1928
1929 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1930 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1931 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1932 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1933 }
f62b8bb8
AV		 1934
1935 mlx5e_build_common_cq_param(priv, param);
9908aa29 1936
6a9764ef
SM		 1937 if (params->rx_am_enabled)
1938 params->rx_cq_moderation =
1939 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
f62b8bb8
AV		 1940}
1941
1942static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1943 struct mlx5e_params *params,
f62b8bb8
AV		 1944 struct mlx5e_cq_param *param)
1945{
1946 void *cqc = param->cqc;
1947
6a9764ef 1948 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1949
1950 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1951
1952 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1953}
1954
d3c9bc27 1955static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1956 u8 log_wq_size,
1957 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1958{
1959 void *cqc = param->cqc;
1960
1961 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1962
1963 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1964
1965 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1966}
1967
1968static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1969 u8 log_wq_size,
1970 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1971{
1972 void *sqc = param->sqc;
1973 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1974
1975 mlx5e_build_sq_param_common(priv, param);
1976
1977 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1978 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1979}
1980
b5503b99 1981static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1982 struct mlx5e_params *params,
b5503b99
SM		 1983 struct mlx5e_sq_param *param)
1984{
1985 void *sqc = param->sqc;
1986 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1987
1988 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1989 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1990}
1991
6a9764ef
SM		 1992static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1993 struct mlx5e_params *params,
1994 struct mlx5e_channel_param *cparam)
f62b8bb8 1995{
bc77b240 1996 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1997
6a9764ef
SM		 1998 mlx5e_build_rq_param(priv, params, &cparam->rq);
1999 mlx5e_build_sq_param(priv, params, &cparam->sq);
2000 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2001 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2002 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2003 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2004 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2005}
2006
55c2503d
SM		 2007int mlx5e_open_channels(struct mlx5e_priv *priv,
2008 struct mlx5e_channels *chs)
f62b8bb8 2009{
6b87663f 2010 struct mlx5e_channel_param *cparam;
03289b88 2011 int err = -ENOMEM;
f62b8bb8 2012 int i;
f62b8bb8 2013
6a9764ef 2014 chs->num = chs->params.num_channels;
03289b88 2015
ff9c852f 2016 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2017 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2018 if (!chs->c || !cparam)
2019 goto err_free;
f62b8bb8 2020
6a9764ef 2021 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2022 for (i = 0; i < chs->num; i++) {
6a9764ef 2023 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2024 if (err)
2025 goto err_close_channels;
2026 }
2027
6b87663f 2028 kfree(cparam);
f62b8bb8
AV		 2029 return 0;
2030
2031err_close_channels:
2032 for (i--; i >= 0; i--)
ff9c852f 2033 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2034
acc6c595 2035err_free:
ff9c852f 2036 kfree(chs->c);
6b87663f 2037 kfree(cparam);
ff9c852f 2038 chs->num = 0;
f62b8bb8
AV		 2039 return err;
2040}
2041
acc6c595 2042static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2043{
2044 int i;
2045
acc6c595
SM		 2046 for (i = 0; i < chs->num; i++)
2047 mlx5e_activate_channel(chs->c[i]);
2048}
2049
2050static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2051{
2052 int err = 0;
2053 int i;
2054
2055 for (i = 0; i < chs->num; i++) {
2056 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2057 if (err)
2058 break;
2059 }
2060
2061 return err;
2062}
2063
2064static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2065{
2066 int i;
2067
2068 for (i = 0; i < chs->num; i++)
2069 mlx5e_deactivate_channel(chs->c[i]);
2070}
2071
55c2503d 2072void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2073{
2074 int i;
c3b7c5c9 2075
ff9c852f
SM		 2076 for (i = 0; i < chs->num; i++)
2077 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2078
ff9c852f
SM		 2079 kfree(chs->c);
2080 chs->num = 0;
f62b8bb8
AV		 2081}
2082
a5f97fee
SM		 2083static int
2084mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2085{
2086 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2087 void *rqtc;
2088 int inlen;
2089 int err;
1da36696 2090 u32 *in;
a5f97fee 2091 int i;
f62b8bb8 2092
f62b8bb8
AV		 2093 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2094 in = mlx5_vzalloc(inlen);
2095 if (!in)
2096 return -ENOMEM;
2097
2098 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2099
2100 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2101 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2102
a5f97fee
SM		 2103 for (i = 0; i < sz; i++)
2104 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2105
398f3351
HHZ		 2106 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2107 if (!err)
2108 rqt->enabled = true;
f62b8bb8
AV		 2109
2110 kvfree(in);
1da36696
TT		 2111 return err;
2112}
2113
cb67b832 2114void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2115{
398f3351
HHZ		 2116 rqt->enabled = false;
2117 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2118}
2119
6bfd390b
HHZ		 2120static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
2121{
2122 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2123
a5f97fee 2124 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
6bfd390b
HHZ		 2125}
2126
cb67b832 2127int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2128{
398f3351 2129 struct mlx5e_rqt *rqt;
1da36696
TT		 2130 int err;
2131 int ix;
2132
6bfd390b 2133 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2134 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2135 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2136 if (err)
2137 goto err_destroy_rqts;
2138 }
2139
2140 return 0;
2141
2142err_destroy_rqts:
2143 for (ix--; ix >= 0; ix--)
398f3351 2144 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2145
f62b8bb8
AV		 2146 return err;
2147}
2148
a5f97fee
SM		 2149static int mlx5e_rx_hash_fn(int hfunc)
2150{
2151 return (hfunc == ETH_RSS_HASH_TOP) ?
2152 MLX5_RX_HASH_FN_TOEPLITZ :
2153 MLX5_RX_HASH_FN_INVERTED_XOR8;
2154}
2155
2156static int mlx5e_bits_invert(unsigned long a, int size)
2157{
2158 int inv = 0;
2159 int i;
2160
2161 for (i = 0; i < size; i++)
2162 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2163
2164 return inv;
2165}
2166
2167static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2168 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2169{
2170 int i;
2171
2172 for (i = 0; i < sz; i++) {
2173 u32 rqn;
2174
2175 if (rrp.is_rss) {
2176 int ix = i;
2177
2178 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2179 ix = mlx5e_bits_invert(i, ilog2(sz));
2180
6a9764ef 2181 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2182 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2183 } else {
2184 rqn = rrp.rqn;
2185 }
2186 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2187 }
2188}
2189
2190int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2191 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2192{
2193 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2194 void *rqtc;
2195 int inlen;
1da36696 2196 u32 *in;
5c50368f
AS		 2197 int err;
2198
5c50368f
AS		 2199 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2200 in = mlx5_vzalloc(inlen);
2201 if (!in)
2202 return -ENOMEM;
2203
2204 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2205
2206 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2207 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2208 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2209 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2210
2211 kvfree(in);
5c50368f
AS		 2212 return err;
2213}
2214
a5f97fee
SM		 2215static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2216 struct mlx5e_redirect_rqt_param rrp)
2217{
2218 if (!rrp.is_rss)
2219 return rrp.rqn;
2220
2221 if (ix >= rrp.rss.channels->num)
2222 return priv->drop_rq.rqn;
2223
2224 return rrp.rss.channels->c[ix]->rq.rqn;
2225}
2226
2227static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2228 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2229{
1da36696
TT		 2230 u32 rqtn;
2231 int ix;
2232
398f3351 2233 if (priv->indir_rqt.enabled) {
a5f97fee 2234 /* RSS RQ table */
398f3351 2235 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2236 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2237 }
2238
a5f97fee
SM		 2239 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2240 struct mlx5e_redirect_rqt_param direct_rrp = {
2241 .is_rss = false,
95632791
AM		 2242 {
2243 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2244 },
a5f97fee
SM		 2245 };
2246
2247 /* Direct RQ Tables */
398f3351
HHZ		 2248 if (!priv->direct_tir[ix].rqt.enabled)
2249 continue;
a5f97fee 2250
398f3351 2251 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2252 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2253 }
40ab6a6e
AS		 2254}
2255
a5f97fee
SM		 2256static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2257 struct mlx5e_channels *chs)
2258{
2259 struct mlx5e_redirect_rqt_param rrp = {
2260 .is_rss = true,
95632791
AM		 2261 {
2262 .rss = {
2263 .channels = chs,
2264 .hfunc = chs->params.rss_hfunc,
2265 }
2266 },
a5f97fee
SM		 2267 };
2268
2269 mlx5e_redirect_rqts(priv, rrp);
2270}
2271
2272static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2273{
2274 struct mlx5e_redirect_rqt_param drop_rrp = {
2275 .is_rss = false,
95632791
AM		 2276 {
2277 .rqn = priv->drop_rq.rqn,
2278 },
a5f97fee
SM		 2279 };
2280
2281 mlx5e_redirect_rqts(priv, drop_rrp);
2282}
2283
6a9764ef 2284static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2285{
6a9764ef 2286 if (!params->lro_en)
5c50368f
AS		 2287 return;
2288
2289#define ROUGH_MAX_L2_L3_HDR_SZ 256
2290
2291 MLX5_SET(tirc, tirc, lro_enable_mask,
2292 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2293 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2294 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2295 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2296 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2297}
2298
6a9764ef
SM		 2299void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2300 enum mlx5e_traffic_types tt,
2301 void *tirc)
bdfc028d 2302{
a100ff3e
GP		 2303 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2304
2305#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2306 MLX5_HASH_FIELD_SEL_DST_IP)
2307
2308#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2309 MLX5_HASH_FIELD_SEL_DST_IP |\
2310 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2311 MLX5_HASH_FIELD_SEL_L4_DPORT)
2312
2313#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2314 MLX5_HASH_FIELD_SEL_DST_IP |\
2315 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2316
6a9764ef
SM		 2317 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2318 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2319 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2320 rx_hash_toeplitz_key);
2321 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2322 rx_hash_toeplitz_key);
2323
2324 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2325 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2326 }
a100ff3e
GP		 2327
2328 switch (tt) {
2329 case MLX5E_TT_IPV4_TCP:
2330 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2331 MLX5_L3_PROT_TYPE_IPV4);
2332 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2333 MLX5_L4_PROT_TYPE_TCP);
2334 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2335 MLX5_HASH_IP_L4PORTS);
2336 break;
2337
2338 case MLX5E_TT_IPV6_TCP:
2339 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2340 MLX5_L3_PROT_TYPE_IPV6);
2341 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2342 MLX5_L4_PROT_TYPE_TCP);
2343 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2344 MLX5_HASH_IP_L4PORTS);
2345 break;
2346
2347 case MLX5E_TT_IPV4_UDP:
2348 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2349 MLX5_L3_PROT_TYPE_IPV4);
2350 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2351 MLX5_L4_PROT_TYPE_UDP);
2352 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2353 MLX5_HASH_IP_L4PORTS);
2354 break;
2355
2356 case MLX5E_TT_IPV6_UDP:
2357 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2358 MLX5_L3_PROT_TYPE_IPV6);
2359 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2360 MLX5_L4_PROT_TYPE_UDP);
2361 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2362 MLX5_HASH_IP_L4PORTS);
2363 break;
2364
2365 case MLX5E_TT_IPV4_IPSEC_AH:
2366 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2367 MLX5_L3_PROT_TYPE_IPV4);
2368 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2369 MLX5_HASH_IP_IPSEC_SPI);
2370 break;
2371
2372 case MLX5E_TT_IPV6_IPSEC_AH:
2373 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2374 MLX5_L3_PROT_TYPE_IPV6);
2375 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2376 MLX5_HASH_IP_IPSEC_SPI);
2377 break;
2378
2379 case MLX5E_TT_IPV4_IPSEC_ESP:
2380 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2381 MLX5_L3_PROT_TYPE_IPV4);
2382 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2383 MLX5_HASH_IP_IPSEC_SPI);
2384 break;
2385
2386 case MLX5E_TT_IPV6_IPSEC_ESP:
2387 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2388 MLX5_L3_PROT_TYPE_IPV6);
2389 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2390 MLX5_HASH_IP_IPSEC_SPI);
2391 break;
2392
2393 case MLX5E_TT_IPV4:
2394 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2395 MLX5_L3_PROT_TYPE_IPV4);
2396 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2397 MLX5_HASH_IP);
2398 break;
2399
2400 case MLX5E_TT_IPV6:
2401 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2402 MLX5_L3_PROT_TYPE_IPV6);
2403 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2404 MLX5_HASH_IP);
2405 break;
2406 default:
2407 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2408 }
bdfc028d
TT		 2409}
2410
ab0394fe 2411static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2412{
2413 struct mlx5_core_dev *mdev = priv->mdev;
2414
2415 void *in;
2416 void *tirc;
2417 int inlen;
2418 int err;
ab0394fe 2419 int tt;
1da36696 2420 int ix;
5c50368f
AS		 2421
2422 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2423 in = mlx5_vzalloc(inlen);
2424 if (!in)
2425 return -ENOMEM;
2426
2427 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2428 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2429
6a9764ef 2430 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2431
1da36696 2432 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2433 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2434 inlen);
ab0394fe 2435 if (err)
1da36696 2436 goto free_in;
ab0394fe 2437 }
5c50368f 2438
6bfd390b 2439 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2440 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2441 in, inlen);
2442 if (err)
2443 goto free_in;
2444 }
2445
2446free_in:
5c50368f
AS		 2447 kvfree(in);
2448
2449 return err;
2450}
2451
cd255eff 2452static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2453{
40ab6a6e 2454 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2455 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2456 int err;
2457
cd255eff 2458 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2459 if (err)
2460 return err;
2461
cd255eff
SM		 2462 /* Update vport context MTU */
2463 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2464 return 0;
2465}
40ab6a6e 2466
cd255eff
SM		 2467static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2468{
2469 struct mlx5_core_dev *mdev = priv->mdev;
2470 u16 hw_mtu = 0;
2471 int err;
40ab6a6e 2472
cd255eff
SM		 2473 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2474 if (err || !hw_mtu) /* fallback to port oper mtu */
2475 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2476
2477 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2478}
2479
2e20a151 2480static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2481{
2e20a151 2482 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2483 u16 mtu;
2484 int err;
2485
2486 err = mlx5e_set_mtu(priv, netdev->mtu);
2487 if (err)
2488 return err;
40ab6a6e 2489
cd255eff
SM		 2490 mlx5e_query_mtu(priv, &mtu);
2491 if (mtu != netdev->mtu)
2492 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2493 __func__, mtu, netdev->mtu);
40ab6a6e 2494
cd255eff 2495 netdev->mtu = mtu;
40ab6a6e
AS		 2496 return 0;
2497}
2498
08fb1dac
SM		 2499static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2500{
2501 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2502 int nch = priv->channels.params.num_channels;
2503 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2504 int tc;
2505
2506 netdev_reset_tc(netdev);
2507
2508 if (ntc == 1)
2509 return;
2510
2511 netdev_set_num_tc(netdev, ntc);
2512
7ccdd084
RS		 2513 /* Map netdev TCs to offset 0
2514 * We have our own UP to TXQ mapping for QoS
2515 */
08fb1dac 2516 for (tc = 0; tc < ntc; tc++)
7ccdd084 2517 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2518}
2519
acc6c595
SM		 2520static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2521{
2522 struct mlx5e_channel *c;
2523 struct mlx5e_txqsq *sq;
2524 int i, tc;
2525
2526 for (i = 0; i < priv->channels.num; i++)
2527 for (tc = 0; tc < priv->profile->max_tc; tc++)
2528 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2529
2530 for (i = 0; i < priv->channels.num; i++) {
2531 c = priv->channels.c[i];
2532 for (tc = 0; tc < c->num_tc; tc++) {
2533 sq = &c->sq[tc];
2534 priv->txq2sq[sq->txq_ix] = sq;
2535 }
2536 }
2537}
2538
2539static void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2540{
9008ae07
SM		 2541 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2542 struct net_device *netdev = priv->netdev;
2543
2544 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2545 netif_set_real_num_tx_queues(netdev, num_txqs);
2546 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2547
acc6c595
SM		 2548 mlx5e_build_channels_tx_maps(priv);
2549 mlx5e_activate_channels(&priv->channels);
2550 netif_tx_start_all_queues(priv->netdev);
9008ae07
SM		 2551
2552 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager))
2553 mlx5e_add_sqs_fwd_rules(priv);
2554
acc6c595 2555 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2556 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2557}
2558
2559static void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2560{
9008ae07
SM		 2561 mlx5e_redirect_rqts_to_drop(priv);
2562
2563 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager))
2564 mlx5e_remove_sqs_fwd_rules(priv);
2565
acc6c595
SM		 2566 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2567 * polling for inactive tx queues.
2568 */
2569 netif_tx_stop_all_queues(priv->netdev);
2570 netif_tx_disable(priv->netdev);
2571 mlx5e_deactivate_channels(&priv->channels);
2572}
2573
55c2503d 2574void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2575 struct mlx5e_channels *new_chs,
2576 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2577{
2578 struct net_device *netdev = priv->netdev;
2579 int new_num_txqs;
2580
2581 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2582
2583 netif_carrier_off(netdev);
2584
2585 if (new_num_txqs < netdev->real_num_tx_queues)
2586 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2587
2588 mlx5e_deactivate_priv_channels(priv);
2589 mlx5e_close_channels(&priv->channels);
2590
2591 priv->channels = *new_chs;
2592
2e20a151
SM		 2593 /* New channels are ready to roll, modify HW settings if needed */
2594 if (hw_modify)
2595 hw_modify(priv);
2596
55c2503d
SM		 2597 mlx5e_refresh_tirs(priv, false);
2598 mlx5e_activate_priv_channels(priv);
2599
2600 mlx5e_update_carrier(priv);
2601}
2602
40ab6a6e
AS		 2603int mlx5e_open_locked(struct net_device *netdev)
2604{
2605 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2606 int err;
2607
2608 set_bit(MLX5E_STATE_OPENED, &priv->state);
2609
ff9c852f 2610 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2611 if (err)
343b29f3 2612 goto err_clear_state_opened_flag;
40ab6a6e 2613
b676f653 2614 mlx5e_refresh_tirs(priv, false);
acc6c595 2615 mlx5e_activate_priv_channels(priv);
ce89ef36 2616 mlx5e_update_carrier(priv);
ef9814de 2617 mlx5e_timestamp_init(priv);
be4891af 2618
cb67b832
HHZ		 2619 if (priv->profile->update_stats)
2620 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2621
9b37b07f 2622 return 0;
343b29f3
AS		 2623
2624err_clear_state_opened_flag:
2625 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2626 return err;
40ab6a6e
AS		 2627}
2628
cb67b832 2629int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2630{
2631 struct mlx5e_priv *priv = netdev_priv(netdev);
2632 int err;
2633
2634 mutex_lock(&priv->state_lock);
2635 err = mlx5e_open_locked(netdev);
2636 mutex_unlock(&priv->state_lock);
2637
2638 return err;
2639}
2640
2641int mlx5e_close_locked(struct net_device *netdev)
2642{
2643 struct mlx5e_priv *priv = netdev_priv(netdev);
2644
a1985740
AS		 2645 /* May already be CLOSED in case a previous configuration operation
2646 * (e.g RX/TX queue size change) that involves close&open failed.
2647 */
2648 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2649 return 0;
2650
40ab6a6e
AS		 2651 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2652
ef9814de 2653 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2654 netif_carrier_off(priv->netdev);
acc6c595
SM		 2655 mlx5e_deactivate_priv_channels(priv);
2656 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2657
2658 return 0;
2659}
2660
cb67b832 2661int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2662{
2663 struct mlx5e_priv *priv = netdev_priv(netdev);
2664 int err;
2665
26e59d80
MHY		 2666 if (!netif_device_present(netdev))
2667 return -ENODEV;
2668
40ab6a6e
AS		 2669 mutex_lock(&priv->state_lock);
2670 err = mlx5e_close_locked(netdev);
2671 mutex_unlock(&priv->state_lock);
2672
2673 return err;
2674}
2675
a43b25da 2676static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2677 struct mlx5e_rq *rq,
2678 struct mlx5e_rq_param *param)
40ab6a6e 2679{
40ab6a6e
AS		 2680 void *rqc = param->rqc;
2681 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2682 int err;
2683
2684 param->wq.db_numa_node = param->wq.buf_numa_node;
2685
2686 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2687 &rq->wq_ctrl);
2688 if (err)
2689 return err;
2690
a43b25da 2691 rq->mdev = mdev;
40ab6a6e
AS		 2692
2693 return 0;
2694}
2695
a43b25da 2696static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2697 struct mlx5e_cq *cq,
2698 struct mlx5e_cq_param *param)
40ab6a6e 2699{
40ab6a6e
AS		 2700 struct mlx5_core_cq *mcq = &cq->mcq;
2701 int eqn_not_used;
0b6e26ce 2702 unsigned int irqn;
40ab6a6e
AS		 2703 int err;
2704
2705 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2706 &cq->wq_ctrl);
2707 if (err)
2708 return err;
2709
2710 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2711
2712 mcq->cqe_sz = 64;
2713 mcq->set_ci_db = cq->wq_ctrl.db.db;
2714 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2715 *mcq->set_ci_db = 0;
2716 *mcq->arm_db = 0;
2717 mcq->vector = param->eq_ix;
2718 mcq->comp = mlx5e_completion_event;
2719 mcq->event = mlx5e_cq_error_event;
2720 mcq->irqn = irqn;
40ab6a6e 2721
a43b25da 2722 cq->mdev = mdev;
40ab6a6e
AS		 2723
2724 return 0;
2725}
2726
a43b25da
SM		 2727static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2728 struct mlx5e_rq *drop_rq)
40ab6a6e 2729{
a43b25da
SM		 2730 struct mlx5e_cq_param cq_param = {};
2731 struct mlx5e_rq_param rq_param = {};
2732 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2733 int err;
2734
556dd1b9 2735 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2736
a43b25da 2737 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2738 if (err)
2739 return err;
2740
3b77235b 2741 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2742 if (err)
3b77235b 2743 goto err_free_cq;
40ab6a6e 2744
a43b25da 2745 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2746 if (err)
3b77235b 2747 goto err_destroy_cq;
40ab6a6e 2748
a43b25da 2749 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2750 if (err)
3b77235b 2751 goto err_free_rq;
40ab6a6e
AS		 2752
2753 return 0;
2754
3b77235b 2755err_free_rq:
a43b25da 2756 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2757
2758err_destroy_cq:
a43b25da 2759 mlx5e_destroy_cq(cq);
40ab6a6e 2760
3b77235b 2761err_free_cq:
a43b25da 2762 mlx5e_free_cq(cq);
3b77235b 2763
40ab6a6e
AS		 2764 return err;
2765}
2766
a43b25da 2767static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2768{
a43b25da
SM		 2769 mlx5e_destroy_rq(drop_rq);
2770 mlx5e_free_rq(drop_rq);
2771 mlx5e_destroy_cq(&drop_rq->cq);
2772 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2773}
2774
2775static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2776{
2777 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2778 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2779 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2780
08fb1dac 2781 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2782 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2783
2784 if (mlx5_lag_is_lacp_owner(mdev))
2785 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2786
40ab6a6e
AS		 2787 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2788}
2789
2790static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2791{
2792 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2793}
2794
cb67b832 2795int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2796{
2797 int err;
2798 int tc;
2799
6bfd390b 2800 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2801 err = mlx5e_create_tis(priv, tc);
2802 if (err)
2803 goto err_close_tises;
2804 }
2805
2806 return 0;
2807
2808err_close_tises:
2809 for (tc--; tc >= 0; tc--)
2810 mlx5e_destroy_tis(priv, tc);
2811
2812 return err;
2813}
2814
cb67b832 2815void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2816{
2817 int tc;
2818
6bfd390b 2819 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2820 mlx5e_destroy_tis(priv, tc);
2821}
2822
6a9764ef
SM		 2823static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2824 enum mlx5e_traffic_types tt,
2825 u32 *tirc)
f62b8bb8 2826{
b50d292b 2827 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2828
6a9764ef 2829 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2830
4cbeaff5 2831 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2832 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
6a9764ef 2833 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
f62b8bb8
AV		 2834}
2835
6a9764ef 2836static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2837{
b50d292b 2838 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2839
6a9764ef 2840 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2841
2842 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2843 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2844 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2845}
2846
6bfd390b 2847static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2848{
724b2aa1 2849 struct mlx5e_tir *tir;
f62b8bb8
AV		 2850 void *tirc;
2851 int inlen;
2852 int err;
1da36696 2853 u32 *in;
1da36696 2854 int tt;
f62b8bb8
AV		 2855
2856 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2857 in = mlx5_vzalloc(inlen);
2858 if (!in)
2859 return -ENOMEM;
2860
1da36696
TT		 2861 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2862 memset(in, 0, inlen);
724b2aa1 2863 tir = &priv->indir_tir[tt];
1da36696 2864 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2865 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2866 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2867 if (err)
40ab6a6e 2868 goto err_destroy_tirs;
f62b8bb8
AV		 2869 }
2870
6bfd390b
HHZ		 2871 kvfree(in);
2872
2873 return 0;
2874
2875err_destroy_tirs:
2876 for (tt--; tt >= 0; tt--)
2877 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2878
2879 kvfree(in);
2880
2881 return err;
2882}
2883
cb67b832 2884int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2885{
2886 int nch = priv->profile->max_nch(priv->mdev);
2887 struct mlx5e_tir *tir;
2888 void *tirc;
2889 int inlen;
2890 int err;
2891 u32 *in;
2892 int ix;
2893
2894 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2895 in = mlx5_vzalloc(inlen);
2896 if (!in)
2897 return -ENOMEM;
2898
1da36696
TT		 2899 for (ix = 0; ix < nch; ix++) {
2900 memset(in, 0, inlen);
724b2aa1 2901 tir = &priv->direct_tir[ix];
1da36696 2902 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2903 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2904 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2905 if (err)
2906 goto err_destroy_ch_tirs;
2907 }
2908
2909 kvfree(in);
2910
f62b8bb8
AV		 2911 return 0;
2912
1da36696
TT		 2913err_destroy_ch_tirs:
2914 for (ix--; ix >= 0; ix--)
724b2aa1 2915 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2916
1da36696 2917 kvfree(in);
f62b8bb8
AV		 2918
2919 return err;
2920}
2921
6bfd390b 2922static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2923{
2924 int i;
2925
1da36696 2926 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2927 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2928}
2929
cb67b832 2930void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2931{
2932 int nch = priv->profile->max_nch(priv->mdev);
2933 int i;
2934
2935 for (i = 0; i < nch; i++)
2936 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2937}
2938
102722fc
GE		 2939static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2940{
2941 int err = 0;
2942 int i;
2943
2944 for (i = 0; i < chs->num; i++) {
2945 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2946 if (err)
2947 return err;
2948 }
2949
2950 return 0;
2951}
2952
ff9c852f 2953int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2954{
2955 int err = 0;
2956 int i;
2957
ff9c852f
SM		 2958 for (i = 0; i < chs->num; i++) {
2959 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2960 if (err)
2961 return err;
2962 }
2963
2964 return 0;
2965}
2966
08fb1dac
SM		 2967static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2968{
2969 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 2970 struct mlx5e_channels new_channels = {};
08fb1dac
SM		 2971 int err = 0;
2972
2973 if (tc && tc != MLX5E_MAX_NUM_TC)
2974 return -EINVAL;
2975
2976 mutex_lock(&priv->state_lock);
2977
6f9485af
SM		 2978 new_channels.params = priv->channels.params;
2979 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 2980
6f9485af
SM		 2981 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
2982 priv->channels.params = new_channels.params;
2983 goto out;
2984 }
08fb1dac 2985
6f9485af
SM		 2986 err = mlx5e_open_channels(priv, &new_channels);
2987 if (err)
2988 goto out;
08fb1dac 2989
2e20a151 2990 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 2991out:
08fb1dac 2992 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 2993 return err;
2994}
2995
2996static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2997 __be16 proto, struct tc_to_netdev *tc)
2998{
e8f887ac
AV		 2999 struct mlx5e_priv *priv = netdev_priv(dev);
3000
3001 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
3002 goto mqprio;
3003
3004 switch (tc->type) {
e3a2b7ed
AV		 3005 case TC_SETUP_CLSFLOWER:
3006 switch (tc->cls_flower->command) {
3007 case TC_CLSFLOWER_REPLACE:
3008 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
3009 case TC_CLSFLOWER_DESTROY:
3010 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 3011 case TC_CLSFLOWER_STATS:
3012 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 3013 }
e8f887ac
AV		 3014 default:
3015 return -EOPNOTSUPP;
3016 }
3017
3018mqprio:
67ba422e 3019 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 3020 return -EINVAL;
3021
56f36acd
AN		 3022 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3023
3024 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
08fb1dac
SM		 3025}
3026
bc1f4470 3027static void
f62b8bb8
AV		 3028mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3029{
3030 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3031 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3032 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3033 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3034
370bad0f
OG		 3035 if (mlx5e_is_uplink_rep(priv)) {
3036 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3037 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3038 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3039 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3040 } else {
3041 stats->rx_packets = sstats->rx_packets;
3042 stats->rx_bytes = sstats->rx_bytes;
3043 stats->tx_packets = sstats->tx_packets;
3044 stats->tx_bytes = sstats->tx_bytes;
3045 stats->tx_dropped = sstats->tx_queue_dropped;
3046 }
269e6b3a
GP		 3047
3048 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3049
3050 stats->rx_length_errors =
9218b44d
GP		 3051 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3052 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3053 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3054 stats->rx_crc_errors =
9218b44d
GP		 3055 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3056 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3057 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 3058 stats->tx_carrier_errors =
9218b44d 3059 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 3060 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3061 stats->rx_frame_errors;
3062 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3063
3064 /* vport multicast also counts packets that are dropped due to steering
3065 * or rx out of buffer
3066 */
9218b44d
GP		 3067 stats->multicast =
3068 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8 3069
f62b8bb8
AV		 3070}
3071
3072static void mlx5e_set_rx_mode(struct net_device *dev)
3073{
3074 struct mlx5e_priv *priv = netdev_priv(dev);
3075
7bb29755 3076 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3077}
3078
3079static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3080{
3081 struct mlx5e_priv *priv = netdev_priv(netdev);
3082 struct sockaddr *saddr = addr;
3083
3084 if (!is_valid_ether_addr(saddr->sa_data))
3085 return -EADDRNOTAVAIL;
3086
3087 netif_addr_lock_bh(netdev);
3088 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3089 netif_addr_unlock_bh(netdev);
3090
7bb29755 3091 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3092
3093 return 0;
3094}
3095
0e405443
GP		 3096#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3097 do { \
3098 if (enable) \
3099 netdev->features |= feature; \
3100 else \
3101 netdev->features &= ~feature; \
3102 } while (0)
3103
3104typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3105
3106static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3107{
3108 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3109 struct mlx5e_channels new_channels = {};
3110 int err = 0;
3111 bool reset;
f62b8bb8
AV		 3112
3113 mutex_lock(&priv->state_lock);
f62b8bb8 3114
2e20a151
SM		 3115 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3116 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3117
2e20a151
SM		 3118 new_channels.params = priv->channels.params;
3119 new_channels.params.lro_en = enable;
3120
3121 if (!reset) {
3122 priv->channels.params = new_channels.params;
3123 err = mlx5e_modify_tirs_lro(priv);
3124 goto out;
98e81b0a 3125 }
f62b8bb8 3126
2e20a151
SM		 3127 err = mlx5e_open_channels(priv, &new_channels);
3128 if (err)
3129 goto out;
0e405443 3130
2e20a151
SM		 3131 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3132out:
9b37b07f 3133 mutex_unlock(&priv->state_lock);
0e405443
GP		 3134 return err;
3135}
3136
3137static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3138{
3139 struct mlx5e_priv *priv = netdev_priv(netdev);
3140
3141 if (enable)
3142 mlx5e_enable_vlan_filter(priv);
3143 else
3144 mlx5e_disable_vlan_filter(priv);
3145
3146 return 0;
3147}
3148
3149static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3150{
3151 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3152
0e405443 3153 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3154 netdev_err(netdev,
3155 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3156 return -EINVAL;
3157 }
3158
0e405443
GP		 3159 return 0;
3160}
3161
94cb1ebb
EBE		 3162static int set_feature_rx_all(struct net_device *netdev, bool enable)
3163{
3164 struct mlx5e_priv *priv = netdev_priv(netdev);
3165 struct mlx5_core_dev *mdev = priv->mdev;
3166
3167 return mlx5_set_port_fcs(mdev, !enable);
3168}
3169
102722fc
GE		 3170static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3171{
3172 struct mlx5e_priv *priv = netdev_priv(netdev);
3173 int err;
3174
3175 mutex_lock(&priv->state_lock);
3176
3177 priv->channels.params.scatter_fcs_en = enable;
3178 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3179 if (err)
3180 priv->channels.params.scatter_fcs_en = !enable;
3181
3182 mutex_unlock(&priv->state_lock);
3183
3184 return err;
3185}
3186
36350114
GP		 3187static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3188{
3189 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3190 int err = 0;
36350114
GP		 3191
3192 mutex_lock(&priv->state_lock);
3193
6a9764ef 3194 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3195 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3196 goto unlock;
3197
3198 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3199 if (err)
6a9764ef 3200 priv->channels.params.vlan_strip_disable = enable;
36350114 3201
ff9c852f 3202unlock:
36350114
GP		 3203 mutex_unlock(&priv->state_lock);
3204
3205 return err;
3206}
3207
45bf454a
MG		 3208#ifdef CONFIG_RFS_ACCEL
3209static int set_feature_arfs(struct net_device *netdev, bool enable)
3210{
3211 struct mlx5e_priv *priv = netdev_priv(netdev);
3212 int err;
3213
3214 if (enable)
3215 err = mlx5e_arfs_enable(priv);
3216 else
3217 err = mlx5e_arfs_disable(priv);
3218
3219 return err;
3220}
3221#endif
3222
0e405443
GP		 3223static int mlx5e_handle_feature(struct net_device *netdev,
3224 netdev_features_t wanted_features,
3225 netdev_features_t feature,
3226 mlx5e_feature_handler feature_handler)
3227{
3228 netdev_features_t changes = wanted_features ^ netdev->features;
3229 bool enable = !!(wanted_features & feature);
3230 int err;
3231
3232 if (!(changes & feature))
3233 return 0;
3234
3235 err = feature_handler(netdev, enable);
3236 if (err) {
3237 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3238 enable ? "Enable" : "Disable", feature, err);
3239 return err;
3240 }
3241
3242 MLX5E_SET_FEATURE(netdev, feature, enable);
3243 return 0;
3244}
3245
3246static int mlx5e_set_features(struct net_device *netdev,
3247 netdev_features_t features)
3248{
3249 int err;
3250
3251 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3252 set_feature_lro);
3253 err |= mlx5e_handle_feature(netdev, features,
3254 NETIF_F_HW_VLAN_CTAG_FILTER,
3255 set_feature_vlan_filter);
3256 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3257 set_feature_tc_num_filters);
94cb1ebb
EBE		 3258 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3259 set_feature_rx_all);
102722fc
GE		 3260 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3261 set_feature_rx_fcs);
36350114
GP		 3262 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3263 set_feature_rx_vlan);
45bf454a
MG		 3264#ifdef CONFIG_RFS_ACCEL
3265 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3266 set_feature_arfs);
3267#endif
0e405443
GP		 3268
3269 return err ? -EINVAL : 0;
f62b8bb8
AV		 3270}
3271
3272static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3273{
3274 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3275 struct mlx5e_channels new_channels = {};
3276 int curr_mtu;
98e81b0a 3277 int err = 0;
506753b0 3278 bool reset;
f62b8bb8 3279
f62b8bb8 3280 mutex_lock(&priv->state_lock);
98e81b0a 3281
6a9764ef
SM		 3282 reset = !priv->channels.params.lro_en &&
3283 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3284 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3285
2e20a151 3286 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3287
2e20a151 3288 curr_mtu = netdev->mtu;
f62b8bb8 3289 netdev->mtu = new_mtu;
98e81b0a 3290
2e20a151
SM		 3291 if (!reset) {
3292 mlx5e_set_dev_port_mtu(priv);
3293 goto out;
3294 }
98e81b0a 3295
2e20a151
SM		 3296 new_channels.params = priv->channels.params;
3297 err = mlx5e_open_channels(priv, &new_channels);
3298 if (err) {
3299 netdev->mtu = curr_mtu;
3300 goto out;
3301 }
3302
3303 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3304
2e20a151
SM		 3305out:
3306 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3307 return err;
3308}
3309
ef9814de
EBE		 3310static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3311{
3312 switch (cmd) {
3313 case SIOCSHWTSTAMP:
3314 return mlx5e_hwstamp_set(dev, ifr);
3315 case SIOCGHWTSTAMP:
3316 return mlx5e_hwstamp_get(dev, ifr);
3317 default:
3318 return -EOPNOTSUPP;
3319 }
3320}
3321
66e49ded
SM		 3322static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3323{
3324 struct mlx5e_priv *priv = netdev_priv(dev);
3325 struct mlx5_core_dev *mdev = priv->mdev;
3326
3327 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3328}
3329
79aab093
MS		 3330static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3331 __be16 vlan_proto)
66e49ded
SM		 3332{
3333 struct mlx5e_priv *priv = netdev_priv(dev);
3334 struct mlx5_core_dev *mdev = priv->mdev;
3335
79aab093
MS		 3336 if (vlan_proto != htons(ETH_P_8021Q))
3337 return -EPROTONOSUPPORT;
3338
66e49ded
SM		 3339 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3340 vlan, qos);
3341}
3342
f942380c
MHY		 3343static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3344{
3345 struct mlx5e_priv *priv = netdev_priv(dev);
3346 struct mlx5_core_dev *mdev = priv->mdev;
3347
3348 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3349}
3350
1edc57e2
MHY		 3351static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3352{
3353 struct mlx5e_priv *priv = netdev_priv(dev);
3354 struct mlx5_core_dev *mdev = priv->mdev;
3355
3356 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3357}
bd77bf1c
MHY		 3358
3359static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3360 int max_tx_rate)
3361{
3362 struct mlx5e_priv *priv = netdev_priv(dev);
3363 struct mlx5_core_dev *mdev = priv->mdev;
3364
bd77bf1c 3365 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3366 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3367}
3368
66e49ded
SM		 3369static int mlx5_vport_link2ifla(u8 esw_link)
3370{
3371 switch (esw_link) {
3372 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3373 return IFLA_VF_LINK_STATE_DISABLE;
3374 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3375 return IFLA_VF_LINK_STATE_ENABLE;
3376 }
3377 return IFLA_VF_LINK_STATE_AUTO;
3378}
3379
3380static int mlx5_ifla_link2vport(u8 ifla_link)
3381{
3382 switch (ifla_link) {
3383 case IFLA_VF_LINK_STATE_DISABLE:
3384 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3385 case IFLA_VF_LINK_STATE_ENABLE:
3386 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3387 }
3388 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3389}
3390
3391static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3392 int link_state)
3393{
3394 struct mlx5e_priv *priv = netdev_priv(dev);
3395 struct mlx5_core_dev *mdev = priv->mdev;
3396
3397 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3398 mlx5_ifla_link2vport(link_state));
3399}
3400
3401static int mlx5e_get_vf_config(struct net_device *dev,
3402 int vf, struct ifla_vf_info *ivi)
3403{
3404 struct mlx5e_priv *priv = netdev_priv(dev);
3405 struct mlx5_core_dev *mdev = priv->mdev;
3406 int err;
3407
3408 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3409 if (err)
3410 return err;
3411 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3412 return 0;
3413}
3414
3415static int mlx5e_get_vf_stats(struct net_device *dev,
3416 int vf, struct ifla_vf_stats *vf_stats)
3417{
3418 struct mlx5e_priv *priv = netdev_priv(dev);
3419 struct mlx5_core_dev *mdev = priv->mdev;
3420
3421 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3422 vf_stats);
3423}
3424
1ad9a00a
PB		 3425static void mlx5e_add_vxlan_port(struct net_device *netdev,
3426 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3427{
3428 struct mlx5e_priv *priv = netdev_priv(netdev);
3429
974c3f30
AD		 3430 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3431 return;
3432
b3f63c3d
MF		 3433 if (!mlx5e_vxlan_allowed(priv->mdev))
3434 return;
3435
974c3f30 3436 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3437}
3438
1ad9a00a
PB		 3439static void mlx5e_del_vxlan_port(struct net_device *netdev,
3440 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3441{
3442 struct mlx5e_priv *priv = netdev_priv(netdev);
3443
974c3f30
AD		 3444 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3445 return;
3446
b3f63c3d
MF		 3447 if (!mlx5e_vxlan_allowed(priv->mdev))
3448 return;
3449
974c3f30 3450 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3451}
3452
3453static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3454 struct sk_buff *skb,
3455 netdev_features_t features)
3456{
3457 struct udphdr *udph;
3458 u16 proto;
3459 u16 port = 0;
3460
3461 switch (vlan_get_protocol(skb)) {
3462 case htons(ETH_P_IP):
3463 proto = ip_hdr(skb)->protocol;
3464 break;
3465 case htons(ETH_P_IPV6):
3466 proto = ipv6_hdr(skb)->nexthdr;
3467 break;
3468 default:
3469 goto out;
3470 }
3471
3472 if (proto == IPPROTO_UDP) {
3473 udph = udp_hdr(skb);
3474 port = be16_to_cpu(udph->dest);
3475 }
3476
3477 /* Verify if UDP port is being offloaded by HW */
3478 if (port && mlx5e_vxlan_lookup_port(priv, port))
3479 return features;
3480
3481out:
3482 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3483 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3484}
3485
3486static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3487 struct net_device *netdev,
3488 netdev_features_t features)
3489{
3490 struct mlx5e_priv *priv = netdev_priv(netdev);
3491
3492 features = vlan_features_check(skb, features);
3493 features = vxlan_features_check(skb, features);
3494
3495 /* Validate if the tunneled packet is being offloaded by HW */
3496 if (skb->encapsulation &&
3497 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3498 return mlx5e_vxlan_features_check(priv, skb, features);
3499
3500 return features;
3501}
3502
3947ca18
DJ		 3503static void mlx5e_tx_timeout(struct net_device *dev)
3504{
3505 struct mlx5e_priv *priv = netdev_priv(dev);
3506 bool sched_work = false;
3507 int i;
3508
3509 netdev_err(dev, "TX timeout detected\n");
3510
6a9764ef 3511 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3512 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3513
2c1ccc99 3514 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3515 continue;
3516 sched_work = true;
c0f1147d 3517 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3518 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3519 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3520 }
3521
3522 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3523 schedule_work(&priv->tx_timeout_work);
3524}
3525
86994156
RS		 3526static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3527{
3528 struct mlx5e_priv *priv = netdev_priv(netdev);
3529 struct bpf_prog *old_prog;
3530 int err = 0;
3531 bool reset, was_opened;
3532 int i;
3533
3534 mutex_lock(&priv->state_lock);
3535
3536 if ((netdev->features & NETIF_F_LRO) && prog) {
3537 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3538 err = -EINVAL;
3539 goto unlock;
3540 }
3541
3542 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3543 /* no need for full reset when exchanging programs */
6a9764ef 3544 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3545
3546 if (was_opened && reset)
3547 mlx5e_close_locked(netdev);
c54c0629
DB		 3548 if (was_opened && !reset) {
3549 /* num_channels is invariant here, so we can take the
3550 * batched reference right upfront.
3551 */
6a9764ef 3552 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3553 if (IS_ERR(prog)) {
3554 err = PTR_ERR(prog);
3555 goto unlock;
3556 }
3557 }
86994156 3558
c54c0629
DB		 3559 /* exchange programs, extra prog reference we got from caller
3560 * as long as we don't fail from this point onwards.
3561 */
6a9764ef 3562 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3563 if (old_prog)
3564 bpf_prog_put(old_prog);
3565
3566 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3567 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3568
3569 if (was_opened && reset)
3570 mlx5e_open_locked(netdev);
3571
3572 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3573 goto unlock;
3574
3575 /* exchanging programs w/o reset, we update ref counts on behalf
3576 * of the channels RQs here.
3577 */
ff9c852f
SM		 3578 for (i = 0; i < priv->channels.num; i++) {
3579 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3580
c0f1147d 3581 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3582 napi_synchronize(&c->napi);
3583 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3584
3585 old_prog = xchg(&c->rq.xdp_prog, prog);
3586
c0f1147d 3587 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3588 /* napi_schedule in case we have missed anything */
3589 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3590 napi_schedule(&c->napi);
3591
3592 if (old_prog)
3593 bpf_prog_put(old_prog);
3594 }
3595
3596unlock:
3597 mutex_unlock(&priv->state_lock);
3598 return err;
3599}
3600
3601static bool mlx5e_xdp_attached(struct net_device *dev)
3602{
3603 struct mlx5e_priv *priv = netdev_priv(dev);
3604
6a9764ef 3605 return !!priv->channels.params.xdp_prog;
86994156
RS		 3606}
3607
3608static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3609{
3610 switch (xdp->command) {
3611 case XDP_SETUP_PROG:
3612 return mlx5e_xdp_set(dev, xdp->prog);
3613 case XDP_QUERY_PROG:
3614 xdp->prog_attached = mlx5e_xdp_attached(dev);
3615 return 0;
3616 default:
3617 return -EINVAL;
3618 }
3619}
3620
80378384
CO		 3621#ifdef CONFIG_NET_POLL_CONTROLLER
3622/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3623 * reenabling interrupts.
3624 */
3625static void mlx5e_netpoll(struct net_device *dev)
3626{
3627 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3628 struct mlx5e_channels *chs = &priv->channels;
3629
80378384
CO		 3630 int i;
3631
ff9c852f
SM		 3632 for (i = 0; i < chs->num; i++)
3633 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3634}
3635#endif
3636
b0eed40e 3637static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3638 .ndo_open = mlx5e_open,
3639 .ndo_stop = mlx5e_close,
3640 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3641 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3642 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3643 .ndo_get_stats64 = mlx5e_get_stats,
3644 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3645 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3646 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3647 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3648 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3649 .ndo_change_mtu = mlx5e_change_mtu,
3650 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3651 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3652#ifdef CONFIG_RFS_ACCEL
3653 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3654#endif
3947ca18 3655 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3656 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3657#ifdef CONFIG_NET_POLL_CONTROLLER
3658 .ndo_poll_controller = mlx5e_netpoll,
3659#endif
b0eed40e
SM		 3660};
3661
3662static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3663 .ndo_open = mlx5e_open,
3664 .ndo_stop = mlx5e_close,
3665 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3666 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3667 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3668 .ndo_get_stats64 = mlx5e_get_stats,
3669 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3670 .ndo_set_mac_address = mlx5e_set_mac,
3671 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3672 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3673 .ndo_set_features = mlx5e_set_features,
3674 .ndo_change_mtu = mlx5e_change_mtu,
3675 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3676 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3677 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3678 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3679 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3680#ifdef CONFIG_RFS_ACCEL
3681 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3682#endif
b0eed40e
SM		 3683 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3684 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3685 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3686 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3687 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3688 .ndo_get_vf_config = mlx5e_get_vf_config,
3689 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3690 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3691 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3692 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3693#ifdef CONFIG_NET_POLL_CONTROLLER
3694 .ndo_poll_controller = mlx5e_netpoll,
3695#endif
370bad0f
OG		 3696 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3697 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3698};
3699
3700static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3701{
3702 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3703 return -EOPNOTSUPP;
f62b8bb8
AV		 3704 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3705 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3706 !MLX5_CAP_ETH(mdev, csum_cap) ||
3707 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3708 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3709 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3710 MLX5_CAP_FLOWTABLE(mdev,
3711 flow_table_properties_nic_receive.max_ft_level)
3712 < 3) {
f62b8bb8
AV		 3713 mlx5_core_warn(mdev,
3714 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3715 return -EOPNOTSUPP;
f62b8bb8 3716 }
66189961
TT		 3717 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3718 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3719 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3720 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3721
f62b8bb8
AV		 3722 return 0;
3723}
3724
58d52291
AS		 3725u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3726{
3727 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3728
3729 return bf_buf_size -
3730 sizeof(struct mlx5e_tx_wqe) +
3731 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3732}
3733
d8c9660d
TT		 3734void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3735 u32 *indirection_rqt, int len,
85082dba
TT		 3736 int num_channels)
3737{
d8c9660d
TT		 3738 int node = mdev->priv.numa_node;
3739 int node_num_of_cores;
85082dba
TT		 3740 int i;
3741
d8c9660d
TT		 3742 if (node == -1)
3743 node = first_online_node;
3744
3745 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3746
3747 if (node_num_of_cores)
3748 num_channels = min_t(int, num_channels, node_num_of_cores);
3749
85082dba
TT		 3750 for (i = 0; i < len; i++)
3751 indirection_rqt[i] = i % num_channels;
3752}
3753
b797a684
SM		 3754static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3755{
3756 enum pcie_link_width width;
3757 enum pci_bus_speed speed;
3758 int err = 0;
3759
3760 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3761 if (err)
3762 return err;
3763
3764 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3765 return -EINVAL;
3766
3767 switch (speed) {
3768 case PCIE_SPEED_2_5GT:
3769 *pci_bw = 2500 * width;
3770 break;
3771 case PCIE_SPEED_5_0GT:
3772 *pci_bw = 5000 * width;
3773 break;
3774 case PCIE_SPEED_8_0GT:
3775 *pci_bw = 8000 * width;
3776 break;
3777 default:
3778 return -EINVAL;
3779 }
3780
3781 return 0;
3782}
3783
3784static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3785{
3786 return (link_speed && pci_bw &&
3787 (pci_bw < 40000) && (pci_bw < link_speed));
3788}
3789
9908aa29
TT		 3790void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3791{
3792 params->rx_cq_period_mode = cq_period_mode;
3793
3794 params->rx_cq_moderation.pkts =
3795 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3796 params->rx_cq_moderation.usec =
3797 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3798
3799 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3800 params->rx_cq_moderation.usec =
3801 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef
SM		 3802
3803 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3804 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3805}
3806
2b029556
SM		 3807u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3808{
3809 int i;
3810
3811 /* The supported periods are organized in ascending order */
3812 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3813 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3814 break;
3815
3816 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3817}
3818
6a9764ef
SM		 3819static void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3820 struct mlx5e_params *params,
3821 u16 max_channels)
f62b8bb8 3822{
6a9764ef 3823 u8 cq_period_mode = 0;
b797a684
SM		 3824 u32 link_speed = 0;
3825 u32 pci_bw = 0;
2fc4bfb7 3826
6a9764ef
SM		 3827 params->num_channels = max_channels;
3828 params->num_tc = 1;
2b029556 3829
6a9764ef
SM		 3830 /* SQ */
3831 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3832 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3833 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3834
b797a684 3835 /* set CQE compression */
6a9764ef 3836 params->rx_cqe_compress_def = false;
b797a684 3837 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
6a9764ef 3838 MLX5_CAP_GEN(mdev, vport_group_manager)) {
b797a684
SM		 3839 mlx5e_get_max_linkspeed(mdev, &link_speed);
3840 mlx5e_get_pci_bw(mdev, &pci_bw);
3841 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
6a9764ef
SM		 3842 link_speed, pci_bw);
3843 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
b797a684 3844 }
6a9764ef
SM		 3845 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3846
3847 /* RQ */
3848 mlx5e_set_rq_params(mdev, params);
b797a684 3849
6a9764ef
SM		 3850 /* HW LRO */
3851 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3852 params->lro_en = true;
3853 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 3854
6a9764ef
SM		 3855 /* CQ moderation params */
3856 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3857 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3858 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3859 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3860 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
9908aa29 3861
6a9764ef
SM		 3862 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3863 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
9908aa29 3864
6a9764ef
SM		 3865 /* TX inline */
3866 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3867 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3868 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
a6f402e4 3869 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
6a9764ef 3870 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
a6f402e4 3871
6a9764ef
SM		 3872 /* RSS */
3873 params->rss_hfunc = ETH_RSS_HASH_XOR;
3874 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3875 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3876 MLX5E_INDIR_RQT_SIZE, max_channels);
3877}
f62b8bb8 3878
6a9764ef
SM		 3879static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3880 struct net_device *netdev,
3881 const struct mlx5e_profile *profile,
3882 void *ppriv)
3883{
3884 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 3885
6a9764ef
SM		 3886 priv->mdev = mdev;
3887 priv->netdev = netdev;
3888 priv->profile = profile;
3889 priv->ppriv = ppriv;
2d75b2bc 3890
6a9764ef 3891 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 3892
f62b8bb8
AV		 3893 mutex_init(&priv->state_lock);
3894
3895 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3896 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3897 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3898 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3899}
3900
3901static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3902{
3903 struct mlx5e_priv *priv = netdev_priv(netdev);
3904
e1d7d349 3905 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3906 if (is_zero_ether_addr(netdev->dev_addr) &&
3907 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3908 eth_hw_addr_random(netdev);
3909 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3910 }
f62b8bb8
AV		 3911}
3912
cb67b832
HHZ		 3913static const struct switchdev_ops mlx5e_switchdev_ops = {
3914 .switchdev_port_attr_get = mlx5e_attr_get,
3915};
3916
6bfd390b 3917static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3918{
3919 struct mlx5e_priv *priv = netdev_priv(netdev);
3920 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3921 bool fcs_supported;
3922 bool fcs_enabled;
f62b8bb8
AV		 3923
3924 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3925
08fb1dac 3926 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3927 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3928#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3929 if (MLX5_CAP_GEN(mdev, qos))
3930 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3931#endif
3932 } else {
b0eed40e 3933 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3934 }
66e49ded 3935
f62b8bb8
AV		 3936 netdev->watchdog_timeo = 15 * HZ;
3937
3938 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3939
12be4b21 3940 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3941 netdev->vlan_features |= NETIF_F_IP_CSUM;
3942 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3943 netdev->vlan_features |= NETIF_F_GRO;
3944 netdev->vlan_features |= NETIF_F_TSO;
3945 netdev->vlan_features |= NETIF_F_TSO6;
3946 netdev->vlan_features |= NETIF_F_RXCSUM;
3947 netdev->vlan_features |= NETIF_F_RXHASH;
3948
3949 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3950 netdev->vlan_features |= NETIF_F_LRO;
3951
3952 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3953 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3954 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3955 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3956
b3f63c3d 3957 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3958 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3959 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3960 NETIF_F_GSO_PARTIAL;
b3f63c3d 3961 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3962 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3963 netdev->hw_enc_features |= NETIF_F_TSO;
3964 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3965 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3966 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3967 NETIF_F_GSO_PARTIAL;
3968 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3969 }
3970
94cb1ebb
EBE		 3971 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3972
3973 if (fcs_supported)
3974 netdev->hw_features |= NETIF_F_RXALL;
3975
102722fc
GE		 3976 if (MLX5_CAP_ETH(mdev, scatter_fcs))
3977 netdev->hw_features |= NETIF_F_RXFCS;
3978
f62b8bb8 3979 netdev->features = netdev->hw_features;
6a9764ef 3980 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 3981 netdev->features &= ~NETIF_F_LRO;
3982
94cb1ebb
EBE		 3983 if (fcs_enabled)
3984 netdev->features &= ~NETIF_F_RXALL;
3985
102722fc
GE		 3986 if (!priv->channels.params.scatter_fcs_en)
3987 netdev->features &= ~NETIF_F_RXFCS;
3988
e8f887ac
AV		 3989#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3990 if (FT_CAP(flow_modify_en) &&
3991 FT_CAP(modify_root) &&
3992 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3993 FT_CAP(flow_table_modify)) {
3994 netdev->hw_features |= NETIF_F_HW_TC;
3995#ifdef CONFIG_RFS_ACCEL
3996 netdev->hw_features |= NETIF_F_NTUPLE;
3997#endif
3998 }
e8f887ac 3999
f62b8bb8
AV		 4000 netdev->features |= NETIF_F_HIGHDMA;
4001
4002 netdev->priv_flags |= IFF_UNICAST_FLT;
4003
4004 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 4005
4006#ifdef CONFIG_NET_SWITCHDEV
4007 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4008 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4009#endif
f62b8bb8
AV		 4010}
4011
593cf338
RS		 4012static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4013{
4014 struct mlx5_core_dev *mdev = priv->mdev;
4015 int err;
4016
4017 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4018 if (err) {
4019 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4020 priv->q_counter = 0;
4021 }
4022}
4023
4024static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4025{
4026 if (!priv->q_counter)
4027 return;
4028
4029 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4030}
4031
6bfd390b
HHZ		 4032static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4033 struct net_device *netdev,
127ea380
HHZ		 4034 const struct mlx5e_profile *profile,
4035 void *ppriv)
6bfd390b
HHZ		 4036{
4037 struct mlx5e_priv *priv = netdev_priv(netdev);
4038
127ea380 4039 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 4040 mlx5e_build_nic_netdev(netdev);
4041 mlx5e_vxlan_init(priv);
4042}
4043
4044static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4045{
4046 mlx5e_vxlan_cleanup(priv);
127ea380 4047
6a9764ef
SM		 4048 if (priv->channels.params.xdp_prog)
4049 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 4050}
4051
4052static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4053{
4054 struct mlx5_core_dev *mdev = priv->mdev;
4055 int err;
4056 int i;
4057
4058 err = mlx5e_create_indirect_rqts(priv);
4059 if (err) {
4060 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
4061 return err;
4062 }
4063
4064 err = mlx5e_create_direct_rqts(priv);
4065 if (err) {
4066 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
4067 goto err_destroy_indirect_rqts;
4068 }
4069
4070 err = mlx5e_create_indirect_tirs(priv);
4071 if (err) {
4072 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
4073 goto err_destroy_direct_rqts;
4074 }
4075
4076 err = mlx5e_create_direct_tirs(priv);
4077 if (err) {
4078 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
4079 goto err_destroy_indirect_tirs;
4080 }
4081
4082 err = mlx5e_create_flow_steering(priv);
4083 if (err) {
4084 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4085 goto err_destroy_direct_tirs;
4086 }
4087
4088 err = mlx5e_tc_init(priv);
4089 if (err)
4090 goto err_destroy_flow_steering;
4091
4092 return 0;
4093
4094err_destroy_flow_steering:
4095 mlx5e_destroy_flow_steering(priv);
4096err_destroy_direct_tirs:
4097 mlx5e_destroy_direct_tirs(priv);
4098err_destroy_indirect_tirs:
4099 mlx5e_destroy_indirect_tirs(priv);
4100err_destroy_direct_rqts:
4101 for (i = 0; i < priv->profile->max_nch(mdev); i++)
4102 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
4103err_destroy_indirect_rqts:
4104 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4105 return err;
4106}
4107
4108static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4109{
4110 int i;
4111
4112 mlx5e_tc_cleanup(priv);
4113 mlx5e_destroy_flow_steering(priv);
4114 mlx5e_destroy_direct_tirs(priv);
4115 mlx5e_destroy_indirect_tirs(priv);
4116 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
4117 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
4118 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4119}
4120
4121static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4122{
4123 int err;
4124
4125 err = mlx5e_create_tises(priv);
4126 if (err) {
4127 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4128 return err;
4129 }
4130
4131#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4132 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4133#endif
4134 return 0;
4135}
4136
4137static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4138{
4139 struct net_device *netdev = priv->netdev;
4140 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 4141 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4142 struct mlx5_eswitch_rep rep;
6bfd390b 4143
7907f23a
AH		 4144 mlx5_lag_add(mdev, netdev);
4145
6bfd390b 4146 mlx5e_enable_async_events(priv);
127ea380
HHZ		 4147
4148 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 4149 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 4150 rep.load = mlx5e_nic_rep_load;
4151 rep.unload = mlx5e_nic_rep_unload;
9deb2241 4152 rep.vport = FDB_UPLINK_VPORT;
726293f1 4153 rep.netdev = netdev;
9deb2241 4154 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 4155 }
610e89e0
SM		 4156
4157 if (netdev->reg_state != NETREG_REGISTERED)
4158 return;
4159
4160 /* Device already registered: sync netdev system state */
4161 if (mlx5e_vxlan_allowed(mdev)) {
4162 rtnl_lock();
4163 udp_tunnel_get_rx_info(netdev);
4164 rtnl_unlock();
4165 }
4166
4167 queue_work(priv->wq, &priv->set_rx_mode_work);
6bfd390b
HHZ		 4168}
4169
4170static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4171{
3deef8ce
SM		 4172 struct mlx5_core_dev *mdev = priv->mdev;
4173 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4174
6bfd390b 4175 queue_work(priv->wq, &priv->set_rx_mode_work);
3deef8ce
SM		 4176 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4177 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b 4178 mlx5e_disable_async_events(priv);
3deef8ce 4179 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4180}
4181
4182static const struct mlx5e_profile mlx5e_nic_profile = {
4183 .init = mlx5e_nic_init,
4184 .cleanup = mlx5e_nic_cleanup,
4185 .init_rx = mlx5e_init_nic_rx,
4186 .cleanup_rx = mlx5e_cleanup_nic_rx,
4187 .init_tx = mlx5e_init_nic_tx,
4188 .cleanup_tx = mlx5e_cleanup_nic_tx,
4189 .enable = mlx5e_nic_enable,
4190 .disable = mlx5e_nic_disable,
4191 .update_stats = mlx5e_update_stats,
4192 .max_nch = mlx5e_get_max_num_channels,
4193 .max_tc = MLX5E_MAX_NUM_TC,
4194};
4195
26e59d80
MHY		 4196struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4197 const struct mlx5e_profile *profile,
4198 void *ppriv)
f62b8bb8 4199{
26e59d80 4200 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4201 struct net_device *netdev;
4202 struct mlx5e_priv *priv;
f62b8bb8 4203
08fb1dac 4204 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4205 nch * profile->max_tc,
08fb1dac 4206 nch);
f62b8bb8
AV		 4207 if (!netdev) {
4208 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4209 return NULL;
4210 }
4211
be4891af
SM		 4212#ifdef CONFIG_RFS_ACCEL
4213 netdev->rx_cpu_rmap = mdev->rmap;
4214#endif
4215
127ea380 4216 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4217
4218 netif_carrier_off(netdev);
4219
4220 priv = netdev_priv(netdev);
4221
7bb29755
MF		 4222 priv->wq = create_singlethread_workqueue("mlx5e");
4223 if (!priv->wq)
26e59d80
MHY		 4224 goto err_cleanup_nic;
4225
4226 return netdev;
4227
4228err_cleanup_nic:
4229 profile->cleanup(priv);
4230 free_netdev(netdev);
4231
4232 return NULL;
4233}
4234
4235int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
4236{
4237 const struct mlx5e_profile *profile;
4238 struct mlx5e_priv *priv;
b80f71f5 4239 u16 max_mtu;
26e59d80
MHY		 4240 int err;
4241
4242 priv = netdev_priv(netdev);
4243 profile = priv->profile;
4244 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4245
6bfd390b
HHZ		 4246 err = profile->init_tx(priv);
4247 if (err)
ec8b9981 4248 goto out;
5c50368f 4249
a43b25da 4250 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4251 if (err) {
4252 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4253 goto err_cleanup_tx;
5c50368f
AS		 4254 }
4255
6bfd390b
HHZ		 4256 err = profile->init_rx(priv);
4257 if (err)
5c50368f 4258 goto err_close_drop_rq;
5c50368f 4259
593cf338
RS		 4260 mlx5e_create_q_counter(priv);
4261
33cfaaa8 4262 mlx5e_init_l2_addr(priv);
5c50368f 4263
b80f71f5
JW		 4264 /* MTU range: 68 - hw-specific max */
4265 netdev->min_mtu = ETH_MIN_MTU;
4266 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4267 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4268
2e20a151 4269 mlx5e_set_dev_port_mtu(priv);
13f9bba7 4270
6bfd390b
HHZ		 4271 if (profile->enable)
4272 profile->enable(priv);
f62b8bb8 4273
26e59d80
MHY		 4274 rtnl_lock();
4275 if (netif_running(netdev))
4276 mlx5e_open(netdev);
4277 netif_device_attach(netdev);
4278 rtnl_unlock();
f62b8bb8 4279
26e59d80 4280 return 0;
5c50368f
AS		 4281
4282err_close_drop_rq:
a43b25da 4283 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4284
6bfd390b
HHZ		 4285err_cleanup_tx:
4286 profile->cleanup_tx(priv);
5c50368f 4287
26e59d80
MHY		 4288out:
4289 return err;
f62b8bb8
AV		 4290}
4291
127ea380
HHZ		 4292static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
4293{
4294 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4295 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4296 int vport;
dbe413e3 4297 u8 mac[ETH_ALEN];
127ea380
HHZ		 4298
4299 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4300 return;
4301
dbe413e3
HHZ		 4302 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
4303
127ea380
HHZ		 4304 for (vport = 1; vport < total_vfs; vport++) {
4305 struct mlx5_eswitch_rep rep;
4306
cb67b832
HHZ		 4307 rep.load = mlx5e_vport_rep_load;
4308 rep.unload = mlx5e_vport_rep_unload;
127ea380 4309 rep.vport = vport;
dbe413e3 4310 ether_addr_copy(rep.hw_id, mac);
9deb2241 4311 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 4312 }
4313}
4314
6f08a22c
SM		 4315static void mlx5e_unregister_vport_rep(struct mlx5_core_dev *mdev)
4316{
4317 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4318 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4319 int vport;
4320
4321 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4322 return;
4323
4324 for (vport = 1; vport < total_vfs; vport++)
4325 mlx5_eswitch_unregister_vport_rep(esw, vport);
4326}
4327
26e59d80
MHY		 4328void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
4329{
4330 struct mlx5e_priv *priv = netdev_priv(netdev);
4331 const struct mlx5e_profile *profile = priv->profile;
4332
4333 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80
MHY		 4334
4335 rtnl_lock();
4336 if (netif_running(netdev))
4337 mlx5e_close(netdev);
4338 netif_device_detach(netdev);
4339 rtnl_unlock();
4340
37f304d1
SM		 4341 if (profile->disable)
4342 profile->disable(priv);
4343 flush_workqueue(priv->wq);
4344
26e59d80
MHY		 4345 mlx5e_destroy_q_counter(priv);
4346 profile->cleanup_rx(priv);
a43b25da 4347 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4348 profile->cleanup_tx(priv);
26e59d80
MHY		 4349 cancel_delayed_work_sync(&priv->update_stats_work);
4350}
4351
4352/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4353 * hardware contexts and to connect it to the current netdev.
4354 */
4355static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4356{
4357 struct mlx5e_priv *priv = vpriv;
4358 struct net_device *netdev = priv->netdev;
4359 int err;
4360
4361 if (netif_device_present(netdev))
4362 return 0;
4363
4364 err = mlx5e_create_mdev_resources(mdev);
4365 if (err)
4366 return err;
4367
4368 err = mlx5e_attach_netdev(mdev, netdev);
4369 if (err) {
4370 mlx5e_destroy_mdev_resources(mdev);
4371 return err;
4372 }
4373
6f08a22c 4374 mlx5e_register_vport_rep(mdev);
26e59d80
MHY		 4375 return 0;
4376}
4377
4378static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4379{
4380 struct mlx5e_priv *priv = vpriv;
4381 struct net_device *netdev = priv->netdev;
4382
4383 if (!netif_device_present(netdev))
4384 return;
4385
6f08a22c 4386 mlx5e_unregister_vport_rep(mdev);
26e59d80
MHY		 4387 mlx5e_detach_netdev(mdev, netdev);
4388 mlx5e_destroy_mdev_resources(mdev);
4389}
4390
b50d292b
HHZ		 4391static void *mlx5e_add(struct mlx5_core_dev *mdev)
4392{
127ea380 4393 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4394 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4395 void *ppriv = NULL;
26e59d80
MHY		 4396 void *priv;
4397 int vport;
4398 int err;
4399 struct net_device *netdev;
b50d292b 4400
26e59d80
MHY		 4401 err = mlx5e_check_required_hca_cap(mdev);
4402 if (err)
b50d292b
HHZ		 4403 return NULL;
4404
127ea380
HHZ		 4405 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4406 ppriv = &esw->offloads.vport_reps[0];
4407
26e59d80
MHY		 4408 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4409 if (!netdev) {
4410 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4411 goto err_unregister_reps;
4412 }
4413
4414 priv = netdev_priv(netdev);
4415
4416 err = mlx5e_attach(mdev, priv);
4417 if (err) {
4418 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4419 goto err_destroy_netdev;
4420 }
4421
4422 err = register_netdev(netdev);
4423 if (err) {
4424 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4425 goto err_detach;
b50d292b 4426 }
26e59d80
MHY		 4427
4428 return priv;
4429
4430err_detach:
4431 mlx5e_detach(mdev, priv);
4432
4433err_destroy_netdev:
4434 mlx5e_destroy_netdev(mdev, priv);
4435
4436err_unregister_reps:
4437 for (vport = 1; vport < total_vfs; vport++)
4438 mlx5_eswitch_unregister_vport_rep(esw, vport);
4439
4440 return NULL;
b50d292b
HHZ		 4441}
4442
cb67b832 4443void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4444{
6bfd390b 4445 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4446 struct net_device *netdev = priv->netdev;
4447
7bb29755 4448 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4449 if (profile->cleanup)
4450 profile->cleanup(priv);
26e59d80 4451 free_netdev(netdev);
f62b8bb8
AV		 4452}
4453
b50d292b
HHZ		 4454static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4455{
4456 struct mlx5e_priv *priv = vpriv;
127ea380 4457
5e1e93c7 4458 unregister_netdev(priv->netdev);
26e59d80
MHY		 4459 mlx5e_detach(mdev, vpriv);
4460 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4461}
4462
f62b8bb8
AV		 4463static void *mlx5e_get_netdev(void *vpriv)
4464{
4465 struct mlx5e_priv *priv = vpriv;
4466
4467 return priv->netdev;
4468}
4469
4470static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4471 .add = mlx5e_add,
4472 .remove = mlx5e_remove,
26e59d80
MHY		 4473 .attach = mlx5e_attach,
4474 .detach = mlx5e_detach,
f62b8bb8
AV		 4475 .event = mlx5e_async_event,
4476 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4477 .get_dev = mlx5e_get_netdev,
4478};
4479
4480void mlx5e_init(void)
4481{
665bc539 4482 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4483 mlx5_register_interface(&mlx5e_interface);
4484}
4485
4486void mlx5e_cleanup(void)
4487{
4488 mlx5_unregister_interface(&mlx5e_interface);
4489}
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