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net/mlx5: Initializing CPU reverse mapping
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8
AV		 41
42struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45};
46
47struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
58d52291 50 u16 max_inline;
d3c9bc27 51 bool icosq;
f62b8bb8
AV		 52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
58};
59
60struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
d3c9bc27 63 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
d3c9bc27 66 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 67};
68
69static void mlx5e_update_carrier(struct mlx5e_priv *priv)
70{
71 struct mlx5_core_dev *mdev = priv->mdev;
72 u8 port_state;
73
74 port_state = mlx5_query_vport_state(mdev,
e7546514 75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 76
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
79 else
80 netif_carrier_off(priv->netdev);
81}
82
83static void mlx5e_update_carrier_work(struct work_struct *work)
84{
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
86 update_carrier_work);
87
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
92}
93
9218b44d 94static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 95{
9218b44d 96 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
9218b44d 99 u64 tx_offload_none = 0;
f62b8bb8
AV		 100 int i, j;
101
9218b44d 102 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
105
faf4478b
GP		 106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
f62b8bb8
AV		 108 s->lro_packets += rq_stats->lro_packets;
109 s->lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
bbceefce 111 s->rx_csum_sw += rq_stats->csum_sw;
1b223dd3 112 s->rx_csum_inner += rq_stats->csum_inner;
f62b8bb8 113 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 114 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 115 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 116 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
f62b8bb8 117
a4418a6c 118 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 119 sq_stats = &priv->channel[i]->sq[j].stats;
120
faf4478b
GP		 121 s->tx_packets += sq_stats->packets;
122 s->tx_bytes += sq_stats->bytes;
f62b8bb8
AV		 123 s->tso_packets += sq_stats->tso_packets;
124 s->tso_bytes += sq_stats->tso_bytes;
89db09eb
MF		 125 s->tso_inner_packets += sq_stats->tso_inner_packets;
126 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 127 s->tx_queue_stopped += sq_stats->stopped;
128 s->tx_queue_wake += sq_stats->wake;
129 s->tx_queue_dropped += sq_stats->dropped;
89db09eb 130 s->tx_csum_inner += sq_stats->csum_offload_inner;
f62b8bb8
AV		 131 tx_offload_none += sq_stats->csum_offload_none;
132 }
133 }
134
9218b44d
GP		 135 /* Update calculated offload counters */
136 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
137 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
138 s->rx_csum_sw;
121fcdc8
GP		 139
140 s->link_down_events = MLX5_GET(ppcnt_reg,
141 priv->stats.pport.phy_counters,
142 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 143}
144
145static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
146{
147 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
148 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
149 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
150 struct mlx5_core_dev *mdev = priv->mdev;
151
f62b8bb8
AV		 152 memset(in, 0, sizeof(in));
153
154 MLX5_SET(query_vport_counter_in, in, opcode,
155 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
156 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
157 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
158
159 memset(out, 0, outlen);
160
9218b44d
GP		 161 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
162}
163
164static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
165{
166 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
167 struct mlx5_core_dev *mdev = priv->mdev;
168 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 169 int prio;
9218b44d
GP		 170 void *out;
171 u32 *in;
172
173 in = mlx5_vzalloc(sz);
174 if (!in)
f62b8bb8
AV		 175 goto free_out;
176
9218b44d 177 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 178
9218b44d
GP		 179 out = pstats->IEEE_802_3_counters;
180 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
181 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 182
9218b44d
GP		 183 out = pstats->RFC_2863_counters;
184 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
185 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
186
187 out = pstats->RFC_2819_counters;
188 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
189 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 190
121fcdc8
GP		 191 out = pstats->phy_counters;
192 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
193 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
194
cf678570
GP		 195 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
196 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
197 out = pstats->per_prio_counters[prio];
198 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
199 mlx5_core_access_reg(mdev, in, sz, out, sz,
200 MLX5_REG_PPCNT, 0, 0);
201 }
202
f62b8bb8 203free_out:
9218b44d
GP		 204 kvfree(in);
205}
206
207static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
208{
209 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
210
211 if (!priv->q_counter)
212 return;
213
214 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
215 &qcnt->rx_out_of_buffer);
216}
217
218void mlx5e_update_stats(struct mlx5e_priv *priv)
219{
9218b44d
GP		 220 mlx5e_update_q_counter(priv);
221 mlx5e_update_vport_counters(priv);
222 mlx5e_update_pport_counters(priv);
121fcdc8 223 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 224}
225
226static void mlx5e_update_stats_work(struct work_struct *work)
227{
228 struct delayed_work *dwork = to_delayed_work(work);
229 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
230 update_stats_work);
231 mutex_lock(&priv->state_lock);
232 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
233 mlx5e_update_stats(priv);
234 schedule_delayed_work(dwork,
235 msecs_to_jiffies(
236 MLX5E_UPDATE_STATS_INTERVAL));
237 }
238 mutex_unlock(&priv->state_lock);
239}
240
daa21560
TT		 241static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
242 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 243{
daa21560
TT		 244 struct mlx5e_priv *priv = vpriv;
245
246 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
247 return;
248
f62b8bb8
AV		 249 switch (event) {
250 case MLX5_DEV_EVENT_PORT_UP:
251 case MLX5_DEV_EVENT_PORT_DOWN:
252 schedule_work(&priv->update_carrier_work);
253 break;
254
255 default:
256 break;
257 }
258}
259
f62b8bb8
AV		 260static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
261{
262 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
263}
264
265static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
266{
f62b8bb8 267 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
daa21560 268 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 269}
270
facc9699
SM		 271#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
272#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
273
f62b8bb8
AV		 274static int mlx5e_create_rq(struct mlx5e_channel *c,
275 struct mlx5e_rq_param *param,
276 struct mlx5e_rq *rq)
277{
278 struct mlx5e_priv *priv = c->priv;
279 struct mlx5_core_dev *mdev = priv->mdev;
280 void *rqc = param->rqc;
281 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 282 u32 byte_count;
f62b8bb8
AV		 283 int wq_sz;
284 int err;
285 int i;
286
311c7c71
SM		 287 param->wq.db_numa_node = cpu_to_node(c->cpu);
288
f62b8bb8
AV		 289 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
290 &rq->wq_ctrl);
291 if (err)
292 return err;
293
294 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
295
296 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 297
461017cb
TT		 298 switch (priv->params.rq_wq_type) {
299 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
300 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
301 GFP_KERNEL, cpu_to_node(c->cpu));
302 if (!rq->wqe_info) {
303 err = -ENOMEM;
304 goto err_rq_wq_destroy;
305 }
306 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
307 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
308
309 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
310 byte_count = rq->wqe_sz;
311 break;
312 default: /* MLX5_WQ_TYPE_LINKED_LIST */
313 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
314 cpu_to_node(c->cpu));
315 if (!rq->skb) {
316 err = -ENOMEM;
317 goto err_rq_wq_destroy;
318 }
319 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
320 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
321
322 rq->wqe_sz = (priv->params.lro_en) ?
323 priv->params.lro_wqe_sz :
324 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 325 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
326 byte_count = rq->wqe_sz;
461017cb
TT		 327 byte_count |= MLX5_HW_START_PADDING;
328 }
f62b8bb8
AV		 329
330 for (i = 0; i < wq_sz; i++) {
331 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
332
461017cb 333 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 334 }
335
461017cb 336 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 337 rq->pdev = c->pdev;
338 rq->netdev = c->netdev;
ef9814de 339 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 340 rq->channel = c;
341 rq->ix = c->ix;
50cfa25a 342 rq->priv = c->priv;
bc77b240
TT		 343 rq->mkey_be = c->mkey_be;
344 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 345
346 return 0;
347
348err_rq_wq_destroy:
349 mlx5_wq_destroy(&rq->wq_ctrl);
350
351 return err;
352}
353
354static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
355{
461017cb
TT		 356 switch (rq->wq_type) {
357 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
358 kfree(rq->wqe_info);
359 break;
360 default: /* MLX5_WQ_TYPE_LINKED_LIST */
361 kfree(rq->skb);
362 }
363
f62b8bb8
AV		 364 mlx5_wq_destroy(&rq->wq_ctrl);
365}
366
367static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
368{
50cfa25a 369 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 370 struct mlx5_core_dev *mdev = priv->mdev;
371
372 void *in;
373 void *rqc;
374 void *wq;
375 int inlen;
376 int err;
377
378 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
379 sizeof(u64) * rq->wq_ctrl.buf.npages;
380 in = mlx5_vzalloc(inlen);
381 if (!in)
382 return -ENOMEM;
383
384 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
385 wq = MLX5_ADDR_OF(rqc, rqc, wq);
386
387 memcpy(rqc, param->rqc, sizeof(param->rqc));
388
97de9f31 389 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 390 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
391 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
36350114 392 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 393 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 394 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 395 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
396
397 mlx5_fill_page_array(&rq->wq_ctrl.buf,
398 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
399
7db22ffb 400 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 401
402 kvfree(in);
403
404 return err;
405}
406
36350114
GP		 407static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
408 int next_state)
f62b8bb8
AV		 409{
410 struct mlx5e_channel *c = rq->channel;
411 struct mlx5e_priv *priv = c->priv;
412 struct mlx5_core_dev *mdev = priv->mdev;
413
414 void *in;
415 void *rqc;
416 int inlen;
417 int err;
418
419 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
420 in = mlx5_vzalloc(inlen);
421 if (!in)
422 return -ENOMEM;
423
424 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
425
426 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
427 MLX5_SET(rqc, rqc, state, next_state);
428
7db22ffb 429 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 430
431 kvfree(in);
432
433 return err;
434}
435
36350114
GP		 436static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
437{
438 struct mlx5e_channel *c = rq->channel;
439 struct mlx5e_priv *priv = c->priv;
440 struct mlx5_core_dev *mdev = priv->mdev;
441
442 void *in;
443 void *rqc;
444 int inlen;
445 int err;
446
447 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
448 in = mlx5_vzalloc(inlen);
449 if (!in)
450 return -ENOMEM;
451
452 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
453
454 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
455 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
456 MLX5_SET(rqc, rqc, vsd, vsd);
457 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
458
459 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
460
461 kvfree(in);
462
463 return err;
464}
465
f62b8bb8
AV		 466static void mlx5e_disable_rq(struct mlx5e_rq *rq)
467{
50cfa25a 468 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 469}
470
471static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
472{
01c196a2 473 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 474 struct mlx5e_channel *c = rq->channel;
475 struct mlx5e_priv *priv = c->priv;
476 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 477
01c196a2 478 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 479 if (wq->cur_sz >= priv->params.min_rx_wqes)
480 return 0;
481
482 msleep(20);
483 }
484
485 return -ETIMEDOUT;
486}
487
488static int mlx5e_open_rq(struct mlx5e_channel *c,
489 struct mlx5e_rq_param *param,
490 struct mlx5e_rq *rq)
491{
d3c9bc27
TT		 492 struct mlx5e_sq *sq = &c->icosq;
493 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 494 int err;
495
496 err = mlx5e_create_rq(c, param, rq);
497 if (err)
498 return err;
499
500 err = mlx5e_enable_rq(rq, param);
501 if (err)
502 goto err_destroy_rq;
503
36350114 504 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 505 if (err)
506 goto err_disable_rq;
507
508 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
d3c9bc27
TT		 509
510 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
511 sq->ico_wqe_info[pi].num_wqebbs = 1;
512 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 513
514 return 0;
515
516err_disable_rq:
517 mlx5e_disable_rq(rq);
518err_destroy_rq:
519 mlx5e_destroy_rq(rq);
520
521 return err;
522}
523
524static void mlx5e_close_rq(struct mlx5e_rq *rq)
525{
526 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
527 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
528
36350114 529 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
f62b8bb8
AV		 530 while (!mlx5_wq_ll_is_empty(&rq->wq))
531 msleep(20);
532
533 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
534 napi_synchronize(&rq->channel->napi);
535
536 mlx5e_disable_rq(rq);
537 mlx5e_destroy_rq(rq);
538}
539
540static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
541{
34802a42 542 kfree(sq->wqe_info);
f62b8bb8
AV		 543 kfree(sq->dma_fifo);
544 kfree(sq->skb);
545}
546
547static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
548{
549 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
550 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
551
552 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
553 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
554 numa);
34802a42
AS		 555 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
556 numa);
f62b8bb8 557
34802a42 558 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 559 mlx5e_free_sq_db(sq);
560 return -ENOMEM;
561 }
562
563 sq->dma_fifo_mask = df_sz - 1;
564
565 return 0;
566}
567
568static int mlx5e_create_sq(struct mlx5e_channel *c,
569 int tc,
570 struct mlx5e_sq_param *param,
571 struct mlx5e_sq *sq)
572{
573 struct mlx5e_priv *priv = c->priv;
574 struct mlx5_core_dev *mdev = priv->mdev;
575
576 void *sqc = param->sqc;
577 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
578 int err;
579
0ba42241 580 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
f62b8bb8
AV		 581 if (err)
582 return err;
583
311c7c71
SM		 584 param->wq.db_numa_node = cpu_to_node(c->cpu);
585
f62b8bb8
AV		 586 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
587 &sq->wq_ctrl);
588 if (err)
589 goto err_unmap_free_uar;
590
591 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 592 if (sq->uar.bf_map) {
593 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
594 sq->uar_map = sq->uar.bf_map;
595 } else {
596 sq->uar_map = sq->uar.map;
597 }
f62b8bb8 598 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 599 sq->max_inline = param->max_inline;
f62b8bb8 600
7ec0bb22
DC		 601 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
602 if (err)
f62b8bb8
AV		 603 goto err_sq_wq_destroy;
604
d3c9bc27
TT		 605 if (param->icosq) {
606 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
607
608 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
609 wq_sz,
610 GFP_KERNEL,
611 cpu_to_node(c->cpu));
612 if (!sq->ico_wqe_info) {
613 err = -ENOMEM;
614 goto err_free_sq_db;
615 }
616 } else {
617 int txq_ix;
618
619 txq_ix = c->ix + tc * priv->params.num_channels;
620 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
621 priv->txq_to_sq_map[txq_ix] = sq;
622 }
f62b8bb8 623
88a85f99 624 sq->pdev = c->pdev;
ef9814de 625 sq->tstamp = &priv->tstamp;
88a85f99
AS		 626 sq->mkey_be = c->mkey_be;
627 sq->channel = c;
628 sq->tc = tc;
629 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
630 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 631
632 return 0;
633
d3c9bc27
TT		 634err_free_sq_db:
635 mlx5e_free_sq_db(sq);
636
f62b8bb8
AV		 637err_sq_wq_destroy:
638 mlx5_wq_destroy(&sq->wq_ctrl);
639
640err_unmap_free_uar:
641 mlx5_unmap_free_uar(mdev, &sq->uar);
642
643 return err;
644}
645
646static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
647{
648 struct mlx5e_channel *c = sq->channel;
649 struct mlx5e_priv *priv = c->priv;
650
d3c9bc27 651 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 652 mlx5e_free_sq_db(sq);
653 mlx5_wq_destroy(&sq->wq_ctrl);
654 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
655}
656
657static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
658{
659 struct mlx5e_channel *c = sq->channel;
660 struct mlx5e_priv *priv = c->priv;
661 struct mlx5_core_dev *mdev = priv->mdev;
662
663 void *in;
664 void *sqc;
665 void *wq;
666 int inlen;
667 int err;
668
669 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
670 sizeof(u64) * sq->wq_ctrl.buf.npages;
671 in = mlx5_vzalloc(inlen);
672 if (!in)
673 return -ENOMEM;
674
675 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
676 wq = MLX5_ADDR_OF(sqc, sqc, wq);
677
678 memcpy(sqc, param->sqc, sizeof(param->sqc));
679
d3c9bc27
TT		 680 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
681 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
f62b8bb8 682 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 683 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 684 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
685
686 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
687 MLX5_SET(wq, wq, uar_page, sq->uar.index);
688 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 689 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 690 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
691
692 mlx5_fill_page_array(&sq->wq_ctrl.buf,
693 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
694
7db22ffb 695 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 696
697 kvfree(in);
698
699 return err;
700}
701
702static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
703{
704 struct mlx5e_channel *c = sq->channel;
705 struct mlx5e_priv *priv = c->priv;
706 struct mlx5_core_dev *mdev = priv->mdev;
707
708 void *in;
709 void *sqc;
710 int inlen;
711 int err;
712
713 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
714 in = mlx5_vzalloc(inlen);
715 if (!in)
716 return -ENOMEM;
717
718 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
719
720 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
721 MLX5_SET(sqc, sqc, state, next_state);
722
7db22ffb 723 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 724
725 kvfree(in);
726
727 return err;
728}
729
730static void mlx5e_disable_sq(struct mlx5e_sq *sq)
731{
732 struct mlx5e_channel *c = sq->channel;
733 struct mlx5e_priv *priv = c->priv;
734 struct mlx5_core_dev *mdev = priv->mdev;
735
7db22ffb 736 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 737}
738
739static int mlx5e_open_sq(struct mlx5e_channel *c,
740 int tc,
741 struct mlx5e_sq_param *param,
742 struct mlx5e_sq *sq)
743{
744 int err;
745
746 err = mlx5e_create_sq(c, tc, param, sq);
747 if (err)
748 return err;
749
750 err = mlx5e_enable_sq(sq, param);
751 if (err)
752 goto err_destroy_sq;
753
754 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
755 if (err)
756 goto err_disable_sq;
757
d3c9bc27
TT		 758 if (sq->txq) {
759 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
760 netdev_tx_reset_queue(sq->txq);
761 netif_tx_start_queue(sq->txq);
762 }
f62b8bb8
AV		 763
764 return 0;
765
766err_disable_sq:
767 mlx5e_disable_sq(sq);
768err_destroy_sq:
769 mlx5e_destroy_sq(sq);
770
771 return err;
772}
773
774static inline void netif_tx_disable_queue(struct netdev_queue *txq)
775{
776 __netif_tx_lock_bh(txq);
777 netif_tx_stop_queue(txq);
778 __netif_tx_unlock_bh(txq);
779}
780
781static void mlx5e_close_sq(struct mlx5e_sq *sq)
782{
d3c9bc27
TT		 783 if (sq->txq) {
784 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
785 /* prevent netif_tx_wake_queue */
786 napi_synchronize(&sq->channel->napi);
787 netif_tx_disable_queue(sq->txq);
f62b8bb8 788
d3c9bc27
TT		 789 /* ensure hw is notified of all pending wqes */
790 if (mlx5e_sq_has_room_for(sq, 1))
791 mlx5e_send_nop(sq, true);
792
793 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
794 }
f62b8bb8 795
f62b8bb8
AV		 796 while (sq->cc != sq->pc) /* wait till sq is empty */
797 msleep(20);
798
799 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
800 napi_synchronize(&sq->channel->napi);
801
802 mlx5e_disable_sq(sq);
803 mlx5e_destroy_sq(sq);
804}
805
806static int mlx5e_create_cq(struct mlx5e_channel *c,
807 struct mlx5e_cq_param *param,
808 struct mlx5e_cq *cq)
809{
810 struct mlx5e_priv *priv = c->priv;
811 struct mlx5_core_dev *mdev = priv->mdev;
812 struct mlx5_core_cq *mcq = &cq->mcq;
813 int eqn_not_used;
0b6e26ce 814 unsigned int irqn;
f62b8bb8
AV		 815 int err;
816 u32 i;
817
311c7c71
SM		 818 param->wq.buf_numa_node = cpu_to_node(c->cpu);
819 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 820 param->eq_ix = c->ix;
821
822 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
823 &cq->wq_ctrl);
824 if (err)
825 return err;
826
827 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
828
829 cq->napi = &c->napi;
830
831 mcq->cqe_sz = 64;
832 mcq->set_ci_db = cq->wq_ctrl.db.db;
833 mcq->arm_db = cq->wq_ctrl.db.db + 1;
834 *mcq->set_ci_db = 0;
835 *mcq->arm_db = 0;
836 mcq->vector = param->eq_ix;
837 mcq->comp = mlx5e_completion_event;
838 mcq->event = mlx5e_cq_error_event;
839 mcq->irqn = irqn;
840 mcq->uar = &priv->cq_uar;
841
842 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
843 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
844
845 cqe->op_own = 0xf1;
846 }
847
848 cq->channel = c;
50cfa25a 849 cq->priv = priv;
f62b8bb8
AV		 850
851 return 0;
852}
853
854static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
855{
856 mlx5_wq_destroy(&cq->wq_ctrl);
857}
858
859static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
860{
50cfa25a 861 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 862 struct mlx5_core_dev *mdev = priv->mdev;
863 struct mlx5_core_cq *mcq = &cq->mcq;
864
865 void *in;
866 void *cqc;
867 int inlen;
0b6e26ce 868 unsigned int irqn_not_used;
f62b8bb8
AV		 869 int eqn;
870 int err;
871
872 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
873 sizeof(u64) * cq->wq_ctrl.buf.npages;
874 in = mlx5_vzalloc(inlen);
875 if (!in)
876 return -ENOMEM;
877
878 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
879
880 memcpy(cqc, param->cqc, sizeof(param->cqc));
881
882 mlx5_fill_page_array(&cq->wq_ctrl.buf,
883 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
884
885 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
886
887 MLX5_SET(cqc, cqc, c_eqn, eqn);
888 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
889 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 890 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 891 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
892
893 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
894
895 kvfree(in);
896
897 if (err)
898 return err;
899
900 mlx5e_cq_arm(cq);
901
902 return 0;
903}
904
905static void mlx5e_disable_cq(struct mlx5e_cq *cq)
906{
50cfa25a 907 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 908 struct mlx5_core_dev *mdev = priv->mdev;
909
910 mlx5_core_destroy_cq(mdev, &cq->mcq);
911}
912
913static int mlx5e_open_cq(struct mlx5e_channel *c,
914 struct mlx5e_cq_param *param,
915 struct mlx5e_cq *cq,
916 u16 moderation_usecs,
917 u16 moderation_frames)
918{
919 int err;
920 struct mlx5e_priv *priv = c->priv;
921 struct mlx5_core_dev *mdev = priv->mdev;
922
923 err = mlx5e_create_cq(c, param, cq);
924 if (err)
925 return err;
926
927 err = mlx5e_enable_cq(cq, param);
928 if (err)
929 goto err_destroy_cq;
930
7524a5d8
GP		 931 if (MLX5_CAP_GEN(mdev, cq_moderation))
932 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
933 moderation_usecs,
934 moderation_frames);
f62b8bb8
AV		 935 return 0;
936
937err_destroy_cq:
938 mlx5e_destroy_cq(cq);
939
940 return err;
941}
942
943static void mlx5e_close_cq(struct mlx5e_cq *cq)
944{
945 mlx5e_disable_cq(cq);
946 mlx5e_destroy_cq(cq);
947}
948
949static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
950{
951 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
952}
953
954static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
955 struct mlx5e_channel_param *cparam)
956{
957 struct mlx5e_priv *priv = c->priv;
958 int err;
959 int tc;
960
961 for (tc = 0; tc < c->num_tc; tc++) {
962 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
963 priv->params.tx_cq_moderation_usec,
964 priv->params.tx_cq_moderation_pkts);
965 if (err)
966 goto err_close_tx_cqs;
f62b8bb8
AV		 967 }
968
969 return 0;
970
971err_close_tx_cqs:
972 for (tc--; tc >= 0; tc--)
973 mlx5e_close_cq(&c->sq[tc].cq);
974
975 return err;
976}
977
978static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
979{
980 int tc;
981
982 for (tc = 0; tc < c->num_tc; tc++)
983 mlx5e_close_cq(&c->sq[tc].cq);
984}
985
986static int mlx5e_open_sqs(struct mlx5e_channel *c,
987 struct mlx5e_channel_param *cparam)
988{
989 int err;
990 int tc;
991
992 for (tc = 0; tc < c->num_tc; tc++) {
993 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
994 if (err)
995 goto err_close_sqs;
996 }
997
998 return 0;
999
1000err_close_sqs:
1001 for (tc--; tc >= 0; tc--)
1002 mlx5e_close_sq(&c->sq[tc]);
1003
1004 return err;
1005}
1006
1007static void mlx5e_close_sqs(struct mlx5e_channel *c)
1008{
1009 int tc;
1010
1011 for (tc = 0; tc < c->num_tc; tc++)
1012 mlx5e_close_sq(&c->sq[tc]);
1013}
1014
5283af89 1015static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1016{
1017 int i;
1018
1019 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 1020 priv->channeltc_to_txq_map[ix][i] =
1021 ix + i * priv->params.num_channels;
03289b88
SM		 1022}
1023
f62b8bb8
AV		 1024static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1025 struct mlx5e_channel_param *cparam,
1026 struct mlx5e_channel **cp)
1027{
1028 struct net_device *netdev = priv->netdev;
1029 int cpu = mlx5e_get_cpu(priv, ix);
1030 struct mlx5e_channel *c;
1031 int err;
1032
1033 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1034 if (!c)
1035 return -ENOMEM;
1036
1037 c->priv = priv;
1038 c->ix = ix;
1039 c->cpu = cpu;
1040 c->pdev = &priv->mdev->pdev->dev;
1041 c->netdev = priv->netdev;
a606b0f6 1042 c->mkey_be = cpu_to_be32(priv->mkey.key);
a4418a6c 1043 c->num_tc = priv->params.num_tc;
f62b8bb8 1044
5283af89 1045 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1046
f62b8bb8
AV		 1047 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1048
d3c9bc27 1049 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
f62b8bb8
AV		 1050 if (err)
1051 goto err_napi_del;
1052
d3c9bc27
TT		 1053 err = mlx5e_open_tx_cqs(c, cparam);
1054 if (err)
1055 goto err_close_icosq_cq;
1056
f62b8bb8
AV		 1057 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1058 priv->params.rx_cq_moderation_usec,
1059 priv->params.rx_cq_moderation_pkts);
1060 if (err)
1061 goto err_close_tx_cqs;
f62b8bb8
AV		 1062
1063 napi_enable(&c->napi);
1064
d3c9bc27 1065 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1066 if (err)
1067 goto err_disable_napi;
1068
d3c9bc27
TT		 1069 err = mlx5e_open_sqs(c, cparam);
1070 if (err)
1071 goto err_close_icosq;
1072
f62b8bb8
AV		 1073 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1074 if (err)
1075 goto err_close_sqs;
1076
1077 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1078 *cp = c;
1079
1080 return 0;
1081
1082err_close_sqs:
1083 mlx5e_close_sqs(c);
1084
d3c9bc27
TT		 1085err_close_icosq:
1086 mlx5e_close_sq(&c->icosq);
1087
f62b8bb8
AV		 1088err_disable_napi:
1089 napi_disable(&c->napi);
1090 mlx5e_close_cq(&c->rq.cq);
1091
1092err_close_tx_cqs:
1093 mlx5e_close_tx_cqs(c);
1094
d3c9bc27
TT		 1095err_close_icosq_cq:
1096 mlx5e_close_cq(&c->icosq.cq);
1097
f62b8bb8
AV		 1098err_napi_del:
1099 netif_napi_del(&c->napi);
7ae92ae5 1100 napi_hash_del(&c->napi);
f62b8bb8
AV		 1101 kfree(c);
1102
1103 return err;
1104}
1105
1106static void mlx5e_close_channel(struct mlx5e_channel *c)
1107{
1108 mlx5e_close_rq(&c->rq);
1109 mlx5e_close_sqs(c);
d3c9bc27 1110 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1111 napi_disable(&c->napi);
1112 mlx5e_close_cq(&c->rq.cq);
1113 mlx5e_close_tx_cqs(c);
d3c9bc27 1114 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1115 netif_napi_del(&c->napi);
7ae92ae5
ED		 1116
1117 napi_hash_del(&c->napi);
1118 synchronize_rcu();
1119
f62b8bb8
AV		 1120 kfree(c);
1121}
1122
1123static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1124 struct mlx5e_rq_param *param)
1125{
1126 void *rqc = param->rqc;
1127 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1128
461017cb
TT		 1129 switch (priv->params.rq_wq_type) {
1130 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1131 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1132 MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1133 MLX5_SET(wq, wq, log_wqe_stride_size,
1134 MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1135 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1136 break;
1137 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1138 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1139 }
1140
f62b8bb8
AV		 1141 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1142 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1143 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1144 MLX5_SET(wq, wq, pd, priv->pdn);
593cf338 1145 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1146
311c7c71 1147 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1148 param->wq.linear = 1;
1149}
1150
556dd1b9
TT		 1151static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1152{
1153 void *rqc = param->rqc;
1154 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1155
1156 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1157 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1158}
1159
d3c9bc27
TT		 1160static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1161 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1162{
1163 void *sqc = param->sqc;
1164 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1165
f62b8bb8
AV		 1166 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1167 MLX5_SET(wq, wq, pd, priv->pdn);
1168
311c7c71 1169 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1170}
1171
1172static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1173 struct mlx5e_sq_param *param)
1174{
1175 void *sqc = param->sqc;
1176 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1177
1178 mlx5e_build_sq_param_common(priv, param);
1179 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1180
58d52291 1181 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1182}
1183
1184static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1185 struct mlx5e_cq_param *param)
1186{
1187 void *cqc = param->cqc;
1188
1189 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1190}
1191
1192static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1193 struct mlx5e_cq_param *param)
1194{
1195 void *cqc = param->cqc;
461017cb 1196 u8 log_cq_size;
f62b8bb8 1197
461017cb
TT		 1198 switch (priv->params.rq_wq_type) {
1199 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1200 log_cq_size = priv->params.log_rq_size +
1201 MLX5_MPWRQ_LOG_NUM_STRIDES;
1202 break;
1203 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1204 log_cq_size = priv->params.log_rq_size;
1205 }
1206
1207 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
f62b8bb8
AV		 1208
1209 mlx5e_build_common_cq_param(priv, param);
1210}
1211
1212static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1213 struct mlx5e_cq_param *param)
1214{
1215 void *cqc = param->cqc;
1216
d3c9bc27 1217 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1218
1219 mlx5e_build_common_cq_param(priv, param);
1220}
1221
d3c9bc27
TT		 1222static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1223 struct mlx5e_cq_param *param,
1224 u8 log_wq_size)
1225{
1226 void *cqc = param->cqc;
1227
1228 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1229
1230 mlx5e_build_common_cq_param(priv, param);
1231}
1232
1233static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1234 struct mlx5e_sq_param *param,
1235 u8 log_wq_size)
1236{
1237 void *sqc = param->sqc;
1238 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1239
1240 mlx5e_build_sq_param_common(priv, param);
1241
1242 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1243 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1244
1245 param->icosq = true;
1246}
1247
6b87663f 1248static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1249{
bc77b240 1250 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1251
f62b8bb8
AV		 1252 mlx5e_build_rq_param(priv, &cparam->rq);
1253 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1254 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1255 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1256 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1257 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1258}
1259
1260static int mlx5e_open_channels(struct mlx5e_priv *priv)
1261{
6b87663f 1262 struct mlx5e_channel_param *cparam;
a4418a6c 1263 int nch = priv->params.num_channels;
03289b88 1264 int err = -ENOMEM;
f62b8bb8
AV		 1265 int i;
1266 int j;
1267
a4418a6c
AS		 1268 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1269 GFP_KERNEL);
03289b88 1270
a4418a6c 1271 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1272 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1273
6b87663f
AB		 1274 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1275
1276 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1277 goto err_free_txq_to_sq_map;
f62b8bb8 1278
6b87663f
AB		 1279 mlx5e_build_channel_param(priv, cparam);
1280
a4418a6c 1281 for (i = 0; i < nch; i++) {
6b87663f 1282 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1283 if (err)
1284 goto err_close_channels;
1285 }
1286
a4418a6c 1287 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1288 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1289 if (err)
1290 goto err_close_channels;
1291 }
1292
6b87663f 1293 kfree(cparam);
f62b8bb8
AV		 1294 return 0;
1295
1296err_close_channels:
1297 for (i--; i >= 0; i--)
1298 mlx5e_close_channel(priv->channel[i]);
1299
03289b88
SM		 1300err_free_txq_to_sq_map:
1301 kfree(priv->txq_to_sq_map);
f62b8bb8 1302 kfree(priv->channel);
6b87663f 1303 kfree(cparam);
f62b8bb8
AV		 1304
1305 return err;
1306}
1307
1308static void mlx5e_close_channels(struct mlx5e_priv *priv)
1309{
1310 int i;
1311
1312 for (i = 0; i < priv->params.num_channels; i++)
1313 mlx5e_close_channel(priv->channel[i]);
1314
03289b88 1315 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1316 kfree(priv->channel);
1317}
1318
2be6967c
SM		 1319static int mlx5e_rx_hash_fn(int hfunc)
1320{
1321 return (hfunc == ETH_RSS_HASH_TOP) ?
1322 MLX5_RX_HASH_FN_TOEPLITZ :
1323 MLX5_RX_HASH_FN_INVERTED_XOR8;
1324}
1325
1326static int mlx5e_bits_invert(unsigned long a, int size)
1327{
1328 int inv = 0;
1329 int i;
1330
1331 for (i = 0; i < size; i++)
1332 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1333
1334 return inv;
1335}
1336
936896e9
AS		 1337static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1338{
1339 int i;
1340
1341 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1342 int ix = i;
1da36696 1343 u32 rqn;
936896e9
AS		 1344
1345 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1346 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1347
2d75b2bc 1348 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1349 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1350 priv->channel[ix]->rq.rqn :
1351 priv->drop_rq.rqn;
1352 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1353 }
1354}
1355
1da36696
TT		 1356static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1357 int ix)
4cbeaff5 1358{
1da36696
TT		 1359 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1360 priv->channel[ix]->rq.rqn :
1361 priv->drop_rq.rqn;
4cbeaff5 1362
1da36696 1363 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1364}
1365
1da36696 1366static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
f62b8bb8
AV		 1367{
1368 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1369 void *rqtc;
1370 int inlen;
1371 int err;
1da36696 1372 u32 *in;
f62b8bb8 1373
f62b8bb8
AV		 1374 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1375 in = mlx5_vzalloc(inlen);
1376 if (!in)
1377 return -ENOMEM;
1378
1379 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1380
1381 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1382 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1383
1da36696
TT		 1384 if (sz > 1) /* RSS */
1385 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1386 else
1387 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1388
1da36696 1389 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
f62b8bb8
AV		 1390
1391 kvfree(in);
1da36696
TT		 1392 return err;
1393}
1394
1395static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1396{
1397 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1398}
1399
1400static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1401{
1402 int nch = mlx5e_get_max_num_channels(priv->mdev);
1403 u32 *rqtn;
1404 int err;
1405 int ix;
1406
1407 /* Indirect RQT */
1408 rqtn = &priv->indir_rqtn;
1409 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1410 if (err)
1411 return err;
1412
1413 /* Direct RQTs */
1414 for (ix = 0; ix < nch; ix++) {
1415 rqtn = &priv->direct_tir[ix].rqtn;
1416 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1417 if (err)
1418 goto err_destroy_rqts;
1419 }
1420
1421 return 0;
1422
1423err_destroy_rqts:
1424 for (ix--; ix >= 0; ix--)
1425 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1426
1427 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
f62b8bb8
AV		 1428
1429 return err;
1430}
1431
1da36696
TT		 1432static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1433{
1434 int nch = mlx5e_get_max_num_channels(priv->mdev);
1435 int i;
1436
1437 for (i = 0; i < nch; i++)
1438 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1439
1440 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1441}
1442
1443int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1444{
1445 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1446 void *rqtc;
1447 int inlen;
1da36696 1448 u32 *in;
5c50368f
AS		 1449 int err;
1450
5c50368f
AS		 1451 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1452 in = mlx5_vzalloc(inlen);
1453 if (!in)
1454 return -ENOMEM;
1455
1456 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1457
1458 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1459 if (sz > 1) /* RSS */
1460 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1461 else
1462 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1463
1464 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1465
1da36696 1466 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1467
1468 kvfree(in);
1469
1470 return err;
1471}
1472
40ab6a6e
AS		 1473static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1474{
1da36696
TT		 1475 u32 rqtn;
1476 int ix;
1477
1478 rqtn = priv->indir_rqtn;
1479 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1480 for (ix = 0; ix < priv->params.num_channels; ix++) {
1481 rqtn = priv->direct_tir[ix].rqtn;
1482 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1483 }
40ab6a6e
AS		 1484}
1485
5c50368f
AS		 1486static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1487{
1488 if (!priv->params.lro_en)
1489 return;
1490
1491#define ROUGH_MAX_L2_L3_HDR_SZ 256
1492
1493 MLX5_SET(tirc, tirc, lro_enable_mask,
1494 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1495 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1496 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1497 (priv->params.lro_wqe_sz -
1498 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1499 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1500 MLX5_CAP_ETH(priv->mdev,
d9a40271 1501 lro_timer_supported_periods[2]));
5c50368f
AS		 1502}
1503
bdfc028d
TT		 1504void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1505{
1506 MLX5_SET(tirc, tirc, rx_hash_fn,
1507 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1508 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1509 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1510 rx_hash_toeplitz_key);
1511 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1512 rx_hash_toeplitz_key);
1513
1514 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1515 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1516 }
1517}
1518
ab0394fe 1519static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1520{
1521 struct mlx5_core_dev *mdev = priv->mdev;
1522
1523 void *in;
1524 void *tirc;
1525 int inlen;
1526 int err;
ab0394fe 1527 int tt;
1da36696 1528 int ix;
5c50368f
AS		 1529
1530 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1531 in = mlx5_vzalloc(inlen);
1532 if (!in)
1533 return -ENOMEM;
1534
1535 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1536 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1537
1538 mlx5e_build_tir_ctx_lro(tirc, priv);
1539
1da36696
TT		 1540 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1541 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1542 inlen);
ab0394fe 1543 if (err)
1da36696 1544 goto free_in;
ab0394fe 1545 }
5c50368f 1546
1da36696
TT		 1547 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1548 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1549 in, inlen);
1550 if (err)
1551 goto free_in;
1552 }
1553
1554free_in:
5c50368f
AS		 1555 kvfree(in);
1556
1557 return err;
1558}
1559
1da36696 1560static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
66189961
TT		 1561{
1562 void *in;
1563 int inlen;
1564 int err;
1da36696 1565 int i;
66189961
TT		 1566
1567 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1568 in = mlx5_vzalloc(inlen);
1569 if (!in)
1570 return -ENOMEM;
1571
1572 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1573
1da36696
TT		 1574 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1575 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1576 inlen);
1577 if (err)
1578 return err;
1579 }
66189961 1580
1da36696
TT		 1581 for (i = 0; i < priv->params.num_channels; i++) {
1582 err = mlx5_core_modify_tir(priv->mdev,
1583 priv->direct_tir[i].tirn, in,
1584 inlen);
66189961
TT		 1585 if (err)
1586 return err;
1587 }
1588
1da36696
TT		 1589 kvfree(in);
1590
66189961
TT		 1591 return 0;
1592}
1593
cd255eff 1594static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 1595{
40ab6a6e 1596 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 1597 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 1598 int err;
1599
cd255eff 1600 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 1601 if (err)
1602 return err;
1603
cd255eff
SM		 1604 /* Update vport context MTU */
1605 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1606 return 0;
1607}
40ab6a6e 1608
cd255eff
SM		 1609static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1610{
1611 struct mlx5_core_dev *mdev = priv->mdev;
1612 u16 hw_mtu = 0;
1613 int err;
40ab6a6e 1614
cd255eff
SM		 1615 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1616 if (err || !hw_mtu) /* fallback to port oper mtu */
1617 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1618
1619 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1620}
1621
1622static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1623{
1624 struct mlx5e_priv *priv = netdev_priv(netdev);
1625 u16 mtu;
1626 int err;
1627
1628 err = mlx5e_set_mtu(priv, netdev->mtu);
1629 if (err)
1630 return err;
40ab6a6e 1631
cd255eff
SM		 1632 mlx5e_query_mtu(priv, &mtu);
1633 if (mtu != netdev->mtu)
1634 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1635 __func__, mtu, netdev->mtu);
40ab6a6e 1636
cd255eff 1637 netdev->mtu = mtu;
40ab6a6e
AS		 1638 return 0;
1639}
1640
08fb1dac
SM		 1641static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1642{
1643 struct mlx5e_priv *priv = netdev_priv(netdev);
1644 int nch = priv->params.num_channels;
1645 int ntc = priv->params.num_tc;
1646 int tc;
1647
1648 netdev_reset_tc(netdev);
1649
1650 if (ntc == 1)
1651 return;
1652
1653 netdev_set_num_tc(netdev, ntc);
1654
1655 for (tc = 0; tc < ntc; tc++)
1656 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1657}
1658
40ab6a6e
AS		 1659int mlx5e_open_locked(struct net_device *netdev)
1660{
1661 struct mlx5e_priv *priv = netdev_priv(netdev);
1662 int num_txqs;
1663 int err;
1664
1665 set_bit(MLX5E_STATE_OPENED, &priv->state);
1666
08fb1dac
SM		 1667 mlx5e_netdev_set_tcs(netdev);
1668
40ab6a6e
AS		 1669 num_txqs = priv->params.num_channels * priv->params.num_tc;
1670 netif_set_real_num_tx_queues(netdev, num_txqs);
1671 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1672
1673 err = mlx5e_set_dev_port_mtu(netdev);
1674 if (err)
343b29f3 1675 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1676
1677 err = mlx5e_open_channels(priv);
1678 if (err) {
1679 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1680 __func__, err);
343b29f3 1681 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1682 }
1683
66189961
TT		 1684 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1685 if (err) {
1686 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1687 __func__, err);
1688 goto err_close_channels;
1689 }
1690
40ab6a6e 1691 mlx5e_redirect_rqts(priv);
ce89ef36 1692 mlx5e_update_carrier(priv);
ef9814de 1693 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 1694#ifdef CONFIG_RFS_ACCEL
1695 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1696#endif
40ab6a6e
AS		 1697
1698 schedule_delayed_work(&priv->update_stats_work, 0);
40ab6a6e 1699
9b37b07f 1700 return 0;
343b29f3 1701
66189961
TT		 1702err_close_channels:
1703 mlx5e_close_channels(priv);
343b29f3
AS		 1704err_clear_state_opened_flag:
1705 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1706 return err;
40ab6a6e
AS		 1707}
1708
1709static int mlx5e_open(struct net_device *netdev)
1710{
1711 struct mlx5e_priv *priv = netdev_priv(netdev);
1712 int err;
1713
1714 mutex_lock(&priv->state_lock);
1715 err = mlx5e_open_locked(netdev);
1716 mutex_unlock(&priv->state_lock);
1717
1718 return err;
1719}
1720
1721int mlx5e_close_locked(struct net_device *netdev)
1722{
1723 struct mlx5e_priv *priv = netdev_priv(netdev);
1724
a1985740
AS		 1725 /* May already be CLOSED in case a previous configuration operation
1726 * (e.g RX/TX queue size change) that involves close&open failed.
1727 */
1728 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1729 return 0;
1730
40ab6a6e
AS		 1731 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1732
ef9814de 1733 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1734 netif_carrier_off(priv->netdev);
ce89ef36 1735 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1736 mlx5e_close_channels(priv);
1737
1738 return 0;
1739}
1740
1741static int mlx5e_close(struct net_device *netdev)
1742{
1743 struct mlx5e_priv *priv = netdev_priv(netdev);
1744 int err;
1745
1746 mutex_lock(&priv->state_lock);
1747 err = mlx5e_close_locked(netdev);
1748 mutex_unlock(&priv->state_lock);
1749
1750 return err;
1751}
1752
1753static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1754 struct mlx5e_rq *rq,
1755 struct mlx5e_rq_param *param)
1756{
1757 struct mlx5_core_dev *mdev = priv->mdev;
1758 void *rqc = param->rqc;
1759 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1760 int err;
1761
1762 param->wq.db_numa_node = param->wq.buf_numa_node;
1763
1764 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1765 &rq->wq_ctrl);
1766 if (err)
1767 return err;
1768
1769 rq->priv = priv;
1770
1771 return 0;
1772}
1773
1774static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1775 struct mlx5e_cq *cq,
1776 struct mlx5e_cq_param *param)
1777{
1778 struct mlx5_core_dev *mdev = priv->mdev;
1779 struct mlx5_core_cq *mcq = &cq->mcq;
1780 int eqn_not_used;
0b6e26ce 1781 unsigned int irqn;
40ab6a6e
AS		 1782 int err;
1783
1784 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1785 &cq->wq_ctrl);
1786 if (err)
1787 return err;
1788
1789 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1790
1791 mcq->cqe_sz = 64;
1792 mcq->set_ci_db = cq->wq_ctrl.db.db;
1793 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1794 *mcq->set_ci_db = 0;
1795 *mcq->arm_db = 0;
1796 mcq->vector = param->eq_ix;
1797 mcq->comp = mlx5e_completion_event;
1798 mcq->event = mlx5e_cq_error_event;
1799 mcq->irqn = irqn;
1800 mcq->uar = &priv->cq_uar;
1801
1802 cq->priv = priv;
1803
1804 return 0;
1805}
1806
1807static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1808{
1809 struct mlx5e_cq_param cq_param;
1810 struct mlx5e_rq_param rq_param;
1811 struct mlx5e_rq *rq = &priv->drop_rq;
1812 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1813 int err;
1814
1815 memset(&cq_param, 0, sizeof(cq_param));
1816 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1817 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1818
1819 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1820 if (err)
1821 return err;
1822
1823 err = mlx5e_enable_cq(cq, &cq_param);
1824 if (err)
1825 goto err_destroy_cq;
1826
1827 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1828 if (err)
1829 goto err_disable_cq;
1830
1831 err = mlx5e_enable_rq(rq, &rq_param);
1832 if (err)
1833 goto err_destroy_rq;
1834
1835 return 0;
1836
1837err_destroy_rq:
1838 mlx5e_destroy_rq(&priv->drop_rq);
1839
1840err_disable_cq:
1841 mlx5e_disable_cq(&priv->drop_rq.cq);
1842
1843err_destroy_cq:
1844 mlx5e_destroy_cq(&priv->drop_rq.cq);
1845
1846 return err;
1847}
1848
1849static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1850{
1851 mlx5e_disable_rq(&priv->drop_rq);
1852 mlx5e_destroy_rq(&priv->drop_rq);
1853 mlx5e_disable_cq(&priv->drop_rq.cq);
1854 mlx5e_destroy_cq(&priv->drop_rq.cq);
1855}
1856
1857static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1858{
1859 struct mlx5_core_dev *mdev = priv->mdev;
1860 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1861 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1862
1863 memset(in, 0, sizeof(in));
1864
08fb1dac 1865 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1866 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1867
1868 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1869}
1870
1871static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1872{
1873 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1874}
1875
1876static int mlx5e_create_tises(struct mlx5e_priv *priv)
1877{
1878 int err;
1879 int tc;
1880
08fb1dac 1881 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1882 err = mlx5e_create_tis(priv, tc);
1883 if (err)
1884 goto err_close_tises;
1885 }
1886
1887 return 0;
1888
1889err_close_tises:
1890 for (tc--; tc >= 0; tc--)
1891 mlx5e_destroy_tis(priv, tc);
1892
1893 return err;
1894}
1895
1896static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1897{
1898 int tc;
1899
08fb1dac 1900 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 1901 mlx5e_destroy_tis(priv, tc);
1902}
1903
1da36696
TT		 1904static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1905 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 1906{
1907 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1908
3191e05f
AS		 1909 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1910
5a6f8aef
AS		 1911#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1912 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1913
5a6f8aef
AS		 1914#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1915 MLX5_HASH_FIELD_SEL_DST_IP |\
1916 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1917 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1918
a741749f
AS		 1919#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1920 MLX5_HASH_FIELD_SEL_DST_IP |\
1921 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1922
5c50368f 1923 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1924
4cbeaff5 1925 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1da36696
TT		 1926 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1927 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 1928
1929 switch (tt) {
1930 case MLX5E_TT_IPV4_TCP:
1931 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1932 MLX5_L3_PROT_TYPE_IPV4);
1933 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1934 MLX5_L4_PROT_TYPE_TCP);
1935 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1936 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1937 break;
1938
1939 case MLX5E_TT_IPV6_TCP:
1940 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1941 MLX5_L3_PROT_TYPE_IPV6);
1942 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1943 MLX5_L4_PROT_TYPE_TCP);
1944 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1945 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1946 break;
1947
1948 case MLX5E_TT_IPV4_UDP:
1949 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1950 MLX5_L3_PROT_TYPE_IPV4);
1951 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1952 MLX5_L4_PROT_TYPE_UDP);
1953 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1954 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1955 break;
1956
1957 case MLX5E_TT_IPV6_UDP:
1958 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1959 MLX5_L3_PROT_TYPE_IPV6);
1960 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1961 MLX5_L4_PROT_TYPE_UDP);
1962 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1963 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1964 break;
1965
a741749f
AS		 1966 case MLX5E_TT_IPV4_IPSEC_AH:
1967 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1968 MLX5_L3_PROT_TYPE_IPV4);
1969 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1970 MLX5_HASH_IP_IPSEC_SPI);
1971 break;
1972
1973 case MLX5E_TT_IPV6_IPSEC_AH:
1974 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1975 MLX5_L3_PROT_TYPE_IPV6);
1976 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1977 MLX5_HASH_IP_IPSEC_SPI);
1978 break;
1979
1980 case MLX5E_TT_IPV4_IPSEC_ESP:
1981 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1982 MLX5_L3_PROT_TYPE_IPV4);
1983 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1984 MLX5_HASH_IP_IPSEC_SPI);
1985 break;
1986
1987 case MLX5E_TT_IPV6_IPSEC_ESP:
1988 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1989 MLX5_L3_PROT_TYPE_IPV6);
1990 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1991 MLX5_HASH_IP_IPSEC_SPI);
1992 break;
1993
f62b8bb8
AV		 1994 case MLX5E_TT_IPV4:
1995 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1996 MLX5_L3_PROT_TYPE_IPV4);
1997 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1998 MLX5_HASH_IP);
1999 break;
2000
2001 case MLX5E_TT_IPV6:
2002 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2003 MLX5_L3_PROT_TYPE_IPV6);
2004 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2005 MLX5_HASH_IP);
2006 break;
1da36696
TT		 2007 default:
2008 WARN_ONCE(true,
2009 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2010 }
2011}
2012
1da36696
TT		 2013static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2014 u32 rqtn)
f62b8bb8 2015{
1da36696
TT		 2016 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2017
2018 mlx5e_build_tir_ctx_lro(tirc, priv);
2019
2020 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2021 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2022 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2023}
2024
2025static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2026{
2027 int nch = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 2028 void *tirc;
2029 int inlen;
1da36696 2030 u32 *tirn;
f62b8bb8 2031 int err;
1da36696
TT		 2032 u32 *in;
2033 int ix;
2034 int tt;
f62b8bb8
AV		 2035
2036 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2037 in = mlx5_vzalloc(inlen);
2038 if (!in)
2039 return -ENOMEM;
2040
1da36696
TT		 2041 /* indirect tirs */
2042 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2043 memset(in, 0, inlen);
2044 tirn = &priv->indir_tirn[tt];
2045 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2046 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2047 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
f62b8bb8 2048 if (err)
40ab6a6e 2049 goto err_destroy_tirs;
f62b8bb8
AV		 2050 }
2051
1da36696
TT		 2052 /* direct tirs */
2053 for (ix = 0; ix < nch; ix++) {
2054 memset(in, 0, inlen);
2055 tirn = &priv->direct_tir[ix].tirn;
2056 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2057 mlx5e_build_direct_tir_ctx(priv, tirc,
2058 priv->direct_tir[ix].rqtn);
2059 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2060 if (err)
2061 goto err_destroy_ch_tirs;
2062 }
2063
2064 kvfree(in);
2065
f62b8bb8
AV		 2066 return 0;
2067
1da36696
TT		 2068err_destroy_ch_tirs:
2069 for (ix--; ix >= 0; ix--)
2070 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2071
40ab6a6e 2072err_destroy_tirs:
1da36696
TT		 2073 for (tt--; tt >= 0; tt--)
2074 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2075
2076 kvfree(in);
f62b8bb8
AV		 2077
2078 return err;
2079}
2080
40ab6a6e 2081static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8 2082{
1da36696 2083 int nch = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 2084 int i;
2085
1da36696
TT		 2086 for (i = 0; i < nch; i++)
2087 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2088
2089 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2090 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
f62b8bb8
AV		 2091}
2092
36350114
GP		 2093int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2094{
2095 int err = 0;
2096 int i;
2097
2098 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2099 return 0;
2100
2101 for (i = 0; i < priv->params.num_channels; i++) {
2102 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2103 if (err)
2104 return err;
2105 }
2106
2107 return 0;
2108}
2109
08fb1dac
SM		 2110static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2111{
2112 struct mlx5e_priv *priv = netdev_priv(netdev);
2113 bool was_opened;
2114 int err = 0;
2115
2116 if (tc && tc != MLX5E_MAX_NUM_TC)
2117 return -EINVAL;
2118
2119 mutex_lock(&priv->state_lock);
2120
2121 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2122 if (was_opened)
2123 mlx5e_close_locked(priv->netdev);
2124
2125 priv->params.num_tc = tc ? tc : 1;
2126
2127 if (was_opened)
2128 err = mlx5e_open_locked(priv->netdev);
2129
2130 mutex_unlock(&priv->state_lock);
2131
2132 return err;
2133}
2134
2135static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2136 __be16 proto, struct tc_to_netdev *tc)
2137{
e8f887ac
AV		 2138 struct mlx5e_priv *priv = netdev_priv(dev);
2139
2140 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2141 goto mqprio;
2142
2143 switch (tc->type) {
e3a2b7ed
AV		 2144 case TC_SETUP_CLSFLOWER:
2145 switch (tc->cls_flower->command) {
2146 case TC_CLSFLOWER_REPLACE:
2147 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2148 case TC_CLSFLOWER_DESTROY:
2149 return mlx5e_delete_flower(priv, tc->cls_flower);
2150 }
e8f887ac
AV		 2151 default:
2152 return -EOPNOTSUPP;
2153 }
2154
2155mqprio:
67ba422e 2156 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2157 return -EINVAL;
2158
2159 return mlx5e_setup_tc(dev, tc->tc);
2160}
2161
f62b8bb8
AV		 2162static struct rtnl_link_stats64 *
2163mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2164{
2165 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2166 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2167 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2168 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2169
9218b44d
GP		 2170 stats->rx_packets = sstats->rx_packets;
2171 stats->rx_bytes = sstats->rx_bytes;
2172 stats->tx_packets = sstats->tx_packets;
2173 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2174
2175 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2176 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2177
2178 stats->rx_length_errors =
9218b44d
GP		 2179 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2180 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2181 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2182 stats->rx_crc_errors =
9218b44d
GP		 2183 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2184 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2185 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2186 stats->tx_carrier_errors =
9218b44d 2187 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2188 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2189 stats->rx_frame_errors;
2190 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2191
2192 /* vport multicast also counts packets that are dropped due to steering
2193 * or rx out of buffer
2194 */
9218b44d
GP		 2195 stats->multicast =
2196 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2197
2198 return stats;
2199}
2200
2201static void mlx5e_set_rx_mode(struct net_device *dev)
2202{
2203 struct mlx5e_priv *priv = netdev_priv(dev);
2204
2205 schedule_work(&priv->set_rx_mode_work);
2206}
2207
2208static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2209{
2210 struct mlx5e_priv *priv = netdev_priv(netdev);
2211 struct sockaddr *saddr = addr;
2212
2213 if (!is_valid_ether_addr(saddr->sa_data))
2214 return -EADDRNOTAVAIL;
2215
2216 netif_addr_lock_bh(netdev);
2217 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2218 netif_addr_unlock_bh(netdev);
2219
2220 schedule_work(&priv->set_rx_mode_work);
2221
2222 return 0;
2223}
2224
0e405443
GP		 2225#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2226 do { \
2227 if (enable) \
2228 netdev->features |= feature; \
2229 else \
2230 netdev->features &= ~feature; \
2231 } while (0)
2232
2233typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2234
2235static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2236{
2237 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2238 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2239 int err;
f62b8bb8
AV		 2240
2241 mutex_lock(&priv->state_lock);
f62b8bb8 2242
0e405443
GP		 2243 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2244 mlx5e_close_locked(priv->netdev);
98e81b0a 2245
0e405443
GP		 2246 priv->params.lro_en = enable;
2247 err = mlx5e_modify_tirs_lro(priv);
2248 if (err) {
2249 netdev_err(netdev, "lro modify failed, %d\n", err);
2250 priv->params.lro_en = !enable;
98e81b0a 2251 }
f62b8bb8 2252
0e405443
GP		 2253 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2254 mlx5e_open_locked(priv->netdev);
2255
9b37b07f
AS		 2256 mutex_unlock(&priv->state_lock);
2257
0e405443
GP		 2258 return err;
2259}
2260
2261static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2262{
2263 struct mlx5e_priv *priv = netdev_priv(netdev);
2264
2265 if (enable)
2266 mlx5e_enable_vlan_filter(priv);
2267 else
2268 mlx5e_disable_vlan_filter(priv);
2269
2270 return 0;
2271}
2272
2273static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2274{
2275 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2276
0e405443 2277 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2278 netdev_err(netdev,
2279 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2280 return -EINVAL;
2281 }
2282
0e405443
GP		 2283 return 0;
2284}
2285
94cb1ebb
EBE		 2286static int set_feature_rx_all(struct net_device *netdev, bool enable)
2287{
2288 struct mlx5e_priv *priv = netdev_priv(netdev);
2289 struct mlx5_core_dev *mdev = priv->mdev;
2290
2291 return mlx5_set_port_fcs(mdev, !enable);
2292}
2293
36350114
GP		 2294static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2295{
2296 struct mlx5e_priv *priv = netdev_priv(netdev);
2297 int err;
2298
2299 mutex_lock(&priv->state_lock);
2300
2301 priv->params.vlan_strip_disable = !enable;
2302 err = mlx5e_modify_rqs_vsd(priv, !enable);
2303 if (err)
2304 priv->params.vlan_strip_disable = enable;
2305
2306 mutex_unlock(&priv->state_lock);
2307
2308 return err;
2309}
2310
0e405443
GP		 2311static int mlx5e_handle_feature(struct net_device *netdev,
2312 netdev_features_t wanted_features,
2313 netdev_features_t feature,
2314 mlx5e_feature_handler feature_handler)
2315{
2316 netdev_features_t changes = wanted_features ^ netdev->features;
2317 bool enable = !!(wanted_features & feature);
2318 int err;
2319
2320 if (!(changes & feature))
2321 return 0;
2322
2323 err = feature_handler(netdev, enable);
2324 if (err) {
2325 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2326 enable ? "Enable" : "Disable", feature, err);
2327 return err;
2328 }
2329
2330 MLX5E_SET_FEATURE(netdev, feature, enable);
2331 return 0;
2332}
2333
2334static int mlx5e_set_features(struct net_device *netdev,
2335 netdev_features_t features)
2336{
2337 int err;
2338
2339 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2340 set_feature_lro);
2341 err |= mlx5e_handle_feature(netdev, features,
2342 NETIF_F_HW_VLAN_CTAG_FILTER,
2343 set_feature_vlan_filter);
2344 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2345 set_feature_tc_num_filters);
94cb1ebb
EBE		 2346 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2347 set_feature_rx_all);
36350114
GP		 2348 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2349 set_feature_rx_vlan);
0e405443
GP		 2350
2351 return err ? -EINVAL : 0;
f62b8bb8
AV		 2352}
2353
d8edd246
SM		 2354#define MXL5_HW_MIN_MTU 64
2355#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2356
f62b8bb8
AV		 2357static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2358{
2359 struct mlx5e_priv *priv = netdev_priv(netdev);
2360 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2361 bool was_opened;
046339ea 2362 u16 max_mtu;
d8edd246 2363 u16 min_mtu;
98e81b0a 2364 int err = 0;
f62b8bb8 2365
facc9699 2366 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2367
50a9eea6 2368 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2369 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2370
d8edd246 2371 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2372 netdev_err(netdev,
d8edd246
SM		 2373 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2374 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2375 return -EINVAL;
2376 }
2377
2378 mutex_lock(&priv->state_lock);
98e81b0a
AS		 2379
2380 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2381 if (was_opened)
2382 mlx5e_close_locked(netdev);
2383
f62b8bb8 2384 netdev->mtu = new_mtu;
98e81b0a
AS		 2385
2386 if (was_opened)
2387 err = mlx5e_open_locked(netdev);
2388
f62b8bb8
AV		 2389 mutex_unlock(&priv->state_lock);
2390
2391 return err;
2392}
2393
ef9814de
EBE		 2394static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2395{
2396 switch (cmd) {
2397 case SIOCSHWTSTAMP:
2398 return mlx5e_hwstamp_set(dev, ifr);
2399 case SIOCGHWTSTAMP:
2400 return mlx5e_hwstamp_get(dev, ifr);
2401 default:
2402 return -EOPNOTSUPP;
2403 }
2404}
2405
66e49ded
SM		 2406static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2407{
2408 struct mlx5e_priv *priv = netdev_priv(dev);
2409 struct mlx5_core_dev *mdev = priv->mdev;
2410
2411 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2412}
2413
2414static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2415{
2416 struct mlx5e_priv *priv = netdev_priv(dev);
2417 struct mlx5_core_dev *mdev = priv->mdev;
2418
2419 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2420 vlan, qos);
2421}
2422
2423static int mlx5_vport_link2ifla(u8 esw_link)
2424{
2425 switch (esw_link) {
2426 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2427 return IFLA_VF_LINK_STATE_DISABLE;
2428 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2429 return IFLA_VF_LINK_STATE_ENABLE;
2430 }
2431 return IFLA_VF_LINK_STATE_AUTO;
2432}
2433
2434static int mlx5_ifla_link2vport(u8 ifla_link)
2435{
2436 switch (ifla_link) {
2437 case IFLA_VF_LINK_STATE_DISABLE:
2438 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2439 case IFLA_VF_LINK_STATE_ENABLE:
2440 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2441 }
2442 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2443}
2444
2445static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2446 int link_state)
2447{
2448 struct mlx5e_priv *priv = netdev_priv(dev);
2449 struct mlx5_core_dev *mdev = priv->mdev;
2450
2451 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2452 mlx5_ifla_link2vport(link_state));
2453}
2454
2455static int mlx5e_get_vf_config(struct net_device *dev,
2456 int vf, struct ifla_vf_info *ivi)
2457{
2458 struct mlx5e_priv *priv = netdev_priv(dev);
2459 struct mlx5_core_dev *mdev = priv->mdev;
2460 int err;
2461
2462 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2463 if (err)
2464 return err;
2465 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2466 return 0;
2467}
2468
2469static int mlx5e_get_vf_stats(struct net_device *dev,
2470 int vf, struct ifla_vf_stats *vf_stats)
2471{
2472 struct mlx5e_priv *priv = netdev_priv(dev);
2473 struct mlx5_core_dev *mdev = priv->mdev;
2474
2475 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2476 vf_stats);
2477}
2478
b3f63c3d
MF		 2479static void mlx5e_add_vxlan_port(struct net_device *netdev,
2480 sa_family_t sa_family, __be16 port)
2481{
2482 struct mlx5e_priv *priv = netdev_priv(netdev);
2483
2484 if (!mlx5e_vxlan_allowed(priv->mdev))
2485 return;
2486
2487 mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2488}
2489
2490static void mlx5e_del_vxlan_port(struct net_device *netdev,
2491 sa_family_t sa_family, __be16 port)
2492{
2493 struct mlx5e_priv *priv = netdev_priv(netdev);
2494
2495 if (!mlx5e_vxlan_allowed(priv->mdev))
2496 return;
2497
2498 mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2499}
2500
2501static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2502 struct sk_buff *skb,
2503 netdev_features_t features)
2504{
2505 struct udphdr *udph;
2506 u16 proto;
2507 u16 port = 0;
2508
2509 switch (vlan_get_protocol(skb)) {
2510 case htons(ETH_P_IP):
2511 proto = ip_hdr(skb)->protocol;
2512 break;
2513 case htons(ETH_P_IPV6):
2514 proto = ipv6_hdr(skb)->nexthdr;
2515 break;
2516 default:
2517 goto out;
2518 }
2519
2520 if (proto == IPPROTO_UDP) {
2521 udph = udp_hdr(skb);
2522 port = be16_to_cpu(udph->dest);
2523 }
2524
2525 /* Verify if UDP port is being offloaded by HW */
2526 if (port && mlx5e_vxlan_lookup_port(priv, port))
2527 return features;
2528
2529out:
2530 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2531 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2532}
2533
2534static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2535 struct net_device *netdev,
2536 netdev_features_t features)
2537{
2538 struct mlx5e_priv *priv = netdev_priv(netdev);
2539
2540 features = vlan_features_check(skb, features);
2541 features = vxlan_features_check(skb, features);
2542
2543 /* Validate if the tunneled packet is being offloaded by HW */
2544 if (skb->encapsulation &&
2545 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2546 return mlx5e_vxlan_features_check(priv, skb, features);
2547
2548 return features;
2549}
2550
b0eed40e 2551static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2552 .ndo_open = mlx5e_open,
2553 .ndo_stop = mlx5e_close,
2554 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2555 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2556 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2557 .ndo_get_stats64 = mlx5e_get_stats,
2558 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2559 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2560 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2561 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2562 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2563 .ndo_change_mtu = mlx5e_change_mtu,
2564 .ndo_do_ioctl = mlx5e_ioctl,
2565};
2566
2567static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2568 .ndo_open = mlx5e_open,
2569 .ndo_stop = mlx5e_close,
2570 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2571 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2572 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2573 .ndo_get_stats64 = mlx5e_get_stats,
2574 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2575 .ndo_set_mac_address = mlx5e_set_mac,
2576 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2577 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2578 .ndo_set_features = mlx5e_set_features,
2579 .ndo_change_mtu = mlx5e_change_mtu,
2580 .ndo_do_ioctl = mlx5e_ioctl,
b3f63c3d
MF		 2581 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2582 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2583 .ndo_features_check = mlx5e_features_check,
b0eed40e
SM		 2584 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2585 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2586 .ndo_get_vf_config = mlx5e_get_vf_config,
2587 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2588 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2589};
2590
2591static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2592{
2593 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2594 return -ENOTSUPP;
2595 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2596 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2597 !MLX5_CAP_ETH(mdev, csum_cap) ||
2598 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2599 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2600 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2601 MLX5_CAP_FLOWTABLE(mdev,
2602 flow_table_properties_nic_receive.max_ft_level)
2603 < 3) {
f62b8bb8
AV		 2604 mlx5_core_warn(mdev,
2605 "Not creating net device, some required device capabilities are missing\n");
2606 return -ENOTSUPP;
2607 }
66189961
TT		 2608 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2609 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2610 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2611 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2612
f62b8bb8
AV		 2613 return 0;
2614}
2615
58d52291
AS		 2616u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2617{
2618 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2619
2620 return bf_buf_size -
2621 sizeof(struct mlx5e_tx_wqe) +
2622 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2623}
2624
08fb1dac
SM		 2625#ifdef CONFIG_MLX5_CORE_EN_DCB
2626static void mlx5e_ets_init(struct mlx5e_priv *priv)
2627{
2628 int i;
2629
2630 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2631 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2632 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2633 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2634 priv->params.ets.prio_tc[i] = i;
2635 }
2636
2637 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2638 priv->params.ets.prio_tc[0] = 1;
2639 priv->params.ets.prio_tc[1] = 0;
2640}
2641#endif
2642
d8c9660d
TT		 2643void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2644 u32 *indirection_rqt, int len,
85082dba
TT		 2645 int num_channels)
2646{
d8c9660d
TT		 2647 int node = mdev->priv.numa_node;
2648 int node_num_of_cores;
85082dba
TT		 2649 int i;
2650
d8c9660d
TT		 2651 if (node == -1)
2652 node = first_online_node;
2653
2654 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2655
2656 if (node_num_of_cores)
2657 num_channels = min_t(int, num_channels, node_num_of_cores);
2658
85082dba
TT		 2659 for (i = 0; i < len; i++)
2660 indirection_rqt[i] = i % num_channels;
2661}
2662
bc77b240
TT		 2663static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2664{
2665 return MLX5_CAP_GEN(mdev, striding_rq) &&
2666 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2667 MLX5_CAP_ETH(mdev, reg_umr_sq);
2668}
2669
f62b8bb8
AV		 2670static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2671 struct net_device *netdev,
936896e9 2672 int num_channels)
f62b8bb8
AV		 2673{
2674 struct mlx5e_priv *priv = netdev_priv(netdev);
2675
2676 priv->params.log_sq_size =
2677 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 2678 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 2679 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2680 MLX5_WQ_TYPE_LINKED_LIST;
2681
2682 switch (priv->params.rq_wq_type) {
2683 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2684 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2685 priv->params.lro_en = true;
2686 break;
2687 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2688 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2689 }
2690
2691 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2692 BIT(priv->params.log_rq_size));
f62b8bb8
AV		 2693 priv->params.rx_cq_moderation_usec =
2694 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2695 priv->params.rx_cq_moderation_pkts =
2696 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2697 priv->params.tx_cq_moderation_usec =
2698 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2699 priv->params.tx_cq_moderation_pkts =
2700 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2701 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8 2702 priv->params.num_tc = 1;
2be6967c 2703 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2704
57afead5
AS		 2705 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2706 sizeof(priv->params.toeplitz_hash_key));
2707
d8c9660d 2708 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
85082dba 2709 MLX5E_INDIR_RQT_SIZE, num_channels);
2d75b2bc 2710
f62b8bb8
AV		 2711 priv->params.lro_wqe_sz =
2712 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2713
2714 priv->mdev = mdev;
2715 priv->netdev = netdev;
936896e9 2716 priv->params.num_channels = num_channels;
f62b8bb8 2717
08fb1dac
SM		 2718#ifdef CONFIG_MLX5_CORE_EN_DCB
2719 mlx5e_ets_init(priv);
2720#endif
f62b8bb8 2721
f62b8bb8
AV		 2722 mutex_init(&priv->state_lock);
2723
2724 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2725 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2726 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2727}
2728
2729static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2730{
2731 struct mlx5e_priv *priv = netdev_priv(netdev);
2732
e1d7d349 2733 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2734 if (is_zero_ether_addr(netdev->dev_addr) &&
2735 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2736 eth_hw_addr_random(netdev);
2737 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2738 }
f62b8bb8
AV		 2739}
2740
2741static void mlx5e_build_netdev(struct net_device *netdev)
2742{
2743 struct mlx5e_priv *priv = netdev_priv(netdev);
2744 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 2745 bool fcs_supported;
2746 bool fcs_enabled;
f62b8bb8
AV		 2747
2748 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2749
08fb1dac 2750 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2751 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2752#ifdef CONFIG_MLX5_CORE_EN_DCB
2753 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2754#endif
2755 } else {
b0eed40e 2756 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2757 }
66e49ded 2758
f62b8bb8
AV		 2759 netdev->watchdog_timeo = 15 * HZ;
2760
2761 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2762
12be4b21 2763 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2764 netdev->vlan_features |= NETIF_F_IP_CSUM;
2765 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2766 netdev->vlan_features |= NETIF_F_GRO;
2767 netdev->vlan_features |= NETIF_F_TSO;
2768 netdev->vlan_features |= NETIF_F_TSO6;
2769 netdev->vlan_features |= NETIF_F_RXCSUM;
2770 netdev->vlan_features |= NETIF_F_RXHASH;
2771
2772 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2773 netdev->vlan_features |= NETIF_F_LRO;
2774
2775 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2776 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2777 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2778 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2779
b3f63c3d
MF		 2780 if (mlx5e_vxlan_allowed(mdev)) {
2781 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2782 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2783 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2784 netdev->hw_enc_features |= NETIF_F_TSO;
2785 netdev->hw_enc_features |= NETIF_F_TSO6;
2786 netdev->hw_enc_features |= NETIF_F_RXHASH;
2787 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2788 }
2789
94cb1ebb
EBE		 2790 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2791
2792 if (fcs_supported)
2793 netdev->hw_features |= NETIF_F_RXALL;
2794
f62b8bb8
AV		 2795 netdev->features = netdev->hw_features;
2796 if (!priv->params.lro_en)
2797 netdev->features &= ~NETIF_F_LRO;
2798
94cb1ebb
EBE		 2799 if (fcs_enabled)
2800 netdev->features &= ~NETIF_F_RXALL;
2801
e8f887ac
AV		 2802#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2803 if (FT_CAP(flow_modify_en) &&
2804 FT_CAP(modify_root) &&
2805 FT_CAP(identified_miss_table_mode) &&
2806 FT_CAP(flow_table_modify))
2807 priv->netdev->hw_features |= NETIF_F_HW_TC;
2808
f62b8bb8
AV		 2809 netdev->features |= NETIF_F_HIGHDMA;
2810
2811 netdev->priv_flags |= IFF_UNICAST_FLT;
2812
2813 mlx5e_set_netdev_dev_addr(netdev);
2814}
2815
2816static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
a606b0f6 2817 struct mlx5_core_mkey *mkey)
f62b8bb8
AV		 2818{
2819 struct mlx5_core_dev *mdev = priv->mdev;
2820 struct mlx5_create_mkey_mbox_in *in;
2821 int err;
2822
2823 in = mlx5_vzalloc(sizeof(*in));
2824 if (!in)
2825 return -ENOMEM;
2826
2827 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2828 MLX5_PERM_LOCAL_READ |
2829 MLX5_ACCESS_MODE_PA;
2830 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2831 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2832
a606b0f6 2833 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
f62b8bb8
AV		 2834 NULL);
2835
2836 kvfree(in);
2837
2838 return err;
2839}
2840
593cf338
RS		 2841static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2842{
2843 struct mlx5_core_dev *mdev = priv->mdev;
2844 int err;
2845
2846 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2847 if (err) {
2848 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2849 priv->q_counter = 0;
2850 }
2851}
2852
2853static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2854{
2855 if (!priv->q_counter)
2856 return;
2857
2858 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2859}
2860
bc77b240
TT		 2861static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2862{
2863 struct mlx5_core_dev *mdev = priv->mdev;
2864 struct mlx5_create_mkey_mbox_in *in;
2865 struct mlx5_mkey_seg *mkc;
2866 int inlen = sizeof(*in);
2867 u64 npages =
2868 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2869 int err;
2870
2871 in = mlx5_vzalloc(inlen);
2872 if (!in)
2873 return -ENOMEM;
2874
2875 mkc = &in->seg;
2876 mkc->status = MLX5_MKEY_STATUS_FREE;
2877 mkc->flags = MLX5_PERM_UMR_EN |
2878 MLX5_PERM_LOCAL_READ |
2879 MLX5_PERM_LOCAL_WRITE |
2880 MLX5_ACCESS_MODE_MTT;
2881
2882 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2883 mkc->flags_pd = cpu_to_be32(priv->pdn);
2884 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2885 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2886 mkc->log2_page_size = PAGE_SHIFT;
2887
2888 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2889 NULL, NULL);
2890
2891 kvfree(in);
2892
2893 return err;
2894}
2895
f62b8bb8
AV		 2896static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2897{
2898 struct net_device *netdev;
2899 struct mlx5e_priv *priv;
3435ab59 2900 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 2901 int err;
2902
2903 if (mlx5e_check_required_hca_cap(mdev))
2904 return NULL;
2905
08fb1dac
SM		 2906 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2907 nch * MLX5E_MAX_NUM_TC,
2908 nch);
f62b8bb8
AV		 2909 if (!netdev) {
2910 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2911 return NULL;
2912 }
2913
936896e9 2914 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 2915 mlx5e_build_netdev(netdev);
2916
2917 netif_carrier_off(netdev);
2918
2919 priv = netdev_priv(netdev);
2920
0ba42241 2921 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
f62b8bb8 2922 if (err) {
1f2a3003 2923 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2924 goto err_free_netdev;
2925 }
2926
2927 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2928 if (err) {
1f2a3003 2929 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2930 goto err_unmap_free_uar;
2931 }
2932
8d7f9ecb 2933 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 2934 if (err) {
1f2a3003 2935 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2936 goto err_dealloc_pd;
2937 }
2938
a606b0f6 2939 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
f62b8bb8 2940 if (err) {
1f2a3003 2941 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2942 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2943 }
2944
bc77b240
TT		 2945 err = mlx5e_create_umr_mkey(priv);
2946 if (err) {
2947 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2948 goto err_destroy_mkey;
2949 }
2950
40ab6a6e 2951 err = mlx5e_create_tises(priv);
5c50368f 2952 if (err) {
40ab6a6e 2953 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
bc77b240 2954 goto err_destroy_umr_mkey;
5c50368f
AS		 2955 }
2956
2957 err = mlx5e_open_drop_rq(priv);
2958 if (err) {
2959 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 2960 goto err_destroy_tises;
5c50368f
AS		 2961 }
2962
1da36696 2963 err = mlx5e_create_rqts(priv);
5c50368f 2964 if (err) {
1da36696 2965 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
5c50368f
AS		 2966 goto err_close_drop_rq;
2967 }
2968
40ab6a6e 2969 err = mlx5e_create_tirs(priv);
5c50368f 2970 if (err) {
40ab6a6e 2971 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
1da36696 2972 goto err_destroy_rqts;
5c50368f
AS		 2973 }
2974
acff797c 2975 err = mlx5e_create_flow_steering(priv);
5c50368f 2976 if (err) {
acff797c 2977 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
40ab6a6e 2978 goto err_destroy_tirs;
5c50368f
AS		 2979 }
2980
593cf338
RS		 2981 mlx5e_create_q_counter(priv);
2982
33cfaaa8 2983 mlx5e_init_l2_addr(priv);
5c50368f 2984
b3f63c3d
MF		 2985 mlx5e_vxlan_init(priv);
2986
e8f887ac
AV		 2987 err = mlx5e_tc_init(priv);
2988 if (err)
593cf338 2989 goto err_dealloc_q_counters;
e8f887ac 2990
08fb1dac
SM		 2991#ifdef CONFIG_MLX5_CORE_EN_DCB
2992 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2993#endif
2994
f62b8bb8
AV		 2995 err = register_netdev(netdev);
2996 if (err) {
1f2a3003 2997 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
e8f887ac 2998 goto err_tc_cleanup;
f62b8bb8
AV		 2999 }
3000
01a14098
MF		 3001 if (mlx5e_vxlan_allowed(mdev)) {
3002 rtnl_lock();
b3f63c3d 3003 vxlan_get_rx_port(netdev);
01a14098
MF		 3004 rtnl_unlock();
3005 }
b3f63c3d 3006
f62b8bb8 3007 mlx5e_enable_async_events(priv);
9b37b07f 3008 schedule_work(&priv->set_rx_mode_work);
f62b8bb8
AV		 3009
3010 return priv;
3011
e8f887ac
AV		 3012err_tc_cleanup:
3013 mlx5e_tc_cleanup(priv);
3014
593cf338
RS		 3015err_dealloc_q_counters:
3016 mlx5e_destroy_q_counter(priv);
acff797c 3017 mlx5e_destroy_flow_steering(priv);
5c50368f 3018
40ab6a6e
AS		 3019err_destroy_tirs:
3020 mlx5e_destroy_tirs(priv);
5c50368f 3021
1da36696
TT		 3022err_destroy_rqts:
3023 mlx5e_destroy_rqts(priv);
5c50368f
AS		 3024
3025err_close_drop_rq:
3026 mlx5e_close_drop_rq(priv);
3027
40ab6a6e
AS		 3028err_destroy_tises:
3029 mlx5e_destroy_tises(priv);
5c50368f 3030
bc77b240
TT		 3031err_destroy_umr_mkey:
3032 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3033
f62b8bb8 3034err_destroy_mkey:
a606b0f6 3035 mlx5_core_destroy_mkey(mdev, &priv->mkey);
f62b8bb8 3036
3191e05f 3037err_dealloc_transport_domain:
8d7f9ecb 3038 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 3039
f62b8bb8
AV		 3040err_dealloc_pd:
3041 mlx5_core_dealloc_pd(mdev, priv->pdn);
3042
3043err_unmap_free_uar:
3044 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3045
3046err_free_netdev:
3047 free_netdev(netdev);
3048
3049 return NULL;
3050}
3051
3052static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3053{
3054 struct mlx5e_priv *priv = vpriv;
3055 struct net_device *netdev = priv->netdev;
3056
9b37b07f
AS		 3057 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3058
3059 schedule_work(&priv->set_rx_mode_work);
1cefa326
AS		 3060 mlx5e_disable_async_events(priv);
3061 flush_scheduled_work();
5fc7197d
MD		 3062 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3063 netif_device_detach(netdev);
3064 mutex_lock(&priv->state_lock);
3065 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3066 mlx5e_close_locked(netdev);
3067 mutex_unlock(&priv->state_lock);
3068 } else {
3069 unregister_netdev(netdev);
3070 }
3071
e8f887ac 3072 mlx5e_tc_cleanup(priv);
b3f63c3d 3073 mlx5e_vxlan_cleanup(priv);
593cf338 3074 mlx5e_destroy_q_counter(priv);
acff797c 3075 mlx5e_destroy_flow_steering(priv);
40ab6a6e 3076 mlx5e_destroy_tirs(priv);
1da36696 3077 mlx5e_destroy_rqts(priv);
5c50368f 3078 mlx5e_close_drop_rq(priv);
40ab6a6e 3079 mlx5e_destroy_tises(priv);
bc77b240 3080 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
a606b0f6 3081 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
8d7f9ecb 3082 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 3083 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3084 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
5fc7197d
MD		 3085
3086 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3087 free_netdev(netdev);
f62b8bb8
AV		 3088}
3089
3090static void *mlx5e_get_netdev(void *vpriv)
3091{
3092 struct mlx5e_priv *priv = vpriv;
3093
3094 return priv->netdev;
3095}
3096
3097static struct mlx5_interface mlx5e_interface = {
3098 .add = mlx5e_create_netdev,
3099 .remove = mlx5e_destroy_netdev,
3100 .event = mlx5e_async_event,
3101 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3102 .get_dev = mlx5e_get_netdev,
3103};
3104
3105void mlx5e_init(void)
3106{
3107 mlx5_register_interface(&mlx5e_interface);
3108}
3109
3110void mlx5e_cleanup(void)
3111{
3112 mlx5_unregister_interface(&mlx5e_interface);
3113}
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