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net/mlx5e: Add support for multiple profiles
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8
AV		 41
42struct mlx5e_rq_param {
cb3c7fd4
GR		 43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45 bool am_enabled;
f62b8bb8
AV		 46};
47
48struct mlx5e_sq_param {
49 u32 sqc[MLX5_ST_SZ_DW(sqc)];
50 struct mlx5_wq_param wq;
58d52291 51 u16 max_inline;
d3c9bc27 52 bool icosq;
f62b8bb8
AV		 53};
54
55struct mlx5e_cq_param {
56 u32 cqc[MLX5_ST_SZ_DW(cqc)];
57 struct mlx5_wq_param wq;
58 u16 eq_ix;
9908aa29 59 u8 cq_period_mode;
f62b8bb8
AV		 60};
61
62struct mlx5e_channel_param {
63 struct mlx5e_rq_param rq;
64 struct mlx5e_sq_param sq;
d3c9bc27 65 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
d3c9bc27 68 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 69};
70
71static void mlx5e_update_carrier(struct mlx5e_priv *priv)
72{
73 struct mlx5_core_dev *mdev = priv->mdev;
74 u8 port_state;
75
76 port_state = mlx5_query_vport_state(mdev,
e7546514 77 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 78
79 if (port_state == VPORT_STATE_UP)
80 netif_carrier_on(priv->netdev);
81 else
82 netif_carrier_off(priv->netdev);
83}
84
85static void mlx5e_update_carrier_work(struct work_struct *work)
86{
87 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
88 update_carrier_work);
89
90 mutex_lock(&priv->state_lock);
91 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
92 mlx5e_update_carrier(priv);
93 mutex_unlock(&priv->state_lock);
94}
95
9218b44d 96static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 97{
9218b44d 98 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 99 struct mlx5e_rq_stats *rq_stats;
100 struct mlx5e_sq_stats *sq_stats;
9218b44d 101 u64 tx_offload_none = 0;
f62b8bb8
AV		 102 int i, j;
103
9218b44d 104 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 105 for (i = 0; i < priv->params.num_channels; i++) {
106 rq_stats = &priv->channel[i]->rq.stats;
107
faf4478b
GP		 108 s->rx_packets += rq_stats->packets;
109 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 110 s->rx_lro_packets += rq_stats->lro_packets;
111 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 112 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 113 s->rx_csum_complete += rq_stats->csum_complete;
114 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
f62b8bb8 115 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 116 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 117 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 118 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 119 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
120 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
f62b8bb8 121
a4418a6c 122 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 123 sq_stats = &priv->channel[i]->sq[j].stats;
124
faf4478b
GP		 125 s->tx_packets += sq_stats->packets;
126 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 127 s->tx_tso_packets += sq_stats->tso_packets;
128 s->tx_tso_bytes += sq_stats->tso_bytes;
129 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
130 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 131 s->tx_queue_stopped += sq_stats->stopped;
132 s->tx_queue_wake += sq_stats->wake;
133 s->tx_queue_dropped += sq_stats->dropped;
bfe6d8d1
GP		 134 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
135 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 136 }
137 }
138
9218b44d 139 /* Update calculated offload counters */
bfe6d8d1
GP		 140 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
141 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 142
bfe6d8d1 143 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 144 priv->stats.pport.phy_counters,
145 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 146}
147
148static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
149{
150 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
151 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
152 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
153 struct mlx5_core_dev *mdev = priv->mdev;
154
f62b8bb8
AV		 155 memset(in, 0, sizeof(in));
156
157 MLX5_SET(query_vport_counter_in, in, opcode,
158 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
159 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
160 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
161
162 memset(out, 0, outlen);
163
9218b44d
GP		 164 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
165}
166
167static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
168{
169 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
170 struct mlx5_core_dev *mdev = priv->mdev;
171 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 172 int prio;
9218b44d
GP		 173 void *out;
174 u32 *in;
175
176 in = mlx5_vzalloc(sz);
177 if (!in)
f62b8bb8
AV		 178 goto free_out;
179
9218b44d 180 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 181
9218b44d
GP		 182 out = pstats->IEEE_802_3_counters;
183 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
184 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 185
9218b44d
GP		 186 out = pstats->RFC_2863_counters;
187 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
188 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
189
190 out = pstats->RFC_2819_counters;
191 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
192 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 193
121fcdc8
GP		 194 out = pstats->phy_counters;
195 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
196 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
197
cf678570
GP		 198 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
199 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
200 out = pstats->per_prio_counters[prio];
201 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
202 mlx5_core_access_reg(mdev, in, sz, out, sz,
203 MLX5_REG_PPCNT, 0, 0);
204 }
205
f62b8bb8 206free_out:
9218b44d
GP		 207 kvfree(in);
208}
209
210static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
211{
212 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
213
214 if (!priv->q_counter)
215 return;
216
217 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
218 &qcnt->rx_out_of_buffer);
219}
220
221void mlx5e_update_stats(struct mlx5e_priv *priv)
222{
9218b44d
GP		 223 mlx5e_update_q_counter(priv);
224 mlx5e_update_vport_counters(priv);
225 mlx5e_update_pport_counters(priv);
121fcdc8 226 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 227}
228
229static void mlx5e_update_stats_work(struct work_struct *work)
230{
231 struct delayed_work *dwork = to_delayed_work(work);
232 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
233 update_stats_work);
234 mutex_lock(&priv->state_lock);
235 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 236 priv->profile->update_stats(priv);
7bb29755
MF		 237 queue_delayed_work(priv->wq, dwork,
238 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 239 }
240 mutex_unlock(&priv->state_lock);
241}
242
daa21560
TT		 243static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
244 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 245{
daa21560
TT		 246 struct mlx5e_priv *priv = vpriv;
247
e0f46eb9 248 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 249 return;
250
f62b8bb8
AV		 251 switch (event) {
252 case MLX5_DEV_EVENT_PORT_UP:
253 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 254 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 255 break;
256
257 default:
258 break;
259 }
260}
261
f62b8bb8
AV		 262static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
263{
e0f46eb9 264 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 265}
266
267static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
268{
e0f46eb9 269 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 270 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 271}
272
facc9699
SM		 273#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
274#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
275
f62b8bb8
AV		 276static int mlx5e_create_rq(struct mlx5e_channel *c,
277 struct mlx5e_rq_param *param,
278 struct mlx5e_rq *rq)
279{
280 struct mlx5e_priv *priv = c->priv;
281 struct mlx5_core_dev *mdev = priv->mdev;
282 void *rqc = param->rqc;
283 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 284 u32 byte_count;
f62b8bb8
AV		 285 int wq_sz;
286 int err;
287 int i;
288
311c7c71
SM		 289 param->wq.db_numa_node = cpu_to_node(c->cpu);
290
f62b8bb8
AV		 291 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
292 &rq->wq_ctrl);
293 if (err)
294 return err;
295
296 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
297
298 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 299
461017cb
TT		 300 switch (priv->params.rq_wq_type) {
301 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
302 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
303 GFP_KERNEL, cpu_to_node(c->cpu));
304 if (!rq->wqe_info) {
305 err = -ENOMEM;
306 goto err_rq_wq_destroy;
307 }
308 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
309 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
310
d9d9f156
TT		 311 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
312 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
313 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
461017cb
TT		 314 byte_count = rq->wqe_sz;
315 break;
316 default: /* MLX5_WQ_TYPE_LINKED_LIST */
317 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
318 cpu_to_node(c->cpu));
319 if (!rq->skb) {
320 err = -ENOMEM;
321 goto err_rq_wq_destroy;
322 }
323 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
324 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
325
326 rq->wqe_sz = (priv->params.lro_en) ?
327 priv->params.lro_wqe_sz :
328 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 329 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
330 byte_count = rq->wqe_sz;
461017cb
TT		 331 byte_count |= MLX5_HW_START_PADDING;
332 }
f62b8bb8
AV		 333
334 for (i = 0; i < wq_sz; i++) {
335 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
336
461017cb 337 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 338 }
339
cb3c7fd4
GR		 340 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
341 rq->am.mode = priv->params.rx_cq_period_mode;
342
461017cb 343 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 344 rq->pdev = c->pdev;
345 rq->netdev = c->netdev;
ef9814de 346 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 347 rq->channel = c;
348 rq->ix = c->ix;
50cfa25a 349 rq->priv = c->priv;
bc77b240
TT		 350 rq->mkey_be = c->mkey_be;
351 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 352
353 return 0;
354
355err_rq_wq_destroy:
356 mlx5_wq_destroy(&rq->wq_ctrl);
357
358 return err;
359}
360
361static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
362{
461017cb
TT		 363 switch (rq->wq_type) {
364 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
365 kfree(rq->wqe_info);
366 break;
367 default: /* MLX5_WQ_TYPE_LINKED_LIST */
368 kfree(rq->skb);
369 }
370
f62b8bb8
AV		 371 mlx5_wq_destroy(&rq->wq_ctrl);
372}
373
374static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
375{
50cfa25a 376 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 377 struct mlx5_core_dev *mdev = priv->mdev;
378
379 void *in;
380 void *rqc;
381 void *wq;
382 int inlen;
383 int err;
384
385 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
386 sizeof(u64) * rq->wq_ctrl.buf.npages;
387 in = mlx5_vzalloc(inlen);
388 if (!in)
389 return -ENOMEM;
390
391 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
392 wq = MLX5_ADDR_OF(rqc, rqc, wq);
393
394 memcpy(rqc, param->rqc, sizeof(param->rqc));
395
97de9f31 396 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 397 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
398 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
36350114 399 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 400 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 401 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 402 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
403
404 mlx5_fill_page_array(&rq->wq_ctrl.buf,
405 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
406
7db22ffb 407 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 408
409 kvfree(in);
410
411 return err;
412}
413
36350114
GP		 414static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
415 int next_state)
f62b8bb8
AV		 416{
417 struct mlx5e_channel *c = rq->channel;
418 struct mlx5e_priv *priv = c->priv;
419 struct mlx5_core_dev *mdev = priv->mdev;
420
421 void *in;
422 void *rqc;
423 int inlen;
424 int err;
425
426 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
427 in = mlx5_vzalloc(inlen);
428 if (!in)
429 return -ENOMEM;
430
431 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
432
433 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
434 MLX5_SET(rqc, rqc, state, next_state);
435
7db22ffb 436 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 437
438 kvfree(in);
439
440 return err;
441}
442
36350114
GP		 443static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
444{
445 struct mlx5e_channel *c = rq->channel;
446 struct mlx5e_priv *priv = c->priv;
447 struct mlx5_core_dev *mdev = priv->mdev;
448
449 void *in;
450 void *rqc;
451 int inlen;
452 int err;
453
454 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
455 in = mlx5_vzalloc(inlen);
456 if (!in)
457 return -ENOMEM;
458
459 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
460
461 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
462 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
463 MLX5_SET(rqc, rqc, vsd, vsd);
464 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
465
466 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
467
468 kvfree(in);
469
470 return err;
471}
472
f62b8bb8
AV		 473static void mlx5e_disable_rq(struct mlx5e_rq *rq)
474{
50cfa25a 475 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 476}
477
478static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
479{
01c196a2 480 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 481 struct mlx5e_channel *c = rq->channel;
482 struct mlx5e_priv *priv = c->priv;
483 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 484
01c196a2 485 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 486 if (wq->cur_sz >= priv->params.min_rx_wqes)
487 return 0;
488
489 msleep(20);
490 }
491
492 return -ETIMEDOUT;
493}
494
495static int mlx5e_open_rq(struct mlx5e_channel *c,
496 struct mlx5e_rq_param *param,
497 struct mlx5e_rq *rq)
498{
d3c9bc27
TT		 499 struct mlx5e_sq *sq = &c->icosq;
500 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 501 int err;
502
503 err = mlx5e_create_rq(c, param, rq);
504 if (err)
505 return err;
506
507 err = mlx5e_enable_rq(rq, param);
508 if (err)
509 goto err_destroy_rq;
510
36350114 511 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 512 if (err)
513 goto err_disable_rq;
514
cb3c7fd4
GR		 515 if (param->am_enabled)
516 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
517
f62b8bb8 518 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
d3c9bc27
TT		 519
520 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
521 sq->ico_wqe_info[pi].num_wqebbs = 1;
522 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 523
524 return 0;
525
526err_disable_rq:
527 mlx5e_disable_rq(rq);
528err_destroy_rq:
529 mlx5e_destroy_rq(rq);
530
531 return err;
532}
533
534static void mlx5e_close_rq(struct mlx5e_rq *rq)
535{
536 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
537 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
538
36350114 539 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
f62b8bb8
AV		 540 while (!mlx5_wq_ll_is_empty(&rq->wq))
541 msleep(20);
542
543 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
544 napi_synchronize(&rq->channel->napi);
545
cb3c7fd4
GR		 546 cancel_work_sync(&rq->am.work);
547
f62b8bb8
AV		 548 mlx5e_disable_rq(rq);
549 mlx5e_destroy_rq(rq);
550}
551
552static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
553{
34802a42 554 kfree(sq->wqe_info);
f62b8bb8
AV		 555 kfree(sq->dma_fifo);
556 kfree(sq->skb);
557}
558
559static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
560{
561 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
562 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
563
564 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
565 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
566 numa);
34802a42
AS		 567 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
568 numa);
f62b8bb8 569
34802a42 570 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 571 mlx5e_free_sq_db(sq);
572 return -ENOMEM;
573 }
574
575 sq->dma_fifo_mask = df_sz - 1;
576
577 return 0;
578}
579
580static int mlx5e_create_sq(struct mlx5e_channel *c,
581 int tc,
582 struct mlx5e_sq_param *param,
583 struct mlx5e_sq *sq)
584{
585 struct mlx5e_priv *priv = c->priv;
586 struct mlx5_core_dev *mdev = priv->mdev;
587
588 void *sqc = param->sqc;
589 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
590 int err;
591
fd4782c2 592 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 593 if (err)
594 return err;
595
311c7c71
SM		 596 param->wq.db_numa_node = cpu_to_node(c->cpu);
597
f62b8bb8
AV		 598 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
599 &sq->wq_ctrl);
600 if (err)
601 goto err_unmap_free_uar;
602
603 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 604 if (sq->uar.bf_map) {
605 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
606 sq->uar_map = sq->uar.bf_map;
607 } else {
608 sq->uar_map = sq->uar.map;
609 }
f62b8bb8 610 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 611 sq->max_inline = param->max_inline;
f62b8bb8 612
7ec0bb22
DC		 613 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
614 if (err)
f62b8bb8
AV		 615 goto err_sq_wq_destroy;
616
d3c9bc27
TT		 617 if (param->icosq) {
618 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
619
620 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
621 wq_sz,
622 GFP_KERNEL,
623 cpu_to_node(c->cpu));
624 if (!sq->ico_wqe_info) {
625 err = -ENOMEM;
626 goto err_free_sq_db;
627 }
628 } else {
629 int txq_ix;
630
631 txq_ix = c->ix + tc * priv->params.num_channels;
632 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
633 priv->txq_to_sq_map[txq_ix] = sq;
634 }
f62b8bb8 635
88a85f99 636 sq->pdev = c->pdev;
ef9814de 637 sq->tstamp = &priv->tstamp;
88a85f99
AS		 638 sq->mkey_be = c->mkey_be;
639 sq->channel = c;
640 sq->tc = tc;
641 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
642 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 643
644 return 0;
645
d3c9bc27
TT		 646err_free_sq_db:
647 mlx5e_free_sq_db(sq);
648
f62b8bb8
AV		 649err_sq_wq_destroy:
650 mlx5_wq_destroy(&sq->wq_ctrl);
651
652err_unmap_free_uar:
653 mlx5_unmap_free_uar(mdev, &sq->uar);
654
655 return err;
656}
657
658static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
659{
660 struct mlx5e_channel *c = sq->channel;
661 struct mlx5e_priv *priv = c->priv;
662
d3c9bc27 663 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 664 mlx5e_free_sq_db(sq);
665 mlx5_wq_destroy(&sq->wq_ctrl);
666 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
667}
668
669static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
670{
671 struct mlx5e_channel *c = sq->channel;
672 struct mlx5e_priv *priv = c->priv;
673 struct mlx5_core_dev *mdev = priv->mdev;
674
675 void *in;
676 void *sqc;
677 void *wq;
678 int inlen;
679 int err;
680
681 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
682 sizeof(u64) * sq->wq_ctrl.buf.npages;
683 in = mlx5_vzalloc(inlen);
684 if (!in)
685 return -ENOMEM;
686
687 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
688 wq = MLX5_ADDR_OF(sqc, sqc, wq);
689
690 memcpy(sqc, param->sqc, sizeof(param->sqc));
691
d3c9bc27
TT		 692 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
693 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
f62b8bb8 694 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 695 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 696 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
697
698 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
699 MLX5_SET(wq, wq, uar_page, sq->uar.index);
700 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 701 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 702 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
703
704 mlx5_fill_page_array(&sq->wq_ctrl.buf,
705 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
706
7db22ffb 707 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 708
709 kvfree(in);
710
711 return err;
712}
713
507f0c81
YP		 714static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
715 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 716{
717 struct mlx5e_channel *c = sq->channel;
718 struct mlx5e_priv *priv = c->priv;
719 struct mlx5_core_dev *mdev = priv->mdev;
720
721 void *in;
722 void *sqc;
723 int inlen;
724 int err;
725
726 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
727 in = mlx5_vzalloc(inlen);
728 if (!in)
729 return -ENOMEM;
730
731 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
732
733 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
734 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 735 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
736 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
737 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
738 }
f62b8bb8 739
7db22ffb 740 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 741
742 kvfree(in);
743
744 return err;
745}
746
747static void mlx5e_disable_sq(struct mlx5e_sq *sq)
748{
749 struct mlx5e_channel *c = sq->channel;
750 struct mlx5e_priv *priv = c->priv;
751 struct mlx5_core_dev *mdev = priv->mdev;
752
7db22ffb 753 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 754 if (sq->rate_limit)
755 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 756}
757
758static int mlx5e_open_sq(struct mlx5e_channel *c,
759 int tc,
760 struct mlx5e_sq_param *param,
761 struct mlx5e_sq *sq)
762{
763 int err;
764
765 err = mlx5e_create_sq(c, tc, param, sq);
766 if (err)
767 return err;
768
769 err = mlx5e_enable_sq(sq, param);
770 if (err)
771 goto err_destroy_sq;
772
507f0c81
YP		 773 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
774 false, 0);
f62b8bb8
AV		 775 if (err)
776 goto err_disable_sq;
777
d3c9bc27
TT		 778 if (sq->txq) {
779 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
780 netdev_tx_reset_queue(sq->txq);
781 netif_tx_start_queue(sq->txq);
782 }
f62b8bb8
AV		 783
784 return 0;
785
786err_disable_sq:
787 mlx5e_disable_sq(sq);
788err_destroy_sq:
789 mlx5e_destroy_sq(sq);
790
791 return err;
792}
793
794static inline void netif_tx_disable_queue(struct netdev_queue *txq)
795{
796 __netif_tx_lock_bh(txq);
797 netif_tx_stop_queue(txq);
798 __netif_tx_unlock_bh(txq);
799}
800
801static void mlx5e_close_sq(struct mlx5e_sq *sq)
802{
d3c9bc27
TT		 803 if (sq->txq) {
804 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
805 /* prevent netif_tx_wake_queue */
806 napi_synchronize(&sq->channel->napi);
807 netif_tx_disable_queue(sq->txq);
f62b8bb8 808
d3c9bc27
TT		 809 /* ensure hw is notified of all pending wqes */
810 if (mlx5e_sq_has_room_for(sq, 1))
811 mlx5e_send_nop(sq, true);
812
507f0c81
YP		 813 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR,
814 false, 0);
d3c9bc27 815 }
f62b8bb8 816
f62b8bb8
AV		 817 while (sq->cc != sq->pc) /* wait till sq is empty */
818 msleep(20);
819
820 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
821 napi_synchronize(&sq->channel->napi);
822
823 mlx5e_disable_sq(sq);
824 mlx5e_destroy_sq(sq);
825}
826
827static int mlx5e_create_cq(struct mlx5e_channel *c,
828 struct mlx5e_cq_param *param,
829 struct mlx5e_cq *cq)
830{
831 struct mlx5e_priv *priv = c->priv;
832 struct mlx5_core_dev *mdev = priv->mdev;
833 struct mlx5_core_cq *mcq = &cq->mcq;
834 int eqn_not_used;
0b6e26ce 835 unsigned int irqn;
f62b8bb8
AV		 836 int err;
837 u32 i;
838
311c7c71
SM		 839 param->wq.buf_numa_node = cpu_to_node(c->cpu);
840 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 841 param->eq_ix = c->ix;
842
843 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
844 &cq->wq_ctrl);
845 if (err)
846 return err;
847
848 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
849
850 cq->napi = &c->napi;
851
852 mcq->cqe_sz = 64;
853 mcq->set_ci_db = cq->wq_ctrl.db.db;
854 mcq->arm_db = cq->wq_ctrl.db.db + 1;
855 *mcq->set_ci_db = 0;
856 *mcq->arm_db = 0;
857 mcq->vector = param->eq_ix;
858 mcq->comp = mlx5e_completion_event;
859 mcq->event = mlx5e_cq_error_event;
860 mcq->irqn = irqn;
b50d292b 861 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 862
863 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
864 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
865
866 cqe->op_own = 0xf1;
867 }
868
869 cq->channel = c;
50cfa25a 870 cq->priv = priv;
f62b8bb8
AV		 871
872 return 0;
873}
874
875static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
876{
877 mlx5_wq_destroy(&cq->wq_ctrl);
878}
879
880static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
881{
50cfa25a 882 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 883 struct mlx5_core_dev *mdev = priv->mdev;
884 struct mlx5_core_cq *mcq = &cq->mcq;
885
886 void *in;
887 void *cqc;
888 int inlen;
0b6e26ce 889 unsigned int irqn_not_used;
f62b8bb8
AV		 890 int eqn;
891 int err;
892
893 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
894 sizeof(u64) * cq->wq_ctrl.buf.npages;
895 in = mlx5_vzalloc(inlen);
896 if (!in)
897 return -ENOMEM;
898
899 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
900
901 memcpy(cqc, param->cqc, sizeof(param->cqc));
902
903 mlx5_fill_page_array(&cq->wq_ctrl.buf,
904 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
905
906 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
907
9908aa29 908 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 909 MLX5_SET(cqc, cqc, c_eqn, eqn);
910 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
911 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 912 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 913 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
914
915 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
916
917 kvfree(in);
918
919 if (err)
920 return err;
921
922 mlx5e_cq_arm(cq);
923
924 return 0;
925}
926
927static void mlx5e_disable_cq(struct mlx5e_cq *cq)
928{
50cfa25a 929 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 930 struct mlx5_core_dev *mdev = priv->mdev;
931
932 mlx5_core_destroy_cq(mdev, &cq->mcq);
933}
934
935static int mlx5e_open_cq(struct mlx5e_channel *c,
936 struct mlx5e_cq_param *param,
937 struct mlx5e_cq *cq,
9908aa29 938 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 939{
940 int err;
941 struct mlx5e_priv *priv = c->priv;
942 struct mlx5_core_dev *mdev = priv->mdev;
943
944 err = mlx5e_create_cq(c, param, cq);
945 if (err)
946 return err;
947
948 err = mlx5e_enable_cq(cq, param);
949 if (err)
950 goto err_destroy_cq;
951
7524a5d8
GP		 952 if (MLX5_CAP_GEN(mdev, cq_moderation))
953 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 954 moderation.usec,
955 moderation.pkts);
f62b8bb8
AV		 956 return 0;
957
958err_destroy_cq:
959 mlx5e_destroy_cq(cq);
960
961 return err;
962}
963
964static void mlx5e_close_cq(struct mlx5e_cq *cq)
965{
966 mlx5e_disable_cq(cq);
967 mlx5e_destroy_cq(cq);
968}
969
970static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
971{
972 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
973}
974
975static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
976 struct mlx5e_channel_param *cparam)
977{
978 struct mlx5e_priv *priv = c->priv;
979 int err;
980 int tc;
981
982 for (tc = 0; tc < c->num_tc; tc++) {
983 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 984 priv->params.tx_cq_moderation);
f62b8bb8
AV		 985 if (err)
986 goto err_close_tx_cqs;
f62b8bb8
AV		 987 }
988
989 return 0;
990
991err_close_tx_cqs:
992 for (tc--; tc >= 0; tc--)
993 mlx5e_close_cq(&c->sq[tc].cq);
994
995 return err;
996}
997
998static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
999{
1000 int tc;
1001
1002 for (tc = 0; tc < c->num_tc; tc++)
1003 mlx5e_close_cq(&c->sq[tc].cq);
1004}
1005
1006static int mlx5e_open_sqs(struct mlx5e_channel *c,
1007 struct mlx5e_channel_param *cparam)
1008{
1009 int err;
1010 int tc;
1011
1012 for (tc = 0; tc < c->num_tc; tc++) {
1013 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1014 if (err)
1015 goto err_close_sqs;
1016 }
1017
1018 return 0;
1019
1020err_close_sqs:
1021 for (tc--; tc >= 0; tc--)
1022 mlx5e_close_sq(&c->sq[tc]);
1023
1024 return err;
1025}
1026
1027static void mlx5e_close_sqs(struct mlx5e_channel *c)
1028{
1029 int tc;
1030
1031 for (tc = 0; tc < c->num_tc; tc++)
1032 mlx5e_close_sq(&c->sq[tc]);
1033}
1034
5283af89 1035static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1036{
1037 int i;
1038
6bfd390b 1039 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1040 priv->channeltc_to_txq_map[ix][i] =
1041 ix + i * priv->params.num_channels;
03289b88
SM		 1042}
1043
507f0c81
YP		 1044static int mlx5e_set_sq_maxrate(struct net_device *dev,
1045 struct mlx5e_sq *sq, u32 rate)
1046{
1047 struct mlx5e_priv *priv = netdev_priv(dev);
1048 struct mlx5_core_dev *mdev = priv->mdev;
1049 u16 rl_index = 0;
1050 int err;
1051
1052 if (rate == sq->rate_limit)
1053 /* nothing to do */
1054 return 0;
1055
1056 if (sq->rate_limit)
1057 /* remove current rl index to free space to next ones */
1058 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1059
1060 sq->rate_limit = 0;
1061
1062 if (rate) {
1063 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1064 if (err) {
1065 netdev_err(dev, "Failed configuring rate %u: %d\n",
1066 rate, err);
1067 return err;
1068 }
1069 }
1070
1071 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1072 MLX5_SQC_STATE_RDY, true, rl_index);
1073 if (err) {
1074 netdev_err(dev, "Failed configuring rate %u: %d\n",
1075 rate, err);
1076 /* remove the rate from the table */
1077 if (rate)
1078 mlx5_rl_remove_rate(mdev, rate);
1079 return err;
1080 }
1081
1082 sq->rate_limit = rate;
1083 return 0;
1084}
1085
1086static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1087{
1088 struct mlx5e_priv *priv = netdev_priv(dev);
1089 struct mlx5_core_dev *mdev = priv->mdev;
1090 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1091 int err = 0;
1092
1093 if (!mlx5_rl_is_supported(mdev)) {
1094 netdev_err(dev, "Rate limiting is not supported on this device\n");
1095 return -EINVAL;
1096 }
1097
1098 /* rate is given in Mb/sec, HW config is in Kb/sec */
1099 rate = rate << 10;
1100
1101 /* Check whether rate in valid range, 0 is always valid */
1102 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1103 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1104 return -ERANGE;
1105 }
1106
1107 mutex_lock(&priv->state_lock);
1108 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1109 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1110 if (!err)
1111 priv->tx_rates[index] = rate;
1112 mutex_unlock(&priv->state_lock);
1113
1114 return err;
1115}
1116
f62b8bb8
AV		 1117static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1118 struct mlx5e_channel_param *cparam,
1119 struct mlx5e_channel **cp)
1120{
9908aa29 1121 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1122 struct net_device *netdev = priv->netdev;
cb3c7fd4 1123 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1124 int cpu = mlx5e_get_cpu(priv, ix);
1125 struct mlx5e_channel *c;
507f0c81 1126 struct mlx5e_sq *sq;
f62b8bb8 1127 int err;
507f0c81 1128 int i;
f62b8bb8
AV		 1129
1130 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1131 if (!c)
1132 return -ENOMEM;
1133
1134 c->priv = priv;
1135 c->ix = ix;
1136 c->cpu = cpu;
1137 c->pdev = &priv->mdev->pdev->dev;
1138 c->netdev = priv->netdev;
b50d292b 1139 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1140 c->num_tc = priv->params.num_tc;
f62b8bb8 1141
cb3c7fd4
GR		 1142 if (priv->params.rx_am_enabled)
1143 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1144 else
1145 rx_cq_profile = priv->params.rx_cq_moderation;
1146
5283af89 1147 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1148
f62b8bb8
AV		 1149 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1150
9908aa29 1151 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1152 if (err)
1153 goto err_napi_del;
1154
d3c9bc27
TT		 1155 err = mlx5e_open_tx_cqs(c, cparam);
1156 if (err)
1157 goto err_close_icosq_cq;
1158
f62b8bb8 1159 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1160 rx_cq_profile);
f62b8bb8
AV		 1161 if (err)
1162 goto err_close_tx_cqs;
f62b8bb8
AV		 1163
1164 napi_enable(&c->napi);
1165
d3c9bc27 1166 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1167 if (err)
1168 goto err_disable_napi;
1169
d3c9bc27
TT		 1170 err = mlx5e_open_sqs(c, cparam);
1171 if (err)
1172 goto err_close_icosq;
1173
507f0c81
YP		 1174 for (i = 0; i < priv->params.num_tc; i++) {
1175 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1176
1177 if (priv->tx_rates[txq_ix]) {
1178 sq = priv->txq_to_sq_map[txq_ix];
1179 mlx5e_set_sq_maxrate(priv->netdev, sq,
1180 priv->tx_rates[txq_ix]);
1181 }
1182 }
1183
f62b8bb8
AV		 1184 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1185 if (err)
1186 goto err_close_sqs;
1187
1188 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1189 *cp = c;
1190
1191 return 0;
1192
1193err_close_sqs:
1194 mlx5e_close_sqs(c);
1195
d3c9bc27
TT		 1196err_close_icosq:
1197 mlx5e_close_sq(&c->icosq);
1198
f62b8bb8
AV		 1199err_disable_napi:
1200 napi_disable(&c->napi);
1201 mlx5e_close_cq(&c->rq.cq);
1202
1203err_close_tx_cqs:
1204 mlx5e_close_tx_cqs(c);
1205
d3c9bc27
TT		 1206err_close_icosq_cq:
1207 mlx5e_close_cq(&c->icosq.cq);
1208
f62b8bb8
AV		 1209err_napi_del:
1210 netif_napi_del(&c->napi);
7ae92ae5 1211 napi_hash_del(&c->napi);
f62b8bb8
AV		 1212 kfree(c);
1213
1214 return err;
1215}
1216
1217static void mlx5e_close_channel(struct mlx5e_channel *c)
1218{
1219 mlx5e_close_rq(&c->rq);
1220 mlx5e_close_sqs(c);
d3c9bc27 1221 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1222 napi_disable(&c->napi);
1223 mlx5e_close_cq(&c->rq.cq);
1224 mlx5e_close_tx_cqs(c);
d3c9bc27 1225 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1226 netif_napi_del(&c->napi);
7ae92ae5
ED		 1227
1228 napi_hash_del(&c->napi);
1229 synchronize_rcu();
1230
f62b8bb8
AV		 1231 kfree(c);
1232}
1233
1234static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1235 struct mlx5e_rq_param *param)
1236{
1237 void *rqc = param->rqc;
1238 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1239
461017cb
TT		 1240 switch (priv->params.rq_wq_type) {
1241 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1242 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1243 priv->params.mpwqe_log_num_strides - 9);
461017cb 1244 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1245 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1246 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1247 break;
1248 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1249 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1250 }
1251
f62b8bb8
AV		 1252 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1253 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1254 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1255 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1256 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1257
311c7c71 1258 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1259 param->wq.linear = 1;
cb3c7fd4
GR		 1260
1261 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1262}
1263
556dd1b9
TT		 1264static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1265{
1266 void *rqc = param->rqc;
1267 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1268
1269 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1270 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1271}
1272
d3c9bc27
TT		 1273static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1274 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1275{
1276 void *sqc = param->sqc;
1277 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1278
f62b8bb8 1279 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1280 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1281
311c7c71 1282 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1283}
1284
1285static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1286 struct mlx5e_sq_param *param)
1287{
1288 void *sqc = param->sqc;
1289 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1290
1291 mlx5e_build_sq_param_common(priv, param);
1292 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1293
58d52291 1294 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1295}
1296
1297static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1298 struct mlx5e_cq_param *param)
1299{
1300 void *cqc = param->cqc;
1301
b50d292b 1302 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1303}
1304
1305static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1306 struct mlx5e_cq_param *param)
1307{
1308 void *cqc = param->cqc;
461017cb 1309 u8 log_cq_size;
f62b8bb8 1310
461017cb
TT		 1311 switch (priv->params.rq_wq_type) {
1312 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1313 log_cq_size = priv->params.log_rq_size +
d9d9f156 1314 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1315 break;
1316 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1317 log_cq_size = priv->params.log_rq_size;
1318 }
1319
1320 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1321 if (priv->params.rx_cqe_compress) {
1322 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1323 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1324 }
f62b8bb8
AV		 1325
1326 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1327
1328 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1329}
1330
1331static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1332 struct mlx5e_cq_param *param)
1333{
1334 void *cqc = param->cqc;
1335
d3c9bc27 1336 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1337
1338 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1339
1340 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1341}
1342
d3c9bc27
TT		 1343static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1344 struct mlx5e_cq_param *param,
1345 u8 log_wq_size)
1346{
1347 void *cqc = param->cqc;
1348
1349 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1350
1351 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1352
1353 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1354}
1355
1356static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1357 struct mlx5e_sq_param *param,
1358 u8 log_wq_size)
1359{
1360 void *sqc = param->sqc;
1361 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1362
1363 mlx5e_build_sq_param_common(priv, param);
1364
1365 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1366 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1367
1368 param->icosq = true;
1369}
1370
6b87663f 1371static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1372{
bc77b240 1373 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1374
f62b8bb8
AV		 1375 mlx5e_build_rq_param(priv, &cparam->rq);
1376 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1377 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1378 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1379 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1380 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1381}
1382
1383static int mlx5e_open_channels(struct mlx5e_priv *priv)
1384{
6b87663f 1385 struct mlx5e_channel_param *cparam;
a4418a6c 1386 int nch = priv->params.num_channels;
03289b88 1387 int err = -ENOMEM;
f62b8bb8
AV		 1388 int i;
1389 int j;
1390
a4418a6c
AS		 1391 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1392 GFP_KERNEL);
03289b88 1393
a4418a6c 1394 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1395 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1396
6b87663f
AB		 1397 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1398
1399 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1400 goto err_free_txq_to_sq_map;
f62b8bb8 1401
6b87663f
AB		 1402 mlx5e_build_channel_param(priv, cparam);
1403
a4418a6c 1404 for (i = 0; i < nch; i++) {
6b87663f 1405 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1406 if (err)
1407 goto err_close_channels;
1408 }
1409
a4418a6c 1410 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1411 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1412 if (err)
1413 goto err_close_channels;
1414 }
1415
6b87663f 1416 kfree(cparam);
f62b8bb8
AV		 1417 return 0;
1418
1419err_close_channels:
1420 for (i--; i >= 0; i--)
1421 mlx5e_close_channel(priv->channel[i]);
1422
03289b88
SM		 1423err_free_txq_to_sq_map:
1424 kfree(priv->txq_to_sq_map);
f62b8bb8 1425 kfree(priv->channel);
6b87663f 1426 kfree(cparam);
f62b8bb8
AV		 1427
1428 return err;
1429}
1430
1431static void mlx5e_close_channels(struct mlx5e_priv *priv)
1432{
1433 int i;
1434
1435 for (i = 0; i < priv->params.num_channels; i++)
1436 mlx5e_close_channel(priv->channel[i]);
1437
03289b88 1438 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1439 kfree(priv->channel);
1440}
1441
2be6967c
SM		 1442static int mlx5e_rx_hash_fn(int hfunc)
1443{
1444 return (hfunc == ETH_RSS_HASH_TOP) ?
1445 MLX5_RX_HASH_FN_TOEPLITZ :
1446 MLX5_RX_HASH_FN_INVERTED_XOR8;
1447}
1448
1449static int mlx5e_bits_invert(unsigned long a, int size)
1450{
1451 int inv = 0;
1452 int i;
1453
1454 for (i = 0; i < size; i++)
1455 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1456
1457 return inv;
1458}
1459
936896e9
AS		 1460static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1461{
1462 int i;
1463
1464 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1465 int ix = i;
1da36696 1466 u32 rqn;
936896e9
AS		 1467
1468 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1469 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1470
2d75b2bc 1471 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1472 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1473 priv->channel[ix]->rq.rqn :
1474 priv->drop_rq.rqn;
1475 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1476 }
1477}
1478
1da36696
TT		 1479static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1480 int ix)
4cbeaff5 1481{
1da36696
TT		 1482 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1483 priv->channel[ix]->rq.rqn :
1484 priv->drop_rq.rqn;
4cbeaff5 1485
1da36696 1486 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1487}
1488
398f3351
HHZ		 1489static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1490 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1491{
1492 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1493 void *rqtc;
1494 int inlen;
1495 int err;
1da36696 1496 u32 *in;
f62b8bb8 1497
f62b8bb8
AV		 1498 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1499 in = mlx5_vzalloc(inlen);
1500 if (!in)
1501 return -ENOMEM;
1502
1503 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1504
1505 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1506 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1507
1da36696
TT		 1508 if (sz > 1) /* RSS */
1509 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1510 else
1511 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1512
398f3351
HHZ		 1513 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1514 if (!err)
1515 rqt->enabled = true;
f62b8bb8
AV		 1516
1517 kvfree(in);
1da36696
TT		 1518 return err;
1519}
1520
398f3351 1521static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1522{
398f3351
HHZ		 1523 rqt->enabled = false;
1524 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1525}
1526
6bfd390b
HHZ		 1527static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1528{
1529 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1530
1531 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1532}
1533
1534static int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1535{
398f3351 1536 struct mlx5e_rqt *rqt;
1da36696
TT		 1537 int err;
1538 int ix;
1539
6bfd390b 1540 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1541 rqt = &priv->direct_tir[ix].rqt;
1542 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1543 if (err)
1544 goto err_destroy_rqts;
1545 }
1546
1547 return 0;
1548
1549err_destroy_rqts:
1550 for (ix--; ix >= 0; ix--)
398f3351 1551 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1552
f62b8bb8
AV		 1553 return err;
1554}
1555
1da36696 1556int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1557{
1558 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1559 void *rqtc;
1560 int inlen;
1da36696 1561 u32 *in;
5c50368f
AS		 1562 int err;
1563
5c50368f
AS		 1564 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1565 in = mlx5_vzalloc(inlen);
1566 if (!in)
1567 return -ENOMEM;
1568
1569 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1570
1571 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1572 if (sz > 1) /* RSS */
1573 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1574 else
1575 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1576
1577 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1578
1da36696 1579 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1580
1581 kvfree(in);
1582
1583 return err;
1584}
1585
40ab6a6e
AS		 1586static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1587{
1da36696
TT		 1588 u32 rqtn;
1589 int ix;
1590
398f3351
HHZ		 1591 if (priv->indir_rqt.enabled) {
1592 rqtn = priv->indir_rqt.rqtn;
1593 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1594 }
1595
1da36696 1596 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 1597 if (!priv->direct_tir[ix].rqt.enabled)
1598 continue;
1599 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 1600 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1601 }
40ab6a6e
AS		 1602}
1603
5c50368f
AS		 1604static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1605{
1606 if (!priv->params.lro_en)
1607 return;
1608
1609#define ROUGH_MAX_L2_L3_HDR_SZ 256
1610
1611 MLX5_SET(tirc, tirc, lro_enable_mask,
1612 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1613 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1614 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1615 (priv->params.lro_wqe_sz -
1616 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1617 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1618 MLX5_CAP_ETH(priv->mdev,
d9a40271 1619 lro_timer_supported_periods[2]));
5c50368f
AS		 1620}
1621
bdfc028d
TT		 1622void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1623{
1624 MLX5_SET(tirc, tirc, rx_hash_fn,
1625 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1626 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1627 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1628 rx_hash_toeplitz_key);
1629 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1630 rx_hash_toeplitz_key);
1631
1632 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1633 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1634 }
1635}
1636
ab0394fe 1637static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1638{
1639 struct mlx5_core_dev *mdev = priv->mdev;
1640
1641 void *in;
1642 void *tirc;
1643 int inlen;
1644 int err;
ab0394fe 1645 int tt;
1da36696 1646 int ix;
5c50368f
AS		 1647
1648 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1649 in = mlx5_vzalloc(inlen);
1650 if (!in)
1651 return -ENOMEM;
1652
1653 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1654 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1655
1656 mlx5e_build_tir_ctx_lro(tirc, priv);
1657
1da36696 1658 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 1659 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 1660 inlen);
ab0394fe 1661 if (err)
1da36696 1662 goto free_in;
ab0394fe 1663 }
5c50368f 1664
6bfd390b 1665 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 1666 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1667 in, inlen);
1668 if (err)
1669 goto free_in;
1670 }
1671
1672free_in:
5c50368f
AS		 1673 kvfree(in);
1674
1675 return err;
1676}
1677
cd255eff 1678static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 1679{
40ab6a6e 1680 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 1681 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 1682 int err;
1683
cd255eff 1684 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 1685 if (err)
1686 return err;
1687
cd255eff
SM		 1688 /* Update vport context MTU */
1689 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1690 return 0;
1691}
40ab6a6e 1692
cd255eff
SM		 1693static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1694{
1695 struct mlx5_core_dev *mdev = priv->mdev;
1696 u16 hw_mtu = 0;
1697 int err;
40ab6a6e 1698
cd255eff
SM		 1699 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1700 if (err || !hw_mtu) /* fallback to port oper mtu */
1701 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1702
1703 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1704}
1705
1706static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1707{
1708 struct mlx5e_priv *priv = netdev_priv(netdev);
1709 u16 mtu;
1710 int err;
1711
1712 err = mlx5e_set_mtu(priv, netdev->mtu);
1713 if (err)
1714 return err;
40ab6a6e 1715
cd255eff
SM		 1716 mlx5e_query_mtu(priv, &mtu);
1717 if (mtu != netdev->mtu)
1718 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1719 __func__, mtu, netdev->mtu);
40ab6a6e 1720
cd255eff 1721 netdev->mtu = mtu;
40ab6a6e
AS		 1722 return 0;
1723}
1724
08fb1dac
SM		 1725static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1726{
1727 struct mlx5e_priv *priv = netdev_priv(netdev);
1728 int nch = priv->params.num_channels;
1729 int ntc = priv->params.num_tc;
1730 int tc;
1731
1732 netdev_reset_tc(netdev);
1733
1734 if (ntc == 1)
1735 return;
1736
1737 netdev_set_num_tc(netdev, ntc);
1738
1739 for (tc = 0; tc < ntc; tc++)
1740 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1741}
1742
40ab6a6e
AS		 1743int mlx5e_open_locked(struct net_device *netdev)
1744{
1745 struct mlx5e_priv *priv = netdev_priv(netdev);
1746 int num_txqs;
1747 int err;
1748
1749 set_bit(MLX5E_STATE_OPENED, &priv->state);
1750
08fb1dac
SM		 1751 mlx5e_netdev_set_tcs(netdev);
1752
40ab6a6e
AS		 1753 num_txqs = priv->params.num_channels * priv->params.num_tc;
1754 netif_set_real_num_tx_queues(netdev, num_txqs);
1755 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1756
1757 err = mlx5e_set_dev_port_mtu(netdev);
1758 if (err)
343b29f3 1759 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1760
1761 err = mlx5e_open_channels(priv);
1762 if (err) {
1763 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1764 __func__, err);
343b29f3 1765 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1766 }
1767
724b2aa1 1768 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
66189961
TT		 1769 if (err) {
1770 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1771 __func__, err);
1772 goto err_close_channels;
1773 }
1774
40ab6a6e 1775 mlx5e_redirect_rqts(priv);
ce89ef36 1776 mlx5e_update_carrier(priv);
ef9814de 1777 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 1778#ifdef CONFIG_RFS_ACCEL
1779 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1780#endif
40ab6a6e 1781
7bb29755 1782 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 1783
9b37b07f 1784 return 0;
343b29f3 1785
66189961
TT		 1786err_close_channels:
1787 mlx5e_close_channels(priv);
343b29f3
AS		 1788err_clear_state_opened_flag:
1789 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1790 return err;
40ab6a6e
AS		 1791}
1792
1793static int mlx5e_open(struct net_device *netdev)
1794{
1795 struct mlx5e_priv *priv = netdev_priv(netdev);
1796 int err;
1797
1798 mutex_lock(&priv->state_lock);
1799 err = mlx5e_open_locked(netdev);
1800 mutex_unlock(&priv->state_lock);
1801
1802 return err;
1803}
1804
1805int mlx5e_close_locked(struct net_device *netdev)
1806{
1807 struct mlx5e_priv *priv = netdev_priv(netdev);
1808
a1985740
AS		 1809 /* May already be CLOSED in case a previous configuration operation
1810 * (e.g RX/TX queue size change) that involves close&open failed.
1811 */
1812 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1813 return 0;
1814
40ab6a6e
AS		 1815 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1816
ef9814de 1817 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1818 netif_carrier_off(priv->netdev);
ce89ef36 1819 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1820 mlx5e_close_channels(priv);
1821
1822 return 0;
1823}
1824
1825static int mlx5e_close(struct net_device *netdev)
1826{
1827 struct mlx5e_priv *priv = netdev_priv(netdev);
1828 int err;
1829
1830 mutex_lock(&priv->state_lock);
1831 err = mlx5e_close_locked(netdev);
1832 mutex_unlock(&priv->state_lock);
1833
1834 return err;
1835}
1836
1837static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1838 struct mlx5e_rq *rq,
1839 struct mlx5e_rq_param *param)
1840{
1841 struct mlx5_core_dev *mdev = priv->mdev;
1842 void *rqc = param->rqc;
1843 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1844 int err;
1845
1846 param->wq.db_numa_node = param->wq.buf_numa_node;
1847
1848 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1849 &rq->wq_ctrl);
1850 if (err)
1851 return err;
1852
1853 rq->priv = priv;
1854
1855 return 0;
1856}
1857
1858static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1859 struct mlx5e_cq *cq,
1860 struct mlx5e_cq_param *param)
1861{
1862 struct mlx5_core_dev *mdev = priv->mdev;
1863 struct mlx5_core_cq *mcq = &cq->mcq;
1864 int eqn_not_used;
0b6e26ce 1865 unsigned int irqn;
40ab6a6e
AS		 1866 int err;
1867
1868 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1869 &cq->wq_ctrl);
1870 if (err)
1871 return err;
1872
1873 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1874
1875 mcq->cqe_sz = 64;
1876 mcq->set_ci_db = cq->wq_ctrl.db.db;
1877 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1878 *mcq->set_ci_db = 0;
1879 *mcq->arm_db = 0;
1880 mcq->vector = param->eq_ix;
1881 mcq->comp = mlx5e_completion_event;
1882 mcq->event = mlx5e_cq_error_event;
1883 mcq->irqn = irqn;
b50d292b 1884 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 1885
1886 cq->priv = priv;
1887
1888 return 0;
1889}
1890
1891static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1892{
1893 struct mlx5e_cq_param cq_param;
1894 struct mlx5e_rq_param rq_param;
1895 struct mlx5e_rq *rq = &priv->drop_rq;
1896 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1897 int err;
1898
1899 memset(&cq_param, 0, sizeof(cq_param));
1900 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1901 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1902
1903 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1904 if (err)
1905 return err;
1906
1907 err = mlx5e_enable_cq(cq, &cq_param);
1908 if (err)
1909 goto err_destroy_cq;
1910
1911 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1912 if (err)
1913 goto err_disable_cq;
1914
1915 err = mlx5e_enable_rq(rq, &rq_param);
1916 if (err)
1917 goto err_destroy_rq;
1918
1919 return 0;
1920
1921err_destroy_rq:
1922 mlx5e_destroy_rq(&priv->drop_rq);
1923
1924err_disable_cq:
1925 mlx5e_disable_cq(&priv->drop_rq.cq);
1926
1927err_destroy_cq:
1928 mlx5e_destroy_cq(&priv->drop_rq.cq);
1929
1930 return err;
1931}
1932
1933static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1934{
1935 mlx5e_disable_rq(&priv->drop_rq);
1936 mlx5e_destroy_rq(&priv->drop_rq);
1937 mlx5e_disable_cq(&priv->drop_rq.cq);
1938 mlx5e_destroy_cq(&priv->drop_rq.cq);
1939}
1940
1941static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1942{
1943 struct mlx5_core_dev *mdev = priv->mdev;
1944 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1945 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1946
1947 memset(in, 0, sizeof(in));
1948
08fb1dac 1949 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 1950 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
40ab6a6e
AS		 1951
1952 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1953}
1954
1955static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1956{
1957 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1958}
1959
1960static int mlx5e_create_tises(struct mlx5e_priv *priv)
1961{
1962 int err;
1963 int tc;
1964
6bfd390b 1965 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 1966 err = mlx5e_create_tis(priv, tc);
1967 if (err)
1968 goto err_close_tises;
1969 }
1970
1971 return 0;
1972
1973err_close_tises:
1974 for (tc--; tc >= 0; tc--)
1975 mlx5e_destroy_tis(priv, tc);
1976
1977 return err;
1978}
1979
6bfd390b 1980static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 1981{
1982 int tc;
1983
6bfd390b 1984 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 1985 mlx5e_destroy_tis(priv, tc);
1986}
1987
1da36696
TT		 1988static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1989 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 1990{
1991 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1992
b50d292b 1993 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 1994
5a6f8aef
AS		 1995#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1996 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1997
5a6f8aef
AS		 1998#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1999 MLX5_HASH_FIELD_SEL_DST_IP |\
2000 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2001 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2002
a741749f
AS		 2003#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2004 MLX5_HASH_FIELD_SEL_DST_IP |\
2005 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2006
5c50368f 2007 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2008
4cbeaff5 2009 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2010 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2011 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2012
2013 switch (tt) {
2014 case MLX5E_TT_IPV4_TCP:
2015 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2016 MLX5_L3_PROT_TYPE_IPV4);
2017 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2018 MLX5_L4_PROT_TYPE_TCP);
2019 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2020 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2021 break;
2022
2023 case MLX5E_TT_IPV6_TCP:
2024 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2025 MLX5_L3_PROT_TYPE_IPV6);
2026 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2027 MLX5_L4_PROT_TYPE_TCP);
2028 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2029 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2030 break;
2031
2032 case MLX5E_TT_IPV4_UDP:
2033 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2034 MLX5_L3_PROT_TYPE_IPV4);
2035 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2036 MLX5_L4_PROT_TYPE_UDP);
2037 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2038 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2039 break;
2040
2041 case MLX5E_TT_IPV6_UDP:
2042 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2043 MLX5_L3_PROT_TYPE_IPV6);
2044 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2045 MLX5_L4_PROT_TYPE_UDP);
2046 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2047 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2048 break;
2049
a741749f
AS		 2050 case MLX5E_TT_IPV4_IPSEC_AH:
2051 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2052 MLX5_L3_PROT_TYPE_IPV4);
2053 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2054 MLX5_HASH_IP_IPSEC_SPI);
2055 break;
2056
2057 case MLX5E_TT_IPV6_IPSEC_AH:
2058 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2059 MLX5_L3_PROT_TYPE_IPV6);
2060 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2061 MLX5_HASH_IP_IPSEC_SPI);
2062 break;
2063
2064 case MLX5E_TT_IPV4_IPSEC_ESP:
2065 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2066 MLX5_L3_PROT_TYPE_IPV4);
2067 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2068 MLX5_HASH_IP_IPSEC_SPI);
2069 break;
2070
2071 case MLX5E_TT_IPV6_IPSEC_ESP:
2072 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2073 MLX5_L3_PROT_TYPE_IPV6);
2074 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2075 MLX5_HASH_IP_IPSEC_SPI);
2076 break;
2077
f62b8bb8
AV		 2078 case MLX5E_TT_IPV4:
2079 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2080 MLX5_L3_PROT_TYPE_IPV4);
2081 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2082 MLX5_HASH_IP);
2083 break;
2084
2085 case MLX5E_TT_IPV6:
2086 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2087 MLX5_L3_PROT_TYPE_IPV6);
2088 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2089 MLX5_HASH_IP);
2090 break;
1da36696
TT		 2091 default:
2092 WARN_ONCE(true,
2093 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2094 }
2095}
2096
1da36696
TT		 2097static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2098 u32 rqtn)
f62b8bb8 2099{
b50d292b 2100 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2101
2102 mlx5e_build_tir_ctx_lro(tirc, priv);
2103
2104 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2105 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2106 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2107}
2108
6bfd390b 2109static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2110{
724b2aa1 2111 struct mlx5e_tir *tir;
f62b8bb8
AV		 2112 void *tirc;
2113 int inlen;
2114 int err;
1da36696 2115 u32 *in;
1da36696 2116 int tt;
f62b8bb8
AV		 2117
2118 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2119 in = mlx5_vzalloc(inlen);
2120 if (!in)
2121 return -ENOMEM;
2122
1da36696
TT		 2123 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2124 memset(in, 0, inlen);
724b2aa1 2125 tir = &priv->indir_tir[tt];
1da36696
TT		 2126 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2127 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2128 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2129 if (err)
40ab6a6e 2130 goto err_destroy_tirs;
f62b8bb8
AV		 2131 }
2132
6bfd390b
HHZ		 2133 kvfree(in);
2134
2135 return 0;
2136
2137err_destroy_tirs:
2138 for (tt--; tt >= 0; tt--)
2139 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2140
2141 kvfree(in);
2142
2143 return err;
2144}
2145
2146static int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2147{
2148 int nch = priv->profile->max_nch(priv->mdev);
2149 struct mlx5e_tir *tir;
2150 void *tirc;
2151 int inlen;
2152 int err;
2153 u32 *in;
2154 int ix;
2155
2156 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2157 in = mlx5_vzalloc(inlen);
2158 if (!in)
2159 return -ENOMEM;
2160
1da36696
TT		 2161 for (ix = 0; ix < nch; ix++) {
2162 memset(in, 0, inlen);
724b2aa1 2163 tir = &priv->direct_tir[ix];
1da36696
TT		 2164 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2165 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2166 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2167 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2168 if (err)
2169 goto err_destroy_ch_tirs;
2170 }
2171
2172 kvfree(in);
2173
f62b8bb8
AV		 2174 return 0;
2175
1da36696
TT		 2176err_destroy_ch_tirs:
2177 for (ix--; ix >= 0; ix--)
724b2aa1 2178 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2179
1da36696 2180 kvfree(in);
f62b8bb8
AV		 2181
2182 return err;
2183}
2184
6bfd390b 2185static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2186{
2187 int i;
2188
1da36696 2189 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2190 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2191}
2192
6bfd390b
HHZ		 2193static void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2194{
2195 int nch = priv->profile->max_nch(priv->mdev);
2196 int i;
2197
2198 for (i = 0; i < nch; i++)
2199 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2200}
2201
36350114
GP		 2202int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2203{
2204 int err = 0;
2205 int i;
2206
2207 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2208 return 0;
2209
2210 for (i = 0; i < priv->params.num_channels; i++) {
2211 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2212 if (err)
2213 return err;
2214 }
2215
2216 return 0;
2217}
2218
08fb1dac
SM		 2219static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2220{
2221 struct mlx5e_priv *priv = netdev_priv(netdev);
2222 bool was_opened;
2223 int err = 0;
2224
2225 if (tc && tc != MLX5E_MAX_NUM_TC)
2226 return -EINVAL;
2227
2228 mutex_lock(&priv->state_lock);
2229
2230 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2231 if (was_opened)
2232 mlx5e_close_locked(priv->netdev);
2233
2234 priv->params.num_tc = tc ? tc : 1;
2235
2236 if (was_opened)
2237 err = mlx5e_open_locked(priv->netdev);
2238
2239 mutex_unlock(&priv->state_lock);
2240
2241 return err;
2242}
2243
2244static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2245 __be16 proto, struct tc_to_netdev *tc)
2246{
e8f887ac
AV		 2247 struct mlx5e_priv *priv = netdev_priv(dev);
2248
2249 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2250 goto mqprio;
2251
2252 switch (tc->type) {
e3a2b7ed
AV		 2253 case TC_SETUP_CLSFLOWER:
2254 switch (tc->cls_flower->command) {
2255 case TC_CLSFLOWER_REPLACE:
2256 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2257 case TC_CLSFLOWER_DESTROY:
2258 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2259 case TC_CLSFLOWER_STATS:
2260 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2261 }
e8f887ac
AV		 2262 default:
2263 return -EOPNOTSUPP;
2264 }
2265
2266mqprio:
67ba422e 2267 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2268 return -EINVAL;
2269
2270 return mlx5e_setup_tc(dev, tc->tc);
2271}
2272
f62b8bb8
AV		 2273static struct rtnl_link_stats64 *
2274mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2275{
2276 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2277 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2278 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2279 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2280
9218b44d
GP		 2281 stats->rx_packets = sstats->rx_packets;
2282 stats->rx_bytes = sstats->rx_bytes;
2283 stats->tx_packets = sstats->tx_packets;
2284 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2285
2286 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2287 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2288
2289 stats->rx_length_errors =
9218b44d
GP		 2290 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2291 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2292 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2293 stats->rx_crc_errors =
9218b44d
GP		 2294 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2295 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2296 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2297 stats->tx_carrier_errors =
9218b44d 2298 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2299 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2300 stats->rx_frame_errors;
2301 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2302
2303 /* vport multicast also counts packets that are dropped due to steering
2304 * or rx out of buffer
2305 */
9218b44d
GP		 2306 stats->multicast =
2307 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2308
2309 return stats;
2310}
2311
2312static void mlx5e_set_rx_mode(struct net_device *dev)
2313{
2314 struct mlx5e_priv *priv = netdev_priv(dev);
2315
7bb29755 2316 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2317}
2318
2319static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2320{
2321 struct mlx5e_priv *priv = netdev_priv(netdev);
2322 struct sockaddr *saddr = addr;
2323
2324 if (!is_valid_ether_addr(saddr->sa_data))
2325 return -EADDRNOTAVAIL;
2326
2327 netif_addr_lock_bh(netdev);
2328 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2329 netif_addr_unlock_bh(netdev);
2330
7bb29755 2331 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2332
2333 return 0;
2334}
2335
0e405443
GP		 2336#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2337 do { \
2338 if (enable) \
2339 netdev->features |= feature; \
2340 else \
2341 netdev->features &= ~feature; \
2342 } while (0)
2343
2344typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2345
2346static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2347{
2348 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2349 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2350 int err;
f62b8bb8
AV		 2351
2352 mutex_lock(&priv->state_lock);
f62b8bb8 2353
0e405443
GP		 2354 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2355 mlx5e_close_locked(priv->netdev);
98e81b0a 2356
0e405443
GP		 2357 priv->params.lro_en = enable;
2358 err = mlx5e_modify_tirs_lro(priv);
2359 if (err) {
2360 netdev_err(netdev, "lro modify failed, %d\n", err);
2361 priv->params.lro_en = !enable;
98e81b0a 2362 }
f62b8bb8 2363
0e405443
GP		 2364 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2365 mlx5e_open_locked(priv->netdev);
2366
9b37b07f
AS		 2367 mutex_unlock(&priv->state_lock);
2368
0e405443
GP		 2369 return err;
2370}
2371
2372static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2373{
2374 struct mlx5e_priv *priv = netdev_priv(netdev);
2375
2376 if (enable)
2377 mlx5e_enable_vlan_filter(priv);
2378 else
2379 mlx5e_disable_vlan_filter(priv);
2380
2381 return 0;
2382}
2383
2384static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2385{
2386 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2387
0e405443 2388 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2389 netdev_err(netdev,
2390 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2391 return -EINVAL;
2392 }
2393
0e405443
GP		 2394 return 0;
2395}
2396
94cb1ebb
EBE		 2397static int set_feature_rx_all(struct net_device *netdev, bool enable)
2398{
2399 struct mlx5e_priv *priv = netdev_priv(netdev);
2400 struct mlx5_core_dev *mdev = priv->mdev;
2401
2402 return mlx5_set_port_fcs(mdev, !enable);
2403}
2404
36350114
GP		 2405static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2406{
2407 struct mlx5e_priv *priv = netdev_priv(netdev);
2408 int err;
2409
2410 mutex_lock(&priv->state_lock);
2411
2412 priv->params.vlan_strip_disable = !enable;
2413 err = mlx5e_modify_rqs_vsd(priv, !enable);
2414 if (err)
2415 priv->params.vlan_strip_disable = enable;
2416
2417 mutex_unlock(&priv->state_lock);
2418
2419 return err;
2420}
2421
45bf454a
MG		 2422#ifdef CONFIG_RFS_ACCEL
2423static int set_feature_arfs(struct net_device *netdev, bool enable)
2424{
2425 struct mlx5e_priv *priv = netdev_priv(netdev);
2426 int err;
2427
2428 if (enable)
2429 err = mlx5e_arfs_enable(priv);
2430 else
2431 err = mlx5e_arfs_disable(priv);
2432
2433 return err;
2434}
2435#endif
2436
0e405443
GP		 2437static int mlx5e_handle_feature(struct net_device *netdev,
2438 netdev_features_t wanted_features,
2439 netdev_features_t feature,
2440 mlx5e_feature_handler feature_handler)
2441{
2442 netdev_features_t changes = wanted_features ^ netdev->features;
2443 bool enable = !!(wanted_features & feature);
2444 int err;
2445
2446 if (!(changes & feature))
2447 return 0;
2448
2449 err = feature_handler(netdev, enable);
2450 if (err) {
2451 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2452 enable ? "Enable" : "Disable", feature, err);
2453 return err;
2454 }
2455
2456 MLX5E_SET_FEATURE(netdev, feature, enable);
2457 return 0;
2458}
2459
2460static int mlx5e_set_features(struct net_device *netdev,
2461 netdev_features_t features)
2462{
2463 int err;
2464
2465 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2466 set_feature_lro);
2467 err |= mlx5e_handle_feature(netdev, features,
2468 NETIF_F_HW_VLAN_CTAG_FILTER,
2469 set_feature_vlan_filter);
2470 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2471 set_feature_tc_num_filters);
94cb1ebb
EBE		 2472 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2473 set_feature_rx_all);
36350114
GP		 2474 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2475 set_feature_rx_vlan);
45bf454a
MG		 2476#ifdef CONFIG_RFS_ACCEL
2477 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2478 set_feature_arfs);
2479#endif
0e405443
GP		 2480
2481 return err ? -EINVAL : 0;
f62b8bb8
AV		 2482}
2483
d8edd246
SM		 2484#define MXL5_HW_MIN_MTU 64
2485#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2486
f62b8bb8
AV		 2487static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2488{
2489 struct mlx5e_priv *priv = netdev_priv(netdev);
2490 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2491 bool was_opened;
046339ea 2492 u16 max_mtu;
d8edd246 2493 u16 min_mtu;
98e81b0a 2494 int err = 0;
f62b8bb8 2495
facc9699 2496 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2497
50a9eea6 2498 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2499 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2500
d8edd246 2501 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2502 netdev_err(netdev,
d8edd246
SM		 2503 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2504 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2505 return -EINVAL;
2506 }
2507
2508 mutex_lock(&priv->state_lock);
98e81b0a
AS		 2509
2510 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2511 if (was_opened)
2512 mlx5e_close_locked(netdev);
2513
f62b8bb8 2514 netdev->mtu = new_mtu;
98e81b0a
AS		 2515
2516 if (was_opened)
2517 err = mlx5e_open_locked(netdev);
2518
f62b8bb8
AV		 2519 mutex_unlock(&priv->state_lock);
2520
2521 return err;
2522}
2523
ef9814de
EBE		 2524static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2525{
2526 switch (cmd) {
2527 case SIOCSHWTSTAMP:
2528 return mlx5e_hwstamp_set(dev, ifr);
2529 case SIOCGHWTSTAMP:
2530 return mlx5e_hwstamp_get(dev, ifr);
2531 default:
2532 return -EOPNOTSUPP;
2533 }
2534}
2535
66e49ded
SM		 2536static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2537{
2538 struct mlx5e_priv *priv = netdev_priv(dev);
2539 struct mlx5_core_dev *mdev = priv->mdev;
2540
2541 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2542}
2543
2544static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2545{
2546 struct mlx5e_priv *priv = netdev_priv(dev);
2547 struct mlx5_core_dev *mdev = priv->mdev;
2548
2549 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2550 vlan, qos);
2551}
2552
f942380c
MHY		 2553static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2554{
2555 struct mlx5e_priv *priv = netdev_priv(dev);
2556 struct mlx5_core_dev *mdev = priv->mdev;
2557
2558 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2559}
2560
1edc57e2
MHY		 2561static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2562{
2563 struct mlx5e_priv *priv = netdev_priv(dev);
2564 struct mlx5_core_dev *mdev = priv->mdev;
2565
2566 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2567}
66e49ded
SM		 2568static int mlx5_vport_link2ifla(u8 esw_link)
2569{
2570 switch (esw_link) {
2571 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2572 return IFLA_VF_LINK_STATE_DISABLE;
2573 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2574 return IFLA_VF_LINK_STATE_ENABLE;
2575 }
2576 return IFLA_VF_LINK_STATE_AUTO;
2577}
2578
2579static int mlx5_ifla_link2vport(u8 ifla_link)
2580{
2581 switch (ifla_link) {
2582 case IFLA_VF_LINK_STATE_DISABLE:
2583 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2584 case IFLA_VF_LINK_STATE_ENABLE:
2585 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2586 }
2587 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2588}
2589
2590static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2591 int link_state)
2592{
2593 struct mlx5e_priv *priv = netdev_priv(dev);
2594 struct mlx5_core_dev *mdev = priv->mdev;
2595
2596 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2597 mlx5_ifla_link2vport(link_state));
2598}
2599
2600static int mlx5e_get_vf_config(struct net_device *dev,
2601 int vf, struct ifla_vf_info *ivi)
2602{
2603 struct mlx5e_priv *priv = netdev_priv(dev);
2604 struct mlx5_core_dev *mdev = priv->mdev;
2605 int err;
2606
2607 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2608 if (err)
2609 return err;
2610 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2611 return 0;
2612}
2613
2614static int mlx5e_get_vf_stats(struct net_device *dev,
2615 int vf, struct ifla_vf_stats *vf_stats)
2616{
2617 struct mlx5e_priv *priv = netdev_priv(dev);
2618 struct mlx5_core_dev *mdev = priv->mdev;
2619
2620 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2621 vf_stats);
2622}
2623
b3f63c3d 2624static void mlx5e_add_vxlan_port(struct net_device *netdev,
974c3f30 2625 struct udp_tunnel_info *ti)
b3f63c3d
MF		 2626{
2627 struct mlx5e_priv *priv = netdev_priv(netdev);
2628
974c3f30
AD		 2629 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2630 return;
2631
b3f63c3d
MF		 2632 if (!mlx5e_vxlan_allowed(priv->mdev))
2633 return;
2634
974c3f30 2635 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 2636}
2637
2638static void mlx5e_del_vxlan_port(struct net_device *netdev,
974c3f30 2639 struct udp_tunnel_info *ti)
b3f63c3d
MF		 2640{
2641 struct mlx5e_priv *priv = netdev_priv(netdev);
2642
974c3f30
AD		 2643 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2644 return;
2645
b3f63c3d
MF		 2646 if (!mlx5e_vxlan_allowed(priv->mdev))
2647 return;
2648
974c3f30 2649 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 2650}
2651
2652static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2653 struct sk_buff *skb,
2654 netdev_features_t features)
2655{
2656 struct udphdr *udph;
2657 u16 proto;
2658 u16 port = 0;
2659
2660 switch (vlan_get_protocol(skb)) {
2661 case htons(ETH_P_IP):
2662 proto = ip_hdr(skb)->protocol;
2663 break;
2664 case htons(ETH_P_IPV6):
2665 proto = ipv6_hdr(skb)->nexthdr;
2666 break;
2667 default:
2668 goto out;
2669 }
2670
2671 if (proto == IPPROTO_UDP) {
2672 udph = udp_hdr(skb);
2673 port = be16_to_cpu(udph->dest);
2674 }
2675
2676 /* Verify if UDP port is being offloaded by HW */
2677 if (port && mlx5e_vxlan_lookup_port(priv, port))
2678 return features;
2679
2680out:
2681 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2682 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2683}
2684
2685static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2686 struct net_device *netdev,
2687 netdev_features_t features)
2688{
2689 struct mlx5e_priv *priv = netdev_priv(netdev);
2690
2691 features = vlan_features_check(skb, features);
2692 features = vxlan_features_check(skb, features);
2693
2694 /* Validate if the tunneled packet is being offloaded by HW */
2695 if (skb->encapsulation &&
2696 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2697 return mlx5e_vxlan_features_check(priv, skb, features);
2698
2699 return features;
2700}
2701
b0eed40e 2702static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2703 .ndo_open = mlx5e_open,
2704 .ndo_stop = mlx5e_close,
2705 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2706 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2707 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2708 .ndo_get_stats64 = mlx5e_get_stats,
2709 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2710 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2711 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2712 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2713 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2714 .ndo_change_mtu = mlx5e_change_mtu,
2715 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 2716 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 2717#ifdef CONFIG_RFS_ACCEL
2718 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2719#endif
b0eed40e
SM		 2720};
2721
2722static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2723 .ndo_open = mlx5e_open,
2724 .ndo_stop = mlx5e_close,
2725 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2726 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2727 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2728 .ndo_get_stats64 = mlx5e_get_stats,
2729 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2730 .ndo_set_mac_address = mlx5e_set_mac,
2731 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2732 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2733 .ndo_set_features = mlx5e_set_features,
2734 .ndo_change_mtu = mlx5e_change_mtu,
2735 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 2736 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
2737 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 2738 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 2739 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 2740#ifdef CONFIG_RFS_ACCEL
2741 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2742#endif
b0eed40e
SM		 2743 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2744 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 2745 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 2746 .ndo_set_vf_trust = mlx5e_set_vf_trust,
b0eed40e
SM		 2747 .ndo_get_vf_config = mlx5e_get_vf_config,
2748 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2749 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2750};
2751
2752static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2753{
2754 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2755 return -ENOTSUPP;
2756 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2757 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2758 !MLX5_CAP_ETH(mdev, csum_cap) ||
2759 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2760 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2761 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2762 MLX5_CAP_FLOWTABLE(mdev,
2763 flow_table_properties_nic_receive.max_ft_level)
2764 < 3) {
f62b8bb8
AV		 2765 mlx5_core_warn(mdev,
2766 "Not creating net device, some required device capabilities are missing\n");
2767 return -ENOTSUPP;
2768 }
66189961
TT		 2769 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2770 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2771 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2772 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2773
f62b8bb8
AV		 2774 return 0;
2775}
2776
58d52291
AS		 2777u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2778{
2779 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2780
2781 return bf_buf_size -
2782 sizeof(struct mlx5e_tx_wqe) +
2783 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2784}
2785
08fb1dac
SM		 2786#ifdef CONFIG_MLX5_CORE_EN_DCB
2787static void mlx5e_ets_init(struct mlx5e_priv *priv)
2788{
2789 int i;
2790
2791 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2792 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2793 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2794 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2795 priv->params.ets.prio_tc[i] = i;
2796 }
2797
2798 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2799 priv->params.ets.prio_tc[0] = 1;
2800 priv->params.ets.prio_tc[1] = 0;
2801}
2802#endif
2803
d8c9660d
TT		 2804void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2805 u32 *indirection_rqt, int len,
85082dba
TT		 2806 int num_channels)
2807{
d8c9660d
TT		 2808 int node = mdev->priv.numa_node;
2809 int node_num_of_cores;
85082dba
TT		 2810 int i;
2811
d8c9660d
TT		 2812 if (node == -1)
2813 node = first_online_node;
2814
2815 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2816
2817 if (node_num_of_cores)
2818 num_channels = min_t(int, num_channels, node_num_of_cores);
2819
85082dba
TT		 2820 for (i = 0; i < len; i++)
2821 indirection_rqt[i] = i % num_channels;
2822}
2823
bc77b240
TT		 2824static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2825{
2826 return MLX5_CAP_GEN(mdev, striding_rq) &&
2827 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2828 MLX5_CAP_ETH(mdev, reg_umr_sq);
2829}
2830
b797a684
SM		 2831static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2832{
2833 enum pcie_link_width width;
2834 enum pci_bus_speed speed;
2835 int err = 0;
2836
2837 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2838 if (err)
2839 return err;
2840
2841 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2842 return -EINVAL;
2843
2844 switch (speed) {
2845 case PCIE_SPEED_2_5GT:
2846 *pci_bw = 2500 * width;
2847 break;
2848 case PCIE_SPEED_5_0GT:
2849 *pci_bw = 5000 * width;
2850 break;
2851 case PCIE_SPEED_8_0GT:
2852 *pci_bw = 8000 * width;
2853 break;
2854 default:
2855 return -EINVAL;
2856 }
2857
2858 return 0;
2859}
2860
2861static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2862{
2863 return (link_speed && pci_bw &&
2864 (pci_bw < 40000) && (pci_bw < link_speed));
2865}
2866
9908aa29
TT		 2867void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2868{
2869 params->rx_cq_period_mode = cq_period_mode;
2870
2871 params->rx_cq_moderation.pkts =
2872 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2873 params->rx_cq_moderation.usec =
2874 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2875
2876 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2877 params->rx_cq_moderation.usec =
2878 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2879}
2880
6bfd390b
HHZ		 2881static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
2882 struct net_device *netdev,
2883 const struct mlx5e_profile *profile)
f62b8bb8
AV		 2884{
2885 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 2886 u32 link_speed = 0;
2887 u32 pci_bw = 0;
cb3c7fd4
GR		 2888 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2889 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
2890 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 2891
2892 priv->params.log_sq_size =
2893 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 2894 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 2895 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2896 MLX5_WQ_TYPE_LINKED_LIST;
2897
b797a684
SM		 2898 /* set CQE compression */
2899 priv->params.rx_cqe_compress_admin = false;
2900 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2901 MLX5_CAP_GEN(mdev, vport_group_manager)) {
2902 mlx5e_get_max_linkspeed(mdev, &link_speed);
2903 mlx5e_get_pci_bw(mdev, &pci_bw);
2904 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2905 link_speed, pci_bw);
2906 priv->params.rx_cqe_compress_admin =
2907 cqe_compress_heuristic(link_speed, pci_bw);
2908 }
2909
2910 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2911
461017cb
TT		 2912 switch (priv->params.rq_wq_type) {
2913 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2914 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
d9d9f156
TT		 2915 priv->params.mpwqe_log_stride_sz =
2916 priv->params.rx_cqe_compress ?
2917 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2918 MLX5_MPWRQ_LOG_STRIDE_SIZE;
2919 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2920 priv->params.mpwqe_log_stride_sz;
461017cb
TT		 2921 priv->params.lro_en = true;
2922 break;
2923 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2924 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2925 }
2926
d9d9f156
TT		 2927 mlx5_core_info(mdev,
2928 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2929 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2930 BIT(priv->params.log_rq_size),
2931 BIT(priv->params.mpwqe_log_stride_sz),
2932 priv->params.rx_cqe_compress_admin);
2933
461017cb
TT		 2934 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2935 BIT(priv->params.log_rq_size));
9908aa29 2936
cb3c7fd4
GR		 2937 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
2938 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 2939
2940 priv->params.tx_cq_moderation.usec =
f62b8bb8 2941 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 2942 priv->params.tx_cq_moderation.pkts =
f62b8bb8 2943 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2944 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8 2945 priv->params.num_tc = 1;
2be6967c 2946 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2947
57afead5
AS		 2948 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2949 sizeof(priv->params.toeplitz_hash_key));
2950
d8c9660d 2951 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 2952 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 2953
f62b8bb8
AV		 2954 priv->params.lro_wqe_sz =
2955 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2956
9908aa29
TT		 2957 /* Initialize pflags */
2958 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
2959 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2960
f62b8bb8
AV		 2961 priv->mdev = mdev;
2962 priv->netdev = netdev;
6bfd390b
HHZ		 2963 priv->params.num_channels = profile->max_nch(mdev);
2964 priv->profile = profile;
f62b8bb8 2965
08fb1dac
SM		 2966#ifdef CONFIG_MLX5_CORE_EN_DCB
2967 mlx5e_ets_init(priv);
2968#endif
f62b8bb8 2969
f62b8bb8
AV		 2970 mutex_init(&priv->state_lock);
2971
2972 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2973 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2974 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2975}
2976
2977static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2978{
2979 struct mlx5e_priv *priv = netdev_priv(netdev);
2980
e1d7d349 2981 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2982 if (is_zero_ether_addr(netdev->dev_addr) &&
2983 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2984 eth_hw_addr_random(netdev);
2985 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2986 }
f62b8bb8
AV		 2987}
2988
6bfd390b 2989static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 2990{
2991 struct mlx5e_priv *priv = netdev_priv(netdev);
2992 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 2993 bool fcs_supported;
2994 bool fcs_enabled;
f62b8bb8
AV		 2995
2996 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2997
08fb1dac 2998 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2999 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 3000#ifdef CONFIG_MLX5_CORE_EN_DCB
3001 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3002#endif
3003 } else {
b0eed40e 3004 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3005 }
66e49ded 3006
f62b8bb8
AV		 3007 netdev->watchdog_timeo = 15 * HZ;
3008
3009 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3010
12be4b21 3011 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3012 netdev->vlan_features |= NETIF_F_IP_CSUM;
3013 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3014 netdev->vlan_features |= NETIF_F_GRO;
3015 netdev->vlan_features |= NETIF_F_TSO;
3016 netdev->vlan_features |= NETIF_F_TSO6;
3017 netdev->vlan_features |= NETIF_F_RXCSUM;
3018 netdev->vlan_features |= NETIF_F_RXHASH;
3019
3020 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3021 netdev->vlan_features |= NETIF_F_LRO;
3022
3023 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3024 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3025 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3026 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3027
b3f63c3d 3028 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3029 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3030 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3031 NETIF_F_GSO_PARTIAL;
b3f63c3d 3032 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3033 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3034 netdev->hw_enc_features |= NETIF_F_TSO;
3035 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3036 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3037 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3038 NETIF_F_GSO_PARTIAL;
3039 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3040 }
3041
94cb1ebb
EBE		 3042 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3043
3044 if (fcs_supported)
3045 netdev->hw_features |= NETIF_F_RXALL;
3046
f62b8bb8
AV		 3047 netdev->features = netdev->hw_features;
3048 if (!priv->params.lro_en)
3049 netdev->features &= ~NETIF_F_LRO;
3050
94cb1ebb
EBE		 3051 if (fcs_enabled)
3052 netdev->features &= ~NETIF_F_RXALL;
3053
e8f887ac
AV		 3054#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3055 if (FT_CAP(flow_modify_en) &&
3056 FT_CAP(modify_root) &&
3057 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3058 FT_CAP(flow_table_modify)) {
3059 netdev->hw_features |= NETIF_F_HW_TC;
3060#ifdef CONFIG_RFS_ACCEL
3061 netdev->hw_features |= NETIF_F_NTUPLE;
3062#endif
3063 }
e8f887ac 3064
f62b8bb8
AV		 3065 netdev->features |= NETIF_F_HIGHDMA;
3066
3067 netdev->priv_flags |= IFF_UNICAST_FLT;
3068
3069 mlx5e_set_netdev_dev_addr(netdev);
3070}
3071
593cf338
RS		 3072static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3073{
3074 struct mlx5_core_dev *mdev = priv->mdev;
3075 int err;
3076
3077 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3078 if (err) {
3079 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3080 priv->q_counter = 0;
3081 }
3082}
3083
3084static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3085{
3086 if (!priv->q_counter)
3087 return;
3088
3089 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3090}
3091
bc77b240
TT		 3092static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3093{
3094 struct mlx5_core_dev *mdev = priv->mdev;
3095 struct mlx5_create_mkey_mbox_in *in;
3096 struct mlx5_mkey_seg *mkc;
3097 int inlen = sizeof(*in);
3098 u64 npages =
6bfd390b 3099 priv->profile->max_nch(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
bc77b240
TT		 3100 int err;
3101
3102 in = mlx5_vzalloc(inlen);
3103 if (!in)
3104 return -ENOMEM;
3105
3106 mkc = &in->seg;
3107 mkc->status = MLX5_MKEY_STATUS_FREE;
3108 mkc->flags = MLX5_PERM_UMR_EN |
3109 MLX5_PERM_LOCAL_READ |
3110 MLX5_PERM_LOCAL_WRITE |
3111 MLX5_ACCESS_MODE_MTT;
3112
3113 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
b50d292b 3114 mkc->flags_pd = cpu_to_be32(mdev->mlx5e_res.pdn);
bc77b240
TT		 3115 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3116 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3117 mkc->log2_page_size = PAGE_SHIFT;
3118
3119 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3120 NULL, NULL);
3121
3122 kvfree(in);
3123
3124 return err;
3125}
3126
6bfd390b
HHZ		 3127static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3128 struct net_device *netdev,
3129 const struct mlx5e_profile *profile)
3130{
3131 struct mlx5e_priv *priv = netdev_priv(netdev);
3132
3133 mlx5e_build_nic_netdev_priv(mdev, netdev, profile);
3134 mlx5e_build_nic_netdev(netdev);
3135 mlx5e_vxlan_init(priv);
3136}
3137
3138static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3139{
3140 mlx5e_vxlan_cleanup(priv);
3141}
3142
3143static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3144{
3145 struct mlx5_core_dev *mdev = priv->mdev;
3146 int err;
3147 int i;
3148
3149 err = mlx5e_create_indirect_rqts(priv);
3150 if (err) {
3151 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3152 return err;
3153 }
3154
3155 err = mlx5e_create_direct_rqts(priv);
3156 if (err) {
3157 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3158 goto err_destroy_indirect_rqts;
3159 }
3160
3161 err = mlx5e_create_indirect_tirs(priv);
3162 if (err) {
3163 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3164 goto err_destroy_direct_rqts;
3165 }
3166
3167 err = mlx5e_create_direct_tirs(priv);
3168 if (err) {
3169 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3170 goto err_destroy_indirect_tirs;
3171 }
3172
3173 err = mlx5e_create_flow_steering(priv);
3174 if (err) {
3175 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3176 goto err_destroy_direct_tirs;
3177 }
3178
3179 err = mlx5e_tc_init(priv);
3180 if (err)
3181 goto err_destroy_flow_steering;
3182
3183 return 0;
3184
3185err_destroy_flow_steering:
3186 mlx5e_destroy_flow_steering(priv);
3187err_destroy_direct_tirs:
3188 mlx5e_destroy_direct_tirs(priv);
3189err_destroy_indirect_tirs:
3190 mlx5e_destroy_indirect_tirs(priv);
3191err_destroy_direct_rqts:
3192 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3193 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3194err_destroy_indirect_rqts:
3195 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3196 return err;
3197}
3198
3199static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3200{
3201 int i;
3202
3203 mlx5e_tc_cleanup(priv);
3204 mlx5e_destroy_flow_steering(priv);
3205 mlx5e_destroy_direct_tirs(priv);
3206 mlx5e_destroy_indirect_tirs(priv);
3207 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3208 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3209 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3210}
3211
3212static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3213{
3214 int err;
3215
3216 err = mlx5e_create_tises(priv);
3217 if (err) {
3218 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3219 return err;
3220 }
3221
3222#ifdef CONFIG_MLX5_CORE_EN_DCB
3223 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3224#endif
3225 return 0;
3226}
3227
3228static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3229{
3230 struct net_device *netdev = priv->netdev;
3231 struct mlx5_core_dev *mdev = priv->mdev;
3232
3233 if (mlx5e_vxlan_allowed(mdev)) {
3234 rtnl_lock();
3235 udp_tunnel_get_rx_info(netdev);
3236 rtnl_unlock();
3237 }
3238
3239 mlx5e_enable_async_events(priv);
3240 queue_work(priv->wq, &priv->set_rx_mode_work);
3241}
3242
3243static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3244{
3245 queue_work(priv->wq, &priv->set_rx_mode_work);
3246 mlx5e_disable_async_events(priv);
3247}
3248
3249static const struct mlx5e_profile mlx5e_nic_profile = {
3250 .init = mlx5e_nic_init,
3251 .cleanup = mlx5e_nic_cleanup,
3252 .init_rx = mlx5e_init_nic_rx,
3253 .cleanup_rx = mlx5e_cleanup_nic_rx,
3254 .init_tx = mlx5e_init_nic_tx,
3255 .cleanup_tx = mlx5e_cleanup_nic_tx,
3256 .enable = mlx5e_nic_enable,
3257 .disable = mlx5e_nic_disable,
3258 .update_stats = mlx5e_update_stats,
3259 .max_nch = mlx5e_get_max_num_channels,
3260 .max_tc = MLX5E_MAX_NUM_TC,
3261};
3262
3263static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3264 const struct mlx5e_profile *profile)
f62b8bb8
AV		 3265{
3266 struct net_device *netdev;
3267 struct mlx5e_priv *priv;
6bfd390b 3268 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3269 int err;
3270
08fb1dac 3271 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3272 nch * profile->max_tc,
08fb1dac 3273 nch);
f62b8bb8
AV		 3274 if (!netdev) {
3275 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3276 return NULL;
3277 }
3278
6bfd390b 3279 profile->init(mdev, netdev, profile);
f62b8bb8
AV		 3280
3281 netif_carrier_off(netdev);
3282
3283 priv = netdev_priv(netdev);
3284
7bb29755
MF		 3285 priv->wq = create_singlethread_workqueue("mlx5e");
3286 if (!priv->wq)
3287 goto err_free_netdev;
3288
bc77b240
TT		 3289 err = mlx5e_create_umr_mkey(priv);
3290 if (err) {
3291 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
b50d292b 3292 goto err_destroy_wq;
bc77b240
TT		 3293 }
3294
6bfd390b
HHZ		 3295 err = profile->init_tx(priv);
3296 if (err)
bc77b240 3297 goto err_destroy_umr_mkey;
5c50368f
AS		 3298
3299 err = mlx5e_open_drop_rq(priv);
3300 if (err) {
3301 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3302 goto err_cleanup_tx;
5c50368f
AS		 3303 }
3304
6bfd390b
HHZ		 3305 err = profile->init_rx(priv);
3306 if (err)
5c50368f 3307 goto err_close_drop_rq;
5c50368f 3308
593cf338
RS		 3309 mlx5e_create_q_counter(priv);
3310
33cfaaa8 3311 mlx5e_init_l2_addr(priv);
5c50368f 3312
f62b8bb8
AV		 3313 err = register_netdev(netdev);
3314 if (err) {
1f2a3003 3315 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
6bfd390b 3316 goto err_dealloc_q_counters;
01a14098 3317 }
b3f63c3d 3318
6bfd390b
HHZ		 3319 if (profile->enable)
3320 profile->enable(priv);
f62b8bb8
AV		 3321
3322 return priv;
3323
593cf338
RS		 3324err_dealloc_q_counters:
3325 mlx5e_destroy_q_counter(priv);
6bfd390b 3326 profile->cleanup_rx(priv);
5c50368f
AS		 3327
3328err_close_drop_rq:
3329 mlx5e_close_drop_rq(priv);
3330
6bfd390b
HHZ		 3331err_cleanup_tx:
3332 profile->cleanup_tx(priv);
5c50368f 3333
bc77b240
TT		 3334err_destroy_umr_mkey:
3335 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3336
7bb29755
MF		 3337err_destroy_wq:
3338 destroy_workqueue(priv->wq);
3339
f62b8bb8
AV		 3340err_free_netdev:
3341 free_netdev(netdev);
3342
3343 return NULL;
3344}
3345
b50d292b
HHZ		 3346static void *mlx5e_add(struct mlx5_core_dev *mdev)
3347{
3348 void *ret;
3349
3350 if (mlx5e_check_required_hca_cap(mdev))
3351 return NULL;
3352
3353 if (mlx5e_create_mdev_resources(mdev))
3354 return NULL;
3355
6bfd390b 3356 ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile);
b50d292b
HHZ		 3357 if (!ret) {
3358 mlx5e_destroy_mdev_resources(mdev);
3359 return NULL;
3360 }
3361 return ret;
3362}
3363
6bfd390b 3364static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 3365{
6bfd390b 3366 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 3367 struct net_device *netdev = priv->netdev;
3368
9b37b07f 3369 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
6bfd390b
HHZ		 3370 if (profile->disable)
3371 profile->disable(priv);
9b37b07f 3372
7bb29755 3373 flush_workqueue(priv->wq);
5fc7197d
MD		 3374 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3375 netif_device_detach(netdev);
811afeaa 3376 mlx5e_close(netdev);
5fc7197d
MD		 3377 } else {
3378 unregister_netdev(netdev);
3379 }
3380
593cf338 3381 mlx5e_destroy_q_counter(priv);
6bfd390b 3382 profile->cleanup_rx(priv);
5c50368f 3383 mlx5e_close_drop_rq(priv);
6bfd390b 3384 profile->cleanup_tx(priv);
bc77b240 3385 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
7bb29755
MF		 3386 cancel_delayed_work_sync(&priv->update_stats_work);
3387 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 3388 if (profile->cleanup)
3389 profile->cleanup(priv);
5fc7197d
MD		 3390
3391 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3392 free_netdev(netdev);
f62b8bb8
AV		 3393}
3394
b50d292b
HHZ		 3395static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3396{
3397 struct mlx5e_priv *priv = vpriv;
3398
3399 mlx5e_destroy_netdev(mdev, priv);
3400 mlx5e_destroy_mdev_resources(mdev);
3401}
3402
f62b8bb8
AV		 3403static void *mlx5e_get_netdev(void *vpriv)
3404{
3405 struct mlx5e_priv *priv = vpriv;
3406
3407 return priv->netdev;
3408}
3409
3410static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 3411 .add = mlx5e_add,
3412 .remove = mlx5e_remove,
f62b8bb8
AV		 3413 .event = mlx5e_async_event,
3414 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3415 .get_dev = mlx5e_get_netdev,
3416};
3417
3418void mlx5e_init(void)
3419{
665bc539 3420 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 3421 mlx5_register_interface(&mlx5e_interface);
3422}
3423
3424void mlx5e_cleanup(void)
3425{
3426 mlx5_unregister_interface(&mlx5e_interface);
3427}
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