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f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac AV |
33 | #include <net/tc_act/tc_gact.h> |
34 | #include <net/pkt_cls.h> | |
86d722ad | 35 | #include <linux/mlx5/fs.h> |
b3f63c3d | 36 | #include <net/vxlan.h> |
f62b8bb8 | 37 | #include "en.h" |
e8f887ac | 38 | #include "en_tc.h" |
66e49ded | 39 | #include "eswitch.h" |
b3f63c3d | 40 | #include "vxlan.h" |
f62b8bb8 AV |
41 | |
42 | struct mlx5e_rq_param { | |
cb3c7fd4 GR |
43 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; |
44 | struct mlx5_wq_param wq; | |
45 | bool am_enabled; | |
f62b8bb8 AV |
46 | }; |
47 | ||
48 | struct mlx5e_sq_param { | |
49 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
50 | struct mlx5_wq_param wq; | |
58d52291 | 51 | u16 max_inline; |
d3c9bc27 | 52 | bool icosq; |
f62b8bb8 AV |
53 | }; |
54 | ||
55 | struct mlx5e_cq_param { | |
56 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
57 | struct mlx5_wq_param wq; | |
58 | u16 eq_ix; | |
9908aa29 | 59 | u8 cq_period_mode; |
f62b8bb8 AV |
60 | }; |
61 | ||
62 | struct mlx5e_channel_param { | |
63 | struct mlx5e_rq_param rq; | |
64 | struct mlx5e_sq_param sq; | |
d3c9bc27 | 65 | struct mlx5e_sq_param icosq; |
f62b8bb8 AV |
66 | struct mlx5e_cq_param rx_cq; |
67 | struct mlx5e_cq_param tx_cq; | |
d3c9bc27 | 68 | struct mlx5e_cq_param icosq_cq; |
f62b8bb8 AV |
69 | }; |
70 | ||
71 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) | |
72 | { | |
73 | struct mlx5_core_dev *mdev = priv->mdev; | |
74 | u8 port_state; | |
75 | ||
76 | port_state = mlx5_query_vport_state(mdev, | |
e7546514 | 77 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); |
f62b8bb8 AV |
78 | |
79 | if (port_state == VPORT_STATE_UP) | |
80 | netif_carrier_on(priv->netdev); | |
81 | else | |
82 | netif_carrier_off(priv->netdev); | |
83 | } | |
84 | ||
85 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
86 | { | |
87 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
88 | update_carrier_work); | |
89 | ||
90 | mutex_lock(&priv->state_lock); | |
91 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
92 | mlx5e_update_carrier(priv); | |
93 | mutex_unlock(&priv->state_lock); | |
94 | } | |
95 | ||
9218b44d | 96 | static void mlx5e_update_sw_counters(struct mlx5e_priv *priv) |
f62b8bb8 | 97 | { |
9218b44d | 98 | struct mlx5e_sw_stats *s = &priv->stats.sw; |
f62b8bb8 AV |
99 | struct mlx5e_rq_stats *rq_stats; |
100 | struct mlx5e_sq_stats *sq_stats; | |
9218b44d | 101 | u64 tx_offload_none = 0; |
f62b8bb8 AV |
102 | int i, j; |
103 | ||
9218b44d | 104 | memset(s, 0, sizeof(*s)); |
f62b8bb8 AV |
105 | for (i = 0; i < priv->params.num_channels; i++) { |
106 | rq_stats = &priv->channel[i]->rq.stats; | |
107 | ||
faf4478b GP |
108 | s->rx_packets += rq_stats->packets; |
109 | s->rx_bytes += rq_stats->bytes; | |
bfe6d8d1 GP |
110 | s->rx_lro_packets += rq_stats->lro_packets; |
111 | s->rx_lro_bytes += rq_stats->lro_bytes; | |
f62b8bb8 | 112 | s->rx_csum_none += rq_stats->csum_none; |
bfe6d8d1 GP |
113 | s->rx_csum_complete += rq_stats->csum_complete; |
114 | s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner; | |
f62b8bb8 | 115 | s->rx_wqe_err += rq_stats->wqe_err; |
461017cb | 116 | s->rx_mpwqe_filler += rq_stats->mpwqe_filler; |
bc77b240 | 117 | s->rx_mpwqe_frag += rq_stats->mpwqe_frag; |
54984407 | 118 | s->rx_buff_alloc_err += rq_stats->buff_alloc_err; |
7219ab34 TT |
119 | s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; |
120 | s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; | |
f62b8bb8 | 121 | |
a4418a6c | 122 | for (j = 0; j < priv->params.num_tc; j++) { |
f62b8bb8 AV |
123 | sq_stats = &priv->channel[i]->sq[j].stats; |
124 | ||
faf4478b GP |
125 | s->tx_packets += sq_stats->packets; |
126 | s->tx_bytes += sq_stats->bytes; | |
bfe6d8d1 GP |
127 | s->tx_tso_packets += sq_stats->tso_packets; |
128 | s->tx_tso_bytes += sq_stats->tso_bytes; | |
129 | s->tx_tso_inner_packets += sq_stats->tso_inner_packets; | |
130 | s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes; | |
f62b8bb8 AV |
131 | s->tx_queue_stopped += sq_stats->stopped; |
132 | s->tx_queue_wake += sq_stats->wake; | |
133 | s->tx_queue_dropped += sq_stats->dropped; | |
bfe6d8d1 GP |
134 | s->tx_csum_partial_inner += sq_stats->csum_partial_inner; |
135 | tx_offload_none += sq_stats->csum_none; | |
f62b8bb8 AV |
136 | } |
137 | } | |
138 | ||
9218b44d | 139 | /* Update calculated offload counters */ |
bfe6d8d1 GP |
140 | s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner; |
141 | s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete; | |
121fcdc8 | 142 | |
bfe6d8d1 | 143 | s->link_down_events_phy = MLX5_GET(ppcnt_reg, |
121fcdc8 GP |
144 | priv->stats.pport.phy_counters, |
145 | counter_set.phys_layer_cntrs.link_down_events); | |
9218b44d GP |
146 | } |
147 | ||
148 | static void mlx5e_update_vport_counters(struct mlx5e_priv *priv) | |
149 | { | |
150 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
151 | u32 *out = (u32 *)priv->stats.vport.query_vport_out; | |
152 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; | |
153 | struct mlx5_core_dev *mdev = priv->mdev; | |
154 | ||
f62b8bb8 AV |
155 | memset(in, 0, sizeof(in)); |
156 | ||
157 | MLX5_SET(query_vport_counter_in, in, opcode, | |
158 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
159 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
160 | MLX5_SET(query_vport_counter_in, in, other_vport, 0); | |
161 | ||
162 | memset(out, 0, outlen); | |
163 | ||
9218b44d GP |
164 | mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); |
165 | } | |
166 | ||
167 | static void mlx5e_update_pport_counters(struct mlx5e_priv *priv) | |
168 | { | |
169 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; | |
170 | struct mlx5_core_dev *mdev = priv->mdev; | |
171 | int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); | |
cf678570 | 172 | int prio; |
9218b44d GP |
173 | void *out; |
174 | u32 *in; | |
175 | ||
176 | in = mlx5_vzalloc(sz); | |
177 | if (!in) | |
f62b8bb8 AV |
178 | goto free_out; |
179 | ||
9218b44d | 180 | MLX5_SET(ppcnt_reg, in, local_port, 1); |
f62b8bb8 | 181 | |
9218b44d GP |
182 | out = pstats->IEEE_802_3_counters; |
183 | MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); | |
184 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
f62b8bb8 | 185 | |
9218b44d GP |
186 | out = pstats->RFC_2863_counters; |
187 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); | |
188 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
189 | ||
190 | out = pstats->RFC_2819_counters; | |
191 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); | |
192 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
593cf338 | 193 | |
121fcdc8 GP |
194 | out = pstats->phy_counters; |
195 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); | |
196 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
197 | ||
cf678570 GP |
198 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); |
199 | for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { | |
200 | out = pstats->per_prio_counters[prio]; | |
201 | MLX5_SET(ppcnt_reg, in, prio_tc, prio); | |
202 | mlx5_core_access_reg(mdev, in, sz, out, sz, | |
203 | MLX5_REG_PPCNT, 0, 0); | |
204 | } | |
205 | ||
f62b8bb8 | 206 | free_out: |
9218b44d GP |
207 | kvfree(in); |
208 | } | |
209 | ||
210 | static void mlx5e_update_q_counter(struct mlx5e_priv *priv) | |
211 | { | |
212 | struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; | |
213 | ||
214 | if (!priv->q_counter) | |
215 | return; | |
216 | ||
217 | mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter, | |
218 | &qcnt->rx_out_of_buffer); | |
219 | } | |
220 | ||
221 | void mlx5e_update_stats(struct mlx5e_priv *priv) | |
222 | { | |
9218b44d GP |
223 | mlx5e_update_q_counter(priv); |
224 | mlx5e_update_vport_counters(priv); | |
225 | mlx5e_update_pport_counters(priv); | |
121fcdc8 | 226 | mlx5e_update_sw_counters(priv); |
f62b8bb8 AV |
227 | } |
228 | ||
229 | static void mlx5e_update_stats_work(struct work_struct *work) | |
230 | { | |
231 | struct delayed_work *dwork = to_delayed_work(work); | |
232 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
233 | update_stats_work); | |
234 | mutex_lock(&priv->state_lock); | |
235 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
236 | mlx5e_update_stats(priv); | |
7bb29755 MF |
237 | queue_delayed_work(priv->wq, dwork, |
238 | msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL)); | |
f62b8bb8 AV |
239 | } |
240 | mutex_unlock(&priv->state_lock); | |
241 | } | |
242 | ||
daa21560 TT |
243 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
244 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 245 | { |
daa21560 TT |
246 | struct mlx5e_priv *priv = vpriv; |
247 | ||
e0f46eb9 | 248 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state)) |
daa21560 TT |
249 | return; |
250 | ||
f62b8bb8 AV |
251 | switch (event) { |
252 | case MLX5_DEV_EVENT_PORT_UP: | |
253 | case MLX5_DEV_EVENT_PORT_DOWN: | |
7bb29755 | 254 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 AV |
255 | break; |
256 | ||
257 | default: | |
258 | break; | |
259 | } | |
260 | } | |
261 | ||
f62b8bb8 AV |
262 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
263 | { | |
e0f46eb9 | 264 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
f62b8bb8 AV |
265 | } |
266 | ||
267 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
268 | { | |
e0f46eb9 | 269 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
daa21560 | 270 | synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
271 | } |
272 | ||
facc9699 SM |
273 | #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
274 | #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
275 | ||
f62b8bb8 AV |
276 | static int mlx5e_create_rq(struct mlx5e_channel *c, |
277 | struct mlx5e_rq_param *param, | |
278 | struct mlx5e_rq *rq) | |
279 | { | |
280 | struct mlx5e_priv *priv = c->priv; | |
281 | struct mlx5_core_dev *mdev = priv->mdev; | |
282 | void *rqc = param->rqc; | |
283 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
461017cb | 284 | u32 byte_count; |
f62b8bb8 AV |
285 | int wq_sz; |
286 | int err; | |
287 | int i; | |
288 | ||
311c7c71 SM |
289 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
290 | ||
f62b8bb8 AV |
291 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, |
292 | &rq->wq_ctrl); | |
293 | if (err) | |
294 | return err; | |
295 | ||
296 | rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; | |
297 | ||
298 | wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
f62b8bb8 | 299 | |
461017cb TT |
300 | switch (priv->params.rq_wq_type) { |
301 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
302 | rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info), | |
303 | GFP_KERNEL, cpu_to_node(c->cpu)); | |
304 | if (!rq->wqe_info) { | |
305 | err = -ENOMEM; | |
306 | goto err_rq_wq_destroy; | |
307 | } | |
308 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq; | |
309 | rq->alloc_wqe = mlx5e_alloc_rx_mpwqe; | |
310 | ||
d9d9f156 TT |
311 | rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz); |
312 | rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides); | |
313 | rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides; | |
461017cb TT |
314 | byte_count = rq->wqe_sz; |
315 | break; | |
316 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
317 | rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL, | |
318 | cpu_to_node(c->cpu)); | |
319 | if (!rq->skb) { | |
320 | err = -ENOMEM; | |
321 | goto err_rq_wq_destroy; | |
322 | } | |
323 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe; | |
324 | rq->alloc_wqe = mlx5e_alloc_rx_wqe; | |
325 | ||
326 | rq->wqe_sz = (priv->params.lro_en) ? | |
327 | priv->params.lro_wqe_sz : | |
328 | MLX5E_SW2HW_MTU(priv->netdev->mtu); | |
c5adb96f TT |
329 | rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz); |
330 | byte_count = rq->wqe_sz; | |
461017cb TT |
331 | byte_count |= MLX5_HW_START_PADDING; |
332 | } | |
f62b8bb8 AV |
333 | |
334 | for (i = 0; i < wq_sz; i++) { | |
335 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); | |
336 | ||
461017cb | 337 | wqe->data.byte_count = cpu_to_be32(byte_count); |
f62b8bb8 AV |
338 | } |
339 | ||
cb3c7fd4 GR |
340 | INIT_WORK(&rq->am.work, mlx5e_rx_am_work); |
341 | rq->am.mode = priv->params.rx_cq_period_mode; | |
342 | ||
461017cb | 343 | rq->wq_type = priv->params.rq_wq_type; |
f62b8bb8 AV |
344 | rq->pdev = c->pdev; |
345 | rq->netdev = c->netdev; | |
ef9814de | 346 | rq->tstamp = &priv->tstamp; |
f62b8bb8 AV |
347 | rq->channel = c; |
348 | rq->ix = c->ix; | |
50cfa25a | 349 | rq->priv = c->priv; |
bc77b240 TT |
350 | rq->mkey_be = c->mkey_be; |
351 | rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key); | |
f62b8bb8 AV |
352 | |
353 | return 0; | |
354 | ||
355 | err_rq_wq_destroy: | |
356 | mlx5_wq_destroy(&rq->wq_ctrl); | |
357 | ||
358 | return err; | |
359 | } | |
360 | ||
361 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) | |
362 | { | |
461017cb TT |
363 | switch (rq->wq_type) { |
364 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
365 | kfree(rq->wqe_info); | |
366 | break; | |
367 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
368 | kfree(rq->skb); | |
369 | } | |
370 | ||
f62b8bb8 AV |
371 | mlx5_wq_destroy(&rq->wq_ctrl); |
372 | } | |
373 | ||
374 | static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) | |
375 | { | |
50cfa25a | 376 | struct mlx5e_priv *priv = rq->priv; |
f62b8bb8 AV |
377 | struct mlx5_core_dev *mdev = priv->mdev; |
378 | ||
379 | void *in; | |
380 | void *rqc; | |
381 | void *wq; | |
382 | int inlen; | |
383 | int err; | |
384 | ||
385 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
386 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
387 | in = mlx5_vzalloc(inlen); | |
388 | if (!in) | |
389 | return -ENOMEM; | |
390 | ||
391 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
392 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
393 | ||
394 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
395 | ||
97de9f31 | 396 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 AV |
397 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
398 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
36350114 | 399 | MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable); |
f62b8bb8 | 400 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 401 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
402 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
403 | ||
404 | mlx5_fill_page_array(&rq->wq_ctrl.buf, | |
405 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
406 | ||
7db22ffb | 407 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
408 | |
409 | kvfree(in); | |
410 | ||
411 | return err; | |
412 | } | |
413 | ||
36350114 GP |
414 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, |
415 | int next_state) | |
f62b8bb8 AV |
416 | { |
417 | struct mlx5e_channel *c = rq->channel; | |
418 | struct mlx5e_priv *priv = c->priv; | |
419 | struct mlx5_core_dev *mdev = priv->mdev; | |
420 | ||
421 | void *in; | |
422 | void *rqc; | |
423 | int inlen; | |
424 | int err; | |
425 | ||
426 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
427 | in = mlx5_vzalloc(inlen); | |
428 | if (!in) | |
429 | return -ENOMEM; | |
430 | ||
431 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
432 | ||
433 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
434 | MLX5_SET(rqc, rqc, state, next_state); | |
435 | ||
7db22ffb | 436 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
437 | |
438 | kvfree(in); | |
439 | ||
440 | return err; | |
441 | } | |
442 | ||
36350114 GP |
443 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) |
444 | { | |
445 | struct mlx5e_channel *c = rq->channel; | |
446 | struct mlx5e_priv *priv = c->priv; | |
447 | struct mlx5_core_dev *mdev = priv->mdev; | |
448 | ||
449 | void *in; | |
450 | void *rqc; | |
451 | int inlen; | |
452 | int err; | |
453 | ||
454 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
455 | in = mlx5_vzalloc(inlen); | |
456 | if (!in) | |
457 | return -ENOMEM; | |
458 | ||
459 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
460 | ||
461 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
462 | MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD); | |
463 | MLX5_SET(rqc, rqc, vsd, vsd); | |
464 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
465 | ||
466 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
467 | ||
468 | kvfree(in); | |
469 | ||
470 | return err; | |
471 | } | |
472 | ||
f62b8bb8 AV |
473 | static void mlx5e_disable_rq(struct mlx5e_rq *rq) |
474 | { | |
50cfa25a | 475 | mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn); |
f62b8bb8 AV |
476 | } |
477 | ||
478 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) | |
479 | { | |
01c196a2 | 480 | unsigned long exp_time = jiffies + msecs_to_jiffies(20000); |
f62b8bb8 AV |
481 | struct mlx5e_channel *c = rq->channel; |
482 | struct mlx5e_priv *priv = c->priv; | |
483 | struct mlx5_wq_ll *wq = &rq->wq; | |
f62b8bb8 | 484 | |
01c196a2 | 485 | while (time_before(jiffies, exp_time)) { |
f62b8bb8 AV |
486 | if (wq->cur_sz >= priv->params.min_rx_wqes) |
487 | return 0; | |
488 | ||
489 | msleep(20); | |
490 | } | |
491 | ||
492 | return -ETIMEDOUT; | |
493 | } | |
494 | ||
495 | static int mlx5e_open_rq(struct mlx5e_channel *c, | |
496 | struct mlx5e_rq_param *param, | |
497 | struct mlx5e_rq *rq) | |
498 | { | |
d3c9bc27 TT |
499 | struct mlx5e_sq *sq = &c->icosq; |
500 | u16 pi = sq->pc & sq->wq.sz_m1; | |
f62b8bb8 AV |
501 | int err; |
502 | ||
503 | err = mlx5e_create_rq(c, param, rq); | |
504 | if (err) | |
505 | return err; | |
506 | ||
507 | err = mlx5e_enable_rq(rq, param); | |
508 | if (err) | |
509 | goto err_destroy_rq; | |
510 | ||
36350114 | 511 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
f62b8bb8 AV |
512 | if (err) |
513 | goto err_disable_rq; | |
514 | ||
cb3c7fd4 GR |
515 | if (param->am_enabled) |
516 | set_bit(MLX5E_RQ_STATE_AM, &c->rq.state); | |
517 | ||
f62b8bb8 | 518 | set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); |
d3c9bc27 TT |
519 | |
520 | sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP; | |
521 | sq->ico_wqe_info[pi].num_wqebbs = 1; | |
522 | mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */ | |
f62b8bb8 AV |
523 | |
524 | return 0; | |
525 | ||
526 | err_disable_rq: | |
527 | mlx5e_disable_rq(rq); | |
528 | err_destroy_rq: | |
529 | mlx5e_destroy_rq(rq); | |
530 | ||
531 | return err; | |
532 | } | |
533 | ||
534 | static void mlx5e_close_rq(struct mlx5e_rq *rq) | |
535 | { | |
536 | clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); | |
537 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ | |
538 | ||
36350114 | 539 | mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); |
f62b8bb8 AV |
540 | while (!mlx5_wq_ll_is_empty(&rq->wq)) |
541 | msleep(20); | |
542 | ||
543 | /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */ | |
544 | napi_synchronize(&rq->channel->napi); | |
545 | ||
cb3c7fd4 GR |
546 | cancel_work_sync(&rq->am.work); |
547 | ||
f62b8bb8 AV |
548 | mlx5e_disable_rq(rq); |
549 | mlx5e_destroy_rq(rq); | |
550 | } | |
551 | ||
552 | static void mlx5e_free_sq_db(struct mlx5e_sq *sq) | |
553 | { | |
34802a42 | 554 | kfree(sq->wqe_info); |
f62b8bb8 AV |
555 | kfree(sq->dma_fifo); |
556 | kfree(sq->skb); | |
557 | } | |
558 | ||
559 | static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa) | |
560 | { | |
561 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
562 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
563 | ||
564 | sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa); | |
565 | sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL, | |
566 | numa); | |
34802a42 AS |
567 | sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL, |
568 | numa); | |
f62b8bb8 | 569 | |
34802a42 | 570 | if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) { |
f62b8bb8 AV |
571 | mlx5e_free_sq_db(sq); |
572 | return -ENOMEM; | |
573 | } | |
574 | ||
575 | sq->dma_fifo_mask = df_sz - 1; | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | static int mlx5e_create_sq(struct mlx5e_channel *c, | |
581 | int tc, | |
582 | struct mlx5e_sq_param *param, | |
583 | struct mlx5e_sq *sq) | |
584 | { | |
585 | struct mlx5e_priv *priv = c->priv; | |
586 | struct mlx5_core_dev *mdev = priv->mdev; | |
587 | ||
588 | void *sqc = param->sqc; | |
589 | void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
590 | int err; | |
591 | ||
fd4782c2 | 592 | err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf)); |
f62b8bb8 AV |
593 | if (err) |
594 | return err; | |
595 | ||
311c7c71 SM |
596 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
597 | ||
f62b8bb8 AV |
598 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, |
599 | &sq->wq_ctrl); | |
600 | if (err) | |
601 | goto err_unmap_free_uar; | |
602 | ||
603 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
0ba42241 ML |
604 | if (sq->uar.bf_map) { |
605 | set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state); | |
606 | sq->uar_map = sq->uar.bf_map; | |
607 | } else { | |
608 | sq->uar_map = sq->uar.map; | |
609 | } | |
f62b8bb8 | 610 | sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; |
58d52291 | 611 | sq->max_inline = param->max_inline; |
f62b8bb8 | 612 | |
7ec0bb22 DC |
613 | err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu)); |
614 | if (err) | |
f62b8bb8 AV |
615 | goto err_sq_wq_destroy; |
616 | ||
d3c9bc27 TT |
617 | if (param->icosq) { |
618 | u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
619 | ||
620 | sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) * | |
621 | wq_sz, | |
622 | GFP_KERNEL, | |
623 | cpu_to_node(c->cpu)); | |
624 | if (!sq->ico_wqe_info) { | |
625 | err = -ENOMEM; | |
626 | goto err_free_sq_db; | |
627 | } | |
628 | } else { | |
629 | int txq_ix; | |
630 | ||
631 | txq_ix = c->ix + tc * priv->params.num_channels; | |
632 | sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix); | |
633 | priv->txq_to_sq_map[txq_ix] = sq; | |
634 | } | |
f62b8bb8 | 635 | |
88a85f99 | 636 | sq->pdev = c->pdev; |
ef9814de | 637 | sq->tstamp = &priv->tstamp; |
88a85f99 AS |
638 | sq->mkey_be = c->mkey_be; |
639 | sq->channel = c; | |
640 | sq->tc = tc; | |
641 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS; | |
642 | sq->bf_budget = MLX5E_SQ_BF_BUDGET; | |
f62b8bb8 AV |
643 | |
644 | return 0; | |
645 | ||
d3c9bc27 TT |
646 | err_free_sq_db: |
647 | mlx5e_free_sq_db(sq); | |
648 | ||
f62b8bb8 AV |
649 | err_sq_wq_destroy: |
650 | mlx5_wq_destroy(&sq->wq_ctrl); | |
651 | ||
652 | err_unmap_free_uar: | |
653 | mlx5_unmap_free_uar(mdev, &sq->uar); | |
654 | ||
655 | return err; | |
656 | } | |
657 | ||
658 | static void mlx5e_destroy_sq(struct mlx5e_sq *sq) | |
659 | { | |
660 | struct mlx5e_channel *c = sq->channel; | |
661 | struct mlx5e_priv *priv = c->priv; | |
662 | ||
d3c9bc27 | 663 | kfree(sq->ico_wqe_info); |
f62b8bb8 AV |
664 | mlx5e_free_sq_db(sq); |
665 | mlx5_wq_destroy(&sq->wq_ctrl); | |
666 | mlx5_unmap_free_uar(priv->mdev, &sq->uar); | |
667 | } | |
668 | ||
669 | static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) | |
670 | { | |
671 | struct mlx5e_channel *c = sq->channel; | |
672 | struct mlx5e_priv *priv = c->priv; | |
673 | struct mlx5_core_dev *mdev = priv->mdev; | |
674 | ||
675 | void *in; | |
676 | void *sqc; | |
677 | void *wq; | |
678 | int inlen; | |
679 | int err; | |
680 | ||
681 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
682 | sizeof(u64) * sq->wq_ctrl.buf.npages; | |
683 | in = mlx5_vzalloc(inlen); | |
684 | if (!in) | |
685 | return -ENOMEM; | |
686 | ||
687 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
688 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
689 | ||
690 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
691 | ||
d3c9bc27 TT |
692 | MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]); |
693 | MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); | |
f62b8bb8 | 694 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
d3c9bc27 | 695 | MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1); |
f62b8bb8 AV |
696 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); |
697 | ||
698 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
699 | MLX5_SET(wq, wq, uar_page, sq->uar.index); | |
700 | MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 701 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
702 | MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); |
703 | ||
704 | mlx5_fill_page_array(&sq->wq_ctrl.buf, | |
705 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
706 | ||
7db22ffb | 707 | err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn); |
f62b8bb8 AV |
708 | |
709 | kvfree(in); | |
710 | ||
711 | return err; | |
712 | } | |
713 | ||
507f0c81 YP |
714 | static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, |
715 | int next_state, bool update_rl, int rl_index) | |
f62b8bb8 AV |
716 | { |
717 | struct mlx5e_channel *c = sq->channel; | |
718 | struct mlx5e_priv *priv = c->priv; | |
719 | struct mlx5_core_dev *mdev = priv->mdev; | |
720 | ||
721 | void *in; | |
722 | void *sqc; | |
723 | int inlen; | |
724 | int err; | |
725 | ||
726 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
727 | in = mlx5_vzalloc(inlen); | |
728 | if (!in) | |
729 | return -ENOMEM; | |
730 | ||
731 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
732 | ||
733 | MLX5_SET(modify_sq_in, in, sq_state, curr_state); | |
734 | MLX5_SET(sqc, sqc, state, next_state); | |
507f0c81 YP |
735 | if (update_rl && next_state == MLX5_SQC_STATE_RDY) { |
736 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); | |
737 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); | |
738 | } | |
f62b8bb8 | 739 | |
7db22ffb | 740 | err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen); |
f62b8bb8 AV |
741 | |
742 | kvfree(in); | |
743 | ||
744 | return err; | |
745 | } | |
746 | ||
747 | static void mlx5e_disable_sq(struct mlx5e_sq *sq) | |
748 | { | |
749 | struct mlx5e_channel *c = sq->channel; | |
750 | struct mlx5e_priv *priv = c->priv; | |
751 | struct mlx5_core_dev *mdev = priv->mdev; | |
752 | ||
7db22ffb | 753 | mlx5_core_destroy_sq(mdev, sq->sqn); |
507f0c81 YP |
754 | if (sq->rate_limit) |
755 | mlx5_rl_remove_rate(mdev, sq->rate_limit); | |
f62b8bb8 AV |
756 | } |
757 | ||
758 | static int mlx5e_open_sq(struct mlx5e_channel *c, | |
759 | int tc, | |
760 | struct mlx5e_sq_param *param, | |
761 | struct mlx5e_sq *sq) | |
762 | { | |
763 | int err; | |
764 | ||
765 | err = mlx5e_create_sq(c, tc, param, sq); | |
766 | if (err) | |
767 | return err; | |
768 | ||
769 | err = mlx5e_enable_sq(sq, param); | |
770 | if (err) | |
771 | goto err_destroy_sq; | |
772 | ||
507f0c81 YP |
773 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY, |
774 | false, 0); | |
f62b8bb8 AV |
775 | if (err) |
776 | goto err_disable_sq; | |
777 | ||
d3c9bc27 TT |
778 | if (sq->txq) { |
779 | set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
780 | netdev_tx_reset_queue(sq->txq); | |
781 | netif_tx_start_queue(sq->txq); | |
782 | } | |
f62b8bb8 AV |
783 | |
784 | return 0; | |
785 | ||
786 | err_disable_sq: | |
787 | mlx5e_disable_sq(sq); | |
788 | err_destroy_sq: | |
789 | mlx5e_destroy_sq(sq); | |
790 | ||
791 | return err; | |
792 | } | |
793 | ||
794 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) | |
795 | { | |
796 | __netif_tx_lock_bh(txq); | |
797 | netif_tx_stop_queue(txq); | |
798 | __netif_tx_unlock_bh(txq); | |
799 | } | |
800 | ||
801 | static void mlx5e_close_sq(struct mlx5e_sq *sq) | |
802 | { | |
d3c9bc27 TT |
803 | if (sq->txq) { |
804 | clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
805 | /* prevent netif_tx_wake_queue */ | |
806 | napi_synchronize(&sq->channel->napi); | |
807 | netif_tx_disable_queue(sq->txq); | |
f62b8bb8 | 808 | |
d3c9bc27 TT |
809 | /* ensure hw is notified of all pending wqes */ |
810 | if (mlx5e_sq_has_room_for(sq, 1)) | |
811 | mlx5e_send_nop(sq, true); | |
812 | ||
507f0c81 YP |
813 | mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR, |
814 | false, 0); | |
d3c9bc27 | 815 | } |
f62b8bb8 | 816 | |
f62b8bb8 AV |
817 | while (sq->cc != sq->pc) /* wait till sq is empty */ |
818 | msleep(20); | |
819 | ||
820 | /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */ | |
821 | napi_synchronize(&sq->channel->napi); | |
822 | ||
823 | mlx5e_disable_sq(sq); | |
824 | mlx5e_destroy_sq(sq); | |
825 | } | |
826 | ||
827 | static int mlx5e_create_cq(struct mlx5e_channel *c, | |
828 | struct mlx5e_cq_param *param, | |
829 | struct mlx5e_cq *cq) | |
830 | { | |
831 | struct mlx5e_priv *priv = c->priv; | |
832 | struct mlx5_core_dev *mdev = priv->mdev; | |
833 | struct mlx5_core_cq *mcq = &cq->mcq; | |
834 | int eqn_not_used; | |
0b6e26ce | 835 | unsigned int irqn; |
f62b8bb8 AV |
836 | int err; |
837 | u32 i; | |
838 | ||
311c7c71 SM |
839 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
840 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
f62b8bb8 AV |
841 | param->eq_ix = c->ix; |
842 | ||
843 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
844 | &cq->wq_ctrl); | |
845 | if (err) | |
846 | return err; | |
847 | ||
848 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
849 | ||
850 | cq->napi = &c->napi; | |
851 | ||
852 | mcq->cqe_sz = 64; | |
853 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
854 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
855 | *mcq->set_ci_db = 0; | |
856 | *mcq->arm_db = 0; | |
857 | mcq->vector = param->eq_ix; | |
858 | mcq->comp = mlx5e_completion_event; | |
859 | mcq->event = mlx5e_cq_error_event; | |
860 | mcq->irqn = irqn; | |
b50d292b | 861 | mcq->uar = &mdev->mlx5e_res.cq_uar; |
f62b8bb8 AV |
862 | |
863 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
864 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
865 | ||
866 | cqe->op_own = 0xf1; | |
867 | } | |
868 | ||
869 | cq->channel = c; | |
50cfa25a | 870 | cq->priv = priv; |
f62b8bb8 AV |
871 | |
872 | return 0; | |
873 | } | |
874 | ||
875 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) | |
876 | { | |
877 | mlx5_wq_destroy(&cq->wq_ctrl); | |
878 | } | |
879 | ||
880 | static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) | |
881 | { | |
50cfa25a | 882 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
883 | struct mlx5_core_dev *mdev = priv->mdev; |
884 | struct mlx5_core_cq *mcq = &cq->mcq; | |
885 | ||
886 | void *in; | |
887 | void *cqc; | |
888 | int inlen; | |
0b6e26ce | 889 | unsigned int irqn_not_used; |
f62b8bb8 AV |
890 | int eqn; |
891 | int err; | |
892 | ||
893 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
894 | sizeof(u64) * cq->wq_ctrl.buf.npages; | |
895 | in = mlx5_vzalloc(inlen); | |
896 | if (!in) | |
897 | return -ENOMEM; | |
898 | ||
899 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
900 | ||
901 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
902 | ||
903 | mlx5_fill_page_array(&cq->wq_ctrl.buf, | |
904 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); | |
905 | ||
906 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
907 | ||
9908aa29 | 908 | MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); |
f62b8bb8 AV |
909 | MLX5_SET(cqc, cqc, c_eqn, eqn); |
910 | MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); | |
911 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 912 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
913 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
914 | ||
915 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
916 | ||
917 | kvfree(in); | |
918 | ||
919 | if (err) | |
920 | return err; | |
921 | ||
922 | mlx5e_cq_arm(cq); | |
923 | ||
924 | return 0; | |
925 | } | |
926 | ||
927 | static void mlx5e_disable_cq(struct mlx5e_cq *cq) | |
928 | { | |
50cfa25a | 929 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
930 | struct mlx5_core_dev *mdev = priv->mdev; |
931 | ||
932 | mlx5_core_destroy_cq(mdev, &cq->mcq); | |
933 | } | |
934 | ||
935 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
936 | struct mlx5e_cq_param *param, | |
937 | struct mlx5e_cq *cq, | |
9908aa29 | 938 | struct mlx5e_cq_moder moderation) |
f62b8bb8 AV |
939 | { |
940 | int err; | |
941 | struct mlx5e_priv *priv = c->priv; | |
942 | struct mlx5_core_dev *mdev = priv->mdev; | |
943 | ||
944 | err = mlx5e_create_cq(c, param, cq); | |
945 | if (err) | |
946 | return err; | |
947 | ||
948 | err = mlx5e_enable_cq(cq, param); | |
949 | if (err) | |
950 | goto err_destroy_cq; | |
951 | ||
7524a5d8 GP |
952 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
953 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, | |
9908aa29 TT |
954 | moderation.usec, |
955 | moderation.pkts); | |
f62b8bb8 AV |
956 | return 0; |
957 | ||
958 | err_destroy_cq: | |
959 | mlx5e_destroy_cq(cq); | |
960 | ||
961 | return err; | |
962 | } | |
963 | ||
964 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
965 | { | |
966 | mlx5e_disable_cq(cq); | |
967 | mlx5e_destroy_cq(cq); | |
968 | } | |
969 | ||
970 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) | |
971 | { | |
972 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
973 | } | |
974 | ||
975 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, | |
976 | struct mlx5e_channel_param *cparam) | |
977 | { | |
978 | struct mlx5e_priv *priv = c->priv; | |
979 | int err; | |
980 | int tc; | |
981 | ||
982 | for (tc = 0; tc < c->num_tc; tc++) { | |
983 | err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq, | |
9908aa29 | 984 | priv->params.tx_cq_moderation); |
f62b8bb8 AV |
985 | if (err) |
986 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
987 | } |
988 | ||
989 | return 0; | |
990 | ||
991 | err_close_tx_cqs: | |
992 | for (tc--; tc >= 0; tc--) | |
993 | mlx5e_close_cq(&c->sq[tc].cq); | |
994 | ||
995 | return err; | |
996 | } | |
997 | ||
998 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
999 | { | |
1000 | int tc; | |
1001 | ||
1002 | for (tc = 0; tc < c->num_tc; tc++) | |
1003 | mlx5e_close_cq(&c->sq[tc].cq); | |
1004 | } | |
1005 | ||
1006 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
1007 | struct mlx5e_channel_param *cparam) | |
1008 | { | |
1009 | int err; | |
1010 | int tc; | |
1011 | ||
1012 | for (tc = 0; tc < c->num_tc; tc++) { | |
1013 | err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); | |
1014 | if (err) | |
1015 | goto err_close_sqs; | |
1016 | } | |
1017 | ||
1018 | return 0; | |
1019 | ||
1020 | err_close_sqs: | |
1021 | for (tc--; tc >= 0; tc--) | |
1022 | mlx5e_close_sq(&c->sq[tc]); | |
1023 | ||
1024 | return err; | |
1025 | } | |
1026 | ||
1027 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
1028 | { | |
1029 | int tc; | |
1030 | ||
1031 | for (tc = 0; tc < c->num_tc; tc++) | |
1032 | mlx5e_close_sq(&c->sq[tc]); | |
1033 | } | |
1034 | ||
5283af89 | 1035 | static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix) |
03289b88 SM |
1036 | { |
1037 | int i; | |
1038 | ||
1039 | for (i = 0; i < MLX5E_MAX_NUM_TC; i++) | |
5283af89 RS |
1040 | priv->channeltc_to_txq_map[ix][i] = |
1041 | ix + i * priv->params.num_channels; | |
03289b88 SM |
1042 | } |
1043 | ||
507f0c81 YP |
1044 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
1045 | struct mlx5e_sq *sq, u32 rate) | |
1046 | { | |
1047 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1048 | struct mlx5_core_dev *mdev = priv->mdev; | |
1049 | u16 rl_index = 0; | |
1050 | int err; | |
1051 | ||
1052 | if (rate == sq->rate_limit) | |
1053 | /* nothing to do */ | |
1054 | return 0; | |
1055 | ||
1056 | if (sq->rate_limit) | |
1057 | /* remove current rl index to free space to next ones */ | |
1058 | mlx5_rl_remove_rate(mdev, sq->rate_limit); | |
1059 | ||
1060 | sq->rate_limit = 0; | |
1061 | ||
1062 | if (rate) { | |
1063 | err = mlx5_rl_add_rate(mdev, rate, &rl_index); | |
1064 | if (err) { | |
1065 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1066 | rate, err); | |
1067 | return err; | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, | |
1072 | MLX5_SQC_STATE_RDY, true, rl_index); | |
1073 | if (err) { | |
1074 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1075 | rate, err); | |
1076 | /* remove the rate from the table */ | |
1077 | if (rate) | |
1078 | mlx5_rl_remove_rate(mdev, rate); | |
1079 | return err; | |
1080 | } | |
1081 | ||
1082 | sq->rate_limit = rate; | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) | |
1087 | { | |
1088 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1089 | struct mlx5_core_dev *mdev = priv->mdev; | |
1090 | struct mlx5e_sq *sq = priv->txq_to_sq_map[index]; | |
1091 | int err = 0; | |
1092 | ||
1093 | if (!mlx5_rl_is_supported(mdev)) { | |
1094 | netdev_err(dev, "Rate limiting is not supported on this device\n"); | |
1095 | return -EINVAL; | |
1096 | } | |
1097 | ||
1098 | /* rate is given in Mb/sec, HW config is in Kb/sec */ | |
1099 | rate = rate << 10; | |
1100 | ||
1101 | /* Check whether rate in valid range, 0 is always valid */ | |
1102 | if (rate && !mlx5_rl_is_in_range(mdev, rate)) { | |
1103 | netdev_err(dev, "TX rate %u, is not in range\n", rate); | |
1104 | return -ERANGE; | |
1105 | } | |
1106 | ||
1107 | mutex_lock(&priv->state_lock); | |
1108 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1109 | err = mlx5e_set_sq_maxrate(dev, sq, rate); | |
1110 | if (!err) | |
1111 | priv->tx_rates[index] = rate; | |
1112 | mutex_unlock(&priv->state_lock); | |
1113 | ||
1114 | return err; | |
1115 | } | |
1116 | ||
f62b8bb8 AV |
1117 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
1118 | struct mlx5e_channel_param *cparam, | |
1119 | struct mlx5e_channel **cp) | |
1120 | { | |
9908aa29 | 1121 | struct mlx5e_cq_moder icosq_cq_moder = {0, 0}; |
f62b8bb8 | 1122 | struct net_device *netdev = priv->netdev; |
cb3c7fd4 | 1123 | struct mlx5e_cq_moder rx_cq_profile; |
f62b8bb8 AV |
1124 | int cpu = mlx5e_get_cpu(priv, ix); |
1125 | struct mlx5e_channel *c; | |
507f0c81 | 1126 | struct mlx5e_sq *sq; |
f62b8bb8 | 1127 | int err; |
507f0c81 | 1128 | int i; |
f62b8bb8 AV |
1129 | |
1130 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); | |
1131 | if (!c) | |
1132 | return -ENOMEM; | |
1133 | ||
1134 | c->priv = priv; | |
1135 | c->ix = ix; | |
1136 | c->cpu = cpu; | |
1137 | c->pdev = &priv->mdev->pdev->dev; | |
1138 | c->netdev = priv->netdev; | |
b50d292b | 1139 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); |
a4418a6c | 1140 | c->num_tc = priv->params.num_tc; |
f62b8bb8 | 1141 | |
cb3c7fd4 GR |
1142 | if (priv->params.rx_am_enabled) |
1143 | rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode); | |
1144 | else | |
1145 | rx_cq_profile = priv->params.rx_cq_moderation; | |
1146 | ||
5283af89 | 1147 | mlx5e_build_channeltc_to_txq_map(priv, ix); |
03289b88 | 1148 | |
f62b8bb8 AV |
1149 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
1150 | ||
9908aa29 | 1151 | err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder); |
f62b8bb8 AV |
1152 | if (err) |
1153 | goto err_napi_del; | |
1154 | ||
d3c9bc27 TT |
1155 | err = mlx5e_open_tx_cqs(c, cparam); |
1156 | if (err) | |
1157 | goto err_close_icosq_cq; | |
1158 | ||
f62b8bb8 | 1159 | err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq, |
cb3c7fd4 | 1160 | rx_cq_profile); |
f62b8bb8 AV |
1161 | if (err) |
1162 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1163 | |
1164 | napi_enable(&c->napi); | |
1165 | ||
d3c9bc27 | 1166 | err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq); |
f62b8bb8 AV |
1167 | if (err) |
1168 | goto err_disable_napi; | |
1169 | ||
d3c9bc27 TT |
1170 | err = mlx5e_open_sqs(c, cparam); |
1171 | if (err) | |
1172 | goto err_close_icosq; | |
1173 | ||
507f0c81 YP |
1174 | for (i = 0; i < priv->params.num_tc; i++) { |
1175 | u32 txq_ix = priv->channeltc_to_txq_map[ix][i]; | |
1176 | ||
1177 | if (priv->tx_rates[txq_ix]) { | |
1178 | sq = priv->txq_to_sq_map[txq_ix]; | |
1179 | mlx5e_set_sq_maxrate(priv->netdev, sq, | |
1180 | priv->tx_rates[txq_ix]); | |
1181 | } | |
1182 | } | |
1183 | ||
f62b8bb8 AV |
1184 | err = mlx5e_open_rq(c, &cparam->rq, &c->rq); |
1185 | if (err) | |
1186 | goto err_close_sqs; | |
1187 | ||
1188 | netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix); | |
1189 | *cp = c; | |
1190 | ||
1191 | return 0; | |
1192 | ||
1193 | err_close_sqs: | |
1194 | mlx5e_close_sqs(c); | |
1195 | ||
d3c9bc27 TT |
1196 | err_close_icosq: |
1197 | mlx5e_close_sq(&c->icosq); | |
1198 | ||
f62b8bb8 AV |
1199 | err_disable_napi: |
1200 | napi_disable(&c->napi); | |
1201 | mlx5e_close_cq(&c->rq.cq); | |
1202 | ||
1203 | err_close_tx_cqs: | |
1204 | mlx5e_close_tx_cqs(c); | |
1205 | ||
d3c9bc27 TT |
1206 | err_close_icosq_cq: |
1207 | mlx5e_close_cq(&c->icosq.cq); | |
1208 | ||
f62b8bb8 AV |
1209 | err_napi_del: |
1210 | netif_napi_del(&c->napi); | |
7ae92ae5 | 1211 | napi_hash_del(&c->napi); |
f62b8bb8 AV |
1212 | kfree(c); |
1213 | ||
1214 | return err; | |
1215 | } | |
1216 | ||
1217 | static void mlx5e_close_channel(struct mlx5e_channel *c) | |
1218 | { | |
1219 | mlx5e_close_rq(&c->rq); | |
1220 | mlx5e_close_sqs(c); | |
d3c9bc27 | 1221 | mlx5e_close_sq(&c->icosq); |
f62b8bb8 AV |
1222 | napi_disable(&c->napi); |
1223 | mlx5e_close_cq(&c->rq.cq); | |
1224 | mlx5e_close_tx_cqs(c); | |
d3c9bc27 | 1225 | mlx5e_close_cq(&c->icosq.cq); |
f62b8bb8 | 1226 | netif_napi_del(&c->napi); |
7ae92ae5 ED |
1227 | |
1228 | napi_hash_del(&c->napi); | |
1229 | synchronize_rcu(); | |
1230 | ||
f62b8bb8 AV |
1231 | kfree(c); |
1232 | } | |
1233 | ||
1234 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
1235 | struct mlx5e_rq_param *param) | |
1236 | { | |
1237 | void *rqc = param->rqc; | |
1238 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1239 | ||
461017cb TT |
1240 | switch (priv->params.rq_wq_type) { |
1241 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
1242 | MLX5_SET(wq, wq, log_wqe_num_of_strides, | |
d9d9f156 | 1243 | priv->params.mpwqe_log_num_strides - 9); |
461017cb | 1244 | MLX5_SET(wq, wq, log_wqe_stride_size, |
d9d9f156 | 1245 | priv->params.mpwqe_log_stride_sz - 6); |
461017cb TT |
1246 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); |
1247 | break; | |
1248 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1249 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1250 | } | |
1251 | ||
f62b8bb8 AV |
1252 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); |
1253 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1254 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); | |
b50d292b | 1255 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); |
593cf338 | 1256 | MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); |
f62b8bb8 | 1257 | |
311c7c71 | 1258 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
f62b8bb8 | 1259 | param->wq.linear = 1; |
cb3c7fd4 GR |
1260 | |
1261 | param->am_enabled = priv->params.rx_am_enabled; | |
f62b8bb8 AV |
1262 | } |
1263 | ||
556dd1b9 TT |
1264 | static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param) |
1265 | { | |
1266 | void *rqc = param->rqc; | |
1267 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1268 | ||
1269 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1270 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1271 | } | |
1272 | ||
d3c9bc27 TT |
1273 | static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, |
1274 | struct mlx5e_sq_param *param) | |
f62b8bb8 AV |
1275 | { |
1276 | void *sqc = param->sqc; | |
1277 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1278 | ||
f62b8bb8 | 1279 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); |
b50d292b | 1280 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); |
f62b8bb8 | 1281 | |
311c7c71 | 1282 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
d3c9bc27 TT |
1283 | } |
1284 | ||
1285 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, | |
1286 | struct mlx5e_sq_param *param) | |
1287 | { | |
1288 | void *sqc = param->sqc; | |
1289 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1290 | ||
1291 | mlx5e_build_sq_param_common(priv, param); | |
1292 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); | |
1293 | ||
58d52291 | 1294 | param->max_inline = priv->params.tx_max_inline; |
f62b8bb8 AV |
1295 | } |
1296 | ||
1297 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
1298 | struct mlx5e_cq_param *param) | |
1299 | { | |
1300 | void *cqc = param->cqc; | |
1301 | ||
b50d292b | 1302 | MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index); |
f62b8bb8 AV |
1303 | } |
1304 | ||
1305 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
1306 | struct mlx5e_cq_param *param) | |
1307 | { | |
1308 | void *cqc = param->cqc; | |
461017cb | 1309 | u8 log_cq_size; |
f62b8bb8 | 1310 | |
461017cb TT |
1311 | switch (priv->params.rq_wq_type) { |
1312 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
1313 | log_cq_size = priv->params.log_rq_size + | |
d9d9f156 | 1314 | priv->params.mpwqe_log_num_strides; |
461017cb TT |
1315 | break; |
1316 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1317 | log_cq_size = priv->params.log_rq_size; | |
1318 | } | |
1319 | ||
1320 | MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); | |
7219ab34 TT |
1321 | if (priv->params.rx_cqe_compress) { |
1322 | MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); | |
1323 | MLX5_SET(cqc, cqc, cqe_comp_en, 1); | |
1324 | } | |
f62b8bb8 AV |
1325 | |
1326 | mlx5e_build_common_cq_param(priv, param); | |
9908aa29 TT |
1327 | |
1328 | param->cq_period_mode = priv->params.rx_cq_period_mode; | |
f62b8bb8 AV |
1329 | } |
1330 | ||
1331 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
1332 | struct mlx5e_cq_param *param) | |
1333 | { | |
1334 | void *cqc = param->cqc; | |
1335 | ||
d3c9bc27 | 1336 | MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); |
f62b8bb8 AV |
1337 | |
1338 | mlx5e_build_common_cq_param(priv, param); | |
9908aa29 TT |
1339 | |
1340 | param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
f62b8bb8 AV |
1341 | } |
1342 | ||
d3c9bc27 TT |
1343 | static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, |
1344 | struct mlx5e_cq_param *param, | |
1345 | u8 log_wq_size) | |
1346 | { | |
1347 | void *cqc = param->cqc; | |
1348 | ||
1349 | MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); | |
1350 | ||
1351 | mlx5e_build_common_cq_param(priv, param); | |
9908aa29 TT |
1352 | |
1353 | param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
d3c9bc27 TT |
1354 | } |
1355 | ||
1356 | static void mlx5e_build_icosq_param(struct mlx5e_priv *priv, | |
1357 | struct mlx5e_sq_param *param, | |
1358 | u8 log_wq_size) | |
1359 | { | |
1360 | void *sqc = param->sqc; | |
1361 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1362 | ||
1363 | mlx5e_build_sq_param_common(priv, param); | |
1364 | ||
1365 | MLX5_SET(wq, wq, log_wq_sz, log_wq_size); | |
bc77b240 | 1366 | MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); |
d3c9bc27 TT |
1367 | |
1368 | param->icosq = true; | |
1369 | } | |
1370 | ||
6b87663f | 1371 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam) |
f62b8bb8 | 1372 | { |
bc77b240 | 1373 | u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; |
d3c9bc27 | 1374 | |
f62b8bb8 AV |
1375 | mlx5e_build_rq_param(priv, &cparam->rq); |
1376 | mlx5e_build_sq_param(priv, &cparam->sq); | |
d3c9bc27 | 1377 | mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz); |
f62b8bb8 AV |
1378 | mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); |
1379 | mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); | |
d3c9bc27 | 1380 | mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz); |
f62b8bb8 AV |
1381 | } |
1382 | ||
1383 | static int mlx5e_open_channels(struct mlx5e_priv *priv) | |
1384 | { | |
6b87663f | 1385 | struct mlx5e_channel_param *cparam; |
a4418a6c | 1386 | int nch = priv->params.num_channels; |
03289b88 | 1387 | int err = -ENOMEM; |
f62b8bb8 AV |
1388 | int i; |
1389 | int j; | |
1390 | ||
a4418a6c AS |
1391 | priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *), |
1392 | GFP_KERNEL); | |
03289b88 | 1393 | |
a4418a6c | 1394 | priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc, |
03289b88 SM |
1395 | sizeof(struct mlx5e_sq *), GFP_KERNEL); |
1396 | ||
6b87663f AB |
1397 | cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); |
1398 | ||
1399 | if (!priv->channel || !priv->txq_to_sq_map || !cparam) | |
03289b88 | 1400 | goto err_free_txq_to_sq_map; |
f62b8bb8 | 1401 | |
6b87663f AB |
1402 | mlx5e_build_channel_param(priv, cparam); |
1403 | ||
a4418a6c | 1404 | for (i = 0; i < nch; i++) { |
6b87663f | 1405 | err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]); |
f62b8bb8 AV |
1406 | if (err) |
1407 | goto err_close_channels; | |
1408 | } | |
1409 | ||
a4418a6c | 1410 | for (j = 0; j < nch; j++) { |
f62b8bb8 AV |
1411 | err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); |
1412 | if (err) | |
1413 | goto err_close_channels; | |
1414 | } | |
1415 | ||
6b87663f | 1416 | kfree(cparam); |
f62b8bb8 AV |
1417 | return 0; |
1418 | ||
1419 | err_close_channels: | |
1420 | for (i--; i >= 0; i--) | |
1421 | mlx5e_close_channel(priv->channel[i]); | |
1422 | ||
03289b88 SM |
1423 | err_free_txq_to_sq_map: |
1424 | kfree(priv->txq_to_sq_map); | |
f62b8bb8 | 1425 | kfree(priv->channel); |
6b87663f | 1426 | kfree(cparam); |
f62b8bb8 AV |
1427 | |
1428 | return err; | |
1429 | } | |
1430 | ||
1431 | static void mlx5e_close_channels(struct mlx5e_priv *priv) | |
1432 | { | |
1433 | int i; | |
1434 | ||
1435 | for (i = 0; i < priv->params.num_channels; i++) | |
1436 | mlx5e_close_channel(priv->channel[i]); | |
1437 | ||
03289b88 | 1438 | kfree(priv->txq_to_sq_map); |
f62b8bb8 AV |
1439 | kfree(priv->channel); |
1440 | } | |
1441 | ||
2be6967c SM |
1442 | static int mlx5e_rx_hash_fn(int hfunc) |
1443 | { | |
1444 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
1445 | MLX5_RX_HASH_FN_TOEPLITZ : | |
1446 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
1447 | } | |
1448 | ||
1449 | static int mlx5e_bits_invert(unsigned long a, int size) | |
1450 | { | |
1451 | int inv = 0; | |
1452 | int i; | |
1453 | ||
1454 | for (i = 0; i < size; i++) | |
1455 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
1456 | ||
1457 | return inv; | |
1458 | } | |
1459 | ||
936896e9 AS |
1460 | static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc) |
1461 | { | |
1462 | int i; | |
1463 | ||
1464 | for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) { | |
1465 | int ix = i; | |
1da36696 | 1466 | u32 rqn; |
936896e9 AS |
1467 | |
1468 | if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR) | |
1469 | ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE); | |
1470 | ||
2d75b2bc | 1471 | ix = priv->params.indirection_rqt[ix]; |
1da36696 TT |
1472 | rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ? |
1473 | priv->channel[ix]->rq.rqn : | |
1474 | priv->drop_rq.rqn; | |
1475 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
936896e9 AS |
1476 | } |
1477 | } | |
1478 | ||
1da36696 TT |
1479 | static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc, |
1480 | int ix) | |
4cbeaff5 | 1481 | { |
1da36696 TT |
1482 | u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ? |
1483 | priv->channel[ix]->rq.rqn : | |
1484 | priv->drop_rq.rqn; | |
4cbeaff5 | 1485 | |
1da36696 | 1486 | MLX5_SET(rqtc, rqtc, rq_num[0], rqn); |
4cbeaff5 AS |
1487 | } |
1488 | ||
1da36696 | 1489 | static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn) |
f62b8bb8 AV |
1490 | { |
1491 | struct mlx5_core_dev *mdev = priv->mdev; | |
f62b8bb8 AV |
1492 | void *rqtc; |
1493 | int inlen; | |
1494 | int err; | |
1da36696 | 1495 | u32 *in; |
f62b8bb8 | 1496 | |
f62b8bb8 AV |
1497 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1498 | in = mlx5_vzalloc(inlen); | |
1499 | if (!in) | |
1500 | return -ENOMEM; | |
1501 | ||
1502 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
1503 | ||
1504 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1505 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
1506 | ||
1da36696 TT |
1507 | if (sz > 1) /* RSS */ |
1508 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); | |
1509 | else | |
1510 | mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix); | |
2be6967c | 1511 | |
1da36696 | 1512 | err = mlx5_core_create_rqt(mdev, in, inlen, rqtn); |
f62b8bb8 AV |
1513 | |
1514 | kvfree(in); | |
1da36696 TT |
1515 | return err; |
1516 | } | |
1517 | ||
1518 | static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn) | |
1519 | { | |
1520 | mlx5_core_destroy_rqt(priv->mdev, rqtn); | |
1521 | } | |
1522 | ||
1523 | static int mlx5e_create_rqts(struct mlx5e_priv *priv) | |
1524 | { | |
1525 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
1526 | u32 *rqtn; | |
1527 | int err; | |
1528 | int ix; | |
1529 | ||
1530 | /* Indirect RQT */ | |
1531 | rqtn = &priv->indir_rqtn; | |
1532 | err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn); | |
1533 | if (err) | |
1534 | return err; | |
1535 | ||
1536 | /* Direct RQTs */ | |
1537 | for (ix = 0; ix < nch; ix++) { | |
1538 | rqtn = &priv->direct_tir[ix].rqtn; | |
1539 | err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn); | |
1540 | if (err) | |
1541 | goto err_destroy_rqts; | |
1542 | } | |
1543 | ||
1544 | return 0; | |
1545 | ||
1546 | err_destroy_rqts: | |
1547 | for (ix--; ix >= 0; ix--) | |
1548 | mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn); | |
1549 | ||
1550 | mlx5e_destroy_rqt(priv, priv->indir_rqtn); | |
f62b8bb8 AV |
1551 | |
1552 | return err; | |
1553 | } | |
1554 | ||
1da36696 TT |
1555 | static void mlx5e_destroy_rqts(struct mlx5e_priv *priv) |
1556 | { | |
1557 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
1558 | int i; | |
1559 | ||
1560 | for (i = 0; i < nch; i++) | |
1561 | mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn); | |
1562 | ||
1563 | mlx5e_destroy_rqt(priv, priv->indir_rqtn); | |
1564 | } | |
1565 | ||
1566 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix) | |
5c50368f AS |
1567 | { |
1568 | struct mlx5_core_dev *mdev = priv->mdev; | |
5c50368f AS |
1569 | void *rqtc; |
1570 | int inlen; | |
1da36696 | 1571 | u32 *in; |
5c50368f AS |
1572 | int err; |
1573 | ||
5c50368f AS |
1574 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; |
1575 | in = mlx5_vzalloc(inlen); | |
1576 | if (!in) | |
1577 | return -ENOMEM; | |
1578 | ||
1579 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
1580 | ||
1581 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1da36696 TT |
1582 | if (sz > 1) /* RSS */ |
1583 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); | |
1584 | else | |
1585 | mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix); | |
5c50368f AS |
1586 | |
1587 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); | |
1588 | ||
1da36696 | 1589 | err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); |
5c50368f AS |
1590 | |
1591 | kvfree(in); | |
1592 | ||
1593 | return err; | |
1594 | } | |
1595 | ||
40ab6a6e AS |
1596 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv) |
1597 | { | |
1da36696 TT |
1598 | u32 rqtn; |
1599 | int ix; | |
1600 | ||
1601 | rqtn = priv->indir_rqtn; | |
1602 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0); | |
1603 | for (ix = 0; ix < priv->params.num_channels; ix++) { | |
1604 | rqtn = priv->direct_tir[ix].rqtn; | |
1605 | mlx5e_redirect_rqt(priv, rqtn, 1, ix); | |
1606 | } | |
40ab6a6e AS |
1607 | } |
1608 | ||
5c50368f AS |
1609 | static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv) |
1610 | { | |
1611 | if (!priv->params.lro_en) | |
1612 | return; | |
1613 | ||
1614 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
1615 | ||
1616 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
1617 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
1618 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
1619 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
1620 | (priv->params.lro_wqe_sz - | |
1621 | ROUGH_MAX_L2_L3_HDR_SZ) >> 8); | |
1622 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, | |
1623 | MLX5_CAP_ETH(priv->mdev, | |
d9a40271 | 1624 | lro_timer_supported_periods[2])); |
5c50368f AS |
1625 | } |
1626 | ||
bdfc028d TT |
1627 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv) |
1628 | { | |
1629 | MLX5_SET(tirc, tirc, rx_hash_fn, | |
1630 | mlx5e_rx_hash_fn(priv->params.rss_hfunc)); | |
1631 | if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) { | |
1632 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, | |
1633 | rx_hash_toeplitz_key); | |
1634 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
1635 | rx_hash_toeplitz_key); | |
1636 | ||
1637 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
1638 | memcpy(rss_key, priv->params.toeplitz_hash_key, len); | |
1639 | } | |
1640 | } | |
1641 | ||
ab0394fe | 1642 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) |
5c50368f AS |
1643 | { |
1644 | struct mlx5_core_dev *mdev = priv->mdev; | |
1645 | ||
1646 | void *in; | |
1647 | void *tirc; | |
1648 | int inlen; | |
1649 | int err; | |
ab0394fe | 1650 | int tt; |
1da36696 | 1651 | int ix; |
5c50368f AS |
1652 | |
1653 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1654 | in = mlx5_vzalloc(inlen); | |
1655 | if (!in) | |
1656 | return -ENOMEM; | |
1657 | ||
1658 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
1659 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
1660 | ||
1661 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
1662 | ||
1da36696 | 1663 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
724b2aa1 | 1664 | err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, |
1da36696 | 1665 | inlen); |
ab0394fe | 1666 | if (err) |
1da36696 | 1667 | goto free_in; |
ab0394fe | 1668 | } |
5c50368f | 1669 | |
1da36696 TT |
1670 | for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) { |
1671 | err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, | |
1672 | in, inlen); | |
1673 | if (err) | |
1674 | goto free_in; | |
1675 | } | |
1676 | ||
1677 | free_in: | |
5c50368f AS |
1678 | kvfree(in); |
1679 | ||
1680 | return err; | |
1681 | } | |
1682 | ||
cd255eff | 1683 | static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu) |
40ab6a6e | 1684 | { |
40ab6a6e | 1685 | struct mlx5_core_dev *mdev = priv->mdev; |
cd255eff | 1686 | u16 hw_mtu = MLX5E_SW2HW_MTU(mtu); |
40ab6a6e AS |
1687 | int err; |
1688 | ||
cd255eff | 1689 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
1690 | if (err) |
1691 | return err; | |
1692 | ||
cd255eff SM |
1693 | /* Update vport context MTU */ |
1694 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
1695 | return 0; | |
1696 | } | |
40ab6a6e | 1697 | |
cd255eff SM |
1698 | static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu) |
1699 | { | |
1700 | struct mlx5_core_dev *mdev = priv->mdev; | |
1701 | u16 hw_mtu = 0; | |
1702 | int err; | |
40ab6a6e | 1703 | |
cd255eff SM |
1704 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); |
1705 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
1706 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
1707 | ||
1708 | *mtu = MLX5E_HW2SW_MTU(hw_mtu); | |
1709 | } | |
1710 | ||
1711 | static int mlx5e_set_dev_port_mtu(struct net_device *netdev) | |
1712 | { | |
1713 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1714 | u16 mtu; | |
1715 | int err; | |
1716 | ||
1717 | err = mlx5e_set_mtu(priv, netdev->mtu); | |
1718 | if (err) | |
1719 | return err; | |
40ab6a6e | 1720 | |
cd255eff SM |
1721 | mlx5e_query_mtu(priv, &mtu); |
1722 | if (mtu != netdev->mtu) | |
1723 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", | |
1724 | __func__, mtu, netdev->mtu); | |
40ab6a6e | 1725 | |
cd255eff | 1726 | netdev->mtu = mtu; |
40ab6a6e AS |
1727 | return 0; |
1728 | } | |
1729 | ||
08fb1dac SM |
1730 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
1731 | { | |
1732 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1733 | int nch = priv->params.num_channels; | |
1734 | int ntc = priv->params.num_tc; | |
1735 | int tc; | |
1736 | ||
1737 | netdev_reset_tc(netdev); | |
1738 | ||
1739 | if (ntc == 1) | |
1740 | return; | |
1741 | ||
1742 | netdev_set_num_tc(netdev, ntc); | |
1743 | ||
1744 | for (tc = 0; tc < ntc; tc++) | |
1745 | netdev_set_tc_queue(netdev, tc, nch, tc * nch); | |
1746 | } | |
1747 | ||
40ab6a6e AS |
1748 | int mlx5e_open_locked(struct net_device *netdev) |
1749 | { | |
1750 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1751 | int num_txqs; | |
1752 | int err; | |
1753 | ||
1754 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
1755 | ||
08fb1dac SM |
1756 | mlx5e_netdev_set_tcs(netdev); |
1757 | ||
40ab6a6e AS |
1758 | num_txqs = priv->params.num_channels * priv->params.num_tc; |
1759 | netif_set_real_num_tx_queues(netdev, num_txqs); | |
1760 | netif_set_real_num_rx_queues(netdev, priv->params.num_channels); | |
1761 | ||
1762 | err = mlx5e_set_dev_port_mtu(netdev); | |
1763 | if (err) | |
343b29f3 | 1764 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1765 | |
1766 | err = mlx5e_open_channels(priv); | |
1767 | if (err) { | |
1768 | netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n", | |
1769 | __func__, err); | |
343b29f3 | 1770 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1771 | } |
1772 | ||
724b2aa1 | 1773 | err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev); |
66189961 TT |
1774 | if (err) { |
1775 | netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n", | |
1776 | __func__, err); | |
1777 | goto err_close_channels; | |
1778 | } | |
1779 | ||
40ab6a6e | 1780 | mlx5e_redirect_rqts(priv); |
ce89ef36 | 1781 | mlx5e_update_carrier(priv); |
ef9814de | 1782 | mlx5e_timestamp_init(priv); |
5a7b27eb MG |
1783 | #ifdef CONFIG_RFS_ACCEL |
1784 | priv->netdev->rx_cpu_rmap = priv->mdev->rmap; | |
1785 | #endif | |
40ab6a6e | 1786 | |
7bb29755 | 1787 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); |
40ab6a6e | 1788 | |
9b37b07f | 1789 | return 0; |
343b29f3 | 1790 | |
66189961 TT |
1791 | err_close_channels: |
1792 | mlx5e_close_channels(priv); | |
343b29f3 AS |
1793 | err_clear_state_opened_flag: |
1794 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
1795 | return err; | |
40ab6a6e AS |
1796 | } |
1797 | ||
1798 | static int mlx5e_open(struct net_device *netdev) | |
1799 | { | |
1800 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1801 | int err; | |
1802 | ||
1803 | mutex_lock(&priv->state_lock); | |
1804 | err = mlx5e_open_locked(netdev); | |
1805 | mutex_unlock(&priv->state_lock); | |
1806 | ||
1807 | return err; | |
1808 | } | |
1809 | ||
1810 | int mlx5e_close_locked(struct net_device *netdev) | |
1811 | { | |
1812 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1813 | ||
a1985740 AS |
1814 | /* May already be CLOSED in case a previous configuration operation |
1815 | * (e.g RX/TX queue size change) that involves close&open failed. | |
1816 | */ | |
1817 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1818 | return 0; | |
1819 | ||
40ab6a6e AS |
1820 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
1821 | ||
ef9814de | 1822 | mlx5e_timestamp_cleanup(priv); |
40ab6a6e | 1823 | netif_carrier_off(priv->netdev); |
ce89ef36 | 1824 | mlx5e_redirect_rqts(priv); |
40ab6a6e AS |
1825 | mlx5e_close_channels(priv); |
1826 | ||
1827 | return 0; | |
1828 | } | |
1829 | ||
1830 | static int mlx5e_close(struct net_device *netdev) | |
1831 | { | |
1832 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1833 | int err; | |
1834 | ||
1835 | mutex_lock(&priv->state_lock); | |
1836 | err = mlx5e_close_locked(netdev); | |
1837 | mutex_unlock(&priv->state_lock); | |
1838 | ||
1839 | return err; | |
1840 | } | |
1841 | ||
1842 | static int mlx5e_create_drop_rq(struct mlx5e_priv *priv, | |
1843 | struct mlx5e_rq *rq, | |
1844 | struct mlx5e_rq_param *param) | |
1845 | { | |
1846 | struct mlx5_core_dev *mdev = priv->mdev; | |
1847 | void *rqc = param->rqc; | |
1848 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1849 | int err; | |
1850 | ||
1851 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
1852 | ||
1853 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
1854 | &rq->wq_ctrl); | |
1855 | if (err) | |
1856 | return err; | |
1857 | ||
1858 | rq->priv = priv; | |
1859 | ||
1860 | return 0; | |
1861 | } | |
1862 | ||
1863 | static int mlx5e_create_drop_cq(struct mlx5e_priv *priv, | |
1864 | struct mlx5e_cq *cq, | |
1865 | struct mlx5e_cq_param *param) | |
1866 | { | |
1867 | struct mlx5_core_dev *mdev = priv->mdev; | |
1868 | struct mlx5_core_cq *mcq = &cq->mcq; | |
1869 | int eqn_not_used; | |
0b6e26ce | 1870 | unsigned int irqn; |
40ab6a6e AS |
1871 | int err; |
1872 | ||
1873 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
1874 | &cq->wq_ctrl); | |
1875 | if (err) | |
1876 | return err; | |
1877 | ||
1878 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1879 | ||
1880 | mcq->cqe_sz = 64; | |
1881 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1882 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1883 | *mcq->set_ci_db = 0; | |
1884 | *mcq->arm_db = 0; | |
1885 | mcq->vector = param->eq_ix; | |
1886 | mcq->comp = mlx5e_completion_event; | |
1887 | mcq->event = mlx5e_cq_error_event; | |
1888 | mcq->irqn = irqn; | |
b50d292b | 1889 | mcq->uar = &mdev->mlx5e_res.cq_uar; |
40ab6a6e AS |
1890 | |
1891 | cq->priv = priv; | |
1892 | ||
1893 | return 0; | |
1894 | } | |
1895 | ||
1896 | static int mlx5e_open_drop_rq(struct mlx5e_priv *priv) | |
1897 | { | |
1898 | struct mlx5e_cq_param cq_param; | |
1899 | struct mlx5e_rq_param rq_param; | |
1900 | struct mlx5e_rq *rq = &priv->drop_rq; | |
1901 | struct mlx5e_cq *cq = &priv->drop_rq.cq; | |
1902 | int err; | |
1903 | ||
1904 | memset(&cq_param, 0, sizeof(cq_param)); | |
1905 | memset(&rq_param, 0, sizeof(rq_param)); | |
556dd1b9 | 1906 | mlx5e_build_drop_rq_param(&rq_param); |
40ab6a6e AS |
1907 | |
1908 | err = mlx5e_create_drop_cq(priv, cq, &cq_param); | |
1909 | if (err) | |
1910 | return err; | |
1911 | ||
1912 | err = mlx5e_enable_cq(cq, &cq_param); | |
1913 | if (err) | |
1914 | goto err_destroy_cq; | |
1915 | ||
1916 | err = mlx5e_create_drop_rq(priv, rq, &rq_param); | |
1917 | if (err) | |
1918 | goto err_disable_cq; | |
1919 | ||
1920 | err = mlx5e_enable_rq(rq, &rq_param); | |
1921 | if (err) | |
1922 | goto err_destroy_rq; | |
1923 | ||
1924 | return 0; | |
1925 | ||
1926 | err_destroy_rq: | |
1927 | mlx5e_destroy_rq(&priv->drop_rq); | |
1928 | ||
1929 | err_disable_cq: | |
1930 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1931 | ||
1932 | err_destroy_cq: | |
1933 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1934 | ||
1935 | return err; | |
1936 | } | |
1937 | ||
1938 | static void mlx5e_close_drop_rq(struct mlx5e_priv *priv) | |
1939 | { | |
1940 | mlx5e_disable_rq(&priv->drop_rq); | |
1941 | mlx5e_destroy_rq(&priv->drop_rq); | |
1942 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1943 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1944 | } | |
1945 | ||
1946 | static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc) | |
1947 | { | |
1948 | struct mlx5_core_dev *mdev = priv->mdev; | |
1949 | u32 in[MLX5_ST_SZ_DW(create_tis_in)]; | |
1950 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); | |
1951 | ||
1952 | memset(in, 0, sizeof(in)); | |
1953 | ||
08fb1dac | 1954 | MLX5_SET(tisc, tisc, prio, tc << 1); |
b50d292b | 1955 | MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn); |
40ab6a6e AS |
1956 | |
1957 | return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]); | |
1958 | } | |
1959 | ||
1960 | static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc) | |
1961 | { | |
1962 | mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); | |
1963 | } | |
1964 | ||
1965 | static int mlx5e_create_tises(struct mlx5e_priv *priv) | |
1966 | { | |
1967 | int err; | |
1968 | int tc; | |
1969 | ||
08fb1dac | 1970 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) { |
40ab6a6e AS |
1971 | err = mlx5e_create_tis(priv, tc); |
1972 | if (err) | |
1973 | goto err_close_tises; | |
1974 | } | |
1975 | ||
1976 | return 0; | |
1977 | ||
1978 | err_close_tises: | |
1979 | for (tc--; tc >= 0; tc--) | |
1980 | mlx5e_destroy_tis(priv, tc); | |
1981 | ||
1982 | return err; | |
1983 | } | |
1984 | ||
1985 | static void mlx5e_destroy_tises(struct mlx5e_priv *priv) | |
1986 | { | |
1987 | int tc; | |
1988 | ||
08fb1dac | 1989 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) |
40ab6a6e AS |
1990 | mlx5e_destroy_tis(priv, tc); |
1991 | } | |
1992 | ||
1da36696 TT |
1993 | static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, |
1994 | enum mlx5e_traffic_types tt) | |
f62b8bb8 AV |
1995 | { |
1996 | void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
1997 | ||
b50d292b | 1998 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
3191e05f | 1999 | |
5a6f8aef AS |
2000 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
2001 | MLX5_HASH_FIELD_SEL_DST_IP) | |
f62b8bb8 | 2002 | |
5a6f8aef AS |
2003 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
2004 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2005 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
2006 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
f62b8bb8 | 2007 | |
a741749f AS |
2008 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
2009 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2010 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
2011 | ||
5c50368f | 2012 | mlx5e_build_tir_ctx_lro(tirc, priv); |
f62b8bb8 | 2013 | |
4cbeaff5 | 2014 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
1da36696 TT |
2015 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn); |
2016 | mlx5e_build_tir_ctx_hash(tirc, priv); | |
f62b8bb8 AV |
2017 | |
2018 | switch (tt) { | |
2019 | case MLX5E_TT_IPV4_TCP: | |
2020 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2021 | MLX5_L3_PROT_TYPE_IPV4); | |
2022 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2023 | MLX5_L4_PROT_TYPE_TCP); | |
2024 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 2025 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
2026 | break; |
2027 | ||
2028 | case MLX5E_TT_IPV6_TCP: | |
2029 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2030 | MLX5_L3_PROT_TYPE_IPV6); | |
2031 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2032 | MLX5_L4_PROT_TYPE_TCP); | |
2033 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 2034 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
2035 | break; |
2036 | ||
2037 | case MLX5E_TT_IPV4_UDP: | |
2038 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2039 | MLX5_L3_PROT_TYPE_IPV4); | |
2040 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2041 | MLX5_L4_PROT_TYPE_UDP); | |
2042 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 2043 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
2044 | break; |
2045 | ||
2046 | case MLX5E_TT_IPV6_UDP: | |
2047 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2048 | MLX5_L3_PROT_TYPE_IPV6); | |
2049 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2050 | MLX5_L4_PROT_TYPE_UDP); | |
2051 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 2052 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
2053 | break; |
2054 | ||
a741749f AS |
2055 | case MLX5E_TT_IPV4_IPSEC_AH: |
2056 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2057 | MLX5_L3_PROT_TYPE_IPV4); | |
2058 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2059 | MLX5_HASH_IP_IPSEC_SPI); | |
2060 | break; | |
2061 | ||
2062 | case MLX5E_TT_IPV6_IPSEC_AH: | |
2063 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2064 | MLX5_L3_PROT_TYPE_IPV6); | |
2065 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2066 | MLX5_HASH_IP_IPSEC_SPI); | |
2067 | break; | |
2068 | ||
2069 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
2070 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2071 | MLX5_L3_PROT_TYPE_IPV4); | |
2072 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2073 | MLX5_HASH_IP_IPSEC_SPI); | |
2074 | break; | |
2075 | ||
2076 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
2077 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2078 | MLX5_L3_PROT_TYPE_IPV6); | |
2079 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2080 | MLX5_HASH_IP_IPSEC_SPI); | |
2081 | break; | |
2082 | ||
f62b8bb8 AV |
2083 | case MLX5E_TT_IPV4: |
2084 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2085 | MLX5_L3_PROT_TYPE_IPV4); | |
2086 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2087 | MLX5_HASH_IP); | |
2088 | break; | |
2089 | ||
2090 | case MLX5E_TT_IPV6: | |
2091 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2092 | MLX5_L3_PROT_TYPE_IPV6); | |
2093 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2094 | MLX5_HASH_IP); | |
2095 | break; | |
1da36696 TT |
2096 | default: |
2097 | WARN_ONCE(true, | |
2098 | "mlx5e_build_indir_tir_ctx: bad traffic type!\n"); | |
f62b8bb8 AV |
2099 | } |
2100 | } | |
2101 | ||
1da36696 TT |
2102 | static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, |
2103 | u32 rqtn) | |
f62b8bb8 | 2104 | { |
b50d292b | 2105 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
1da36696 TT |
2106 | |
2107 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
2108 | ||
2109 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2110 | MLX5_SET(tirc, tirc, indirect_table, rqtn); | |
2111 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
2112 | } | |
2113 | ||
2114 | static int mlx5e_create_tirs(struct mlx5e_priv *priv) | |
2115 | { | |
2116 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
724b2aa1 | 2117 | struct mlx5e_tir *tir; |
f62b8bb8 AV |
2118 | void *tirc; |
2119 | int inlen; | |
2120 | int err; | |
1da36696 TT |
2121 | u32 *in; |
2122 | int ix; | |
2123 | int tt; | |
f62b8bb8 AV |
2124 | |
2125 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
2126 | in = mlx5_vzalloc(inlen); | |
2127 | if (!in) | |
2128 | return -ENOMEM; | |
2129 | ||
1da36696 TT |
2130 | /* indirect tirs */ |
2131 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | |
2132 | memset(in, 0, inlen); | |
724b2aa1 | 2133 | tir = &priv->indir_tir[tt]; |
1da36696 TT |
2134 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
2135 | mlx5e_build_indir_tir_ctx(priv, tirc, tt); | |
724b2aa1 | 2136 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
f62b8bb8 | 2137 | if (err) |
40ab6a6e | 2138 | goto err_destroy_tirs; |
f62b8bb8 AV |
2139 | } |
2140 | ||
1da36696 TT |
2141 | /* direct tirs */ |
2142 | for (ix = 0; ix < nch; ix++) { | |
2143 | memset(in, 0, inlen); | |
724b2aa1 | 2144 | tir = &priv->direct_tir[ix]; |
1da36696 TT |
2145 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
2146 | mlx5e_build_direct_tir_ctx(priv, tirc, | |
2147 | priv->direct_tir[ix].rqtn); | |
724b2aa1 | 2148 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
1da36696 TT |
2149 | if (err) |
2150 | goto err_destroy_ch_tirs; | |
2151 | } | |
2152 | ||
2153 | kvfree(in); | |
2154 | ||
f62b8bb8 AV |
2155 | return 0; |
2156 | ||
1da36696 TT |
2157 | err_destroy_ch_tirs: |
2158 | for (ix--; ix >= 0; ix--) | |
724b2aa1 | 2159 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]); |
1da36696 | 2160 | |
40ab6a6e | 2161 | err_destroy_tirs: |
1da36696 | 2162 | for (tt--; tt >= 0; tt--) |
724b2aa1 | 2163 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]); |
1da36696 TT |
2164 | |
2165 | kvfree(in); | |
f62b8bb8 AV |
2166 | |
2167 | return err; | |
2168 | } | |
2169 | ||
40ab6a6e | 2170 | static void mlx5e_destroy_tirs(struct mlx5e_priv *priv) |
f62b8bb8 | 2171 | { |
1da36696 | 2172 | int nch = mlx5e_get_max_num_channels(priv->mdev); |
f62b8bb8 AV |
2173 | int i; |
2174 | ||
1da36696 | 2175 | for (i = 0; i < nch; i++) |
724b2aa1 | 2176 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]); |
1da36696 TT |
2177 | |
2178 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) | |
724b2aa1 | 2179 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]); |
f62b8bb8 AV |
2180 | } |
2181 | ||
36350114 GP |
2182 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd) |
2183 | { | |
2184 | int err = 0; | |
2185 | int i; | |
2186 | ||
2187 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2188 | return 0; | |
2189 | ||
2190 | for (i = 0; i < priv->params.num_channels; i++) { | |
2191 | err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd); | |
2192 | if (err) | |
2193 | return err; | |
2194 | } | |
2195 | ||
2196 | return 0; | |
2197 | } | |
2198 | ||
08fb1dac SM |
2199 | static int mlx5e_setup_tc(struct net_device *netdev, u8 tc) |
2200 | { | |
2201 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2202 | bool was_opened; | |
2203 | int err = 0; | |
2204 | ||
2205 | if (tc && tc != MLX5E_MAX_NUM_TC) | |
2206 | return -EINVAL; | |
2207 | ||
2208 | mutex_lock(&priv->state_lock); | |
2209 | ||
2210 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2211 | if (was_opened) | |
2212 | mlx5e_close_locked(priv->netdev); | |
2213 | ||
2214 | priv->params.num_tc = tc ? tc : 1; | |
2215 | ||
2216 | if (was_opened) | |
2217 | err = mlx5e_open_locked(priv->netdev); | |
2218 | ||
2219 | mutex_unlock(&priv->state_lock); | |
2220 | ||
2221 | return err; | |
2222 | } | |
2223 | ||
2224 | static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle, | |
2225 | __be16 proto, struct tc_to_netdev *tc) | |
2226 | { | |
e8f887ac AV |
2227 | struct mlx5e_priv *priv = netdev_priv(dev); |
2228 | ||
2229 | if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS)) | |
2230 | goto mqprio; | |
2231 | ||
2232 | switch (tc->type) { | |
e3a2b7ed AV |
2233 | case TC_SETUP_CLSFLOWER: |
2234 | switch (tc->cls_flower->command) { | |
2235 | case TC_CLSFLOWER_REPLACE: | |
2236 | return mlx5e_configure_flower(priv, proto, tc->cls_flower); | |
2237 | case TC_CLSFLOWER_DESTROY: | |
2238 | return mlx5e_delete_flower(priv, tc->cls_flower); | |
aad7e08d AV |
2239 | case TC_CLSFLOWER_STATS: |
2240 | return mlx5e_stats_flower(priv, tc->cls_flower); | |
e3a2b7ed | 2241 | } |
e8f887ac AV |
2242 | default: |
2243 | return -EOPNOTSUPP; | |
2244 | } | |
2245 | ||
2246 | mqprio: | |
67ba422e | 2247 | if (tc->type != TC_SETUP_MQPRIO) |
08fb1dac SM |
2248 | return -EINVAL; |
2249 | ||
2250 | return mlx5e_setup_tc(dev, tc->tc); | |
2251 | } | |
2252 | ||
f62b8bb8 AV |
2253 | static struct rtnl_link_stats64 * |
2254 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
2255 | { | |
2256 | struct mlx5e_priv *priv = netdev_priv(dev); | |
9218b44d | 2257 | struct mlx5e_sw_stats *sstats = &priv->stats.sw; |
f62b8bb8 | 2258 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; |
269e6b3a | 2259 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; |
f62b8bb8 | 2260 | |
9218b44d GP |
2261 | stats->rx_packets = sstats->rx_packets; |
2262 | stats->rx_bytes = sstats->rx_bytes; | |
2263 | stats->tx_packets = sstats->tx_packets; | |
2264 | stats->tx_bytes = sstats->tx_bytes; | |
269e6b3a GP |
2265 | |
2266 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
9218b44d | 2267 | stats->tx_dropped = sstats->tx_queue_dropped; |
269e6b3a GP |
2268 | |
2269 | stats->rx_length_errors = | |
9218b44d GP |
2270 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + |
2271 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
2272 | PPORT_802_3_GET(pstats, a_frame_too_long_errors); | |
269e6b3a | 2273 | stats->rx_crc_errors = |
9218b44d GP |
2274 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); |
2275 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
2276 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
269e6b3a | 2277 | stats->tx_carrier_errors = |
9218b44d | 2278 | PPORT_802_3_GET(pstats, a_symbol_error_during_carrier); |
269e6b3a GP |
2279 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
2280 | stats->rx_frame_errors; | |
2281 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
2282 | ||
2283 | /* vport multicast also counts packets that are dropped due to steering | |
2284 | * or rx out of buffer | |
2285 | */ | |
9218b44d GP |
2286 | stats->multicast = |
2287 | VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
f62b8bb8 AV |
2288 | |
2289 | return stats; | |
2290 | } | |
2291 | ||
2292 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
2293 | { | |
2294 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2295 | ||
7bb29755 | 2296 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
2297 | } |
2298 | ||
2299 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
2300 | { | |
2301 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2302 | struct sockaddr *saddr = addr; | |
2303 | ||
2304 | if (!is_valid_ether_addr(saddr->sa_data)) | |
2305 | return -EADDRNOTAVAIL; | |
2306 | ||
2307 | netif_addr_lock_bh(netdev); | |
2308 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
2309 | netif_addr_unlock_bh(netdev); | |
2310 | ||
7bb29755 | 2311 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
2312 | |
2313 | return 0; | |
2314 | } | |
2315 | ||
0e405443 GP |
2316 | #define MLX5E_SET_FEATURE(netdev, feature, enable) \ |
2317 | do { \ | |
2318 | if (enable) \ | |
2319 | netdev->features |= feature; \ | |
2320 | else \ | |
2321 | netdev->features &= ~feature; \ | |
2322 | } while (0) | |
2323 | ||
2324 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
2325 | ||
2326 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
f62b8bb8 AV |
2327 | { |
2328 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
0e405443 GP |
2329 | bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
2330 | int err; | |
f62b8bb8 AV |
2331 | |
2332 | mutex_lock(&priv->state_lock); | |
f62b8bb8 | 2333 | |
0e405443 GP |
2334 | if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)) |
2335 | mlx5e_close_locked(priv->netdev); | |
98e81b0a | 2336 | |
0e405443 GP |
2337 | priv->params.lro_en = enable; |
2338 | err = mlx5e_modify_tirs_lro(priv); | |
2339 | if (err) { | |
2340 | netdev_err(netdev, "lro modify failed, %d\n", err); | |
2341 | priv->params.lro_en = !enable; | |
98e81b0a | 2342 | } |
f62b8bb8 | 2343 | |
0e405443 GP |
2344 | if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)) |
2345 | mlx5e_open_locked(priv->netdev); | |
2346 | ||
9b37b07f AS |
2347 | mutex_unlock(&priv->state_lock); |
2348 | ||
0e405443 GP |
2349 | return err; |
2350 | } | |
2351 | ||
2352 | static int set_feature_vlan_filter(struct net_device *netdev, bool enable) | |
2353 | { | |
2354 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2355 | ||
2356 | if (enable) | |
2357 | mlx5e_enable_vlan_filter(priv); | |
2358 | else | |
2359 | mlx5e_disable_vlan_filter(priv); | |
2360 | ||
2361 | return 0; | |
2362 | } | |
2363 | ||
2364 | static int set_feature_tc_num_filters(struct net_device *netdev, bool enable) | |
2365 | { | |
2366 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
f62b8bb8 | 2367 | |
0e405443 | 2368 | if (!enable && mlx5e_tc_num_filters(priv)) { |
e8f887ac AV |
2369 | netdev_err(netdev, |
2370 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
2371 | return -EINVAL; | |
2372 | } | |
2373 | ||
0e405443 GP |
2374 | return 0; |
2375 | } | |
2376 | ||
94cb1ebb EBE |
2377 | static int set_feature_rx_all(struct net_device *netdev, bool enable) |
2378 | { | |
2379 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2380 | struct mlx5_core_dev *mdev = priv->mdev; | |
2381 | ||
2382 | return mlx5_set_port_fcs(mdev, !enable); | |
2383 | } | |
2384 | ||
36350114 GP |
2385 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) |
2386 | { | |
2387 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2388 | int err; | |
2389 | ||
2390 | mutex_lock(&priv->state_lock); | |
2391 | ||
2392 | priv->params.vlan_strip_disable = !enable; | |
2393 | err = mlx5e_modify_rqs_vsd(priv, !enable); | |
2394 | if (err) | |
2395 | priv->params.vlan_strip_disable = enable; | |
2396 | ||
2397 | mutex_unlock(&priv->state_lock); | |
2398 | ||
2399 | return err; | |
2400 | } | |
2401 | ||
45bf454a MG |
2402 | #ifdef CONFIG_RFS_ACCEL |
2403 | static int set_feature_arfs(struct net_device *netdev, bool enable) | |
2404 | { | |
2405 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2406 | int err; | |
2407 | ||
2408 | if (enable) | |
2409 | err = mlx5e_arfs_enable(priv); | |
2410 | else | |
2411 | err = mlx5e_arfs_disable(priv); | |
2412 | ||
2413 | return err; | |
2414 | } | |
2415 | #endif | |
2416 | ||
0e405443 GP |
2417 | static int mlx5e_handle_feature(struct net_device *netdev, |
2418 | netdev_features_t wanted_features, | |
2419 | netdev_features_t feature, | |
2420 | mlx5e_feature_handler feature_handler) | |
2421 | { | |
2422 | netdev_features_t changes = wanted_features ^ netdev->features; | |
2423 | bool enable = !!(wanted_features & feature); | |
2424 | int err; | |
2425 | ||
2426 | if (!(changes & feature)) | |
2427 | return 0; | |
2428 | ||
2429 | err = feature_handler(netdev, enable); | |
2430 | if (err) { | |
2431 | netdev_err(netdev, "%s feature 0x%llx failed err %d\n", | |
2432 | enable ? "Enable" : "Disable", feature, err); | |
2433 | return err; | |
2434 | } | |
2435 | ||
2436 | MLX5E_SET_FEATURE(netdev, feature, enable); | |
2437 | return 0; | |
2438 | } | |
2439 | ||
2440 | static int mlx5e_set_features(struct net_device *netdev, | |
2441 | netdev_features_t features) | |
2442 | { | |
2443 | int err; | |
2444 | ||
2445 | err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO, | |
2446 | set_feature_lro); | |
2447 | err |= mlx5e_handle_feature(netdev, features, | |
2448 | NETIF_F_HW_VLAN_CTAG_FILTER, | |
2449 | set_feature_vlan_filter); | |
2450 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC, | |
2451 | set_feature_tc_num_filters); | |
94cb1ebb EBE |
2452 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL, |
2453 | set_feature_rx_all); | |
36350114 GP |
2454 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX, |
2455 | set_feature_rx_vlan); | |
45bf454a MG |
2456 | #ifdef CONFIG_RFS_ACCEL |
2457 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE, | |
2458 | set_feature_arfs); | |
2459 | #endif | |
0e405443 GP |
2460 | |
2461 | return err ? -EINVAL : 0; | |
f62b8bb8 AV |
2462 | } |
2463 | ||
d8edd246 SM |
2464 | #define MXL5_HW_MIN_MTU 64 |
2465 | #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN) | |
2466 | ||
f62b8bb8 AV |
2467 | static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu) |
2468 | { | |
2469 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2470 | struct mlx5_core_dev *mdev = priv->mdev; | |
98e81b0a | 2471 | bool was_opened; |
046339ea | 2472 | u16 max_mtu; |
d8edd246 | 2473 | u16 min_mtu; |
98e81b0a | 2474 | int err = 0; |
f62b8bb8 | 2475 | |
facc9699 | 2476 | mlx5_query_port_max_mtu(mdev, &max_mtu, 1); |
f62b8bb8 | 2477 | |
50a9eea6 | 2478 | max_mtu = MLX5E_HW2SW_MTU(max_mtu); |
d8edd246 | 2479 | min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU); |
50a9eea6 | 2480 | |
d8edd246 | 2481 | if (new_mtu > max_mtu || new_mtu < min_mtu) { |
facc9699 | 2482 | netdev_err(netdev, |
d8edd246 SM |
2483 | "%s: Bad MTU (%d), valid range is: [%d..%d]\n", |
2484 | __func__, new_mtu, min_mtu, max_mtu); | |
f62b8bb8 AV |
2485 | return -EINVAL; |
2486 | } | |
2487 | ||
2488 | mutex_lock(&priv->state_lock); | |
98e81b0a AS |
2489 | |
2490 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2491 | if (was_opened) | |
2492 | mlx5e_close_locked(netdev); | |
2493 | ||
f62b8bb8 | 2494 | netdev->mtu = new_mtu; |
98e81b0a AS |
2495 | |
2496 | if (was_opened) | |
2497 | err = mlx5e_open_locked(netdev); | |
2498 | ||
f62b8bb8 AV |
2499 | mutex_unlock(&priv->state_lock); |
2500 | ||
2501 | return err; | |
2502 | } | |
2503 | ||
ef9814de EBE |
2504 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2505 | { | |
2506 | switch (cmd) { | |
2507 | case SIOCSHWTSTAMP: | |
2508 | return mlx5e_hwstamp_set(dev, ifr); | |
2509 | case SIOCGHWTSTAMP: | |
2510 | return mlx5e_hwstamp_get(dev, ifr); | |
2511 | default: | |
2512 | return -EOPNOTSUPP; | |
2513 | } | |
2514 | } | |
2515 | ||
66e49ded SM |
2516 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
2517 | { | |
2518 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2519 | struct mlx5_core_dev *mdev = priv->mdev; | |
2520 | ||
2521 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
2522 | } | |
2523 | ||
2524 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos) | |
2525 | { | |
2526 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2527 | struct mlx5_core_dev *mdev = priv->mdev; | |
2528 | ||
2529 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, | |
2530 | vlan, qos); | |
2531 | } | |
2532 | ||
f942380c MHY |
2533 | static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
2534 | { | |
2535 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2536 | struct mlx5_core_dev *mdev = priv->mdev; | |
2537 | ||
2538 | return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); | |
2539 | } | |
2540 | ||
1edc57e2 MHY |
2541 | static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) |
2542 | { | |
2543 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2544 | struct mlx5_core_dev *mdev = priv->mdev; | |
2545 | ||
2546 | return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); | |
2547 | } | |
66e49ded SM |
2548 | static int mlx5_vport_link2ifla(u8 esw_link) |
2549 | { | |
2550 | switch (esw_link) { | |
2551 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
2552 | return IFLA_VF_LINK_STATE_DISABLE; | |
2553 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
2554 | return IFLA_VF_LINK_STATE_ENABLE; | |
2555 | } | |
2556 | return IFLA_VF_LINK_STATE_AUTO; | |
2557 | } | |
2558 | ||
2559 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
2560 | { | |
2561 | switch (ifla_link) { | |
2562 | case IFLA_VF_LINK_STATE_DISABLE: | |
2563 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
2564 | case IFLA_VF_LINK_STATE_ENABLE: | |
2565 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
2566 | } | |
2567 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
2568 | } | |
2569 | ||
2570 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
2571 | int link_state) | |
2572 | { | |
2573 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2574 | struct mlx5_core_dev *mdev = priv->mdev; | |
2575 | ||
2576 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
2577 | mlx5_ifla_link2vport(link_state)); | |
2578 | } | |
2579 | ||
2580 | static int mlx5e_get_vf_config(struct net_device *dev, | |
2581 | int vf, struct ifla_vf_info *ivi) | |
2582 | { | |
2583 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2584 | struct mlx5_core_dev *mdev = priv->mdev; | |
2585 | int err; | |
2586 | ||
2587 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
2588 | if (err) | |
2589 | return err; | |
2590 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
2591 | return 0; | |
2592 | } | |
2593 | ||
2594 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
2595 | int vf, struct ifla_vf_stats *vf_stats) | |
2596 | { | |
2597 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2598 | struct mlx5_core_dev *mdev = priv->mdev; | |
2599 | ||
2600 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
2601 | vf_stats); | |
2602 | } | |
2603 | ||
b3f63c3d | 2604 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
974c3f30 | 2605 | struct udp_tunnel_info *ti) |
b3f63c3d MF |
2606 | { |
2607 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2608 | ||
974c3f30 AD |
2609 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
2610 | return; | |
2611 | ||
b3f63c3d MF |
2612 | if (!mlx5e_vxlan_allowed(priv->mdev)) |
2613 | return; | |
2614 | ||
974c3f30 | 2615 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1); |
b3f63c3d MF |
2616 | } |
2617 | ||
2618 | static void mlx5e_del_vxlan_port(struct net_device *netdev, | |
974c3f30 | 2619 | struct udp_tunnel_info *ti) |
b3f63c3d MF |
2620 | { |
2621 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2622 | ||
974c3f30 AD |
2623 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
2624 | return; | |
2625 | ||
b3f63c3d MF |
2626 | if (!mlx5e_vxlan_allowed(priv->mdev)) |
2627 | return; | |
2628 | ||
974c3f30 | 2629 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0); |
b3f63c3d MF |
2630 | } |
2631 | ||
2632 | static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv, | |
2633 | struct sk_buff *skb, | |
2634 | netdev_features_t features) | |
2635 | { | |
2636 | struct udphdr *udph; | |
2637 | u16 proto; | |
2638 | u16 port = 0; | |
2639 | ||
2640 | switch (vlan_get_protocol(skb)) { | |
2641 | case htons(ETH_P_IP): | |
2642 | proto = ip_hdr(skb)->protocol; | |
2643 | break; | |
2644 | case htons(ETH_P_IPV6): | |
2645 | proto = ipv6_hdr(skb)->nexthdr; | |
2646 | break; | |
2647 | default: | |
2648 | goto out; | |
2649 | } | |
2650 | ||
2651 | if (proto == IPPROTO_UDP) { | |
2652 | udph = udp_hdr(skb); | |
2653 | port = be16_to_cpu(udph->dest); | |
2654 | } | |
2655 | ||
2656 | /* Verify if UDP port is being offloaded by HW */ | |
2657 | if (port && mlx5e_vxlan_lookup_port(priv, port)) | |
2658 | return features; | |
2659 | ||
2660 | out: | |
2661 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
2662 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
2663 | } | |
2664 | ||
2665 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
2666 | struct net_device *netdev, | |
2667 | netdev_features_t features) | |
2668 | { | |
2669 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2670 | ||
2671 | features = vlan_features_check(skb, features); | |
2672 | features = vxlan_features_check(skb, features); | |
2673 | ||
2674 | /* Validate if the tunneled packet is being offloaded by HW */ | |
2675 | if (skb->encapsulation && | |
2676 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
2677 | return mlx5e_vxlan_features_check(priv, skb, features); | |
2678 | ||
2679 | return features; | |
2680 | } | |
2681 | ||
b0eed40e | 2682 | static const struct net_device_ops mlx5e_netdev_ops_basic = { |
f62b8bb8 AV |
2683 | .ndo_open = mlx5e_open, |
2684 | .ndo_stop = mlx5e_close, | |
2685 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2686 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2687 | .ndo_select_queue = mlx5e_select_queue, | |
f62b8bb8 AV |
2688 | .ndo_get_stats64 = mlx5e_get_stats, |
2689 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2690 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
2691 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
2692 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 2693 | .ndo_set_features = mlx5e_set_features, |
b0eed40e SM |
2694 | .ndo_change_mtu = mlx5e_change_mtu, |
2695 | .ndo_do_ioctl = mlx5e_ioctl, | |
507f0c81 | 2696 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, |
45bf454a MG |
2697 | #ifdef CONFIG_RFS_ACCEL |
2698 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
2699 | #endif | |
b0eed40e SM |
2700 | }; |
2701 | ||
2702 | static const struct net_device_ops mlx5e_netdev_ops_sriov = { | |
2703 | .ndo_open = mlx5e_open, | |
2704 | .ndo_stop = mlx5e_close, | |
2705 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2706 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2707 | .ndo_select_queue = mlx5e_select_queue, | |
b0eed40e SM |
2708 | .ndo_get_stats64 = mlx5e_get_stats, |
2709 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2710 | .ndo_set_mac_address = mlx5e_set_mac, | |
2711 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, | |
2712 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
2713 | .ndo_set_features = mlx5e_set_features, | |
2714 | .ndo_change_mtu = mlx5e_change_mtu, | |
2715 | .ndo_do_ioctl = mlx5e_ioctl, | |
974c3f30 AD |
2716 | .ndo_udp_tunnel_add = mlx5e_add_vxlan_port, |
2717 | .ndo_udp_tunnel_del = mlx5e_del_vxlan_port, | |
507f0c81 | 2718 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, |
b3f63c3d | 2719 | .ndo_features_check = mlx5e_features_check, |
45bf454a MG |
2720 | #ifdef CONFIG_RFS_ACCEL |
2721 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
2722 | #endif | |
b0eed40e SM |
2723 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
2724 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
f942380c | 2725 | .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, |
1edc57e2 | 2726 | .ndo_set_vf_trust = mlx5e_set_vf_trust, |
b0eed40e SM |
2727 | .ndo_get_vf_config = mlx5e_get_vf_config, |
2728 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
2729 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
f62b8bb8 AV |
2730 | }; |
2731 | ||
2732 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
2733 | { | |
2734 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
2735 | return -ENOTSUPP; | |
2736 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || | |
2737 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
2738 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
2739 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
2740 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
2741 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
2742 | MLX5_CAP_FLOWTABLE(mdev, | |
2743 | flow_table_properties_nic_receive.max_ft_level) | |
2744 | < 3) { | |
f62b8bb8 AV |
2745 | mlx5_core_warn(mdev, |
2746 | "Not creating net device, some required device capabilities are missing\n"); | |
2747 | return -ENOTSUPP; | |
2748 | } | |
66189961 TT |
2749 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
2750 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
7524a5d8 GP |
2751 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
2752 | mlx5_core_warn(mdev, "CQ modiration is not supported\n"); | |
66189961 | 2753 | |
f62b8bb8 AV |
2754 | return 0; |
2755 | } | |
2756 | ||
58d52291 AS |
2757 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) |
2758 | { | |
2759 | int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; | |
2760 | ||
2761 | return bf_buf_size - | |
2762 | sizeof(struct mlx5e_tx_wqe) + | |
2763 | 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/; | |
2764 | } | |
2765 | ||
08fb1dac SM |
2766 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2767 | static void mlx5e_ets_init(struct mlx5e_priv *priv) | |
2768 | { | |
2769 | int i; | |
2770 | ||
2771 | priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1; | |
2772 | for (i = 0; i < priv->params.ets.ets_cap; i++) { | |
2773 | priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC; | |
2774 | priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR; | |
2775 | priv->params.ets.prio_tc[i] = i; | |
2776 | } | |
2777 | ||
2778 | /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */ | |
2779 | priv->params.ets.prio_tc[0] = 1; | |
2780 | priv->params.ets.prio_tc[1] = 0; | |
2781 | } | |
2782 | #endif | |
2783 | ||
d8c9660d TT |
2784 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
2785 | u32 *indirection_rqt, int len, | |
85082dba TT |
2786 | int num_channels) |
2787 | { | |
d8c9660d TT |
2788 | int node = mdev->priv.numa_node; |
2789 | int node_num_of_cores; | |
85082dba TT |
2790 | int i; |
2791 | ||
d8c9660d TT |
2792 | if (node == -1) |
2793 | node = first_online_node; | |
2794 | ||
2795 | node_num_of_cores = cpumask_weight(cpumask_of_node(node)); | |
2796 | ||
2797 | if (node_num_of_cores) | |
2798 | num_channels = min_t(int, num_channels, node_num_of_cores); | |
2799 | ||
85082dba TT |
2800 | for (i = 0; i < len; i++) |
2801 | indirection_rqt[i] = i % num_channels; | |
2802 | } | |
2803 | ||
bc77b240 TT |
2804 | static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) |
2805 | { | |
2806 | return MLX5_CAP_GEN(mdev, striding_rq) && | |
2807 | MLX5_CAP_GEN(mdev, umr_ptr_rlky) && | |
2808 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
2809 | } | |
2810 | ||
b797a684 SM |
2811 | static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw) |
2812 | { | |
2813 | enum pcie_link_width width; | |
2814 | enum pci_bus_speed speed; | |
2815 | int err = 0; | |
2816 | ||
2817 | err = pcie_get_minimum_link(mdev->pdev, &speed, &width); | |
2818 | if (err) | |
2819 | return err; | |
2820 | ||
2821 | if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) | |
2822 | return -EINVAL; | |
2823 | ||
2824 | switch (speed) { | |
2825 | case PCIE_SPEED_2_5GT: | |
2826 | *pci_bw = 2500 * width; | |
2827 | break; | |
2828 | case PCIE_SPEED_5_0GT: | |
2829 | *pci_bw = 5000 * width; | |
2830 | break; | |
2831 | case PCIE_SPEED_8_0GT: | |
2832 | *pci_bw = 8000 * width; | |
2833 | break; | |
2834 | default: | |
2835 | return -EINVAL; | |
2836 | } | |
2837 | ||
2838 | return 0; | |
2839 | } | |
2840 | ||
2841 | static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw) | |
2842 | { | |
2843 | return (link_speed && pci_bw && | |
2844 | (pci_bw < 40000) && (pci_bw < link_speed)); | |
2845 | } | |
2846 | ||
9908aa29 TT |
2847 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) |
2848 | { | |
2849 | params->rx_cq_period_mode = cq_period_mode; | |
2850 | ||
2851 | params->rx_cq_moderation.pkts = | |
2852 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
2853 | params->rx_cq_moderation.usec = | |
2854 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
2855 | ||
2856 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) | |
2857 | params->rx_cq_moderation.usec = | |
2858 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; | |
2859 | } | |
2860 | ||
f62b8bb8 AV |
2861 | static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, |
2862 | struct net_device *netdev, | |
936896e9 | 2863 | int num_channels) |
f62b8bb8 AV |
2864 | { |
2865 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
b797a684 SM |
2866 | u32 link_speed = 0; |
2867 | u32 pci_bw = 0; | |
cb3c7fd4 GR |
2868 | u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? |
2869 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : | |
2870 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
f62b8bb8 AV |
2871 | |
2872 | priv->params.log_sq_size = | |
2873 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
bc77b240 | 2874 | priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ? |
461017cb TT |
2875 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : |
2876 | MLX5_WQ_TYPE_LINKED_LIST; | |
2877 | ||
b797a684 SM |
2878 | /* set CQE compression */ |
2879 | priv->params.rx_cqe_compress_admin = false; | |
2880 | if (MLX5_CAP_GEN(mdev, cqe_compression) && | |
2881 | MLX5_CAP_GEN(mdev, vport_group_manager)) { | |
2882 | mlx5e_get_max_linkspeed(mdev, &link_speed); | |
2883 | mlx5e_get_pci_bw(mdev, &pci_bw); | |
2884 | mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n", | |
2885 | link_speed, pci_bw); | |
2886 | priv->params.rx_cqe_compress_admin = | |
2887 | cqe_compress_heuristic(link_speed, pci_bw); | |
2888 | } | |
2889 | ||
2890 | priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin; | |
2891 | ||
461017cb TT |
2892 | switch (priv->params.rq_wq_type) { |
2893 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
2894 | priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW; | |
d9d9f156 TT |
2895 | priv->params.mpwqe_log_stride_sz = |
2896 | priv->params.rx_cqe_compress ? | |
2897 | MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS : | |
2898 | MLX5_MPWRQ_LOG_STRIDE_SIZE; | |
2899 | priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - | |
2900 | priv->params.mpwqe_log_stride_sz; | |
461017cb TT |
2901 | priv->params.lro_en = true; |
2902 | break; | |
2903 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
2904 | priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
2905 | } | |
2906 | ||
d9d9f156 TT |
2907 | mlx5_core_info(mdev, |
2908 | "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", | |
2909 | priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, | |
2910 | BIT(priv->params.log_rq_size), | |
2911 | BIT(priv->params.mpwqe_log_stride_sz), | |
2912 | priv->params.rx_cqe_compress_admin); | |
2913 | ||
461017cb TT |
2914 | priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type, |
2915 | BIT(priv->params.log_rq_size)); | |
9908aa29 | 2916 | |
cb3c7fd4 GR |
2917 | priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
2918 | mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode); | |
9908aa29 TT |
2919 | |
2920 | priv->params.tx_cq_moderation.usec = | |
f62b8bb8 | 2921 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; |
9908aa29 | 2922 | priv->params.tx_cq_moderation.pkts = |
f62b8bb8 | 2923 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; |
58d52291 | 2924 | priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); |
f62b8bb8 | 2925 | priv->params.num_tc = 1; |
2be6967c | 2926 | priv->params.rss_hfunc = ETH_RSS_HASH_XOR; |
f62b8bb8 | 2927 | |
57afead5 AS |
2928 | netdev_rss_key_fill(priv->params.toeplitz_hash_key, |
2929 | sizeof(priv->params.toeplitz_hash_key)); | |
2930 | ||
d8c9660d | 2931 | mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt, |
85082dba | 2932 | MLX5E_INDIR_RQT_SIZE, num_channels); |
2d75b2bc | 2933 | |
f62b8bb8 AV |
2934 | priv->params.lro_wqe_sz = |
2935 | MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; | |
2936 | ||
9908aa29 TT |
2937 | /* Initialize pflags */ |
2938 | MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER, | |
2939 | priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
2940 | ||
f62b8bb8 AV |
2941 | priv->mdev = mdev; |
2942 | priv->netdev = netdev; | |
936896e9 | 2943 | priv->params.num_channels = num_channels; |
f62b8bb8 | 2944 | |
08fb1dac SM |
2945 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2946 | mlx5e_ets_init(priv); | |
2947 | #endif | |
f62b8bb8 | 2948 | |
f62b8bb8 AV |
2949 | mutex_init(&priv->state_lock); |
2950 | ||
2951 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
2952 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
2953 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); | |
2954 | } | |
2955 | ||
2956 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
2957 | { | |
2958 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2959 | ||
e1d7d349 | 2960 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
2961 | if (is_zero_ether_addr(netdev->dev_addr) && |
2962 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
2963 | eth_hw_addr_random(netdev); | |
2964 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
2965 | } | |
f62b8bb8 AV |
2966 | } |
2967 | ||
2968 | static void mlx5e_build_netdev(struct net_device *netdev) | |
2969 | { | |
2970 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2971 | struct mlx5_core_dev *mdev = priv->mdev; | |
94cb1ebb EBE |
2972 | bool fcs_supported; |
2973 | bool fcs_enabled; | |
f62b8bb8 AV |
2974 | |
2975 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
2976 | ||
08fb1dac | 2977 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) { |
b0eed40e | 2978 | netdev->netdev_ops = &mlx5e_netdev_ops_sriov; |
08fb1dac SM |
2979 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2980 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
2981 | #endif | |
2982 | } else { | |
b0eed40e | 2983 | netdev->netdev_ops = &mlx5e_netdev_ops_basic; |
08fb1dac | 2984 | } |
66e49ded | 2985 | |
f62b8bb8 AV |
2986 | netdev->watchdog_timeo = 15 * HZ; |
2987 | ||
2988 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
2989 | ||
12be4b21 | 2990 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
2991 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
2992 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
2993 | netdev->vlan_features |= NETIF_F_GRO; | |
2994 | netdev->vlan_features |= NETIF_F_TSO; | |
2995 | netdev->vlan_features |= NETIF_F_TSO6; | |
2996 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
2997 | netdev->vlan_features |= NETIF_F_RXHASH; | |
2998 | ||
2999 | if (!!MLX5_CAP_ETH(mdev, lro_cap)) | |
3000 | netdev->vlan_features |= NETIF_F_LRO; | |
3001 | ||
3002 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 3003 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
3004 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
3005 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
3006 | ||
b3f63c3d | 3007 | if (mlx5e_vxlan_allowed(mdev)) { |
b49663c8 AD |
3008 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | |
3009 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
3010 | NETIF_F_GSO_PARTIAL; | |
b3f63c3d | 3011 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; |
f3ed653c | 3012 | netdev->hw_enc_features |= NETIF_F_IPV6_CSUM; |
b3f63c3d MF |
3013 | netdev->hw_enc_features |= NETIF_F_TSO; |
3014 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
b3f63c3d | 3015 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; |
b49663c8 AD |
3016 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM | |
3017 | NETIF_F_GSO_PARTIAL; | |
3018 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
b3f63c3d MF |
3019 | } |
3020 | ||
94cb1ebb EBE |
3021 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); |
3022 | ||
3023 | if (fcs_supported) | |
3024 | netdev->hw_features |= NETIF_F_RXALL; | |
3025 | ||
f62b8bb8 AV |
3026 | netdev->features = netdev->hw_features; |
3027 | if (!priv->params.lro_en) | |
3028 | netdev->features &= ~NETIF_F_LRO; | |
3029 | ||
94cb1ebb EBE |
3030 | if (fcs_enabled) |
3031 | netdev->features &= ~NETIF_F_RXALL; | |
3032 | ||
e8f887ac AV |
3033 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
3034 | if (FT_CAP(flow_modify_en) && | |
3035 | FT_CAP(modify_root) && | |
3036 | FT_CAP(identified_miss_table_mode) && | |
1cabe6b0 MG |
3037 | FT_CAP(flow_table_modify)) { |
3038 | netdev->hw_features |= NETIF_F_HW_TC; | |
3039 | #ifdef CONFIG_RFS_ACCEL | |
3040 | netdev->hw_features |= NETIF_F_NTUPLE; | |
3041 | #endif | |
3042 | } | |
e8f887ac | 3043 | |
f62b8bb8 AV |
3044 | netdev->features |= NETIF_F_HIGHDMA; |
3045 | ||
3046 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
3047 | ||
3048 | mlx5e_set_netdev_dev_addr(netdev); | |
3049 | } | |
3050 | ||
593cf338 RS |
3051 | static void mlx5e_create_q_counter(struct mlx5e_priv *priv) |
3052 | { | |
3053 | struct mlx5_core_dev *mdev = priv->mdev; | |
3054 | int err; | |
3055 | ||
3056 | err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter); | |
3057 | if (err) { | |
3058 | mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err); | |
3059 | priv->q_counter = 0; | |
3060 | } | |
3061 | } | |
3062 | ||
3063 | static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv) | |
3064 | { | |
3065 | if (!priv->q_counter) | |
3066 | return; | |
3067 | ||
3068 | mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter); | |
3069 | } | |
3070 | ||
bc77b240 TT |
3071 | static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv) |
3072 | { | |
3073 | struct mlx5_core_dev *mdev = priv->mdev; | |
3074 | struct mlx5_create_mkey_mbox_in *in; | |
3075 | struct mlx5_mkey_seg *mkc; | |
3076 | int inlen = sizeof(*in); | |
3077 | u64 npages = | |
3078 | mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS; | |
3079 | int err; | |
3080 | ||
3081 | in = mlx5_vzalloc(inlen); | |
3082 | if (!in) | |
3083 | return -ENOMEM; | |
3084 | ||
3085 | mkc = &in->seg; | |
3086 | mkc->status = MLX5_MKEY_STATUS_FREE; | |
3087 | mkc->flags = MLX5_PERM_UMR_EN | | |
3088 | MLX5_PERM_LOCAL_READ | | |
3089 | MLX5_PERM_LOCAL_WRITE | | |
3090 | MLX5_ACCESS_MODE_MTT; | |
3091 | ||
3092 | mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
b50d292b | 3093 | mkc->flags_pd = cpu_to_be32(mdev->mlx5e_res.pdn); |
bc77b240 TT |
3094 | mkc->len = cpu_to_be64(npages << PAGE_SHIFT); |
3095 | mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages)); | |
3096 | mkc->log2_page_size = PAGE_SHIFT; | |
3097 | ||
3098 | err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL, | |
3099 | NULL, NULL); | |
3100 | ||
3101 | kvfree(in); | |
3102 | ||
3103 | return err; | |
3104 | } | |
3105 | ||
f62b8bb8 AV |
3106 | static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev) |
3107 | { | |
3108 | struct net_device *netdev; | |
3109 | struct mlx5e_priv *priv; | |
3435ab59 | 3110 | int nch = mlx5e_get_max_num_channels(mdev); |
f62b8bb8 AV |
3111 | int err; |
3112 | ||
08fb1dac SM |
3113 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
3114 | nch * MLX5E_MAX_NUM_TC, | |
3115 | nch); | |
f62b8bb8 AV |
3116 | if (!netdev) { |
3117 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
3118 | return NULL; | |
3119 | } | |
3120 | ||
936896e9 | 3121 | mlx5e_build_netdev_priv(mdev, netdev, nch); |
f62b8bb8 AV |
3122 | mlx5e_build_netdev(netdev); |
3123 | ||
3124 | netif_carrier_off(netdev); | |
3125 | ||
3126 | priv = netdev_priv(netdev); | |
3127 | ||
7bb29755 MF |
3128 | priv->wq = create_singlethread_workqueue("mlx5e"); |
3129 | if (!priv->wq) | |
3130 | goto err_free_netdev; | |
3131 | ||
bc77b240 TT |
3132 | err = mlx5e_create_umr_mkey(priv); |
3133 | if (err) { | |
3134 | mlx5_core_err(mdev, "create umr mkey failed, %d\n", err); | |
b50d292b | 3135 | goto err_destroy_wq; |
bc77b240 TT |
3136 | } |
3137 | ||
40ab6a6e | 3138 | err = mlx5e_create_tises(priv); |
5c50368f | 3139 | if (err) { |
40ab6a6e | 3140 | mlx5_core_warn(mdev, "create tises failed, %d\n", err); |
bc77b240 | 3141 | goto err_destroy_umr_mkey; |
5c50368f AS |
3142 | } |
3143 | ||
3144 | err = mlx5e_open_drop_rq(priv); | |
3145 | if (err) { | |
3146 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
40ab6a6e | 3147 | goto err_destroy_tises; |
5c50368f AS |
3148 | } |
3149 | ||
1da36696 | 3150 | err = mlx5e_create_rqts(priv); |
5c50368f | 3151 | if (err) { |
1da36696 | 3152 | mlx5_core_warn(mdev, "create rqts failed, %d\n", err); |
5c50368f AS |
3153 | goto err_close_drop_rq; |
3154 | } | |
3155 | ||
40ab6a6e | 3156 | err = mlx5e_create_tirs(priv); |
5c50368f | 3157 | if (err) { |
40ab6a6e | 3158 | mlx5_core_warn(mdev, "create tirs failed, %d\n", err); |
1da36696 | 3159 | goto err_destroy_rqts; |
5c50368f AS |
3160 | } |
3161 | ||
acff797c | 3162 | err = mlx5e_create_flow_steering(priv); |
5c50368f | 3163 | if (err) { |
acff797c | 3164 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); |
40ab6a6e | 3165 | goto err_destroy_tirs; |
5c50368f AS |
3166 | } |
3167 | ||
593cf338 RS |
3168 | mlx5e_create_q_counter(priv); |
3169 | ||
33cfaaa8 | 3170 | mlx5e_init_l2_addr(priv); |
5c50368f | 3171 | |
b3f63c3d MF |
3172 | mlx5e_vxlan_init(priv); |
3173 | ||
e8f887ac AV |
3174 | err = mlx5e_tc_init(priv); |
3175 | if (err) | |
593cf338 | 3176 | goto err_dealloc_q_counters; |
e8f887ac | 3177 | |
08fb1dac SM |
3178 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
3179 | mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets); | |
3180 | #endif | |
3181 | ||
f62b8bb8 AV |
3182 | err = register_netdev(netdev); |
3183 | if (err) { | |
1f2a3003 | 3184 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); |
e8f887ac | 3185 | goto err_tc_cleanup; |
f62b8bb8 AV |
3186 | } |
3187 | ||
01a14098 MF |
3188 | if (mlx5e_vxlan_allowed(mdev)) { |
3189 | rtnl_lock(); | |
974c3f30 | 3190 | udp_tunnel_get_rx_info(netdev); |
01a14098 MF |
3191 | rtnl_unlock(); |
3192 | } | |
b3f63c3d | 3193 | |
f62b8bb8 | 3194 | mlx5e_enable_async_events(priv); |
7bb29755 | 3195 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3196 | |
3197 | return priv; | |
3198 | ||
e8f887ac AV |
3199 | err_tc_cleanup: |
3200 | mlx5e_tc_cleanup(priv); | |
3201 | ||
593cf338 RS |
3202 | err_dealloc_q_counters: |
3203 | mlx5e_destroy_q_counter(priv); | |
acff797c | 3204 | mlx5e_destroy_flow_steering(priv); |
5c50368f | 3205 | |
40ab6a6e AS |
3206 | err_destroy_tirs: |
3207 | mlx5e_destroy_tirs(priv); | |
5c50368f | 3208 | |
1da36696 TT |
3209 | err_destroy_rqts: |
3210 | mlx5e_destroy_rqts(priv); | |
5c50368f AS |
3211 | |
3212 | err_close_drop_rq: | |
3213 | mlx5e_close_drop_rq(priv); | |
3214 | ||
40ab6a6e AS |
3215 | err_destroy_tises: |
3216 | mlx5e_destroy_tises(priv); | |
5c50368f | 3217 | |
bc77b240 TT |
3218 | err_destroy_umr_mkey: |
3219 | mlx5_core_destroy_mkey(mdev, &priv->umr_mkey); | |
3220 | ||
7bb29755 MF |
3221 | err_destroy_wq: |
3222 | destroy_workqueue(priv->wq); | |
3223 | ||
f62b8bb8 AV |
3224 | err_free_netdev: |
3225 | free_netdev(netdev); | |
3226 | ||
3227 | return NULL; | |
3228 | } | |
3229 | ||
b50d292b HHZ |
3230 | static void *mlx5e_add(struct mlx5_core_dev *mdev) |
3231 | { | |
3232 | void *ret; | |
3233 | ||
3234 | if (mlx5e_check_required_hca_cap(mdev)) | |
3235 | return NULL; | |
3236 | ||
3237 | if (mlx5e_create_mdev_resources(mdev)) | |
3238 | return NULL; | |
3239 | ||
3240 | ret = mlx5e_create_netdev(mdev); | |
3241 | if (!ret) { | |
3242 | mlx5e_destroy_mdev_resources(mdev); | |
3243 | return NULL; | |
3244 | } | |
3245 | return ret; | |
3246 | } | |
3247 | ||
3248 | static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, | |
3249 | struct mlx5e_priv *priv) | |
f62b8bb8 | 3250 | { |
f62b8bb8 AV |
3251 | struct net_device *netdev = priv->netdev; |
3252 | ||
9b37b07f AS |
3253 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); |
3254 | ||
7bb29755 | 3255 | queue_work(priv->wq, &priv->set_rx_mode_work); |
1cefa326 | 3256 | mlx5e_disable_async_events(priv); |
7bb29755 | 3257 | flush_workqueue(priv->wq); |
5fc7197d MD |
3258 | if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) { |
3259 | netif_device_detach(netdev); | |
811afeaa | 3260 | mlx5e_close(netdev); |
5fc7197d MD |
3261 | } else { |
3262 | unregister_netdev(netdev); | |
3263 | } | |
3264 | ||
e8f887ac | 3265 | mlx5e_tc_cleanup(priv); |
b3f63c3d | 3266 | mlx5e_vxlan_cleanup(priv); |
593cf338 | 3267 | mlx5e_destroy_q_counter(priv); |
acff797c | 3268 | mlx5e_destroy_flow_steering(priv); |
40ab6a6e | 3269 | mlx5e_destroy_tirs(priv); |
1da36696 | 3270 | mlx5e_destroy_rqts(priv); |
5c50368f | 3271 | mlx5e_close_drop_rq(priv); |
40ab6a6e | 3272 | mlx5e_destroy_tises(priv); |
bc77b240 | 3273 | mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey); |
7bb29755 MF |
3274 | cancel_delayed_work_sync(&priv->update_stats_work); |
3275 | destroy_workqueue(priv->wq); | |
5fc7197d MD |
3276 | |
3277 | if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) | |
3278 | free_netdev(netdev); | |
f62b8bb8 AV |
3279 | } |
3280 | ||
b50d292b HHZ |
3281 | static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) |
3282 | { | |
3283 | struct mlx5e_priv *priv = vpriv; | |
3284 | ||
3285 | mlx5e_destroy_netdev(mdev, priv); | |
3286 | mlx5e_destroy_mdev_resources(mdev); | |
3287 | } | |
3288 | ||
f62b8bb8 AV |
3289 | static void *mlx5e_get_netdev(void *vpriv) |
3290 | { | |
3291 | struct mlx5e_priv *priv = vpriv; | |
3292 | ||
3293 | return priv->netdev; | |
3294 | } | |
3295 | ||
3296 | static struct mlx5_interface mlx5e_interface = { | |
b50d292b HHZ |
3297 | .add = mlx5e_add, |
3298 | .remove = mlx5e_remove, | |
f62b8bb8 AV |
3299 | .event = mlx5e_async_event, |
3300 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
3301 | .get_dev = mlx5e_get_netdev, | |
3302 | }; | |
3303 | ||
3304 | void mlx5e_init(void) | |
3305 | { | |
665bc539 | 3306 | mlx5e_build_ptys2ethtool_map(); |
f62b8bb8 AV |
3307 | mlx5_register_interface(&mlx5e_interface); |
3308 | } | |
3309 | ||
3310 | void mlx5e_cleanup(void) | |
3311 | { | |
3312 | mlx5_unregister_interface(&mlx5e_interface); | |
3313 | } |