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f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac AV |
33 | #include <net/tc_act/tc_gact.h> |
34 | #include <net/pkt_cls.h> | |
86d722ad | 35 | #include <linux/mlx5/fs.h> |
b3f63c3d | 36 | #include <net/vxlan.h> |
f62b8bb8 | 37 | #include "en.h" |
e8f887ac | 38 | #include "en_tc.h" |
66e49ded | 39 | #include "eswitch.h" |
b3f63c3d | 40 | #include "vxlan.h" |
f62b8bb8 AV |
41 | |
42 | struct mlx5e_rq_param { | |
43 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; | |
44 | struct mlx5_wq_param wq; | |
45 | }; | |
46 | ||
47 | struct mlx5e_sq_param { | |
48 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
49 | struct mlx5_wq_param wq; | |
58d52291 | 50 | u16 max_inline; |
d3c9bc27 | 51 | bool icosq; |
f62b8bb8 AV |
52 | }; |
53 | ||
54 | struct mlx5e_cq_param { | |
55 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
56 | struct mlx5_wq_param wq; | |
57 | u16 eq_ix; | |
58 | }; | |
59 | ||
60 | struct mlx5e_channel_param { | |
61 | struct mlx5e_rq_param rq; | |
62 | struct mlx5e_sq_param sq; | |
d3c9bc27 | 63 | struct mlx5e_sq_param icosq; |
f62b8bb8 AV |
64 | struct mlx5e_cq_param rx_cq; |
65 | struct mlx5e_cq_param tx_cq; | |
d3c9bc27 | 66 | struct mlx5e_cq_param icosq_cq; |
f62b8bb8 AV |
67 | }; |
68 | ||
69 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) | |
70 | { | |
71 | struct mlx5_core_dev *mdev = priv->mdev; | |
72 | u8 port_state; | |
73 | ||
74 | port_state = mlx5_query_vport_state(mdev, | |
e7546514 | 75 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); |
f62b8bb8 AV |
76 | |
77 | if (port_state == VPORT_STATE_UP) | |
78 | netif_carrier_on(priv->netdev); | |
79 | else | |
80 | netif_carrier_off(priv->netdev); | |
81 | } | |
82 | ||
83 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
84 | { | |
85 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
86 | update_carrier_work); | |
87 | ||
88 | mutex_lock(&priv->state_lock); | |
89 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
90 | mlx5e_update_carrier(priv); | |
91 | mutex_unlock(&priv->state_lock); | |
92 | } | |
93 | ||
9218b44d | 94 | static void mlx5e_update_sw_counters(struct mlx5e_priv *priv) |
f62b8bb8 | 95 | { |
9218b44d | 96 | struct mlx5e_sw_stats *s = &priv->stats.sw; |
f62b8bb8 AV |
97 | struct mlx5e_rq_stats *rq_stats; |
98 | struct mlx5e_sq_stats *sq_stats; | |
9218b44d | 99 | u64 tx_offload_none = 0; |
f62b8bb8 AV |
100 | int i, j; |
101 | ||
9218b44d | 102 | memset(s, 0, sizeof(*s)); |
f62b8bb8 AV |
103 | for (i = 0; i < priv->params.num_channels; i++) { |
104 | rq_stats = &priv->channel[i]->rq.stats; | |
105 | ||
faf4478b GP |
106 | s->rx_packets += rq_stats->packets; |
107 | s->rx_bytes += rq_stats->bytes; | |
f62b8bb8 AV |
108 | s->lro_packets += rq_stats->lro_packets; |
109 | s->lro_bytes += rq_stats->lro_bytes; | |
110 | s->rx_csum_none += rq_stats->csum_none; | |
bbceefce | 111 | s->rx_csum_sw += rq_stats->csum_sw; |
1b223dd3 | 112 | s->rx_csum_inner += rq_stats->csum_inner; |
f62b8bb8 | 113 | s->rx_wqe_err += rq_stats->wqe_err; |
461017cb | 114 | s->rx_mpwqe_filler += rq_stats->mpwqe_filler; |
bc77b240 | 115 | s->rx_mpwqe_frag += rq_stats->mpwqe_frag; |
54984407 | 116 | s->rx_buff_alloc_err += rq_stats->buff_alloc_err; |
f62b8bb8 | 117 | |
a4418a6c | 118 | for (j = 0; j < priv->params.num_tc; j++) { |
f62b8bb8 AV |
119 | sq_stats = &priv->channel[i]->sq[j].stats; |
120 | ||
faf4478b GP |
121 | s->tx_packets += sq_stats->packets; |
122 | s->tx_bytes += sq_stats->bytes; | |
f62b8bb8 AV |
123 | s->tso_packets += sq_stats->tso_packets; |
124 | s->tso_bytes += sq_stats->tso_bytes; | |
89db09eb MF |
125 | s->tso_inner_packets += sq_stats->tso_inner_packets; |
126 | s->tso_inner_bytes += sq_stats->tso_inner_bytes; | |
f62b8bb8 AV |
127 | s->tx_queue_stopped += sq_stats->stopped; |
128 | s->tx_queue_wake += sq_stats->wake; | |
129 | s->tx_queue_dropped += sq_stats->dropped; | |
89db09eb | 130 | s->tx_csum_inner += sq_stats->csum_offload_inner; |
f62b8bb8 AV |
131 | tx_offload_none += sq_stats->csum_offload_none; |
132 | } | |
133 | } | |
134 | ||
9218b44d GP |
135 | /* Update calculated offload counters */ |
136 | s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner; | |
137 | s->rx_csum_good = s->rx_packets - s->rx_csum_none - | |
138 | s->rx_csum_sw; | |
121fcdc8 GP |
139 | |
140 | s->link_down_events = MLX5_GET(ppcnt_reg, | |
141 | priv->stats.pport.phy_counters, | |
142 | counter_set.phys_layer_cntrs.link_down_events); | |
9218b44d GP |
143 | } |
144 | ||
145 | static void mlx5e_update_vport_counters(struct mlx5e_priv *priv) | |
146 | { | |
147 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
148 | u32 *out = (u32 *)priv->stats.vport.query_vport_out; | |
149 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; | |
150 | struct mlx5_core_dev *mdev = priv->mdev; | |
151 | ||
f62b8bb8 AV |
152 | memset(in, 0, sizeof(in)); |
153 | ||
154 | MLX5_SET(query_vport_counter_in, in, opcode, | |
155 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
156 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
157 | MLX5_SET(query_vport_counter_in, in, other_vport, 0); | |
158 | ||
159 | memset(out, 0, outlen); | |
160 | ||
9218b44d GP |
161 | mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); |
162 | } | |
163 | ||
164 | static void mlx5e_update_pport_counters(struct mlx5e_priv *priv) | |
165 | { | |
166 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; | |
167 | struct mlx5_core_dev *mdev = priv->mdev; | |
168 | int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); | |
cf678570 | 169 | int prio; |
9218b44d GP |
170 | void *out; |
171 | u32 *in; | |
172 | ||
173 | in = mlx5_vzalloc(sz); | |
174 | if (!in) | |
f62b8bb8 AV |
175 | goto free_out; |
176 | ||
9218b44d | 177 | MLX5_SET(ppcnt_reg, in, local_port, 1); |
f62b8bb8 | 178 | |
9218b44d GP |
179 | out = pstats->IEEE_802_3_counters; |
180 | MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); | |
181 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
f62b8bb8 | 182 | |
9218b44d GP |
183 | out = pstats->RFC_2863_counters; |
184 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); | |
185 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
186 | ||
187 | out = pstats->RFC_2819_counters; | |
188 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); | |
189 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
593cf338 | 190 | |
121fcdc8 GP |
191 | out = pstats->phy_counters; |
192 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); | |
193 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
194 | ||
cf678570 GP |
195 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); |
196 | for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { | |
197 | out = pstats->per_prio_counters[prio]; | |
198 | MLX5_SET(ppcnt_reg, in, prio_tc, prio); | |
199 | mlx5_core_access_reg(mdev, in, sz, out, sz, | |
200 | MLX5_REG_PPCNT, 0, 0); | |
201 | } | |
202 | ||
f62b8bb8 | 203 | free_out: |
9218b44d GP |
204 | kvfree(in); |
205 | } | |
206 | ||
207 | static void mlx5e_update_q_counter(struct mlx5e_priv *priv) | |
208 | { | |
209 | struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; | |
210 | ||
211 | if (!priv->q_counter) | |
212 | return; | |
213 | ||
214 | mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter, | |
215 | &qcnt->rx_out_of_buffer); | |
216 | } | |
217 | ||
218 | void mlx5e_update_stats(struct mlx5e_priv *priv) | |
219 | { | |
9218b44d GP |
220 | mlx5e_update_q_counter(priv); |
221 | mlx5e_update_vport_counters(priv); | |
222 | mlx5e_update_pport_counters(priv); | |
121fcdc8 | 223 | mlx5e_update_sw_counters(priv); |
f62b8bb8 AV |
224 | } |
225 | ||
226 | static void mlx5e_update_stats_work(struct work_struct *work) | |
227 | { | |
228 | struct delayed_work *dwork = to_delayed_work(work); | |
229 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
230 | update_stats_work); | |
231 | mutex_lock(&priv->state_lock); | |
232 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
233 | mlx5e_update_stats(priv); | |
7bb29755 MF |
234 | queue_delayed_work(priv->wq, dwork, |
235 | msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL)); | |
f62b8bb8 AV |
236 | } |
237 | mutex_unlock(&priv->state_lock); | |
238 | } | |
239 | ||
daa21560 TT |
240 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
241 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 242 | { |
daa21560 TT |
243 | struct mlx5e_priv *priv = vpriv; |
244 | ||
245 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) | |
246 | return; | |
247 | ||
f62b8bb8 AV |
248 | switch (event) { |
249 | case MLX5_DEV_EVENT_PORT_UP: | |
250 | case MLX5_DEV_EVENT_PORT_DOWN: | |
7bb29755 | 251 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 AV |
252 | break; |
253 | ||
254 | default: | |
255 | break; | |
256 | } | |
257 | } | |
258 | ||
f62b8bb8 AV |
259 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
260 | { | |
261 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); | |
262 | } | |
263 | ||
264 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
265 | { | |
f62b8bb8 | 266 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); |
daa21560 | 267 | synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
268 | } |
269 | ||
facc9699 SM |
270 | #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
271 | #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
272 | ||
f62b8bb8 AV |
273 | static int mlx5e_create_rq(struct mlx5e_channel *c, |
274 | struct mlx5e_rq_param *param, | |
275 | struct mlx5e_rq *rq) | |
276 | { | |
277 | struct mlx5e_priv *priv = c->priv; | |
278 | struct mlx5_core_dev *mdev = priv->mdev; | |
279 | void *rqc = param->rqc; | |
280 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
461017cb | 281 | u32 byte_count; |
f62b8bb8 AV |
282 | int wq_sz; |
283 | int err; | |
284 | int i; | |
285 | ||
311c7c71 SM |
286 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
287 | ||
f62b8bb8 AV |
288 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, |
289 | &rq->wq_ctrl); | |
290 | if (err) | |
291 | return err; | |
292 | ||
293 | rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; | |
294 | ||
295 | wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
f62b8bb8 | 296 | |
461017cb TT |
297 | switch (priv->params.rq_wq_type) { |
298 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
299 | rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info), | |
300 | GFP_KERNEL, cpu_to_node(c->cpu)); | |
301 | if (!rq->wqe_info) { | |
302 | err = -ENOMEM; | |
303 | goto err_rq_wq_destroy; | |
304 | } | |
305 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq; | |
306 | rq->alloc_wqe = mlx5e_alloc_rx_mpwqe; | |
307 | ||
308 | rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE; | |
309 | byte_count = rq->wqe_sz; | |
310 | break; | |
311 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
312 | rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL, | |
313 | cpu_to_node(c->cpu)); | |
314 | if (!rq->skb) { | |
315 | err = -ENOMEM; | |
316 | goto err_rq_wq_destroy; | |
317 | } | |
318 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe; | |
319 | rq->alloc_wqe = mlx5e_alloc_rx_wqe; | |
320 | ||
321 | rq->wqe_sz = (priv->params.lro_en) ? | |
322 | priv->params.lro_wqe_sz : | |
323 | MLX5E_SW2HW_MTU(priv->netdev->mtu); | |
c5adb96f TT |
324 | rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz); |
325 | byte_count = rq->wqe_sz; | |
461017cb TT |
326 | byte_count |= MLX5_HW_START_PADDING; |
327 | } | |
f62b8bb8 AV |
328 | |
329 | for (i = 0; i < wq_sz; i++) { | |
330 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); | |
331 | ||
461017cb | 332 | wqe->data.byte_count = cpu_to_be32(byte_count); |
f62b8bb8 AV |
333 | } |
334 | ||
461017cb | 335 | rq->wq_type = priv->params.rq_wq_type; |
f62b8bb8 AV |
336 | rq->pdev = c->pdev; |
337 | rq->netdev = c->netdev; | |
ef9814de | 338 | rq->tstamp = &priv->tstamp; |
f62b8bb8 AV |
339 | rq->channel = c; |
340 | rq->ix = c->ix; | |
50cfa25a | 341 | rq->priv = c->priv; |
bc77b240 TT |
342 | rq->mkey_be = c->mkey_be; |
343 | rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key); | |
f62b8bb8 AV |
344 | |
345 | return 0; | |
346 | ||
347 | err_rq_wq_destroy: | |
348 | mlx5_wq_destroy(&rq->wq_ctrl); | |
349 | ||
350 | return err; | |
351 | } | |
352 | ||
353 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) | |
354 | { | |
461017cb TT |
355 | switch (rq->wq_type) { |
356 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
357 | kfree(rq->wqe_info); | |
358 | break; | |
359 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
360 | kfree(rq->skb); | |
361 | } | |
362 | ||
f62b8bb8 AV |
363 | mlx5_wq_destroy(&rq->wq_ctrl); |
364 | } | |
365 | ||
366 | static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) | |
367 | { | |
50cfa25a | 368 | struct mlx5e_priv *priv = rq->priv; |
f62b8bb8 AV |
369 | struct mlx5_core_dev *mdev = priv->mdev; |
370 | ||
371 | void *in; | |
372 | void *rqc; | |
373 | void *wq; | |
374 | int inlen; | |
375 | int err; | |
376 | ||
377 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
378 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
379 | in = mlx5_vzalloc(inlen); | |
380 | if (!in) | |
381 | return -ENOMEM; | |
382 | ||
383 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
384 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
385 | ||
386 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
387 | ||
97de9f31 | 388 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 AV |
389 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
390 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
36350114 | 391 | MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable); |
f62b8bb8 | 392 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 393 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
394 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
395 | ||
396 | mlx5_fill_page_array(&rq->wq_ctrl.buf, | |
397 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
398 | ||
7db22ffb | 399 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
400 | |
401 | kvfree(in); | |
402 | ||
403 | return err; | |
404 | } | |
405 | ||
36350114 GP |
406 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, |
407 | int next_state) | |
f62b8bb8 AV |
408 | { |
409 | struct mlx5e_channel *c = rq->channel; | |
410 | struct mlx5e_priv *priv = c->priv; | |
411 | struct mlx5_core_dev *mdev = priv->mdev; | |
412 | ||
413 | void *in; | |
414 | void *rqc; | |
415 | int inlen; | |
416 | int err; | |
417 | ||
418 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
419 | in = mlx5_vzalloc(inlen); | |
420 | if (!in) | |
421 | return -ENOMEM; | |
422 | ||
423 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
424 | ||
425 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
426 | MLX5_SET(rqc, rqc, state, next_state); | |
427 | ||
7db22ffb | 428 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
429 | |
430 | kvfree(in); | |
431 | ||
432 | return err; | |
433 | } | |
434 | ||
36350114 GP |
435 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) |
436 | { | |
437 | struct mlx5e_channel *c = rq->channel; | |
438 | struct mlx5e_priv *priv = c->priv; | |
439 | struct mlx5_core_dev *mdev = priv->mdev; | |
440 | ||
441 | void *in; | |
442 | void *rqc; | |
443 | int inlen; | |
444 | int err; | |
445 | ||
446 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
447 | in = mlx5_vzalloc(inlen); | |
448 | if (!in) | |
449 | return -ENOMEM; | |
450 | ||
451 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
452 | ||
453 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
454 | MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD); | |
455 | MLX5_SET(rqc, rqc, vsd, vsd); | |
456 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
457 | ||
458 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
459 | ||
460 | kvfree(in); | |
461 | ||
462 | return err; | |
463 | } | |
464 | ||
f62b8bb8 AV |
465 | static void mlx5e_disable_rq(struct mlx5e_rq *rq) |
466 | { | |
50cfa25a | 467 | mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn); |
f62b8bb8 AV |
468 | } |
469 | ||
470 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) | |
471 | { | |
01c196a2 | 472 | unsigned long exp_time = jiffies + msecs_to_jiffies(20000); |
f62b8bb8 AV |
473 | struct mlx5e_channel *c = rq->channel; |
474 | struct mlx5e_priv *priv = c->priv; | |
475 | struct mlx5_wq_ll *wq = &rq->wq; | |
f62b8bb8 | 476 | |
01c196a2 | 477 | while (time_before(jiffies, exp_time)) { |
f62b8bb8 AV |
478 | if (wq->cur_sz >= priv->params.min_rx_wqes) |
479 | return 0; | |
480 | ||
481 | msleep(20); | |
482 | } | |
483 | ||
484 | return -ETIMEDOUT; | |
485 | } | |
486 | ||
487 | static int mlx5e_open_rq(struct mlx5e_channel *c, | |
488 | struct mlx5e_rq_param *param, | |
489 | struct mlx5e_rq *rq) | |
490 | { | |
d3c9bc27 TT |
491 | struct mlx5e_sq *sq = &c->icosq; |
492 | u16 pi = sq->pc & sq->wq.sz_m1; | |
f62b8bb8 AV |
493 | int err; |
494 | ||
495 | err = mlx5e_create_rq(c, param, rq); | |
496 | if (err) | |
497 | return err; | |
498 | ||
499 | err = mlx5e_enable_rq(rq, param); | |
500 | if (err) | |
501 | goto err_destroy_rq; | |
502 | ||
36350114 | 503 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
f62b8bb8 AV |
504 | if (err) |
505 | goto err_disable_rq; | |
506 | ||
507 | set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); | |
d3c9bc27 TT |
508 | |
509 | sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP; | |
510 | sq->ico_wqe_info[pi].num_wqebbs = 1; | |
511 | mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */ | |
f62b8bb8 AV |
512 | |
513 | return 0; | |
514 | ||
515 | err_disable_rq: | |
516 | mlx5e_disable_rq(rq); | |
517 | err_destroy_rq: | |
518 | mlx5e_destroy_rq(rq); | |
519 | ||
520 | return err; | |
521 | } | |
522 | ||
523 | static void mlx5e_close_rq(struct mlx5e_rq *rq) | |
524 | { | |
525 | clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); | |
526 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ | |
527 | ||
36350114 | 528 | mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); |
f62b8bb8 AV |
529 | while (!mlx5_wq_ll_is_empty(&rq->wq)) |
530 | msleep(20); | |
531 | ||
532 | /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */ | |
533 | napi_synchronize(&rq->channel->napi); | |
534 | ||
535 | mlx5e_disable_rq(rq); | |
536 | mlx5e_destroy_rq(rq); | |
537 | } | |
538 | ||
539 | static void mlx5e_free_sq_db(struct mlx5e_sq *sq) | |
540 | { | |
34802a42 | 541 | kfree(sq->wqe_info); |
f62b8bb8 AV |
542 | kfree(sq->dma_fifo); |
543 | kfree(sq->skb); | |
544 | } | |
545 | ||
546 | static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa) | |
547 | { | |
548 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
549 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
550 | ||
551 | sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa); | |
552 | sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL, | |
553 | numa); | |
34802a42 AS |
554 | sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL, |
555 | numa); | |
f62b8bb8 | 556 | |
34802a42 | 557 | if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) { |
f62b8bb8 AV |
558 | mlx5e_free_sq_db(sq); |
559 | return -ENOMEM; | |
560 | } | |
561 | ||
562 | sq->dma_fifo_mask = df_sz - 1; | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
567 | static int mlx5e_create_sq(struct mlx5e_channel *c, | |
568 | int tc, | |
569 | struct mlx5e_sq_param *param, | |
570 | struct mlx5e_sq *sq) | |
571 | { | |
572 | struct mlx5e_priv *priv = c->priv; | |
573 | struct mlx5_core_dev *mdev = priv->mdev; | |
574 | ||
575 | void *sqc = param->sqc; | |
576 | void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
577 | int err; | |
578 | ||
0ba42241 | 579 | err = mlx5_alloc_map_uar(mdev, &sq->uar, true); |
f62b8bb8 AV |
580 | if (err) |
581 | return err; | |
582 | ||
311c7c71 SM |
583 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
584 | ||
f62b8bb8 AV |
585 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, |
586 | &sq->wq_ctrl); | |
587 | if (err) | |
588 | goto err_unmap_free_uar; | |
589 | ||
590 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
0ba42241 ML |
591 | if (sq->uar.bf_map) { |
592 | set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state); | |
593 | sq->uar_map = sq->uar.bf_map; | |
594 | } else { | |
595 | sq->uar_map = sq->uar.map; | |
596 | } | |
f62b8bb8 | 597 | sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; |
58d52291 | 598 | sq->max_inline = param->max_inline; |
f62b8bb8 | 599 | |
7ec0bb22 DC |
600 | err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu)); |
601 | if (err) | |
f62b8bb8 AV |
602 | goto err_sq_wq_destroy; |
603 | ||
d3c9bc27 TT |
604 | if (param->icosq) { |
605 | u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
606 | ||
607 | sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) * | |
608 | wq_sz, | |
609 | GFP_KERNEL, | |
610 | cpu_to_node(c->cpu)); | |
611 | if (!sq->ico_wqe_info) { | |
612 | err = -ENOMEM; | |
613 | goto err_free_sq_db; | |
614 | } | |
615 | } else { | |
616 | int txq_ix; | |
617 | ||
618 | txq_ix = c->ix + tc * priv->params.num_channels; | |
619 | sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix); | |
620 | priv->txq_to_sq_map[txq_ix] = sq; | |
621 | } | |
f62b8bb8 | 622 | |
88a85f99 | 623 | sq->pdev = c->pdev; |
ef9814de | 624 | sq->tstamp = &priv->tstamp; |
88a85f99 AS |
625 | sq->mkey_be = c->mkey_be; |
626 | sq->channel = c; | |
627 | sq->tc = tc; | |
628 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS; | |
629 | sq->bf_budget = MLX5E_SQ_BF_BUDGET; | |
f62b8bb8 AV |
630 | |
631 | return 0; | |
632 | ||
d3c9bc27 TT |
633 | err_free_sq_db: |
634 | mlx5e_free_sq_db(sq); | |
635 | ||
f62b8bb8 AV |
636 | err_sq_wq_destroy: |
637 | mlx5_wq_destroy(&sq->wq_ctrl); | |
638 | ||
639 | err_unmap_free_uar: | |
640 | mlx5_unmap_free_uar(mdev, &sq->uar); | |
641 | ||
642 | return err; | |
643 | } | |
644 | ||
645 | static void mlx5e_destroy_sq(struct mlx5e_sq *sq) | |
646 | { | |
647 | struct mlx5e_channel *c = sq->channel; | |
648 | struct mlx5e_priv *priv = c->priv; | |
649 | ||
d3c9bc27 | 650 | kfree(sq->ico_wqe_info); |
f62b8bb8 AV |
651 | mlx5e_free_sq_db(sq); |
652 | mlx5_wq_destroy(&sq->wq_ctrl); | |
653 | mlx5_unmap_free_uar(priv->mdev, &sq->uar); | |
654 | } | |
655 | ||
656 | static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) | |
657 | { | |
658 | struct mlx5e_channel *c = sq->channel; | |
659 | struct mlx5e_priv *priv = c->priv; | |
660 | struct mlx5_core_dev *mdev = priv->mdev; | |
661 | ||
662 | void *in; | |
663 | void *sqc; | |
664 | void *wq; | |
665 | int inlen; | |
666 | int err; | |
667 | ||
668 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
669 | sizeof(u64) * sq->wq_ctrl.buf.npages; | |
670 | in = mlx5_vzalloc(inlen); | |
671 | if (!in) | |
672 | return -ENOMEM; | |
673 | ||
674 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
675 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
676 | ||
677 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
678 | ||
d3c9bc27 TT |
679 | MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]); |
680 | MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); | |
f62b8bb8 | 681 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
d3c9bc27 | 682 | MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1); |
f62b8bb8 AV |
683 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); |
684 | ||
685 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
686 | MLX5_SET(wq, wq, uar_page, sq->uar.index); | |
687 | MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 688 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
689 | MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); |
690 | ||
691 | mlx5_fill_page_array(&sq->wq_ctrl.buf, | |
692 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
693 | ||
7db22ffb | 694 | err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn); |
f62b8bb8 AV |
695 | |
696 | kvfree(in); | |
697 | ||
698 | return err; | |
699 | } | |
700 | ||
701 | static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) | |
702 | { | |
703 | struct mlx5e_channel *c = sq->channel; | |
704 | struct mlx5e_priv *priv = c->priv; | |
705 | struct mlx5_core_dev *mdev = priv->mdev; | |
706 | ||
707 | void *in; | |
708 | void *sqc; | |
709 | int inlen; | |
710 | int err; | |
711 | ||
712 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
713 | in = mlx5_vzalloc(inlen); | |
714 | if (!in) | |
715 | return -ENOMEM; | |
716 | ||
717 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
718 | ||
719 | MLX5_SET(modify_sq_in, in, sq_state, curr_state); | |
720 | MLX5_SET(sqc, sqc, state, next_state); | |
721 | ||
7db22ffb | 722 | err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen); |
f62b8bb8 AV |
723 | |
724 | kvfree(in); | |
725 | ||
726 | return err; | |
727 | } | |
728 | ||
729 | static void mlx5e_disable_sq(struct mlx5e_sq *sq) | |
730 | { | |
731 | struct mlx5e_channel *c = sq->channel; | |
732 | struct mlx5e_priv *priv = c->priv; | |
733 | struct mlx5_core_dev *mdev = priv->mdev; | |
734 | ||
7db22ffb | 735 | mlx5_core_destroy_sq(mdev, sq->sqn); |
f62b8bb8 AV |
736 | } |
737 | ||
738 | static int mlx5e_open_sq(struct mlx5e_channel *c, | |
739 | int tc, | |
740 | struct mlx5e_sq_param *param, | |
741 | struct mlx5e_sq *sq) | |
742 | { | |
743 | int err; | |
744 | ||
745 | err = mlx5e_create_sq(c, tc, param, sq); | |
746 | if (err) | |
747 | return err; | |
748 | ||
749 | err = mlx5e_enable_sq(sq, param); | |
750 | if (err) | |
751 | goto err_destroy_sq; | |
752 | ||
753 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); | |
754 | if (err) | |
755 | goto err_disable_sq; | |
756 | ||
d3c9bc27 TT |
757 | if (sq->txq) { |
758 | set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
759 | netdev_tx_reset_queue(sq->txq); | |
760 | netif_tx_start_queue(sq->txq); | |
761 | } | |
f62b8bb8 AV |
762 | |
763 | return 0; | |
764 | ||
765 | err_disable_sq: | |
766 | mlx5e_disable_sq(sq); | |
767 | err_destroy_sq: | |
768 | mlx5e_destroy_sq(sq); | |
769 | ||
770 | return err; | |
771 | } | |
772 | ||
773 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) | |
774 | { | |
775 | __netif_tx_lock_bh(txq); | |
776 | netif_tx_stop_queue(txq); | |
777 | __netif_tx_unlock_bh(txq); | |
778 | } | |
779 | ||
780 | static void mlx5e_close_sq(struct mlx5e_sq *sq) | |
781 | { | |
d3c9bc27 TT |
782 | if (sq->txq) { |
783 | clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
784 | /* prevent netif_tx_wake_queue */ | |
785 | napi_synchronize(&sq->channel->napi); | |
786 | netif_tx_disable_queue(sq->txq); | |
f62b8bb8 | 787 | |
d3c9bc27 TT |
788 | /* ensure hw is notified of all pending wqes */ |
789 | if (mlx5e_sq_has_room_for(sq, 1)) | |
790 | mlx5e_send_nop(sq, true); | |
791 | ||
792 | mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); | |
793 | } | |
f62b8bb8 | 794 | |
f62b8bb8 AV |
795 | while (sq->cc != sq->pc) /* wait till sq is empty */ |
796 | msleep(20); | |
797 | ||
798 | /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */ | |
799 | napi_synchronize(&sq->channel->napi); | |
800 | ||
801 | mlx5e_disable_sq(sq); | |
802 | mlx5e_destroy_sq(sq); | |
803 | } | |
804 | ||
805 | static int mlx5e_create_cq(struct mlx5e_channel *c, | |
806 | struct mlx5e_cq_param *param, | |
807 | struct mlx5e_cq *cq) | |
808 | { | |
809 | struct mlx5e_priv *priv = c->priv; | |
810 | struct mlx5_core_dev *mdev = priv->mdev; | |
811 | struct mlx5_core_cq *mcq = &cq->mcq; | |
812 | int eqn_not_used; | |
0b6e26ce | 813 | unsigned int irqn; |
f62b8bb8 AV |
814 | int err; |
815 | u32 i; | |
816 | ||
311c7c71 SM |
817 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
818 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
f62b8bb8 AV |
819 | param->eq_ix = c->ix; |
820 | ||
821 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
822 | &cq->wq_ctrl); | |
823 | if (err) | |
824 | return err; | |
825 | ||
826 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
827 | ||
828 | cq->napi = &c->napi; | |
829 | ||
830 | mcq->cqe_sz = 64; | |
831 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
832 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
833 | *mcq->set_ci_db = 0; | |
834 | *mcq->arm_db = 0; | |
835 | mcq->vector = param->eq_ix; | |
836 | mcq->comp = mlx5e_completion_event; | |
837 | mcq->event = mlx5e_cq_error_event; | |
838 | mcq->irqn = irqn; | |
839 | mcq->uar = &priv->cq_uar; | |
840 | ||
841 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
842 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
843 | ||
844 | cqe->op_own = 0xf1; | |
845 | } | |
846 | ||
847 | cq->channel = c; | |
50cfa25a | 848 | cq->priv = priv; |
f62b8bb8 AV |
849 | |
850 | return 0; | |
851 | } | |
852 | ||
853 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) | |
854 | { | |
855 | mlx5_wq_destroy(&cq->wq_ctrl); | |
856 | } | |
857 | ||
858 | static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) | |
859 | { | |
50cfa25a | 860 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
861 | struct mlx5_core_dev *mdev = priv->mdev; |
862 | struct mlx5_core_cq *mcq = &cq->mcq; | |
863 | ||
864 | void *in; | |
865 | void *cqc; | |
866 | int inlen; | |
0b6e26ce | 867 | unsigned int irqn_not_used; |
f62b8bb8 AV |
868 | int eqn; |
869 | int err; | |
870 | ||
871 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
872 | sizeof(u64) * cq->wq_ctrl.buf.npages; | |
873 | in = mlx5_vzalloc(inlen); | |
874 | if (!in) | |
875 | return -ENOMEM; | |
876 | ||
877 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
878 | ||
879 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
880 | ||
881 | mlx5_fill_page_array(&cq->wq_ctrl.buf, | |
882 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); | |
883 | ||
884 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
885 | ||
886 | MLX5_SET(cqc, cqc, c_eqn, eqn); | |
887 | MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); | |
888 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 889 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
890 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
891 | ||
892 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
893 | ||
894 | kvfree(in); | |
895 | ||
896 | if (err) | |
897 | return err; | |
898 | ||
899 | mlx5e_cq_arm(cq); | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
904 | static void mlx5e_disable_cq(struct mlx5e_cq *cq) | |
905 | { | |
50cfa25a | 906 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
907 | struct mlx5_core_dev *mdev = priv->mdev; |
908 | ||
909 | mlx5_core_destroy_cq(mdev, &cq->mcq); | |
910 | } | |
911 | ||
912 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
913 | struct mlx5e_cq_param *param, | |
914 | struct mlx5e_cq *cq, | |
915 | u16 moderation_usecs, | |
916 | u16 moderation_frames) | |
917 | { | |
918 | int err; | |
919 | struct mlx5e_priv *priv = c->priv; | |
920 | struct mlx5_core_dev *mdev = priv->mdev; | |
921 | ||
922 | err = mlx5e_create_cq(c, param, cq); | |
923 | if (err) | |
924 | return err; | |
925 | ||
926 | err = mlx5e_enable_cq(cq, param); | |
927 | if (err) | |
928 | goto err_destroy_cq; | |
929 | ||
7524a5d8 GP |
930 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
931 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, | |
932 | moderation_usecs, | |
933 | moderation_frames); | |
f62b8bb8 AV |
934 | return 0; |
935 | ||
936 | err_destroy_cq: | |
937 | mlx5e_destroy_cq(cq); | |
938 | ||
939 | return err; | |
940 | } | |
941 | ||
942 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
943 | { | |
944 | mlx5e_disable_cq(cq); | |
945 | mlx5e_destroy_cq(cq); | |
946 | } | |
947 | ||
948 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) | |
949 | { | |
950 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
951 | } | |
952 | ||
953 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, | |
954 | struct mlx5e_channel_param *cparam) | |
955 | { | |
956 | struct mlx5e_priv *priv = c->priv; | |
957 | int err; | |
958 | int tc; | |
959 | ||
960 | for (tc = 0; tc < c->num_tc; tc++) { | |
961 | err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq, | |
962 | priv->params.tx_cq_moderation_usec, | |
963 | priv->params.tx_cq_moderation_pkts); | |
964 | if (err) | |
965 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
966 | } |
967 | ||
968 | return 0; | |
969 | ||
970 | err_close_tx_cqs: | |
971 | for (tc--; tc >= 0; tc--) | |
972 | mlx5e_close_cq(&c->sq[tc].cq); | |
973 | ||
974 | return err; | |
975 | } | |
976 | ||
977 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
978 | { | |
979 | int tc; | |
980 | ||
981 | for (tc = 0; tc < c->num_tc; tc++) | |
982 | mlx5e_close_cq(&c->sq[tc].cq); | |
983 | } | |
984 | ||
985 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
986 | struct mlx5e_channel_param *cparam) | |
987 | { | |
988 | int err; | |
989 | int tc; | |
990 | ||
991 | for (tc = 0; tc < c->num_tc; tc++) { | |
992 | err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); | |
993 | if (err) | |
994 | goto err_close_sqs; | |
995 | } | |
996 | ||
997 | return 0; | |
998 | ||
999 | err_close_sqs: | |
1000 | for (tc--; tc >= 0; tc--) | |
1001 | mlx5e_close_sq(&c->sq[tc]); | |
1002 | ||
1003 | return err; | |
1004 | } | |
1005 | ||
1006 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
1007 | { | |
1008 | int tc; | |
1009 | ||
1010 | for (tc = 0; tc < c->num_tc; tc++) | |
1011 | mlx5e_close_sq(&c->sq[tc]); | |
1012 | } | |
1013 | ||
5283af89 | 1014 | static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix) |
03289b88 SM |
1015 | { |
1016 | int i; | |
1017 | ||
1018 | for (i = 0; i < MLX5E_MAX_NUM_TC; i++) | |
5283af89 RS |
1019 | priv->channeltc_to_txq_map[ix][i] = |
1020 | ix + i * priv->params.num_channels; | |
03289b88 SM |
1021 | } |
1022 | ||
f62b8bb8 AV |
1023 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
1024 | struct mlx5e_channel_param *cparam, | |
1025 | struct mlx5e_channel **cp) | |
1026 | { | |
1027 | struct net_device *netdev = priv->netdev; | |
1028 | int cpu = mlx5e_get_cpu(priv, ix); | |
1029 | struct mlx5e_channel *c; | |
1030 | int err; | |
1031 | ||
1032 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); | |
1033 | if (!c) | |
1034 | return -ENOMEM; | |
1035 | ||
1036 | c->priv = priv; | |
1037 | c->ix = ix; | |
1038 | c->cpu = cpu; | |
1039 | c->pdev = &priv->mdev->pdev->dev; | |
1040 | c->netdev = priv->netdev; | |
a606b0f6 | 1041 | c->mkey_be = cpu_to_be32(priv->mkey.key); |
a4418a6c | 1042 | c->num_tc = priv->params.num_tc; |
f62b8bb8 | 1043 | |
5283af89 | 1044 | mlx5e_build_channeltc_to_txq_map(priv, ix); |
03289b88 | 1045 | |
f62b8bb8 AV |
1046 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
1047 | ||
d3c9bc27 | 1048 | err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0); |
f62b8bb8 AV |
1049 | if (err) |
1050 | goto err_napi_del; | |
1051 | ||
d3c9bc27 TT |
1052 | err = mlx5e_open_tx_cqs(c, cparam); |
1053 | if (err) | |
1054 | goto err_close_icosq_cq; | |
1055 | ||
f62b8bb8 AV |
1056 | err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq, |
1057 | priv->params.rx_cq_moderation_usec, | |
1058 | priv->params.rx_cq_moderation_pkts); | |
1059 | if (err) | |
1060 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1061 | |
1062 | napi_enable(&c->napi); | |
1063 | ||
d3c9bc27 | 1064 | err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq); |
f62b8bb8 AV |
1065 | if (err) |
1066 | goto err_disable_napi; | |
1067 | ||
d3c9bc27 TT |
1068 | err = mlx5e_open_sqs(c, cparam); |
1069 | if (err) | |
1070 | goto err_close_icosq; | |
1071 | ||
f62b8bb8 AV |
1072 | err = mlx5e_open_rq(c, &cparam->rq, &c->rq); |
1073 | if (err) | |
1074 | goto err_close_sqs; | |
1075 | ||
1076 | netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix); | |
1077 | *cp = c; | |
1078 | ||
1079 | return 0; | |
1080 | ||
1081 | err_close_sqs: | |
1082 | mlx5e_close_sqs(c); | |
1083 | ||
d3c9bc27 TT |
1084 | err_close_icosq: |
1085 | mlx5e_close_sq(&c->icosq); | |
1086 | ||
f62b8bb8 AV |
1087 | err_disable_napi: |
1088 | napi_disable(&c->napi); | |
1089 | mlx5e_close_cq(&c->rq.cq); | |
1090 | ||
1091 | err_close_tx_cqs: | |
1092 | mlx5e_close_tx_cqs(c); | |
1093 | ||
d3c9bc27 TT |
1094 | err_close_icosq_cq: |
1095 | mlx5e_close_cq(&c->icosq.cq); | |
1096 | ||
f62b8bb8 AV |
1097 | err_napi_del: |
1098 | netif_napi_del(&c->napi); | |
7ae92ae5 | 1099 | napi_hash_del(&c->napi); |
f62b8bb8 AV |
1100 | kfree(c); |
1101 | ||
1102 | return err; | |
1103 | } | |
1104 | ||
1105 | static void mlx5e_close_channel(struct mlx5e_channel *c) | |
1106 | { | |
1107 | mlx5e_close_rq(&c->rq); | |
1108 | mlx5e_close_sqs(c); | |
d3c9bc27 | 1109 | mlx5e_close_sq(&c->icosq); |
f62b8bb8 AV |
1110 | napi_disable(&c->napi); |
1111 | mlx5e_close_cq(&c->rq.cq); | |
1112 | mlx5e_close_tx_cqs(c); | |
d3c9bc27 | 1113 | mlx5e_close_cq(&c->icosq.cq); |
f62b8bb8 | 1114 | netif_napi_del(&c->napi); |
7ae92ae5 ED |
1115 | |
1116 | napi_hash_del(&c->napi); | |
1117 | synchronize_rcu(); | |
1118 | ||
f62b8bb8 AV |
1119 | kfree(c); |
1120 | } | |
1121 | ||
1122 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
1123 | struct mlx5e_rq_param *param) | |
1124 | { | |
1125 | void *rqc = param->rqc; | |
1126 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1127 | ||
461017cb TT |
1128 | switch (priv->params.rq_wq_type) { |
1129 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
1130 | MLX5_SET(wq, wq, log_wqe_num_of_strides, | |
1131 | MLX5_MPWRQ_LOG_NUM_STRIDES - 9); | |
1132 | MLX5_SET(wq, wq, log_wqe_stride_size, | |
1133 | MLX5_MPWRQ_LOG_STRIDE_SIZE - 6); | |
1134 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); | |
1135 | break; | |
1136 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1137 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1138 | } | |
1139 | ||
f62b8bb8 AV |
1140 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); |
1141 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1142 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); | |
1143 | MLX5_SET(wq, wq, pd, priv->pdn); | |
593cf338 | 1144 | MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); |
f62b8bb8 | 1145 | |
311c7c71 | 1146 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
f62b8bb8 AV |
1147 | param->wq.linear = 1; |
1148 | } | |
1149 | ||
556dd1b9 TT |
1150 | static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param) |
1151 | { | |
1152 | void *rqc = param->rqc; | |
1153 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1154 | ||
1155 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1156 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1157 | } | |
1158 | ||
d3c9bc27 TT |
1159 | static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, |
1160 | struct mlx5e_sq_param *param) | |
f62b8bb8 AV |
1161 | { |
1162 | void *sqc = param->sqc; | |
1163 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1164 | ||
f62b8bb8 AV |
1165 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); |
1166 | MLX5_SET(wq, wq, pd, priv->pdn); | |
1167 | ||
311c7c71 | 1168 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
d3c9bc27 TT |
1169 | } |
1170 | ||
1171 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, | |
1172 | struct mlx5e_sq_param *param) | |
1173 | { | |
1174 | void *sqc = param->sqc; | |
1175 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1176 | ||
1177 | mlx5e_build_sq_param_common(priv, param); | |
1178 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); | |
1179 | ||
58d52291 | 1180 | param->max_inline = priv->params.tx_max_inline; |
f62b8bb8 AV |
1181 | } |
1182 | ||
1183 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
1184 | struct mlx5e_cq_param *param) | |
1185 | { | |
1186 | void *cqc = param->cqc; | |
1187 | ||
1188 | MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); | |
1189 | } | |
1190 | ||
1191 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
1192 | struct mlx5e_cq_param *param) | |
1193 | { | |
1194 | void *cqc = param->cqc; | |
461017cb | 1195 | u8 log_cq_size; |
f62b8bb8 | 1196 | |
461017cb TT |
1197 | switch (priv->params.rq_wq_type) { |
1198 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
1199 | log_cq_size = priv->params.log_rq_size + | |
1200 | MLX5_MPWRQ_LOG_NUM_STRIDES; | |
1201 | break; | |
1202 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1203 | log_cq_size = priv->params.log_rq_size; | |
1204 | } | |
1205 | ||
1206 | MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); | |
f62b8bb8 AV |
1207 | |
1208 | mlx5e_build_common_cq_param(priv, param); | |
1209 | } | |
1210 | ||
1211 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
1212 | struct mlx5e_cq_param *param) | |
1213 | { | |
1214 | void *cqc = param->cqc; | |
1215 | ||
d3c9bc27 | 1216 | MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); |
f62b8bb8 AV |
1217 | |
1218 | mlx5e_build_common_cq_param(priv, param); | |
1219 | } | |
1220 | ||
d3c9bc27 TT |
1221 | static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, |
1222 | struct mlx5e_cq_param *param, | |
1223 | u8 log_wq_size) | |
1224 | { | |
1225 | void *cqc = param->cqc; | |
1226 | ||
1227 | MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); | |
1228 | ||
1229 | mlx5e_build_common_cq_param(priv, param); | |
1230 | } | |
1231 | ||
1232 | static void mlx5e_build_icosq_param(struct mlx5e_priv *priv, | |
1233 | struct mlx5e_sq_param *param, | |
1234 | u8 log_wq_size) | |
1235 | { | |
1236 | void *sqc = param->sqc; | |
1237 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1238 | ||
1239 | mlx5e_build_sq_param_common(priv, param); | |
1240 | ||
1241 | MLX5_SET(wq, wq, log_wq_sz, log_wq_size); | |
bc77b240 | 1242 | MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); |
d3c9bc27 TT |
1243 | |
1244 | param->icosq = true; | |
1245 | } | |
1246 | ||
6b87663f | 1247 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam) |
f62b8bb8 | 1248 | { |
bc77b240 | 1249 | u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; |
d3c9bc27 | 1250 | |
f62b8bb8 AV |
1251 | mlx5e_build_rq_param(priv, &cparam->rq); |
1252 | mlx5e_build_sq_param(priv, &cparam->sq); | |
d3c9bc27 | 1253 | mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz); |
f62b8bb8 AV |
1254 | mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); |
1255 | mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); | |
d3c9bc27 | 1256 | mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz); |
f62b8bb8 AV |
1257 | } |
1258 | ||
1259 | static int mlx5e_open_channels(struct mlx5e_priv *priv) | |
1260 | { | |
6b87663f | 1261 | struct mlx5e_channel_param *cparam; |
a4418a6c | 1262 | int nch = priv->params.num_channels; |
03289b88 | 1263 | int err = -ENOMEM; |
f62b8bb8 AV |
1264 | int i; |
1265 | int j; | |
1266 | ||
a4418a6c AS |
1267 | priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *), |
1268 | GFP_KERNEL); | |
03289b88 | 1269 | |
a4418a6c | 1270 | priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc, |
03289b88 SM |
1271 | sizeof(struct mlx5e_sq *), GFP_KERNEL); |
1272 | ||
6b87663f AB |
1273 | cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); |
1274 | ||
1275 | if (!priv->channel || !priv->txq_to_sq_map || !cparam) | |
03289b88 | 1276 | goto err_free_txq_to_sq_map; |
f62b8bb8 | 1277 | |
6b87663f AB |
1278 | mlx5e_build_channel_param(priv, cparam); |
1279 | ||
a4418a6c | 1280 | for (i = 0; i < nch; i++) { |
6b87663f | 1281 | err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]); |
f62b8bb8 AV |
1282 | if (err) |
1283 | goto err_close_channels; | |
1284 | } | |
1285 | ||
a4418a6c | 1286 | for (j = 0; j < nch; j++) { |
f62b8bb8 AV |
1287 | err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); |
1288 | if (err) | |
1289 | goto err_close_channels; | |
1290 | } | |
1291 | ||
6b87663f | 1292 | kfree(cparam); |
f62b8bb8 AV |
1293 | return 0; |
1294 | ||
1295 | err_close_channels: | |
1296 | for (i--; i >= 0; i--) | |
1297 | mlx5e_close_channel(priv->channel[i]); | |
1298 | ||
03289b88 SM |
1299 | err_free_txq_to_sq_map: |
1300 | kfree(priv->txq_to_sq_map); | |
f62b8bb8 | 1301 | kfree(priv->channel); |
6b87663f | 1302 | kfree(cparam); |
f62b8bb8 AV |
1303 | |
1304 | return err; | |
1305 | } | |
1306 | ||
1307 | static void mlx5e_close_channels(struct mlx5e_priv *priv) | |
1308 | { | |
1309 | int i; | |
1310 | ||
1311 | for (i = 0; i < priv->params.num_channels; i++) | |
1312 | mlx5e_close_channel(priv->channel[i]); | |
1313 | ||
03289b88 | 1314 | kfree(priv->txq_to_sq_map); |
f62b8bb8 AV |
1315 | kfree(priv->channel); |
1316 | } | |
1317 | ||
2be6967c SM |
1318 | static int mlx5e_rx_hash_fn(int hfunc) |
1319 | { | |
1320 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
1321 | MLX5_RX_HASH_FN_TOEPLITZ : | |
1322 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
1323 | } | |
1324 | ||
1325 | static int mlx5e_bits_invert(unsigned long a, int size) | |
1326 | { | |
1327 | int inv = 0; | |
1328 | int i; | |
1329 | ||
1330 | for (i = 0; i < size; i++) | |
1331 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
1332 | ||
1333 | return inv; | |
1334 | } | |
1335 | ||
936896e9 AS |
1336 | static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc) |
1337 | { | |
1338 | int i; | |
1339 | ||
1340 | for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) { | |
1341 | int ix = i; | |
1da36696 | 1342 | u32 rqn; |
936896e9 AS |
1343 | |
1344 | if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR) | |
1345 | ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE); | |
1346 | ||
2d75b2bc | 1347 | ix = priv->params.indirection_rqt[ix]; |
1da36696 TT |
1348 | rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ? |
1349 | priv->channel[ix]->rq.rqn : | |
1350 | priv->drop_rq.rqn; | |
1351 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
936896e9 AS |
1352 | } |
1353 | } | |
1354 | ||
1da36696 TT |
1355 | static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc, |
1356 | int ix) | |
4cbeaff5 | 1357 | { |
1da36696 TT |
1358 | u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ? |
1359 | priv->channel[ix]->rq.rqn : | |
1360 | priv->drop_rq.rqn; | |
4cbeaff5 | 1361 | |
1da36696 | 1362 | MLX5_SET(rqtc, rqtc, rq_num[0], rqn); |
4cbeaff5 AS |
1363 | } |
1364 | ||
1da36696 | 1365 | static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn) |
f62b8bb8 AV |
1366 | { |
1367 | struct mlx5_core_dev *mdev = priv->mdev; | |
f62b8bb8 AV |
1368 | void *rqtc; |
1369 | int inlen; | |
1370 | int err; | |
1da36696 | 1371 | u32 *in; |
f62b8bb8 | 1372 | |
f62b8bb8 AV |
1373 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1374 | in = mlx5_vzalloc(inlen); | |
1375 | if (!in) | |
1376 | return -ENOMEM; | |
1377 | ||
1378 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
1379 | ||
1380 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1381 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
1382 | ||
1da36696 TT |
1383 | if (sz > 1) /* RSS */ |
1384 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); | |
1385 | else | |
1386 | mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix); | |
2be6967c | 1387 | |
1da36696 | 1388 | err = mlx5_core_create_rqt(mdev, in, inlen, rqtn); |
f62b8bb8 AV |
1389 | |
1390 | kvfree(in); | |
1da36696 TT |
1391 | return err; |
1392 | } | |
1393 | ||
1394 | static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn) | |
1395 | { | |
1396 | mlx5_core_destroy_rqt(priv->mdev, rqtn); | |
1397 | } | |
1398 | ||
1399 | static int mlx5e_create_rqts(struct mlx5e_priv *priv) | |
1400 | { | |
1401 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
1402 | u32 *rqtn; | |
1403 | int err; | |
1404 | int ix; | |
1405 | ||
1406 | /* Indirect RQT */ | |
1407 | rqtn = &priv->indir_rqtn; | |
1408 | err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn); | |
1409 | if (err) | |
1410 | return err; | |
1411 | ||
1412 | /* Direct RQTs */ | |
1413 | for (ix = 0; ix < nch; ix++) { | |
1414 | rqtn = &priv->direct_tir[ix].rqtn; | |
1415 | err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn); | |
1416 | if (err) | |
1417 | goto err_destroy_rqts; | |
1418 | } | |
1419 | ||
1420 | return 0; | |
1421 | ||
1422 | err_destroy_rqts: | |
1423 | for (ix--; ix >= 0; ix--) | |
1424 | mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn); | |
1425 | ||
1426 | mlx5e_destroy_rqt(priv, priv->indir_rqtn); | |
f62b8bb8 AV |
1427 | |
1428 | return err; | |
1429 | } | |
1430 | ||
1da36696 TT |
1431 | static void mlx5e_destroy_rqts(struct mlx5e_priv *priv) |
1432 | { | |
1433 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
1434 | int i; | |
1435 | ||
1436 | for (i = 0; i < nch; i++) | |
1437 | mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn); | |
1438 | ||
1439 | mlx5e_destroy_rqt(priv, priv->indir_rqtn); | |
1440 | } | |
1441 | ||
1442 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix) | |
5c50368f AS |
1443 | { |
1444 | struct mlx5_core_dev *mdev = priv->mdev; | |
5c50368f AS |
1445 | void *rqtc; |
1446 | int inlen; | |
1da36696 | 1447 | u32 *in; |
5c50368f AS |
1448 | int err; |
1449 | ||
5c50368f AS |
1450 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; |
1451 | in = mlx5_vzalloc(inlen); | |
1452 | if (!in) | |
1453 | return -ENOMEM; | |
1454 | ||
1455 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
1456 | ||
1457 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1da36696 TT |
1458 | if (sz > 1) /* RSS */ |
1459 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); | |
1460 | else | |
1461 | mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix); | |
5c50368f AS |
1462 | |
1463 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); | |
1464 | ||
1da36696 | 1465 | err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); |
5c50368f AS |
1466 | |
1467 | kvfree(in); | |
1468 | ||
1469 | return err; | |
1470 | } | |
1471 | ||
40ab6a6e AS |
1472 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv) |
1473 | { | |
1da36696 TT |
1474 | u32 rqtn; |
1475 | int ix; | |
1476 | ||
1477 | rqtn = priv->indir_rqtn; | |
1478 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0); | |
1479 | for (ix = 0; ix < priv->params.num_channels; ix++) { | |
1480 | rqtn = priv->direct_tir[ix].rqtn; | |
1481 | mlx5e_redirect_rqt(priv, rqtn, 1, ix); | |
1482 | } | |
40ab6a6e AS |
1483 | } |
1484 | ||
5c50368f AS |
1485 | static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv) |
1486 | { | |
1487 | if (!priv->params.lro_en) | |
1488 | return; | |
1489 | ||
1490 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
1491 | ||
1492 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
1493 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
1494 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
1495 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
1496 | (priv->params.lro_wqe_sz - | |
1497 | ROUGH_MAX_L2_L3_HDR_SZ) >> 8); | |
1498 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, | |
1499 | MLX5_CAP_ETH(priv->mdev, | |
d9a40271 | 1500 | lro_timer_supported_periods[2])); |
5c50368f AS |
1501 | } |
1502 | ||
bdfc028d TT |
1503 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv) |
1504 | { | |
1505 | MLX5_SET(tirc, tirc, rx_hash_fn, | |
1506 | mlx5e_rx_hash_fn(priv->params.rss_hfunc)); | |
1507 | if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) { | |
1508 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, | |
1509 | rx_hash_toeplitz_key); | |
1510 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
1511 | rx_hash_toeplitz_key); | |
1512 | ||
1513 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
1514 | memcpy(rss_key, priv->params.toeplitz_hash_key, len); | |
1515 | } | |
1516 | } | |
1517 | ||
ab0394fe | 1518 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) |
5c50368f AS |
1519 | { |
1520 | struct mlx5_core_dev *mdev = priv->mdev; | |
1521 | ||
1522 | void *in; | |
1523 | void *tirc; | |
1524 | int inlen; | |
1525 | int err; | |
ab0394fe | 1526 | int tt; |
1da36696 | 1527 | int ix; |
5c50368f AS |
1528 | |
1529 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1530 | in = mlx5_vzalloc(inlen); | |
1531 | if (!in) | |
1532 | return -ENOMEM; | |
1533 | ||
1534 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
1535 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
1536 | ||
1537 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
1538 | ||
1da36696 TT |
1539 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
1540 | err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in, | |
1541 | inlen); | |
ab0394fe | 1542 | if (err) |
1da36696 | 1543 | goto free_in; |
ab0394fe | 1544 | } |
5c50368f | 1545 | |
1da36696 TT |
1546 | for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) { |
1547 | err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, | |
1548 | in, inlen); | |
1549 | if (err) | |
1550 | goto free_in; | |
1551 | } | |
1552 | ||
1553 | free_in: | |
5c50368f AS |
1554 | kvfree(in); |
1555 | ||
1556 | return err; | |
1557 | } | |
1558 | ||
1da36696 | 1559 | static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv) |
66189961 TT |
1560 | { |
1561 | void *in; | |
1562 | int inlen; | |
1563 | int err; | |
1da36696 | 1564 | int i; |
66189961 TT |
1565 | |
1566 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1567 | in = mlx5_vzalloc(inlen); | |
1568 | if (!in) | |
1569 | return -ENOMEM; | |
1570 | ||
1571 | MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1); | |
1572 | ||
1da36696 TT |
1573 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { |
1574 | err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in, | |
1575 | inlen); | |
1576 | if (err) | |
1577 | return err; | |
1578 | } | |
66189961 | 1579 | |
1da36696 TT |
1580 | for (i = 0; i < priv->params.num_channels; i++) { |
1581 | err = mlx5_core_modify_tir(priv->mdev, | |
1582 | priv->direct_tir[i].tirn, in, | |
1583 | inlen); | |
66189961 TT |
1584 | if (err) |
1585 | return err; | |
1586 | } | |
1587 | ||
1da36696 TT |
1588 | kvfree(in); |
1589 | ||
66189961 TT |
1590 | return 0; |
1591 | } | |
1592 | ||
cd255eff | 1593 | static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu) |
40ab6a6e | 1594 | { |
40ab6a6e | 1595 | struct mlx5_core_dev *mdev = priv->mdev; |
cd255eff | 1596 | u16 hw_mtu = MLX5E_SW2HW_MTU(mtu); |
40ab6a6e AS |
1597 | int err; |
1598 | ||
cd255eff | 1599 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
1600 | if (err) |
1601 | return err; | |
1602 | ||
cd255eff SM |
1603 | /* Update vport context MTU */ |
1604 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
1605 | return 0; | |
1606 | } | |
40ab6a6e | 1607 | |
cd255eff SM |
1608 | static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu) |
1609 | { | |
1610 | struct mlx5_core_dev *mdev = priv->mdev; | |
1611 | u16 hw_mtu = 0; | |
1612 | int err; | |
40ab6a6e | 1613 | |
cd255eff SM |
1614 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); |
1615 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
1616 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
1617 | ||
1618 | *mtu = MLX5E_HW2SW_MTU(hw_mtu); | |
1619 | } | |
1620 | ||
1621 | static int mlx5e_set_dev_port_mtu(struct net_device *netdev) | |
1622 | { | |
1623 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1624 | u16 mtu; | |
1625 | int err; | |
1626 | ||
1627 | err = mlx5e_set_mtu(priv, netdev->mtu); | |
1628 | if (err) | |
1629 | return err; | |
40ab6a6e | 1630 | |
cd255eff SM |
1631 | mlx5e_query_mtu(priv, &mtu); |
1632 | if (mtu != netdev->mtu) | |
1633 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", | |
1634 | __func__, mtu, netdev->mtu); | |
40ab6a6e | 1635 | |
cd255eff | 1636 | netdev->mtu = mtu; |
40ab6a6e AS |
1637 | return 0; |
1638 | } | |
1639 | ||
08fb1dac SM |
1640 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
1641 | { | |
1642 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1643 | int nch = priv->params.num_channels; | |
1644 | int ntc = priv->params.num_tc; | |
1645 | int tc; | |
1646 | ||
1647 | netdev_reset_tc(netdev); | |
1648 | ||
1649 | if (ntc == 1) | |
1650 | return; | |
1651 | ||
1652 | netdev_set_num_tc(netdev, ntc); | |
1653 | ||
1654 | for (tc = 0; tc < ntc; tc++) | |
1655 | netdev_set_tc_queue(netdev, tc, nch, tc * nch); | |
1656 | } | |
1657 | ||
40ab6a6e AS |
1658 | int mlx5e_open_locked(struct net_device *netdev) |
1659 | { | |
1660 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1661 | int num_txqs; | |
1662 | int err; | |
1663 | ||
1664 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
1665 | ||
08fb1dac SM |
1666 | mlx5e_netdev_set_tcs(netdev); |
1667 | ||
40ab6a6e AS |
1668 | num_txqs = priv->params.num_channels * priv->params.num_tc; |
1669 | netif_set_real_num_tx_queues(netdev, num_txqs); | |
1670 | netif_set_real_num_rx_queues(netdev, priv->params.num_channels); | |
1671 | ||
1672 | err = mlx5e_set_dev_port_mtu(netdev); | |
1673 | if (err) | |
343b29f3 | 1674 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1675 | |
1676 | err = mlx5e_open_channels(priv); | |
1677 | if (err) { | |
1678 | netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n", | |
1679 | __func__, err); | |
343b29f3 | 1680 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1681 | } |
1682 | ||
66189961 TT |
1683 | err = mlx5e_refresh_tirs_self_loopback_enable(priv); |
1684 | if (err) { | |
1685 | netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n", | |
1686 | __func__, err); | |
1687 | goto err_close_channels; | |
1688 | } | |
1689 | ||
40ab6a6e | 1690 | mlx5e_redirect_rqts(priv); |
ce89ef36 | 1691 | mlx5e_update_carrier(priv); |
ef9814de | 1692 | mlx5e_timestamp_init(priv); |
5a7b27eb MG |
1693 | #ifdef CONFIG_RFS_ACCEL |
1694 | priv->netdev->rx_cpu_rmap = priv->mdev->rmap; | |
1695 | #endif | |
40ab6a6e | 1696 | |
7bb29755 | 1697 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); |
40ab6a6e | 1698 | |
9b37b07f | 1699 | return 0; |
343b29f3 | 1700 | |
66189961 TT |
1701 | err_close_channels: |
1702 | mlx5e_close_channels(priv); | |
343b29f3 AS |
1703 | err_clear_state_opened_flag: |
1704 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
1705 | return err; | |
40ab6a6e AS |
1706 | } |
1707 | ||
1708 | static int mlx5e_open(struct net_device *netdev) | |
1709 | { | |
1710 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1711 | int err; | |
1712 | ||
1713 | mutex_lock(&priv->state_lock); | |
1714 | err = mlx5e_open_locked(netdev); | |
1715 | mutex_unlock(&priv->state_lock); | |
1716 | ||
1717 | return err; | |
1718 | } | |
1719 | ||
1720 | int mlx5e_close_locked(struct net_device *netdev) | |
1721 | { | |
1722 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1723 | ||
a1985740 AS |
1724 | /* May already be CLOSED in case a previous configuration operation |
1725 | * (e.g RX/TX queue size change) that involves close&open failed. | |
1726 | */ | |
1727 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1728 | return 0; | |
1729 | ||
40ab6a6e AS |
1730 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
1731 | ||
ef9814de | 1732 | mlx5e_timestamp_cleanup(priv); |
40ab6a6e | 1733 | netif_carrier_off(priv->netdev); |
ce89ef36 | 1734 | mlx5e_redirect_rqts(priv); |
40ab6a6e AS |
1735 | mlx5e_close_channels(priv); |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | ||
1740 | static int mlx5e_close(struct net_device *netdev) | |
1741 | { | |
1742 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1743 | int err; | |
1744 | ||
1745 | mutex_lock(&priv->state_lock); | |
1746 | err = mlx5e_close_locked(netdev); | |
1747 | mutex_unlock(&priv->state_lock); | |
1748 | ||
1749 | return err; | |
1750 | } | |
1751 | ||
1752 | static int mlx5e_create_drop_rq(struct mlx5e_priv *priv, | |
1753 | struct mlx5e_rq *rq, | |
1754 | struct mlx5e_rq_param *param) | |
1755 | { | |
1756 | struct mlx5_core_dev *mdev = priv->mdev; | |
1757 | void *rqc = param->rqc; | |
1758 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1759 | int err; | |
1760 | ||
1761 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
1762 | ||
1763 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
1764 | &rq->wq_ctrl); | |
1765 | if (err) | |
1766 | return err; | |
1767 | ||
1768 | rq->priv = priv; | |
1769 | ||
1770 | return 0; | |
1771 | } | |
1772 | ||
1773 | static int mlx5e_create_drop_cq(struct mlx5e_priv *priv, | |
1774 | struct mlx5e_cq *cq, | |
1775 | struct mlx5e_cq_param *param) | |
1776 | { | |
1777 | struct mlx5_core_dev *mdev = priv->mdev; | |
1778 | struct mlx5_core_cq *mcq = &cq->mcq; | |
1779 | int eqn_not_used; | |
0b6e26ce | 1780 | unsigned int irqn; |
40ab6a6e AS |
1781 | int err; |
1782 | ||
1783 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
1784 | &cq->wq_ctrl); | |
1785 | if (err) | |
1786 | return err; | |
1787 | ||
1788 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1789 | ||
1790 | mcq->cqe_sz = 64; | |
1791 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1792 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1793 | *mcq->set_ci_db = 0; | |
1794 | *mcq->arm_db = 0; | |
1795 | mcq->vector = param->eq_ix; | |
1796 | mcq->comp = mlx5e_completion_event; | |
1797 | mcq->event = mlx5e_cq_error_event; | |
1798 | mcq->irqn = irqn; | |
1799 | mcq->uar = &priv->cq_uar; | |
1800 | ||
1801 | cq->priv = priv; | |
1802 | ||
1803 | return 0; | |
1804 | } | |
1805 | ||
1806 | static int mlx5e_open_drop_rq(struct mlx5e_priv *priv) | |
1807 | { | |
1808 | struct mlx5e_cq_param cq_param; | |
1809 | struct mlx5e_rq_param rq_param; | |
1810 | struct mlx5e_rq *rq = &priv->drop_rq; | |
1811 | struct mlx5e_cq *cq = &priv->drop_rq.cq; | |
1812 | int err; | |
1813 | ||
1814 | memset(&cq_param, 0, sizeof(cq_param)); | |
1815 | memset(&rq_param, 0, sizeof(rq_param)); | |
556dd1b9 | 1816 | mlx5e_build_drop_rq_param(&rq_param); |
40ab6a6e AS |
1817 | |
1818 | err = mlx5e_create_drop_cq(priv, cq, &cq_param); | |
1819 | if (err) | |
1820 | return err; | |
1821 | ||
1822 | err = mlx5e_enable_cq(cq, &cq_param); | |
1823 | if (err) | |
1824 | goto err_destroy_cq; | |
1825 | ||
1826 | err = mlx5e_create_drop_rq(priv, rq, &rq_param); | |
1827 | if (err) | |
1828 | goto err_disable_cq; | |
1829 | ||
1830 | err = mlx5e_enable_rq(rq, &rq_param); | |
1831 | if (err) | |
1832 | goto err_destroy_rq; | |
1833 | ||
1834 | return 0; | |
1835 | ||
1836 | err_destroy_rq: | |
1837 | mlx5e_destroy_rq(&priv->drop_rq); | |
1838 | ||
1839 | err_disable_cq: | |
1840 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1841 | ||
1842 | err_destroy_cq: | |
1843 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1844 | ||
1845 | return err; | |
1846 | } | |
1847 | ||
1848 | static void mlx5e_close_drop_rq(struct mlx5e_priv *priv) | |
1849 | { | |
1850 | mlx5e_disable_rq(&priv->drop_rq); | |
1851 | mlx5e_destroy_rq(&priv->drop_rq); | |
1852 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1853 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1854 | } | |
1855 | ||
1856 | static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc) | |
1857 | { | |
1858 | struct mlx5_core_dev *mdev = priv->mdev; | |
1859 | u32 in[MLX5_ST_SZ_DW(create_tis_in)]; | |
1860 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); | |
1861 | ||
1862 | memset(in, 0, sizeof(in)); | |
1863 | ||
08fb1dac | 1864 | MLX5_SET(tisc, tisc, prio, tc << 1); |
40ab6a6e AS |
1865 | MLX5_SET(tisc, tisc, transport_domain, priv->tdn); |
1866 | ||
1867 | return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]); | |
1868 | } | |
1869 | ||
1870 | static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc) | |
1871 | { | |
1872 | mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); | |
1873 | } | |
1874 | ||
1875 | static int mlx5e_create_tises(struct mlx5e_priv *priv) | |
1876 | { | |
1877 | int err; | |
1878 | int tc; | |
1879 | ||
08fb1dac | 1880 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) { |
40ab6a6e AS |
1881 | err = mlx5e_create_tis(priv, tc); |
1882 | if (err) | |
1883 | goto err_close_tises; | |
1884 | } | |
1885 | ||
1886 | return 0; | |
1887 | ||
1888 | err_close_tises: | |
1889 | for (tc--; tc >= 0; tc--) | |
1890 | mlx5e_destroy_tis(priv, tc); | |
1891 | ||
1892 | return err; | |
1893 | } | |
1894 | ||
1895 | static void mlx5e_destroy_tises(struct mlx5e_priv *priv) | |
1896 | { | |
1897 | int tc; | |
1898 | ||
08fb1dac | 1899 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) |
40ab6a6e AS |
1900 | mlx5e_destroy_tis(priv, tc); |
1901 | } | |
1902 | ||
1da36696 TT |
1903 | static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, |
1904 | enum mlx5e_traffic_types tt) | |
f62b8bb8 AV |
1905 | { |
1906 | void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
1907 | ||
3191e05f AS |
1908 | MLX5_SET(tirc, tirc, transport_domain, priv->tdn); |
1909 | ||
5a6f8aef AS |
1910 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1911 | MLX5_HASH_FIELD_SEL_DST_IP) | |
f62b8bb8 | 1912 | |
5a6f8aef AS |
1913 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1914 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
1915 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
1916 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
f62b8bb8 | 1917 | |
a741749f AS |
1918 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1919 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
1920 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
1921 | ||
5c50368f | 1922 | mlx5e_build_tir_ctx_lro(tirc, priv); |
f62b8bb8 | 1923 | |
4cbeaff5 | 1924 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
1da36696 TT |
1925 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn); |
1926 | mlx5e_build_tir_ctx_hash(tirc, priv); | |
f62b8bb8 AV |
1927 | |
1928 | switch (tt) { | |
1929 | case MLX5E_TT_IPV4_TCP: | |
1930 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1931 | MLX5_L3_PROT_TYPE_IPV4); | |
1932 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1933 | MLX5_L4_PROT_TYPE_TCP); | |
1934 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1935 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1936 | break; |
1937 | ||
1938 | case MLX5E_TT_IPV6_TCP: | |
1939 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1940 | MLX5_L3_PROT_TYPE_IPV6); | |
1941 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1942 | MLX5_L4_PROT_TYPE_TCP); | |
1943 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1944 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1945 | break; |
1946 | ||
1947 | case MLX5E_TT_IPV4_UDP: | |
1948 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1949 | MLX5_L3_PROT_TYPE_IPV4); | |
1950 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1951 | MLX5_L4_PROT_TYPE_UDP); | |
1952 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1953 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1954 | break; |
1955 | ||
1956 | case MLX5E_TT_IPV6_UDP: | |
1957 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1958 | MLX5_L3_PROT_TYPE_IPV6); | |
1959 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1960 | MLX5_L4_PROT_TYPE_UDP); | |
1961 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1962 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1963 | break; |
1964 | ||
a741749f AS |
1965 | case MLX5E_TT_IPV4_IPSEC_AH: |
1966 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1967 | MLX5_L3_PROT_TYPE_IPV4); | |
1968 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1969 | MLX5_HASH_IP_IPSEC_SPI); | |
1970 | break; | |
1971 | ||
1972 | case MLX5E_TT_IPV6_IPSEC_AH: | |
1973 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1974 | MLX5_L3_PROT_TYPE_IPV6); | |
1975 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1976 | MLX5_HASH_IP_IPSEC_SPI); | |
1977 | break; | |
1978 | ||
1979 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
1980 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1981 | MLX5_L3_PROT_TYPE_IPV4); | |
1982 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1983 | MLX5_HASH_IP_IPSEC_SPI); | |
1984 | break; | |
1985 | ||
1986 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
1987 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1988 | MLX5_L3_PROT_TYPE_IPV6); | |
1989 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1990 | MLX5_HASH_IP_IPSEC_SPI); | |
1991 | break; | |
1992 | ||
f62b8bb8 AV |
1993 | case MLX5E_TT_IPV4: |
1994 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1995 | MLX5_L3_PROT_TYPE_IPV4); | |
1996 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1997 | MLX5_HASH_IP); | |
1998 | break; | |
1999 | ||
2000 | case MLX5E_TT_IPV6: | |
2001 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2002 | MLX5_L3_PROT_TYPE_IPV6); | |
2003 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2004 | MLX5_HASH_IP); | |
2005 | break; | |
1da36696 TT |
2006 | default: |
2007 | WARN_ONCE(true, | |
2008 | "mlx5e_build_indir_tir_ctx: bad traffic type!\n"); | |
f62b8bb8 AV |
2009 | } |
2010 | } | |
2011 | ||
1da36696 TT |
2012 | static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, |
2013 | u32 rqtn) | |
f62b8bb8 | 2014 | { |
1da36696 TT |
2015 | MLX5_SET(tirc, tirc, transport_domain, priv->tdn); |
2016 | ||
2017 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
2018 | ||
2019 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2020 | MLX5_SET(tirc, tirc, indirect_table, rqtn); | |
2021 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
2022 | } | |
2023 | ||
2024 | static int mlx5e_create_tirs(struct mlx5e_priv *priv) | |
2025 | { | |
2026 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
f62b8bb8 AV |
2027 | void *tirc; |
2028 | int inlen; | |
1da36696 | 2029 | u32 *tirn; |
f62b8bb8 | 2030 | int err; |
1da36696 TT |
2031 | u32 *in; |
2032 | int ix; | |
2033 | int tt; | |
f62b8bb8 AV |
2034 | |
2035 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
2036 | in = mlx5_vzalloc(inlen); | |
2037 | if (!in) | |
2038 | return -ENOMEM; | |
2039 | ||
1da36696 TT |
2040 | /* indirect tirs */ |
2041 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | |
2042 | memset(in, 0, inlen); | |
2043 | tirn = &priv->indir_tirn[tt]; | |
2044 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
2045 | mlx5e_build_indir_tir_ctx(priv, tirc, tt); | |
2046 | err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn); | |
f62b8bb8 | 2047 | if (err) |
40ab6a6e | 2048 | goto err_destroy_tirs; |
f62b8bb8 AV |
2049 | } |
2050 | ||
1da36696 TT |
2051 | /* direct tirs */ |
2052 | for (ix = 0; ix < nch; ix++) { | |
2053 | memset(in, 0, inlen); | |
2054 | tirn = &priv->direct_tir[ix].tirn; | |
2055 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
2056 | mlx5e_build_direct_tir_ctx(priv, tirc, | |
2057 | priv->direct_tir[ix].rqtn); | |
2058 | err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn); | |
2059 | if (err) | |
2060 | goto err_destroy_ch_tirs; | |
2061 | } | |
2062 | ||
2063 | kvfree(in); | |
2064 | ||
f62b8bb8 AV |
2065 | return 0; |
2066 | ||
1da36696 TT |
2067 | err_destroy_ch_tirs: |
2068 | for (ix--; ix >= 0; ix--) | |
2069 | mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn); | |
2070 | ||
40ab6a6e | 2071 | err_destroy_tirs: |
1da36696 TT |
2072 | for (tt--; tt >= 0; tt--) |
2073 | mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]); | |
2074 | ||
2075 | kvfree(in); | |
f62b8bb8 AV |
2076 | |
2077 | return err; | |
2078 | } | |
2079 | ||
40ab6a6e | 2080 | static void mlx5e_destroy_tirs(struct mlx5e_priv *priv) |
f62b8bb8 | 2081 | { |
1da36696 | 2082 | int nch = mlx5e_get_max_num_channels(priv->mdev); |
f62b8bb8 AV |
2083 | int i; |
2084 | ||
1da36696 TT |
2085 | for (i = 0; i < nch; i++) |
2086 | mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn); | |
2087 | ||
2088 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) | |
2089 | mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]); | |
f62b8bb8 AV |
2090 | } |
2091 | ||
36350114 GP |
2092 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd) |
2093 | { | |
2094 | int err = 0; | |
2095 | int i; | |
2096 | ||
2097 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2098 | return 0; | |
2099 | ||
2100 | for (i = 0; i < priv->params.num_channels; i++) { | |
2101 | err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd); | |
2102 | if (err) | |
2103 | return err; | |
2104 | } | |
2105 | ||
2106 | return 0; | |
2107 | } | |
2108 | ||
08fb1dac SM |
2109 | static int mlx5e_setup_tc(struct net_device *netdev, u8 tc) |
2110 | { | |
2111 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2112 | bool was_opened; | |
2113 | int err = 0; | |
2114 | ||
2115 | if (tc && tc != MLX5E_MAX_NUM_TC) | |
2116 | return -EINVAL; | |
2117 | ||
2118 | mutex_lock(&priv->state_lock); | |
2119 | ||
2120 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2121 | if (was_opened) | |
2122 | mlx5e_close_locked(priv->netdev); | |
2123 | ||
2124 | priv->params.num_tc = tc ? tc : 1; | |
2125 | ||
2126 | if (was_opened) | |
2127 | err = mlx5e_open_locked(priv->netdev); | |
2128 | ||
2129 | mutex_unlock(&priv->state_lock); | |
2130 | ||
2131 | return err; | |
2132 | } | |
2133 | ||
2134 | static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle, | |
2135 | __be16 proto, struct tc_to_netdev *tc) | |
2136 | { | |
e8f887ac AV |
2137 | struct mlx5e_priv *priv = netdev_priv(dev); |
2138 | ||
2139 | if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS)) | |
2140 | goto mqprio; | |
2141 | ||
2142 | switch (tc->type) { | |
e3a2b7ed AV |
2143 | case TC_SETUP_CLSFLOWER: |
2144 | switch (tc->cls_flower->command) { | |
2145 | case TC_CLSFLOWER_REPLACE: | |
2146 | return mlx5e_configure_flower(priv, proto, tc->cls_flower); | |
2147 | case TC_CLSFLOWER_DESTROY: | |
2148 | return mlx5e_delete_flower(priv, tc->cls_flower); | |
2149 | } | |
e8f887ac AV |
2150 | default: |
2151 | return -EOPNOTSUPP; | |
2152 | } | |
2153 | ||
2154 | mqprio: | |
67ba422e | 2155 | if (tc->type != TC_SETUP_MQPRIO) |
08fb1dac SM |
2156 | return -EINVAL; |
2157 | ||
2158 | return mlx5e_setup_tc(dev, tc->tc); | |
2159 | } | |
2160 | ||
f62b8bb8 AV |
2161 | static struct rtnl_link_stats64 * |
2162 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
2163 | { | |
2164 | struct mlx5e_priv *priv = netdev_priv(dev); | |
9218b44d | 2165 | struct mlx5e_sw_stats *sstats = &priv->stats.sw; |
f62b8bb8 | 2166 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; |
269e6b3a | 2167 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; |
f62b8bb8 | 2168 | |
9218b44d GP |
2169 | stats->rx_packets = sstats->rx_packets; |
2170 | stats->rx_bytes = sstats->rx_bytes; | |
2171 | stats->tx_packets = sstats->tx_packets; | |
2172 | stats->tx_bytes = sstats->tx_bytes; | |
269e6b3a GP |
2173 | |
2174 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
9218b44d | 2175 | stats->tx_dropped = sstats->tx_queue_dropped; |
269e6b3a GP |
2176 | |
2177 | stats->rx_length_errors = | |
9218b44d GP |
2178 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + |
2179 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
2180 | PPORT_802_3_GET(pstats, a_frame_too_long_errors); | |
269e6b3a | 2181 | stats->rx_crc_errors = |
9218b44d GP |
2182 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); |
2183 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
2184 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
269e6b3a | 2185 | stats->tx_carrier_errors = |
9218b44d | 2186 | PPORT_802_3_GET(pstats, a_symbol_error_during_carrier); |
269e6b3a GP |
2187 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
2188 | stats->rx_frame_errors; | |
2189 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
2190 | ||
2191 | /* vport multicast also counts packets that are dropped due to steering | |
2192 | * or rx out of buffer | |
2193 | */ | |
9218b44d GP |
2194 | stats->multicast = |
2195 | VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
f62b8bb8 AV |
2196 | |
2197 | return stats; | |
2198 | } | |
2199 | ||
2200 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
2201 | { | |
2202 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2203 | ||
7bb29755 | 2204 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
2205 | } |
2206 | ||
2207 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
2208 | { | |
2209 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2210 | struct sockaddr *saddr = addr; | |
2211 | ||
2212 | if (!is_valid_ether_addr(saddr->sa_data)) | |
2213 | return -EADDRNOTAVAIL; | |
2214 | ||
2215 | netif_addr_lock_bh(netdev); | |
2216 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
2217 | netif_addr_unlock_bh(netdev); | |
2218 | ||
7bb29755 | 2219 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
2220 | |
2221 | return 0; | |
2222 | } | |
2223 | ||
0e405443 GP |
2224 | #define MLX5E_SET_FEATURE(netdev, feature, enable) \ |
2225 | do { \ | |
2226 | if (enable) \ | |
2227 | netdev->features |= feature; \ | |
2228 | else \ | |
2229 | netdev->features &= ~feature; \ | |
2230 | } while (0) | |
2231 | ||
2232 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
2233 | ||
2234 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
f62b8bb8 AV |
2235 | { |
2236 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
0e405443 GP |
2237 | bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
2238 | int err; | |
f62b8bb8 AV |
2239 | |
2240 | mutex_lock(&priv->state_lock); | |
f62b8bb8 | 2241 | |
0e405443 GP |
2242 | if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)) |
2243 | mlx5e_close_locked(priv->netdev); | |
98e81b0a | 2244 | |
0e405443 GP |
2245 | priv->params.lro_en = enable; |
2246 | err = mlx5e_modify_tirs_lro(priv); | |
2247 | if (err) { | |
2248 | netdev_err(netdev, "lro modify failed, %d\n", err); | |
2249 | priv->params.lro_en = !enable; | |
98e81b0a | 2250 | } |
f62b8bb8 | 2251 | |
0e405443 GP |
2252 | if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)) |
2253 | mlx5e_open_locked(priv->netdev); | |
2254 | ||
9b37b07f AS |
2255 | mutex_unlock(&priv->state_lock); |
2256 | ||
0e405443 GP |
2257 | return err; |
2258 | } | |
2259 | ||
2260 | static int set_feature_vlan_filter(struct net_device *netdev, bool enable) | |
2261 | { | |
2262 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2263 | ||
2264 | if (enable) | |
2265 | mlx5e_enable_vlan_filter(priv); | |
2266 | else | |
2267 | mlx5e_disable_vlan_filter(priv); | |
2268 | ||
2269 | return 0; | |
2270 | } | |
2271 | ||
2272 | static int set_feature_tc_num_filters(struct net_device *netdev, bool enable) | |
2273 | { | |
2274 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
f62b8bb8 | 2275 | |
0e405443 | 2276 | if (!enable && mlx5e_tc_num_filters(priv)) { |
e8f887ac AV |
2277 | netdev_err(netdev, |
2278 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
2279 | return -EINVAL; | |
2280 | } | |
2281 | ||
0e405443 GP |
2282 | return 0; |
2283 | } | |
2284 | ||
94cb1ebb EBE |
2285 | static int set_feature_rx_all(struct net_device *netdev, bool enable) |
2286 | { | |
2287 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2288 | struct mlx5_core_dev *mdev = priv->mdev; | |
2289 | ||
2290 | return mlx5_set_port_fcs(mdev, !enable); | |
2291 | } | |
2292 | ||
36350114 GP |
2293 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) |
2294 | { | |
2295 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2296 | int err; | |
2297 | ||
2298 | mutex_lock(&priv->state_lock); | |
2299 | ||
2300 | priv->params.vlan_strip_disable = !enable; | |
2301 | err = mlx5e_modify_rqs_vsd(priv, !enable); | |
2302 | if (err) | |
2303 | priv->params.vlan_strip_disable = enable; | |
2304 | ||
2305 | mutex_unlock(&priv->state_lock); | |
2306 | ||
2307 | return err; | |
2308 | } | |
2309 | ||
45bf454a MG |
2310 | #ifdef CONFIG_RFS_ACCEL |
2311 | static int set_feature_arfs(struct net_device *netdev, bool enable) | |
2312 | { | |
2313 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2314 | int err; | |
2315 | ||
2316 | if (enable) | |
2317 | err = mlx5e_arfs_enable(priv); | |
2318 | else | |
2319 | err = mlx5e_arfs_disable(priv); | |
2320 | ||
2321 | return err; | |
2322 | } | |
2323 | #endif | |
2324 | ||
0e405443 GP |
2325 | static int mlx5e_handle_feature(struct net_device *netdev, |
2326 | netdev_features_t wanted_features, | |
2327 | netdev_features_t feature, | |
2328 | mlx5e_feature_handler feature_handler) | |
2329 | { | |
2330 | netdev_features_t changes = wanted_features ^ netdev->features; | |
2331 | bool enable = !!(wanted_features & feature); | |
2332 | int err; | |
2333 | ||
2334 | if (!(changes & feature)) | |
2335 | return 0; | |
2336 | ||
2337 | err = feature_handler(netdev, enable); | |
2338 | if (err) { | |
2339 | netdev_err(netdev, "%s feature 0x%llx failed err %d\n", | |
2340 | enable ? "Enable" : "Disable", feature, err); | |
2341 | return err; | |
2342 | } | |
2343 | ||
2344 | MLX5E_SET_FEATURE(netdev, feature, enable); | |
2345 | return 0; | |
2346 | } | |
2347 | ||
2348 | static int mlx5e_set_features(struct net_device *netdev, | |
2349 | netdev_features_t features) | |
2350 | { | |
2351 | int err; | |
2352 | ||
2353 | err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO, | |
2354 | set_feature_lro); | |
2355 | err |= mlx5e_handle_feature(netdev, features, | |
2356 | NETIF_F_HW_VLAN_CTAG_FILTER, | |
2357 | set_feature_vlan_filter); | |
2358 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC, | |
2359 | set_feature_tc_num_filters); | |
94cb1ebb EBE |
2360 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL, |
2361 | set_feature_rx_all); | |
36350114 GP |
2362 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX, |
2363 | set_feature_rx_vlan); | |
45bf454a MG |
2364 | #ifdef CONFIG_RFS_ACCEL |
2365 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE, | |
2366 | set_feature_arfs); | |
2367 | #endif | |
0e405443 GP |
2368 | |
2369 | return err ? -EINVAL : 0; | |
f62b8bb8 AV |
2370 | } |
2371 | ||
d8edd246 SM |
2372 | #define MXL5_HW_MIN_MTU 64 |
2373 | #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN) | |
2374 | ||
f62b8bb8 AV |
2375 | static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu) |
2376 | { | |
2377 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2378 | struct mlx5_core_dev *mdev = priv->mdev; | |
98e81b0a | 2379 | bool was_opened; |
046339ea | 2380 | u16 max_mtu; |
d8edd246 | 2381 | u16 min_mtu; |
98e81b0a | 2382 | int err = 0; |
f62b8bb8 | 2383 | |
facc9699 | 2384 | mlx5_query_port_max_mtu(mdev, &max_mtu, 1); |
f62b8bb8 | 2385 | |
50a9eea6 | 2386 | max_mtu = MLX5E_HW2SW_MTU(max_mtu); |
d8edd246 | 2387 | min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU); |
50a9eea6 | 2388 | |
d8edd246 | 2389 | if (new_mtu > max_mtu || new_mtu < min_mtu) { |
facc9699 | 2390 | netdev_err(netdev, |
d8edd246 SM |
2391 | "%s: Bad MTU (%d), valid range is: [%d..%d]\n", |
2392 | __func__, new_mtu, min_mtu, max_mtu); | |
f62b8bb8 AV |
2393 | return -EINVAL; |
2394 | } | |
2395 | ||
2396 | mutex_lock(&priv->state_lock); | |
98e81b0a AS |
2397 | |
2398 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2399 | if (was_opened) | |
2400 | mlx5e_close_locked(netdev); | |
2401 | ||
f62b8bb8 | 2402 | netdev->mtu = new_mtu; |
98e81b0a AS |
2403 | |
2404 | if (was_opened) | |
2405 | err = mlx5e_open_locked(netdev); | |
2406 | ||
f62b8bb8 AV |
2407 | mutex_unlock(&priv->state_lock); |
2408 | ||
2409 | return err; | |
2410 | } | |
2411 | ||
ef9814de EBE |
2412 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2413 | { | |
2414 | switch (cmd) { | |
2415 | case SIOCSHWTSTAMP: | |
2416 | return mlx5e_hwstamp_set(dev, ifr); | |
2417 | case SIOCGHWTSTAMP: | |
2418 | return mlx5e_hwstamp_get(dev, ifr); | |
2419 | default: | |
2420 | return -EOPNOTSUPP; | |
2421 | } | |
2422 | } | |
2423 | ||
66e49ded SM |
2424 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
2425 | { | |
2426 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2427 | struct mlx5_core_dev *mdev = priv->mdev; | |
2428 | ||
2429 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
2430 | } | |
2431 | ||
2432 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos) | |
2433 | { | |
2434 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2435 | struct mlx5_core_dev *mdev = priv->mdev; | |
2436 | ||
2437 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, | |
2438 | vlan, qos); | |
2439 | } | |
2440 | ||
2441 | static int mlx5_vport_link2ifla(u8 esw_link) | |
2442 | { | |
2443 | switch (esw_link) { | |
2444 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
2445 | return IFLA_VF_LINK_STATE_DISABLE; | |
2446 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
2447 | return IFLA_VF_LINK_STATE_ENABLE; | |
2448 | } | |
2449 | return IFLA_VF_LINK_STATE_AUTO; | |
2450 | } | |
2451 | ||
2452 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
2453 | { | |
2454 | switch (ifla_link) { | |
2455 | case IFLA_VF_LINK_STATE_DISABLE: | |
2456 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
2457 | case IFLA_VF_LINK_STATE_ENABLE: | |
2458 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
2459 | } | |
2460 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
2461 | } | |
2462 | ||
2463 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
2464 | int link_state) | |
2465 | { | |
2466 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2467 | struct mlx5_core_dev *mdev = priv->mdev; | |
2468 | ||
2469 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
2470 | mlx5_ifla_link2vport(link_state)); | |
2471 | } | |
2472 | ||
2473 | static int mlx5e_get_vf_config(struct net_device *dev, | |
2474 | int vf, struct ifla_vf_info *ivi) | |
2475 | { | |
2476 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2477 | struct mlx5_core_dev *mdev = priv->mdev; | |
2478 | int err; | |
2479 | ||
2480 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
2481 | if (err) | |
2482 | return err; | |
2483 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
2484 | return 0; | |
2485 | } | |
2486 | ||
2487 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
2488 | int vf, struct ifla_vf_stats *vf_stats) | |
2489 | { | |
2490 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2491 | struct mlx5_core_dev *mdev = priv->mdev; | |
2492 | ||
2493 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
2494 | vf_stats); | |
2495 | } | |
2496 | ||
b3f63c3d MF |
2497 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
2498 | sa_family_t sa_family, __be16 port) | |
2499 | { | |
2500 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2501 | ||
2502 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
2503 | return; | |
2504 | ||
d8cf2dda | 2505 | mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1); |
b3f63c3d MF |
2506 | } |
2507 | ||
2508 | static void mlx5e_del_vxlan_port(struct net_device *netdev, | |
2509 | sa_family_t sa_family, __be16 port) | |
2510 | { | |
2511 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2512 | ||
2513 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
2514 | return; | |
2515 | ||
d8cf2dda | 2516 | mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0); |
b3f63c3d MF |
2517 | } |
2518 | ||
2519 | static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv, | |
2520 | struct sk_buff *skb, | |
2521 | netdev_features_t features) | |
2522 | { | |
2523 | struct udphdr *udph; | |
2524 | u16 proto; | |
2525 | u16 port = 0; | |
2526 | ||
2527 | switch (vlan_get_protocol(skb)) { | |
2528 | case htons(ETH_P_IP): | |
2529 | proto = ip_hdr(skb)->protocol; | |
2530 | break; | |
2531 | case htons(ETH_P_IPV6): | |
2532 | proto = ipv6_hdr(skb)->nexthdr; | |
2533 | break; | |
2534 | default: | |
2535 | goto out; | |
2536 | } | |
2537 | ||
2538 | if (proto == IPPROTO_UDP) { | |
2539 | udph = udp_hdr(skb); | |
2540 | port = be16_to_cpu(udph->dest); | |
2541 | } | |
2542 | ||
2543 | /* Verify if UDP port is being offloaded by HW */ | |
2544 | if (port && mlx5e_vxlan_lookup_port(priv, port)) | |
2545 | return features; | |
2546 | ||
2547 | out: | |
2548 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
2549 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
2550 | } | |
2551 | ||
2552 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
2553 | struct net_device *netdev, | |
2554 | netdev_features_t features) | |
2555 | { | |
2556 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2557 | ||
2558 | features = vlan_features_check(skb, features); | |
2559 | features = vxlan_features_check(skb, features); | |
2560 | ||
2561 | /* Validate if the tunneled packet is being offloaded by HW */ | |
2562 | if (skb->encapsulation && | |
2563 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
2564 | return mlx5e_vxlan_features_check(priv, skb, features); | |
2565 | ||
2566 | return features; | |
2567 | } | |
2568 | ||
b0eed40e | 2569 | static const struct net_device_ops mlx5e_netdev_ops_basic = { |
f62b8bb8 AV |
2570 | .ndo_open = mlx5e_open, |
2571 | .ndo_stop = mlx5e_close, | |
2572 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2573 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2574 | .ndo_select_queue = mlx5e_select_queue, | |
f62b8bb8 AV |
2575 | .ndo_get_stats64 = mlx5e_get_stats, |
2576 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2577 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
2578 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
2579 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 2580 | .ndo_set_features = mlx5e_set_features, |
b0eed40e SM |
2581 | .ndo_change_mtu = mlx5e_change_mtu, |
2582 | .ndo_do_ioctl = mlx5e_ioctl, | |
45bf454a MG |
2583 | #ifdef CONFIG_RFS_ACCEL |
2584 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
2585 | #endif | |
b0eed40e SM |
2586 | }; |
2587 | ||
2588 | static const struct net_device_ops mlx5e_netdev_ops_sriov = { | |
2589 | .ndo_open = mlx5e_open, | |
2590 | .ndo_stop = mlx5e_close, | |
2591 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2592 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2593 | .ndo_select_queue = mlx5e_select_queue, | |
b0eed40e SM |
2594 | .ndo_get_stats64 = mlx5e_get_stats, |
2595 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2596 | .ndo_set_mac_address = mlx5e_set_mac, | |
2597 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, | |
2598 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
2599 | .ndo_set_features = mlx5e_set_features, | |
2600 | .ndo_change_mtu = mlx5e_change_mtu, | |
2601 | .ndo_do_ioctl = mlx5e_ioctl, | |
b3f63c3d MF |
2602 | .ndo_add_vxlan_port = mlx5e_add_vxlan_port, |
2603 | .ndo_del_vxlan_port = mlx5e_del_vxlan_port, | |
2604 | .ndo_features_check = mlx5e_features_check, | |
45bf454a MG |
2605 | #ifdef CONFIG_RFS_ACCEL |
2606 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
2607 | #endif | |
b0eed40e SM |
2608 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
2609 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
2610 | .ndo_get_vf_config = mlx5e_get_vf_config, | |
2611 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
2612 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
f62b8bb8 AV |
2613 | }; |
2614 | ||
2615 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
2616 | { | |
2617 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
2618 | return -ENOTSUPP; | |
2619 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || | |
2620 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
2621 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
2622 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
2623 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
2624 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
2625 | MLX5_CAP_FLOWTABLE(mdev, | |
2626 | flow_table_properties_nic_receive.max_ft_level) | |
2627 | < 3) { | |
f62b8bb8 AV |
2628 | mlx5_core_warn(mdev, |
2629 | "Not creating net device, some required device capabilities are missing\n"); | |
2630 | return -ENOTSUPP; | |
2631 | } | |
66189961 TT |
2632 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
2633 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
7524a5d8 GP |
2634 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
2635 | mlx5_core_warn(mdev, "CQ modiration is not supported\n"); | |
66189961 | 2636 | |
f62b8bb8 AV |
2637 | return 0; |
2638 | } | |
2639 | ||
58d52291 AS |
2640 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) |
2641 | { | |
2642 | int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; | |
2643 | ||
2644 | return bf_buf_size - | |
2645 | sizeof(struct mlx5e_tx_wqe) + | |
2646 | 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/; | |
2647 | } | |
2648 | ||
08fb1dac SM |
2649 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2650 | static void mlx5e_ets_init(struct mlx5e_priv *priv) | |
2651 | { | |
2652 | int i; | |
2653 | ||
2654 | priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1; | |
2655 | for (i = 0; i < priv->params.ets.ets_cap; i++) { | |
2656 | priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC; | |
2657 | priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR; | |
2658 | priv->params.ets.prio_tc[i] = i; | |
2659 | } | |
2660 | ||
2661 | /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */ | |
2662 | priv->params.ets.prio_tc[0] = 1; | |
2663 | priv->params.ets.prio_tc[1] = 0; | |
2664 | } | |
2665 | #endif | |
2666 | ||
d8c9660d TT |
2667 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
2668 | u32 *indirection_rqt, int len, | |
85082dba TT |
2669 | int num_channels) |
2670 | { | |
d8c9660d TT |
2671 | int node = mdev->priv.numa_node; |
2672 | int node_num_of_cores; | |
85082dba TT |
2673 | int i; |
2674 | ||
d8c9660d TT |
2675 | if (node == -1) |
2676 | node = first_online_node; | |
2677 | ||
2678 | node_num_of_cores = cpumask_weight(cpumask_of_node(node)); | |
2679 | ||
2680 | if (node_num_of_cores) | |
2681 | num_channels = min_t(int, num_channels, node_num_of_cores); | |
2682 | ||
85082dba TT |
2683 | for (i = 0; i < len; i++) |
2684 | indirection_rqt[i] = i % num_channels; | |
2685 | } | |
2686 | ||
bc77b240 TT |
2687 | static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) |
2688 | { | |
2689 | return MLX5_CAP_GEN(mdev, striding_rq) && | |
2690 | MLX5_CAP_GEN(mdev, umr_ptr_rlky) && | |
2691 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
2692 | } | |
2693 | ||
f62b8bb8 AV |
2694 | static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, |
2695 | struct net_device *netdev, | |
936896e9 | 2696 | int num_channels) |
f62b8bb8 AV |
2697 | { |
2698 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2699 | ||
2700 | priv->params.log_sq_size = | |
2701 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
bc77b240 | 2702 | priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ? |
461017cb TT |
2703 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : |
2704 | MLX5_WQ_TYPE_LINKED_LIST; | |
2705 | ||
2706 | switch (priv->params.rq_wq_type) { | |
2707 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
2708 | priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW; | |
2709 | priv->params.lro_en = true; | |
2710 | break; | |
2711 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
2712 | priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
2713 | } | |
2714 | ||
2715 | priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type, | |
2716 | BIT(priv->params.log_rq_size)); | |
f62b8bb8 AV |
2717 | priv->params.rx_cq_moderation_usec = |
2718 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
2719 | priv->params.rx_cq_moderation_pkts = | |
2720 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
2721 | priv->params.tx_cq_moderation_usec = | |
2722 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
2723 | priv->params.tx_cq_moderation_pkts = | |
2724 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
58d52291 | 2725 | priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); |
f62b8bb8 | 2726 | priv->params.num_tc = 1; |
2be6967c | 2727 | priv->params.rss_hfunc = ETH_RSS_HASH_XOR; |
f62b8bb8 | 2728 | |
57afead5 AS |
2729 | netdev_rss_key_fill(priv->params.toeplitz_hash_key, |
2730 | sizeof(priv->params.toeplitz_hash_key)); | |
2731 | ||
d8c9660d | 2732 | mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt, |
85082dba | 2733 | MLX5E_INDIR_RQT_SIZE, num_channels); |
2d75b2bc | 2734 | |
f62b8bb8 AV |
2735 | priv->params.lro_wqe_sz = |
2736 | MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; | |
2737 | ||
2738 | priv->mdev = mdev; | |
2739 | priv->netdev = netdev; | |
936896e9 | 2740 | priv->params.num_channels = num_channels; |
f62b8bb8 | 2741 | |
08fb1dac SM |
2742 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2743 | mlx5e_ets_init(priv); | |
2744 | #endif | |
f62b8bb8 | 2745 | |
f62b8bb8 AV |
2746 | mutex_init(&priv->state_lock); |
2747 | ||
2748 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
2749 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
2750 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); | |
2751 | } | |
2752 | ||
2753 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
2754 | { | |
2755 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2756 | ||
e1d7d349 | 2757 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
2758 | if (is_zero_ether_addr(netdev->dev_addr) && |
2759 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
2760 | eth_hw_addr_random(netdev); | |
2761 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
2762 | } | |
f62b8bb8 AV |
2763 | } |
2764 | ||
2765 | static void mlx5e_build_netdev(struct net_device *netdev) | |
2766 | { | |
2767 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2768 | struct mlx5_core_dev *mdev = priv->mdev; | |
94cb1ebb EBE |
2769 | bool fcs_supported; |
2770 | bool fcs_enabled; | |
f62b8bb8 AV |
2771 | |
2772 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
2773 | ||
08fb1dac | 2774 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) { |
b0eed40e | 2775 | netdev->netdev_ops = &mlx5e_netdev_ops_sriov; |
08fb1dac SM |
2776 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2777 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
2778 | #endif | |
2779 | } else { | |
b0eed40e | 2780 | netdev->netdev_ops = &mlx5e_netdev_ops_basic; |
08fb1dac | 2781 | } |
66e49ded | 2782 | |
f62b8bb8 AV |
2783 | netdev->watchdog_timeo = 15 * HZ; |
2784 | ||
2785 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
2786 | ||
12be4b21 | 2787 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
2788 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
2789 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
2790 | netdev->vlan_features |= NETIF_F_GRO; | |
2791 | netdev->vlan_features |= NETIF_F_TSO; | |
2792 | netdev->vlan_features |= NETIF_F_TSO6; | |
2793 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
2794 | netdev->vlan_features |= NETIF_F_RXHASH; | |
2795 | ||
2796 | if (!!MLX5_CAP_ETH(mdev, lro_cap)) | |
2797 | netdev->vlan_features |= NETIF_F_LRO; | |
2798 | ||
2799 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 2800 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
2801 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
2802 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
2803 | ||
b3f63c3d | 2804 | if (mlx5e_vxlan_allowed(mdev)) { |
b49663c8 AD |
2805 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | |
2806 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
2807 | NETIF_F_GSO_PARTIAL; | |
b3f63c3d MF |
2808 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; |
2809 | netdev->hw_enc_features |= NETIF_F_RXCSUM; | |
2810 | netdev->hw_enc_features |= NETIF_F_TSO; | |
2811 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
2812 | netdev->hw_enc_features |= NETIF_F_RXHASH; | |
2813 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; | |
b49663c8 AD |
2814 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM | |
2815 | NETIF_F_GSO_PARTIAL; | |
2816 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
b3f63c3d MF |
2817 | } |
2818 | ||
94cb1ebb EBE |
2819 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); |
2820 | ||
2821 | if (fcs_supported) | |
2822 | netdev->hw_features |= NETIF_F_RXALL; | |
2823 | ||
f62b8bb8 AV |
2824 | netdev->features = netdev->hw_features; |
2825 | if (!priv->params.lro_en) | |
2826 | netdev->features &= ~NETIF_F_LRO; | |
2827 | ||
94cb1ebb EBE |
2828 | if (fcs_enabled) |
2829 | netdev->features &= ~NETIF_F_RXALL; | |
2830 | ||
e8f887ac AV |
2831 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
2832 | if (FT_CAP(flow_modify_en) && | |
2833 | FT_CAP(modify_root) && | |
2834 | FT_CAP(identified_miss_table_mode) && | |
1cabe6b0 MG |
2835 | FT_CAP(flow_table_modify)) { |
2836 | netdev->hw_features |= NETIF_F_HW_TC; | |
2837 | #ifdef CONFIG_RFS_ACCEL | |
2838 | netdev->hw_features |= NETIF_F_NTUPLE; | |
2839 | #endif | |
2840 | } | |
e8f887ac | 2841 | |
f62b8bb8 AV |
2842 | netdev->features |= NETIF_F_HIGHDMA; |
2843 | ||
2844 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
2845 | ||
2846 | mlx5e_set_netdev_dev_addr(netdev); | |
2847 | } | |
2848 | ||
2849 | static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, | |
a606b0f6 | 2850 | struct mlx5_core_mkey *mkey) |
f62b8bb8 AV |
2851 | { |
2852 | struct mlx5_core_dev *mdev = priv->mdev; | |
2853 | struct mlx5_create_mkey_mbox_in *in; | |
2854 | int err; | |
2855 | ||
2856 | in = mlx5_vzalloc(sizeof(*in)); | |
2857 | if (!in) | |
2858 | return -ENOMEM; | |
2859 | ||
2860 | in->seg.flags = MLX5_PERM_LOCAL_WRITE | | |
2861 | MLX5_PERM_LOCAL_READ | | |
2862 | MLX5_ACCESS_MODE_PA; | |
2863 | in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64); | |
2864 | in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
2865 | ||
a606b0f6 | 2866 | err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL, |
f62b8bb8 AV |
2867 | NULL); |
2868 | ||
2869 | kvfree(in); | |
2870 | ||
2871 | return err; | |
2872 | } | |
2873 | ||
593cf338 RS |
2874 | static void mlx5e_create_q_counter(struct mlx5e_priv *priv) |
2875 | { | |
2876 | struct mlx5_core_dev *mdev = priv->mdev; | |
2877 | int err; | |
2878 | ||
2879 | err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter); | |
2880 | if (err) { | |
2881 | mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err); | |
2882 | priv->q_counter = 0; | |
2883 | } | |
2884 | } | |
2885 | ||
2886 | static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv) | |
2887 | { | |
2888 | if (!priv->q_counter) | |
2889 | return; | |
2890 | ||
2891 | mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter); | |
2892 | } | |
2893 | ||
bc77b240 TT |
2894 | static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv) |
2895 | { | |
2896 | struct mlx5_core_dev *mdev = priv->mdev; | |
2897 | struct mlx5_create_mkey_mbox_in *in; | |
2898 | struct mlx5_mkey_seg *mkc; | |
2899 | int inlen = sizeof(*in); | |
2900 | u64 npages = | |
2901 | mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS; | |
2902 | int err; | |
2903 | ||
2904 | in = mlx5_vzalloc(inlen); | |
2905 | if (!in) | |
2906 | return -ENOMEM; | |
2907 | ||
2908 | mkc = &in->seg; | |
2909 | mkc->status = MLX5_MKEY_STATUS_FREE; | |
2910 | mkc->flags = MLX5_PERM_UMR_EN | | |
2911 | MLX5_PERM_LOCAL_READ | | |
2912 | MLX5_PERM_LOCAL_WRITE | | |
2913 | MLX5_ACCESS_MODE_MTT; | |
2914 | ||
2915 | mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
2916 | mkc->flags_pd = cpu_to_be32(priv->pdn); | |
2917 | mkc->len = cpu_to_be64(npages << PAGE_SHIFT); | |
2918 | mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages)); | |
2919 | mkc->log2_page_size = PAGE_SHIFT; | |
2920 | ||
2921 | err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL, | |
2922 | NULL, NULL); | |
2923 | ||
2924 | kvfree(in); | |
2925 | ||
2926 | return err; | |
2927 | } | |
2928 | ||
f62b8bb8 AV |
2929 | static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev) |
2930 | { | |
2931 | struct net_device *netdev; | |
2932 | struct mlx5e_priv *priv; | |
3435ab59 | 2933 | int nch = mlx5e_get_max_num_channels(mdev); |
f62b8bb8 AV |
2934 | int err; |
2935 | ||
2936 | if (mlx5e_check_required_hca_cap(mdev)) | |
2937 | return NULL; | |
2938 | ||
08fb1dac SM |
2939 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
2940 | nch * MLX5E_MAX_NUM_TC, | |
2941 | nch); | |
f62b8bb8 AV |
2942 | if (!netdev) { |
2943 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
2944 | return NULL; | |
2945 | } | |
2946 | ||
936896e9 | 2947 | mlx5e_build_netdev_priv(mdev, netdev, nch); |
f62b8bb8 AV |
2948 | mlx5e_build_netdev(netdev); |
2949 | ||
2950 | netif_carrier_off(netdev); | |
2951 | ||
2952 | priv = netdev_priv(netdev); | |
2953 | ||
7bb29755 MF |
2954 | priv->wq = create_singlethread_workqueue("mlx5e"); |
2955 | if (!priv->wq) | |
2956 | goto err_free_netdev; | |
2957 | ||
0ba42241 | 2958 | err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false); |
f62b8bb8 | 2959 | if (err) { |
1f2a3003 | 2960 | mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err); |
7bb29755 | 2961 | goto err_destroy_wq; |
f62b8bb8 AV |
2962 | } |
2963 | ||
2964 | err = mlx5_core_alloc_pd(mdev, &priv->pdn); | |
2965 | if (err) { | |
1f2a3003 | 2966 | mlx5_core_err(mdev, "alloc pd failed, %d\n", err); |
f62b8bb8 AV |
2967 | goto err_unmap_free_uar; |
2968 | } | |
2969 | ||
8d7f9ecb | 2970 | err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn); |
3191e05f | 2971 | if (err) { |
1f2a3003 | 2972 | mlx5_core_err(mdev, "alloc td failed, %d\n", err); |
3191e05f AS |
2973 | goto err_dealloc_pd; |
2974 | } | |
2975 | ||
a606b0f6 | 2976 | err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey); |
f62b8bb8 | 2977 | if (err) { |
1f2a3003 | 2978 | mlx5_core_err(mdev, "create mkey failed, %d\n", err); |
3191e05f | 2979 | goto err_dealloc_transport_domain; |
f62b8bb8 AV |
2980 | } |
2981 | ||
bc77b240 TT |
2982 | err = mlx5e_create_umr_mkey(priv); |
2983 | if (err) { | |
2984 | mlx5_core_err(mdev, "create umr mkey failed, %d\n", err); | |
2985 | goto err_destroy_mkey; | |
2986 | } | |
2987 | ||
40ab6a6e | 2988 | err = mlx5e_create_tises(priv); |
5c50368f | 2989 | if (err) { |
40ab6a6e | 2990 | mlx5_core_warn(mdev, "create tises failed, %d\n", err); |
bc77b240 | 2991 | goto err_destroy_umr_mkey; |
5c50368f AS |
2992 | } |
2993 | ||
2994 | err = mlx5e_open_drop_rq(priv); | |
2995 | if (err) { | |
2996 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
40ab6a6e | 2997 | goto err_destroy_tises; |
5c50368f AS |
2998 | } |
2999 | ||
1da36696 | 3000 | err = mlx5e_create_rqts(priv); |
5c50368f | 3001 | if (err) { |
1da36696 | 3002 | mlx5_core_warn(mdev, "create rqts failed, %d\n", err); |
5c50368f AS |
3003 | goto err_close_drop_rq; |
3004 | } | |
3005 | ||
40ab6a6e | 3006 | err = mlx5e_create_tirs(priv); |
5c50368f | 3007 | if (err) { |
40ab6a6e | 3008 | mlx5_core_warn(mdev, "create tirs failed, %d\n", err); |
1da36696 | 3009 | goto err_destroy_rqts; |
5c50368f AS |
3010 | } |
3011 | ||
acff797c | 3012 | err = mlx5e_create_flow_steering(priv); |
5c50368f | 3013 | if (err) { |
acff797c | 3014 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); |
40ab6a6e | 3015 | goto err_destroy_tirs; |
5c50368f AS |
3016 | } |
3017 | ||
593cf338 RS |
3018 | mlx5e_create_q_counter(priv); |
3019 | ||
33cfaaa8 | 3020 | mlx5e_init_l2_addr(priv); |
5c50368f | 3021 | |
b3f63c3d MF |
3022 | mlx5e_vxlan_init(priv); |
3023 | ||
e8f887ac AV |
3024 | err = mlx5e_tc_init(priv); |
3025 | if (err) | |
593cf338 | 3026 | goto err_dealloc_q_counters; |
e8f887ac | 3027 | |
08fb1dac SM |
3028 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
3029 | mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets); | |
3030 | #endif | |
3031 | ||
f62b8bb8 AV |
3032 | err = register_netdev(netdev); |
3033 | if (err) { | |
1f2a3003 | 3034 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); |
e8f887ac | 3035 | goto err_tc_cleanup; |
f62b8bb8 AV |
3036 | } |
3037 | ||
01a14098 MF |
3038 | if (mlx5e_vxlan_allowed(mdev)) { |
3039 | rtnl_lock(); | |
b3f63c3d | 3040 | vxlan_get_rx_port(netdev); |
01a14098 MF |
3041 | rtnl_unlock(); |
3042 | } | |
b3f63c3d | 3043 | |
f62b8bb8 | 3044 | mlx5e_enable_async_events(priv); |
7bb29755 | 3045 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3046 | |
3047 | return priv; | |
3048 | ||
e8f887ac AV |
3049 | err_tc_cleanup: |
3050 | mlx5e_tc_cleanup(priv); | |
3051 | ||
593cf338 RS |
3052 | err_dealloc_q_counters: |
3053 | mlx5e_destroy_q_counter(priv); | |
acff797c | 3054 | mlx5e_destroy_flow_steering(priv); |
5c50368f | 3055 | |
40ab6a6e AS |
3056 | err_destroy_tirs: |
3057 | mlx5e_destroy_tirs(priv); | |
5c50368f | 3058 | |
1da36696 TT |
3059 | err_destroy_rqts: |
3060 | mlx5e_destroy_rqts(priv); | |
5c50368f AS |
3061 | |
3062 | err_close_drop_rq: | |
3063 | mlx5e_close_drop_rq(priv); | |
3064 | ||
40ab6a6e AS |
3065 | err_destroy_tises: |
3066 | mlx5e_destroy_tises(priv); | |
5c50368f | 3067 | |
bc77b240 TT |
3068 | err_destroy_umr_mkey: |
3069 | mlx5_core_destroy_mkey(mdev, &priv->umr_mkey); | |
3070 | ||
f62b8bb8 | 3071 | err_destroy_mkey: |
a606b0f6 | 3072 | mlx5_core_destroy_mkey(mdev, &priv->mkey); |
f62b8bb8 | 3073 | |
3191e05f | 3074 | err_dealloc_transport_domain: |
8d7f9ecb | 3075 | mlx5_core_dealloc_transport_domain(mdev, priv->tdn); |
3191e05f | 3076 | |
f62b8bb8 AV |
3077 | err_dealloc_pd: |
3078 | mlx5_core_dealloc_pd(mdev, priv->pdn); | |
3079 | ||
3080 | err_unmap_free_uar: | |
3081 | mlx5_unmap_free_uar(mdev, &priv->cq_uar); | |
3082 | ||
7bb29755 MF |
3083 | err_destroy_wq: |
3084 | destroy_workqueue(priv->wq); | |
3085 | ||
f62b8bb8 AV |
3086 | err_free_netdev: |
3087 | free_netdev(netdev); | |
3088 | ||
3089 | return NULL; | |
3090 | } | |
3091 | ||
3092 | static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv) | |
3093 | { | |
3094 | struct mlx5e_priv *priv = vpriv; | |
3095 | struct net_device *netdev = priv->netdev; | |
3096 | ||
9b37b07f AS |
3097 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); |
3098 | ||
7bb29755 | 3099 | queue_work(priv->wq, &priv->set_rx_mode_work); |
1cefa326 | 3100 | mlx5e_disable_async_events(priv); |
7bb29755 | 3101 | flush_workqueue(priv->wq); |
5fc7197d MD |
3102 | if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) { |
3103 | netif_device_detach(netdev); | |
3104 | mutex_lock(&priv->state_lock); | |
3105 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
3106 | mlx5e_close_locked(netdev); | |
3107 | mutex_unlock(&priv->state_lock); | |
3108 | } else { | |
3109 | unregister_netdev(netdev); | |
3110 | } | |
3111 | ||
e8f887ac | 3112 | mlx5e_tc_cleanup(priv); |
b3f63c3d | 3113 | mlx5e_vxlan_cleanup(priv); |
593cf338 | 3114 | mlx5e_destroy_q_counter(priv); |
acff797c | 3115 | mlx5e_destroy_flow_steering(priv); |
40ab6a6e | 3116 | mlx5e_destroy_tirs(priv); |
1da36696 | 3117 | mlx5e_destroy_rqts(priv); |
5c50368f | 3118 | mlx5e_close_drop_rq(priv); |
40ab6a6e | 3119 | mlx5e_destroy_tises(priv); |
bc77b240 | 3120 | mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey); |
a606b0f6 | 3121 | mlx5_core_destroy_mkey(priv->mdev, &priv->mkey); |
8d7f9ecb | 3122 | mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn); |
f62b8bb8 AV |
3123 | mlx5_core_dealloc_pd(priv->mdev, priv->pdn); |
3124 | mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); | |
7bb29755 MF |
3125 | cancel_delayed_work_sync(&priv->update_stats_work); |
3126 | destroy_workqueue(priv->wq); | |
5fc7197d MD |
3127 | |
3128 | if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) | |
3129 | free_netdev(netdev); | |
f62b8bb8 AV |
3130 | } |
3131 | ||
3132 | static void *mlx5e_get_netdev(void *vpriv) | |
3133 | { | |
3134 | struct mlx5e_priv *priv = vpriv; | |
3135 | ||
3136 | return priv->netdev; | |
3137 | } | |
3138 | ||
3139 | static struct mlx5_interface mlx5e_interface = { | |
3140 | .add = mlx5e_create_netdev, | |
3141 | .remove = mlx5e_destroy_netdev, | |
3142 | .event = mlx5e_async_event, | |
3143 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
3144 | .get_dev = mlx5e_get_netdev, | |
3145 | }; | |
3146 | ||
3147 | void mlx5e_init(void) | |
3148 | { | |
3149 | mlx5_register_interface(&mlx5e_interface); | |
3150 | } | |
3151 | ||
3152 | void mlx5e_cleanup(void) | |
3153 | { | |
3154 | mlx5_unregister_interface(&mlx5e_interface); | |
3155 | } |