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net/mlx4_en: Use HW counters for rx/tx bytes/packets in PF device
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/mlx5/flow_table.h>
34#include "en.h"
35
36struct mlx5e_rq_param {
37 u32 rqc[MLX5_ST_SZ_DW(rqc)];
38 struct mlx5_wq_param wq;
39};
40
41struct mlx5e_sq_param {
42 u32 sqc[MLX5_ST_SZ_DW(sqc)];
43 struct mlx5_wq_param wq;
44};
45
46struct mlx5e_cq_param {
47 u32 cqc[MLX5_ST_SZ_DW(cqc)];
48 struct mlx5_wq_param wq;
49 u16 eq_ix;
50};
51
52struct mlx5e_channel_param {
53 struct mlx5e_rq_param rq;
54 struct mlx5e_sq_param sq;
55 struct mlx5e_cq_param rx_cq;
56 struct mlx5e_cq_param tx_cq;
57};
58
59static void mlx5e_update_carrier(struct mlx5e_priv *priv)
60{
61 struct mlx5_core_dev *mdev = priv->mdev;
62 u8 port_state;
63
64 port_state = mlx5_query_vport_state(mdev,
65 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
66
67 if (port_state == VPORT_STATE_UP)
68 netif_carrier_on(priv->netdev);
69 else
70 netif_carrier_off(priv->netdev);
71}
72
73static void mlx5e_update_carrier_work(struct work_struct *work)
74{
75 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
76 update_carrier_work);
77
78 mutex_lock(&priv->state_lock);
79 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
80 mlx5e_update_carrier(priv);
81 mutex_unlock(&priv->state_lock);
82}
83
84void mlx5e_update_stats(struct mlx5e_priv *priv)
85{
86 struct mlx5_core_dev *mdev = priv->mdev;
87 struct mlx5e_vport_stats *s = &priv->stats.vport;
88 struct mlx5e_rq_stats *rq_stats;
89 struct mlx5e_sq_stats *sq_stats;
90 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
91 u32 *out;
92 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
93 u64 tx_offload_none;
94 int i, j;
95
96 out = mlx5_vzalloc(outlen);
97 if (!out)
98 return;
99
100 /* Collect firts the SW counters and then HW for consistency */
101 s->tso_packets = 0;
102 s->tso_bytes = 0;
103 s->tx_queue_stopped = 0;
104 s->tx_queue_wake = 0;
105 s->tx_queue_dropped = 0;
106 tx_offload_none = 0;
107 s->lro_packets = 0;
108 s->lro_bytes = 0;
109 s->rx_csum_none = 0;
110 s->rx_wqe_err = 0;
111 for (i = 0; i < priv->params.num_channels; i++) {
112 rq_stats = &priv->channel[i]->rq.stats;
113
114 s->lro_packets += rq_stats->lro_packets;
115 s->lro_bytes += rq_stats->lro_bytes;
116 s->rx_csum_none += rq_stats->csum_none;
117 s->rx_wqe_err += rq_stats->wqe_err;
118
119 for (j = 0; j < priv->num_tc; j++) {
120 sq_stats = &priv->channel[i]->sq[j].stats;
121
122 s->tso_packets += sq_stats->tso_packets;
123 s->tso_bytes += sq_stats->tso_bytes;
124 s->tx_queue_stopped += sq_stats->stopped;
125 s->tx_queue_wake += sq_stats->wake;
126 s->tx_queue_dropped += sq_stats->dropped;
127 tx_offload_none += sq_stats->csum_offload_none;
128 }
129 }
130
131 /* HW counters */
132 memset(in, 0, sizeof(in));
133
134 MLX5_SET(query_vport_counter_in, in, opcode,
135 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
136 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
137 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
138
139 memset(out, 0, outlen);
140
141 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
142 goto free_out;
143
144#define MLX5_GET_CTR(p, x) \
145 MLX5_GET64(query_vport_counter_out, p, x)
146
147 s->rx_error_packets =
148 MLX5_GET_CTR(out, received_errors.packets);
149 s->rx_error_bytes =
150 MLX5_GET_CTR(out, received_errors.octets);
151 s->tx_error_packets =
152 MLX5_GET_CTR(out, transmit_errors.packets);
153 s->tx_error_bytes =
154 MLX5_GET_CTR(out, transmit_errors.octets);
155
156 s->rx_unicast_packets =
157 MLX5_GET_CTR(out, received_eth_unicast.packets);
158 s->rx_unicast_bytes =
159 MLX5_GET_CTR(out, received_eth_unicast.octets);
160 s->tx_unicast_packets =
161 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
162 s->tx_unicast_bytes =
163 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
164
165 s->rx_multicast_packets =
166 MLX5_GET_CTR(out, received_eth_multicast.packets);
167 s->rx_multicast_bytes =
168 MLX5_GET_CTR(out, received_eth_multicast.octets);
169 s->tx_multicast_packets =
170 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
171 s->tx_multicast_bytes =
172 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
173
174 s->rx_broadcast_packets =
175 MLX5_GET_CTR(out, received_eth_broadcast.packets);
176 s->rx_broadcast_bytes =
177 MLX5_GET_CTR(out, received_eth_broadcast.octets);
178 s->tx_broadcast_packets =
179 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
180 s->tx_broadcast_bytes =
181 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
182
183 s->rx_packets =
184 s->rx_unicast_packets +
185 s->rx_multicast_packets +
186 s->rx_broadcast_packets;
187 s->rx_bytes =
188 s->rx_unicast_bytes +
189 s->rx_multicast_bytes +
190 s->rx_broadcast_bytes;
191 s->tx_packets =
192 s->tx_unicast_packets +
193 s->tx_multicast_packets +
194 s->tx_broadcast_packets;
195 s->tx_bytes =
196 s->tx_unicast_bytes +
197 s->tx_multicast_bytes +
198 s->tx_broadcast_bytes;
199
200 /* Update calculated offload counters */
201 s->tx_csum_offload = s->tx_packets - tx_offload_none;
202 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
203
204free_out:
205 kvfree(out);
206}
207
208static void mlx5e_update_stats_work(struct work_struct *work)
209{
210 struct delayed_work *dwork = to_delayed_work(work);
211 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
212 update_stats_work);
213 mutex_lock(&priv->state_lock);
214 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
215 mlx5e_update_stats(priv);
216 schedule_delayed_work(dwork,
217 msecs_to_jiffies(
218 MLX5E_UPDATE_STATS_INTERVAL));
219 }
220 mutex_unlock(&priv->state_lock);
221}
222
223static void __mlx5e_async_event(struct mlx5e_priv *priv,
224 enum mlx5_dev_event event)
225{
226 switch (event) {
227 case MLX5_DEV_EVENT_PORT_UP:
228 case MLX5_DEV_EVENT_PORT_DOWN:
229 schedule_work(&priv->update_carrier_work);
230 break;
231
232 default:
233 break;
234 }
235}
236
237static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
238 enum mlx5_dev_event event, unsigned long param)
239{
240 struct mlx5e_priv *priv = vpriv;
241
242 spin_lock(&priv->async_events_spinlock);
243 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
244 __mlx5e_async_event(priv, event);
245 spin_unlock(&priv->async_events_spinlock);
246}
247
248static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
249{
250 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
251}
252
253static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
254{
255 spin_lock_irq(&priv->async_events_spinlock);
256 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
257 spin_unlock_irq(&priv->async_events_spinlock);
258}
259
facc9699
SM		 260#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
261#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
262
f62b8bb8
AV		 263static int mlx5e_create_rq(struct mlx5e_channel *c,
264 struct mlx5e_rq_param *param,
265 struct mlx5e_rq *rq)
266{
267 struct mlx5e_priv *priv = c->priv;
268 struct mlx5_core_dev *mdev = priv->mdev;
269 void *rqc = param->rqc;
270 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
271 int wq_sz;
272 int err;
273 int i;
274
275 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
276 &rq->wq_ctrl);
277 if (err)
278 return err;
279
280 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
281
282 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
283 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
284 cpu_to_node(c->cpu));
285 if (!rq->skb) {
286 err = -ENOMEM;
287 goto err_rq_wq_destroy;
288 }
289
290 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
facc9699 291 MLX5E_SW2HW_MTU(priv->netdev->mtu);
fc11fbf9 292 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
f62b8bb8
AV		 293
294 for (i = 0; i < wq_sz; i++) {
295 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
fc11fbf9 296 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
f62b8bb8
AV		 297
298 wqe->data.lkey = c->mkey_be;
fc11fbf9
SM		 299 wqe->data.byte_count =
300 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
f62b8bb8
AV		 301 }
302
303 rq->pdev = c->pdev;
304 rq->netdev = c->netdev;
305 rq->channel = c;
306 rq->ix = c->ix;
307
308 return 0;
309
310err_rq_wq_destroy:
311 mlx5_wq_destroy(&rq->wq_ctrl);
312
313 return err;
314}
315
316static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
317{
318 kfree(rq->skb);
319 mlx5_wq_destroy(&rq->wq_ctrl);
320}
321
322static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
323{
324 struct mlx5e_channel *c = rq->channel;
325 struct mlx5e_priv *priv = c->priv;
326 struct mlx5_core_dev *mdev = priv->mdev;
327
328 void *in;
329 void *rqc;
330 void *wq;
331 int inlen;
332 int err;
333
334 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
335 sizeof(u64) * rq->wq_ctrl.buf.npages;
336 in = mlx5_vzalloc(inlen);
337 if (!in)
338 return -ENOMEM;
339
340 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
341 wq = MLX5_ADDR_OF(rqc, rqc, wq);
342
343 memcpy(rqc, param->rqc, sizeof(param->rqc));
344
345 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
346 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
347 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
348 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
349 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
350 PAGE_SHIFT);
351 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
352
353 mlx5_fill_page_array(&rq->wq_ctrl.buf,
354 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
355
7db22ffb 356 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 357
358 kvfree(in);
359
360 return err;
361}
362
363static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
364{
365 struct mlx5e_channel *c = rq->channel;
366 struct mlx5e_priv *priv = c->priv;
367 struct mlx5_core_dev *mdev = priv->mdev;
368
369 void *in;
370 void *rqc;
371 int inlen;
372 int err;
373
374 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
375 in = mlx5_vzalloc(inlen);
376 if (!in)
377 return -ENOMEM;
378
379 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
380
381 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
382 MLX5_SET(rqc, rqc, state, next_state);
383
7db22ffb 384 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 385
386 kvfree(in);
387
388 return err;
389}
390
391static void mlx5e_disable_rq(struct mlx5e_rq *rq)
392{
393 struct mlx5e_channel *c = rq->channel;
394 struct mlx5e_priv *priv = c->priv;
395 struct mlx5_core_dev *mdev = priv->mdev;
396
7db22ffb 397 mlx5_core_destroy_rq(mdev, rq->rqn);
f62b8bb8
AV		 398}
399
400static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
401{
402 struct mlx5e_channel *c = rq->channel;
403 struct mlx5e_priv *priv = c->priv;
404 struct mlx5_wq_ll *wq = &rq->wq;
405 int i;
406
407 for (i = 0; i < 1000; i++) {
408 if (wq->cur_sz >= priv->params.min_rx_wqes)
409 return 0;
410
411 msleep(20);
412 }
413
414 return -ETIMEDOUT;
415}
416
417static int mlx5e_open_rq(struct mlx5e_channel *c,
418 struct mlx5e_rq_param *param,
419 struct mlx5e_rq *rq)
420{
421 int err;
422
423 err = mlx5e_create_rq(c, param, rq);
424 if (err)
425 return err;
426
427 err = mlx5e_enable_rq(rq, param);
428 if (err)
429 goto err_destroy_rq;
430
431 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
432 if (err)
433 goto err_disable_rq;
434
435 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
12be4b21 436 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 437
438 return 0;
439
440err_disable_rq:
441 mlx5e_disable_rq(rq);
442err_destroy_rq:
443 mlx5e_destroy_rq(rq);
444
445 return err;
446}
447
448static void mlx5e_close_rq(struct mlx5e_rq *rq)
449{
450 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
451 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
452
453 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
454 while (!mlx5_wq_ll_is_empty(&rq->wq))
455 msleep(20);
456
457 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
458 napi_synchronize(&rq->channel->napi);
459
460 mlx5e_disable_rq(rq);
461 mlx5e_destroy_rq(rq);
462}
463
464static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
465{
466 kfree(sq->dma_fifo);
467 kfree(sq->skb);
468}
469
470static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
471{
472 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
473 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
474
475 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
476 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
477 numa);
478
479 if (!sq->skb || !sq->dma_fifo) {
480 mlx5e_free_sq_db(sq);
481 return -ENOMEM;
482 }
483
484 sq->dma_fifo_mask = df_sz - 1;
485
486 return 0;
487}
488
489static int mlx5e_create_sq(struct mlx5e_channel *c,
490 int tc,
491 struct mlx5e_sq_param *param,
492 struct mlx5e_sq *sq)
493{
494 struct mlx5e_priv *priv = c->priv;
495 struct mlx5_core_dev *mdev = priv->mdev;
496
497 void *sqc = param->sqc;
498 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
499 int err;
500
501 err = mlx5_alloc_map_uar(mdev, &sq->uar);
502 if (err)
503 return err;
504
505 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
506 &sq->wq_ctrl);
507 if (err)
508 goto err_unmap_free_uar;
509
510 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
511 sq->uar_map = sq->uar.map;
512 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
513
7ec0bb22
DC		 514 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
515 if (err)
f62b8bb8
AV		 516 goto err_sq_wq_destroy;
517
518 sq->txq = netdev_get_tx_queue(priv->netdev,
519 c->ix + tc * priv->params.num_channels);
520
521 sq->pdev = c->pdev;
522 sq->mkey_be = c->mkey_be;
523 sq->channel = c;
524 sq->tc = tc;
12be4b21 525 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 526
527 return 0;
528
529err_sq_wq_destroy:
530 mlx5_wq_destroy(&sq->wq_ctrl);
531
532err_unmap_free_uar:
533 mlx5_unmap_free_uar(mdev, &sq->uar);
534
535 return err;
536}
537
538static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
539{
540 struct mlx5e_channel *c = sq->channel;
541 struct mlx5e_priv *priv = c->priv;
542
543 mlx5e_free_sq_db(sq);
544 mlx5_wq_destroy(&sq->wq_ctrl);
545 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
546}
547
548static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
549{
550 struct mlx5e_channel *c = sq->channel;
551 struct mlx5e_priv *priv = c->priv;
552 struct mlx5_core_dev *mdev = priv->mdev;
553
554 void *in;
555 void *sqc;
556 void *wq;
557 int inlen;
558 int err;
559
560 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
561 sizeof(u64) * sq->wq_ctrl.buf.npages;
562 in = mlx5_vzalloc(inlen);
563 if (!in)
564 return -ENOMEM;
565
566 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
567 wq = MLX5_ADDR_OF(sqc, sqc, wq);
568
569 memcpy(sqc, param->sqc, sizeof(param->sqc));
570
571 MLX5_SET(sqc, sqc, user_index, sq->tc);
572 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
573 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
574 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
575 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
576 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
577
578 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
579 MLX5_SET(wq, wq, uar_page, sq->uar.index);
580 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
581 PAGE_SHIFT);
582 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
583
584 mlx5_fill_page_array(&sq->wq_ctrl.buf,
585 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
586
7db22ffb 587 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 588
589 kvfree(in);
590
591 return err;
592}
593
594static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
595{
596 struct mlx5e_channel *c = sq->channel;
597 struct mlx5e_priv *priv = c->priv;
598 struct mlx5_core_dev *mdev = priv->mdev;
599
600 void *in;
601 void *sqc;
602 int inlen;
603 int err;
604
605 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
606 in = mlx5_vzalloc(inlen);
607 if (!in)
608 return -ENOMEM;
609
610 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
611
612 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
613 MLX5_SET(sqc, sqc, state, next_state);
614
7db22ffb 615 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 616
617 kvfree(in);
618
619 return err;
620}
621
622static void mlx5e_disable_sq(struct mlx5e_sq *sq)
623{
624 struct mlx5e_channel *c = sq->channel;
625 struct mlx5e_priv *priv = c->priv;
626 struct mlx5_core_dev *mdev = priv->mdev;
627
7db22ffb 628 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 629}
630
631static int mlx5e_open_sq(struct mlx5e_channel *c,
632 int tc,
633 struct mlx5e_sq_param *param,
634 struct mlx5e_sq *sq)
635{
636 int err;
637
638 err = mlx5e_create_sq(c, tc, param, sq);
639 if (err)
640 return err;
641
642 err = mlx5e_enable_sq(sq, param);
643 if (err)
644 goto err_destroy_sq;
645
646 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
647 if (err)
648 goto err_disable_sq;
649
650 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
651 netdev_tx_reset_queue(sq->txq);
652 netif_tx_start_queue(sq->txq);
653
654 return 0;
655
656err_disable_sq:
657 mlx5e_disable_sq(sq);
658err_destroy_sq:
659 mlx5e_destroy_sq(sq);
660
661 return err;
662}
663
664static inline void netif_tx_disable_queue(struct netdev_queue *txq)
665{
666 __netif_tx_lock_bh(txq);
667 netif_tx_stop_queue(txq);
668 __netif_tx_unlock_bh(txq);
669}
670
671static void mlx5e_close_sq(struct mlx5e_sq *sq)
672{
673 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
674 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
675 netif_tx_disable_queue(sq->txq);
676
677 /* ensure hw is notified of all pending wqes */
678 if (mlx5e_sq_has_room_for(sq, 1))
12be4b21 679 mlx5e_send_nop(sq, true);
f62b8bb8
AV		 680
681 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
682 while (sq->cc != sq->pc) /* wait till sq is empty */
683 msleep(20);
684
685 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
686 napi_synchronize(&sq->channel->napi);
687
688 mlx5e_disable_sq(sq);
689 mlx5e_destroy_sq(sq);
690}
691
692static int mlx5e_create_cq(struct mlx5e_channel *c,
693 struct mlx5e_cq_param *param,
694 struct mlx5e_cq *cq)
695{
696 struct mlx5e_priv *priv = c->priv;
697 struct mlx5_core_dev *mdev = priv->mdev;
698 struct mlx5_core_cq *mcq = &cq->mcq;
699 int eqn_not_used;
700 int irqn;
701 int err;
702 u32 i;
703
704 param->wq.numa = cpu_to_node(c->cpu);
705 param->eq_ix = c->ix;
706
707 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
708 &cq->wq_ctrl);
709 if (err)
710 return err;
711
712 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
713
714 cq->napi = &c->napi;
715
716 mcq->cqe_sz = 64;
717 mcq->set_ci_db = cq->wq_ctrl.db.db;
718 mcq->arm_db = cq->wq_ctrl.db.db + 1;
719 *mcq->set_ci_db = 0;
720 *mcq->arm_db = 0;
721 mcq->vector = param->eq_ix;
722 mcq->comp = mlx5e_completion_event;
723 mcq->event = mlx5e_cq_error_event;
724 mcq->irqn = irqn;
725 mcq->uar = &priv->cq_uar;
726
727 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
728 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
729
730 cqe->op_own = 0xf1;
731 }
732
733 cq->channel = c;
734
735 return 0;
736}
737
738static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
739{
740 mlx5_wq_destroy(&cq->wq_ctrl);
741}
742
743static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
744{
745 struct mlx5e_channel *c = cq->channel;
746 struct mlx5e_priv *priv = c->priv;
747 struct mlx5_core_dev *mdev = priv->mdev;
748 struct mlx5_core_cq *mcq = &cq->mcq;
749
750 void *in;
751 void *cqc;
752 int inlen;
753 int irqn_not_used;
754 int eqn;
755 int err;
756
757 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
758 sizeof(u64) * cq->wq_ctrl.buf.npages;
759 in = mlx5_vzalloc(inlen);
760 if (!in)
761 return -ENOMEM;
762
763 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
764
765 memcpy(cqc, param->cqc, sizeof(param->cqc));
766
767 mlx5_fill_page_array(&cq->wq_ctrl.buf,
768 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
769
770 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
771
772 MLX5_SET(cqc, cqc, c_eqn, eqn);
773 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
774 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
775 PAGE_SHIFT);
776 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
777
778 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
779
780 kvfree(in);
781
782 if (err)
783 return err;
784
785 mlx5e_cq_arm(cq);
786
787 return 0;
788}
789
790static void mlx5e_disable_cq(struct mlx5e_cq *cq)
791{
792 struct mlx5e_channel *c = cq->channel;
793 struct mlx5e_priv *priv = c->priv;
794 struct mlx5_core_dev *mdev = priv->mdev;
795
796 mlx5_core_destroy_cq(mdev, &cq->mcq);
797}
798
799static int mlx5e_open_cq(struct mlx5e_channel *c,
800 struct mlx5e_cq_param *param,
801 struct mlx5e_cq *cq,
802 u16 moderation_usecs,
803 u16 moderation_frames)
804{
805 int err;
806 struct mlx5e_priv *priv = c->priv;
807 struct mlx5_core_dev *mdev = priv->mdev;
808
809 err = mlx5e_create_cq(c, param, cq);
810 if (err)
811 return err;
812
813 err = mlx5e_enable_cq(cq, param);
814 if (err)
815 goto err_destroy_cq;
816
817 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
818 moderation_usecs,
819 moderation_frames);
820 if (err)
821 goto err_destroy_cq;
822
823 return 0;
824
825err_destroy_cq:
826 mlx5e_destroy_cq(cq);
827
828 return err;
829}
830
831static void mlx5e_close_cq(struct mlx5e_cq *cq)
832{
833 mlx5e_disable_cq(cq);
834 mlx5e_destroy_cq(cq);
835}
836
837static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
838{
839 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
840}
841
842static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
843 struct mlx5e_channel_param *cparam)
844{
845 struct mlx5e_priv *priv = c->priv;
846 int err;
847 int tc;
848
849 for (tc = 0; tc < c->num_tc; tc++) {
850 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
851 priv->params.tx_cq_moderation_usec,
852 priv->params.tx_cq_moderation_pkts);
853 if (err)
854 goto err_close_tx_cqs;
855
856 c->sq[tc].cq.sqrq = &c->sq[tc];
857 }
858
859 return 0;
860
861err_close_tx_cqs:
862 for (tc--; tc >= 0; tc--)
863 mlx5e_close_cq(&c->sq[tc].cq);
864
865 return err;
866}
867
868static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
869{
870 int tc;
871
872 for (tc = 0; tc < c->num_tc; tc++)
873 mlx5e_close_cq(&c->sq[tc].cq);
874}
875
876static int mlx5e_open_sqs(struct mlx5e_channel *c,
877 struct mlx5e_channel_param *cparam)
878{
879 int err;
880 int tc;
881
882 for (tc = 0; tc < c->num_tc; tc++) {
883 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
884 if (err)
885 goto err_close_sqs;
886 }
887
888 return 0;
889
890err_close_sqs:
891 for (tc--; tc >= 0; tc--)
892 mlx5e_close_sq(&c->sq[tc]);
893
894 return err;
895}
896
897static void mlx5e_close_sqs(struct mlx5e_channel *c)
898{
899 int tc;
900
901 for (tc = 0; tc < c->num_tc; tc++)
902 mlx5e_close_sq(&c->sq[tc]);
903}
904
905static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
906 struct mlx5e_channel_param *cparam,
907 struct mlx5e_channel **cp)
908{
909 struct net_device *netdev = priv->netdev;
910 int cpu = mlx5e_get_cpu(priv, ix);
911 struct mlx5e_channel *c;
912 int err;
913
914 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
915 if (!c)
916 return -ENOMEM;
917
918 c->priv = priv;
919 c->ix = ix;
920 c->cpu = cpu;
921 c->pdev = &priv->mdev->pdev->dev;
922 c->netdev = priv->netdev;
923 c->mkey_be = cpu_to_be32(priv->mr.key);
924 c->num_tc = priv->num_tc;
925
926 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
927
928 err = mlx5e_open_tx_cqs(c, cparam);
929 if (err)
930 goto err_napi_del;
931
932 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
933 priv->params.rx_cq_moderation_usec,
934 priv->params.rx_cq_moderation_pkts);
935 if (err)
936 goto err_close_tx_cqs;
937 c->rq.cq.sqrq = &c->rq;
938
939 napi_enable(&c->napi);
940
941 err = mlx5e_open_sqs(c, cparam);
942 if (err)
943 goto err_disable_napi;
944
945 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
946 if (err)
947 goto err_close_sqs;
948
949 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
950 *cp = c;
951
952 return 0;
953
954err_close_sqs:
955 mlx5e_close_sqs(c);
956
957err_disable_napi:
958 napi_disable(&c->napi);
959 mlx5e_close_cq(&c->rq.cq);
960
961err_close_tx_cqs:
962 mlx5e_close_tx_cqs(c);
963
964err_napi_del:
965 netif_napi_del(&c->napi);
966 kfree(c);
967
968 return err;
969}
970
971static void mlx5e_close_channel(struct mlx5e_channel *c)
972{
973 mlx5e_close_rq(&c->rq);
974 mlx5e_close_sqs(c);
975 napi_disable(&c->napi);
976 mlx5e_close_cq(&c->rq.cq);
977 mlx5e_close_tx_cqs(c);
978 netif_napi_del(&c->napi);
979 kfree(c);
980}
981
982static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
983 struct mlx5e_rq_param *param)
984{
985 void *rqc = param->rqc;
986 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
987
988 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
989 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
990 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
991 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
992 MLX5_SET(wq, wq, pd, priv->pdn);
993
994 param->wq.numa = dev_to_node(&priv->mdev->pdev->dev);
995 param->wq.linear = 1;
996}
997
998static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
999 struct mlx5e_sq_param *param)
1000{
1001 void *sqc = param->sqc;
1002 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1003
1004 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1005 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1006 MLX5_SET(wq, wq, pd, priv->pdn);
1007
1008 param->wq.numa = dev_to_node(&priv->mdev->pdev->dev);
1009}
1010
1011static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1012 struct mlx5e_cq_param *param)
1013{
1014 void *cqc = param->cqc;
1015
1016 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1017}
1018
1019static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1020 struct mlx5e_cq_param *param)
1021{
1022 void *cqc = param->cqc;
1023
1024 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1025
1026 mlx5e_build_common_cq_param(priv, param);
1027}
1028
1029static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1030 struct mlx5e_cq_param *param)
1031{
1032 void *cqc = param->cqc;
1033
1034 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1035
1036 mlx5e_build_common_cq_param(priv, param);
1037}
1038
1039static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1040 struct mlx5e_channel_param *cparam)
1041{
1042 memset(cparam, 0, sizeof(*cparam));
1043
1044 mlx5e_build_rq_param(priv, &cparam->rq);
1045 mlx5e_build_sq_param(priv, &cparam->sq);
1046 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1047 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1048}
1049
1050static int mlx5e_open_channels(struct mlx5e_priv *priv)
1051{
1052 struct mlx5e_channel_param cparam;
1053 int err;
1054 int i;
1055 int j;
1056
1057 priv->channel = kcalloc(priv->params.num_channels,
1058 sizeof(struct mlx5e_channel *), GFP_KERNEL);
1059 if (!priv->channel)
1060 return -ENOMEM;
1061
1062 mlx5e_build_channel_param(priv, &cparam);
1063 for (i = 0; i < priv->params.num_channels; i++) {
1064 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1065 if (err)
1066 goto err_close_channels;
1067 }
1068
1069 for (j = 0; j < priv->params.num_channels; j++) {
1070 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1071 if (err)
1072 goto err_close_channels;
1073 }
1074
1075 return 0;
1076
1077err_close_channels:
1078 for (i--; i >= 0; i--)
1079 mlx5e_close_channel(priv->channel[i]);
1080
1081 kfree(priv->channel);
1082
1083 return err;
1084}
1085
1086static void mlx5e_close_channels(struct mlx5e_priv *priv)
1087{
1088 int i;
1089
1090 for (i = 0; i < priv->params.num_channels; i++)
1091 mlx5e_close_channel(priv->channel[i]);
1092
1093 kfree(priv->channel);
1094}
1095
1096static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1097{
1098 struct mlx5_core_dev *mdev = priv->mdev;
1099 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1100 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1101
1102 memset(in, 0, sizeof(in));
1103
1104 MLX5_SET(tisc, tisc, prio, tc);
3191e05f 1105 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
f62b8bb8 1106
7db22ffb 1107 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
f62b8bb8
AV		 1108}
1109
1110static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1111{
7db22ffb 1112 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
f62b8bb8
AV		 1113}
1114
1115static int mlx5e_open_tises(struct mlx5e_priv *priv)
1116{
1117 int num_tc = priv->num_tc;
1118 int err;
1119 int tc;
1120
1121 for (tc = 0; tc < num_tc; tc++) {
1122 err = mlx5e_open_tis(priv, tc);
1123 if (err)
1124 goto err_close_tises;
1125 }
1126
1127 return 0;
1128
1129err_close_tises:
1130 for (tc--; tc >= 0; tc--)
1131 mlx5e_close_tis(priv, tc);
1132
1133 return err;
1134}
1135
1136static void mlx5e_close_tises(struct mlx5e_priv *priv)
1137{
1138 int num_tc = priv->num_tc;
1139 int tc;
1140
1141 for (tc = 0; tc < num_tc; tc++)
1142 mlx5e_close_tis(priv, tc);
1143}
1144
1145static int mlx5e_open_rqt(struct mlx5e_priv *priv)
1146{
1147 struct mlx5_core_dev *mdev = priv->mdev;
1148 u32 *in;
1149 u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1150 void *rqtc;
1151 int inlen;
1152 int err;
1153 int sz;
1154 int i;
1155
1156 sz = 1 << priv->params.rx_hash_log_tbl_sz;
1157
1158 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1159 in = mlx5_vzalloc(inlen);
1160 if (!in)
1161 return -ENOMEM;
1162
1163 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1164
1165 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1166 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1167
1168 for (i = 0; i < sz; i++) {
1169 int ix = i % priv->params.num_channels;
1170
1171 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1172 }
1173
1174 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1175
1176 memset(out, 0, sizeof(out));
1177 err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1178 if (!err)
1179 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1180
1181 kvfree(in);
1182
1183 return err;
1184}
1185
1186static void mlx5e_close_rqt(struct mlx5e_priv *priv)
1187{
1188 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1189 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1190
1191 memset(in, 0, sizeof(in));
1192
1193 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1194 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1195
1196 mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1197 sizeof(out));
1198}
1199
1200static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1201{
1202 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1203
3191e05f
AS		 1204 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1205
f62b8bb8
AV		 1206#define ROUGH_MAX_L2_L3_HDR_SZ 256
1207
1208#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1209 MLX5_HASH_FIELD_SEL_DST_IP)
1210
1211#define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
1212 MLX5_HASH_FIELD_SEL_DST_IP |\
1213 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1214 MLX5_HASH_FIELD_SEL_L4_DPORT)
1215
1216 if (priv->params.lro_en) {
1217 MLX5_SET(tirc, tirc, lro_enable_mask,
1218 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1219 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1220 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1221 (priv->params.lro_wqe_sz -
1222 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1223 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1224 MLX5_CAP_ETH(priv->mdev,
1225 lro_timer_supported_periods[3]));
1226 }
1227
1228 switch (tt) {
1229 case MLX5E_TT_ANY:
1230 MLX5_SET(tirc, tirc, disp_type,
1231 MLX5_TIRC_DISP_TYPE_DIRECT);
1232 MLX5_SET(tirc, tirc, inline_rqn,
1233 priv->channel[0]->rq.rqn);
1234 break;
1235 default:
1236 MLX5_SET(tirc, tirc, disp_type,
1237 MLX5_TIRC_DISP_TYPE_INDIRECT);
1238 MLX5_SET(tirc, tirc, indirect_table,
1239 priv->rqtn);
1240 MLX5_SET(tirc, tirc, rx_hash_fn,
1241 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1242 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1243 netdev_rss_key_fill(MLX5_ADDR_OF(tirc, tirc,
1244 rx_hash_toeplitz_key),
1245 MLX5_FLD_SZ_BYTES(tirc,
1246 rx_hash_toeplitz_key));
1247 break;
1248 }
1249
1250 switch (tt) {
1251 case MLX5E_TT_IPV4_TCP:
1252 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1253 MLX5_L3_PROT_TYPE_IPV4);
1254 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1255 MLX5_L4_PROT_TYPE_TCP);
1256 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1257 MLX5_HASH_ALL);
1258 break;
1259
1260 case MLX5E_TT_IPV6_TCP:
1261 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1262 MLX5_L3_PROT_TYPE_IPV6);
1263 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1264 MLX5_L4_PROT_TYPE_TCP);
1265 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1266 MLX5_HASH_ALL);
1267 break;
1268
1269 case MLX5E_TT_IPV4_UDP:
1270 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1271 MLX5_L3_PROT_TYPE_IPV4);
1272 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1273 MLX5_L4_PROT_TYPE_UDP);
1274 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1275 MLX5_HASH_ALL);
1276 break;
1277
1278 case MLX5E_TT_IPV6_UDP:
1279 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1280 MLX5_L3_PROT_TYPE_IPV6);
1281 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1282 MLX5_L4_PROT_TYPE_UDP);
1283 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1284 MLX5_HASH_ALL);
1285 break;
1286
1287 case MLX5E_TT_IPV4:
1288 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1289 MLX5_L3_PROT_TYPE_IPV4);
1290 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1291 MLX5_HASH_IP);
1292 break;
1293
1294 case MLX5E_TT_IPV6:
1295 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1296 MLX5_L3_PROT_TYPE_IPV6);
1297 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1298 MLX5_HASH_IP);
1299 break;
1300 }
1301}
1302
1303static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1304{
1305 struct mlx5_core_dev *mdev = priv->mdev;
1306 u32 *in;
1307 void *tirc;
1308 int inlen;
1309 int err;
1310
1311 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1312 in = mlx5_vzalloc(inlen);
1313 if (!in)
1314 return -ENOMEM;
1315
1316 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1317
1318 mlx5e_build_tir_ctx(priv, tirc, tt);
1319
7db22ffb 1320 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1321
1322 kvfree(in);
1323
1324 return err;
1325}
1326
1327static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1328{
7db22ffb 1329 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1330}
1331
1332static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1333{
1334 int err;
1335 int i;
1336
1337 for (i = 0; i < MLX5E_NUM_TT; i++) {
1338 err = mlx5e_open_tir(priv, i);
1339 if (err)
1340 goto err_close_tirs;
1341 }
1342
1343 return 0;
1344
1345err_close_tirs:
1346 for (i--; i >= 0; i--)
1347 mlx5e_close_tir(priv, i);
1348
1349 return err;
1350}
1351
1352static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1353{
1354 int i;
1355
1356 for (i = 0; i < MLX5E_NUM_TT; i++)
1357 mlx5e_close_tir(priv, i);
1358}
1359
facc9699 1360static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
f62b8bb8
AV		 1361{
1362 struct mlx5e_priv *priv = netdev_priv(netdev);
1363 struct mlx5_core_dev *mdev = priv->mdev;
facc9699
SM		 1364 int hw_mtu;
1365 int err;
1366
1367 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1368 if (err)
1369 return err;
1370
1371 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1372
1373 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1374 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1375 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1376
1377 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1378 return 0;
1379}
1380
1381int mlx5e_open_locked(struct net_device *netdev)
1382{
1383 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8
AV		 1384 int num_txqs;
1385 int err;
1386
1387 num_txqs = roundup_pow_of_two(priv->params.num_channels) *
1388 priv->params.num_tc;
1389 netif_set_real_num_tx_queues(netdev, num_txqs);
1390 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1391
facc9699
SM		 1392 err = mlx5e_set_dev_port_mtu(netdev);
1393 if (err)
f62b8bb8 1394 return err;
f62b8bb8
AV		 1395
1396 err = mlx5e_open_tises(priv);
1397 if (err) {
1398 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1399 __func__, err);
1400 return err;
1401 }
1402
1403 err = mlx5e_open_channels(priv);
1404 if (err) {
1405 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1406 __func__, err);
1407 goto err_close_tises;
1408 }
1409
1410 err = mlx5e_open_rqt(priv);
1411 if (err) {
1412 netdev_err(netdev, "%s: mlx5e_open_rqt failed, %d\n",
1413 __func__, err);
1414 goto err_close_channels;
1415 }
1416
1417 err = mlx5e_open_tirs(priv);
1418 if (err) {
1419 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1420 __func__, err);
1421 goto err_close_rqls;
1422 }
1423
1424 err = mlx5e_open_flow_table(priv);
1425 if (err) {
1426 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1427 __func__, err);
1428 goto err_close_tirs;
1429 }
1430
1431 err = mlx5e_add_all_vlan_rules(priv);
1432 if (err) {
1433 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1434 __func__, err);
1435 goto err_close_flow_table;
1436 }
1437
1438 mlx5e_init_eth_addr(priv);
1439
1440 set_bit(MLX5E_STATE_OPENED, &priv->state);
1441
1442 mlx5e_update_carrier(priv);
1443 mlx5e_set_rx_mode_core(priv);
1444
1445 schedule_delayed_work(&priv->update_stats_work, 0);
1446 return 0;
1447
1448err_close_flow_table:
1449 mlx5e_close_flow_table(priv);
1450
1451err_close_tirs:
1452 mlx5e_close_tirs(priv);
1453
1454err_close_rqls:
1455 mlx5e_close_rqt(priv);
1456
1457err_close_channels:
1458 mlx5e_close_channels(priv);
1459
1460err_close_tises:
1461 mlx5e_close_tises(priv);
1462
1463 return err;
1464}
1465
1466static int mlx5e_open(struct net_device *netdev)
1467{
1468 struct mlx5e_priv *priv = netdev_priv(netdev);
1469 int err;
1470
1471 mutex_lock(&priv->state_lock);
1472 err = mlx5e_open_locked(netdev);
1473 mutex_unlock(&priv->state_lock);
1474
1475 return err;
1476}
1477
1478int mlx5e_close_locked(struct net_device *netdev)
1479{
1480 struct mlx5e_priv *priv = netdev_priv(netdev);
1481
1482 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1483
1484 mlx5e_set_rx_mode_core(priv);
1485 mlx5e_del_all_vlan_rules(priv);
1486 netif_carrier_off(priv->netdev);
1487 mlx5e_close_flow_table(priv);
1488 mlx5e_close_tirs(priv);
1489 mlx5e_close_rqt(priv);
1490 mlx5e_close_channels(priv);
1491 mlx5e_close_tises(priv);
1492
1493 return 0;
1494}
1495
1496static int mlx5e_close(struct net_device *netdev)
1497{
1498 struct mlx5e_priv *priv = netdev_priv(netdev);
1499 int err;
1500
1501 mutex_lock(&priv->state_lock);
1502 err = mlx5e_close_locked(netdev);
1503 mutex_unlock(&priv->state_lock);
1504
1505 return err;
1506}
1507
1508int mlx5e_update_priv_params(struct mlx5e_priv *priv,
1509 struct mlx5e_params *new_params)
1510{
1511 int err = 0;
1512 int was_opened;
1513
1514 WARN_ON(!mutex_is_locked(&priv->state_lock));
1515
1516 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1517 if (was_opened)
1518 mlx5e_close_locked(priv->netdev);
1519
1520 priv->params = *new_params;
1521
1522 if (was_opened)
1523 err = mlx5e_open_locked(priv->netdev);
1524
1525 return err;
1526}
1527
1528static struct rtnl_link_stats64 *
1529mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1530{
1531 struct mlx5e_priv *priv = netdev_priv(dev);
1532 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1533
1534 stats->rx_packets = vstats->rx_packets;
1535 stats->rx_bytes = vstats->rx_bytes;
1536 stats->tx_packets = vstats->tx_packets;
1537 stats->tx_bytes = vstats->tx_bytes;
1538 stats->multicast = vstats->rx_multicast_packets +
1539 vstats->tx_multicast_packets;
1540 stats->tx_errors = vstats->tx_error_packets;
1541 stats->rx_errors = vstats->rx_error_packets;
1542 stats->tx_dropped = vstats->tx_queue_dropped;
1543 stats->rx_crc_errors = 0;
1544 stats->rx_length_errors = 0;
1545
1546 return stats;
1547}
1548
1549static void mlx5e_set_rx_mode(struct net_device *dev)
1550{
1551 struct mlx5e_priv *priv = netdev_priv(dev);
1552
1553 schedule_work(&priv->set_rx_mode_work);
1554}
1555
1556static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1557{
1558 struct mlx5e_priv *priv = netdev_priv(netdev);
1559 struct sockaddr *saddr = addr;
1560
1561 if (!is_valid_ether_addr(saddr->sa_data))
1562 return -EADDRNOTAVAIL;
1563
1564 netif_addr_lock_bh(netdev);
1565 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1566 netif_addr_unlock_bh(netdev);
1567
1568 schedule_work(&priv->set_rx_mode_work);
1569
1570 return 0;
1571}
1572
1573static int mlx5e_set_features(struct net_device *netdev,
1574 netdev_features_t features)
1575{
1576 struct mlx5e_priv *priv = netdev_priv(netdev);
1577 netdev_features_t changes = features ^ netdev->features;
1578 struct mlx5e_params new_params;
1579 bool update_params = false;
1580
1581 mutex_lock(&priv->state_lock);
1582 new_params = priv->params;
1583
1584 if (changes & NETIF_F_LRO) {
1585 new_params.lro_en = !!(features & NETIF_F_LRO);
1586 update_params = true;
1587 }
1588
1589 if (update_params)
1590 mlx5e_update_priv_params(priv, &new_params);
1591
1592 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1593 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1594 mlx5e_enable_vlan_filter(priv);
1595 else
1596 mlx5e_disable_vlan_filter(priv);
1597 }
1598
1599 mutex_unlock(&priv->state_lock);
1600
1601 return 0;
1602}
1603
1604static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1605{
1606 struct mlx5e_priv *priv = netdev_priv(netdev);
1607 struct mlx5_core_dev *mdev = priv->mdev;
1608 int max_mtu;
facc9699 1609 int err;
f62b8bb8 1610
facc9699 1611 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 1612
facc9699
SM		 1613 if (new_mtu > max_mtu) {
1614 netdev_err(netdev,
1615 "%s: Bad MTU (%d) > (%d) Max\n",
1616 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 1617 return -EINVAL;
1618 }
1619
1620 mutex_lock(&priv->state_lock);
1621 netdev->mtu = new_mtu;
1622 err = mlx5e_update_priv_params(priv, &priv->params);
1623 mutex_unlock(&priv->state_lock);
1624
1625 return err;
1626}
1627
1628static struct net_device_ops mlx5e_netdev_ops = {
1629 .ndo_open = mlx5e_open,
1630 .ndo_stop = mlx5e_close,
1631 .ndo_start_xmit = mlx5e_xmit,
1632 .ndo_get_stats64 = mlx5e_get_stats,
1633 .ndo_set_rx_mode = mlx5e_set_rx_mode,
1634 .ndo_set_mac_address = mlx5e_set_mac,
1635 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
1636 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
1637 .ndo_set_features = mlx5e_set_features,
1638 .ndo_change_mtu = mlx5e_change_mtu,
1639};
1640
1641static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1642{
1643 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1644 return -ENOTSUPP;
1645 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1646 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1647 !MLX5_CAP_ETH(mdev, csum_cap) ||
1648 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1649 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 1650 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1651 MLX5_CAP_FLOWTABLE(mdev,
1652 flow_table_properties_nic_receive.max_ft_level)
1653 < 3) {
f62b8bb8
AV		 1654 mlx5_core_warn(mdev,
1655 "Not creating net device, some required device capabilities are missing\n");
1656 return -ENOTSUPP;
1657 }
1658 return 0;
1659}
1660
1661static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1662 struct net_device *netdev,
1663 int num_comp_vectors)
1664{
1665 struct mlx5e_priv *priv = netdev_priv(netdev);
1666
1667 priv->params.log_sq_size =
1668 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1669 priv->params.log_rq_size =
1670 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1671 priv->params.rx_cq_moderation_usec =
1672 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1673 priv->params.rx_cq_moderation_pkts =
1674 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1675 priv->params.tx_cq_moderation_usec =
1676 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1677 priv->params.tx_cq_moderation_pkts =
1678 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1679 priv->params.min_rx_wqes =
1680 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1681 priv->params.rx_hash_log_tbl_sz =
1682 (order_base_2(num_comp_vectors) >
1683 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1684 order_base_2(num_comp_vectors) :
1685 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1686 priv->params.num_tc = 1;
1687 priv->params.default_vlan_prio = 0;
1688
1689 priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1690 priv->params.lro_wqe_sz =
1691 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1692
1693 priv->mdev = mdev;
1694 priv->netdev = netdev;
1695 priv->params.num_channels = num_comp_vectors;
1696 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
1697 priv->queue_mapping_channel_mask =
1698 roundup_pow_of_two(num_comp_vectors) - 1;
1699 priv->num_tc = priv->params.num_tc;
1700 priv->default_vlan_prio = priv->params.default_vlan_prio;
1701
1702 spin_lock_init(&priv->async_events_spinlock);
1703 mutex_init(&priv->state_lock);
1704
1705 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1706 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1707 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1708}
1709
1710static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1711{
1712 struct mlx5e_priv *priv = netdev_priv(netdev);
1713
d18a9470 1714 mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
f62b8bb8
AV		 1715}
1716
1717static void mlx5e_build_netdev(struct net_device *netdev)
1718{
1719 struct mlx5e_priv *priv = netdev_priv(netdev);
1720 struct mlx5_core_dev *mdev = priv->mdev;
1721
1722 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1723
1724 if (priv->num_tc > 1) {
1725 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1726 mlx5e_netdev_ops.ndo_start_xmit = mlx5e_xmit_multi_tc;
1727 }
1728
1729 netdev->netdev_ops = &mlx5e_netdev_ops;
1730 netdev->watchdog_timeo = 15 * HZ;
1731
1732 netdev->ethtool_ops = &mlx5e_ethtool_ops;
1733
12be4b21 1734 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 1735 netdev->vlan_features |= NETIF_F_IP_CSUM;
1736 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1737 netdev->vlan_features |= NETIF_F_GRO;
1738 netdev->vlan_features |= NETIF_F_TSO;
1739 netdev->vlan_features |= NETIF_F_TSO6;
1740 netdev->vlan_features |= NETIF_F_RXCSUM;
1741 netdev->vlan_features |= NETIF_F_RXHASH;
1742
1743 if (!!MLX5_CAP_ETH(mdev, lro_cap))
1744 netdev->vlan_features |= NETIF_F_LRO;
1745
1746 netdev->hw_features = netdev->vlan_features;
f62b8bb8
AV		 1747 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1748 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1749
1750 netdev->features = netdev->hw_features;
1751 if (!priv->params.lro_en)
1752 netdev->features &= ~NETIF_F_LRO;
1753
1754 netdev->features |= NETIF_F_HIGHDMA;
1755
1756 netdev->priv_flags |= IFF_UNICAST_FLT;
1757
1758 mlx5e_set_netdev_dev_addr(netdev);
1759}
1760
1761static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1762 struct mlx5_core_mr *mr)
1763{
1764 struct mlx5_core_dev *mdev = priv->mdev;
1765 struct mlx5_create_mkey_mbox_in *in;
1766 int err;
1767
1768 in = mlx5_vzalloc(sizeof(*in));
1769 if (!in)
1770 return -ENOMEM;
1771
1772 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1773 MLX5_PERM_LOCAL_READ |
1774 MLX5_ACCESS_MODE_PA;
1775 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1776 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1777
1778 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1779 NULL);
1780
1781 kvfree(in);
1782
1783 return err;
1784}
1785
1786static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1787{
1788 struct net_device *netdev;
1789 struct mlx5e_priv *priv;
1790 int ncv = mdev->priv.eq_table.num_comp_vectors;
1791 int err;
1792
1793 if (mlx5e_check_required_hca_cap(mdev))
1794 return NULL;
1795
1796 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
1797 roundup_pow_of_two(ncv) * MLX5E_MAX_NUM_TC,
1798 ncv);
1799 if (!netdev) {
1800 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1801 return NULL;
1802 }
1803
1804 mlx5e_build_netdev_priv(mdev, netdev, ncv);
1805 mlx5e_build_netdev(netdev);
1806
1807 netif_carrier_off(netdev);
1808
1809 priv = netdev_priv(netdev);
1810
1811 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
1812 if (err) {
1813 netdev_err(netdev, "%s: mlx5_alloc_map_uar failed, %d\n",
1814 __func__, err);
1815 goto err_free_netdev;
1816 }
1817
1818 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
1819 if (err) {
1820 netdev_err(netdev, "%s: mlx5_core_alloc_pd failed, %d\n",
1821 __func__, err);
1822 goto err_unmap_free_uar;
1823 }
1824
3191e05f
AS		 1825 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
1826 if (err) {
1827 netdev_err(netdev, "%s: mlx5_alloc_transport_domain failed, %d\n",
1828 __func__, err);
1829 goto err_dealloc_pd;
1830 }
1831
f62b8bb8
AV		 1832 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
1833 if (err) {
1834 netdev_err(netdev, "%s: mlx5e_create_mkey failed, %d\n",
1835 __func__, err);
3191e05f 1836 goto err_dealloc_transport_domain;
f62b8bb8
AV		 1837 }
1838
1839 err = register_netdev(netdev);
1840 if (err) {
1841 netdev_err(netdev, "%s: register_netdev failed, %d\n",
1842 __func__, err);
1843 goto err_destroy_mkey;
1844 }
1845
1846 mlx5e_enable_async_events(priv);
1847
1848 return priv;
1849
1850err_destroy_mkey:
1851 mlx5_core_destroy_mkey(mdev, &priv->mr);
1852
3191e05f
AS		 1853err_dealloc_transport_domain:
1854 mlx5_dealloc_transport_domain(mdev, priv->tdn);
1855
f62b8bb8
AV		 1856err_dealloc_pd:
1857 mlx5_core_dealloc_pd(mdev, priv->pdn);
1858
1859err_unmap_free_uar:
1860 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
1861
1862err_free_netdev:
1863 free_netdev(netdev);
1864
1865 return NULL;
1866}
1867
1868static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
1869{
1870 struct mlx5e_priv *priv = vpriv;
1871 struct net_device *netdev = priv->netdev;
1872
1873 unregister_netdev(netdev);
1874 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3191e05f 1875 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 1876 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
1877 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
1878 mlx5e_disable_async_events(priv);
1879 flush_scheduled_work();
1880 free_netdev(netdev);
1881}
1882
1883static void *mlx5e_get_netdev(void *vpriv)
1884{
1885 struct mlx5e_priv *priv = vpriv;
1886
1887 return priv->netdev;
1888}
1889
1890static struct mlx5_interface mlx5e_interface = {
1891 .add = mlx5e_create_netdev,
1892 .remove = mlx5e_destroy_netdev,
1893 .event = mlx5e_async_event,
1894 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
1895 .get_dev = mlx5e_get_netdev,
1896};
1897
1898void mlx5e_init(void)
1899{
1900 mlx5_register_interface(&mlx5e_interface);
1901}
1902
1903void mlx5e_cleanup(void)
1904{
1905 mlx5_unregister_interface(&mlx5e_interface);
1906}
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