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net/mlx5e: Use modify header ID cache for offloaded TC E-Switch flows
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV
1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV
35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV
38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG
41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
e8f887ac 54
3bc4b7bf
OG
55struct mlx5_nic_flow_attr {
56 u32 action;
57 u32 flow_tag;
2f4fe4ca 58 u32 mod_hdr_id;
3bc4b7bf
OG
59};
60
65ba8fb7
OG
61enum {
62 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 63 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 64 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
65ba8fb7
OG
65};
66
e8f887ac
AV
67struct mlx5e_tc_flow {
68 struct rhash_head node;
69 u64 cookie;
65ba8fb7 70 u8 flags;
74491de9 71 struct mlx5_flow_handle *rule;
11c9c548
OG
72 struct list_head encap; /* flows sharing the same encap ID */
73 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
3bc4b7bf
OG
74 union {
75 struct mlx5_esw_flow_attr esw_attr[0];
76 struct mlx5_nic_flow_attr nic_attr[0];
77 };
e8f887ac
AV
78};
79
17091853
OG
80struct mlx5e_tc_flow_parse_attr {
81 struct mlx5_flow_spec spec;
d79b6df6
OG
82 int num_mod_hdr_actions;
83 void *mod_hdr_actions;
17091853
OG
84};
85
a54e20b4
HHZ
86enum {
87 MLX5_HEADER_TYPE_VXLAN = 0x0,
88 MLX5_HEADER_TYPE_NVGRE = 0x1,
89};
90
acff797c
MG
91#define MLX5E_TC_TABLE_NUM_ENTRIES 1024
92#define MLX5E_TC_TABLE_NUM_GROUPS 4
e8f887ac 93
11c9c548
OG
94struct mod_hdr_key {
95 int num_actions;
96 void *actions;
97};
98
99struct mlx5e_mod_hdr_entry {
100 /* a node of a hash table which keeps all the mod_hdr entries */
101 struct hlist_node mod_hdr_hlist;
102
103 /* flows sharing the same mod_hdr entry */
104 struct list_head flows;
105
106 struct mod_hdr_key key;
107
108 u32 mod_hdr_id;
109};
110
111#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
112
113static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
114{
115 return jhash(key->actions,
116 key->num_actions * MLX5_MH_ACT_SZ, 0);
117}
118
119static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
120 struct mod_hdr_key *b)
121{
122 if (a->num_actions != b->num_actions)
123 return 1;
124
125 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
126}
127
128static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
129 struct mlx5e_tc_flow *flow,
130 struct mlx5e_tc_flow_parse_attr *parse_attr)
131{
132 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
133 int num_actions, actions_size, namespace, err;
134 struct mlx5e_mod_hdr_entry *mh;
135 struct mod_hdr_key key;
136 bool found = false;
137 u32 hash_key;
138
139 num_actions = parse_attr->num_mod_hdr_actions;
140 actions_size = MLX5_MH_ACT_SZ * num_actions;
141
142 key.actions = parse_attr->mod_hdr_actions;
143 key.num_actions = num_actions;
144
145 hash_key = hash_mod_hdr_info(&key);
146
147 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
148 namespace = MLX5_FLOW_NAMESPACE_FDB;
149 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
150 mod_hdr_hlist, hash_key) {
151 if (!cmp_mod_hdr_info(&mh->key, &key)) {
152 found = true;
153 break;
154 }
155 }
156 } else {
157 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
158 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
159 mod_hdr_hlist, hash_key) {
160 if (!cmp_mod_hdr_info(&mh->key, &key)) {
161 found = true;
162 break;
163 }
164 }
165 }
166
167 if (found)
168 goto attach_flow;
169
170 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
171 if (!mh)
172 return -ENOMEM;
173
174 mh->key.actions = (void *)mh + sizeof(*mh);
175 memcpy(mh->key.actions, key.actions, actions_size);
176 mh->key.num_actions = num_actions;
177 INIT_LIST_HEAD(&mh->flows);
178
179 err = mlx5_modify_header_alloc(priv->mdev, namespace,
180 mh->key.num_actions,
181 mh->key.actions,
182 &mh->mod_hdr_id);
183 if (err)
184 goto out_err;
185
186 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
187 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
188 else
189 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
190
191attach_flow:
192 list_add(&flow->mod_hdr, &mh->flows);
193 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
194 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
195 else
196 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
197
198 return 0;
199
200out_err:
201 kfree(mh);
202 return err;
203}
204
205static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
206 struct mlx5e_tc_flow *flow)
207{
208 struct list_head *next = flow->mod_hdr.next;
209
210 list_del(&flow->mod_hdr);
211
212 if (list_empty(next)) {
213 struct mlx5e_mod_hdr_entry *mh;
214
215 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
216
217 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
218 hash_del(&mh->mod_hdr_hlist);
219 kfree(mh);
220 }
221}
222
74491de9
MB
223static struct mlx5_flow_handle *
224mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 225 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 226 struct mlx5e_tc_flow *flow)
e8f887ac 227{
aa0cbbae 228 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 229 struct mlx5_core_dev *dev = priv->mdev;
aa0cbbae 230 struct mlx5_flow_destination dest = {};
66958ed9 231 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG
232 .action = attr->action,
233 .flow_tag = attr->flow_tag,
66958ed9
HHZ
234 .encap_id = 0,
235 };
aad7e08d 236 struct mlx5_fc *counter = NULL;
74491de9 237 struct mlx5_flow_handle *rule;
e8f887ac 238 bool table_created = false;
2f4fe4ca 239 int err;
e8f887ac 240
3bc4b7bf 241 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
aad7e08d
AV
242 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
243 dest.ft = priv->fs.vlan.ft.t;
3bc4b7bf 244 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
aad7e08d
AV
245 counter = mlx5_fc_create(dev, true);
246 if (IS_ERR(counter))
247 return ERR_CAST(counter);
248
249 dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
250 dest.counter = counter;
251 }
252
2f4fe4ca
OG
253 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
254 err = mlx5_modify_header_alloc(dev, MLX5_FLOW_NAMESPACE_KERNEL,
255 parse_attr->num_mod_hdr_actions,
256 parse_attr->mod_hdr_actions,
257 &attr->mod_hdr_id);
d7e75a32 258 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG
259 kfree(parse_attr->mod_hdr_actions);
260 if (err) {
261 rule = ERR_PTR(err);
262 goto err_create_mod_hdr_id;
263 }
264 }
265
acff797c
MG
266 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
267 priv->fs.tc.t =
268 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
269 MLX5E_TC_PRIO,
270 MLX5E_TC_TABLE_NUM_ENTRIES,
271 MLX5E_TC_TABLE_NUM_GROUPS,
c9f1b073 272 0, 0);
acff797c 273 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV
274 netdev_err(priv->netdev,
275 "Failed to create tc offload table\n");
aad7e08d
AV
276 rule = ERR_CAST(priv->fs.tc.t);
277 goto err_create_ft;
e8f887ac
AV
278 }
279
280 table_created = true;
281 }
282
17091853
OG
283 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
284 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
285 &flow_act, &dest, 1);
aad7e08d
AV
286
287 if (IS_ERR(rule))
288 goto err_add_rule;
289
290 return rule;
e8f887ac 291
aad7e08d
AV
292err_add_rule:
293 if (table_created) {
acff797c
MG
294 mlx5_destroy_flow_table(priv->fs.tc.t);
295 priv->fs.tc.t = NULL;
e8f887ac 296 }
aad7e08d 297err_create_ft:
2f4fe4ca
OG
298 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
299 mlx5_modify_header_dealloc(priv->mdev,
300 attr->mod_hdr_id);
301err_create_mod_hdr_id:
aad7e08d 302 mlx5_fc_destroy(dev, counter);
e8f887ac
AV
303
304 return rule;
305}
306
d85cdccb
OG
307static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
308 struct mlx5e_tc_flow *flow)
309{
513f8f7f 310 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG
311 struct mlx5_fc *counter = NULL;
312
aa0cbbae
OG
313 counter = mlx5_flow_rule_counter(flow->rule);
314 mlx5_del_flow_rules(flow->rule);
315 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG
316
317 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
318 mlx5_destroy_flow_table(priv->fs.tc.t);
319 priv->fs.tc.t = NULL;
320 }
2f4fe4ca 321
513f8f7f 322 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2f4fe4ca 323 mlx5_modify_header_dealloc(priv->mdev,
513f8f7f 324 attr->mod_hdr_id);
d85cdccb
OG
325}
326
aa0cbbae
OG
327static void mlx5e_detach_encap(struct mlx5e_priv *priv,
328 struct mlx5e_tc_flow *flow);
329
74491de9
MB
330static struct mlx5_flow_handle *
331mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 332 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 333 struct mlx5e_tc_flow *flow)
adb4c123
OG
334{
335 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae
OG
336 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
337 struct mlx5_flow_handle *rule;
8b32580d
OG
338 int err;
339
340 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG
341 if (err) {
342 rule = ERR_PTR(err);
343 goto err_add_vlan;
344 }
adb4c123 345
d7e75a32 346 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 347 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32
OG
348 kfree(parse_attr->mod_hdr_actions);
349 if (err) {
350 rule = ERR_PTR(err);
351 goto err_mod_hdr;
352 }
353 }
354
aa0cbbae
OG
355 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
356 if (IS_ERR(rule))
357 goto err_add_rule;
adb4c123 358
aa0cbbae
OG
359 return rule;
360
361err_add_rule:
513f8f7f 362 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 363 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 364err_mod_hdr:
aa0cbbae
OG
365 mlx5_eswitch_del_vlan_action(esw, attr);
366err_add_vlan:
367 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
368 mlx5e_detach_encap(priv, flow);
aa0cbbae
OG
369 return rule;
370}
d85cdccb
OG
371
372static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
373 struct mlx5e_tc_flow *flow)
374{
375 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 376 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 377
232c0013
HHZ
378 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
379 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 380 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 381 }
d85cdccb 382
513f8f7f 383 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 384
513f8f7f 385 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 386 mlx5e_detach_encap(priv, flow);
513f8f7f 387 kvfree(attr->parse_attr);
232c0013 388 }
d7e75a32 389
513f8f7f 390 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 391 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG
392}
393
232c0013
HHZ
394void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
395 struct mlx5e_encap_entry *e)
396{
397 struct mlx5e_tc_flow *flow;
398 int err;
399
400 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
401 e->encap_size, e->encap_header,
402 &e->encap_id);
403 if (err) {
404 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
405 err);
406 return;
407 }
408 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 409 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ
410
411 list_for_each_entry(flow, &e->flows, encap) {
412 flow->esw_attr->encap_id = e->encap_id;
413 flow->rule = mlx5e_tc_add_fdb_flow(priv,
414 flow->esw_attr->parse_attr,
415 flow);
416 if (IS_ERR(flow->rule)) {
417 err = PTR_ERR(flow->rule);
418 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
419 err);
420 continue;
421 }
422 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
423 }
424}
425
426void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
427 struct mlx5e_encap_entry *e)
428{
429 struct mlx5e_tc_flow *flow;
430 struct mlx5_fc *counter;
431
432 list_for_each_entry(flow, &e->flows, encap) {
433 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
434 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
435 counter = mlx5_flow_rule_counter(flow->rule);
436 mlx5_del_flow_rules(flow->rule);
437 mlx5_fc_destroy(priv->mdev, counter);
438 }
439 }
440
441 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
442 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
443 mlx5_encap_dealloc(priv->mdev, e->encap_id);
444 }
445}
446
f6dfb4c3
HHZ
447void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
448{
449 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
450 u64 bytes, packets, lastuse = 0;
451 struct mlx5e_tc_flow *flow;
452 struct mlx5e_encap_entry *e;
453 struct mlx5_fc *counter;
454 struct neigh_table *tbl;
455 bool neigh_used = false;
456 struct neighbour *n;
457
458 if (m_neigh->family == AF_INET)
459 tbl = &arp_tbl;
460#if IS_ENABLED(CONFIG_IPV6)
461 else if (m_neigh->family == AF_INET6)
462 tbl = ipv6_stub->nd_tbl;
463#endif
464 else
465 return;
466
467 list_for_each_entry(e, &nhe->encap_list, encap_list) {
468 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
469 continue;
470 list_for_each_entry(flow, &e->flows, encap) {
471 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
472 counter = mlx5_flow_rule_counter(flow->rule);
473 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
474 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
475 neigh_used = true;
476 break;
477 }
478 }
479 }
480 }
481
482 if (neigh_used) {
483 nhe->reported_lastuse = jiffies;
484
485 /* find the relevant neigh according to the cached device and
486 * dst ip pair
487 */
488 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
489 if (!n) {
490 WARN(1, "The neighbour already freed\n");
491 return;
492 }
493
494 neigh_event_send(n, NULL);
495 neigh_release(n);
496 }
497}
498
d85cdccb
OG
499static void mlx5e_detach_encap(struct mlx5e_priv *priv,
500 struct mlx5e_tc_flow *flow)
501{
5067b602
RD
502 struct list_head *next = flow->encap.next;
503
504 list_del(&flow->encap);
505 if (list_empty(next)) {
c1ae1152 506 struct mlx5e_encap_entry *e;
5067b602 507
c1ae1152 508 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ
509 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
510
511 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 512 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 513
cdc5a7f3 514 hash_del_rcu(&e->encap_hlist);
232c0013 515 kfree(e->encap_header);
5067b602
RD
516 kfree(e);
517 }
518}
519
e8f887ac 520static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 521 struct mlx5e_tc_flow *flow)
e8f887ac 522{
d85cdccb
OG
523 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
524 mlx5e_tc_del_fdb_flow(priv, flow);
525 else
526 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV
527}
528
bbd00f7e
HHZ
529static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
530 struct tc_cls_flower_offload *f)
531{
532 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
533 outer_headers);
534 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
535 outer_headers);
536 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
537 misc_parameters);
538 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
539 misc_parameters);
540
541 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
542 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
543
544 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
545 struct flow_dissector_key_keyid *key =
546 skb_flow_dissector_target(f->dissector,
547 FLOW_DISSECTOR_KEY_ENC_KEYID,
548 f->key);
549 struct flow_dissector_key_keyid *mask =
550 skb_flow_dissector_target(f->dissector,
551 FLOW_DISSECTOR_KEY_ENC_KEYID,
552 f->mask);
553 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
554 be32_to_cpu(mask->keyid));
555 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
556 be32_to_cpu(key->keyid));
557 }
558}
559
560static int parse_tunnel_attr(struct mlx5e_priv *priv,
561 struct mlx5_flow_spec *spec,
562 struct tc_cls_flower_offload *f)
563{
564 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
565 outer_headers);
566 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
567 outer_headers);
568
2e72eb43
OG
569 struct flow_dissector_key_control *enc_control =
570 skb_flow_dissector_target(f->dissector,
571 FLOW_DISSECTOR_KEY_ENC_CONTROL,
572 f->key);
573
bbd00f7e
HHZ
574 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
575 struct flow_dissector_key_ports *key =
576 skb_flow_dissector_target(f->dissector,
577 FLOW_DISSECTOR_KEY_ENC_PORTS,
578 f->key);
579 struct flow_dissector_key_ports *mask =
580 skb_flow_dissector_target(f->dissector,
581 FLOW_DISSECTOR_KEY_ENC_PORTS,
582 f->mask);
1ad9a00a
PB
583 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
584 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
585 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ
586
587 /* Full udp dst port must be given */
588 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 589 goto vxlan_match_offload_err;
bbd00f7e 590
1ad9a00a 591 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ
592 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
593 parse_vxlan_attr(spec, f);
2fcd82e9
OG
594 else {
595 netdev_warn(priv->netdev,
596 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 597 return -EOPNOTSUPP;
2fcd82e9 598 }
bbd00f7e
HHZ
599
600 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
601 udp_dport, ntohs(mask->dst));
602 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
603 udp_dport, ntohs(key->dst));
604
cd377663
OG
605 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
606 udp_sport, ntohs(mask->src));
607 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
608 udp_sport, ntohs(key->src));
bbd00f7e 609 } else { /* udp dst port must be given */
2fcd82e9
OG
610vxlan_match_offload_err:
611 netdev_warn(priv->netdev,
612 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
613 return -EOPNOTSUPP;
bbd00f7e
HHZ
614 }
615
2e72eb43 616 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ
617 struct flow_dissector_key_ipv4_addrs *key =
618 skb_flow_dissector_target(f->dissector,
619 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
620 f->key);
621 struct flow_dissector_key_ipv4_addrs *mask =
622 skb_flow_dissector_target(f->dissector,
623 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
624 f->mask);
625 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
626 src_ipv4_src_ipv6.ipv4_layout.ipv4,
627 ntohl(mask->src));
628 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
629 src_ipv4_src_ipv6.ipv4_layout.ipv4,
630 ntohl(key->src));
631
632 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
633 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
634 ntohl(mask->dst));
635 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
636 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
637 ntohl(key->dst));
bbd00f7e 638
2e72eb43
OG
639 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
640 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG
641 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
642 struct flow_dissector_key_ipv6_addrs *key =
643 skb_flow_dissector_target(f->dissector,
644 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
645 f->key);
646 struct flow_dissector_key_ipv6_addrs *mask =
647 skb_flow_dissector_target(f->dissector,
648 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
649 f->mask);
650
651 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
652 src_ipv4_src_ipv6.ipv6_layout.ipv6),
653 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
654 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
655 src_ipv4_src_ipv6.ipv6_layout.ipv6),
656 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
657
658 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
659 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
660 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
661 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
662 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
663 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
664
665 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
666 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 667 }
bbd00f7e
HHZ
668
669 /* Enforce DMAC when offloading incoming tunneled flows.
670 * Flow counters require a match on the DMAC.
671 */
672 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
673 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
674 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
675 dmac_47_16), priv->netdev->dev_addr);
676
677 /* let software handle IP fragments */
678 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
679 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
680
681 return 0;
682}
683
de0af0bf
RD
684static int __parse_cls_flower(struct mlx5e_priv *priv,
685 struct mlx5_flow_spec *spec,
686 struct tc_cls_flower_offload *f,
687 u8 *min_inline)
e3a2b7ed 688{
c5bb1730
MG
689 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
690 outer_headers);
691 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
692 outer_headers);
e3a2b7ed
AV
693 u16 addr_type = 0;
694 u8 ip_proto = 0;
695
de0af0bf
RD
696 *min_inline = MLX5_INLINE_MODE_L2;
697
e3a2b7ed
AV
698 if (f->dissector->used_keys &
699 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
700 BIT(FLOW_DISSECTOR_KEY_BASIC) |
701 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 702 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV
703 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
704 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ
705 BIT(FLOW_DISSECTOR_KEY_PORTS) |
706 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
707 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
708 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
709 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 710 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG
711 BIT(FLOW_DISSECTOR_KEY_TCP) |
712 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV
713 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
714 f->dissector->used_keys);
715 return -EOPNOTSUPP;
716 }
717
bbd00f7e
HHZ
718 if ((dissector_uses_key(f->dissector,
719 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
720 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
721 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
722 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
723 struct flow_dissector_key_control *key =
724 skb_flow_dissector_target(f->dissector,
725 FLOW_DISSECTOR_KEY_ENC_CONTROL,
726 f->key);
727 switch (key->addr_type) {
728 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 729 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ
730 if (parse_tunnel_attr(priv, spec, f))
731 return -EOPNOTSUPP;
732 break;
733 default:
734 return -EOPNOTSUPP;
735 }
736
737 /* In decap flow, header pointers should point to the inner
738 * headers, outer header were already set by parse_tunnel_attr
739 */
740 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
741 inner_headers);
742 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
743 inner_headers);
744 }
745
e3a2b7ed
AV
746 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
747 struct flow_dissector_key_control *key =
748 skb_flow_dissector_target(f->dissector,
1dbd0d37 749 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 750 f->key);
3f7d0eb4
OG
751
752 struct flow_dissector_key_control *mask =
753 skb_flow_dissector_target(f->dissector,
754 FLOW_DISSECTOR_KEY_CONTROL,
755 f->mask);
e3a2b7ed 756 addr_type = key->addr_type;
3f7d0eb4
OG
757
758 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
759 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
760 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
761 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG
762
763 /* the HW doesn't need L3 inline to match on frag=no */
764 if (key->flags & FLOW_DIS_IS_FRAGMENT)
765 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 766 }
e3a2b7ed
AV
767 }
768
769 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
770 struct flow_dissector_key_basic *key =
771 skb_flow_dissector_target(f->dissector,
772 FLOW_DISSECTOR_KEY_BASIC,
773 f->key);
774 struct flow_dissector_key_basic *mask =
775 skb_flow_dissector_target(f->dissector,
776 FLOW_DISSECTOR_KEY_BASIC,
777 f->mask);
778 ip_proto = key->ip_proto;
779
780 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
781 ntohs(mask->n_proto));
782 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
783 ntohs(key->n_proto));
784
785 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
786 mask->ip_proto);
787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
788 key->ip_proto);
de0af0bf
RD
789
790 if (mask->ip_proto)
791 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
792 }
793
794 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
795 struct flow_dissector_key_eth_addrs *key =
796 skb_flow_dissector_target(f->dissector,
797 FLOW_DISSECTOR_KEY_ETH_ADDRS,
798 f->key);
799 struct flow_dissector_key_eth_addrs *mask =
800 skb_flow_dissector_target(f->dissector,
801 FLOW_DISSECTOR_KEY_ETH_ADDRS,
802 f->mask);
803
804 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
805 dmac_47_16),
806 mask->dst);
807 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
808 dmac_47_16),
809 key->dst);
810
811 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
812 smac_47_16),
813 mask->src);
814 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
815 smac_47_16),
816 key->src);
817 }
818
095b6cfd
OG
819 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
820 struct flow_dissector_key_vlan *key =
821 skb_flow_dissector_target(f->dissector,
822 FLOW_DISSECTOR_KEY_VLAN,
823 f->key);
824 struct flow_dissector_key_vlan *mask =
825 skb_flow_dissector_target(f->dissector,
826 FLOW_DISSECTOR_KEY_VLAN,
827 f->mask);
358d79a4 828 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY
829 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
830 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG
831
832 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
833 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG
834
835 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
836 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG
837 }
838 }
839
e3a2b7ed
AV
840 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
841 struct flow_dissector_key_ipv4_addrs *key =
842 skb_flow_dissector_target(f->dissector,
843 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
844 f->key);
845 struct flow_dissector_key_ipv4_addrs *mask =
846 skb_flow_dissector_target(f->dissector,
847 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
848 f->mask);
849
850 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
851 src_ipv4_src_ipv6.ipv4_layout.ipv4),
852 &mask->src, sizeof(mask->src));
853 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
854 src_ipv4_src_ipv6.ipv4_layout.ipv4),
855 &key->src, sizeof(key->src));
856 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
857 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
858 &mask->dst, sizeof(mask->dst));
859 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
860 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
861 &key->dst, sizeof(key->dst));
de0af0bf
RD
862
863 if (mask->src || mask->dst)
864 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
865 }
866
867 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
868 struct flow_dissector_key_ipv6_addrs *key =
869 skb_flow_dissector_target(f->dissector,
870 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
871 f->key);
872 struct flow_dissector_key_ipv6_addrs *mask =
873 skb_flow_dissector_target(f->dissector,
874 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
875 f->mask);
876
877 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
878 src_ipv4_src_ipv6.ipv6_layout.ipv6),
879 &mask->src, sizeof(mask->src));
880 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
881 src_ipv4_src_ipv6.ipv6_layout.ipv6),
882 &key->src, sizeof(key->src));
883
884 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
885 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
886 &mask->dst, sizeof(mask->dst));
887 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
888 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
889 &key->dst, sizeof(key->dst));
de0af0bf
RD
890
891 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
892 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
893 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
894 }
895
896 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
897 struct flow_dissector_key_ports *key =
898 skb_flow_dissector_target(f->dissector,
899 FLOW_DISSECTOR_KEY_PORTS,
900 f->key);
901 struct flow_dissector_key_ports *mask =
902 skb_flow_dissector_target(f->dissector,
903 FLOW_DISSECTOR_KEY_PORTS,
904 f->mask);
905 switch (ip_proto) {
906 case IPPROTO_TCP:
907 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
908 tcp_sport, ntohs(mask->src));
909 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
910 tcp_sport, ntohs(key->src));
911
912 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
913 tcp_dport, ntohs(mask->dst));
914 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
915 tcp_dport, ntohs(key->dst));
916 break;
917
918 case IPPROTO_UDP:
919 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
920 udp_sport, ntohs(mask->src));
921 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
922 udp_sport, ntohs(key->src));
923
924 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
925 udp_dport, ntohs(mask->dst));
926 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
927 udp_dport, ntohs(key->dst));
928 break;
929 default:
930 netdev_err(priv->netdev,
931 "Only UDP and TCP transport are supported\n");
932 return -EINVAL;
933 }
de0af0bf
RD
934
935 if (mask->src || mask->dst)
936 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV
937 }
938
fd7da28b
OG
939 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
940 struct flow_dissector_key_ip *key =
941 skb_flow_dissector_target(f->dissector,
942 FLOW_DISSECTOR_KEY_IP,
943 f->key);
944 struct flow_dissector_key_ip *mask =
945 skb_flow_dissector_target(f->dissector,
946 FLOW_DISSECTOR_KEY_IP,
947 f->mask);
948
949 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
950 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
951
952 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
953 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
954
955 if (mask->tos)
956 *min_inline = MLX5_INLINE_MODE_IP;
957
958 if (mask->ttl) /* currently not supported */
959 return -EOPNOTSUPP;
960 }
961
e77834ec
OG
962 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
963 struct flow_dissector_key_tcp *key =
964 skb_flow_dissector_target(f->dissector,
965 FLOW_DISSECTOR_KEY_TCP,
966 f->key);
967 struct flow_dissector_key_tcp *mask =
968 skb_flow_dissector_target(f->dissector,
969 FLOW_DISSECTOR_KEY_TCP,
970 f->mask);
971
972 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
973 ntohs(mask->flags));
974 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
975 ntohs(key->flags));
976
977 if (mask->flags)
978 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
979 }
980
e3a2b7ed
AV
981 return 0;
982}
983
de0af0bf 984static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 985 struct mlx5e_tc_flow *flow,
de0af0bf
RD
986 struct mlx5_flow_spec *spec,
987 struct tc_cls_flower_offload *f)
988{
989 struct mlx5_core_dev *dev = priv->mdev;
990 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM
991 struct mlx5e_rep_priv *rpriv = priv->ppriv;
992 struct mlx5_eswitch_rep *rep;
de0af0bf
RD
993 u8 min_inline;
994 int err;
995
996 err = __parse_cls_flower(priv, spec, f, &min_inline);
997
1d447a39
SM
998 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
999 rep = rpriv->rep;
1000 if (rep->vport != FDB_UPLINK_VPORT &&
1001 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1002 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD
1003 netdev_warn(priv->netdev,
1004 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1005 min_inline, esw->offloads.inline_mode);
1006 return -EOPNOTSUPP;
1007 }
1008 }
1009
1010 return err;
1011}
1012
d79b6df6
OG
1013struct pedit_headers {
1014 struct ethhdr eth;
1015 struct iphdr ip4;
1016 struct ipv6hdr ip6;
1017 struct tcphdr tcp;
1018 struct udphdr udp;
1019};
1020
1021static int pedit_header_offsets[] = {
1022 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1023 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1024 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1025 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1026 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1027};
1028
1029#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1030
1031static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1032 struct pedit_headers *masks,
1033 struct pedit_headers *vals)
1034{
1035 u32 *curr_pmask, *curr_pval;
1036
1037 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1038 goto out_err;
1039
1040 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1041 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1042
1043 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1044 goto out_err;
1045
1046 *curr_pmask |= mask;
1047 *curr_pval |= (val & mask);
1048
1049 return 0;
1050
1051out_err:
1052 return -EOPNOTSUPP;
1053}
1054
1055struct mlx5_fields {
1056 u8 field;
1057 u8 size;
1058 u32 offset;
1059};
1060
1061static struct mlx5_fields fields[] = {
1062 {MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_dest[0])},
1063 {MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_dest[4])},
1064 {MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_source[0])},
1065 {MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_source[4])},
1066 {MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE, 2, offsetof(struct pedit_headers, eth.h_proto)},
1067
1068 {MLX5_ACTION_IN_FIELD_OUT_IP_DSCP, 1, offsetof(struct pedit_headers, ip4.tos)},
1069 {MLX5_ACTION_IN_FIELD_OUT_IP_TTL, 1, offsetof(struct pedit_headers, ip4.ttl)},
1070 {MLX5_ACTION_IN_FIELD_OUT_SIPV4, 4, offsetof(struct pedit_headers, ip4.saddr)},
1071 {MLX5_ACTION_IN_FIELD_OUT_DIPV4, 4, offsetof(struct pedit_headers, ip4.daddr)},
1072
1073 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[0])},
1074 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[1])},
1075 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[2])},
1076 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[3])},
1077 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[0])},
1078 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[1])},
1079 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[2])},
1080 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[3])},
1081
1082 {MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT, 2, offsetof(struct pedit_headers, tcp.source)},
1083 {MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT, 2, offsetof(struct pedit_headers, tcp.dest)},
1084 {MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS, 1, offsetof(struct pedit_headers, tcp.ack_seq) + 5},
1085
1086 {MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT, 2, offsetof(struct pedit_headers, udp.source)},
1087 {MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT, 2, offsetof(struct pedit_headers, udp.dest)},
1088};
1089
1090/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1091 * max from the SW pedit action. On success, it says how many HW actions were
1092 * actually parsed.
1093 */
1094static int offload_pedit_fields(struct pedit_headers *masks,
1095 struct pedit_headers *vals,
1096 struct mlx5e_tc_flow_parse_attr *parse_attr)
1097{
1098 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
d824bf3f 1099 int i, action_size, nactions, max_actions, first, last, first_z;
d79b6df6 1100 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG
1101 struct mlx5_fields *f;
1102 u8 cmd, field_bsize;
e3ca4e05 1103 u32 s_mask, a_mask;
d79b6df6
OG
1104 unsigned long mask;
1105 void *action;
1106
1107 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1108 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1109 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1110 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1111
1112 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1113 action = parse_attr->mod_hdr_actions;
1114 max_actions = parse_attr->num_mod_hdr_actions;
1115 nactions = 0;
1116
1117 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1118 f = &fields[i];
1119 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG
1120 s_mask = 0;
1121 a_mask = 0;
d79b6df6
OG
1122
1123 s_masks_p = (void *)set_masks + f->offset;
1124 a_masks_p = (void *)add_masks + f->offset;
1125
1126 memcpy(&s_mask, s_masks_p, f->size);
1127 memcpy(&a_mask, a_masks_p, f->size);
1128
1129 if (!s_mask && !a_mask) /* nothing to offload here */
1130 continue;
1131
1132 if (s_mask && a_mask) {
1133 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1134 return -EOPNOTSUPP;
1135 }
1136
1137 if (nactions == max_actions) {
1138 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1139 return -EOPNOTSUPP;
1140 }
1141
1142 if (s_mask) {
1143 cmd = MLX5_ACTION_TYPE_SET;
1144 mask = s_mask;
1145 vals_p = (void *)set_vals + f->offset;
1146 /* clear to denote we consumed this field */
1147 memset(s_masks_p, 0, f->size);
1148 } else {
1149 cmd = MLX5_ACTION_TYPE_ADD;
1150 mask = a_mask;
1151 vals_p = (void *)add_vals + f->offset;
1152 /* clear to denote we consumed this field */
1153 memset(a_masks_p, 0, f->size);
1154 }
1155
d79b6df6 1156 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1157
d824bf3f 1158 first_z = find_first_zero_bit(&mask, field_bsize);
d79b6df6
OG
1159 first = find_first_bit(&mask, field_bsize);
1160 last = find_last_bit(&mask, field_bsize);
d824bf3f 1161 if (first > 0 || last != (field_bsize - 1) || first_z < last) {
d79b6df6
OG
1162 printk(KERN_WARNING "mlx5: partial rewrite (mask %lx) is currently not offloaded\n",
1163 mask);
1164 return -EOPNOTSUPP;
1165 }
1166
1167 MLX5_SET(set_action_in, action, action_type, cmd);
1168 MLX5_SET(set_action_in, action, field, f->field);
1169
1170 if (cmd == MLX5_ACTION_TYPE_SET) {
1171 MLX5_SET(set_action_in, action, offset, 0);
1172 /* length is num of bits to be written, zero means length of 32 */
1173 MLX5_SET(set_action_in, action, length, field_bsize);
1174 }
1175
1176 if (field_bsize == 32)
e3ca4e05 1177 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p));
d79b6df6 1178 else if (field_bsize == 16)
e3ca4e05 1179 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p));
d79b6df6 1180 else if (field_bsize == 8)
e3ca4e05 1181 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p);
d79b6df6
OG
1182
1183 action += action_size;
1184 nactions++;
1185 }
1186
1187 parse_attr->num_mod_hdr_actions = nactions;
1188 return 0;
1189}
1190
1191static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1192 const struct tc_action *a, int namespace,
1193 struct mlx5e_tc_flow_parse_attr *parse_attr)
1194{
1195 int nkeys, action_size, max_actions;
1196
1197 nkeys = tcf_pedit_nkeys(a);
1198 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1199
1200 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1201 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1202 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1203 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1204
1205 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1206 max_actions = min(max_actions, nkeys * 16);
1207
1208 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1209 if (!parse_attr->mod_hdr_actions)
1210 return -ENOMEM;
1211
1212 parse_attr->num_mod_hdr_actions = max_actions;
1213 return 0;
1214}
1215
1216static const struct pedit_headers zero_masks = {};
1217
1218static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1219 const struct tc_action *a, int namespace,
1220 struct mlx5e_tc_flow_parse_attr *parse_attr)
1221{
1222 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1223 int nkeys, i, err = -EOPNOTSUPP;
1224 u32 mask, val, offset;
1225 u8 cmd, htype;
1226
1227 nkeys = tcf_pedit_nkeys(a);
1228
1229 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1230 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1231
1232 for (i = 0; i < nkeys; i++) {
1233 htype = tcf_pedit_htype(a, i);
1234 cmd = tcf_pedit_cmd(a, i);
1235 err = -EOPNOTSUPP; /* can't be all optimistic */
1236
1237 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1238 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1239 goto out_err;
1240 }
1241
1242 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1243 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1244 goto out_err;
1245 }
1246
1247 mask = tcf_pedit_mask(a, i);
1248 val = tcf_pedit_val(a, i);
1249 offset = tcf_pedit_offset(a, i);
1250
1251 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1252 if (err)
1253 goto out_err;
1254 }
1255
1256 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1257 if (err)
1258 goto out_err;
1259
1260 err = offload_pedit_fields(masks, vals, parse_attr);
1261 if (err < 0)
1262 goto out_dealloc_parsed_actions;
1263
1264 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1265 cmd_masks = &masks[cmd];
1266 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1267 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1268 cmd);
1269 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1270 16, 1, cmd_masks, sizeof(zero_masks), true);
1271 err = -EOPNOTSUPP;
1272 goto out_dealloc_parsed_actions;
1273 }
1274 }
1275
1276 return 0;
1277
1278out_dealloc_parsed_actions:
1279 kfree(parse_attr->mod_hdr_actions);
1280out_err:
1281 return err;
1282}
1283
26c02749
OG
1284static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1285{
1286 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1287 TCA_CSUM_UPDATE_FLAG_UDP;
1288
1289 /* The HW recalcs checksums only if re-writing headers */
1290 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1291 netdev_warn(priv->netdev,
1292 "TC csum action is only offloaded with pedit\n");
1293 return false;
1294 }
1295
1296 if (update_flags & ~prot_flags) {
1297 netdev_warn(priv->netdev,
1298 "can't offload TC csum action for some header/s - flags %#x\n",
1299 update_flags);
1300 return false;
1301 }
1302
1303 return true;
1304}
1305
5c40348c 1306static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG
1307 struct mlx5e_tc_flow_parse_attr *parse_attr,
1308 struct mlx5e_tc_flow *flow)
e3a2b7ed 1309{
aa0cbbae 1310 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1311 const struct tc_action *a;
22dc13c8 1312 LIST_HEAD(actions);
2f4fe4ca 1313 int err;
e3a2b7ed
AV
1314
1315 if (tc_no_actions(exts))
1316 return -EINVAL;
1317
3bc4b7bf
OG
1318 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1319 attr->action = 0;
e3a2b7ed 1320
22dc13c8
WC
1321 tcf_exts_to_list(exts, &actions);
1322 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1323 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1324 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV
1325 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1326 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1327 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV
1328 continue;
1329 }
1330
2f4fe4ca
OG
1331 if (is_tcf_pedit(a)) {
1332 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1333 parse_attr);
1334 if (err)
1335 return err;
1336
1337 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1338 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1339 continue;
1340 }
1341
26c02749
OG
1342 if (is_tcf_csum(a)) {
1343 if (csum_offload_supported(priv, attr->action,
1344 tcf_csum_update_flags(a)))
1345 continue;
1346
1347 return -EOPNOTSUPP;
1348 }
1349
e3a2b7ed
AV
1350 if (is_tcf_skbedit_mark(a)) {
1351 u32 mark = tcf_skbedit_mark(a);
1352
1353 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1354 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1355 mark);
1356 return -EINVAL;
1357 }
1358
3bc4b7bf
OG
1359 attr->flow_tag = mark;
1360 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV
1361 continue;
1362 }
1363
1364 return -EINVAL;
1365 }
1366
1367 return 0;
1368}
1369
76f7444d
OG
1370static inline int cmp_encap_info(struct ip_tunnel_key *a,
1371 struct ip_tunnel_key *b)
a54e20b4
HHZ
1372{
1373 return memcmp(a, b, sizeof(*a));
1374}
1375
76f7444d 1376static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 1377{
76f7444d 1378 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ
1379}
1380
1381static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
1382 struct net_device *mirred_dev,
1383 struct net_device **out_dev,
1384 struct flowi4 *fl4,
1385 struct neighbour **out_n,
a54e20b4
HHZ
1386 int *out_ttl)
1387{
3e621b19 1388 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a54e20b4
HHZ
1389 struct rtable *rt;
1390 struct neighbour *n = NULL;
a54e20b4
HHZ
1391
1392#if IS_ENABLED(CONFIG_INET)
abeffce9
AB
1393 int ret;
1394
a54e20b4 1395 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB
1396 ret = PTR_ERR_OR_ZERO(rt);
1397 if (ret)
1398 return ret;
a54e20b4
HHZ
1399#else
1400 return -EOPNOTSUPP;
1401#endif
3e621b19
HHZ
1402 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1403 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
1404 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1405 else
1406 *out_dev = rt->dst.dev;
a54e20b4 1407
75c33da8 1408 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ
1409 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
1410 ip_rt_put(rt);
1411 if (!n)
1412 return -ENOMEM;
1413
1414 *out_n = n;
a54e20b4
HHZ
1415 return 0;
1416}
1417
ce99f6b9
OG
1418static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
1419 struct net_device *mirred_dev,
1420 struct net_device **out_dev,
1421 struct flowi6 *fl6,
1422 struct neighbour **out_n,
1423 int *out_ttl)
1424{
1425 struct neighbour *n = NULL;
1426 struct dst_entry *dst;
1427
1428#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
1429 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1430 int ret;
1431
1432 dst = ip6_route_output(dev_net(mirred_dev), NULL, fl6);
321fa4ff
AB
1433 ret = dst->error;
1434 if (ret) {
ce99f6b9
OG
1435 dst_release(dst);
1436 return ret;
1437 }
1438
1439 *out_ttl = ip6_dst_hoplimit(dst);
1440
1441 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1442 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
1443 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1444 else
1445 *out_dev = dst->dev;
1446#else
1447 return -EOPNOTSUPP;
1448#endif
1449
1450 n = dst_neigh_lookup(dst, &fl6->daddr);
1451 dst_release(dst);
1452 if (!n)
1453 return -ENOMEM;
1454
1455 *out_n = n;
1456 return 0;
1457}
1458
32f3671f
OG
1459static void gen_vxlan_header_ipv4(struct net_device *out_dev,
1460 char buf[], int encap_size,
1461 unsigned char h_dest[ETH_ALEN],
1462 int ttl,
1463 __be32 daddr,
1464 __be32 saddr,
1465 __be16 udp_dst_port,
1466 __be32 vx_vni)
a54e20b4 1467{
a54e20b4
HHZ
1468 struct ethhdr *eth = (struct ethhdr *)buf;
1469 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
1470 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
1471 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1472
1473 memset(buf, 0, encap_size);
1474
1475 ether_addr_copy(eth->h_dest, h_dest);
1476 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1477 eth->h_proto = htons(ETH_P_IP);
1478
1479 ip->daddr = daddr;
1480 ip->saddr = saddr;
1481
1482 ip->ttl = ttl;
1483 ip->protocol = IPPROTO_UDP;
1484 ip->version = 0x4;
1485 ip->ihl = 0x5;
1486
1487 udp->dest = udp_dst_port;
1488 vxh->vx_flags = VXLAN_HF_VNI;
1489 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ
1490}
1491
225aabaf
OG
1492static void gen_vxlan_header_ipv6(struct net_device *out_dev,
1493 char buf[], int encap_size,
1494 unsigned char h_dest[ETH_ALEN],
1495 int ttl,
1496 struct in6_addr *daddr,
1497 struct in6_addr *saddr,
1498 __be16 udp_dst_port,
1499 __be32 vx_vni)
ce99f6b9 1500{
ce99f6b9
OG
1501 struct ethhdr *eth = (struct ethhdr *)buf;
1502 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
1503 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
1504 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1505
1506 memset(buf, 0, encap_size);
1507
1508 ether_addr_copy(eth->h_dest, h_dest);
1509 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1510 eth->h_proto = htons(ETH_P_IPV6);
1511
1512 ip6_flow_hdr(ip6h, 0, 0);
1513 /* the HW fills up ipv6 payload len */
1514 ip6h->nexthdr = IPPROTO_UDP;
1515 ip6h->hop_limit = ttl;
1516 ip6h->daddr = *daddr;
1517 ip6h->saddr = *saddr;
1518
1519 udp->dest = udp_dst_port;
1520 vxh->vx_flags = VXLAN_HF_VNI;
1521 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG
1522}
1523
a54e20b4
HHZ
1524static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
1525 struct net_device *mirred_dev,
1a8552bd 1526 struct mlx5e_encap_entry *e)
a54e20b4
HHZ
1527{
1528 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 1529 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 1530 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1531 struct net_device *out_dev;
a42485eb 1532 struct neighbour *n = NULL;
a54e20b4 1533 struct flowi4 fl4 = {};
a54e20b4 1534 char *encap_header;
32f3671f 1535 int ttl, err;
033354d5 1536 u8 nud_state;
32f3671f
OG
1537
1538 if (max_encap_size < ipv4_encap_size) {
1539 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1540 ipv4_encap_size, max_encap_size);
1541 return -EOPNOTSUPP;
1542 }
a54e20b4 1543
32f3671f 1544 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ
1545 if (!encap_header)
1546 return -ENOMEM;
1547
1548 switch (e->tunnel_type) {
1549 case MLX5_HEADER_TYPE_VXLAN:
1550 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 1551 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ
1552 break;
1553 default:
1554 err = -EOPNOTSUPP;
1555 goto out;
1556 }
9a941117 1557 fl4.flowi4_tos = tun_key->tos;
76f7444d 1558 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 1559 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 1560
1a8552bd 1561 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 1562 &fl4, &n, &ttl);
a54e20b4
HHZ
1563 if (err)
1564 goto out;
1565
232c0013
HHZ
1566 /* used by mlx5e_detach_encap to lookup a neigh hash table
1567 * entry in the neigh hash table when a user deletes a rule
1568 */
1569 e->m_neigh.dev = n->dev;
f6dfb4c3 1570 e->m_neigh.family = n->ops->family;
232c0013
HHZ
1571 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1572 e->out_dev = out_dev;
1573
1574 /* It's importent to add the neigh to the hash table before checking
1575 * the neigh validity state. So if we'll get a notification, in case the
1576 * neigh changes it's validity state, we would find the relevant neigh
1577 * in the hash.
1578 */
1579 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1580 if (err)
1581 goto out;
1582
033354d5
HHZ
1583 read_lock_bh(&n->lock);
1584 nud_state = n->nud_state;
1585 ether_addr_copy(e->h_dest, n->ha);
1586 read_unlock_bh(&n->lock);
1587
a54e20b4
HHZ
1588 switch (e->tunnel_type) {
1589 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1590 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG
1591 ipv4_encap_size, e->h_dest, ttl,
1592 fl4.daddr,
1593 fl4.saddr, tun_key->tp_dst,
1594 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ
1595 break;
1596 default:
1597 err = -EOPNOTSUPP;
232c0013
HHZ
1598 goto destroy_neigh_entry;
1599 }
1600 e->encap_size = ipv4_encap_size;
1601 e->encap_header = encap_header;
1602
1603 if (!(nud_state & NUD_VALID)) {
1604 neigh_event_send(n, NULL);
27902f08
WY
1605 err = -EAGAIN;
1606 goto out;
a54e20b4
HHZ
1607 }
1608
1609 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 1610 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ
1611 if (err)
1612 goto destroy_neigh_entry;
1613
1614 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1615 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ
1616 neigh_release(n);
1617 return err;
1618
1619destroy_neigh_entry:
1620 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
a54e20b4
HHZ
1621out:
1622 kfree(encap_header);
232c0013
HHZ
1623 if (n)
1624 neigh_release(n);
a54e20b4
HHZ
1625 return err;
1626}
1627
ce99f6b9
OG
1628static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
1629 struct net_device *mirred_dev,
1a8552bd 1630 struct mlx5e_encap_entry *e)
ce99f6b9
OG
1631{
1632 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 1633 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 1634 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1635 struct net_device *out_dev;
ce99f6b9
OG
1636 struct neighbour *n = NULL;
1637 struct flowi6 fl6 = {};
1638 char *encap_header;
225aabaf 1639 int err, ttl = 0;
033354d5 1640 u8 nud_state;
ce99f6b9 1641
225aabaf
OG
1642 if (max_encap_size < ipv6_encap_size) {
1643 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1644 ipv6_encap_size, max_encap_size);
1645 return -EOPNOTSUPP;
1646 }
ce99f6b9 1647
225aabaf 1648 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG
1649 if (!encap_header)
1650 return -ENOMEM;
1651
1652 switch (e->tunnel_type) {
1653 case MLX5_HEADER_TYPE_VXLAN:
1654 fl6.flowi6_proto = IPPROTO_UDP;
1655 fl6.fl6_dport = tun_key->tp_dst;
1656 break;
1657 default:
1658 err = -EOPNOTSUPP;
1659 goto out;
1660 }
1661
1662 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
1663 fl6.daddr = tun_key->u.ipv6.dst;
1664 fl6.saddr = tun_key->u.ipv6.src;
1665
1a8552bd 1666 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG
1667 &fl6, &n, &ttl);
1668 if (err)
1669 goto out;
1670
232c0013
HHZ
1671 /* used by mlx5e_detach_encap to lookup a neigh hash table
1672 * entry in the neigh hash table when a user deletes a rule
1673 */
1674 e->m_neigh.dev = n->dev;
f6dfb4c3 1675 e->m_neigh.family = n->ops->family;
232c0013
HHZ
1676 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1677 e->out_dev = out_dev;
1678
1679 /* It's importent to add the neigh to the hash table before checking
1680 * the neigh validity state. So if we'll get a notification, in case the
1681 * neigh changes it's validity state, we would find the relevant neigh
1682 * in the hash.
1683 */
1684 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1685 if (err)
1686 goto out;
1687
033354d5
HHZ
1688 read_lock_bh(&n->lock);
1689 nud_state = n->nud_state;
1690 ether_addr_copy(e->h_dest, n->ha);
1691 read_unlock_bh(&n->lock);
1692
ce99f6b9
OG
1693 switch (e->tunnel_type) {
1694 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1695 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG
1696 ipv6_encap_size, e->h_dest, ttl,
1697 &fl6.daddr,
1698 &fl6.saddr, tun_key->tp_dst,
1699 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG
1700 break;
1701 default:
1702 err = -EOPNOTSUPP;
232c0013
HHZ
1703 goto destroy_neigh_entry;
1704 }
1705
1706 e->encap_size = ipv6_encap_size;
1707 e->encap_header = encap_header;
1708
1709 if (!(nud_state & NUD_VALID)) {
1710 neigh_event_send(n, NULL);
27902f08
WY
1711 err = -EAGAIN;
1712 goto out;
ce99f6b9
OG
1713 }
1714
1715 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 1716 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ
1717 if (err)
1718 goto destroy_neigh_entry;
1719
1720 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1721 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ
1722 neigh_release(n);
1723 return err;
1724
1725destroy_neigh_entry:
1726 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ce99f6b9 1727out:
ce99f6b9 1728 kfree(encap_header);
232c0013
HHZ
1729 if (n)
1730 neigh_release(n);
ce99f6b9
OG
1731 return err;
1732}
1733
a54e20b4
HHZ
1734static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1735 struct ip_tunnel_info *tun_info,
1736 struct net_device *mirred_dev,
45247bf2
OG
1737 struct net_device **encap_dev,
1738 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ
1739{
1740 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1ad9a00a 1741 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
a54e20b4 1742 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG
1743 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
1744 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 1745 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 1746 struct mlx5e_encap_entry *e;
45247bf2 1747 int tunnel_type, err = 0;
a54e20b4
HHZ
1748 uintptr_t hash_key;
1749 bool found = false;
a54e20b4 1750
2fcd82e9 1751 /* udp dst port must be set */
a54e20b4 1752 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 1753 goto vxlan_encap_offload_err;
a54e20b4 1754
cd377663 1755 /* setting udp src port isn't supported */
2fcd82e9
OG
1756 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
1757vxlan_encap_offload_err:
1758 netdev_warn(priv->netdev,
1759 "must set udp dst port and not set udp src port\n");
cd377663 1760 return -EOPNOTSUPP;
2fcd82e9 1761 }
cd377663 1762
1ad9a00a 1763 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 1764 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ
1765 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
1766 } else {
2fcd82e9
OG
1767 netdev_warn(priv->netdev,
1768 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ
1769 return -EOPNOTSUPP;
1770 }
1771
76f7444d 1772 hash_key = hash_encap_info(key);
a54e20b4
HHZ
1773
1774 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
1775 encap_hlist, hash_key) {
76f7444d 1776 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ
1777 found = true;
1778 break;
1779 }
1780 }
1781
45247bf2
OG
1782 if (found)
1783 goto attach_flow;
a54e20b4
HHZ
1784
1785 e = kzalloc(sizeof(*e), GFP_KERNEL);
1786 if (!e)
1787 return -ENOMEM;
1788
76f7444d 1789 e->tun_info = *tun_info;
a54e20b4
HHZ
1790 e->tunnel_type = tunnel_type;
1791 INIT_LIST_HEAD(&e->flows);
1792
ce99f6b9 1793 if (family == AF_INET)
1a8552bd 1794 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 1795 else if (family == AF_INET6)
1a8552bd 1796 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 1797
232c0013 1798 if (err && err != -EAGAIN)
a54e20b4
HHZ
1799 goto out_err;
1800
a54e20b4
HHZ
1801 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
1802
45247bf2
OG
1803attach_flow:
1804 list_add(&flow->encap, &e->flows);
1805 *encap_dev = e->out_dev;
232c0013
HHZ
1806 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1807 attr->encap_id = e->encap_id;
45247bf2 1808
232c0013 1809 return err;
a54e20b4
HHZ
1810
1811out_err:
1812 kfree(e);
1813 return err;
1814}
1815
03a9d11e 1816static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 1817 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 1818 struct mlx5e_tc_flow *flow)
03a9d11e 1819{
ecf5bb79 1820 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 1821 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 1822 struct ip_tunnel_info *info = NULL;
03a9d11e 1823 const struct tc_action *a;
22dc13c8 1824 LIST_HEAD(actions);
a54e20b4 1825 bool encap = false;
232c0013 1826 int err = 0;
03a9d11e
OG
1827
1828 if (tc_no_actions(exts))
1829 return -EINVAL;
1830
776b12b6 1831 memset(attr, 0, sizeof(*attr));
1d447a39 1832 attr->in_rep = rpriv->rep;
03a9d11e 1833
22dc13c8
WC
1834 tcf_exts_to_list(exts, &actions);
1835 list_for_each_entry(a, &actions, list) {
03a9d11e 1836 if (is_tcf_gact_shot(a)) {
8b32580d
OG
1837 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
1838 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG
1839 continue;
1840 }
1841
d7e75a32
OG
1842 if (is_tcf_pedit(a)) {
1843 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
1844 parse_attr);
1845 if (err)
1846 return err;
1847
1848 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1849 continue;
1850 }
1851
26c02749
OG
1852 if (is_tcf_csum(a)) {
1853 if (csum_offload_supported(priv, attr->action,
1854 tcf_csum_update_flags(a)))
1855 continue;
1856
1857 return -EOPNOTSUPP;
1858 }
1859
5724b8b5 1860 if (is_tcf_mirred_egress_redirect(a)) {
03a9d11e 1861 int ifindex = tcf_mirred_ifindex(a);
45247bf2 1862 struct net_device *out_dev, *encap_dev = NULL;
03a9d11e 1863 struct mlx5e_priv *out_priv;
03a9d11e
OG
1864
1865 out_dev = __dev_get_by_index(dev_net(priv->netdev), ifindex);
1866
a54e20b4
HHZ
1867 if (switchdev_port_same_parent_id(priv->netdev,
1868 out_dev)) {
1869 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1870 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1871 out_priv = netdev_priv(out_dev);
1d447a39
SM
1872 rpriv = out_priv->ppriv;
1873 attr->out_rep = rpriv->rep;
a54e20b4
HHZ
1874 } else if (encap) {
1875 err = mlx5e_attach_encap(priv, info,
45247bf2 1876 out_dev, &encap_dev, flow);
232c0013 1877 if (err && err != -EAGAIN)
a54e20b4 1878 return err;
a54e20b4
HHZ
1879 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
1880 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1881 MLX5_FLOW_CONTEXT_ACTION_COUNT;
45247bf2 1882 out_priv = netdev_priv(encap_dev);
1d447a39
SM
1883 rpriv = out_priv->ppriv;
1884 attr->out_rep = rpriv->rep;
232c0013 1885 attr->parse_attr = parse_attr;
a54e20b4 1886 } else {
03a9d11e
OG
1887 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
1888 priv->netdev->name, out_dev->name);
1889 return -EINVAL;
1890 }
a54e20b4
HHZ
1891 continue;
1892 }
03a9d11e 1893
a54e20b4
HHZ
1894 if (is_tcf_tunnel_set(a)) {
1895 info = tcf_tunnel_info(a);
1896 if (info)
1897 encap = true;
1898 else
1899 return -EOPNOTSUPP;
03a9d11e
OG
1900 continue;
1901 }
1902
8b32580d 1903 if (is_tcf_vlan(a)) {
09c91ddf 1904 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 1905 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 1906 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d
OG
1907 if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
1908 return -EOPNOTSUPP;
1909
1910 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1911 attr->vlan = tcf_vlan_push_vid(a);
09c91ddf
OG
1912 } else { /* action is TCA_VLAN_ACT_MODIFY */
1913 return -EOPNOTSUPP;
8b32580d
OG
1914 }
1915 continue;
1916 }
1917
bbd00f7e
HHZ
1918 if (is_tcf_tunnel_release(a)) {
1919 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
1920 continue;
1921 }
1922
03a9d11e
OG
1923 return -EINVAL;
1924 }
232c0013 1925 return err;
03a9d11e
OG
1926}
1927
e3a2b7ed
AV
1928int mlx5e_configure_flower(struct mlx5e_priv *priv, __be16 protocol,
1929 struct tc_cls_flower_offload *f)
1930{
3bc4b7bf 1931 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 1932 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 1933 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG
1934 struct mlx5e_tc_flow *flow;
1935 int attr_size, err = 0;
65ba8fb7 1936 u8 flow_flags = 0;
e3a2b7ed 1937
65ba8fb7
OG
1938 if (esw && esw->mode == SRIOV_OFFLOADS) {
1939 flow_flags = MLX5E_TC_FLOW_ESWITCH;
1940 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG
1941 } else {
1942 flow_flags = MLX5E_TC_FLOW_NIC;
1943 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 1944 }
e3a2b7ed 1945
65ba8fb7 1946 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 1947 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 1948 if (!parse_attr || !flow) {
e3a2b7ed
AV
1949 err = -ENOMEM;
1950 goto err_free;
1951 }
1952
1953 flow->cookie = f->cookie;
65ba8fb7 1954 flow->flags = flow_flags;
e3a2b7ed 1955
17091853 1956 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV
1957 if (err < 0)
1958 goto err_free;
1959
65ba8fb7 1960 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 1961 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 1962 if (err < 0)
232c0013 1963 goto err_handle_encap_flow;
aa0cbbae 1964 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 1965 } else {
aa0cbbae 1966 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG
1967 if (err < 0)
1968 goto err_free;
aa0cbbae 1969 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 1970 }
e3a2b7ed 1971
e3a2b7ed
AV
1972 if (IS_ERR(flow->rule)) {
1973 err = PTR_ERR(flow->rule);
aa0cbbae 1974 goto err_free;
e3a2b7ed
AV
1975 }
1976
0b67a38f 1977 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
5c40348c
OG
1978 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1979 tc->ht_params);
1980 if (err)
1981 goto err_del_rule;
1982
232c0013
HHZ
1983 if (flow->flags & MLX5E_TC_FLOW_ESWITCH &&
1984 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
1985 kvfree(parse_attr);
1986 return err;
e3a2b7ed 1987
5c40348c 1988err_del_rule:
5e86397a 1989 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed 1990
232c0013
HHZ
1991err_handle_encap_flow:
1992 if (err == -EAGAIN) {
1993 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1994 tc->ht_params);
1995 if (err)
1996 mlx5e_tc_del_flow(priv, flow);
1997 else
1998 return 0;
1999 }
2000
e3a2b7ed 2001err_free:
17091853 2002 kvfree(parse_attr);
232c0013 2003 kfree(flow);
e3a2b7ed
AV
2004 return err;
2005}
2006
2007int mlx5e_delete_flower(struct mlx5e_priv *priv,
2008 struct tc_cls_flower_offload *f)
2009{
2010 struct mlx5e_tc_flow *flow;
acff797c 2011 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV
2012
2013 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2014 tc->ht_params);
2015 if (!flow)
2016 return -EINVAL;
2017
2018 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2019
961e8979 2020 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV
2021
2022 kfree(flow);
2023
2024 return 0;
2025}
2026
aad7e08d
AV
2027int mlx5e_stats_flower(struct mlx5e_priv *priv,
2028 struct tc_cls_flower_offload *f)
2029{
2030 struct mlx5e_tc_table *tc = &priv->fs.tc;
2031 struct mlx5e_tc_flow *flow;
aad7e08d
AV
2032 struct mlx5_fc *counter;
2033 u64 bytes;
2034 u64 packets;
2035 u64 lastuse;
2036
2037 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2038 tc->ht_params);
2039 if (!flow)
2040 return -EINVAL;
2041
0b67a38f
HHZ
2042 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2043 return 0;
2044
aad7e08d
AV
2045 counter = mlx5_flow_rule_counter(flow->rule);
2046 if (!counter)
2047 return 0;
2048
2049 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2050
d897a638 2051 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2052
aad7e08d
AV
2053 return 0;
2054}
2055
e8f887ac
AV
2056static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2057 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2058 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2059 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2060 .automatic_shrinking = true,
2061};
2062
2063int mlx5e_tc_init(struct mlx5e_priv *priv)
2064{
acff797c 2065 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2066
11c9c548
OG
2067 hash_init(tc->mod_hdr_tbl);
2068
e8f887ac
AV
2069 tc->ht_params = mlx5e_tc_flow_ht_params;
2070 return rhashtable_init(&tc->ht, &tc->ht_params);
2071}
2072
2073static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2074{
2075 struct mlx5e_tc_flow *flow = ptr;
2076 struct mlx5e_priv *priv = arg;
2077
961e8979 2078 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV
2079 kfree(flow);
2080}
2081
2082void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2083{
acff797c 2084 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV
2085
2086 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2087
acff797c
MG
2088 if (!IS_ERR_OR_NULL(tc->t)) {
2089 mlx5_destroy_flow_table(tc->t);
2090 tc->t = NULL;
e8f887ac
AV
2091 }
2092}