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net/mlx5: E-Switch, Use vport metadata matching only when mandatory
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
5a7e5bcb 41#include <linux/refcount.h>
db76ca24 42#include <linux/completion.h>
03a9d11e 43#include <net/tc_act/tc_mirred.h>
776b12b6 44#include <net/tc_act/tc_vlan.h>
bbd00f7e 45#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 46#include <net/tc_act/tc_pedit.h>
26c02749 47#include <net/tc_act/tc_csum.h>
f6dfb4c3 48#include <net/arp.h>
3616d08b 49#include <net/ipv6_stubs.h>
e8f887ac 50#include "en.h"
1d447a39 51#include "en_rep.h"
232c0013 52#include "en_tc.h"
03a9d11e 53#include "eswitch.h"
39ac237c 54#include "eswitch_offloads_chains.h"
3f6d08d1 55#include "fs_core.h"
2c81bfd5 56#include "en/port.h"
101f4de9 57#include "en/tc_tun.h"
04de7dda 58#include "lib/devcom.h"
9272e3df 59#include "lib/geneve.h"
7a978759 60#include "diag/en_tc_tracepoint.h"
e8f887ac 61
3bc4b7bf
OG		 62struct mlx5_nic_flow_attr {
63 u32 action;
64 u32 flow_tag;
2b688ea5 65 struct mlx5_modify_hdr *modify_hdr;
5c65c564 66 u32 hairpin_tirn;
38aa51c1 67 u8 match_level;
3f6d08d1 68 struct mlx5_flow_table *hairpin_ft;
b8aee822 69 struct mlx5_fc *counter;
3bc4b7bf
OG		 70};
71
226f2ca3 72#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 73
65ba8fb7 74enum {
226f2ca3
VB		 75 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
76 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
77 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 78 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 79 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
80 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
81 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
82 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
83 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
84 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
85 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 86 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
65ba8fb7
OG		 87};
88
e4ad91f2
CM		 89#define MLX5E_TC_MAX_SPLITS 1
90
79baaec7
EB		 91/* Helper struct for accessing a struct containing list_head array.
92 * Containing struct
93 * |- Helper array
94 * [0] Helper item 0
95 * |- list_head item 0
96 * |- index (0)
97 * [1] Helper item 1
98 * |- list_head item 1
99 * |- index (1)
100 * To access the containing struct from one of the list_head items:
101 * 1. Get the helper item from the list_head item using
102 * helper item =
103 * container_of(list_head item, helper struct type, list_head field)
104 * 2. Get the contining struct from the helper item and its index in the array:
105 * containing struct =
106 * container_of(helper item, containing struct type, helper field[index])
107 */
108struct encap_flow_item {
948993f2 109 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 110 struct list_head list;
111 int index;
112};
113
e8f887ac
AV		 114struct mlx5e_tc_flow {
115 struct rhash_head node;
655dc3d2 116 struct mlx5e_priv *priv;
e8f887ac 117 u64 cookie;
226f2ca3 118 unsigned long flags;
e4ad91f2 119 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 120 /* Flow can be associated with multiple encap IDs.
121 * The number of encaps is bounded by the number of supported
122 * destinations.
123 */
124 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 125 struct mlx5e_tc_flow *peer_flow;
dd58edc3 126 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
11c9c548 127 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
e4f9abbd 128 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 129 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 130 struct list_head peer; /* flows with peer flow */
b4a23329 131 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
2a1f1768 132 int tmp_efi_index;
6a06c2f7 133 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 134 refcount_t refcnt;
c5d326b2 135 struct rcu_head rcu_head;
95435ad7 136 struct completion init_done;
3bc4b7bf
OG		 137 union {
138 struct mlx5_esw_flow_attr esw_attr[0];
139 struct mlx5_nic_flow_attr nic_attr[0];
140 };
e8f887ac
AV		 141};
142
17091853 143struct mlx5e_tc_flow_parse_attr {
1f6da306 144 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 145 struct net_device *filter_dev;
17091853 146 struct mlx5_flow_spec spec;
d79b6df6 147 int num_mod_hdr_actions;
218d05ce 148 int max_mod_hdr_actions;
d79b6df6 149 void *mod_hdr_actions;
98b66cb1 150 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 151};
152
acff797c 153#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 154#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 155
77ab67b7
OG		 156struct mlx5e_hairpin {
157 struct mlx5_hairpin *pair;
158
159 struct mlx5_core_dev *func_mdev;
3f6d08d1 160 struct mlx5e_priv *func_priv;
77ab67b7
OG		 161 u32 tdn;
162 u32 tirn;
3f6d08d1
OG		 163
164 int num_channels;
165 struct mlx5e_rqt indir_rqt;
166 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
167 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 168};
169
5c65c564
OG		 170struct mlx5e_hairpin_entry {
171 /* a node of a hash table which keeps all the hairpin entries */
172 struct hlist_node hairpin_hlist;
173
73edca73
VB		 174 /* protects flows list */
175 spinlock_t flows_lock;
5c65c564
OG		 176 /* flows sharing the same hairpin */
177 struct list_head flows;
db76ca24
VB		 178 /* hpe's that were not fully initialized when dead peer update event
179 * function traversed them.
180 */
181 struct list_head dead_peer_wait_list;
5c65c564 182
d8822868 183 u16 peer_vhca_id;
106be53b 184 u8 prio;
5c65c564 185 struct mlx5e_hairpin *hp;
e4f9abbd 186 refcount_t refcnt;
db76ca24 187 struct completion res_ready;
5c65c564
OG		 188};
189
11c9c548
OG		 190struct mod_hdr_key {
191 int num_actions;
192 void *actions;
193};
194
195struct mlx5e_mod_hdr_entry {
196 /* a node of a hash table which keeps all the mod_hdr entries */
197 struct hlist_node mod_hdr_hlist;
198
83a52f0d
VB		 199 /* protects flows list */
200 spinlock_t flows_lock;
11c9c548
OG		 201 /* flows sharing the same mod_hdr entry */
202 struct list_head flows;
203
204 struct mod_hdr_key key;
205
2b688ea5 206 struct mlx5_modify_hdr *modify_hdr;
dd58edc3
VB		 207
208 refcount_t refcnt;
a734d007
VB		 209 struct completion res_ready;
210 int compl_result;
11c9c548
OG		 211};
212
213#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
214
5a7e5bcb
VB		 215static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
216 struct mlx5e_tc_flow *flow);
217
218static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
219{
220 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
221 return ERR_PTR(-EINVAL);
222 return flow;
223}
224
225static void mlx5e_flow_put(struct mlx5e_priv *priv,
226 struct mlx5e_tc_flow *flow)
227{
228 if (refcount_dec_and_test(&flow->refcnt)) {
229 mlx5e_tc_del_flow(priv, flow);
c5d326b2 230 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 231 }
232}
233
226f2ca3
VB		 234static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
235{
236 /* Complete all memory stores before setting bit. */
237 smp_mb__before_atomic();
238 set_bit(flag, &flow->flags);
239}
240
241#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
242
c5d326b2
VB		 243static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
244 unsigned long flag)
245{
246 /* test_and_set_bit() provides all necessary barriers */
247 return test_and_set_bit(flag, &flow->flags);
248}
249
250#define flow_flag_test_and_set(flow, flag) \
251 __flow_flag_test_and_set(flow, \
252 MLX5E_TC_FLOW_FLAG_##flag)
253
226f2ca3
VB		 254static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
255{
256 /* Complete all memory stores before clearing bit. */
257 smp_mb__before_atomic();
258 clear_bit(flag, &flow->flags);
259}
260
261#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
262 MLX5E_TC_FLOW_FLAG_##flag)
263
264static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
265{
266 bool ret = test_bit(flag, &flow->flags);
267
268 /* Read fields of flow structure only after checking flags. */
269 smp_mb__after_atomic();
270 return ret;
271}
272
273#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
274 MLX5E_TC_FLOW_FLAG_##flag)
275
276static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
277{
278 return flow_flag_test(flow, ESWITCH);
279}
280
84179981
PB		 281static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
282{
283 return flow_flag_test(flow, FT);
284}
285
226f2ca3
VB		 286static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
287{
288 return flow_flag_test(flow, OFFLOADED);
289}
290
11c9c548
OG		 291static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
292{
293 return jhash(key->actions,
294 key->num_actions * MLX5_MH_ACT_SZ, 0);
295}
296
297static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
298 struct mod_hdr_key *b)
299{
300 if (a->num_actions != b->num_actions)
301 return 1;
302
303 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
304}
305
dd58edc3
VB		 306static struct mod_hdr_tbl *
307get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
308{
309 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
310
311 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
312 &priv->fs.tc.mod_hdr;
313}
314
315static struct mlx5e_mod_hdr_entry *
316mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
317{
318 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
319
320 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
321 if (!cmp_mod_hdr_info(&mh->key, key)) {
322 refcount_inc(&mh->refcnt);
323 found = mh;
324 break;
325 }
326 }
327
328 return found;
329}
330
331static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
d2faae25
VB		 332 struct mlx5e_mod_hdr_entry *mh,
333 int namespace)
dd58edc3 334{
d2faae25
VB		 335 struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
336
337 if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
dd58edc3 338 return;
d2faae25
VB		 339 hash_del(&mh->mod_hdr_hlist);
340 mutex_unlock(&tbl->lock);
dd58edc3
VB		 341
342 WARN_ON(!list_empty(&mh->flows));
a734d007 343 if (mh->compl_result > 0)
2b688ea5 344 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
d2faae25 345
dd58edc3
VB		 346 kfree(mh);
347}
348
d2faae25
VB		 349static int get_flow_name_space(struct mlx5e_tc_flow *flow)
350{
351 return mlx5e_is_eswitch_flow(flow) ?
352 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
353}
11c9c548
OG		 354static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
355 struct mlx5e_tc_flow *flow,
356 struct mlx5e_tc_flow_parse_attr *parse_attr)
357{
11c9c548
OG		 358 int num_actions, actions_size, namespace, err;
359 struct mlx5e_mod_hdr_entry *mh;
dd58edc3 360 struct mod_hdr_tbl *tbl;
11c9c548 361 struct mod_hdr_key key;
11c9c548
OG		 362 u32 hash_key;
363
364 num_actions = parse_attr->num_mod_hdr_actions;
365 actions_size = MLX5_MH_ACT_SZ * num_actions;
366
367 key.actions = parse_attr->mod_hdr_actions;
368 key.num_actions = num_actions;
369
370 hash_key = hash_mod_hdr_info(&key);
371
d2faae25 372 namespace = get_flow_name_space(flow);
dd58edc3 373 tbl = get_mod_hdr_table(priv, namespace);
11c9c548 374
d2faae25 375 mutex_lock(&tbl->lock);
dd58edc3 376 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
a734d007
VB		 377 if (mh) {
378 mutex_unlock(&tbl->lock);
379 wait_for_completion(&mh->res_ready);
380
381 if (mh->compl_result < 0) {
382 err = -EREMOTEIO;
383 goto attach_header_err;
384 }
11c9c548 385 goto attach_flow;
a734d007 386 }
11c9c548
OG		 387
388 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
d2faae25 389 if (!mh) {
a734d007
VB		 390 mutex_unlock(&tbl->lock);
391 return -ENOMEM;
d2faae25 392 }
11c9c548
OG		 393
394 mh->key.actions = (void *)mh + sizeof(*mh);
395 memcpy(mh->key.actions, key.actions, actions_size);
396 mh->key.num_actions = num_actions;
83a52f0d 397 spin_lock_init(&mh->flows_lock);
11c9c548 398 INIT_LIST_HEAD(&mh->flows);
dd58edc3 399 refcount_set(&mh->refcnt, 1);
a734d007
VB		 400 init_completion(&mh->res_ready);
401
402 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
403 mutex_unlock(&tbl->lock);
11c9c548 404
2b688ea5
MG		 405 mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
406 mh->key.num_actions,
407 mh->key.actions);
408 if (IS_ERR(mh->modify_hdr)) {
409 err = PTR_ERR(mh->modify_hdr);
a734d007
VB		 410 mh->compl_result = err;
411 goto alloc_header_err;
412 }
413 mh->compl_result = 1;
414 complete_all(&mh->res_ready);
11c9c548
OG		 415
416attach_flow:
dd58edc3 417 flow->mh = mh;
83a52f0d 418 spin_lock(&mh->flows_lock);
11c9c548 419 list_add(&flow->mod_hdr, &mh->flows);
83a52f0d 420 spin_unlock(&mh->flows_lock);
d2faae25 421 if (mlx5e_is_eswitch_flow(flow))
2b688ea5 422 flow->esw_attr->modify_hdr = mh->modify_hdr;
11c9c548 423 else
2b688ea5 424 flow->nic_attr->modify_hdr = mh->modify_hdr;
11c9c548
OG		 425
426 return 0;
427
a734d007
VB		 428alloc_header_err:
429 complete_all(&mh->res_ready);
430attach_header_err:
431 mlx5e_mod_hdr_put(priv, mh, namespace);
11c9c548
OG		 432 return err;
433}
434
435static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
436 struct mlx5e_tc_flow *flow)
437{
5a7e5bcb 438 /* flow wasn't fully initialized */
dd58edc3 439 if (!flow->mh)
5a7e5bcb
VB		 440 return;
441
83a52f0d 442 spin_lock(&flow->mh->flows_lock);
11c9c548 443 list_del(&flow->mod_hdr);
83a52f0d 444 spin_unlock(&flow->mh->flows_lock);
11c9c548 445
d2faae25 446 mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
dd58edc3 447 flow->mh = NULL;
11c9c548
OG		 448}
449
77ab67b7
OG		 450static
451struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
452{
453 struct net_device *netdev;
454 struct mlx5e_priv *priv;
455
456 netdev = __dev_get_by_index(net, ifindex);
457 priv = netdev_priv(netdev);
458 return priv->mdev;
459}
460
461static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
462{
463 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
464 void *tirc;
465 int err;
466
467 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
468 if (err)
469 goto alloc_tdn_err;
470
471 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
472
473 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 474 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 475 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
476
477 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
478 if (err)
479 goto create_tir_err;
480
481 return 0;
482
483create_tir_err:
484 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
485alloc_tdn_err:
486 return err;
487}
488
489static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
490{
491 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
492 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
493}
494
3f6d08d1
OG		 495static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
496{
497 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
498 struct mlx5e_priv *priv = hp->func_priv;
499 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
500
501 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
502 hp->num_channels);
503
504 for (i = 0; i < sz; i++) {
505 ix = i;
bbeb53b8 506 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 507 ix = mlx5e_bits_invert(i, ilog2(sz));
508 ix = indirection_rqt[ix];
509 rqn = hp->pair->rqn[ix];
510 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
511 }
512}
513
514static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
515{
516 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
517 struct mlx5e_priv *priv = hp->func_priv;
518 struct mlx5_core_dev *mdev = priv->mdev;
519 void *rqtc;
520 u32 *in;
521
522 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
523 in = kvzalloc(inlen, GFP_KERNEL);
524 if (!in)
525 return -ENOMEM;
526
527 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
528
529 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
530 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
531
532 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
533
534 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
535 if (!err)
536 hp->indir_rqt.enabled = true;
537
538 kvfree(in);
539 return err;
540}
541
542static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
543{
544 struct mlx5e_priv *priv = hp->func_priv;
545 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
546 int tt, i, err;
547 void *tirc;
548
549 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 550 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
551
3f6d08d1
OG		 552 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
553 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
554
555 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
556 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
557 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 558 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
559
3f6d08d1
OG		 560 err = mlx5_core_create_tir(hp->func_mdev, in,
561 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
562 if (err) {
563 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
564 goto err_destroy_tirs;
565 }
566 }
567 return 0;
568
569err_destroy_tirs:
570 for (i = 0; i < tt; i++)
571 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
572 return err;
573}
574
575static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
576{
577 int tt;
578
579 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
580 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
581}
582
583static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
584 struct ttc_params *ttc_params)
585{
586 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
587 int tt;
588
589 memset(ttc_params, 0, sizeof(*ttc_params));
590
591 ttc_params->any_tt_tirn = hp->tirn;
592
593 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
594 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
595
6412bb39 596 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 597 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
598 ft_attr->prio = MLX5E_TC_PRIO;
599}
600
601static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
602{
603 struct mlx5e_priv *priv = hp->func_priv;
604 struct ttc_params ttc_params;
605 int err;
606
607 err = mlx5e_hairpin_create_indirect_rqt(hp);
608 if (err)
609 return err;
610
611 err = mlx5e_hairpin_create_indirect_tirs(hp);
612 if (err)
613 goto err_create_indirect_tirs;
614
615 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
616 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
617 if (err)
618 goto err_create_ttc_table;
619
620 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
621 hp->num_channels, hp->ttc.ft.t->id);
622
623 return 0;
624
625err_create_ttc_table:
626 mlx5e_hairpin_destroy_indirect_tirs(hp);
627err_create_indirect_tirs:
628 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
629
630 return err;
631}
632
633static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
634{
635 struct mlx5e_priv *priv = hp->func_priv;
636
637 mlx5e_destroy_ttc_table(priv, &hp->ttc);
638 mlx5e_hairpin_destroy_indirect_tirs(hp);
639 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
640}
641
77ab67b7
OG		 642static struct mlx5e_hairpin *
643mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
644 int peer_ifindex)
645{
646 struct mlx5_core_dev *func_mdev, *peer_mdev;
647 struct mlx5e_hairpin *hp;
648 struct mlx5_hairpin *pair;
649 int err;
650
651 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
652 if (!hp)
653 return ERR_PTR(-ENOMEM);
654
655 func_mdev = priv->mdev;
656 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
657
658 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
659 if (IS_ERR(pair)) {
660 err = PTR_ERR(pair);
661 goto create_pair_err;
662 }
663 hp->pair = pair;
664 hp->func_mdev = func_mdev;
3f6d08d1
OG		 665 hp->func_priv = priv;
666 hp->num_channels = params->num_channels;
77ab67b7
OG		 667
668 err = mlx5e_hairpin_create_transport(hp);
669 if (err)
670 goto create_transport_err;
671
3f6d08d1
OG		 672 if (hp->num_channels > 1) {
673 err = mlx5e_hairpin_rss_init(hp);
674 if (err)
675 goto rss_init_err;
676 }
677
77ab67b7
OG		 678 return hp;
679
3f6d08d1
OG		 680rss_init_err:
681 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 682create_transport_err:
683 mlx5_core_hairpin_destroy(hp->pair);
684create_pair_err:
685 kfree(hp);
686 return ERR_PTR(err);
687}
688
689static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
690{
3f6d08d1
OG		 691 if (hp->num_channels > 1)
692 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 693 mlx5e_hairpin_destroy_transport(hp);
694 mlx5_core_hairpin_destroy(hp->pair);
695 kvfree(hp);
696}
697
106be53b
OG		 698static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
699{
700 return (peer_vhca_id << 16 | prio);
701}
702
5c65c564 703static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 704 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 705{
706 struct mlx5e_hairpin_entry *hpe;
106be53b 707 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 708
709 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 710 hairpin_hlist, hash_key) {
e4f9abbd
VB		 711 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
712 refcount_inc(&hpe->refcnt);
5c65c564 713 return hpe;
e4f9abbd 714 }
5c65c564
OG		 715 }
716
717 return NULL;
718}
719
e4f9abbd
VB		 720static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
721 struct mlx5e_hairpin_entry *hpe)
722{
723 /* no more hairpin flows for us, release the hairpin pair */
b32accda 724 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 725 return;
b32accda
VB		 726 hash_del(&hpe->hairpin_hlist);
727 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 728
db76ca24
VB		 729 if (!IS_ERR_OR_NULL(hpe->hp)) {
730 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
731 dev_name(hpe->hp->pair->peer_mdev->device));
732
733 mlx5e_hairpin_destroy(hpe->hp);
734 }
e4f9abbd
VB		 735
736 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 737 kfree(hpe);
738}
739
106be53b
OG		 740#define UNKNOWN_MATCH_PRIO 8
741
742static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 743 struct mlx5_flow_spec *spec, u8 *match_prio,
744 struct netlink_ext_ack *extack)
106be53b
OG		 745{
746 void *headers_c, *headers_v;
747 u8 prio_val, prio_mask = 0;
748 bool vlan_present;
749
750#ifdef CONFIG_MLX5_CORE_EN_DCB
751 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 752 NL_SET_ERR_MSG_MOD(extack,
753 "only PCP trust state supported for hairpin");
106be53b
OG		 754 return -EOPNOTSUPP;
755 }
756#endif
757 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
758 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
759
760 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
761 if (vlan_present) {
762 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
763 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
764 }
765
766 if (!vlan_present || !prio_mask) {
767 prio_val = UNKNOWN_MATCH_PRIO;
768 } else if (prio_mask != 0x7) {
e98bedf5
EB		 769 NL_SET_ERR_MSG_MOD(extack,
770 "masked priority match not supported for hairpin");
106be53b
OG		 771 return -EOPNOTSUPP;
772 }
773
774 *match_prio = prio_val;
775 return 0;
776}
777
5c65c564
OG		 778static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
779 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 780 struct mlx5e_tc_flow_parse_attr *parse_attr,
781 struct netlink_ext_ack *extack)
5c65c564 782{
98b66cb1 783 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 784 struct mlx5_hairpin_params params;
d8822868 785 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 786 struct mlx5e_hairpin_entry *hpe;
787 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 788 u64 link_speed64;
789 u32 link_speed;
106be53b 790 u8 match_prio;
d8822868 791 u16 peer_id;
5c65c564
OG		 792 int err;
793
d8822868
OG		 794 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
795 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 796 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 797 return -EOPNOTSUPP;
798 }
799
d8822868 800 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 801 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
802 extack);
106be53b
OG		 803 if (err)
804 return err;
b32accda
VB		 805
806 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 807 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 808 if (hpe) {
809 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
810 wait_for_completion(&hpe->res_ready);
811
812 if (IS_ERR(hpe->hp)) {
813 err = -EREMOTEIO;
814 goto out_err;
815 }
5c65c564 816 goto attach_flow;
db76ca24 817 }
5c65c564
OG		 818
819 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 820 if (!hpe) {
db76ca24
VB		 821 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
822 return -ENOMEM;
b32accda 823 }
5c65c564 824
73edca73 825 spin_lock_init(&hpe->flows_lock);
5c65c564 826 INIT_LIST_HEAD(&hpe->flows);
db76ca24 827 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 828 hpe->peer_vhca_id = peer_id;
106be53b 829 hpe->prio = match_prio;
e4f9abbd 830 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 831 init_completion(&hpe->res_ready);
832
833 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
834 hash_hairpin_info(peer_id, match_prio));
835 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 836
837 params.log_data_size = 15;
838 params.log_data_size = min_t(u8, params.log_data_size,
839 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
840 params.log_data_size = max_t(u8, params.log_data_size,
841 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 842
eb9180f7
OG		 843 params.log_num_packets = params.log_data_size -
844 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
845 params.log_num_packets = min_t(u8, params.log_num_packets,
846 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
847
848 params.q_counter = priv->q_counter;
3f6d08d1 849 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 850 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 851 link_speed = max_t(u32, link_speed, 50000);
852 link_speed64 = link_speed;
853 do_div(link_speed64, 50000);
854 params.num_channels = link_speed64;
855
5c65c564 856 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 857 hpe->hp = hp;
858 complete_all(&hpe->res_ready);
5c65c564
OG		 859 if (IS_ERR(hp)) {
860 err = PTR_ERR(hp);
db76ca24 861 goto out_err;
5c65c564
OG		 862 }
863
eb9180f7 864 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 865 hp->tirn, hp->pair->rqn[0],
866 dev_name(hp->pair->peer_mdev->device),
eb9180f7 867 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 868
5c65c564 869attach_flow:
3f6d08d1 870 if (hpe->hp->num_channels > 1) {
226f2ca3 871 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 872 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
873 } else {
874 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
875 }
b32accda 876
e4f9abbd 877 flow->hpe = hpe;
73edca73 878 spin_lock(&hpe->flows_lock);
5c65c564 879 list_add(&flow->hairpin, &hpe->flows);
73edca73 880 spin_unlock(&hpe->flows_lock);
3f6d08d1 881
5c65c564
OG		 882 return 0;
883
db76ca24
VB		 884out_err:
885 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 886 return err;
887}
888
889static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
890 struct mlx5e_tc_flow *flow)
891{
5a7e5bcb 892 /* flow wasn't fully initialized */
e4f9abbd 893 if (!flow->hpe)
5a7e5bcb
VB		 894 return;
895
73edca73 896 spin_lock(&flow->hpe->flows_lock);
5c65c564 897 list_del(&flow->hairpin);
73edca73
VB		 898 spin_unlock(&flow->hpe->flows_lock);
899
e4f9abbd
VB		 900 mlx5e_hairpin_put(priv, flow->hpe);
901 flow->hpe = NULL;
5c65c564
OG		 902}
903
c83954ab 904static int
74491de9 905mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 906 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 907 struct mlx5e_tc_flow *flow,
908 struct netlink_ext_ack *extack)
e8f887ac 909{
bb0ee7dc 910 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 911 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 912 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 913 struct mlx5_flow_destination dest[2] = {};
66958ed9 914 struct mlx5_flow_act flow_act = {
3bc4b7bf 915 .action = attr->action,
bb0ee7dc 916 .flags = FLOW_ACT_NO_APPEND,
66958ed9 917 };
aad7e08d 918 struct mlx5_fc *counter = NULL;
5c65c564 919 int err, dest_ix = 0;
e8f887ac 920
bb0ee7dc
JL		 921 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
922 flow_context->flow_tag = attr->flow_tag;
923
226f2ca3 924 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 925 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 926 if (err)
927 return err;
928
226f2ca3 929 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 930 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
931 dest[dest_ix].ft = attr->hairpin_ft;
932 } else {
5c65c564
OG		 933 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
934 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 935 }
936 dest_ix++;
3f6d08d1
OG		 937 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
938 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
939 dest[dest_ix].ft = priv->fs.vlan.ft.t;
940 dest_ix++;
5c65c564 941 }
aad7e08d 942
5c65c564
OG		 943 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
944 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 945 if (IS_ERR(counter))
946 return PTR_ERR(counter);
947
5c65c564 948 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 949 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 950 dest_ix++;
b8aee822 951 attr->counter = counter;
aad7e08d
AV		 952 }
953
2f4fe4ca 954 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 955 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2b688ea5 956 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 957 kfree(parse_attr->mod_hdr_actions);
c83954ab 958 if (err)
5a7e5bcb 959 return err;
2f4fe4ca
OG		 960 }
961
b6fac0b4 962 mutex_lock(&priv->fs.tc.t_lock);
acff797c 963 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
61dc7b01
PB		 964 struct mlx5_flow_table_attr ft_attr = {};
965 int tc_grp_size, tc_tbl_size, tc_num_grps;
21b9c144
OG		 966 u32 max_flow_counter;
967
968 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
969 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
970
971 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
972
973 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
974 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
61dc7b01 975 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
21b9c144 976
61dc7b01
PB		 977 ft_attr.prio = MLX5E_TC_PRIO;
978 ft_attr.max_fte = tc_tbl_size;
979 ft_attr.level = MLX5E_TC_FT_LEVEL;
980 ft_attr.autogroup.max_num_groups = tc_num_grps;
acff797c
MG		 981 priv->fs.tc.t =
982 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
61dc7b01 983 &ft_attr);
acff797c 984 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 985 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5
EB		 986 NL_SET_ERR_MSG_MOD(extack,
987 "Failed to create tc offload table\n");
e8f887ac
AV		 988 netdev_err(priv->netdev,
989 "Failed to create tc offload table\n");
5a7e5bcb 990 return PTR_ERR(priv->fs.tc.t);
e8f887ac 991 }
e8f887ac
AV		 992 }
993
38aa51c1 994 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 995 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 996
c83954ab
RL		 997 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
998 &flow_act, dest, dest_ix);
b6fac0b4 999 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 1000
a2b7189b 1001 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1002}
1003
d85cdccb
OG		 1004static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1005 struct mlx5e_tc_flow *flow)
1006{
513f8f7f 1007 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 1008 struct mlx5_fc *counter = NULL;
1009
b8aee822 1010 counter = attr->counter;
5a7e5bcb
VB		 1011 if (!IS_ERR_OR_NULL(flow->rule[0]))
1012 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 1013 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 1014
b6fac0b4 1015 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 1016 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 1017 mlx5_destroy_flow_table(priv->fs.tc.t);
1018 priv->fs.tc.t = NULL;
1019 }
b6fac0b4 1020 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1021
513f8f7f 1022 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1023 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1024
226f2ca3 1025 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1026 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 1027}
1028
aa0cbbae 1029static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1030 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1031
3c37745e 1032static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1033 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1034 struct net_device *mirred_dev,
1035 int out_index,
8c4dc42b 1036 struct netlink_ext_ack *extack,
0ad060ee
RD		 1037 struct net_device **encap_dev,
1038 bool *encap_valid);
3c37745e 1039
6d2a3ed0
OG		 1040static struct mlx5_flow_handle *
1041mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1042 struct mlx5e_tc_flow *flow,
1043 struct mlx5_flow_spec *spec,
1044 struct mlx5_esw_flow_attr *attr)
1045{
1046 struct mlx5_flow_handle *rule;
1047
1048 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1049 if (IS_ERR(rule))
1050 return rule;
1051
e85e02ba 1052 if (attr->split_count) {
6d2a3ed0
OG		 1053 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1054 if (IS_ERR(flow->rule[1])) {
1055 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1056 return flow->rule[1];
1057 }
1058 }
1059
6d2a3ed0
OG		 1060 return rule;
1061}
1062
1063static void
1064mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1065 struct mlx5e_tc_flow *flow,
1066 struct mlx5_esw_flow_attr *attr)
1067{
226f2ca3 1068 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1069
e85e02ba 1070 if (attr->split_count)
6d2a3ed0
OG		 1071 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1072
1073 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1074}
1075
5dbe906f
PB		 1076static struct mlx5_flow_handle *
1077mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1078 struct mlx5e_tc_flow *flow,
178f69b4 1079 struct mlx5_flow_spec *spec)
5dbe906f 1080{
178f69b4 1081 struct mlx5_esw_flow_attr slow_attr;
5dbe906f
PB		 1082 struct mlx5_flow_handle *rule;
1083
178f69b4
EC		 1084 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1085 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1086 slow_attr.split_count = 0;
1087 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
5dbe906f 1088
178f69b4 1089 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr);
5dbe906f 1090 if (!IS_ERR(rule))
226f2ca3 1091 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1092
1093 return rule;
1094}
1095
1096static void
1097mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1098 struct mlx5e_tc_flow *flow)
5dbe906f 1099{
178f69b4
EC		 1100 struct mlx5_esw_flow_attr slow_attr;
1101
1102 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1103 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1104 slow_attr.split_count = 0;
1105 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1106 mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr);
226f2ca3 1107 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1108}
1109
ad86755b
VB		 1110/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1111 * function.
1112 */
1113static void unready_flow_add(struct mlx5e_tc_flow *flow,
1114 struct list_head *unready_flows)
1115{
1116 flow_flag_set(flow, NOT_READY);
1117 list_add_tail(&flow->unready, unready_flows);
1118}
1119
1120/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1121 * function.
1122 */
1123static void unready_flow_del(struct mlx5e_tc_flow *flow)
1124{
1125 list_del(&flow->unready);
1126 flow_flag_clear(flow, NOT_READY);
1127}
1128
b4a23329
RD		 1129static void add_unready_flow(struct mlx5e_tc_flow *flow)
1130{
1131 struct mlx5_rep_uplink_priv *uplink_priv;
1132 struct mlx5e_rep_priv *rpriv;
1133 struct mlx5_eswitch *esw;
1134
1135 esw = flow->priv->mdev->priv.eswitch;
1136 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1137 uplink_priv = &rpriv->uplink_priv;
1138
ad86755b
VB		 1139 mutex_lock(&uplink_priv->unready_flows_lock);
1140 unready_flow_add(flow, &uplink_priv->unready_flows);
1141 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1142}
1143
1144static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1145{
ad86755b
VB		 1146 struct mlx5_rep_uplink_priv *uplink_priv;
1147 struct mlx5e_rep_priv *rpriv;
1148 struct mlx5_eswitch *esw;
1149
1150 esw = flow->priv->mdev->priv.eswitch;
1151 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1152 uplink_priv = &rpriv->uplink_priv;
1153
1154 mutex_lock(&uplink_priv->unready_flows_lock);
1155 unready_flow_del(flow);
1156 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1157}
1158
c83954ab 1159static int
74491de9 1160mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1161 struct mlx5e_tc_flow *flow,
1162 struct netlink_ext_ack *extack)
adb4c123
OG		 1163{
1164 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 1165 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1166 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3c37745e 1167 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1168 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1169 struct mlx5e_rep_priv *rpriv;
1170 struct mlx5e_priv *out_priv;
0ad060ee 1171 bool encap_valid = true;
39ac237c 1172 u32 max_prio, max_chain;
0ad060ee 1173 int err = 0;
f493f155 1174 int out_index;
8b32580d 1175
39ac237c 1176 if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
61644c3d
RD		 1177 NL_SET_ERR_MSG_MOD(extack,
1178 "E-switch priorities unsupported, upgrade FW");
d14f6f2a
OG		 1179 return -EOPNOTSUPP;
1180 }
bf07aa73 1181
84179981
PB		 1182 /* We check chain range only for tc flows.
1183 * For ft flows, we checked attr->chain was originally 0 and set it to
1184 * FDB_FT_CHAIN which is outside tc range.
1185 * See mlx5e_rep_setup_ft_cb().
1186 */
39ac237c 1187 max_chain = mlx5_esw_chains_get_chain_range(esw);
84179981 1188 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1189 NL_SET_ERR_MSG_MOD(extack,
1190 "Requested chain is out of supported range");
5a7e5bcb 1191 return -EOPNOTSUPP;
bf07aa73
PB		 1192 }
1193
39ac237c 1194 max_prio = mlx5_esw_chains_get_prio_range(esw);
bf07aa73 1195 if (attr->prio > max_prio) {
61644c3d
RD		 1196 NL_SET_ERR_MSG_MOD(extack,
1197 "Requested priority is out of supported range");
5a7e5bcb 1198 return -EOPNOTSUPP;
bf07aa73 1199 }
e52c2802 1200
f493f155 1201 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1202 int mirred_ifindex;
1203
f493f155
EB		 1204 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1205 continue;
1206
7040632d 1207 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1208 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1209 mirred_ifindex);
733d4f36 1210 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1211 extack, &encap_dev, &encap_valid);
1212 if (err)
5a7e5bcb 1213 return err;
0ad060ee 1214
3c37745e
OG		 1215 out_priv = netdev_priv(encap_dev);
1216 rpriv = out_priv->ppriv;
1cc26d74
EB		 1217 attr->dests[out_index].rep = rpriv->rep;
1218 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1219 }
1220
8b32580d 1221 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1222 if (err)
5a7e5bcb 1223 return err;
adb4c123 1224
d7e75a32 1225 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1226 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1227 kfree(parse_attr->mod_hdr_actions);
c83954ab 1228 if (err)
5a7e5bcb 1229 return err;
d7e75a32
OG		 1230 }
1231
b8aee822 1232 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1233 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1234 if (IS_ERR(counter))
1235 return PTR_ERR(counter);
b8aee822
MB		 1236
1237 attr->counter = counter;
1238 }
1239
0ad060ee
RD		 1240 /* we get here if one of the following takes place:
1241 * (1) there's no error
1242 * (2) there's an encap action and we don't have valid neigh
3c37745e 1243 */
bc1d75fa 1244 if (!encap_valid)
178f69b4 1245 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1246 else
6d2a3ed0 1247 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1248
5a7e5bcb
VB		 1249 if (IS_ERR(flow->rule[0]))
1250 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1251 else
1252 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1253
1254 return 0;
aa0cbbae 1255}
d85cdccb 1256
9272e3df
YK		 1257static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1258{
1259 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1260 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1261 spec->match_value,
1262 misc_parameters_3);
1263 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1264 headers_v,
1265 geneve_tlv_option_0_data);
1266
1267 return !!geneve_tlv_opt_0_data;
1268}
1269
d85cdccb
OG		 1270static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1271 struct mlx5e_tc_flow *flow)
1272{
1273 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1274 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
f493f155 1275 int out_index;
d85cdccb 1276
226f2ca3 1277 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1278 remove_unready_flow(flow);
ef06c9ee
RD		 1279 kvfree(attr->parse_attr);
1280 return;
1281 }
1282
226f2ca3
VB		 1283 if (mlx5e_is_offloaded_flow(flow)) {
1284 if (flow_flag_test(flow, SLOW))
178f69b4 1285 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1286 else
1287 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1288 }
d85cdccb 1289
9272e3df
YK		 1290 if (mlx5_flow_has_geneve_opt(flow))
1291 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1292
513f8f7f 1293 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1294
f493f155 1295 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
2a4b6526 1296 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1297 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1298 kfree(attr->parse_attr->tun_info[out_index]);
1299 }
f493f155 1300 kvfree(attr->parse_attr);
d7e75a32 1301
513f8f7f 1302 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1303 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1304
1305 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1306 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1307}
1308
232c0013 1309void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1310 struct mlx5e_encap_entry *e,
1311 struct list_head *flow_list)
232c0013 1312{
3c37745e 1313 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1314 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0
OG		 1315 struct mlx5_flow_handle *rule;
1316 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1317 struct mlx5e_tc_flow *flow;
1318 int err;
1319
2b688ea5
MG		 1320 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1321 e->reformat_type,
1322 e->encap_size, e->encap_header,
1323 MLX5_FLOW_NAMESPACE_FDB);
1324 if (IS_ERR(e->pkt_reformat)) {
1325 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1326 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1327 return;
1328 }
1329 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1330 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1331
2a1f1768 1332 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1333 bool all_flow_encaps_valid = true;
1334 int i;
1335
95435ad7
VB		 1336 if (!mlx5e_is_offloaded_flow(flow))
1337 continue;
3c37745e 1338 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1339 spec = &esw_attr->parse_attr->spec;
1340
2b688ea5 1341 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1342 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1343 /* Flow can be associated with multiple encap entries.
1344 * Before offloading the flow verify that all of them have
1345 * a valid neighbour.
1346 */
1347 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1348 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1349 continue;
1350 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1351 all_flow_encaps_valid = false;
1352 break;
1353 }
1354 }
1355 /* Do not offload flows with unresolved neighbors */
1356 if (!all_flow_encaps_valid)
2a1f1768 1357 continue;
5dbe906f 1358 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1359 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1360 if (IS_ERR(rule)) {
1361 err = PTR_ERR(rule);
232c0013
HHZ		 1362 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1363 err);
2a1f1768 1364 continue;
232c0013 1365 }
5dbe906f 1366
178f69b4 1367 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1368 flow->rule[0] = rule;
226f2ca3
VB		 1369 /* was unset when slow path rule removed */
1370 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1371 }
1372}
1373
1374void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1375 struct mlx5e_encap_entry *e,
1376 struct list_head *flow_list)
232c0013 1377{
3c37745e 1378 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1379 struct mlx5_flow_handle *rule;
1380 struct mlx5_flow_spec *spec;
232c0013 1381 struct mlx5e_tc_flow *flow;
5dbe906f 1382 int err;
232c0013 1383
2a1f1768 1384 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1385 if (!mlx5e_is_offloaded_flow(flow))
1386 continue;
5dbe906f
PB		 1387 spec = &flow->esw_attr->parse_attr->spec;
1388
1389 /* update from encap rule to slow path rule */
178f69b4 1390 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1391 /* mark the flow's encap dest as non-valid */
2a1f1768 1392 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1393
1394 if (IS_ERR(rule)) {
1395 err = PTR_ERR(rule);
1396 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1397 err);
2a1f1768 1398 continue;
5dbe906f
PB		 1399 }
1400
1401 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1402 flow->rule[0] = rule;
226f2ca3
VB		 1403 /* was unset when fast path rule removed */
1404 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1405 }
1406
61c806da
OG		 1407 /* we know that the encap is valid */
1408 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1409 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1410}
1411
b8aee822
MB		 1412static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1413{
226f2ca3 1414 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1415 return flow->esw_attr->counter;
1416 else
1417 return flow->nic_attr->counter;
1418}
1419
2a1f1768
VB		 1420/* Takes reference to all flows attached to encap and adds the flows to
1421 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1422 */
1423void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1424{
1425 struct encap_flow_item *efi;
1426 struct mlx5e_tc_flow *flow;
1427
1428 list_for_each_entry(efi, &e->flows, list) {
1429 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1430 if (IS_ERR(mlx5e_flow_get(flow)))
1431 continue;
95435ad7 1432 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1433
1434 flow->tmp_efi_index = efi->index;
1435 list_add(&flow->tmp_list, flow_list);
1436 }
1437}
1438
6a06c2f7 1439/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1440void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1441{
1442 struct mlx5e_tc_flow *flow, *tmp;
1443
1444 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1445 mlx5e_flow_put(priv, flow);
1446}
1447
ac0d9176
VB		 1448static struct mlx5e_encap_entry *
1449mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1450 struct mlx5e_encap_entry *e)
1451{
1452 struct mlx5e_encap_entry *next = NULL;
1453
1454retry:
1455 rcu_read_lock();
1456
1457 /* find encap with non-zero reference counter value */
1458 for (next = e ?
1459 list_next_or_null_rcu(&nhe->encap_list,
1460 &e->encap_list,
1461 struct mlx5e_encap_entry,
1462 encap_list) :
1463 list_first_or_null_rcu(&nhe->encap_list,
1464 struct mlx5e_encap_entry,
1465 encap_list);
1466 next;
1467 next = list_next_or_null_rcu(&nhe->encap_list,
1468 &next->encap_list,
1469 struct mlx5e_encap_entry,
1470 encap_list))
1471 if (mlx5e_encap_take(next))
1472 break;
1473
1474 rcu_read_unlock();
1475
1476 /* release starting encap */
1477 if (e)
1478 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1479 if (!next)
1480 return next;
1481
1482 /* wait for encap to be fully initialized */
1483 wait_for_completion(&next->res_ready);
1484 /* continue searching if encap entry is not in valid state after completion */
1485 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1486 e = next;
1487 goto retry;
1488 }
1489
1490 return next;
1491}
1492
f6dfb4c3
HHZ		 1493void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1494{
1495 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1496 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1497 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1498 struct mlx5_fc *counter;
1499 struct neigh_table *tbl;
1500 bool neigh_used = false;
1501 struct neighbour *n;
90bb7692 1502 u64 lastuse;
f6dfb4c3
HHZ		 1503
1504 if (m_neigh->family == AF_INET)
1505 tbl = &arp_tbl;
1506#if IS_ENABLED(CONFIG_IPV6)
1507 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1508 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1509#endif
1510 else
1511 return;
1512
ac0d9176
VB		 1513 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1514 * next one.
1515 */
1516 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1517 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1518 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1519 struct mlx5_eswitch *esw;
1520 LIST_HEAD(flow_list);
948993f2 1521
6a06c2f7
VB		 1522 esw = priv->mdev->priv.eswitch;
1523 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1524 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1525 flow = container_of(efi, struct mlx5e_tc_flow,
1526 encaps[efi->index]);
5a7e5bcb
VB		 1527 if (IS_ERR(mlx5e_flow_get(flow)))
1528 continue;
6a06c2f7 1529 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1530
226f2ca3 1531 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1532 counter = mlx5e_tc_get_counter(flow);
90bb7692 1533 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1534 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1535 neigh_used = true;
1536 break;
1537 }
1538 }
1539 }
6a06c2f7 1540 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1541
6a06c2f7 1542 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1543 if (neigh_used) {
1544 /* release current encap before breaking the loop */
6a06c2f7 1545 mlx5e_encap_put(priv, e);
e36d4810 1546 break;
ac0d9176 1547 }
f6dfb4c3
HHZ		 1548 }
1549
c786fe59
VB		 1550 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1551
f6dfb4c3
HHZ		 1552 if (neigh_used) {
1553 nhe->reported_lastuse = jiffies;
1554
1555 /* find the relevant neigh according to the cached device and
1556 * dst ip pair
1557 */
1558 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1559 if (!n)
f6dfb4c3 1560 return;
f6dfb4c3
HHZ		 1561
1562 neigh_event_send(n, NULL);
1563 neigh_release(n);
1564 }
1565}
1566
61086f39 1567static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1568{
948993f2 1569 WARN_ON(!list_empty(&e->flows));
948993f2 1570
3c140dd5
VB		 1571 if (e->compl_result > 0) {
1572 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1573
1574 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1575 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1576 }
948993f2 1577
2a4b6526 1578 kfree(e->tun_info);
948993f2 1579 kfree(e->encap_header);
ac0d9176 1580 kfree_rcu(e, rcu);
948993f2
VB		 1581}
1582
61086f39
VB		 1583void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1584{
1585 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1586
1587 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1588 return;
1589 hash_del_rcu(&e->encap_hlist);
1590 mutex_unlock(&esw->offloads.encap_tbl_lock);
1591
1592 mlx5e_encap_dealloc(priv, e);
1593}
1594
d85cdccb 1595static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1596 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1597{
61086f39
VB		 1598 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1599 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1600
5a7e5bcb 1601 /* flow wasn't fully initialized */
61086f39 1602 if (!e)
5a7e5bcb
VB		 1603 return;
1604
61086f39 1605 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1606 list_del(&flow->encaps[out_index].list);
948993f2 1607 flow->encaps[out_index].e = NULL;
61086f39
VB		 1608 if (!refcount_dec_and_test(&e->refcnt)) {
1609 mutex_unlock(&esw->offloads.encap_tbl_lock);
1610 return;
1611 }
1612 hash_del_rcu(&e->encap_hlist);
1613 mutex_unlock(&esw->offloads.encap_tbl_lock);
1614
1615 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1616}
1617
04de7dda
RD		 1618static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1619{
1620 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1621
226f2ca3
VB		 1622 if (!flow_flag_test(flow, ESWITCH) ||
1623 !flow_flag_test(flow, DUP))
04de7dda
RD		 1624 return;
1625
1626 mutex_lock(&esw->offloads.peer_mutex);
1627 list_del(&flow->peer);
1628 mutex_unlock(&esw->offloads.peer_mutex);
1629
226f2ca3 1630 flow_flag_clear(flow, DUP);
04de7dda 1631
eb252c3a
RD		 1632 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1633 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1634 kfree(flow->peer_flow);
1635 }
1636
04de7dda
RD		 1637 flow->peer_flow = NULL;
1638}
1639
1640static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1641{
1642 struct mlx5_core_dev *dev = flow->priv->mdev;
1643 struct mlx5_devcom *devcom = dev->priv.devcom;
1644 struct mlx5_eswitch *peer_esw;
1645
1646 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1647 if (!peer_esw)
1648 return;
1649
1650 __mlx5e_tc_del_fdb_peer_flow(flow);
1651 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1652}
1653
e8f887ac 1654static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1655 struct mlx5e_tc_flow *flow)
e8f887ac 1656{
226f2ca3 1657 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1658 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1659 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1660 } else {
d85cdccb 1661 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1662 }
e8f887ac
AV		 1663}
1664
bbd00f7e
HHZ		 1665
1666static int parse_tunnel_attr(struct mlx5e_priv *priv,
1667 struct mlx5_flow_spec *spec,
f9e30088 1668 struct flow_cls_offload *f,
6363651d 1669 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1670{
e98bedf5 1671 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1672 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1673 outer_headers);
1674 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1675 outer_headers);
f9e30088 1676 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1677 int err;
2e72eb43 1678
101f4de9 1679 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1680 headers_c, headers_v, match_level);
54c177ca
OS		 1681 if (err) {
1682 NL_SET_ERR_MSG_MOD(extack,
1683 "failed to parse tunnel attributes");
101f4de9 1684 return err;
bbd00f7e
HHZ		 1685 }
1686
fe1587a7
DL		 1687 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1688 struct flow_match_control match;
1689 u16 addr_type;
1690
1691 flow_rule_match_enc_control(rule, &match);
1692 addr_type = match.key->addr_type;
1693
1694 /* For tunnel addr_type used same key id`s as for non-tunnel */
1695 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1696 struct flow_match_ipv4_addrs match;
1697
1698 flow_rule_match_enc_ipv4_addrs(rule, &match);
1699 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1700 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1701 ntohl(match.mask->src));
1702 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1703 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1704 ntohl(match.key->src));
1705
1706 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1707 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1708 ntohl(match.mask->dst));
1709 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1710 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1711 ntohl(match.key->dst));
1712
1713 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1714 ethertype);
1715 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1716 ETH_P_IP);
1717 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1718 struct flow_match_ipv6_addrs match;
1719
1720 flow_rule_match_enc_ipv6_addrs(rule, &match);
1721 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1722 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1723 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1724 ipv6));
1725 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1726 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1727 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1728 ipv6));
1729
1730 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1731 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1732 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1733 ipv6));
1734 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1735 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1736 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1737 ipv6));
1738
1739 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1740 ethertype);
1741 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1742 ETH_P_IPV6);
1743 }
2e72eb43 1744 }
bbd00f7e 1745
8f256622
PNA		 1746 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1747 struct flow_match_ip match;
bcef735c 1748
8f256622
PNA		 1749 flow_rule_match_enc_ip(rule, &match);
1750 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1751 match.mask->tos & 0x3);
1752 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1753 match.key->tos & 0x3);
bcef735c 1754
8f256622
PNA		 1755 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1756 match.mask->tos >> 2);
1757 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1758 match.key->tos >> 2);
bcef735c 1759
8f256622
PNA		 1760 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1761 match.mask->ttl);
1762 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1763 match.key->ttl);
e98bedf5 1764
8f256622 1765 if (match.mask->ttl &&
e98bedf5
EB		 1766 !MLX5_CAP_ESW_FLOWTABLE_FDB
1767 (priv->mdev,
1768 ft_field_support.outer_ipv4_ttl)) {
1769 NL_SET_ERR_MSG_MOD(extack,
1770 "Matching on TTL is not supported");
1771 return -EOPNOTSUPP;
1772 }
1773
bcef735c
OG		 1774 }
1775
bbd00f7e
HHZ		 1776 /* Enforce DMAC when offloading incoming tunneled flows.
1777 * Flow counters require a match on the DMAC.
1778 */
1779 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1780 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1781 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1782 dmac_47_16), priv->netdev->dev_addr);
1783
1784 /* let software handle IP fragments */
1785 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1786 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1787
1788 return 0;
1789}
1790
8377629e
EB		 1791static void *get_match_headers_criteria(u32 flags,
1792 struct mlx5_flow_spec *spec)
1793{
1794 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1795 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1796 inner_headers) :
1797 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1798 outer_headers);
1799}
1800
1801static void *get_match_headers_value(u32 flags,
1802 struct mlx5_flow_spec *spec)
1803{
1804 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1805 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1806 inner_headers) :
1807 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1808 outer_headers);
1809}
1810
6d65bc64 1811static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1812 struct flow_cls_offload *f)
1813{
1814 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1815 struct netlink_ext_ack *extack = f->common.extack;
1816 struct net_device *ingress_dev;
1817 struct flow_match_meta match;
1818
1819 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1820 return 0;
1821
1822 flow_rule_match_meta(rule, &match);
1823 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1824 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
1825 return -EINVAL;
1826 }
1827
1828 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1829 match.key->ingress_ifindex);
1830 if (!ingress_dev) {
1831 NL_SET_ERR_MSG_MOD(extack,
1832 "Can't find the ingress port to match on");
1833 return -EINVAL;
1834 }
1835
1836 if (ingress_dev != filter_dev) {
1837 NL_SET_ERR_MSG_MOD(extack,
1838 "Can't match on the ingress filter port");
1839 return -EINVAL;
1840 }
1841
1842 return 0;
1843}
1844
de0af0bf
RD		 1845static int __parse_cls_flower(struct mlx5e_priv *priv,
1846 struct mlx5_flow_spec *spec,
f9e30088 1847 struct flow_cls_offload *f,
54c177ca 1848 struct net_device *filter_dev,
93b3586e 1849 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 1850{
e98bedf5 1851 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1852 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1853 outer_headers);
1854 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1855 outer_headers);
699e96dd
JL		 1856 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1857 misc_parameters);
1858 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1859 misc_parameters);
f9e30088 1860 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1861 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1862 u16 addr_type = 0;
1863 u8 ip_proto = 0;
93b3586e 1864 u8 *match_level;
6d65bc64 1865 int err;
e3a2b7ed 1866
93b3586e 1867 match_level = outer_match_level;
de0af0bf 1868
8f256622 1869 if (dissector->used_keys &
3d144578
VB		 1870 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1871 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 1872 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1873 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1874 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1875 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1876 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1877 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1878 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1879 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1880 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1881 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1882 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1883 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1884 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1885 BIT(FLOW_DISSECTOR_KEY_IP) |
9272e3df
YK		 1886 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1887 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 1888 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1889 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1890 dissector->used_keys);
e3a2b7ed
AV		 1891 return -EOPNOTSUPP;
1892 }
1893
075973c7 1894 if (mlx5e_get_tc_tun(filter_dev)) {
93b3586e
HN		 1895 if (parse_tunnel_attr(priv, spec, f, filter_dev,
1896 outer_match_level))
bbd00f7e 1897 return -EOPNOTSUPP;
bbd00f7e 1898
93b3586e 1899 /* At this point, header pointers should point to the inner
bbd00f7e
HHZ		 1900 * headers, outer header were already set by parse_tunnel_attr
1901 */
93b3586e 1902 match_level = inner_match_level;
8377629e
EB		 1903 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1904 spec);
1905 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1906 spec);
bbd00f7e
HHZ		 1907 }
1908
6d65bc64 1909 err = mlx5e_flower_parse_meta(filter_dev, f);
1910 if (err)
1911 return err;
1912
8f256622
PNA		 1913 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1914 struct flow_match_basic match;
1915
1916 flow_rule_match_basic(rule, &match);
d3a80bb5 1917 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1918 ntohs(match.mask->n_proto));
d3a80bb5 1919 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1920 ntohs(match.key->n_proto));
e3a2b7ed 1921
8f256622 1922 if (match.mask->n_proto)
d708f902 1923 *match_level = MLX5_MATCH_L2;
e3a2b7ed 1924 }
35a605db
EB		 1925 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1926 is_vlan_dev(filter_dev)) {
1927 struct flow_dissector_key_vlan filter_dev_mask;
1928 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 1929 struct flow_match_vlan match;
1930
35a605db
EB		 1931 if (is_vlan_dev(filter_dev)) {
1932 match.key = &filter_dev_key;
1933 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1934 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1935 match.key->vlan_priority = 0;
1936 match.mask = &filter_dev_mask;
1937 memset(match.mask, 0xff, sizeof(*match.mask));
1938 match.mask->vlan_priority = 0;
1939 } else {
1940 flow_rule_match_vlan(rule, &match);
1941 }
8f256622
PNA		 1942 if (match.mask->vlan_id ||
1943 match.mask->vlan_priority ||
1944 match.mask->vlan_tpid) {
1945 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1946 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1947 svlan_tag, 1);
1948 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1949 svlan_tag, 1);
1950 } else {
1951 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1952 cvlan_tag, 1);
1953 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1954 cvlan_tag, 1);
1955 }
095b6cfd 1956
8f256622
PNA		 1957 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1958 match.mask->vlan_id);
1959 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1960 match.key->vlan_id);
358d79a4 1961
8f256622
PNA		 1962 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1963 match.mask->vlan_priority);
1964 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1965 match.key->vlan_priority);
54782900 1966
d708f902 1967 *match_level = MLX5_MATCH_L2;
54782900 1968 }
d3a80bb5 1969 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 1970 /* cvlan_tag enabled in match criteria and
1971 * disabled in match value means both S & C tags
1972 * don't exist (untagged of both)
1973 */
cee26487 1974 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1975 *match_level = MLX5_MATCH_L2;
54782900
OG		 1976 }
1977
8f256622
PNA		 1978 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1979 struct flow_match_vlan match;
1980
12d5cbf8 1981 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 1982 if (match.mask->vlan_id ||
1983 match.mask->vlan_priority ||
1984 match.mask->vlan_tpid) {
1985 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1986 MLX5_SET(fte_match_set_misc, misc_c,
1987 outer_second_svlan_tag, 1);
1988 MLX5_SET(fte_match_set_misc, misc_v,
1989 outer_second_svlan_tag, 1);
1990 } else {
1991 MLX5_SET(fte_match_set_misc, misc_c,
1992 outer_second_cvlan_tag, 1);
1993 MLX5_SET(fte_match_set_misc, misc_v,
1994 outer_second_cvlan_tag, 1);
1995 }
1996
1997 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1998 match.mask->vlan_id);
699e96dd 1999 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2000 match.key->vlan_id);
699e96dd 2001 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2002 match.mask->vlan_priority);
699e96dd 2003 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2004 match.key->vlan_priority);
699e96dd
JL		 2005
2006 *match_level = MLX5_MATCH_L2;
2007 }
2008 }
2009
8f256622
PNA		 2010 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2011 struct flow_match_eth_addrs match;
54782900 2012
8f256622 2013 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2014 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2015 dmac_47_16),
8f256622 2016 match.mask->dst);
d3a80bb5
OG		 2017 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2018 dmac_47_16),
8f256622 2019 match.key->dst);
d3a80bb5
OG		 2020
2021 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2022 smac_47_16),
8f256622 2023 match.mask->src);
d3a80bb5
OG		 2024 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2025 smac_47_16),
8f256622 2026 match.key->src);
d3a80bb5 2027
8f256622
PNA		 2028 if (!is_zero_ether_addr(match.mask->src) ||
2029 !is_zero_ether_addr(match.mask->dst))
d708f902 2030 *match_level = MLX5_MATCH_L2;
54782900
OG		 2031 }
2032
8f256622
PNA		 2033 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2034 struct flow_match_control match;
54782900 2035
8f256622
PNA		 2036 flow_rule_match_control(rule, &match);
2037 addr_type = match.key->addr_type;
54782900
OG		 2038
2039 /* the HW doesn't support frag first/later */
8f256622 2040 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2041 return -EOPNOTSUPP;
2042
8f256622 2043 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2044 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2045 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2046 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2047
2048 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2049 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2050 *match_level = MLX5_MATCH_L2;
54782900
OG		 2051 /* *** L2 attributes parsing up to here *** */
2052 else
83621b7d 2053 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2054 }
2055 }
2056
8f256622
PNA		 2057 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2058 struct flow_match_basic match;
2059
2060 flow_rule_match_basic(rule, &match);
2061 ip_proto = match.key->ip_proto;
54782900
OG		 2062
2063 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2064 match.mask->ip_proto);
54782900 2065 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2066 match.key->ip_proto);
54782900 2067
8f256622 2068 if (match.mask->ip_proto)
d708f902 2069 *match_level = MLX5_MATCH_L3;
54782900
OG		 2070 }
2071
e3a2b7ed 2072 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2073 struct flow_match_ipv4_addrs match;
e3a2b7ed 2074
8f256622 2075 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2076 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2077 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2078 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2079 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2080 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2081 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2082 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2083 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2084 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2085 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2086 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2087 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2088
8f256622 2089 if (match.mask->src || match.mask->dst)
d708f902 2090 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2091 }
2092
2093 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2094 struct flow_match_ipv6_addrs match;
e3a2b7ed 2095
8f256622 2096 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2097 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2098 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2099 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2100 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2101 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2102 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2103
2104 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2105 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2106 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2107 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2108 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2109 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2110
8f256622
PNA		 2111 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2112 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2113 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2114 }
2115
8f256622
PNA		 2116 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2117 struct flow_match_ip match;
1f97a526 2118
8f256622
PNA		 2119 flow_rule_match_ip(rule, &match);
2120 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2121 match.mask->tos & 0x3);
2122 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2123 match.key->tos & 0x3);
1f97a526 2124
8f256622
PNA		 2125 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2126 match.mask->tos >> 2);
2127 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2128 match.key->tos >> 2);
1f97a526 2129
8f256622
PNA		 2130 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2131 match.mask->ttl);
2132 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2133 match.key->ttl);
1f97a526 2134
8f256622 2135 if (match.mask->ttl &&
a8ade55f 2136 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2137 ft_field_support.outer_ipv4_ttl)) {
2138 NL_SET_ERR_MSG_MOD(extack,
2139 "Matching on TTL is not supported");
1f97a526 2140 return -EOPNOTSUPP;
e98bedf5 2141 }
a8ade55f 2142
8f256622 2143 if (match.mask->tos || match.mask->ttl)
d708f902 2144 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2145 }
2146
54782900
OG		 2147 /* *** L3 attributes parsing up to here *** */
2148
8f256622
PNA		 2149 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2150 struct flow_match_ports match;
2151
2152 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2153 switch (ip_proto) {
2154 case IPPROTO_TCP:
2155 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2156 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2157 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2158 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2159
2160 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2161 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2162 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2163 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2164 break;
2165
2166 case IPPROTO_UDP:
2167 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2168 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2169 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2170 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2171
2172 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2173 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2174 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2175 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2176 break;
2177 default:
e98bedf5
EB		 2178 NL_SET_ERR_MSG_MOD(extack,
2179 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2180 netdev_err(priv->netdev,
2181 "Only UDP and TCP transport are supported\n");
2182 return -EINVAL;
2183 }
de0af0bf 2184
8f256622 2185 if (match.mask->src || match.mask->dst)
d708f902 2186 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2187 }
2188
8f256622
PNA		 2189 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2190 struct flow_match_tcp match;
e77834ec 2191
8f256622 2192 flow_rule_match_tcp(rule, &match);
e77834ec 2193 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2194 ntohs(match.mask->flags));
e77834ec 2195 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2196 ntohs(match.key->flags));
e77834ec 2197
8f256622 2198 if (match.mask->flags)
d708f902 2199 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2200 }
2201
e3a2b7ed
AV		 2202 return 0;
2203}
2204
de0af0bf 2205static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2206 struct mlx5e_tc_flow *flow,
de0af0bf 2207 struct mlx5_flow_spec *spec,
f9e30088 2208 struct flow_cls_offload *f,
54c177ca 2209 struct net_device *filter_dev)
de0af0bf 2210{
93b3586e 2211 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2212 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2213 struct mlx5_core_dev *dev = priv->mdev;
2214 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2215 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2216 struct mlx5_eswitch_rep *rep;
226f2ca3 2217 bool is_eswitch_flow;
de0af0bf
RD		 2218 int err;
2219
93b3586e
HN		 2220 inner_match_level = MLX5_MATCH_NONE;
2221 outer_match_level = MLX5_MATCH_NONE;
2222
2223 err = __parse_cls_flower(priv, spec, f, filter_dev, &inner_match_level,
2224 &outer_match_level);
2225 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2226 outer_match_level : inner_match_level;
de0af0bf 2227
226f2ca3
VB		 2228 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2229 if (!err && is_eswitch_flow) {
1d447a39 2230 rep = rpriv->rep;
b05af6aa 2231 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2232 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2233 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2234 NL_SET_ERR_MSG_MOD(extack,
2235 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2236 netdev_warn(priv->netdev,
2237 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2238 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2239 return -EOPNOTSUPP;
2240 }
2241 }
2242
226f2ca3 2243 if (is_eswitch_flow) {
93b3586e
HN		 2244 flow->esw_attr->inner_match_level = inner_match_level;
2245 flow->esw_attr->outer_match_level = outer_match_level;
6363651d 2246 } else {
93b3586e 2247 flow->nic_attr->match_level = non_tunnel_match_level;
6363651d 2248 }
38aa51c1 2249
de0af0bf
RD		 2250 return err;
2251}
2252
d79b6df6
OG		 2253struct pedit_headers {
2254 struct ethhdr eth;
0eb69bb9 2255 struct vlan_hdr vlan;
d79b6df6
OG		 2256 struct iphdr ip4;
2257 struct ipv6hdr ip6;
2258 struct tcphdr tcp;
2259 struct udphdr udp;
2260};
2261
c500c86b
PNA		 2262struct pedit_headers_action {
2263 struct pedit_headers vals;
2264 struct pedit_headers masks;
2265 u32 pedits;
2266};
2267
d79b6df6 2268static int pedit_header_offsets[] = {
73867881
PNA		 2269 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2270 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2271 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2272 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2273 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2274};
2275
2276#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2277
2278static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2279 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2280{
2281 u32 *curr_pmask, *curr_pval;
2282
c500c86b
PNA		 2283 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2284 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2285
2286 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2287 goto out_err;
2288
2289 *curr_pmask |= mask;
2290 *curr_pval |= (val & mask);
2291
2292 return 0;
2293
2294out_err:
2295 return -EOPNOTSUPP;
2296}
2297
2298struct mlx5_fields {
2299 u8 field;
88f30bbc
DL		 2300 u8 field_bsize;
2301 u32 field_mask;
d79b6df6 2302 u32 offset;
27c11b6b 2303 u32 match_offset;
d79b6df6
OG		 2304};
2305
88f30bbc
DL		 2306#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2307 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2308 offsetof(struct pedit_headers, field) + (off), \
2309 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2310
2ef86872
EB		 2311/* masked values are the same and there are no rewrites that do not have a
2312 * match.
2313 */
2314#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2315 type matchmaskx = *(type *)(matchmaskp); \
2316 type matchvalx = *(type *)(matchvalp); \
2317 type maskx = *(type *)(maskp); \
2318 type valx = *(type *)(valp); \
2319 \
2320 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2321 matchmaskx)); \
2322})
2323
27c11b6b 2324static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2325 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2326{
2327 bool same = false;
2328
88f30bbc
DL		 2329 switch (bsize) {
2330 case 8:
2ef86872 2331 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2332 break;
88f30bbc 2333 case 16:
2ef86872 2334 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2335 break;
88f30bbc 2336 case 32:
2ef86872 2337 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2338 break;
2339 }
2340
2341 return same;
2342}
a8e4f0c4 2343
d79b6df6 2344static struct mlx5_fields fields[] = {
88f30bbc
DL		 2345 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2346 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2347 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2348 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2349 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2350 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2351
ab9341b5 2352 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2353 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2354 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2355 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2356
2357 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2358 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2359 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2360 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2361 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2362 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2363 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2364 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2365 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2366 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2367 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2368 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2369 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2370 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2371 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2372 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2373 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
27c11b6b 2374
88f30bbc
DL		 2375 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2376 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2377 /* in linux iphdr tcp_flags is 8 bits long */
2378 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2379
88f30bbc
DL		 2380 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2381 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2382};
2383
218d05ce
TZ		 2384/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2385 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2386 * says how many HW actions were actually parsed.
d79b6df6 2387 */
c500c86b 2388static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5 2389 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2390 u32 *action_flags,
e98bedf5 2391 struct netlink_ext_ack *extack)
d79b6df6
OG		 2392{
2393 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 2394 int i, action_size, nactions, max_actions, first, last, next_z;
88f30bbc
DL		 2395 void *headers_c, *headers_v, *action, *vals_p;
2396 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
d79b6df6 2397 struct mlx5_fields *f;
d79b6df6 2398 unsigned long mask;
2b64beba
OG		 2399 __be32 mask_be32;
2400 __be16 mask_be16;
88f30bbc
DL		 2401 u8 cmd;
2402
2403 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2404 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2405
73867881
PNA		 2406 set_masks = &hdrs[0].masks;
2407 add_masks = &hdrs[1].masks;
2408 set_vals = &hdrs[0].vals;
2409 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2410
2411 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 2412 action = parse_attr->mod_hdr_actions +
2413 parse_attr->num_mod_hdr_actions * action_size;
2414
2415 max_actions = parse_attr->max_mod_hdr_actions;
2416 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 2417
2418 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2419 bool skip;
2420
d79b6df6
OG		 2421 f = &fields[i];
2422 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2423 s_mask = 0;
2424 a_mask = 0;
d79b6df6
OG		 2425
2426 s_masks_p = (void *)set_masks + f->offset;
2427 a_masks_p = (void *)add_masks + f->offset;
2428
88f30bbc
DL		 2429 s_mask = *s_masks_p & f->field_mask;
2430 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2431
2432 if (!s_mask && !a_mask) /* nothing to offload here */
2433 continue;
2434
2435 if (s_mask && a_mask) {
e98bedf5
EB		 2436 NL_SET_ERR_MSG_MOD(extack,
2437 "can't set and add to the same HW field");
d79b6df6
OG		 2438 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2439 return -EOPNOTSUPP;
2440 }
2441
2442 if (nactions == max_actions) {
e98bedf5
EB		 2443 NL_SET_ERR_MSG_MOD(extack,
2444 "too many pedit actions, can't offload");
d79b6df6
OG		 2445 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2446 return -EOPNOTSUPP;
2447 }
2448
27c11b6b 2449 skip = false;
d79b6df6 2450 if (s_mask) {
27c11b6b
EB		 2451 void *match_mask = headers_c + f->match_offset;
2452 void *match_val = headers_v + f->match_offset;
2453
d79b6df6
OG		 2454 cmd = MLX5_ACTION_TYPE_SET;
2455 mask = s_mask;
2456 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2457 /* don't rewrite if we have a match on the same value */
2458 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2459 match_mask, f->field_bsize))
27c11b6b 2460 skip = true;
d79b6df6 2461 /* clear to denote we consumed this field */
88f30bbc 2462 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2463 } else {
2464 cmd = MLX5_ACTION_TYPE_ADD;
2465 mask = a_mask;
2466 vals_p = (void *)add_vals + f->offset;
27c11b6b 2467 /* add 0 is no change */
88f30bbc 2468 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2469 skip = true;
d79b6df6 2470 /* clear to denote we consumed this field */
88f30bbc 2471 *a_masks_p &= ~f->field_mask;
d79b6df6 2472 }
27c11b6b
EB		 2473 if (skip)
2474 continue;
d79b6df6 2475
88f30bbc 2476 if (f->field_bsize == 32) {
2b64beba
OG		 2477 mask_be32 = *(__be32 *)&mask;
2478 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
88f30bbc 2479 } else if (f->field_bsize == 16) {
2b64beba
OG		 2480 mask_be16 = *(__be16 *)&mask;
2481 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2482 }
2483
88f30bbc
DL		 2484 first = find_first_bit(&mask, f->field_bsize);
2485 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2486 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2487 if (first < next_z && next_z < last) {
e98bedf5
EB		 2488 NL_SET_ERR_MSG_MOD(extack,
2489 "rewrite of few sub-fields isn't supported");
2b64beba 2490 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2491 mask);
2492 return -EOPNOTSUPP;
2493 }
2494
2495 MLX5_SET(set_action_in, action, action_type, cmd);
2496 MLX5_SET(set_action_in, action, field, f->field);
2497
2498 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2499 int start;
2500
2501 /* if field is bit sized it can start not from first bit */
2502 start = find_first_bit((unsigned long *)&f->field_mask,
2503 f->field_bsize);
2504
2505 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2506 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2507 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2508 }
2509
88f30bbc 2510 if (f->field_bsize == 32)
2b64beba 2511 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2512 else if (f->field_bsize == 16)
2b64beba 2513 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2514 else if (f->field_bsize == 8)
2b64beba 2515 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2516
2517 action += action_size;
2518 nactions++;
2519 }
2520
2521 parse_attr->num_mod_hdr_actions = nactions;
2522 return 0;
2523}
2524
2cc1cb1d
TZ		 2525static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2526 int namespace)
2527{
2528 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2529 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2530 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2531 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2532}
2533
d79b6df6 2534static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2535 struct pedit_headers_action *hdrs,
2536 int namespace,
d79b6df6
OG		 2537 struct mlx5e_tc_flow_parse_attr *parse_attr)
2538{
2539 int nkeys, action_size, max_actions;
2540
c500c86b
PNA		 2541 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2542 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2543 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2544
2cc1cb1d 2545 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
d79b6df6
OG		 2546 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2547 max_actions = min(max_actions, nkeys * 16);
2548
2549 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2550 if (!parse_attr->mod_hdr_actions)
2551 return -ENOMEM;
2552
218d05ce 2553 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2554 return 0;
2555}
2556
2557static const struct pedit_headers zero_masks = {};
2558
2559static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2560 const struct flow_action_entry *act, int namespace,
c500c86b 2561 struct pedit_headers_action *hdrs,
e98bedf5 2562 struct netlink_ext_ack *extack)
d79b6df6 2563{
73867881
PNA		 2564 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2565 int err = -EOPNOTSUPP;
d79b6df6 2566 u32 mask, val, offset;
73867881 2567 u8 htype;
d79b6df6 2568
73867881
PNA		 2569 htype = act->mangle.htype;
2570 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2571
73867881
PNA		 2572 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2573 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2574 goto out_err;
2575 }
d79b6df6 2576
2cc1cb1d
TZ		 2577 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2578 NL_SET_ERR_MSG_MOD(extack,
2579 "The pedit offload action is not supported");
2580 goto out_err;
2581 }
2582
73867881
PNA		 2583 mask = act->mangle.mask;
2584 val = act->mangle.val;
2585 offset = act->mangle.offset;
d79b6df6 2586
73867881
PNA		 2587 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2588 if (err)
2589 goto out_err;
c500c86b 2590
73867881 2591 hdrs[cmd].pedits++;
d79b6df6 2592
c500c86b
PNA		 2593 return 0;
2594out_err:
2595 return err;
2596}
2597
2598static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2599 struct mlx5e_tc_flow_parse_attr *parse_attr,
2600 struct pedit_headers_action *hdrs,
27c11b6b 2601 u32 *action_flags,
c500c86b
PNA		 2602 struct netlink_ext_ack *extack)
2603{
2604 struct pedit_headers *cmd_masks;
2605 int err;
2606 u8 cmd;
2607
218d05ce 2608 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2609 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2610 if (err)
2611 goto out_err;
2612 }
d79b6df6 2613
27c11b6b 2614 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
d79b6df6
OG		 2615 if (err < 0)
2616 goto out_dealloc_parsed_actions;
2617
2618 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2619 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2620 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2621 NL_SET_ERR_MSG_MOD(extack,
2622 "attempt to offload an unsupported field");
b3a433de 2623 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2624 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2625 16, 1, cmd_masks, sizeof(zero_masks), true);
2626 err = -EOPNOTSUPP;
2627 goto out_dealloc_parsed_actions;
2628 }
2629 }
2630
2631 return 0;
2632
2633out_dealloc_parsed_actions:
2634 kfree(parse_attr->mod_hdr_actions);
2635out_err:
2636 return err;
2637}
2638
e98bedf5
EB		 2639static bool csum_offload_supported(struct mlx5e_priv *priv,
2640 u32 action,
2641 u32 update_flags,
2642 struct netlink_ext_ack *extack)
26c02749
OG		 2643{
2644 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2645 TCA_CSUM_UPDATE_FLAG_UDP;
2646
2647 /* The HW recalcs checksums only if re-writing headers */
2648 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2649 NL_SET_ERR_MSG_MOD(extack,
2650 "TC csum action is only offloaded with pedit");
26c02749
OG		 2651 netdev_warn(priv->netdev,
2652 "TC csum action is only offloaded with pedit\n");
2653 return false;
2654 }
2655
2656 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2657 NL_SET_ERR_MSG_MOD(extack,
2658 "can't offload TC csum action for some header/s");
26c02749
OG		 2659 netdev_warn(priv->netdev,
2660 "can't offload TC csum action for some header/s - flags %#x\n",
2661 update_flags);
2662 return false;
2663 }
2664
2665 return true;
2666}
2667
8998576b
DL		 2668struct ip_ttl_word {
2669 __u8 ttl;
2670 __u8 protocol;
2671 __sum16 check;
2672};
2673
2674struct ipv6_hoplimit_word {
2675 __be16 payload_len;
2676 __u8 nexthdr;
2677 __u8 hop_limit;
2678};
2679
2680static bool is_action_keys_supported(const struct flow_action_entry *act)
2681{
2682 u32 mask, offset;
2683 u8 htype;
2684
2685 htype = act->mangle.htype;
2686 offset = act->mangle.offset;
2687 mask = ~act->mangle.mask;
2688 /* For IPv4 & IPv6 header check 4 byte word,
2689 * to determine that modified fields
2690 * are NOT ttl & hop_limit only.
2691 */
2692 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2693 struct ip_ttl_word *ttl_word =
2694 (struct ip_ttl_word *)&mask;
2695
2696 if (offset != offsetof(struct iphdr, ttl) ||
2697 ttl_word->protocol ||
2698 ttl_word->check) {
2699 return true;
2700 }
2701 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2702 struct ipv6_hoplimit_word *hoplimit_word =
2703 (struct ipv6_hoplimit_word *)&mask;
2704
2705 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2706 hoplimit_word->payload_len ||
2707 hoplimit_word->nexthdr) {
2708 return true;
2709 }
2710 }
2711 return false;
2712}
2713
bdd66ac0 2714static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2715 struct flow_action *flow_action,
1651925d 2716 u32 actions,
e98bedf5 2717 struct netlink_ext_ack *extack)
bdd66ac0 2718{
73867881 2719 const struct flow_action_entry *act;
bdd66ac0 2720 bool modify_ip_header;
bdd66ac0
OG		 2721 void *headers_v;
2722 u16 ethertype;
8998576b 2723 u8 ip_proto;
73867881 2724 int i;
bdd66ac0 2725
8377629e 2726 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2727 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2728
2729 /* for non-IP we only re-write MACs, so we're okay */
2730 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2731 goto out_ok;
2732
2733 modify_ip_header = false;
73867881
PNA		 2734 flow_action_for_each(i, act, flow_action) {
2735 if (act->id != FLOW_ACTION_MANGLE &&
2736 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2737 continue;
2738
8998576b 2739 if (is_action_keys_supported(act)) {
73867881
PNA		 2740 modify_ip_header = true;
2741 break;
bdd66ac0
OG		 2742 }
2743 }
2744
2745 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2746 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2747 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2748 NL_SET_ERR_MSG_MOD(extack,
2749 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2750 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2751 return false;
2752 }
2753
2754out_ok:
2755 return true;
2756}
2757
2758static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2759 struct flow_action *flow_action,
bdd66ac0 2760 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2761 struct mlx5e_tc_flow *flow,
2762 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2763{
2764 u32 actions;
2765
226f2ca3 2766 if (mlx5e_is_eswitch_flow(flow))
bdd66ac0
OG		 2767 actions = flow->esw_attr->action;
2768 else
2769 actions = flow->nic_attr->action;
2770
226f2ca3 2771 if (flow_flag_test(flow, EGRESS) &&
35a605db 2772 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
6830b468
TZ		 2773 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2774 (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
7e29392e
RD		 2775 return false;
2776
bdd66ac0 2777 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2778 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2779 flow_action, actions,
e98bedf5 2780 extack);
bdd66ac0
OG		 2781
2782 return true;
2783}
2784
5c65c564
OG		 2785static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2786{
2787 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2788 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2789
2790 fmdev = priv->mdev;
2791 pmdev = peer_priv->mdev;
2792
59c9d35e
AH		 2793 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2794 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2795
816f6706 2796 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2797}
2798
bdc837ee
EB		 2799static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2800 const struct flow_action_entry *act,
2801 struct mlx5e_tc_flow_parse_attr *parse_attr,
2802 struct pedit_headers_action *hdrs,
2803 u32 *action, struct netlink_ext_ack *extack)
2804{
2805 u16 mask16 = VLAN_VID_MASK;
2806 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2807 const struct flow_action_entry pedit_act = {
2808 .id = FLOW_ACTION_MANGLE,
2809 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2810 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2811 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2812 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2813 };
6fca9d1e 2814 u8 match_prio_mask, match_prio_val;
bf2f3bca 2815 void *headers_c, *headers_v;
bdc837ee
EB		 2816 int err;
2817
bf2f3bca
EB		 2818 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2819 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2820
2821 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2822 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2823 NL_SET_ERR_MSG_MOD(extack,
2824 "VLAN rewrite action must have VLAN protocol match");
2825 return -EOPNOTSUPP;
2826 }
2827
6fca9d1e
EB		 2828 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2829 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2830 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2831 NL_SET_ERR_MSG_MOD(extack,
2832 "Changing VLAN prio is not supported");
bdc837ee
EB		 2833 return -EOPNOTSUPP;
2834 }
2835
dec481c8 2836 err = parse_tc_pedit_action(priv, &pedit_act, namespace, hdrs, NULL);
bdc837ee
EB		 2837 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2838
2839 return err;
2840}
2841
0bac1194
EB		 2842static int
2843add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2844 struct mlx5e_tc_flow_parse_attr *parse_attr,
2845 struct pedit_headers_action *hdrs,
2846 u32 *action, struct netlink_ext_ack *extack)
2847{
2848 const struct flow_action_entry prio_tag_act = {
2849 .vlan.vid = 0,
2850 .vlan.prio =
2851 MLX5_GET(fte_match_set_lyr_2_4,
2852 get_match_headers_value(*action,
2853 &parse_attr->spec),
2854 first_prio) &
2855 MLX5_GET(fte_match_set_lyr_2_4,
2856 get_match_headers_criteria(*action,
2857 &parse_attr->spec),
2858 first_prio),
2859 };
2860
2861 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2862 &prio_tag_act, parse_attr, hdrs, action,
2863 extack);
2864}
2865
73867881
PNA		 2866static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2867 struct flow_action *flow_action,
aa0cbbae 2868 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2869 struct mlx5e_tc_flow *flow,
2870 struct netlink_ext_ack *extack)
e3a2b7ed 2871{
aa0cbbae 2872 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2873 struct pedit_headers_action hdrs[2] = {};
2874 const struct flow_action_entry *act;
1cab1cd7 2875 u32 action = 0;
244cd96a 2876 int err, i;
e3a2b7ed 2877
73867881 2878 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2879 return -EINVAL;
2880
48855479
JP		 2881 if (!flow_action_hw_stats_types_check(flow_action, extack,
2882 FLOW_ACTION_HW_STATS_TYPE_DELAYED))
319a1d19
JP		 2883 return -EOPNOTSUPP;
2884
3bc4b7bf 2885 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2886
73867881
PNA		 2887 flow_action_for_each(i, act, flow_action) {
2888 switch (act->id) {
15fc92ec
TZ		 2889 case FLOW_ACTION_ACCEPT:
2890 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2891 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2892 break;
73867881 2893 case FLOW_ACTION_DROP:
1cab1cd7 2894 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2895 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2896 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2897 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2898 break;
2899 case FLOW_ACTION_MANGLE:
2900 case FLOW_ACTION_ADD:
2901 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
dec481c8 2902 hdrs, extack);
2f4fe4ca
OG		 2903 if (err)
2904 return err;
2905
1cab1cd7
OG		 2906 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2907 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2908 break;
bdc837ee
EB		 2909 case FLOW_ACTION_VLAN_MANGLE:
2910 err = add_vlan_rewrite_action(priv,
2911 MLX5_FLOW_NAMESPACE_KERNEL,
2912 act, parse_attr, hdrs,
2913 &action, extack);
2914 if (err)
2915 return err;
2916
2917 break;
73867881 2918 case FLOW_ACTION_CSUM:
1cab1cd7 2919 if (csum_offload_supported(priv, action,
73867881 2920 act->csum_flags,
e98bedf5 2921 extack))
73867881 2922 break;
26c02749
OG		 2923
2924 return -EOPNOTSUPP;
73867881
PNA		 2925 case FLOW_ACTION_REDIRECT: {
2926 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2927
2928 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2929 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2930 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 2931 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 2932 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2933 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2934 } else {
e98bedf5
EB		 2935 NL_SET_ERR_MSG_MOD(extack,
2936 "device is not on same HW, can't offload");
5c65c564
OG		 2937 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2938 peer_dev->name);
2939 return -EINVAL;
2940 }
73867881
PNA		 2941 }
2942 break;
2943 case FLOW_ACTION_MARK: {
2944 u32 mark = act->mark;
e3a2b7ed
AV		 2945
2946 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2947 NL_SET_ERR_MSG_MOD(extack,
2948 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2949 return -EINVAL;
2950 }
2951
3bc4b7bf 2952 attr->flow_tag = mark;
1cab1cd7 2953 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2954 }
2955 break;
2956 default:
2cc1cb1d
TZ		 2957 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2958 return -EOPNOTSUPP;
e3a2b7ed 2959 }
e3a2b7ed
AV		 2960 }
2961
c500c86b
PNA		 2962 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2963 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2964 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 2965 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2966 if (err)
2967 return err;
27c11b6b
EB		 2968 /* in case all pedit actions are skipped, remove the MOD_HDR
2969 * flag.
2970 */
e7739a60 2971 if (parse_attr->num_mod_hdr_actions == 0) {
27c11b6b 2972 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60
EB		 2973 kfree(parse_attr->mod_hdr_actions);
2974 }
c500c86b
PNA		 2975 }
2976
1cab1cd7 2977 attr->action = action;
73867881 2978 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2979 return -EOPNOTSUPP;
2980
e3a2b7ed
AV		 2981 return 0;
2982}
2983
7f1a546e 2984struct encap_key {
1f6da306 2985 const struct ip_tunnel_key *ip_tun_key;
d386939a 2986 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 2987};
2988
2989static inline int cmp_encap_info(struct encap_key *a,
2990 struct encap_key *b)
a54e20b4 2991{
7f1a546e 2992 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 2993 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 2994}
2995
7f1a546e 2996static inline int hash_encap_info(struct encap_key *key)
a54e20b4 2997{
7f1a546e 2998 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 2999 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3000}
3001
a54e20b4 3002
b1d90e6b
RL		 3003static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
3004 struct net_device *peer_netdev)
3005{
3006 struct mlx5e_priv *peer_priv;
3007
3008 peer_priv = netdev_priv(peer_netdev);
3009
3010 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 3011 mlx5e_eswitch_rep(priv->netdev) &&
3012 mlx5e_eswitch_rep(peer_netdev) &&
3013 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3014}
3015
32f3671f 3016
f5bc2c5d 3017
948993f2
VB		 3018bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3019{
3020 return refcount_inc_not_zero(&e->refcnt);
3021}
3022
3023static struct mlx5e_encap_entry *
3024mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3025 uintptr_t hash_key)
3026{
3027 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3028 struct mlx5e_encap_entry *e;
3029 struct encap_key e_key;
3030
3031 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3032 encap_hlist, hash_key) {
3033 e_key.ip_tun_key = &e->tun_info->key;
3034 e_key.tc_tunnel = e->tunnel;
3035 if (!cmp_encap_info(&e_key, key) &&
3036 mlx5e_encap_take(e))
3037 return e;
3038 }
3039
3040 return NULL;
3041}
3042
2a4b6526
VB		 3043static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3044{
3045 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3046
3047 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3048}
3049
554fe75c
DL		 3050static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3051 struct mlx5e_tc_flow *flow,
3052 int out_index,
3053 struct mlx5e_encap_entry *e,
3054 struct netlink_ext_ack *extack)
3055{
3056 int i;
3057
3058 for (i = 0; i < out_index; i++) {
3059 if (flow->encaps[i].e != e)
3060 continue;
3061 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3062 netdev_err(priv->netdev, "can't duplicate encap action\n");
3063 return true;
3064 }
3065
3066 return false;
3067}
3068
a54e20b4 3069static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3070 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3071 struct net_device *mirred_dev,
3072 int out_index,
8c4dc42b 3073 struct netlink_ext_ack *extack,
0ad060ee
RD		 3074 struct net_device **encap_dev,
3075 bool *encap_valid)
a54e20b4
HHZ		 3076{
3077 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 3078 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 3079 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 3080 const struct ip_tunnel_info *tun_info;
948993f2 3081 struct encap_key key;
c1ae1152 3082 struct mlx5e_encap_entry *e;
733d4f36 3083 unsigned short family;
a54e20b4 3084 uintptr_t hash_key;
54c177ca 3085 int err = 0;
a54e20b4 3086
733d4f36 3087 parse_attr = attr->parse_attr;
1f6da306 3088 tun_info = parse_attr->tun_info[out_index];
733d4f36 3089 family = ip_tunnel_info_af(tun_info);
7f1a546e 3090 key.ip_tun_key = &tun_info->key;
d386939a 3091 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3092 if (!key.tc_tunnel) {
3093 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3094 return -EOPNOTSUPP;
3095 }
733d4f36 3096
7f1a546e 3097 hash_key = hash_encap_info(&key);
a54e20b4 3098
61086f39 3099 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3100 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3101
b2812089 3102 /* must verify if encap is valid or not */
d589e785 3103 if (e) {
554fe75c
DL		 3104 /* Check that entry was not already attached to this flow */
3105 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3106 err = -EOPNOTSUPP;
3107 goto out_err;
3108 }
3109
d589e785
VB		 3110 mutex_unlock(&esw->offloads.encap_tbl_lock);
3111 wait_for_completion(&e->res_ready);
3112
3113 /* Protect against concurrent neigh update. */
3114 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3115 if (e->compl_result < 0) {
d589e785
VB		 3116 err = -EREMOTEIO;
3117 goto out_err;
3118 }
45247bf2 3119 goto attach_flow;
d589e785 3120 }
a54e20b4
HHZ		 3121
3122 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3123 if (!e) {
3124 err = -ENOMEM;
3125 goto out_err;
3126 }
a54e20b4 3127
948993f2 3128 refcount_set(&e->refcnt, 1);
d589e785
VB		 3129 init_completion(&e->res_ready);
3130
2a4b6526
VB		 3131 tun_info = dup_tun_info(tun_info);
3132 if (!tun_info) {
3133 err = -ENOMEM;
3134 goto out_err_init;
3135 }
1f6da306 3136 e->tun_info = tun_info;
101f4de9 3137 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3138 if (err)
3139 goto out_err_init;
54c177ca 3140
a54e20b4 3141 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3142 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3143 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3144
ce99f6b9 3145 if (family == AF_INET)
101f4de9 3146 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3147 else if (family == AF_INET6)
101f4de9 3148 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3149
d589e785
VB		 3150 /* Protect against concurrent neigh update. */
3151 mutex_lock(&esw->offloads.encap_tbl_lock);
3152 complete_all(&e->res_ready);
3153 if (err) {
3154 e->compl_result = err;
a54e20b4 3155 goto out_err;
d589e785 3156 }
3c140dd5 3157 e->compl_result = 1;
a54e20b4 3158
45247bf2 3159attach_flow:
948993f2 3160 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3161 list_add(&flow->encaps[out_index].list, &e->flows);
3162 flow->encaps[out_index].index = out_index;
45247bf2 3163 *encap_dev = e->out_dev;
8c4dc42b 3164 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2b688ea5 3165 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
8c4dc42b 3166 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3167 *encap_valid = true;
8c4dc42b 3168 } else {
0ad060ee 3169 *encap_valid = false;
8c4dc42b 3170 }
61086f39 3171 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3172
232c0013 3173 return err;
a54e20b4
HHZ		 3174
3175out_err:
61086f39 3176 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3177 if (e)
3178 mlx5e_encap_put(priv, e);
a54e20b4 3179 return err;
2a4b6526
VB		 3180
3181out_err_init:
3182 mutex_unlock(&esw->offloads.encap_tbl_lock);
3183 kfree(tun_info);
3184 kfree(e);
3185 return err;
a54e20b4
HHZ		 3186}
3187
1482bd3d 3188static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3189 const struct flow_action_entry *act,
1482bd3d
JL		 3190 struct mlx5_esw_flow_attr *attr,
3191 u32 *action)
3192{
cc495188
JL		 3193 u8 vlan_idx = attr->total_vlan;
3194
3195 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3196 return -EOPNOTSUPP;
3197
73867881
PNA		 3198 switch (act->id) {
3199 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3200 if (vlan_idx) {
3201 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3202 MLX5_FS_VLAN_DEPTH))
3203 return -EOPNOTSUPP;
3204
3205 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3206 } else {
3207 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3208 }
73867881
PNA		 3209 break;
3210 case FLOW_ACTION_VLAN_PUSH:
3211 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3212 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3213 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3214 if (!attr->vlan_proto[vlan_idx])
3215 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3216
3217 if (vlan_idx) {
3218 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3219 MLX5_FS_VLAN_DEPTH))
3220 return -EOPNOTSUPP;
3221
3222 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3223 } else {
3224 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3225 (act->vlan.proto != htons(ETH_P_8021Q) ||
3226 act->vlan.prio))
cc495188
JL		 3227 return -EOPNOTSUPP;
3228
3229 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3230 }
73867881
PNA		 3231 break;
3232 default:
bdc837ee 3233 return -EINVAL;
1482bd3d
JL		 3234 }
3235
cc495188
JL		 3236 attr->total_vlan = vlan_idx + 1;
3237
1482bd3d
JL		 3238 return 0;
3239}
3240
278748a9
EB		 3241static int add_vlan_push_action(struct mlx5e_priv *priv,
3242 struct mlx5_esw_flow_attr *attr,
3243 struct net_device **out_dev,
3244 u32 *action)
3245{
3246 struct net_device *vlan_dev = *out_dev;
3247 struct flow_action_entry vlan_act = {
3248 .id = FLOW_ACTION_VLAN_PUSH,
3249 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3250 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3251 .vlan.prio = 0,
3252 };
3253 int err;
3254
3255 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3256 if (err)
3257 return err;
3258
3259 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3260 dev_get_iflink(vlan_dev));
3261 if (is_vlan_dev(*out_dev))
3262 err = add_vlan_push_action(priv, attr, out_dev, action);
3263
3264 return err;
3265}
3266
35a605db
EB		 3267static int add_vlan_pop_action(struct mlx5e_priv *priv,
3268 struct mlx5_esw_flow_attr *attr,
3269 u32 *action)
3270{
f3b0a18b 3271 int nest_level = attr->parse_attr->filter_dev->lower_level;
35a605db
EB		 3272 struct flow_action_entry vlan_act = {
3273 .id = FLOW_ACTION_VLAN_POP,
3274 };
3275 int err = 0;
3276
3277 while (nest_level--) {
3278 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3279 if (err)
3280 return err;
3281 }
3282
3283 return err;
3284}
3285
f6dc1264
PB		 3286bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3287 struct net_device *out_dev)
3288{
3289 if (is_merged_eswitch_dev(priv, out_dev))
3290 return true;
3291
3292 return mlx5e_eswitch_rep(out_dev) &&
3293 same_hw_devs(priv, netdev_priv(out_dev));
3294}
3295
554fe75c
DL		 3296static bool is_duplicated_output_device(struct net_device *dev,
3297 struct net_device *out_dev,
3298 int *ifindexes, int if_count,
3299 struct netlink_ext_ack *extack)
3300{
3301 int i;
3302
3303 for (i = 0; i < if_count; i++) {
3304 if (ifindexes[i] == out_dev->ifindex) {
3305 NL_SET_ERR_MSG_MOD(extack,
3306 "can't duplicate output to same device");
3307 netdev_err(dev, "can't duplicate output to same device: %s\n",
3308 out_dev->name);
3309 return true;
3310 }
3311 }
3312
3313 return false;
3314}
3315
73867881
PNA		 3316static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3317 struct flow_action *flow_action,
e98bedf5
EB		 3318 struct mlx5e_tc_flow *flow,
3319 struct netlink_ext_ack *extack)
03a9d11e 3320{
73867881 3321 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3322 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 3323 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 3324 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 3325 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3326 const struct ip_tunnel_info *info = NULL;
554fe75c 3327 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3328 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3329 const struct flow_action_entry *act;
554fe75c 3330 int err, i, if_count = 0;
a54e20b4 3331 bool encap = false;
1cab1cd7 3332 u32 action = 0;
03a9d11e 3333
73867881 3334 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3335 return -EINVAL;
3336
48855479
JP		 3337 if (!flow_action_hw_stats_types_check(flow_action, extack,
3338 FLOW_ACTION_HW_STATS_TYPE_DELAYED))
319a1d19
JP		 3339 return -EOPNOTSUPP;
3340
73867881
PNA		 3341 flow_action_for_each(i, act, flow_action) {
3342 switch (act->id) {
3343 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3344 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3345 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3346 break;
3347 case FLOW_ACTION_MANGLE:
3348 case FLOW_ACTION_ADD:
3349 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
dec481c8 3350 hdrs, extack);
d7e75a32
OG		 3351 if (err)
3352 return err;
3353
1cab1cd7 3354 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 3355 attr->split_count = attr->out_count;
73867881
PNA		 3356 break;
3357 case FLOW_ACTION_CSUM:
1cab1cd7 3358 if (csum_offload_supported(priv, action,
73867881
PNA		 3359 act->csum_flags, extack))
3360 break;
26c02749
OG		 3361
3362 return -EOPNOTSUPP;
73867881
PNA		 3363 case FLOW_ACTION_REDIRECT:
3364 case FLOW_ACTION_MIRRED: {
03a9d11e 3365 struct mlx5e_priv *out_priv;
592d3651 3366 struct net_device *out_dev;
03a9d11e 3367
73867881 3368 out_dev = act->dev;
ef381359
OS		 3369 if (!out_dev) {
3370 /* out_dev is NULL when filters with
3371 * non-existing mirred device are replayed to
3372 * the driver.
3373 */
3374 return -EINVAL;
3375 }
03a9d11e 3376
84179981
PB		 3377 if (ft_flow && out_dev == priv->netdev) {
3378 /* Ignore forward to self rules generated
3379 * by adding both mlx5 devs to the flow table
3380 * block on a normal nft offload setup.
3381 */
3382 return -EOPNOTSUPP;
3383 }
3384
592d3651 3385 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3386 NL_SET_ERR_MSG_MOD(extack,
3387 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3388 netdev_warn(priv->netdev,
3389 "can't support more than %d output ports, can't offload forwarding\n",
3390 attr->out_count);
592d3651
CM		 3391 return -EOPNOTSUPP;
3392 }
3393
f493f155
EB		 3394 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3395 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24
VB		 3396 if (encap) {
3397 parse_attr->mirred_ifindex[attr->out_count] =
3398 out_dev->ifindex;
3399 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3400 if (!parse_attr->tun_info[attr->out_count])
3401 return -ENOMEM;
3402 encap = false;
3403 attr->dests[attr->out_count].flags |=
3404 MLX5_ESW_DEST_ENCAP;
3405 attr->out_count++;
3406 /* attr->dests[].rep is resolved when we
3407 * handle encap
3408 */
3409 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3410 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3411 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
fa833bd5 3412 struct net_device *uplink_upper;
ffec9702 3413 struct mlx5e_rep_priv *rep_priv;
7ba58ba7 3414
554fe75c
DL		 3415 if (is_duplicated_output_device(priv->netdev,
3416 out_dev,
3417 ifindexes,
3418 if_count,
3419 extack))
3420 return -EOPNOTSUPP;
3421
3422 ifindexes[if_count] = out_dev->ifindex;
3423 if_count++;
3424
fa833bd5
VB		 3425 rcu_read_lock();
3426 uplink_upper =
3427 netdev_master_upper_dev_get_rcu(uplink_dev);
7ba58ba7
RL		 3428 if (uplink_upper &&
3429 netif_is_lag_master(uplink_upper) &&
3430 uplink_upper == out_dev)
3431 out_dev = uplink_dev;
fa833bd5 3432 rcu_read_unlock();
7ba58ba7 3433
278748a9
EB		 3434 if (is_vlan_dev(out_dev)) {
3435 err = add_vlan_push_action(priv, attr,
3436 &out_dev,
3437 &action);
3438 if (err)
3439 return err;
3440 }
f6dc1264 3441
35a605db
EB		 3442 if (is_vlan_dev(parse_attr->filter_dev)) {
3443 err = add_vlan_pop_action(priv, attr,
3444 &action);
3445 if (err)
3446 return err;
3447 }
278748a9 3448
ffec9702
TZ		 3449 /* Don't allow forwarding between uplink.
3450 *
3451 * Input vport was stored esw_attr->in_rep.
3452 * In LAG case, *priv* is the private data of
3453 * uplink which may be not the input vport.
3454 */
3455 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3456 if (mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3457 mlx5e_eswitch_uplink_rep(out_dev)) {
3458 NL_SET_ERR_MSG_MOD(extack,
3459 "devices are both uplink, can't offload forwarding");
3460 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3461 priv->netdev->name, out_dev->name);
3462 return -EOPNOTSUPP;
3463 }
3464
f6dc1264
PB		 3465 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3466 NL_SET_ERR_MSG_MOD(extack,
3467 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3468 netdev_warn(priv->netdev,
3469 "devices %s %s not on same switch HW, can't offload forwarding\n",
3470 priv->netdev->name,
3471 out_dev->name);
a0646c88 3472 return -EOPNOTSUPP;
f6dc1264 3473 }
a0646c88 3474
a54e20b4 3475 out_priv = netdev_priv(out_dev);
1d447a39 3476 rpriv = out_priv->ppriv;
df65a573
EB		 3477 attr->dests[attr->out_count].rep = rpriv->rep;
3478 attr->dests[attr->out_count].mdev = out_priv->mdev;
3479 attr->out_count++;
ef381359
OS		 3480 } else if (parse_attr->filter_dev != priv->netdev) {
3481 /* All mlx5 devices are called to configure
3482 * high level device filters. Therefore, the
3483 * *attempt* to install a filter on invalid
3484 * eswitch should not trigger an explicit error
3485 */
3486 return -EINVAL;
a54e20b4 3487 } else {
e98bedf5
EB		 3488 NL_SET_ERR_MSG_MOD(extack,
3489 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3490 netdev_warn(priv->netdev,
3491 "devices %s %s not on same switch HW, can't offload forwarding\n",
3492 priv->netdev->name,
3493 out_dev->name);
03a9d11e
OG		 3494 return -EINVAL;
3495 }
73867881
PNA		 3496 }
3497 break;
3498 case FLOW_ACTION_TUNNEL_ENCAP:
3499 info = act->tunnel;
a54e20b4
HHZ		 3500 if (info)
3501 encap = true;
3502 else
3503 return -EOPNOTSUPP;
1482bd3d 3504
73867881
PNA		 3505 break;
3506 case FLOW_ACTION_VLAN_PUSH:
3507 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3508 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3509 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3510 /* Replace vlan pop+push with vlan modify */
3511 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3512 err = add_vlan_rewrite_action(priv,
3513 MLX5_FLOW_NAMESPACE_FDB,
3514 act, parse_attr, hdrs,
3515 &action, extack);
3516 } else {
3517 err = parse_tc_vlan_action(priv, act, attr, &action);
3518 }
1482bd3d
JL		 3519 if (err)
3520 return err;
3521
bdc837ee
EB		 3522 attr->split_count = attr->out_count;
3523 break;
3524 case FLOW_ACTION_VLAN_MANGLE:
3525 err = add_vlan_rewrite_action(priv,
3526 MLX5_FLOW_NAMESPACE_FDB,
3527 act, parse_attr, hdrs,
3528 &action, extack);
3529 if (err)
3530 return err;
3531
e85e02ba 3532 attr->split_count = attr->out_count;
73867881
PNA		 3533 break;
3534 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 3535 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 3536 break;
3537 case FLOW_ACTION_GOTO: {
3538 u32 dest_chain = act->chain_index;
39ac237c 3539 u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
bf07aa73 3540
84179981
PB		 3541 if (ft_flow) {
3542 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3543 return -EOPNOTSUPP;
3544 }
297eaf5b
RD		 3545 if (!mlx5_esw_chains_backwards_supported(esw) &&
3546 dest_chain <= attr->chain) {
61644c3d
RD		 3547 NL_SET_ERR_MSG_MOD(extack,
3548 "Goto earlier chain isn't supported");
bf07aa73
PB		 3549 return -EOPNOTSUPP;
3550 }
3551 if (dest_chain > max_chain) {
61644c3d
RD		 3552 NL_SET_ERR_MSG_MOD(extack,
3553 "Requested destination chain is out of supported range");
bf07aa73
PB		 3554 return -EOPNOTSUPP;
3555 }
e88afe75 3556 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 3557 attr->dest_chain = dest_chain;
73867881
PNA		 3558 break;
3559 }
3560 default:
2cc1cb1d
TZ		 3561 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3562 return -EOPNOTSUPP;
bf07aa73 3563 }
03a9d11e 3564 }
bdd66ac0 3565
0bac1194
EB		 3566 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3567 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3568 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3569 * tag rewrite.
3570 */
3571 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3572 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3573 &action, extack);
3574 if (err)
3575 return err;
3576 }
3577
c500c86b
PNA		 3578 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3579 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3580 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3581 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3582 if (err)
3583 return err;
27c11b6b
EB		 3584 /* in case all pedit actions are skipped, remove the MOD_HDR
3585 * flag. we might have set split_count either by pedit or
3586 * pop/push. if there is no pop/push either, reset it too.
3587 */
3588 if (parse_attr->num_mod_hdr_actions == 0) {
3589 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60 3590 kfree(parse_attr->mod_hdr_actions);
27c11b6b
EB		 3591 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3592 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3593 attr->split_count = 0;
3594 }
c500c86b
PNA		 3595 }
3596
1cab1cd7 3597 attr->action = action;
73867881 3598 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3599 return -EOPNOTSUPP;
3600
e88afe75
OG		 3601 if (attr->dest_chain) {
3602 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 3603 NL_SET_ERR_MSG_MOD(extack,
3604 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 3605 return -EOPNOTSUPP;
3606 }
3607 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3608 }
3609
ae2741e2
VB		 3610 if (!(attr->action &
3611 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 3612 NL_SET_ERR_MSG_MOD(extack,
3613 "Rule must have at least one forward/drop action");
ae2741e2
VB		 3614 return -EOPNOTSUPP;
3615 }
3616
e85e02ba 3617 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3618 NL_SET_ERR_MSG_MOD(extack,
3619 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3620 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3621 return -EOPNOTSUPP;
3622 }
3623
31c8eba5 3624 return 0;
03a9d11e
OG		 3625}
3626
226f2ca3 3627static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3628{
226f2ca3 3629 unsigned long __flow_flags = 0;
60bd4af8 3630
226f2ca3
VB		 3631 if (flags & MLX5_TC_FLAG(INGRESS))
3632 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3633 if (flags & MLX5_TC_FLAG(EGRESS))
3634 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3635
226f2ca3
VB		 3636 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3637 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3638 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3639 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 3640 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3641 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 3642
60bd4af8
OG		 3643 *flow_flags = __flow_flags;
3644}
3645
05866c82
OG		 3646static const struct rhashtable_params tc_ht_params = {
3647 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3648 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3649 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3650 .automatic_shrinking = true,
3651};
3652
226f2ca3
VB		 3653static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3654 unsigned long flags)
05866c82 3655{
655dc3d2
OG		 3656 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3657 struct mlx5e_rep_priv *uplink_rpriv;
3658
226f2ca3 3659 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3660 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3661 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3662 } else /* NIC offload */
655dc3d2 3663 return &priv->fs.tc.ht;
05866c82
OG		 3664}
3665
04de7dda
RD		 3666static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3667{
1418ddd9 3668 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 3669 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3670 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3671 bool act_is_encap = !!(attr->action &
3672 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3673 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3674 MLX5_DEVCOM_ESW_OFFLOADS);
3675
10fbb1cd
RD		 3676 if (!esw_paired)
3677 return false;
3678
3679 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3680 mlx5_lag_is_multipath(attr->in_mdev)) &&
3681 (is_rep_ingress || act_is_encap))
3682 return true;
3683
3684 return false;
04de7dda
RD		 3685}
3686
a88780a9
RD		 3687static int
3688mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3689 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3690 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3691 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3692{
17091853 3693 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3694 struct mlx5e_tc_flow *flow;
5a7e5bcb 3695 int out_index, err;
e3a2b7ed 3696
65ba8fb7 3697 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3698 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3699 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3700 err = -ENOMEM;
3701 goto err_free;
3702 }
3703
3704 flow->cookie = f->cookie;
65ba8fb7 3705 flow->flags = flow_flags;
655dc3d2 3706 flow->priv = priv;
5a7e5bcb
VB		 3707 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3708 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3709 INIT_LIST_HEAD(&flow->mod_hdr);
3710 INIT_LIST_HEAD(&flow->hairpin);
3711 refcount_set(&flow->refcnt, 1);
95435ad7 3712 init_completion(&flow->init_done);
e3a2b7ed 3713
a88780a9
RD		 3714 *__flow = flow;
3715 *__parse_attr = parse_attr;
3716
3717 return 0;
3718
3719err_free:
3720 kfree(flow);
3721 kvfree(parse_attr);
3722 return err;
3723}
3724
988ab9c7
TZ		 3725static void
3726mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3727 struct mlx5e_priv *priv,
3728 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3729 struct flow_cls_offload *f,
988ab9c7
TZ		 3730 struct mlx5_eswitch_rep *in_rep,
3731 struct mlx5_core_dev *in_mdev)
3732{
3733 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3734
3735 esw_attr->parse_attr = parse_attr;
3736 esw_attr->chain = f->common.chain_index;
ef01adae 3737 esw_attr->prio = f->common.prio;
988ab9c7
TZ		 3738
3739 esw_attr->in_rep = in_rep;
3740 esw_attr->in_mdev = in_mdev;
3741
3742 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3743 MLX5_COUNTER_SOURCE_ESWITCH)
3744 esw_attr->counter_dev = in_mdev;
3745 else
3746 esw_attr->counter_dev = priv->mdev;
3747}
3748
71129676 3749static struct mlx5e_tc_flow *
04de7dda 3750__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3751 struct flow_cls_offload *f,
226f2ca3 3752 unsigned long flow_flags,
04de7dda
RD		 3753 struct net_device *filter_dev,
3754 struct mlx5_eswitch_rep *in_rep,
71129676 3755 struct mlx5_core_dev *in_mdev)
a88780a9 3756{
f9e30088 3757 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3758 struct netlink_ext_ack *extack = f->common.extack;
3759 struct mlx5e_tc_flow_parse_attr *parse_attr;
3760 struct mlx5e_tc_flow *flow;
3761 int attr_size, err;
e3a2b7ed 3762
226f2ca3 3763 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3764 attr_size = sizeof(struct mlx5_esw_flow_attr);
3765 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3766 &parse_attr, &flow);
3767 if (err)
3768 goto out;
988ab9c7 3769
d11afc26 3770 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 3771 mlx5e_flow_esw_attr_init(flow->esw_attr,
3772 priv, parse_attr,
3773 f, in_rep, in_mdev);
3774
54c177ca
OS		 3775 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3776 f, filter_dev);
d11afc26
OS		 3777 if (err)
3778 goto err_free;
a88780a9 3779
6f9af8ff 3780 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3781 if (err)
3782 goto err_free;
3783
7040632d 3784 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 3785 complete_all(&flow->init_done);
ef06c9ee
RD		 3786 if (err) {
3787 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3788 goto err_free;
3789
b4a23329 3790 add_unready_flow(flow);
ef06c9ee 3791 }
e3a2b7ed 3792
71129676 3793 return flow;
a88780a9
RD		 3794
3795err_free:
5a7e5bcb 3796 mlx5e_flow_put(priv, flow);
a88780a9 3797out:
71129676 3798 return ERR_PTR(err);
a88780a9
RD		 3799}
3800
f9e30088 3801static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3802 struct mlx5e_tc_flow *flow,
226f2ca3 3803 unsigned long flow_flags)
04de7dda
RD		 3804{
3805 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3806 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3807 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3808 struct mlx5e_tc_flow_parse_attr *parse_attr;
3809 struct mlx5e_rep_priv *peer_urpriv;
3810 struct mlx5e_tc_flow *peer_flow;
3811 struct mlx5_core_dev *in_mdev;
3812 int err = 0;
3813
3814 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3815 if (!peer_esw)
3816 return -ENODEV;
3817
3818 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3819 peer_priv = netdev_priv(peer_urpriv->netdev);
3820
3821 /* in_mdev is assigned of which the packet originated from.
3822 * So packets redirected to uplink use the same mdev of the
3823 * original flow and packets redirected from uplink use the
3824 * peer mdev.
3825 */
b05af6aa 3826 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3827 in_mdev = peer_priv->mdev;
3828 else
3829 in_mdev = priv->mdev;
3830
3831 parse_attr = flow->esw_attr->parse_attr;
95dc1902 3832 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 3833 parse_attr->filter_dev,
3834 flow->esw_attr->in_rep, in_mdev);
3835 if (IS_ERR(peer_flow)) {
3836 err = PTR_ERR(peer_flow);
04de7dda 3837 goto out;
71129676 3838 }
04de7dda
RD		 3839
3840 flow->peer_flow = peer_flow;
226f2ca3 3841 flow_flag_set(flow, DUP);
04de7dda
RD		 3842 mutex_lock(&esw->offloads.peer_mutex);
3843 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3844 mutex_unlock(&esw->offloads.peer_mutex);
3845
3846out:
3847 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3848 return err;
3849}
3850
3851static int
3852mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3853 struct flow_cls_offload *f,
226f2ca3 3854 unsigned long flow_flags,
04de7dda
RD		 3855 struct net_device *filter_dev,
3856 struct mlx5e_tc_flow **__flow)
3857{
3858 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3859 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3860 struct mlx5_core_dev *in_mdev = priv->mdev;
3861 struct mlx5e_tc_flow *flow;
3862 int err;
3863
71129676
JG		 3864 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3865 in_mdev);
3866 if (IS_ERR(flow))
3867 return PTR_ERR(flow);
04de7dda
RD		 3868
3869 if (is_peer_flow_needed(flow)) {
95dc1902 3870 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3871 if (err) {
3872 mlx5e_tc_del_fdb_flow(priv, flow);
3873 goto out;
3874 }
3875 }
3876
3877 *__flow = flow;
3878
3879 return 0;
3880
3881out:
3882 return err;
3883}
3884
a88780a9
RD		 3885static int
3886mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3887 struct flow_cls_offload *f,
226f2ca3 3888 unsigned long flow_flags,
d11afc26 3889 struct net_device *filter_dev,
a88780a9
RD		 3890 struct mlx5e_tc_flow **__flow)
3891{
f9e30088 3892 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3893 struct netlink_ext_ack *extack = f->common.extack;
3894 struct mlx5e_tc_flow_parse_attr *parse_attr;
3895 struct mlx5e_tc_flow *flow;
3896 int attr_size, err;
3897
bf07aa73
PB		 3898 /* multi-chain not supported for NIC rules */
3899 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3900 return -EOPNOTSUPP;
3901
226f2ca3 3902 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3903 attr_size = sizeof(struct mlx5_nic_flow_attr);
3904 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3905 &parse_attr, &flow);
3906 if (err)
3907 goto out;
3908
d11afc26 3909 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3910 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3911 f, filter_dev);
d11afc26
OS		 3912 if (err)
3913 goto err_free;
3914
73867881 3915 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3916 if (err)
3917 goto err_free;
3918
3919 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3920 if (err)
3921 goto err_free;
3922
226f2ca3 3923 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3924 kvfree(parse_attr);
3925 *__flow = flow;
3926
3927 return 0;
e3a2b7ed 3928
e3a2b7ed 3929err_free:
5a7e5bcb 3930 mlx5e_flow_put(priv, flow);
17091853 3931 kvfree(parse_attr);
a88780a9
RD		 3932out:
3933 return err;
3934}
3935
3936static int
3937mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3938 struct flow_cls_offload *f,
226f2ca3 3939 unsigned long flags,
d11afc26 3940 struct net_device *filter_dev,
a88780a9
RD		 3941 struct mlx5e_tc_flow **flow)
3942{
3943 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3944 unsigned long flow_flags;
a88780a9
RD		 3945 int err;
3946
3947 get_flags(flags, &flow_flags);
3948
bf07aa73
PB		 3949 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3950 return -EOPNOTSUPP;
3951
f6455de0 3952 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3953 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3954 filter_dev, flow);
a88780a9 3955 else
d11afc26
OS		 3956 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3957 filter_dev, flow);
a88780a9
RD		 3958
3959 return err;
3960}
3961
71d82d2a 3962int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3963 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3964{
3965 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3966 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3967 struct mlx5e_tc_flow *flow;
3968 int err = 0;
3969
c5d326b2
VB		 3970 rcu_read_lock();
3971 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3972 rcu_read_unlock();
a88780a9
RD		 3973 if (flow) {
3974 NL_SET_ERR_MSG_MOD(extack,
3975 "flow cookie already exists, ignoring");
3976 netdev_warn_once(priv->netdev,
3977 "flow cookie %lx already exists, ignoring\n",
3978 f->cookie);
0e1c1a2f 3979 err = -EEXIST;
a88780a9
RD		 3980 goto out;
3981 }
3982
7a978759 3983 trace_mlx5e_configure_flower(f);
d11afc26 3984 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3985 if (err)
3986 goto out;
3987
c5d326b2 3988 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 3989 if (err)
3990 goto err_free;
3991
3992 return 0;
3993
3994err_free:
5a7e5bcb 3995 mlx5e_flow_put(priv, flow);
a88780a9 3996out:
e3a2b7ed
AV		 3997 return err;
3998}
3999
8f8ae895
OG		 4000static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4001{
226f2ca3
VB		 4002 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4003 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4004
226f2ca3
VB		 4005 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4006 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4007}
4008
71d82d2a 4009int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4010 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4011{
d9ee0491 4012 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4013 struct mlx5e_tc_flow *flow;
c5d326b2 4014 int err;
e3a2b7ed 4015
c5d326b2 4016 rcu_read_lock();
ab818362 4017 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4018 if (!flow || !same_flow_direction(flow, flags)) {
4019 err = -EINVAL;
4020 goto errout;
4021 }
e3a2b7ed 4022
c5d326b2
VB		 4023 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4024 * set.
4025 */
4026 if (flow_flag_test_and_set(flow, DELETED)) {
4027 err = -EINVAL;
4028 goto errout;
4029 }
05866c82 4030 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4031 rcu_read_unlock();
e3a2b7ed 4032
7a978759 4033 trace_mlx5e_delete_flower(f);
5a7e5bcb 4034 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4035
4036 return 0;
c5d326b2
VB		 4037
4038errout:
4039 rcu_read_unlock();
4040 return err;
e3a2b7ed
AV		 4041}
4042
71d82d2a 4043int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4044 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4045{
04de7dda 4046 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4047 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4048 struct mlx5_eswitch *peer_esw;
aad7e08d 4049 struct mlx5e_tc_flow *flow;
aad7e08d 4050 struct mlx5_fc *counter;
316d5f72
RD		 4051 u64 lastuse = 0;
4052 u64 packets = 0;
4053 u64 bytes = 0;
5a7e5bcb 4054 int err = 0;
aad7e08d 4055
c5d326b2
VB		 4056 rcu_read_lock();
4057 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4058 tc_ht_params));
4059 rcu_read_unlock();
5a7e5bcb
VB		 4060 if (IS_ERR(flow))
4061 return PTR_ERR(flow);
4062
4063 if (!same_flow_direction(flow, flags)) {
4064 err = -EINVAL;
4065 goto errout;
4066 }
aad7e08d 4067
226f2ca3 4068 if (mlx5e_is_offloaded_flow(flow)) {
316d5f72
RD		 4069 counter = mlx5e_tc_get_counter(flow);
4070 if (!counter)
5a7e5bcb 4071 goto errout;
aad7e08d 4072
316d5f72
RD		 4073 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4074 }
aad7e08d 4075
316d5f72
RD		 4076 /* Under multipath it's possible for one rule to be currently
4077 * un-offloaded while the other rule is offloaded.
4078 */
04de7dda
RD		 4079 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4080 if (!peer_esw)
4081 goto out;
4082
226f2ca3
VB		 4083 if (flow_flag_test(flow, DUP) &&
4084 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4085 u64 bytes2;
4086 u64 packets2;
4087 u64 lastuse2;
4088
4089 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4090 if (!counter)
4091 goto no_peer_counter;
04de7dda
RD		 4092 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4093
4094 bytes += bytes2;
4095 packets += packets2;
4096 lastuse = max_t(u64, lastuse, lastuse2);
4097 }
4098
316d5f72 4099no_peer_counter:
04de7dda 4100 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4101out:
3b1903ef 4102 flow_stats_update(&f->stats, bytes, packets, lastuse);
7a978759 4103 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4104errout:
4105 mlx5e_flow_put(priv, flow);
4106 return err;
aad7e08d
AV		 4107}
4108
fcb64c0f
EC		 4109static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4110 struct netlink_ext_ack *extack)
4111{
4112 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4113 struct mlx5_eswitch *esw;
4114 u16 vport_num;
4115 u32 rate_mbps;
4116 int err;
4117
e401a184
EC		 4118 vport_num = rpriv->rep->vport;
4119 if (vport_num >= MLX5_VPORT_ECPF) {
4120 NL_SET_ERR_MSG_MOD(extack,
4121 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4122 return -EOPNOTSUPP;
4123 }
4124
fcb64c0f
EC		 4125 esw = priv->mdev->priv.eswitch;
4126 /* rate is given in bytes/sec.
4127 * First convert to bits/sec and then round to the nearest mbit/secs.
4128 * mbit means million bits.
4129 * Moreover, if rate is non zero we choose to configure to a minimum of
4130 * 1 mbit/sec.
4131 */
4132 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
fcb64c0f
EC		 4133 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4134 if (err)
4135 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4136
4137 return err;
4138}
4139
4140static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4141 struct flow_action *flow_action,
4142 struct netlink_ext_ack *extack)
4143{
4144 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4145 const struct flow_action_entry *act;
4146 int err;
4147 int i;
4148
4149 if (!flow_action_has_entries(flow_action)) {
4150 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4151 return -EINVAL;
4152 }
4153
4154 if (!flow_offload_has_one_action(flow_action)) {
4155 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4156 return -EOPNOTSUPP;
4157 }
4158
319a1d19
JP		 4159 if (!flow_action_basic_hw_stats_types_check(flow_action, extack))
4160 return -EOPNOTSUPP;
4161
fcb64c0f
EC		 4162 flow_action_for_each(i, act, flow_action) {
4163 switch (act->id) {
4164 case FLOW_ACTION_POLICE:
4165 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4166 if (err)
4167 return err;
4168
4169 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4170 break;
4171 default:
4172 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4173 return -EOPNOTSUPP;
4174 }
4175 }
4176
4177 return 0;
4178}
4179
4180int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4181 struct tc_cls_matchall_offload *ma)
4182{
4183 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4184
7b83355f 4185 if (ma->common.prio != 1) {
fcb64c0f
EC		 4186 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4187 return -EINVAL;
4188 }
4189
4190 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4191}
4192
4193int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4194 struct tc_cls_matchall_offload *ma)
4195{
4196 struct netlink_ext_ack *extack = ma->common.extack;
4197
4198 return apply_police_params(priv, 0, extack);
4199}
4200
4201void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4202 struct tc_cls_matchall_offload *ma)
4203{
4204 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4205 struct rtnl_link_stats64 cur_stats;
4206 u64 dbytes;
4207 u64 dpkts;
4208
4209 cur_stats = priv->stats.vf_vport;
4210 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4211 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4212 rpriv->prev_vf_vport_stats = cur_stats;
4213 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
4214}
4215
4d8fcf21
AH		 4216static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4217 struct mlx5e_priv *peer_priv)
4218{
4219 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4220 struct mlx5e_hairpin_entry *hpe, *tmp;
4221 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4222 u16 peer_vhca_id;
4223 int bkt;
4224
4225 if (!same_hw_devs(priv, peer_priv))
4226 return;
4227
4228 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4229
b32accda 4230 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4231 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4232 if (refcount_inc_not_zero(&hpe->refcnt))
4233 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4234 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4235
4236 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4237 wait_for_completion(&hpe->res_ready);
4238 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4239 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4240
4241 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4242 }
4243}
4244
4245static int mlx5e_tc_netdev_event(struct notifier_block *this,
4246 unsigned long event, void *ptr)
4247{
4248 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4249 struct mlx5e_flow_steering *fs;
4250 struct mlx5e_priv *peer_priv;
4251 struct mlx5e_tc_table *tc;
4252 struct mlx5e_priv *priv;
4253
4254 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4255 event != NETDEV_UNREGISTER ||
4256 ndev->reg_state == NETREG_REGISTERED)
4257 return NOTIFY_DONE;
4258
4259 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4260 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4261 priv = container_of(fs, struct mlx5e_priv, fs);
4262 peer_priv = netdev_priv(ndev);
4263 if (priv == peer_priv ||
4264 !(priv->netdev->features & NETIF_F_HW_TC))
4265 return NOTIFY_DONE;
4266
4267 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4268
4269 return NOTIFY_DONE;
4270}
4271
655dc3d2 4272int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4273{
acff797c 4274 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 4275 int err;
e8f887ac 4276
b6fac0b4 4277 mutex_init(&tc->t_lock);
d2faae25 4278 mutex_init(&tc->mod_hdr.lock);
dd58edc3 4279 hash_init(tc->mod_hdr.hlist);
b32accda 4280 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4281 hash_init(tc->hairpin_tbl);
11c9c548 4282
4d8fcf21
AH		 4283 err = rhashtable_init(&tc->ht, &tc_ht_params);
4284 if (err)
4285 return err;
4286
4287 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4288 err = register_netdevice_notifier_dev_net(priv->netdev,
4289 &tc->netdevice_nb,
4290 &tc->netdevice_nn);
4291 if (err) {
4d8fcf21
AH		 4292 tc->netdevice_nb.notifier_call = NULL;
4293 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4294 }
4295
4296 return err;
e8f887ac
AV		 4297}
4298
4299static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4300{
4301 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4302 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4303
961e8979 4304 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4305 kfree(flow);
4306}
4307
655dc3d2 4308void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4309{
acff797c 4310 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4311
4d8fcf21 4312 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4313 unregister_netdevice_notifier_dev_net(priv->netdev,
4314 &tc->netdevice_nb,
4315 &tc->netdevice_nn);
4d8fcf21 4316
d2faae25 4317 mutex_destroy(&tc->mod_hdr.lock);
b32accda
VB		 4318 mutex_destroy(&tc->hairpin_tbl_lock);
4319
d9ee0491 4320 rhashtable_destroy(&tc->ht);
e8f887ac 4321
acff797c
MG		 4322 if (!IS_ERR_OR_NULL(tc->t)) {
4323 mlx5_destroy_flow_table(tc->t);
4324 tc->t = NULL;
e8f887ac 4325 }
b6fac0b4 4326 mutex_destroy(&tc->t_lock);
e8f887ac 4327}
655dc3d2
OG		 4328
4329int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4330{
4331 return rhashtable_init(tc_ht, &tc_ht_params);
4332}
4333
4334void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4335{
4336 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4337}
01252a27 4338
226f2ca3 4339int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4340{
d9ee0491 4341 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4342
4343 return atomic_read(&tc_ht->nelems);
4344}
04de7dda
RD		 4345
4346void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4347{
4348 struct mlx5e_tc_flow *flow, *tmp;
4349
4350 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4351 __mlx5e_tc_del_fdb_peer_flow(flow);
4352}
b4a23329
RD		 4353
4354void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4355{
4356 struct mlx5_rep_uplink_priv *rpriv =
4357 container_of(work, struct mlx5_rep_uplink_priv,
4358 reoffload_flows_work);
4359 struct mlx5e_tc_flow *flow, *tmp;
4360
ad86755b 4361 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4362 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4363 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4364 unready_flow_del(flow);
b4a23329 4365 }
ad86755b 4366 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4367}
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