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net/mlx5e: CT: Handle misses after executing CT action
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
5a7e5bcb 41#include <linux/refcount.h>
db76ca24 42#include <linux/completion.h>
03a9d11e 43#include <net/tc_act/tc_mirred.h>
776b12b6 44#include <net/tc_act/tc_vlan.h>
bbd00f7e 45#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 46#include <net/tc_act/tc_pedit.h>
26c02749 47#include <net/tc_act/tc_csum.h>
f6dfb4c3 48#include <net/arp.h>
3616d08b 49#include <net/ipv6_stubs.h>
e8f887ac 50#include "en.h"
1d447a39 51#include "en_rep.h"
232c0013 52#include "en_tc.h"
03a9d11e 53#include "eswitch.h"
39ac237c 54#include "eswitch_offloads_chains.h"
3f6d08d1 55#include "fs_core.h"
2c81bfd5 56#include "en/port.h"
101f4de9 57#include "en/tc_tun.h"
0a7fcb78 58#include "en/mapping.h"
4c3844d9 59#include "en/tc_ct.h"
04de7dda 60#include "lib/devcom.h"
9272e3df 61#include "lib/geneve.h"
7a978759 62#include "diag/en_tc_tracepoint.h"
e8f887ac 63
0a7fcb78
PB		 64#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
65
3bc4b7bf
OG		 66struct mlx5_nic_flow_attr {
67 u32 action;
68 u32 flow_tag;
2b688ea5 69 struct mlx5_modify_hdr *modify_hdr;
5c65c564 70 u32 hairpin_tirn;
38aa51c1 71 u8 match_level;
3f6d08d1 72 struct mlx5_flow_table *hairpin_ft;
b8aee822 73 struct mlx5_fc *counter;
3bc4b7bf
OG		 74};
75
226f2ca3 76#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 77
65ba8fb7 78enum {
226f2ca3
VB		 79 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
80 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
81 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 82 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 83 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
84 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
85 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
86 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
87 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
88 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
89 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 90 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
4c3844d9 91 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
65ba8fb7
OG		 92};
93
e4ad91f2
CM		 94#define MLX5E_TC_MAX_SPLITS 1
95
79baaec7
EB		 96/* Helper struct for accessing a struct containing list_head array.
97 * Containing struct
98 * |- Helper array
99 * [0] Helper item 0
100 * |- list_head item 0
101 * |- index (0)
102 * [1] Helper item 1
103 * |- list_head item 1
104 * |- index (1)
105 * To access the containing struct from one of the list_head items:
106 * 1. Get the helper item from the list_head item using
107 * helper item =
108 * container_of(list_head item, helper struct type, list_head field)
109 * 2. Get the contining struct from the helper item and its index in the array:
110 * containing struct =
111 * container_of(helper item, containing struct type, helper field[index])
112 */
113struct encap_flow_item {
948993f2 114 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 115 struct list_head list;
116 int index;
117};
118
e8f887ac
AV		 119struct mlx5e_tc_flow {
120 struct rhash_head node;
655dc3d2 121 struct mlx5e_priv *priv;
e8f887ac 122 u64 cookie;
226f2ca3 123 unsigned long flags;
e4ad91f2 124 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 125 /* Flow can be associated with multiple encap IDs.
126 * The number of encaps is bounded by the number of supported
127 * destinations.
128 */
129 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 130 struct mlx5e_tc_flow *peer_flow;
dd58edc3 131 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
11c9c548 132 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
e4f9abbd 133 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 134 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 135 struct list_head peer; /* flows with peer flow */
b4a23329 136 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
2a1f1768 137 int tmp_efi_index;
6a06c2f7 138 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 139 refcount_t refcnt;
c5d326b2 140 struct rcu_head rcu_head;
95435ad7 141 struct completion init_done;
0a7fcb78
PB		 142 int tunnel_id; /* the mapped tunnel id of this flow */
143
3bc4b7bf
OG		 144 union {
145 struct mlx5_esw_flow_attr esw_attr[0];
146 struct mlx5_nic_flow_attr nic_attr[0];
147 };
e8f887ac
AV		 148};
149
17091853 150struct mlx5e_tc_flow_parse_attr {
1f6da306 151 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 152 struct net_device *filter_dev;
17091853 153 struct mlx5_flow_spec spec;
6ae4a6a5 154 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
98b66cb1 155 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 156};
157
acff797c 158#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 159#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 160
0a7fcb78
PB		 161struct tunnel_match_key {
162 struct flow_dissector_key_control enc_control;
163 struct flow_dissector_key_keyid enc_key_id;
164 struct flow_dissector_key_ports enc_tp;
165 struct flow_dissector_key_ip enc_ip;
166 union {
167 struct flow_dissector_key_ipv4_addrs enc_ipv4;
168 struct flow_dissector_key_ipv6_addrs enc_ipv6;
169 };
170
171 int filter_ifindex;
172};
173
174/* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
175 * Upper TUNNEL_INFO_BITS for general tunnel info.
176 * Lower ENC_OPTS_BITS bits for enc_opts.
177 */
178#define TUNNEL_INFO_BITS 6
179#define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
180#define ENC_OPTS_BITS 2
181#define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
182#define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
183#define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)
184
8f1e0b97
PB		 185struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
186 [CHAIN_TO_REG] = {
187 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
188 .moffset = 0,
189 .mlen = 2,
190 },
0a7fcb78
PB		 191 [TUNNEL_TO_REG] = {
192 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
193 .moffset = 3,
194 .mlen = 1,
195 .soffset = MLX5_BYTE_OFF(fte_match_param,
196 misc_parameters_2.metadata_reg_c_1),
197 },
4c3844d9
PB		 198 [ZONE_TO_REG] = zone_to_reg_ct,
199 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
200 [MARK_TO_REG] = mark_to_reg_ct,
201 [LABELS_TO_REG] = labels_to_reg_ct,
202 [FTEID_TO_REG] = fteid_to_reg_ct,
5c6b9460 203 [TUPLEID_TO_REG] = tupleid_to_reg_ct,
8f1e0b97
PB		 204};
205
0a7fcb78
PB		 206static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
207
208void
209mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
210 enum mlx5e_tc_attr_to_reg type,
211 u32 data,
212 u32 mask)
213{
214 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
215 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
216 void *headers_c = spec->match_criteria;
217 void *headers_v = spec->match_value;
218 void *fmask, *fval;
219
220 fmask = headers_c + soffset;
221 fval = headers_v + soffset;
222
223 mask = cpu_to_be32(mask) >> (32 - (match_len * 8));
224 data = cpu_to_be32(data) >> (32 - (match_len * 8));
225
226 memcpy(fmask, &mask, match_len);
227 memcpy(fval, &data, match_len);
228
229 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
230}
231
232int
233mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
234 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
235 enum mlx5e_tc_attr_to_reg type,
236 u32 data)
237{
238 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
239 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
240 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
241 char *modact;
242 int err;
243
244 err = alloc_mod_hdr_actions(mdev, MLX5_FLOW_NAMESPACE_FDB,
245 mod_hdr_acts);
246 if (err)
247 return err;
248
249 modact = mod_hdr_acts->actions +
250 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
251
252 /* Firmware has 5bit length field and 0 means 32bits */
253 if (mlen == 4)
254 mlen = 0;
255
256 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
257 MLX5_SET(set_action_in, modact, field, mfield);
258 MLX5_SET(set_action_in, modact, offset, moffset * 8);
259 MLX5_SET(set_action_in, modact, length, mlen * 8);
260 MLX5_SET(set_action_in, modact, data, data);
261 mod_hdr_acts->num_actions++;
262
263 return 0;
264}
265
77ab67b7
OG		 266struct mlx5e_hairpin {
267 struct mlx5_hairpin *pair;
268
269 struct mlx5_core_dev *func_mdev;
3f6d08d1 270 struct mlx5e_priv *func_priv;
77ab67b7
OG		 271 u32 tdn;
272 u32 tirn;
3f6d08d1
OG		 273
274 int num_channels;
275 struct mlx5e_rqt indir_rqt;
276 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
277 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 278};
279
5c65c564
OG		 280struct mlx5e_hairpin_entry {
281 /* a node of a hash table which keeps all the hairpin entries */
282 struct hlist_node hairpin_hlist;
283
73edca73
VB		 284 /* protects flows list */
285 spinlock_t flows_lock;
5c65c564
OG		 286 /* flows sharing the same hairpin */
287 struct list_head flows;
db76ca24
VB		 288 /* hpe's that were not fully initialized when dead peer update event
289 * function traversed them.
290 */
291 struct list_head dead_peer_wait_list;
5c65c564 292
d8822868 293 u16 peer_vhca_id;
106be53b 294 u8 prio;
5c65c564 295 struct mlx5e_hairpin *hp;
e4f9abbd 296 refcount_t refcnt;
db76ca24 297 struct completion res_ready;
5c65c564
OG		 298};
299
11c9c548
OG		 300struct mod_hdr_key {
301 int num_actions;
302 void *actions;
303};
304
305struct mlx5e_mod_hdr_entry {
306 /* a node of a hash table which keeps all the mod_hdr entries */
307 struct hlist_node mod_hdr_hlist;
308
83a52f0d
VB		 309 /* protects flows list */
310 spinlock_t flows_lock;
11c9c548
OG		 311 /* flows sharing the same mod_hdr entry */
312 struct list_head flows;
313
314 struct mod_hdr_key key;
315
2b688ea5 316 struct mlx5_modify_hdr *modify_hdr;
dd58edc3
VB		 317
318 refcount_t refcnt;
a734d007
VB		 319 struct completion res_ready;
320 int compl_result;
11c9c548
OG		 321};
322
5a7e5bcb
VB		 323static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
324 struct mlx5e_tc_flow *flow);
325
326static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
327{
328 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
329 return ERR_PTR(-EINVAL);
330 return flow;
331}
332
333static void mlx5e_flow_put(struct mlx5e_priv *priv,
334 struct mlx5e_tc_flow *flow)
335{
336 if (refcount_dec_and_test(&flow->refcnt)) {
337 mlx5e_tc_del_flow(priv, flow);
c5d326b2 338 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 339 }
340}
341
226f2ca3
VB		 342static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
343{
344 /* Complete all memory stores before setting bit. */
345 smp_mb__before_atomic();
346 set_bit(flag, &flow->flags);
347}
348
349#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
350
c5d326b2
VB		 351static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
352 unsigned long flag)
353{
354 /* test_and_set_bit() provides all necessary barriers */
355 return test_and_set_bit(flag, &flow->flags);
356}
357
358#define flow_flag_test_and_set(flow, flag) \
359 __flow_flag_test_and_set(flow, \
360 MLX5E_TC_FLOW_FLAG_##flag)
361
226f2ca3
VB		 362static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
363{
364 /* Complete all memory stores before clearing bit. */
365 smp_mb__before_atomic();
366 clear_bit(flag, &flow->flags);
367}
368
369#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
370 MLX5E_TC_FLOW_FLAG_##flag)
371
372static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
373{
374 bool ret = test_bit(flag, &flow->flags);
375
376 /* Read fields of flow structure only after checking flags. */
377 smp_mb__after_atomic();
378 return ret;
379}
380
381#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
382 MLX5E_TC_FLOW_FLAG_##flag)
383
384static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
385{
386 return flow_flag_test(flow, ESWITCH);
387}
388
84179981
PB		 389static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
390{
391 return flow_flag_test(flow, FT);
392}
393
226f2ca3
VB		 394static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
395{
396 return flow_flag_test(flow, OFFLOADED);
397}
398
11c9c548
OG		 399static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
400{
401 return jhash(key->actions,
402 key->num_actions * MLX5_MH_ACT_SZ, 0);
403}
404
405static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
406 struct mod_hdr_key *b)
407{
408 if (a->num_actions != b->num_actions)
409 return 1;
410
411 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
412}
413
dd58edc3
VB		 414static struct mod_hdr_tbl *
415get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
416{
417 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
418
419 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
420 &priv->fs.tc.mod_hdr;
421}
422
423static struct mlx5e_mod_hdr_entry *
424mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
425{
426 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
427
428 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
429 if (!cmp_mod_hdr_info(&mh->key, key)) {
430 refcount_inc(&mh->refcnt);
431 found = mh;
432 break;
433 }
434 }
435
436 return found;
437}
438
439static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
d2faae25
VB		 440 struct mlx5e_mod_hdr_entry *mh,
441 int namespace)
dd58edc3 442{
d2faae25
VB		 443 struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
444
445 if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
dd58edc3 446 return;
d2faae25
VB		 447 hash_del(&mh->mod_hdr_hlist);
448 mutex_unlock(&tbl->lock);
dd58edc3
VB		 449
450 WARN_ON(!list_empty(&mh->flows));
a734d007 451 if (mh->compl_result > 0)
2b688ea5 452 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
d2faae25 453
dd58edc3
VB		 454 kfree(mh);
455}
456
d2faae25
VB		 457static int get_flow_name_space(struct mlx5e_tc_flow *flow)
458{
459 return mlx5e_is_eswitch_flow(flow) ?
460 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
461}
11c9c548
OG		 462static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
463 struct mlx5e_tc_flow *flow,
464 struct mlx5e_tc_flow_parse_attr *parse_attr)
465{
11c9c548
OG		 466 int num_actions, actions_size, namespace, err;
467 struct mlx5e_mod_hdr_entry *mh;
dd58edc3 468 struct mod_hdr_tbl *tbl;
11c9c548 469 struct mod_hdr_key key;
11c9c548
OG		 470 u32 hash_key;
471
6ae4a6a5 472 num_actions = parse_attr->mod_hdr_acts.num_actions;
11c9c548
OG		 473 actions_size = MLX5_MH_ACT_SZ * num_actions;
474
6ae4a6a5 475 key.actions = parse_attr->mod_hdr_acts.actions;
11c9c548
OG		 476 key.num_actions = num_actions;
477
478 hash_key = hash_mod_hdr_info(&key);
479
d2faae25 480 namespace = get_flow_name_space(flow);
dd58edc3 481 tbl = get_mod_hdr_table(priv, namespace);
11c9c548 482
d2faae25 483 mutex_lock(&tbl->lock);
dd58edc3 484 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
a734d007
VB		 485 if (mh) {
486 mutex_unlock(&tbl->lock);
487 wait_for_completion(&mh->res_ready);
488
489 if (mh->compl_result < 0) {
490 err = -EREMOTEIO;
491 goto attach_header_err;
492 }
11c9c548 493 goto attach_flow;
a734d007 494 }
11c9c548
OG		 495
496 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
d2faae25 497 if (!mh) {
a734d007
VB		 498 mutex_unlock(&tbl->lock);
499 return -ENOMEM;
d2faae25 500 }
11c9c548
OG		 501
502 mh->key.actions = (void *)mh + sizeof(*mh);
503 memcpy(mh->key.actions, key.actions, actions_size);
504 mh->key.num_actions = num_actions;
83a52f0d 505 spin_lock_init(&mh->flows_lock);
11c9c548 506 INIT_LIST_HEAD(&mh->flows);
dd58edc3 507 refcount_set(&mh->refcnt, 1);
a734d007
VB		 508 init_completion(&mh->res_ready);
509
510 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
511 mutex_unlock(&tbl->lock);
11c9c548 512
2b688ea5
MG		 513 mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
514 mh->key.num_actions,
515 mh->key.actions);
516 if (IS_ERR(mh->modify_hdr)) {
517 err = PTR_ERR(mh->modify_hdr);
a734d007
VB		 518 mh->compl_result = err;
519 goto alloc_header_err;
520 }
521 mh->compl_result = 1;
522 complete_all(&mh->res_ready);
11c9c548
OG		 523
524attach_flow:
dd58edc3 525 flow->mh = mh;
83a52f0d 526 spin_lock(&mh->flows_lock);
11c9c548 527 list_add(&flow->mod_hdr, &mh->flows);
83a52f0d 528 spin_unlock(&mh->flows_lock);
d2faae25 529 if (mlx5e_is_eswitch_flow(flow))
2b688ea5 530 flow->esw_attr->modify_hdr = mh->modify_hdr;
11c9c548 531 else
2b688ea5 532 flow->nic_attr->modify_hdr = mh->modify_hdr;
11c9c548
OG		 533
534 return 0;
535
a734d007
VB		 536alloc_header_err:
537 complete_all(&mh->res_ready);
538attach_header_err:
539 mlx5e_mod_hdr_put(priv, mh, namespace);
11c9c548
OG		 540 return err;
541}
542
543static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
544 struct mlx5e_tc_flow *flow)
545{
5a7e5bcb 546 /* flow wasn't fully initialized */
dd58edc3 547 if (!flow->mh)
5a7e5bcb
VB		 548 return;
549
83a52f0d 550 spin_lock(&flow->mh->flows_lock);
11c9c548 551 list_del(&flow->mod_hdr);
83a52f0d 552 spin_unlock(&flow->mh->flows_lock);
11c9c548 553
d2faae25 554 mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
dd58edc3 555 flow->mh = NULL;
11c9c548
OG		 556}
557
77ab67b7
OG		 558static
559struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
560{
561 struct net_device *netdev;
562 struct mlx5e_priv *priv;
563
564 netdev = __dev_get_by_index(net, ifindex);
565 priv = netdev_priv(netdev);
566 return priv->mdev;
567}
568
569static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
570{
571 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
572 void *tirc;
573 int err;
574
575 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
576 if (err)
577 goto alloc_tdn_err;
578
579 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
580
581 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 582 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 583 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
584
585 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
586 if (err)
587 goto create_tir_err;
588
589 return 0;
590
591create_tir_err:
592 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
593alloc_tdn_err:
594 return err;
595}
596
597static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
598{
599 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
600 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
601}
602
3f6d08d1
OG		 603static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
604{
605 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
606 struct mlx5e_priv *priv = hp->func_priv;
607 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
608
609 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
610 hp->num_channels);
611
612 for (i = 0; i < sz; i++) {
613 ix = i;
bbeb53b8 614 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 615 ix = mlx5e_bits_invert(i, ilog2(sz));
616 ix = indirection_rqt[ix];
617 rqn = hp->pair->rqn[ix];
618 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
619 }
620}
621
622static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
623{
624 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
625 struct mlx5e_priv *priv = hp->func_priv;
626 struct mlx5_core_dev *mdev = priv->mdev;
627 void *rqtc;
628 u32 *in;
629
630 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
631 in = kvzalloc(inlen, GFP_KERNEL);
632 if (!in)
633 return -ENOMEM;
634
635 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
636
637 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
638 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
639
640 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
641
642 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
643 if (!err)
644 hp->indir_rqt.enabled = true;
645
646 kvfree(in);
647 return err;
648}
649
650static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
651{
652 struct mlx5e_priv *priv = hp->func_priv;
653 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
654 int tt, i, err;
655 void *tirc;
656
657 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 658 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
659
3f6d08d1
OG		 660 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
661 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
662
663 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
664 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
665 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 666 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
667
3f6d08d1
OG		 668 err = mlx5_core_create_tir(hp->func_mdev, in,
669 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
670 if (err) {
671 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
672 goto err_destroy_tirs;
673 }
674 }
675 return 0;
676
677err_destroy_tirs:
678 for (i = 0; i < tt; i++)
679 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
680 return err;
681}
682
683static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
684{
685 int tt;
686
687 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
688 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
689}
690
691static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
692 struct ttc_params *ttc_params)
693{
694 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
695 int tt;
696
697 memset(ttc_params, 0, sizeof(*ttc_params));
698
699 ttc_params->any_tt_tirn = hp->tirn;
700
701 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
702 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
703
6412bb39 704 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 705 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
706 ft_attr->prio = MLX5E_TC_PRIO;
707}
708
709static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
710{
711 struct mlx5e_priv *priv = hp->func_priv;
712 struct ttc_params ttc_params;
713 int err;
714
715 err = mlx5e_hairpin_create_indirect_rqt(hp);
716 if (err)
717 return err;
718
719 err = mlx5e_hairpin_create_indirect_tirs(hp);
720 if (err)
721 goto err_create_indirect_tirs;
722
723 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
724 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
725 if (err)
726 goto err_create_ttc_table;
727
728 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
729 hp->num_channels, hp->ttc.ft.t->id);
730
731 return 0;
732
733err_create_ttc_table:
734 mlx5e_hairpin_destroy_indirect_tirs(hp);
735err_create_indirect_tirs:
736 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
737
738 return err;
739}
740
741static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
742{
743 struct mlx5e_priv *priv = hp->func_priv;
744
745 mlx5e_destroy_ttc_table(priv, &hp->ttc);
746 mlx5e_hairpin_destroy_indirect_tirs(hp);
747 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
748}
749
77ab67b7
OG		 750static struct mlx5e_hairpin *
751mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
752 int peer_ifindex)
753{
754 struct mlx5_core_dev *func_mdev, *peer_mdev;
755 struct mlx5e_hairpin *hp;
756 struct mlx5_hairpin *pair;
757 int err;
758
759 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
760 if (!hp)
761 return ERR_PTR(-ENOMEM);
762
763 func_mdev = priv->mdev;
764 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
765
766 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
767 if (IS_ERR(pair)) {
768 err = PTR_ERR(pair);
769 goto create_pair_err;
770 }
771 hp->pair = pair;
772 hp->func_mdev = func_mdev;
3f6d08d1
OG		 773 hp->func_priv = priv;
774 hp->num_channels = params->num_channels;
77ab67b7
OG		 775
776 err = mlx5e_hairpin_create_transport(hp);
777 if (err)
778 goto create_transport_err;
779
3f6d08d1
OG		 780 if (hp->num_channels > 1) {
781 err = mlx5e_hairpin_rss_init(hp);
782 if (err)
783 goto rss_init_err;
784 }
785
77ab67b7
OG		 786 return hp;
787
3f6d08d1
OG		 788rss_init_err:
789 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 790create_transport_err:
791 mlx5_core_hairpin_destroy(hp->pair);
792create_pair_err:
793 kfree(hp);
794 return ERR_PTR(err);
795}
796
797static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
798{
3f6d08d1
OG		 799 if (hp->num_channels > 1)
800 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 801 mlx5e_hairpin_destroy_transport(hp);
802 mlx5_core_hairpin_destroy(hp->pair);
803 kvfree(hp);
804}
805
106be53b
OG		 806static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
807{
808 return (peer_vhca_id << 16 | prio);
809}
810
5c65c564 811static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 812 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 813{
814 struct mlx5e_hairpin_entry *hpe;
106be53b 815 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 816
817 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 818 hairpin_hlist, hash_key) {
e4f9abbd
VB		 819 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
820 refcount_inc(&hpe->refcnt);
5c65c564 821 return hpe;
e4f9abbd 822 }
5c65c564
OG		 823 }
824
825 return NULL;
826}
827
e4f9abbd
VB		 828static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
829 struct mlx5e_hairpin_entry *hpe)
830{
831 /* no more hairpin flows for us, release the hairpin pair */
b32accda 832 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 833 return;
b32accda
VB		 834 hash_del(&hpe->hairpin_hlist);
835 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 836
db76ca24
VB		 837 if (!IS_ERR_OR_NULL(hpe->hp)) {
838 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
839 dev_name(hpe->hp->pair->peer_mdev->device));
840
841 mlx5e_hairpin_destroy(hpe->hp);
842 }
e4f9abbd
VB		 843
844 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 845 kfree(hpe);
846}
847
106be53b
OG		 848#define UNKNOWN_MATCH_PRIO 8
849
850static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 851 struct mlx5_flow_spec *spec, u8 *match_prio,
852 struct netlink_ext_ack *extack)
106be53b
OG		 853{
854 void *headers_c, *headers_v;
855 u8 prio_val, prio_mask = 0;
856 bool vlan_present;
857
858#ifdef CONFIG_MLX5_CORE_EN_DCB
859 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 860 NL_SET_ERR_MSG_MOD(extack,
861 "only PCP trust state supported for hairpin");
106be53b
OG		 862 return -EOPNOTSUPP;
863 }
864#endif
865 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
866 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
867
868 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
869 if (vlan_present) {
870 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
871 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
872 }
873
874 if (!vlan_present || !prio_mask) {
875 prio_val = UNKNOWN_MATCH_PRIO;
876 } else if (prio_mask != 0x7) {
e98bedf5
EB		 877 NL_SET_ERR_MSG_MOD(extack,
878 "masked priority match not supported for hairpin");
106be53b
OG		 879 return -EOPNOTSUPP;
880 }
881
882 *match_prio = prio_val;
883 return 0;
884}
885
5c65c564
OG		 886static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
887 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 888 struct mlx5e_tc_flow_parse_attr *parse_attr,
889 struct netlink_ext_ack *extack)
5c65c564 890{
98b66cb1 891 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 892 struct mlx5_hairpin_params params;
d8822868 893 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 894 struct mlx5e_hairpin_entry *hpe;
895 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 896 u64 link_speed64;
897 u32 link_speed;
106be53b 898 u8 match_prio;
d8822868 899 u16 peer_id;
5c65c564
OG		 900 int err;
901
d8822868
OG		 902 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
903 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 904 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 905 return -EOPNOTSUPP;
906 }
907
d8822868 908 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 909 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
910 extack);
106be53b
OG		 911 if (err)
912 return err;
b32accda
VB		 913
914 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 915 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 916 if (hpe) {
917 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
918 wait_for_completion(&hpe->res_ready);
919
920 if (IS_ERR(hpe->hp)) {
921 err = -EREMOTEIO;
922 goto out_err;
923 }
5c65c564 924 goto attach_flow;
db76ca24 925 }
5c65c564
OG		 926
927 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 928 if (!hpe) {
db76ca24
VB		 929 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
930 return -ENOMEM;
b32accda 931 }
5c65c564 932
73edca73 933 spin_lock_init(&hpe->flows_lock);
5c65c564 934 INIT_LIST_HEAD(&hpe->flows);
db76ca24 935 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 936 hpe->peer_vhca_id = peer_id;
106be53b 937 hpe->prio = match_prio;
e4f9abbd 938 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 939 init_completion(&hpe->res_ready);
940
941 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
942 hash_hairpin_info(peer_id, match_prio));
943 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 944
945 params.log_data_size = 15;
946 params.log_data_size = min_t(u8, params.log_data_size,
947 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
948 params.log_data_size = max_t(u8, params.log_data_size,
949 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 950
eb9180f7
OG		 951 params.log_num_packets = params.log_data_size -
952 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
953 params.log_num_packets = min_t(u8, params.log_num_packets,
954 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
955
956 params.q_counter = priv->q_counter;
3f6d08d1 957 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 958 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 959 link_speed = max_t(u32, link_speed, 50000);
960 link_speed64 = link_speed;
961 do_div(link_speed64, 50000);
962 params.num_channels = link_speed64;
963
5c65c564 964 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 965 hpe->hp = hp;
966 complete_all(&hpe->res_ready);
5c65c564
OG		 967 if (IS_ERR(hp)) {
968 err = PTR_ERR(hp);
db76ca24 969 goto out_err;
5c65c564
OG		 970 }
971
eb9180f7 972 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 973 hp->tirn, hp->pair->rqn[0],
974 dev_name(hp->pair->peer_mdev->device),
eb9180f7 975 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 976
5c65c564 977attach_flow:
3f6d08d1 978 if (hpe->hp->num_channels > 1) {
226f2ca3 979 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 980 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
981 } else {
982 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
983 }
b32accda 984
e4f9abbd 985 flow->hpe = hpe;
73edca73 986 spin_lock(&hpe->flows_lock);
5c65c564 987 list_add(&flow->hairpin, &hpe->flows);
73edca73 988 spin_unlock(&hpe->flows_lock);
3f6d08d1 989
5c65c564
OG		 990 return 0;
991
db76ca24
VB		 992out_err:
993 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 994 return err;
995}
996
997static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
998 struct mlx5e_tc_flow *flow)
999{
5a7e5bcb 1000 /* flow wasn't fully initialized */
e4f9abbd 1001 if (!flow->hpe)
5a7e5bcb
VB		 1002 return;
1003
73edca73 1004 spin_lock(&flow->hpe->flows_lock);
5c65c564 1005 list_del(&flow->hairpin);
73edca73
VB		 1006 spin_unlock(&flow->hpe->flows_lock);
1007
e4f9abbd
VB		 1008 mlx5e_hairpin_put(priv, flow->hpe);
1009 flow->hpe = NULL;
5c65c564
OG		 1010}
1011
c83954ab 1012static int
74491de9 1013mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 1014 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 1015 struct mlx5e_tc_flow *flow,
1016 struct netlink_ext_ack *extack)
e8f887ac 1017{
bb0ee7dc 1018 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 1019 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 1020 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 1021 struct mlx5_flow_destination dest[2] = {};
66958ed9 1022 struct mlx5_flow_act flow_act = {
3bc4b7bf 1023 .action = attr->action,
bb0ee7dc 1024 .flags = FLOW_ACT_NO_APPEND,
66958ed9 1025 };
aad7e08d 1026 struct mlx5_fc *counter = NULL;
5c65c564 1027 int err, dest_ix = 0;
e8f887ac 1028
bb0ee7dc
JL		 1029 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1030 flow_context->flow_tag = attr->flow_tag;
1031
226f2ca3 1032 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 1033 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 1034 if (err)
1035 return err;
1036
226f2ca3 1037 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 1038 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1039 dest[dest_ix].ft = attr->hairpin_ft;
1040 } else {
5c65c564
OG		 1041 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1042 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 1043 }
1044 dest_ix++;
3f6d08d1
OG		 1045 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1046 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1047 dest[dest_ix].ft = priv->fs.vlan.ft.t;
1048 dest_ix++;
5c65c564 1049 }
aad7e08d 1050
5c65c564
OG		 1051 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1052 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 1053 if (IS_ERR(counter))
1054 return PTR_ERR(counter);
1055
5c65c564 1056 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 1057 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 1058 dest_ix++;
b8aee822 1059 attr->counter = counter;
aad7e08d
AV		 1060 }
1061
2f4fe4ca 1062 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 1063 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2b688ea5 1064 flow_act.modify_hdr = attr->modify_hdr;
6ae4a6a5 1065 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1066 if (err)
5a7e5bcb 1067 return err;
2f4fe4ca
OG		 1068 }
1069
b6fac0b4 1070 mutex_lock(&priv->fs.tc.t_lock);
acff797c 1071 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
61dc7b01
PB		 1072 struct mlx5_flow_table_attr ft_attr = {};
1073 int tc_grp_size, tc_tbl_size, tc_num_grps;
21b9c144
OG		 1074 u32 max_flow_counter;
1075
1076 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
1077 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
1078
1079 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
1080
1081 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
1082 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
61dc7b01 1083 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
21b9c144 1084
61dc7b01
PB		 1085 ft_attr.prio = MLX5E_TC_PRIO;
1086 ft_attr.max_fte = tc_tbl_size;
1087 ft_attr.level = MLX5E_TC_FT_LEVEL;
1088 ft_attr.autogroup.max_num_groups = tc_num_grps;
acff797c
MG		 1089 priv->fs.tc.t =
1090 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
61dc7b01 1091 &ft_attr);
acff797c 1092 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 1093 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5
EB		 1094 NL_SET_ERR_MSG_MOD(extack,
1095 "Failed to create tc offload table\n");
e8f887ac
AV		 1096 netdev_err(priv->netdev,
1097 "Failed to create tc offload table\n");
5a7e5bcb 1098 return PTR_ERR(priv->fs.tc.t);
e8f887ac 1099 }
e8f887ac
AV		 1100 }
1101
38aa51c1 1102 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 1103 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1104
c83954ab
RL		 1105 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
1106 &flow_act, dest, dest_ix);
b6fac0b4 1107 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 1108
a2b7189b 1109 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1110}
1111
d85cdccb
OG		 1112static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1113 struct mlx5e_tc_flow *flow)
1114{
513f8f7f 1115 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 1116 struct mlx5_fc *counter = NULL;
1117
b8aee822 1118 counter = attr->counter;
5a7e5bcb
VB		 1119 if (!IS_ERR_OR_NULL(flow->rule[0]))
1120 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 1121 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 1122
b6fac0b4 1123 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 1124 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 1125 mlx5_destroy_flow_table(priv->fs.tc.t);
1126 priv->fs.tc.t = NULL;
1127 }
b6fac0b4 1128 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1129
513f8f7f 1130 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1131 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1132
226f2ca3 1133 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1134 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 1135}
1136
aa0cbbae 1137static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1138 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1139
3c37745e 1140static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1141 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1142 struct net_device *mirred_dev,
1143 int out_index,
8c4dc42b 1144 struct netlink_ext_ack *extack,
0ad060ee
RD		 1145 struct net_device **encap_dev,
1146 bool *encap_valid);
3c37745e 1147
6d2a3ed0
OG		 1148static struct mlx5_flow_handle *
1149mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1150 struct mlx5e_tc_flow *flow,
1151 struct mlx5_flow_spec *spec,
1152 struct mlx5_esw_flow_attr *attr)
1153{
1154 struct mlx5_flow_handle *rule;
4c3844d9
PB		 1155 struct mlx5e_tc_mod_hdr_acts;
1156
1157 if (flow_flag_test(flow, CT))
1158 return mlx5_tc_ct_flow_offload(flow->priv, flow, spec, attr);
6d2a3ed0
OG		 1159
1160 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1161 if (IS_ERR(rule))
1162 return rule;
1163
e85e02ba 1164 if (attr->split_count) {
6d2a3ed0
OG		 1165 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1166 if (IS_ERR(flow->rule[1])) {
1167 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1168 return flow->rule[1];
1169 }
1170 }
1171
6d2a3ed0
OG		 1172 return rule;
1173}
1174
1175static void
1176mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1177 struct mlx5e_tc_flow *flow,
4c3844d9 1178 struct mlx5_esw_flow_attr *attr)
6d2a3ed0 1179{
226f2ca3 1180 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1181
4c3844d9
PB		 1182 if (flow_flag_test(flow, CT)) {
1183 mlx5_tc_ct_delete_flow(flow->priv, flow, attr);
1184 return;
1185 }
1186
e85e02ba 1187 if (attr->split_count)
6d2a3ed0
OG		 1188 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1189
1190 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1191}
1192
5dbe906f
PB		 1193static struct mlx5_flow_handle *
1194mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1195 struct mlx5e_tc_flow *flow,
178f69b4 1196 struct mlx5_flow_spec *spec)
5dbe906f 1197{
178f69b4 1198 struct mlx5_esw_flow_attr slow_attr;
5dbe906f
PB		 1199 struct mlx5_flow_handle *rule;
1200
178f69b4
EC		 1201 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1202 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1203 slow_attr.split_count = 0;
1204 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
5dbe906f 1205
178f69b4 1206 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr);
5dbe906f 1207 if (!IS_ERR(rule))
226f2ca3 1208 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1209
1210 return rule;
1211}
1212
1213static void
1214mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1215 struct mlx5e_tc_flow *flow)
5dbe906f 1216{
178f69b4
EC		 1217 struct mlx5_esw_flow_attr slow_attr;
1218
1219 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1220 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1221 slow_attr.split_count = 0;
1222 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1223 mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr);
226f2ca3 1224 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1225}
1226
ad86755b
VB		 1227/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1228 * function.
1229 */
1230static void unready_flow_add(struct mlx5e_tc_flow *flow,
1231 struct list_head *unready_flows)
1232{
1233 flow_flag_set(flow, NOT_READY);
1234 list_add_tail(&flow->unready, unready_flows);
1235}
1236
1237/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1238 * function.
1239 */
1240static void unready_flow_del(struct mlx5e_tc_flow *flow)
1241{
1242 list_del(&flow->unready);
1243 flow_flag_clear(flow, NOT_READY);
1244}
1245
b4a23329
RD		 1246static void add_unready_flow(struct mlx5e_tc_flow *flow)
1247{
1248 struct mlx5_rep_uplink_priv *uplink_priv;
1249 struct mlx5e_rep_priv *rpriv;
1250 struct mlx5_eswitch *esw;
1251
1252 esw = flow->priv->mdev->priv.eswitch;
1253 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1254 uplink_priv = &rpriv->uplink_priv;
1255
ad86755b
VB		 1256 mutex_lock(&uplink_priv->unready_flows_lock);
1257 unready_flow_add(flow, &uplink_priv->unready_flows);
1258 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1259}
1260
1261static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1262{
ad86755b
VB		 1263 struct mlx5_rep_uplink_priv *uplink_priv;
1264 struct mlx5e_rep_priv *rpriv;
1265 struct mlx5_eswitch *esw;
1266
1267 esw = flow->priv->mdev->priv.eswitch;
1268 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1269 uplink_priv = &rpriv->uplink_priv;
1270
1271 mutex_lock(&uplink_priv->unready_flows_lock);
1272 unready_flow_del(flow);
1273 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1274}
1275
c83954ab 1276static int
74491de9 1277mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1278 struct mlx5e_tc_flow *flow,
1279 struct netlink_ext_ack *extack)
adb4c123
OG		 1280{
1281 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 1282 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1283 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3c37745e 1284 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1285 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1286 struct mlx5e_rep_priv *rpriv;
1287 struct mlx5e_priv *out_priv;
0ad060ee 1288 bool encap_valid = true;
39ac237c 1289 u32 max_prio, max_chain;
0ad060ee 1290 int err = 0;
f493f155 1291 int out_index;
8b32580d 1292
39ac237c 1293 if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
61644c3d
RD		 1294 NL_SET_ERR_MSG_MOD(extack,
1295 "E-switch priorities unsupported, upgrade FW");
d14f6f2a
OG		 1296 return -EOPNOTSUPP;
1297 }
bf07aa73 1298
84179981
PB		 1299 /* We check chain range only for tc flows.
1300 * For ft flows, we checked attr->chain was originally 0 and set it to
1301 * FDB_FT_CHAIN which is outside tc range.
1302 * See mlx5e_rep_setup_ft_cb().
1303 */
39ac237c 1304 max_chain = mlx5_esw_chains_get_chain_range(esw);
84179981 1305 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1306 NL_SET_ERR_MSG_MOD(extack,
1307 "Requested chain is out of supported range");
5a7e5bcb 1308 return -EOPNOTSUPP;
bf07aa73
PB		 1309 }
1310
39ac237c 1311 max_prio = mlx5_esw_chains_get_prio_range(esw);
bf07aa73 1312 if (attr->prio > max_prio) {
61644c3d
RD		 1313 NL_SET_ERR_MSG_MOD(extack,
1314 "Requested priority is out of supported range");
5a7e5bcb 1315 return -EOPNOTSUPP;
bf07aa73 1316 }
e52c2802 1317
f493f155 1318 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1319 int mirred_ifindex;
1320
f493f155
EB		 1321 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1322 continue;
1323
7040632d 1324 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1325 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1326 mirred_ifindex);
733d4f36 1327 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1328 extack, &encap_dev, &encap_valid);
1329 if (err)
5a7e5bcb 1330 return err;
0ad060ee 1331
3c37745e
OG		 1332 out_priv = netdev_priv(encap_dev);
1333 rpriv = out_priv->ppriv;
1cc26d74
EB		 1334 attr->dests[out_index].rep = rpriv->rep;
1335 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1336 }
1337
8b32580d 1338 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1339 if (err)
5a7e5bcb 1340 return err;
adb4c123 1341
d7e75a32 1342 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1343 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
6ae4a6a5 1344 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1345 if (err)
5a7e5bcb 1346 return err;
d7e75a32
OG		 1347 }
1348
b8aee822 1349 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1350 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1351 if (IS_ERR(counter))
1352 return PTR_ERR(counter);
b8aee822
MB		 1353
1354 attr->counter = counter;
1355 }
1356
0ad060ee
RD		 1357 /* we get here if one of the following takes place:
1358 * (1) there's no error
1359 * (2) there's an encap action and we don't have valid neigh
3c37745e 1360 */
bc1d75fa 1361 if (!encap_valid)
178f69b4 1362 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1363 else
6d2a3ed0 1364 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1365
5a7e5bcb
VB		 1366 if (IS_ERR(flow->rule[0]))
1367 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1368 else
1369 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1370
1371 return 0;
aa0cbbae 1372}
d85cdccb 1373
9272e3df
YK		 1374static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1375{
1376 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1377 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1378 spec->match_value,
1379 misc_parameters_3);
1380 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1381 headers_v,
1382 geneve_tlv_option_0_data);
1383
1384 return !!geneve_tlv_opt_0_data;
1385}
1386
d85cdccb
OG		 1387static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1388 struct mlx5e_tc_flow *flow)
1389{
1390 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1391 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
f493f155 1392 int out_index;
d85cdccb 1393
0a7fcb78
PB		 1394 mlx5e_put_flow_tunnel_id(flow);
1395
226f2ca3 1396 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1397 remove_unready_flow(flow);
ef06c9ee
RD		 1398 kvfree(attr->parse_attr);
1399 return;
1400 }
1401
226f2ca3
VB		 1402 if (mlx5e_is_offloaded_flow(flow)) {
1403 if (flow_flag_test(flow, SLOW))
178f69b4 1404 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1405 else
1406 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1407 }
d85cdccb 1408
9272e3df
YK		 1409 if (mlx5_flow_has_geneve_opt(flow))
1410 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1411
513f8f7f 1412 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1413
f493f155 1414 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
2a4b6526 1415 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1416 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1417 kfree(attr->parse_attr->tun_info[out_index]);
1418 }
f493f155 1419 kvfree(attr->parse_attr);
d7e75a32 1420
513f8f7f 1421 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1422 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1423
1424 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1425 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1426}
1427
232c0013 1428void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1429 struct mlx5e_encap_entry *e,
1430 struct list_head *flow_list)
232c0013 1431{
3c37745e 1432 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1433 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0
OG		 1434 struct mlx5_flow_handle *rule;
1435 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1436 struct mlx5e_tc_flow *flow;
1437 int err;
1438
2b688ea5
MG		 1439 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1440 e->reformat_type,
1441 e->encap_size, e->encap_header,
1442 MLX5_FLOW_NAMESPACE_FDB);
1443 if (IS_ERR(e->pkt_reformat)) {
1444 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1445 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1446 return;
1447 }
1448 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1449 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1450
2a1f1768 1451 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1452 bool all_flow_encaps_valid = true;
1453 int i;
1454
95435ad7
VB		 1455 if (!mlx5e_is_offloaded_flow(flow))
1456 continue;
3c37745e 1457 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1458 spec = &esw_attr->parse_attr->spec;
1459
2b688ea5 1460 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1461 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1462 /* Flow can be associated with multiple encap entries.
1463 * Before offloading the flow verify that all of them have
1464 * a valid neighbour.
1465 */
1466 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1467 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1468 continue;
1469 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1470 all_flow_encaps_valid = false;
1471 break;
1472 }
1473 }
1474 /* Do not offload flows with unresolved neighbors */
1475 if (!all_flow_encaps_valid)
2a1f1768 1476 continue;
5dbe906f 1477 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1478 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1479 if (IS_ERR(rule)) {
1480 err = PTR_ERR(rule);
232c0013
HHZ		 1481 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1482 err);
2a1f1768 1483 continue;
232c0013 1484 }
5dbe906f 1485
178f69b4 1486 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1487 flow->rule[0] = rule;
226f2ca3
VB		 1488 /* was unset when slow path rule removed */
1489 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1490 }
1491}
1492
1493void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1494 struct mlx5e_encap_entry *e,
1495 struct list_head *flow_list)
232c0013 1496{
3c37745e 1497 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1498 struct mlx5_flow_handle *rule;
1499 struct mlx5_flow_spec *spec;
232c0013 1500 struct mlx5e_tc_flow *flow;
5dbe906f 1501 int err;
232c0013 1502
2a1f1768 1503 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1504 if (!mlx5e_is_offloaded_flow(flow))
1505 continue;
5dbe906f
PB		 1506 spec = &flow->esw_attr->parse_attr->spec;
1507
1508 /* update from encap rule to slow path rule */
178f69b4 1509 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1510 /* mark the flow's encap dest as non-valid */
2a1f1768 1511 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1512
1513 if (IS_ERR(rule)) {
1514 err = PTR_ERR(rule);
1515 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1516 err);
2a1f1768 1517 continue;
5dbe906f
PB		 1518 }
1519
1520 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1521 flow->rule[0] = rule;
226f2ca3
VB		 1522 /* was unset when fast path rule removed */
1523 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1524 }
1525
61c806da
OG		 1526 /* we know that the encap is valid */
1527 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1528 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1529}
1530
b8aee822
MB		 1531static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1532{
226f2ca3 1533 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1534 return flow->esw_attr->counter;
1535 else
1536 return flow->nic_attr->counter;
1537}
1538
2a1f1768
VB		 1539/* Takes reference to all flows attached to encap and adds the flows to
1540 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1541 */
1542void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1543{
1544 struct encap_flow_item *efi;
1545 struct mlx5e_tc_flow *flow;
1546
1547 list_for_each_entry(efi, &e->flows, list) {
1548 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1549 if (IS_ERR(mlx5e_flow_get(flow)))
1550 continue;
95435ad7 1551 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1552
1553 flow->tmp_efi_index = efi->index;
1554 list_add(&flow->tmp_list, flow_list);
1555 }
1556}
1557
6a06c2f7 1558/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1559void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1560{
1561 struct mlx5e_tc_flow *flow, *tmp;
1562
1563 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1564 mlx5e_flow_put(priv, flow);
1565}
1566
ac0d9176
VB		 1567static struct mlx5e_encap_entry *
1568mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1569 struct mlx5e_encap_entry *e)
1570{
1571 struct mlx5e_encap_entry *next = NULL;
1572
1573retry:
1574 rcu_read_lock();
1575
1576 /* find encap with non-zero reference counter value */
1577 for (next = e ?
1578 list_next_or_null_rcu(&nhe->encap_list,
1579 &e->encap_list,
1580 struct mlx5e_encap_entry,
1581 encap_list) :
1582 list_first_or_null_rcu(&nhe->encap_list,
1583 struct mlx5e_encap_entry,
1584 encap_list);
1585 next;
1586 next = list_next_or_null_rcu(&nhe->encap_list,
1587 &next->encap_list,
1588 struct mlx5e_encap_entry,
1589 encap_list))
1590 if (mlx5e_encap_take(next))
1591 break;
1592
1593 rcu_read_unlock();
1594
1595 /* release starting encap */
1596 if (e)
1597 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1598 if (!next)
1599 return next;
1600
1601 /* wait for encap to be fully initialized */
1602 wait_for_completion(&next->res_ready);
1603 /* continue searching if encap entry is not in valid state after completion */
1604 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1605 e = next;
1606 goto retry;
1607 }
1608
1609 return next;
1610}
1611
f6dfb4c3
HHZ		 1612void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1613{
1614 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1615 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1616 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1617 struct mlx5_fc *counter;
1618 struct neigh_table *tbl;
1619 bool neigh_used = false;
1620 struct neighbour *n;
90bb7692 1621 u64 lastuse;
f6dfb4c3
HHZ		 1622
1623 if (m_neigh->family == AF_INET)
1624 tbl = &arp_tbl;
1625#if IS_ENABLED(CONFIG_IPV6)
1626 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1627 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1628#endif
1629 else
1630 return;
1631
ac0d9176
VB		 1632 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1633 * next one.
1634 */
1635 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1636 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1637 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1638 struct mlx5_eswitch *esw;
1639 LIST_HEAD(flow_list);
948993f2 1640
6a06c2f7
VB		 1641 esw = priv->mdev->priv.eswitch;
1642 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1643 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1644 flow = container_of(efi, struct mlx5e_tc_flow,
1645 encaps[efi->index]);
5a7e5bcb
VB		 1646 if (IS_ERR(mlx5e_flow_get(flow)))
1647 continue;
6a06c2f7 1648 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1649
226f2ca3 1650 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1651 counter = mlx5e_tc_get_counter(flow);
90bb7692 1652 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1653 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1654 neigh_used = true;
1655 break;
1656 }
1657 }
1658 }
6a06c2f7 1659 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1660
6a06c2f7 1661 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1662 if (neigh_used) {
1663 /* release current encap before breaking the loop */
6a06c2f7 1664 mlx5e_encap_put(priv, e);
e36d4810 1665 break;
ac0d9176 1666 }
f6dfb4c3
HHZ		 1667 }
1668
c786fe59
VB		 1669 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1670
f6dfb4c3
HHZ		 1671 if (neigh_used) {
1672 nhe->reported_lastuse = jiffies;
1673
1674 /* find the relevant neigh according to the cached device and
1675 * dst ip pair
1676 */
1677 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1678 if (!n)
f6dfb4c3 1679 return;
f6dfb4c3
HHZ		 1680
1681 neigh_event_send(n, NULL);
1682 neigh_release(n);
1683 }
1684}
1685
61086f39 1686static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1687{
948993f2 1688 WARN_ON(!list_empty(&e->flows));
948993f2 1689
3c140dd5
VB		 1690 if (e->compl_result > 0) {
1691 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1692
1693 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1694 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1695 }
948993f2 1696
2a4b6526 1697 kfree(e->tun_info);
948993f2 1698 kfree(e->encap_header);
ac0d9176 1699 kfree_rcu(e, rcu);
948993f2
VB		 1700}
1701
61086f39
VB		 1702void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1703{
1704 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1705
1706 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1707 return;
1708 hash_del_rcu(&e->encap_hlist);
1709 mutex_unlock(&esw->offloads.encap_tbl_lock);
1710
1711 mlx5e_encap_dealloc(priv, e);
1712}
1713
d85cdccb 1714static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1715 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1716{
61086f39
VB		 1717 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1718 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1719
5a7e5bcb 1720 /* flow wasn't fully initialized */
61086f39 1721 if (!e)
5a7e5bcb
VB		 1722 return;
1723
61086f39 1724 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1725 list_del(&flow->encaps[out_index].list);
948993f2 1726 flow->encaps[out_index].e = NULL;
61086f39
VB		 1727 if (!refcount_dec_and_test(&e->refcnt)) {
1728 mutex_unlock(&esw->offloads.encap_tbl_lock);
1729 return;
1730 }
1731 hash_del_rcu(&e->encap_hlist);
1732 mutex_unlock(&esw->offloads.encap_tbl_lock);
1733
1734 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1735}
1736
04de7dda
RD		 1737static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1738{
1739 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1740
226f2ca3
VB		 1741 if (!flow_flag_test(flow, ESWITCH) ||
1742 !flow_flag_test(flow, DUP))
04de7dda
RD		 1743 return;
1744
1745 mutex_lock(&esw->offloads.peer_mutex);
1746 list_del(&flow->peer);
1747 mutex_unlock(&esw->offloads.peer_mutex);
1748
226f2ca3 1749 flow_flag_clear(flow, DUP);
04de7dda 1750
eb252c3a
RD		 1751 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1752 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1753 kfree(flow->peer_flow);
1754 }
1755
04de7dda
RD		 1756 flow->peer_flow = NULL;
1757}
1758
1759static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1760{
1761 struct mlx5_core_dev *dev = flow->priv->mdev;
1762 struct mlx5_devcom *devcom = dev->priv.devcom;
1763 struct mlx5_eswitch *peer_esw;
1764
1765 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1766 if (!peer_esw)
1767 return;
1768
1769 __mlx5e_tc_del_fdb_peer_flow(flow);
1770 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1771}
1772
e8f887ac 1773static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1774 struct mlx5e_tc_flow *flow)
e8f887ac 1775{
226f2ca3 1776 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1777 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1778 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1779 } else {
d85cdccb 1780 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1781 }
e8f887ac
AV		 1782}
1783
0a7fcb78
PB		 1784static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1785{
1786 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1787 struct flow_action *flow_action = &rule->action;
1788 const struct flow_action_entry *act;
1789 int i;
1790
1791 flow_action_for_each(i, act, flow_action) {
1792 switch (act->id) {
1793 case FLOW_ACTION_GOTO:
1794 return true;
1795 default:
1796 continue;
1797 }
1798 }
1799
1800 return false;
1801}
bbd00f7e 1802
0a7fcb78
PB		 1803static int
1804enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1805 struct flow_dissector_key_enc_opts *opts,
1806 struct netlink_ext_ack *extack,
1807 bool *dont_care)
1808{
1809 struct geneve_opt *opt;
1810 int off = 0;
1811
1812 *dont_care = true;
1813
1814 while (opts->len > off) {
1815 opt = (struct geneve_opt *)&opts->data[off];
1816
1817 if (!(*dont_care) || opt->opt_class || opt->type ||
1818 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1819 *dont_care = false;
1820
1821 if (opt->opt_class != U16_MAX ||
1822 opt->type != U8_MAX ||
1823 memchr_inv(opt->opt_data, 0xFF,
1824 opt->length * 4)) {
1825 NL_SET_ERR_MSG(extack,
1826 "Partial match of tunnel options in chain > 0 isn't supported");
1827 netdev_warn(priv->netdev,
1828 "Partial match of tunnel options in chain > 0 isn't supported");
1829 return -EOPNOTSUPP;
1830 }
1831 }
1832
1833 off += sizeof(struct geneve_opt) + opt->length * 4;
1834 }
1835
1836 return 0;
1837}
1838
1839#define COPY_DISSECTOR(rule, diss_key, dst)\
1840({ \
1841 struct flow_rule *__rule = (rule);\
1842 typeof(dst) __dst = dst;\
1843\
1844 memcpy(__dst,\
1845 skb_flow_dissector_target(__rule->match.dissector,\
1846 diss_key,\
1847 __rule->match.key),\
1848 sizeof(*__dst));\
1849})
1850
1851static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1852 struct mlx5e_tc_flow *flow,
1853 struct flow_cls_offload *f,
1854 struct net_device *filter_dev)
bbd00f7e 1855{
f9e30088 1856 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78
PB		 1857 struct netlink_ext_ack *extack = f->common.extack;
1858 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1859 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1860 struct flow_match_enc_opts enc_opts_match;
1861 struct mlx5_rep_uplink_priv *uplink_priv;
1862 struct mlx5e_rep_priv *uplink_rpriv;
1863 struct tunnel_match_key tunnel_key;
1864 bool enc_opts_is_dont_care = true;
1865 u32 tun_id, enc_opts_id = 0;
1866 struct mlx5_eswitch *esw;
1867 u32 value, mask;
8f256622 1868 int err;
2e72eb43 1869
0a7fcb78
PB		 1870 esw = priv->mdev->priv.eswitch;
1871 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1872 uplink_priv = &uplink_rpriv->uplink_priv;
1873
1874 memset(&tunnel_key, 0, sizeof(tunnel_key));
1875 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1876 &tunnel_key.enc_control);
1877 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1878 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1879 &tunnel_key.enc_ipv4);
1880 else
1881 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1882 &tunnel_key.enc_ipv6);
1883 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1884 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1885 &tunnel_key.enc_tp);
1886 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1887 &tunnel_key.enc_key_id);
1888 tunnel_key.filter_ifindex = filter_dev->ifindex;
1889
1890 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1891 if (err)
101f4de9 1892 return err;
bbd00f7e 1893
0a7fcb78
PB		 1894 flow_rule_match_enc_opts(rule, &enc_opts_match);
1895 err = enc_opts_is_dont_care_or_full_match(priv,
1896 enc_opts_match.mask,
1897 extack,
1898 &enc_opts_is_dont_care);
1899 if (err)
1900 goto err_enc_opts;
fe1587a7 1901
0a7fcb78
PB		 1902 if (!enc_opts_is_dont_care) {
1903 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
1904 enc_opts_match.key, &enc_opts_id);
1905 if (err)
1906 goto err_enc_opts;
1907 }
fe1587a7 1908
0a7fcb78
PB		 1909 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1910 mask = enc_opts_id ? TUNNEL_ID_MASK :
1911 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1912
0a7fcb78
PB		 1913 if (attr->chain) {
1914 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1915 TUNNEL_TO_REG, value, mask);
1916 } else {
1917 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1918 err = mlx5e_tc_match_to_reg_set(priv->mdev,
1919 mod_hdr_acts,
1920 TUNNEL_TO_REG, value);
1921 if (err)
1922 goto err_set;
fe1587a7 1923
0a7fcb78 1924 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1925 }
bbd00f7e 1926
0a7fcb78
PB		 1927 flow->tunnel_id = value;
1928 return 0;
bcef735c 1929
0a7fcb78
PB		 1930err_set:
1931 if (enc_opts_id)
1932 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1933 enc_opts_id);
1934err_enc_opts:
1935 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1936 return err;
1937}
bcef735c 1938
0a7fcb78
PB		 1939static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1940{
1941 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1942 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1943 struct mlx5_rep_uplink_priv *uplink_priv;
1944 struct mlx5e_rep_priv *uplink_rpriv;
1945 struct mlx5_eswitch *esw;
bcef735c 1946
0a7fcb78
PB		 1947 esw = flow->priv->mdev->priv.eswitch;
1948 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1949 uplink_priv = &uplink_rpriv->uplink_priv;
1950
1951 if (tun_id)
1952 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1953 if (enc_opts_id)
1954 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1955 enc_opts_id);
1956}
e98bedf5 1957
4c3844d9
PB		 1958u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1959{
1960 return flow->tunnel_id;
1961}
1962
bbd00f7e 1963static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1964 struct mlx5e_tc_flow *flow,
bbd00f7e 1965 struct mlx5_flow_spec *spec,
f9e30088 1966 struct flow_cls_offload *f,
0a7fcb78
PB		 1967 struct net_device *filter_dev,
1968 u8 *match_level,
1969 bool *match_inner)
bbd00f7e 1970{
0a7fcb78 1971 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1972 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1973 bool needs_mapping, sets_mapping;
8f256622 1974 int err;
2e72eb43 1975
0a7fcb78
PB		 1976 if (!mlx5e_is_eswitch_flow(flow))
1977 return -EOPNOTSUPP;
1978
1979 needs_mapping = !!flow->esw_attr->chain;
1980 sets_mapping = !flow->esw_attr->chain && flow_has_tc_fwd_action(f);
1981 *match_inner = !needs_mapping;
1982
1983 if ((needs_mapping || sets_mapping) &&
1984 !mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1985 NL_SET_ERR_MSG(extack,
1986 "Chains on tunnel devices isn't supported without register metadata support");
1987 netdev_warn(priv->netdev,
1988 "Chains on tunnel devices isn't supported without register metadata support");
1989 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1990 }
1991
0a7fcb78
PB		 1992 if (!flow->esw_attr->chain) {
1993 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1994 match_level);
1995 if (err) {
e98bedf5 1996 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1997 "Failed to parse tunnel attributes");
1998 netdev_warn(priv->netdev,
1999 "Failed to parse tunnel attributes");
2000 return err;
e98bedf5
EB		 2001 }
2002
0a7fcb78 2003 flow->esw_attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bcef735c
OG		 2004 }
2005
0a7fcb78
PB		 2006 if (!needs_mapping && !sets_mapping)
2007 return 0;
bbd00f7e 2008
0a7fcb78 2009 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2010}
bbd00f7e 2011
0a7fcb78 2012static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2013{
0a7fcb78
PB		 2014 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2015 inner_headers);
bbd00f7e
HHZ		 2016}
2017
0a7fcb78 2018static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2019{
0a7fcb78
PB		 2020 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2021 inner_headers);
2022}
2023
2024static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2025{
2026 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2027 outer_headers);
2028}
2029
2030static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2031{
2032 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2033 outer_headers);
8377629e
EB		 2034}
2035
2036static void *get_match_headers_value(u32 flags,
2037 struct mlx5_flow_spec *spec)
2038{
2039 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2040 get_match_inner_headers_value(spec) :
2041 get_match_outer_headers_value(spec);
2042}
2043
2044static void *get_match_headers_criteria(u32 flags,
2045 struct mlx5_flow_spec *spec)
2046{
2047 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2048 get_match_inner_headers_criteria(spec) :
2049 get_match_outer_headers_criteria(spec);
8377629e
EB		 2050}
2051
6d65bc64 2052static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2053 struct flow_cls_offload *f)
2054{
2055 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2056 struct netlink_ext_ack *extack = f->common.extack;
2057 struct net_device *ingress_dev;
2058 struct flow_match_meta match;
2059
2060 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2061 return 0;
2062
2063 flow_rule_match_meta(rule, &match);
2064 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2065 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2066 return -EINVAL;
2067 }
2068
2069 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2070 match.key->ingress_ifindex);
2071 if (!ingress_dev) {
2072 NL_SET_ERR_MSG_MOD(extack,
2073 "Can't find the ingress port to match on");
2074 return -EINVAL;
2075 }
2076
2077 if (ingress_dev != filter_dev) {
2078 NL_SET_ERR_MSG_MOD(extack,
2079 "Can't match on the ingress filter port");
2080 return -EINVAL;
2081 }
2082
2083 return 0;
2084}
2085
de0af0bf 2086static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2087 struct mlx5e_tc_flow *flow,
de0af0bf 2088 struct mlx5_flow_spec *spec,
f9e30088 2089 struct flow_cls_offload *f,
54c177ca 2090 struct net_device *filter_dev,
93b3586e 2091 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2092{
e98bedf5 2093 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2094 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2095 outer_headers);
2096 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2097 outer_headers);
699e96dd
JL		 2098 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2099 misc_parameters);
2100 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2101 misc_parameters);
f9e30088 2102 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2103 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2104 u16 addr_type = 0;
2105 u8 ip_proto = 0;
93b3586e 2106 u8 *match_level;
6d65bc64 2107 int err;
e3a2b7ed 2108
93b3586e 2109 match_level = outer_match_level;
de0af0bf 2110
8f256622 2111 if (dissector->used_keys &
3d144578
VB		 2112 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2113 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2114 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2115 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2116 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2117 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2118 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2119 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2120 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2121 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2122 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2123 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2124 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2125 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2126 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2127 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2128 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df
YK		 2129 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
2130 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 2131 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 2132 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 2133 dissector->used_keys);
e3a2b7ed
AV		 2134 return -EOPNOTSUPP;
2135 }
2136
075973c7 2137 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2138 bool match_inner = false;
bbd00f7e 2139
0a7fcb78
PB		 2140 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2141 outer_match_level, &match_inner);
2142 if (err)
2143 return err;
2144
2145 if (match_inner) {
2146 /* header pointers should point to the inner headers
2147 * if the packet was decapsulated already.
2148 * outer headers are set by parse_tunnel_attr.
2149 */
2150 match_level = inner_match_level;
2151 headers_c = get_match_inner_headers_criteria(spec);
2152 headers_v = get_match_inner_headers_value(spec);
2153 }
bbd00f7e
HHZ		 2154 }
2155
6d65bc64 2156 err = mlx5e_flower_parse_meta(filter_dev, f);
2157 if (err)
2158 return err;
2159
8f256622
PNA		 2160 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2161 struct flow_match_basic match;
2162
2163 flow_rule_match_basic(rule, &match);
d3a80bb5 2164 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 2165 ntohs(match.mask->n_proto));
d3a80bb5 2166 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 2167 ntohs(match.key->n_proto));
e3a2b7ed 2168
8f256622 2169 if (match.mask->n_proto)
d708f902 2170 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2171 }
35a605db
EB		 2172 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2173 is_vlan_dev(filter_dev)) {
2174 struct flow_dissector_key_vlan filter_dev_mask;
2175 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2176 struct flow_match_vlan match;
2177
35a605db
EB		 2178 if (is_vlan_dev(filter_dev)) {
2179 match.key = &filter_dev_key;
2180 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2181 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2182 match.key->vlan_priority = 0;
2183 match.mask = &filter_dev_mask;
2184 memset(match.mask, 0xff, sizeof(*match.mask));
2185 match.mask->vlan_priority = 0;
2186 } else {
2187 flow_rule_match_vlan(rule, &match);
2188 }
8f256622
PNA		 2189 if (match.mask->vlan_id ||
2190 match.mask->vlan_priority ||
2191 match.mask->vlan_tpid) {
2192 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2193 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2194 svlan_tag, 1);
2195 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2196 svlan_tag, 1);
2197 } else {
2198 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2199 cvlan_tag, 1);
2200 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2201 cvlan_tag, 1);
2202 }
095b6cfd 2203
8f256622
PNA		 2204 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2205 match.mask->vlan_id);
2206 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2207 match.key->vlan_id);
358d79a4 2208
8f256622
PNA		 2209 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2210 match.mask->vlan_priority);
2211 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2212 match.key->vlan_priority);
54782900 2213
d708f902 2214 *match_level = MLX5_MATCH_L2;
54782900 2215 }
d3a80bb5 2216 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2217 /* cvlan_tag enabled in match criteria and
2218 * disabled in match value means both S & C tags
2219 * don't exist (untagged of both)
2220 */
cee26487 2221 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2222 *match_level = MLX5_MATCH_L2;
54782900
OG		 2223 }
2224
8f256622
PNA		 2225 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2226 struct flow_match_vlan match;
2227
12d5cbf8 2228 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2229 if (match.mask->vlan_id ||
2230 match.mask->vlan_priority ||
2231 match.mask->vlan_tpid) {
2232 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2233 MLX5_SET(fte_match_set_misc, misc_c,
2234 outer_second_svlan_tag, 1);
2235 MLX5_SET(fte_match_set_misc, misc_v,
2236 outer_second_svlan_tag, 1);
2237 } else {
2238 MLX5_SET(fte_match_set_misc, misc_c,
2239 outer_second_cvlan_tag, 1);
2240 MLX5_SET(fte_match_set_misc, misc_v,
2241 outer_second_cvlan_tag, 1);
2242 }
2243
2244 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2245 match.mask->vlan_id);
699e96dd 2246 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2247 match.key->vlan_id);
699e96dd 2248 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2249 match.mask->vlan_priority);
699e96dd 2250 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2251 match.key->vlan_priority);
699e96dd
JL		 2252
2253 *match_level = MLX5_MATCH_L2;
2254 }
2255 }
2256
8f256622
PNA		 2257 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2258 struct flow_match_eth_addrs match;
54782900 2259
8f256622 2260 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2261 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2262 dmac_47_16),
8f256622 2263 match.mask->dst);
d3a80bb5
OG		 2264 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2265 dmac_47_16),
8f256622 2266 match.key->dst);
d3a80bb5
OG		 2267
2268 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2269 smac_47_16),
8f256622 2270 match.mask->src);
d3a80bb5
OG		 2271 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2272 smac_47_16),
8f256622 2273 match.key->src);
d3a80bb5 2274
8f256622
PNA		 2275 if (!is_zero_ether_addr(match.mask->src) ||
2276 !is_zero_ether_addr(match.mask->dst))
d708f902 2277 *match_level = MLX5_MATCH_L2;
54782900
OG		 2278 }
2279
8f256622
PNA		 2280 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2281 struct flow_match_control match;
54782900 2282
8f256622
PNA		 2283 flow_rule_match_control(rule, &match);
2284 addr_type = match.key->addr_type;
54782900
OG		 2285
2286 /* the HW doesn't support frag first/later */
8f256622 2287 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2288 return -EOPNOTSUPP;
2289
8f256622 2290 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2291 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2292 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2293 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2294
2295 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2296 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2297 *match_level = MLX5_MATCH_L2;
54782900
OG		 2298 /* *** L2 attributes parsing up to here *** */
2299 else
83621b7d 2300 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2301 }
2302 }
2303
8f256622
PNA		 2304 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2305 struct flow_match_basic match;
2306
2307 flow_rule_match_basic(rule, &match);
2308 ip_proto = match.key->ip_proto;
54782900
OG		 2309
2310 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2311 match.mask->ip_proto);
54782900 2312 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2313 match.key->ip_proto);
54782900 2314
8f256622 2315 if (match.mask->ip_proto)
d708f902 2316 *match_level = MLX5_MATCH_L3;
54782900
OG		 2317 }
2318
e3a2b7ed 2319 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2320 struct flow_match_ipv4_addrs match;
e3a2b7ed 2321
8f256622 2322 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2323 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2324 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2325 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2326 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2327 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2328 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2329 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2330 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2331 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2332 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2333 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2334 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2335
8f256622 2336 if (match.mask->src || match.mask->dst)
d708f902 2337 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2338 }
2339
2340 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2341 struct flow_match_ipv6_addrs match;
e3a2b7ed 2342
8f256622 2343 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2344 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2345 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2346 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2347 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2348 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2349 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2350
2351 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2352 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2353 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2354 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2355 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2356 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2357
8f256622
PNA		 2358 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2359 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2360 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2361 }
2362
8f256622
PNA		 2363 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2364 struct flow_match_ip match;
1f97a526 2365
8f256622
PNA		 2366 flow_rule_match_ip(rule, &match);
2367 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2368 match.mask->tos & 0x3);
2369 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2370 match.key->tos & 0x3);
1f97a526 2371
8f256622
PNA		 2372 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2373 match.mask->tos >> 2);
2374 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2375 match.key->tos >> 2);
1f97a526 2376
8f256622
PNA		 2377 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2378 match.mask->ttl);
2379 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2380 match.key->ttl);
1f97a526 2381
8f256622 2382 if (match.mask->ttl &&
a8ade55f 2383 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2384 ft_field_support.outer_ipv4_ttl)) {
2385 NL_SET_ERR_MSG_MOD(extack,
2386 "Matching on TTL is not supported");
1f97a526 2387 return -EOPNOTSUPP;
e98bedf5 2388 }
a8ade55f 2389
8f256622 2390 if (match.mask->tos || match.mask->ttl)
d708f902 2391 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2392 }
2393
54782900
OG		 2394 /* *** L3 attributes parsing up to here *** */
2395
8f256622
PNA		 2396 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2397 struct flow_match_ports match;
2398
2399 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2400 switch (ip_proto) {
2401 case IPPROTO_TCP:
2402 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2403 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2404 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2405 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2406
2407 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2408 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2409 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2410 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2411 break;
2412
2413 case IPPROTO_UDP:
2414 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2415 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2416 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2417 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2418
2419 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2420 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2421 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2422 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2423 break;
2424 default:
e98bedf5
EB		 2425 NL_SET_ERR_MSG_MOD(extack,
2426 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2427 netdev_err(priv->netdev,
2428 "Only UDP and TCP transport are supported\n");
2429 return -EINVAL;
2430 }
de0af0bf 2431
8f256622 2432 if (match.mask->src || match.mask->dst)
d708f902 2433 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2434 }
2435
8f256622
PNA		 2436 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2437 struct flow_match_tcp match;
e77834ec 2438
8f256622 2439 flow_rule_match_tcp(rule, &match);
e77834ec 2440 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2441 ntohs(match.mask->flags));
e77834ec 2442 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2443 ntohs(match.key->flags));
e77834ec 2444
8f256622 2445 if (match.mask->flags)
d708f902 2446 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2447 }
2448
e3a2b7ed
AV		 2449 return 0;
2450}
2451
de0af0bf 2452static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2453 struct mlx5e_tc_flow *flow,
de0af0bf 2454 struct mlx5_flow_spec *spec,
f9e30088 2455 struct flow_cls_offload *f,
54c177ca 2456 struct net_device *filter_dev)
de0af0bf 2457{
93b3586e 2458 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2459 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2460 struct mlx5_core_dev *dev = priv->mdev;
2461 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2462 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2463 struct mlx5_eswitch_rep *rep;
226f2ca3 2464 bool is_eswitch_flow;
de0af0bf
RD		 2465 int err;
2466
93b3586e
HN		 2467 inner_match_level = MLX5_MATCH_NONE;
2468 outer_match_level = MLX5_MATCH_NONE;
2469
0a7fcb78
PB		 2470 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2471 &inner_match_level, &outer_match_level);
93b3586e
HN		 2472 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2473 outer_match_level : inner_match_level;
de0af0bf 2474
226f2ca3
VB		 2475 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2476 if (!err && is_eswitch_flow) {
1d447a39 2477 rep = rpriv->rep;
b05af6aa 2478 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2479 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2480 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2481 NL_SET_ERR_MSG_MOD(extack,
2482 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2483 netdev_warn(priv->netdev,
2484 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2485 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2486 return -EOPNOTSUPP;
2487 }
2488 }
2489
226f2ca3 2490 if (is_eswitch_flow) {
93b3586e
HN		 2491 flow->esw_attr->inner_match_level = inner_match_level;
2492 flow->esw_attr->outer_match_level = outer_match_level;
6363651d 2493 } else {
93b3586e 2494 flow->nic_attr->match_level = non_tunnel_match_level;
6363651d 2495 }
38aa51c1 2496
de0af0bf
RD		 2497 return err;
2498}
2499
d79b6df6
OG		 2500struct pedit_headers {
2501 struct ethhdr eth;
0eb69bb9 2502 struct vlan_hdr vlan;
d79b6df6
OG		 2503 struct iphdr ip4;
2504 struct ipv6hdr ip6;
2505 struct tcphdr tcp;
2506 struct udphdr udp;
2507};
2508
c500c86b
PNA		 2509struct pedit_headers_action {
2510 struct pedit_headers vals;
2511 struct pedit_headers masks;
2512 u32 pedits;
2513};
2514
d79b6df6 2515static int pedit_header_offsets[] = {
73867881
PNA		 2516 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2517 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2518 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2519 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2520 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2521};
2522
2523#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2524
2525static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2526 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2527{
2528 u32 *curr_pmask, *curr_pval;
2529
c500c86b
PNA		 2530 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2531 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2532
2533 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2534 goto out_err;
2535
2536 *curr_pmask |= mask;
2537 *curr_pval |= (val & mask);
2538
2539 return 0;
2540
2541out_err:
2542 return -EOPNOTSUPP;
2543}
2544
2545struct mlx5_fields {
2546 u8 field;
88f30bbc
DL		 2547 u8 field_bsize;
2548 u32 field_mask;
d79b6df6 2549 u32 offset;
27c11b6b 2550 u32 match_offset;
d79b6df6
OG		 2551};
2552
88f30bbc
DL		 2553#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2554 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2555 offsetof(struct pedit_headers, field) + (off), \
2556 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2557
2ef86872
EB		 2558/* masked values are the same and there are no rewrites that do not have a
2559 * match.
2560 */
2561#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2562 type matchmaskx = *(type *)(matchmaskp); \
2563 type matchvalx = *(type *)(matchvalp); \
2564 type maskx = *(type *)(maskp); \
2565 type valx = *(type *)(valp); \
2566 \
2567 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2568 matchmaskx)); \
2569})
2570
27c11b6b 2571static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2572 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2573{
2574 bool same = false;
2575
88f30bbc
DL		 2576 switch (bsize) {
2577 case 8:
2ef86872 2578 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2579 break;
88f30bbc 2580 case 16:
2ef86872 2581 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2582 break;
88f30bbc 2583 case 32:
2ef86872 2584 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2585 break;
2586 }
2587
2588 return same;
2589}
a8e4f0c4 2590
d79b6df6 2591static struct mlx5_fields fields[] = {
88f30bbc
DL		 2592 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2593 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2594 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2595 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2596 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2597 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2598
ab9341b5 2599 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2600 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2601 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2602 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2603
2604 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2605 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2606 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2607 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2608 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2609 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2610 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2611 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2612 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2613 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2614 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2615 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2616 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2617 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2618 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2619 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2620 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
27c11b6b 2621
88f30bbc
DL		 2622 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2623 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2624 /* in linux iphdr tcp_flags is 8 bits long */
2625 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2626
88f30bbc
DL		 2627 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2628 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2629};
2630
6ae4a6a5
PB		 2631static int offload_pedit_fields(struct mlx5e_priv *priv,
2632 int namespace,
2633 struct pedit_headers_action *hdrs,
e98bedf5 2634 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2635 u32 *action_flags,
e98bedf5 2636 struct netlink_ext_ack *extack)
d79b6df6
OG		 2637{
2638 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2639 int i, action_size, first, last, next_z;
88f30bbc
DL		 2640 void *headers_c, *headers_v, *action, *vals_p;
2641 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2642 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2643 struct mlx5_fields *f;
d79b6df6 2644 unsigned long mask;
2b64beba
OG		 2645 __be32 mask_be32;
2646 __be16 mask_be16;
6ae4a6a5 2647 int err;
88f30bbc
DL		 2648 u8 cmd;
2649
6ae4a6a5 2650 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2651 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2652 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2653
73867881
PNA		 2654 set_masks = &hdrs[0].masks;
2655 add_masks = &hdrs[1].masks;
2656 set_vals = &hdrs[0].vals;
2657 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2658
2659 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
d79b6df6
OG		 2660
2661 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2662 bool skip;
2663
d79b6df6
OG		 2664 f = &fields[i];
2665 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2666 s_mask = 0;
2667 a_mask = 0;
d79b6df6
OG		 2668
2669 s_masks_p = (void *)set_masks + f->offset;
2670 a_masks_p = (void *)add_masks + f->offset;
2671
88f30bbc
DL		 2672 s_mask = *s_masks_p & f->field_mask;
2673 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2674
2675 if (!s_mask && !a_mask) /* nothing to offload here */
2676 continue;
2677
2678 if (s_mask && a_mask) {
e98bedf5
EB		 2679 NL_SET_ERR_MSG_MOD(extack,
2680 "can't set and add to the same HW field");
d79b6df6
OG		 2681 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2682 return -EOPNOTSUPP;
2683 }
2684
27c11b6b 2685 skip = false;
d79b6df6 2686 if (s_mask) {
27c11b6b
EB		 2687 void *match_mask = headers_c + f->match_offset;
2688 void *match_val = headers_v + f->match_offset;
2689
d79b6df6
OG		 2690 cmd = MLX5_ACTION_TYPE_SET;
2691 mask = s_mask;
2692 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2693 /* don't rewrite if we have a match on the same value */
2694 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2695 match_mask, f->field_bsize))
27c11b6b 2696 skip = true;
d79b6df6 2697 /* clear to denote we consumed this field */
88f30bbc 2698 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2699 } else {
2700 cmd = MLX5_ACTION_TYPE_ADD;
2701 mask = a_mask;
2702 vals_p = (void *)add_vals + f->offset;
27c11b6b 2703 /* add 0 is no change */
88f30bbc 2704 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2705 skip = true;
d79b6df6 2706 /* clear to denote we consumed this field */
88f30bbc 2707 *a_masks_p &= ~f->field_mask;
d79b6df6 2708 }
27c11b6b
EB		 2709 if (skip)
2710 continue;
d79b6df6 2711
88f30bbc 2712 if (f->field_bsize == 32) {
2b64beba
OG		 2713 mask_be32 = *(__be32 *)&mask;
2714 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
88f30bbc 2715 } else if (f->field_bsize == 16) {
2b64beba
OG		 2716 mask_be16 = *(__be16 *)&mask;
2717 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2718 }
2719
88f30bbc
DL		 2720 first = find_first_bit(&mask, f->field_bsize);
2721 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2722 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2723 if (first < next_z && next_z < last) {
e98bedf5
EB		 2724 NL_SET_ERR_MSG_MOD(extack,
2725 "rewrite of few sub-fields isn't supported");
2b64beba 2726 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2727 mask);
2728 return -EOPNOTSUPP;
2729 }
2730
6ae4a6a5
PB		 2731 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2732 if (err) {
2733 NL_SET_ERR_MSG_MOD(extack,
2734 "too many pedit actions, can't offload");
2735 mlx5_core_warn(priv->mdev,
2736 "mlx5: parsed %d pedit actions, can't do more\n",
2737 mod_acts->num_actions);
2738 return err;
2739 }
2740
2741 action = mod_acts->actions +
2742 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2743 MLX5_SET(set_action_in, action, action_type, cmd);
2744 MLX5_SET(set_action_in, action, field, f->field);
2745
2746 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2747 int start;
2748
2749 /* if field is bit sized it can start not from first bit */
2750 start = find_first_bit((unsigned long *)&f->field_mask,
2751 f->field_bsize);
2752
2753 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2754 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2755 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2756 }
2757
88f30bbc 2758 if (f->field_bsize == 32)
2b64beba 2759 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2760 else if (f->field_bsize == 16)
2b64beba 2761 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2762 else if (f->field_bsize == 8)
2b64beba 2763 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2764
6ae4a6a5 2765 ++mod_acts->num_actions;
d79b6df6
OG		 2766 }
2767
d79b6df6
OG		 2768 return 0;
2769}
2770
2cc1cb1d
TZ		 2771static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2772 int namespace)
2773{
2774 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2775 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2776 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2777 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2778}
2779
6ae4a6a5
PB		 2780int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2781 int namespace,
2782 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2783{
6ae4a6a5
PB		 2784 int action_size, new_num_actions, max_hw_actions;
2785 size_t new_sz, old_sz;
2786 void *ret;
d79b6df6 2787
6ae4a6a5
PB		 2788 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2789 return 0;
d79b6df6 2790
6ae4a6a5 2791 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
d79b6df6 2792
6ae4a6a5
PB		 2793 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2794 namespace);
2795 new_num_actions = min(max_hw_actions,
2796 mod_hdr_acts->actions ?
2797 mod_hdr_acts->max_actions * 2 : 1);
2798 if (mod_hdr_acts->max_actions == new_num_actions)
2799 return -ENOSPC;
2800
2801 new_sz = action_size * new_num_actions;
2802 old_sz = mod_hdr_acts->max_actions * action_size;
2803 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2804 if (!ret)
d79b6df6
OG		 2805 return -ENOMEM;
2806
6ae4a6a5
PB		 2807 memset(ret + old_sz, 0, new_sz - old_sz);
2808 mod_hdr_acts->actions = ret;
2809 mod_hdr_acts->max_actions = new_num_actions;
2810
d79b6df6
OG		 2811 return 0;
2812}
2813
6ae4a6a5
PB		 2814void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2815{
2816 kfree(mod_hdr_acts->actions);
2817 mod_hdr_acts->actions = NULL;
2818 mod_hdr_acts->num_actions = 0;
2819 mod_hdr_acts->max_actions = 0;
2820}
2821
d79b6df6
OG		 2822static const struct pedit_headers zero_masks = {};
2823
2824static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2825 const struct flow_action_entry *act, int namespace,
c500c86b 2826 struct pedit_headers_action *hdrs,
e98bedf5 2827 struct netlink_ext_ack *extack)
d79b6df6 2828{
73867881
PNA		 2829 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2830 int err = -EOPNOTSUPP;
d79b6df6 2831 u32 mask, val, offset;
73867881 2832 u8 htype;
d79b6df6 2833
73867881
PNA		 2834 htype = act->mangle.htype;
2835 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2836
73867881
PNA		 2837 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2838 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2839 goto out_err;
2840 }
d79b6df6 2841
2cc1cb1d
TZ		 2842 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2843 NL_SET_ERR_MSG_MOD(extack,
2844 "The pedit offload action is not supported");
2845 goto out_err;
2846 }
2847
73867881
PNA		 2848 mask = act->mangle.mask;
2849 val = act->mangle.val;
2850 offset = act->mangle.offset;
d79b6df6 2851
73867881
PNA		 2852 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2853 if (err)
2854 goto out_err;
c500c86b 2855
73867881 2856 hdrs[cmd].pedits++;
d79b6df6 2857
c500c86b
PNA		 2858 return 0;
2859out_err:
2860 return err;
2861}
2862
2863static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2864 struct mlx5e_tc_flow_parse_attr *parse_attr,
2865 struct pedit_headers_action *hdrs,
27c11b6b 2866 u32 *action_flags,
c500c86b
PNA		 2867 struct netlink_ext_ack *extack)
2868{
2869 struct pedit_headers *cmd_masks;
2870 int err;
2871 u8 cmd;
2872
6ae4a6a5
PB		 2873 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2874 action_flags, extack);
d79b6df6
OG		 2875 if (err < 0)
2876 goto out_dealloc_parsed_actions;
2877
2878 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2879 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2880 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2881 NL_SET_ERR_MSG_MOD(extack,
2882 "attempt to offload an unsupported field");
b3a433de 2883 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2884 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2885 16, 1, cmd_masks, sizeof(zero_masks), true);
2886 err = -EOPNOTSUPP;
2887 goto out_dealloc_parsed_actions;
2888 }
2889 }
2890
2891 return 0;
2892
2893out_dealloc_parsed_actions:
6ae4a6a5 2894 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2895 return err;
2896}
2897
e98bedf5
EB		 2898static bool csum_offload_supported(struct mlx5e_priv *priv,
2899 u32 action,
2900 u32 update_flags,
2901 struct netlink_ext_ack *extack)
26c02749
OG		 2902{
2903 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2904 TCA_CSUM_UPDATE_FLAG_UDP;
2905
2906 /* The HW recalcs checksums only if re-writing headers */
2907 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2908 NL_SET_ERR_MSG_MOD(extack,
2909 "TC csum action is only offloaded with pedit");
26c02749
OG		 2910 netdev_warn(priv->netdev,
2911 "TC csum action is only offloaded with pedit\n");
2912 return false;
2913 }
2914
2915 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2916 NL_SET_ERR_MSG_MOD(extack,
2917 "can't offload TC csum action for some header/s");
26c02749
OG		 2918 netdev_warn(priv->netdev,
2919 "can't offload TC csum action for some header/s - flags %#x\n",
2920 update_flags);
2921 return false;
2922 }
2923
2924 return true;
2925}
2926
8998576b
DL		 2927struct ip_ttl_word {
2928 __u8 ttl;
2929 __u8 protocol;
2930 __sum16 check;
2931};
2932
2933struct ipv6_hoplimit_word {
2934 __be16 payload_len;
2935 __u8 nexthdr;
2936 __u8 hop_limit;
2937};
2938
4c3844d9
PB		 2939static int is_action_keys_supported(const struct flow_action_entry *act,
2940 bool ct_flow, bool *modify_ip_header,
2941 struct netlink_ext_ack *extack)
8998576b
DL		 2942{
2943 u32 mask, offset;
2944 u8 htype;
2945
2946 htype = act->mangle.htype;
2947 offset = act->mangle.offset;
2948 mask = ~act->mangle.mask;
2949 /* For IPv4 & IPv6 header check 4 byte word,
2950 * to determine that modified fields
2951 * are NOT ttl & hop_limit only.
2952 */
2953 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2954 struct ip_ttl_word *ttl_word =
2955 (struct ip_ttl_word *)&mask;
2956
2957 if (offset != offsetof(struct iphdr, ttl) ||
2958 ttl_word->protocol ||
2959 ttl_word->check) {
4c3844d9
PB		 2960 *modify_ip_header = true;
2961 }
2962
2963 if (ct_flow && offset >= offsetof(struct iphdr, saddr)) {
2964 NL_SET_ERR_MSG_MOD(extack,
2965 "can't offload re-write of ipv4 address with action ct");
2966 return -EOPNOTSUPP;
8998576b
DL		 2967 }
2968 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2969 struct ipv6_hoplimit_word *hoplimit_word =
2970 (struct ipv6_hoplimit_word *)&mask;
2971
2972 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2973 hoplimit_word->payload_len ||
2974 hoplimit_word->nexthdr) {
4c3844d9
PB		 2975 *modify_ip_header = true;
2976 }
2977
2978 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr)) {
2979 NL_SET_ERR_MSG_MOD(extack,
2980 "can't offload re-write of ipv6 address with action ct");
2981 return -EOPNOTSUPP;
8998576b 2982 }
4c3844d9
PB		 2983 } else if (ct_flow && (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
2984 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP)) {
2985 NL_SET_ERR_MSG_MOD(extack,
2986 "can't offload re-write of transport header ports with action ct");
2987 return -EOPNOTSUPP;
8998576b 2988 }
4c3844d9
PB		 2989
2990 return 0;
8998576b
DL		 2991}
2992
bdd66ac0 2993static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2994 struct flow_action *flow_action,
4c3844d9 2995 u32 actions, bool ct_flow,
e98bedf5 2996 struct netlink_ext_ack *extack)
bdd66ac0 2997{
73867881 2998 const struct flow_action_entry *act;
bdd66ac0 2999 bool modify_ip_header;
bdd66ac0
OG		 3000 void *headers_v;
3001 u16 ethertype;
8998576b 3002 u8 ip_proto;
4c3844d9 3003 int i, err;
bdd66ac0 3004
8377629e 3005 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3006 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3007
3008 /* for non-IP we only re-write MACs, so we're okay */
3009 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3010 goto out_ok;
3011
3012 modify_ip_header = false;
73867881
PNA		 3013 flow_action_for_each(i, act, flow_action) {
3014 if (act->id != FLOW_ACTION_MANGLE &&
3015 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3016 continue;
3017
4c3844d9
PB		 3018 err = is_action_keys_supported(act, ct_flow,
3019 &modify_ip_header, extack);
3020 if (err)
3021 return err;
bdd66ac0
OG		 3022 }
3023
3024 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3025 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3026 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3027 NL_SET_ERR_MSG_MOD(extack,
3028 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 3029 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
3030 return false;
3031 }
3032
3033out_ok:
3034 return true;
3035}
3036
3037static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3038 struct flow_action *flow_action,
bdd66ac0 3039 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3040 struct mlx5e_tc_flow *flow,
3041 struct netlink_ext_ack *extack)
bdd66ac0 3042{
7f2fd0a5 3043 struct net_device *filter_dev = parse_attr->filter_dev;
4c3844d9 3044 bool drop_action, pop_action, ct_flow;
bdd66ac0
OG		 3045 u32 actions;
3046
4c3844d9
PB		 3047 ct_flow = flow_flag_test(flow, CT);
3048 if (mlx5e_is_eswitch_flow(flow)) {
bdd66ac0 3049 actions = flow->esw_attr->action;
4c3844d9
PB		 3050
3051 if (flow->esw_attr->split_count && ct_flow) {
3052 /* All registers used by ct are cleared when using
3053 * split rules.
3054 */
3055 NL_SET_ERR_MSG_MOD(extack,
3056 "Can't offload mirroring with action ct");
3057 return -EOPNOTSUPP;
3058 }
3059 } else {
bdd66ac0 3060 actions = flow->nic_attr->action;
4c3844d9 3061 }
bdd66ac0 3062
7f2fd0a5 3063 drop_action = actions & MLX5_FLOW_CONTEXT_ACTION_DROP;
7f2fd0a5
PB		 3064 pop_action = actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3065
3066 if (flow_flag_test(flow, EGRESS) && !drop_action) {
0a7fcb78
PB		 3067 /* We only support filters on tunnel device, or on vlan
3068 * devices if they have pop/drop action
3069 */
3070 if (!mlx5e_get_tc_tun(filter_dev) ||
3071 (is_vlan_dev(filter_dev) && !pop_action))
7f2fd0a5 3072 return false;
7f2fd0a5 3073 }
7e29392e 3074
bdd66ac0 3075 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 3076 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 3077 flow_action, actions,
4c3844d9 3078 ct_flow, extack);
bdd66ac0
OG		 3079
3080 return true;
3081}
3082
5c65c564
OG		 3083static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3084{
3085 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3086 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3087
3088 fmdev = priv->mdev;
3089 pmdev = peer_priv->mdev;
3090
59c9d35e
AH		 3091 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3092 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3093
816f6706 3094 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3095}
3096
bdc837ee
EB		 3097static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3098 const struct flow_action_entry *act,
3099 struct mlx5e_tc_flow_parse_attr *parse_attr,
3100 struct pedit_headers_action *hdrs,
3101 u32 *action, struct netlink_ext_ack *extack)
3102{
3103 u16 mask16 = VLAN_VID_MASK;
3104 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3105 const struct flow_action_entry pedit_act = {
3106 .id = FLOW_ACTION_MANGLE,
3107 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3108 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3109 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3110 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3111 };
6fca9d1e 3112 u8 match_prio_mask, match_prio_val;
bf2f3bca 3113 void *headers_c, *headers_v;
bdc837ee
EB		 3114 int err;
3115
bf2f3bca
EB		 3116 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3117 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3118
3119 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3120 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3121 NL_SET_ERR_MSG_MOD(extack,
3122 "VLAN rewrite action must have VLAN protocol match");
3123 return -EOPNOTSUPP;
3124 }
3125
6fca9d1e
EB		 3126 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3127 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3128 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3129 NL_SET_ERR_MSG_MOD(extack,
3130 "Changing VLAN prio is not supported");
bdc837ee
EB		 3131 return -EOPNOTSUPP;
3132 }
3133
dec481c8 3134 err = parse_tc_pedit_action(priv, &pedit_act, namespace, hdrs, NULL);
bdc837ee
EB		 3135 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3136
3137 return err;
3138}
3139
0bac1194
EB		 3140static int
3141add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3142 struct mlx5e_tc_flow_parse_attr *parse_attr,
3143 struct pedit_headers_action *hdrs,
3144 u32 *action, struct netlink_ext_ack *extack)
3145{
3146 const struct flow_action_entry prio_tag_act = {
3147 .vlan.vid = 0,
3148 .vlan.prio =
3149 MLX5_GET(fte_match_set_lyr_2_4,
3150 get_match_headers_value(*action,
3151 &parse_attr->spec),
3152 first_prio) &
3153 MLX5_GET(fte_match_set_lyr_2_4,
3154 get_match_headers_criteria(*action,
3155 &parse_attr->spec),
3156 first_prio),
3157 };
3158
3159 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3160 &prio_tag_act, parse_attr, hdrs, action,
3161 extack);
3162}
3163
73867881
PNA		 3164static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3165 struct flow_action *flow_action,
aa0cbbae 3166 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3167 struct mlx5e_tc_flow *flow,
3168 struct netlink_ext_ack *extack)
e3a2b7ed 3169{
aa0cbbae 3170 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 3171 struct pedit_headers_action hdrs[2] = {};
3172 const struct flow_action_entry *act;
1cab1cd7 3173 u32 action = 0;
244cd96a 3174 int err, i;
e3a2b7ed 3175
73867881 3176 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3177 return -EINVAL;
3178
48855479 3179 if (!flow_action_hw_stats_types_check(flow_action, extack,
a16fa289 3180 FLOW_ACTION_HW_STATS_TYPE_DELAYED_BIT))
319a1d19
JP		 3181 return -EOPNOTSUPP;
3182
3bc4b7bf 3183 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3184
73867881
PNA		 3185 flow_action_for_each(i, act, flow_action) {
3186 switch (act->id) {
15fc92ec
TZ		 3187 case FLOW_ACTION_ACCEPT:
3188 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3189 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3190 break;
73867881 3191 case FLOW_ACTION_DROP:
1cab1cd7 3192 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3193 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3194 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3195 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3196 break;
3197 case FLOW_ACTION_MANGLE:
3198 case FLOW_ACTION_ADD:
3199 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
dec481c8 3200 hdrs, extack);
2f4fe4ca
OG		 3201 if (err)
3202 return err;
3203
1cab1cd7
OG		 3204 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
3205 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 3206 break;
bdc837ee
EB		 3207 case FLOW_ACTION_VLAN_MANGLE:
3208 err = add_vlan_rewrite_action(priv,
3209 MLX5_FLOW_NAMESPACE_KERNEL,
3210 act, parse_attr, hdrs,
3211 &action, extack);
3212 if (err)
3213 return err;
3214
3215 break;
73867881 3216 case FLOW_ACTION_CSUM:
1cab1cd7 3217 if (csum_offload_supported(priv, action,
73867881 3218 act->csum_flags,
e98bedf5 3219 extack))
73867881 3220 break;
26c02749
OG		 3221
3222 return -EOPNOTSUPP;
73867881
PNA		 3223 case FLOW_ACTION_REDIRECT: {
3224 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3225
3226 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3227 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3228 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3229 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3230 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3231 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3232 } else {
e98bedf5
EB		 3233 NL_SET_ERR_MSG_MOD(extack,
3234 "device is not on same HW, can't offload");
5c65c564
OG		 3235 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3236 peer_dev->name);
3237 return -EINVAL;
3238 }
73867881
PNA		 3239 }
3240 break;
3241 case FLOW_ACTION_MARK: {
3242 u32 mark = act->mark;
e3a2b7ed
AV		 3243
3244 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3245 NL_SET_ERR_MSG_MOD(extack,
3246 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3247 return -EINVAL;
3248 }
3249
3bc4b7bf 3250 attr->flow_tag = mark;
1cab1cd7 3251 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3252 }
3253 break;
3254 default:
2cc1cb1d
TZ		 3255 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3256 return -EOPNOTSUPP;
e3a2b7ed 3257 }
e3a2b7ed
AV		 3258 }
3259
c500c86b
PNA		 3260 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3261 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3262 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3263 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3264 if (err)
3265 return err;
27c11b6b
EB		 3266 /* in case all pedit actions are skipped, remove the MOD_HDR
3267 * flag.
3268 */
6ae4a6a5 3269 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3270 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3271 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3272 }
c500c86b
PNA		 3273 }
3274
1cab1cd7 3275 attr->action = action;
73867881 3276 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3277 return -EOPNOTSUPP;
3278
e3a2b7ed
AV		 3279 return 0;
3280}
3281
7f1a546e 3282struct encap_key {
1f6da306 3283 const struct ip_tunnel_key *ip_tun_key;
d386939a 3284 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 3285};
3286
3287static inline int cmp_encap_info(struct encap_key *a,
3288 struct encap_key *b)
a54e20b4 3289{
7f1a546e 3290 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 3291 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 3292}
3293
7f1a546e 3294static inline int hash_encap_info(struct encap_key *key)
a54e20b4 3295{
7f1a546e 3296 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 3297 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3298}
3299
a54e20b4 3300
b1d90e6b
RL		 3301static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
3302 struct net_device *peer_netdev)
3303{
3304 struct mlx5e_priv *peer_priv;
3305
3306 peer_priv = netdev_priv(peer_netdev);
3307
3308 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 3309 mlx5e_eswitch_rep(priv->netdev) &&
3310 mlx5e_eswitch_rep(peer_netdev) &&
3311 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3312}
3313
32f3671f 3314
f5bc2c5d 3315
948993f2
VB		 3316bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3317{
3318 return refcount_inc_not_zero(&e->refcnt);
3319}
3320
3321static struct mlx5e_encap_entry *
3322mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3323 uintptr_t hash_key)
3324{
3325 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3326 struct mlx5e_encap_entry *e;
3327 struct encap_key e_key;
3328
3329 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3330 encap_hlist, hash_key) {
3331 e_key.ip_tun_key = &e->tun_info->key;
3332 e_key.tc_tunnel = e->tunnel;
3333 if (!cmp_encap_info(&e_key, key) &&
3334 mlx5e_encap_take(e))
3335 return e;
3336 }
3337
3338 return NULL;
3339}
3340
2a4b6526
VB		 3341static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3342{
3343 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3344
3345 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3346}
3347
554fe75c
DL		 3348static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3349 struct mlx5e_tc_flow *flow,
3350 int out_index,
3351 struct mlx5e_encap_entry *e,
3352 struct netlink_ext_ack *extack)
3353{
3354 int i;
3355
3356 for (i = 0; i < out_index; i++) {
3357 if (flow->encaps[i].e != e)
3358 continue;
3359 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3360 netdev_err(priv->netdev, "can't duplicate encap action\n");
3361 return true;
3362 }
3363
3364 return false;
3365}
3366
a54e20b4 3367static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3368 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3369 struct net_device *mirred_dev,
3370 int out_index,
8c4dc42b 3371 struct netlink_ext_ack *extack,
0ad060ee
RD		 3372 struct net_device **encap_dev,
3373 bool *encap_valid)
a54e20b4
HHZ		 3374{
3375 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 3376 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 3377 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 3378 const struct ip_tunnel_info *tun_info;
948993f2 3379 struct encap_key key;
c1ae1152 3380 struct mlx5e_encap_entry *e;
733d4f36 3381 unsigned short family;
a54e20b4 3382 uintptr_t hash_key;
54c177ca 3383 int err = 0;
a54e20b4 3384
733d4f36 3385 parse_attr = attr->parse_attr;
1f6da306 3386 tun_info = parse_attr->tun_info[out_index];
733d4f36 3387 family = ip_tunnel_info_af(tun_info);
7f1a546e 3388 key.ip_tun_key = &tun_info->key;
d386939a 3389 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3390 if (!key.tc_tunnel) {
3391 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3392 return -EOPNOTSUPP;
3393 }
733d4f36 3394
7f1a546e 3395 hash_key = hash_encap_info(&key);
a54e20b4 3396
61086f39 3397 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3398 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3399
b2812089 3400 /* must verify if encap is valid or not */
d589e785 3401 if (e) {
554fe75c
DL		 3402 /* Check that entry was not already attached to this flow */
3403 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3404 err = -EOPNOTSUPP;
3405 goto out_err;
3406 }
3407
d589e785
VB		 3408 mutex_unlock(&esw->offloads.encap_tbl_lock);
3409 wait_for_completion(&e->res_ready);
3410
3411 /* Protect against concurrent neigh update. */
3412 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3413 if (e->compl_result < 0) {
d589e785
VB		 3414 err = -EREMOTEIO;
3415 goto out_err;
3416 }
45247bf2 3417 goto attach_flow;
d589e785 3418 }
a54e20b4
HHZ		 3419
3420 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3421 if (!e) {
3422 err = -ENOMEM;
3423 goto out_err;
3424 }
a54e20b4 3425
948993f2 3426 refcount_set(&e->refcnt, 1);
d589e785
VB		 3427 init_completion(&e->res_ready);
3428
2a4b6526
VB		 3429 tun_info = dup_tun_info(tun_info);
3430 if (!tun_info) {
3431 err = -ENOMEM;
3432 goto out_err_init;
3433 }
1f6da306 3434 e->tun_info = tun_info;
101f4de9 3435 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3436 if (err)
3437 goto out_err_init;
54c177ca 3438
a54e20b4 3439 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3440 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3441 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3442
ce99f6b9 3443 if (family == AF_INET)
101f4de9 3444 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3445 else if (family == AF_INET6)
101f4de9 3446 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3447
d589e785
VB		 3448 /* Protect against concurrent neigh update. */
3449 mutex_lock(&esw->offloads.encap_tbl_lock);
3450 complete_all(&e->res_ready);
3451 if (err) {
3452 e->compl_result = err;
a54e20b4 3453 goto out_err;
d589e785 3454 }
3c140dd5 3455 e->compl_result = 1;
a54e20b4 3456
45247bf2 3457attach_flow:
948993f2 3458 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3459 list_add(&flow->encaps[out_index].list, &e->flows);
3460 flow->encaps[out_index].index = out_index;
45247bf2 3461 *encap_dev = e->out_dev;
8c4dc42b 3462 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2b688ea5 3463 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
8c4dc42b 3464 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3465 *encap_valid = true;
8c4dc42b 3466 } else {
0ad060ee 3467 *encap_valid = false;
8c4dc42b 3468 }
61086f39 3469 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3470
232c0013 3471 return err;
a54e20b4
HHZ		 3472
3473out_err:
61086f39 3474 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3475 if (e)
3476 mlx5e_encap_put(priv, e);
a54e20b4 3477 return err;
2a4b6526
VB		 3478
3479out_err_init:
3480 mutex_unlock(&esw->offloads.encap_tbl_lock);
3481 kfree(tun_info);
3482 kfree(e);
3483 return err;
a54e20b4
HHZ		 3484}
3485
1482bd3d 3486static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3487 const struct flow_action_entry *act,
1482bd3d
JL		 3488 struct mlx5_esw_flow_attr *attr,
3489 u32 *action)
3490{
cc495188
JL		 3491 u8 vlan_idx = attr->total_vlan;
3492
3493 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3494 return -EOPNOTSUPP;
3495
73867881
PNA		 3496 switch (act->id) {
3497 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3498 if (vlan_idx) {
3499 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3500 MLX5_FS_VLAN_DEPTH))
3501 return -EOPNOTSUPP;
3502
3503 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3504 } else {
3505 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3506 }
73867881
PNA		 3507 break;
3508 case FLOW_ACTION_VLAN_PUSH:
3509 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3510 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3511 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3512 if (!attr->vlan_proto[vlan_idx])
3513 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3514
3515 if (vlan_idx) {
3516 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3517 MLX5_FS_VLAN_DEPTH))
3518 return -EOPNOTSUPP;
3519
3520 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3521 } else {
3522 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 3523 (act->vlan.proto != htons(ETH_P_8021Q) ||
3524 act->vlan.prio))
cc495188
JL		 3525 return -EOPNOTSUPP;
3526
3527 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3528 }
73867881
PNA		 3529 break;
3530 default:
bdc837ee 3531 return -EINVAL;
1482bd3d
JL		 3532 }
3533
cc495188
JL		 3534 attr->total_vlan = vlan_idx + 1;
3535
1482bd3d
JL		 3536 return 0;
3537}
3538
278748a9
EB		 3539static int add_vlan_push_action(struct mlx5e_priv *priv,
3540 struct mlx5_esw_flow_attr *attr,
3541 struct net_device **out_dev,
3542 u32 *action)
3543{
3544 struct net_device *vlan_dev = *out_dev;
3545 struct flow_action_entry vlan_act = {
3546 .id = FLOW_ACTION_VLAN_PUSH,
3547 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3548 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3549 .vlan.prio = 0,
3550 };
3551 int err;
3552
3553 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3554 if (err)
3555 return err;
3556
3557 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3558 dev_get_iflink(vlan_dev));
3559 if (is_vlan_dev(*out_dev))
3560 err = add_vlan_push_action(priv, attr, out_dev, action);
3561
3562 return err;
3563}
3564
35a605db
EB		 3565static int add_vlan_pop_action(struct mlx5e_priv *priv,
3566 struct mlx5_esw_flow_attr *attr,
3567 u32 *action)
3568{
f3b0a18b 3569 int nest_level = attr->parse_attr->filter_dev->lower_level;
35a605db
EB		 3570 struct flow_action_entry vlan_act = {
3571 .id = FLOW_ACTION_VLAN_POP,
3572 };
3573 int err = 0;
3574
3575 while (nest_level--) {
3576 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3577 if (err)
3578 return err;
3579 }
3580
3581 return err;
3582}
3583
f6dc1264
PB		 3584bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3585 struct net_device *out_dev)
3586{
3587 if (is_merged_eswitch_dev(priv, out_dev))
3588 return true;
3589
3590 return mlx5e_eswitch_rep(out_dev) &&
3591 same_hw_devs(priv, netdev_priv(out_dev));
3592}
3593
554fe75c
DL		 3594static bool is_duplicated_output_device(struct net_device *dev,
3595 struct net_device *out_dev,
3596 int *ifindexes, int if_count,
3597 struct netlink_ext_ack *extack)
3598{
3599 int i;
3600
3601 for (i = 0; i < if_count; i++) {
3602 if (ifindexes[i] == out_dev->ifindex) {
3603 NL_SET_ERR_MSG_MOD(extack,
3604 "can't duplicate output to same device");
3605 netdev_err(dev, "can't duplicate output to same device: %s\n",
3606 out_dev->name);
3607 return true;
3608 }
3609 }
3610
3611 return false;
3612}
3613
2fbbc30d
EC		 3614static int mlx5_validate_goto_chain(struct mlx5_eswitch *esw,
3615 struct mlx5e_tc_flow *flow,
3616 const struct flow_action_entry *act,
3617 u32 actions,
3618 struct netlink_ext_ack *extack)
3619{
3620 u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
3621 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3622 bool ft_flow = mlx5e_is_ft_flow(flow);
3623 u32 dest_chain = act->chain_index;
3624
3625 if (ft_flow) {
3626 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3627 return -EOPNOTSUPP;
3628 }
3629
3630 if (!mlx5_esw_chains_backwards_supported(esw) &&
3631 dest_chain <= attr->chain) {
3632 NL_SET_ERR_MSG_MOD(extack,
3633 "Goto lower numbered chain isn't supported");
3634 return -EOPNOTSUPP;
3635 }
3636 if (dest_chain > max_chain) {
3637 NL_SET_ERR_MSG_MOD(extack,
3638 "Requested destination chain is out of supported range");
3639 return -EOPNOTSUPP;
3640 }
3641
3642 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3643 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3644 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat_and_fwd_to_table)) {
3645 NL_SET_ERR_MSG_MOD(extack,
3646 "Goto chain is not allowed if action has reformat or decap");
3647 return -EOPNOTSUPP;
3648 }
3649
3650 return 0;
3651}
3652
73867881
PNA		 3653static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3654 struct flow_action *flow_action,
e98bedf5
EB		 3655 struct mlx5e_tc_flow *flow,
3656 struct netlink_ext_ack *extack)
03a9d11e 3657{
73867881 3658 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3659 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 3660 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 3661 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 3662 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 3663 const struct ip_tunnel_info *info = NULL;
554fe75c 3664 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3665 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3666 const struct flow_action_entry *act;
0a7fcb78
PB		 3667 bool encap = false, decap = false;
3668 u32 action = attr->action;
554fe75c 3669 int err, i, if_count = 0;
03a9d11e 3670
73867881 3671 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 3672 return -EINVAL;
3673
48855479 3674 if (!flow_action_hw_stats_types_check(flow_action, extack,
a16fa289 3675 FLOW_ACTION_HW_STATS_TYPE_DELAYED_BIT))
319a1d19
JP		 3676 return -EOPNOTSUPP;
3677
73867881
PNA		 3678 flow_action_for_each(i, act, flow_action) {
3679 switch (act->id) {
3680 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3681 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3682 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3683 break;
3684 case FLOW_ACTION_MANGLE:
3685 case FLOW_ACTION_ADD:
3686 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
dec481c8 3687 hdrs, extack);
d7e75a32
OG		 3688 if (err)
3689 return err;
3690
1cab1cd7 3691 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 3692 attr->split_count = attr->out_count;
73867881
PNA		 3693 break;
3694 case FLOW_ACTION_CSUM:
1cab1cd7 3695 if (csum_offload_supported(priv, action,
73867881
PNA		 3696 act->csum_flags, extack))
3697 break;
26c02749
OG		 3698
3699 return -EOPNOTSUPP;
73867881
PNA		 3700 case FLOW_ACTION_REDIRECT:
3701 case FLOW_ACTION_MIRRED: {
03a9d11e 3702 struct mlx5e_priv *out_priv;
592d3651 3703 struct net_device *out_dev;
03a9d11e 3704
73867881 3705 out_dev = act->dev;
ef381359
OS		 3706 if (!out_dev) {
3707 /* out_dev is NULL when filters with
3708 * non-existing mirred device are replayed to
3709 * the driver.
3710 */
3711 return -EINVAL;
3712 }
03a9d11e 3713
84179981
PB		 3714 if (ft_flow && out_dev == priv->netdev) {
3715 /* Ignore forward to self rules generated
3716 * by adding both mlx5 devs to the flow table
3717 * block on a normal nft offload setup.
3718 */
3719 return -EOPNOTSUPP;
3720 }
3721
592d3651 3722 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3723 NL_SET_ERR_MSG_MOD(extack,
3724 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3725 netdev_warn(priv->netdev,
3726 "can't support more than %d output ports, can't offload forwarding\n",
3727 attr->out_count);
592d3651
CM		 3728 return -EOPNOTSUPP;
3729 }
3730
f493f155
EB		 3731 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3732 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24
VB		 3733 if (encap) {
3734 parse_attr->mirred_ifindex[attr->out_count] =
3735 out_dev->ifindex;
3736 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3737 if (!parse_attr->tun_info[attr->out_count])
3738 return -ENOMEM;
3739 encap = false;
3740 attr->dests[attr->out_count].flags |=
3741 MLX5_ESW_DEST_ENCAP;
3742 attr->out_count++;
3743 /* attr->dests[].rep is resolved when we
3744 * handle encap
3745 */
3746 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3747 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3748 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
fa833bd5 3749 struct net_device *uplink_upper;
ffec9702 3750 struct mlx5e_rep_priv *rep_priv;
7ba58ba7 3751
554fe75c
DL		 3752 if (is_duplicated_output_device(priv->netdev,
3753 out_dev,
3754 ifindexes,
3755 if_count,
3756 extack))
3757 return -EOPNOTSUPP;
3758
3759 ifindexes[if_count] = out_dev->ifindex;
3760 if_count++;
3761
fa833bd5
VB		 3762 rcu_read_lock();
3763 uplink_upper =
3764 netdev_master_upper_dev_get_rcu(uplink_dev);
7ba58ba7
RL		 3765 if (uplink_upper &&
3766 netif_is_lag_master(uplink_upper) &&
3767 uplink_upper == out_dev)
3768 out_dev = uplink_dev;
fa833bd5 3769 rcu_read_unlock();
7ba58ba7 3770
278748a9
EB		 3771 if (is_vlan_dev(out_dev)) {
3772 err = add_vlan_push_action(priv, attr,
3773 &out_dev,
3774 &action);
3775 if (err)
3776 return err;
3777 }
f6dc1264 3778
35a605db
EB		 3779 if (is_vlan_dev(parse_attr->filter_dev)) {
3780 err = add_vlan_pop_action(priv, attr,
3781 &action);
3782 if (err)
3783 return err;
3784 }
278748a9 3785
ffec9702
TZ		 3786 /* Don't allow forwarding between uplink.
3787 *
3788 * Input vport was stored esw_attr->in_rep.
3789 * In LAG case, *priv* is the private data of
3790 * uplink which may be not the input vport.
3791 */
3792 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3793 if (mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3794 mlx5e_eswitch_uplink_rep(out_dev)) {
3795 NL_SET_ERR_MSG_MOD(extack,
3796 "devices are both uplink, can't offload forwarding");
3797 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3798 priv->netdev->name, out_dev->name);
3799 return -EOPNOTSUPP;
3800 }
3801
f6dc1264
PB		 3802 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3803 NL_SET_ERR_MSG_MOD(extack,
3804 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3805 netdev_warn(priv->netdev,
3806 "devices %s %s not on same switch HW, can't offload forwarding\n",
3807 priv->netdev->name,
3808 out_dev->name);
a0646c88 3809 return -EOPNOTSUPP;
f6dc1264 3810 }
a0646c88 3811
a54e20b4 3812 out_priv = netdev_priv(out_dev);
1d447a39 3813 rpriv = out_priv->ppriv;
df65a573
EB		 3814 attr->dests[attr->out_count].rep = rpriv->rep;
3815 attr->dests[attr->out_count].mdev = out_priv->mdev;
3816 attr->out_count++;
ef381359
OS		 3817 } else if (parse_attr->filter_dev != priv->netdev) {
3818 /* All mlx5 devices are called to configure
3819 * high level device filters. Therefore, the
3820 * *attempt* to install a filter on invalid
3821 * eswitch should not trigger an explicit error
3822 */
3823 return -EINVAL;
a54e20b4 3824 } else {
e98bedf5
EB		 3825 NL_SET_ERR_MSG_MOD(extack,
3826 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 3827 netdev_warn(priv->netdev,
3828 "devices %s %s not on same switch HW, can't offload forwarding\n",
3829 priv->netdev->name,
3830 out_dev->name);
03a9d11e
OG		 3831 return -EINVAL;
3832 }
73867881
PNA		 3833 }
3834 break;
3835 case FLOW_ACTION_TUNNEL_ENCAP:
3836 info = act->tunnel;
a54e20b4
HHZ		 3837 if (info)
3838 encap = true;
3839 else
3840 return -EOPNOTSUPP;
1482bd3d 3841
73867881
PNA		 3842 break;
3843 case FLOW_ACTION_VLAN_PUSH:
3844 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3845 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3846 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3847 /* Replace vlan pop+push with vlan modify */
3848 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3849 err = add_vlan_rewrite_action(priv,
3850 MLX5_FLOW_NAMESPACE_FDB,
3851 act, parse_attr, hdrs,
3852 &action, extack);
3853 } else {
3854 err = parse_tc_vlan_action(priv, act, attr, &action);
3855 }
1482bd3d
JL		 3856 if (err)
3857 return err;
3858
bdc837ee
EB		 3859 attr->split_count = attr->out_count;
3860 break;
3861 case FLOW_ACTION_VLAN_MANGLE:
3862 err = add_vlan_rewrite_action(priv,
3863 MLX5_FLOW_NAMESPACE_FDB,
3864 act, parse_attr, hdrs,
3865 &action, extack);
3866 if (err)
3867 return err;
3868
e85e02ba 3869 attr->split_count = attr->out_count;
73867881
PNA		 3870 break;
3871 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 3872 decap = true;
73867881 3873 break;
2fbbc30d
EC		 3874 case FLOW_ACTION_GOTO:
3875 err = mlx5_validate_goto_chain(esw, flow, act, action,
3876 extack);
3877 if (err)
3878 return err;
bf07aa73 3879
e88afe75 3880 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 3881 attr->dest_chain = act->chain_index;
73867881 3882 break;
4c3844d9
PB		 3883 case FLOW_ACTION_CT:
3884 err = mlx5_tc_ct_parse_action(priv, attr, act, extack);
3885 if (err)
3886 return err;
3887
3888 flow_flag_set(flow, CT);
3889 break;
73867881 3890 default:
2cc1cb1d
TZ		 3891 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3892 return -EOPNOTSUPP;
bf07aa73 3893 }
03a9d11e 3894 }
bdd66ac0 3895
0bac1194
EB		 3896 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3897 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3898 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3899 * tag rewrite.
3900 */
3901 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3902 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3903 &action, extack);
3904 if (err)
3905 return err;
3906 }
3907
c500c86b
PNA		 3908 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3909 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3910 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3911 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3912 if (err)
3913 return err;
27c11b6b
EB		 3914 /* in case all pedit actions are skipped, remove the MOD_HDR
3915 * flag. we might have set split_count either by pedit or
3916 * pop/push. if there is no pop/push either, reset it too.
3917 */
6ae4a6a5 3918 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3919 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3920 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 3921 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3922 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3923 attr->split_count = 0;
3924 }
c500c86b
PNA		 3925 }
3926
1cab1cd7 3927 attr->action = action;
73867881 3928 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3929 return -EOPNOTSUPP;
3930
e88afe75 3931 if (attr->dest_chain) {
0a7fcb78
PB		 3932 if (decap) {
3933 /* It can be supported if we'll create a mapping for
3934 * the tunnel device only (without tunnel), and set
3935 * this tunnel id with this decap flow.
3936 *
3937 * On restore (miss), we'll just set this saved tunnel
3938 * device.
3939 */
3940
3941 NL_SET_ERR_MSG(extack,
3942 "Decap with goto isn't supported");
3943 netdev_warn(priv->netdev,
3944 "Decap with goto isn't supported");
3945 return -EOPNOTSUPP;
3946 }
3947
e88afe75 3948 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 3949 NL_SET_ERR_MSG_MOD(extack,
3950 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 3951 return -EOPNOTSUPP;
3952 }
3953 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3954 }
3955
ae2741e2
VB		 3956 if (!(attr->action &
3957 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 3958 NL_SET_ERR_MSG_MOD(extack,
3959 "Rule must have at least one forward/drop action");
ae2741e2
VB		 3960 return -EOPNOTSUPP;
3961 }
3962
e85e02ba 3963 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3964 NL_SET_ERR_MSG_MOD(extack,
3965 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3966 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3967 return -EOPNOTSUPP;
3968 }
3969
31c8eba5 3970 return 0;
03a9d11e
OG		 3971}
3972
226f2ca3 3973static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3974{
226f2ca3 3975 unsigned long __flow_flags = 0;
60bd4af8 3976
226f2ca3
VB		 3977 if (flags & MLX5_TC_FLAG(INGRESS))
3978 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3979 if (flags & MLX5_TC_FLAG(EGRESS))
3980 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3981
226f2ca3
VB		 3982 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3983 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3984 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3985 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 3986 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3987 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 3988
60bd4af8
OG		 3989 *flow_flags = __flow_flags;
3990}
3991
05866c82
OG		 3992static const struct rhashtable_params tc_ht_params = {
3993 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3994 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3995 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3996 .automatic_shrinking = true,
3997};
3998
226f2ca3
VB		 3999static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4000 unsigned long flags)
05866c82 4001{
655dc3d2
OG		 4002 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4003 struct mlx5e_rep_priv *uplink_rpriv;
4004
226f2ca3 4005 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4006 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4007 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4008 } else /* NIC offload */
655dc3d2 4009 return &priv->fs.tc.ht;
05866c82
OG		 4010}
4011
04de7dda
RD		 4012static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4013{
1418ddd9 4014 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 4015 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4016 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4017 bool act_is_encap = !!(attr->action &
4018 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4019 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
4020 MLX5_DEVCOM_ESW_OFFLOADS);
4021
10fbb1cd
RD		 4022 if (!esw_paired)
4023 return false;
4024
4025 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
4026 mlx5_lag_is_multipath(attr->in_mdev)) &&
4027 (is_rep_ingress || act_is_encap))
4028 return true;
4029
4030 return false;
04de7dda
RD		 4031}
4032
a88780a9
RD		 4033static int
4034mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4035 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4036 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4037 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4038{
17091853 4039 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 4040 struct mlx5e_tc_flow *flow;
5a7e5bcb 4041 int out_index, err;
e3a2b7ed 4042
65ba8fb7 4043 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 4044 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 4045 if (!parse_attr || !flow) {
e3a2b7ed
AV		 4046 err = -ENOMEM;
4047 goto err_free;
4048 }
4049
4050 flow->cookie = f->cookie;
65ba8fb7 4051 flow->flags = flow_flags;
655dc3d2 4052 flow->priv = priv;
5a7e5bcb
VB		 4053 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4054 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4055 INIT_LIST_HEAD(&flow->mod_hdr);
4056 INIT_LIST_HEAD(&flow->hairpin);
4057 refcount_set(&flow->refcnt, 1);
95435ad7 4058 init_completion(&flow->init_done);
e3a2b7ed 4059
a88780a9
RD		 4060 *__flow = flow;
4061 *__parse_attr = parse_attr;
4062
4063 return 0;
4064
4065err_free:
4066 kfree(flow);
4067 kvfree(parse_attr);
4068 return err;
4069}
4070
988ab9c7
TZ		 4071static void
4072mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
4073 struct mlx5e_priv *priv,
4074 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4075 struct flow_cls_offload *f,
988ab9c7
TZ		 4076 struct mlx5_eswitch_rep *in_rep,
4077 struct mlx5_core_dev *in_mdev)
4078{
4079 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4080
4081 esw_attr->parse_attr = parse_attr;
4082 esw_attr->chain = f->common.chain_index;
ef01adae 4083 esw_attr->prio = f->common.prio;
988ab9c7
TZ		 4084
4085 esw_attr->in_rep = in_rep;
4086 esw_attr->in_mdev = in_mdev;
4087
4088 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4089 MLX5_COUNTER_SOURCE_ESWITCH)
4090 esw_attr->counter_dev = in_mdev;
4091 else
4092 esw_attr->counter_dev = priv->mdev;
4093}
4094
71129676 4095static struct mlx5e_tc_flow *
04de7dda 4096__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4097 struct flow_cls_offload *f,
226f2ca3 4098 unsigned long flow_flags,
04de7dda
RD		 4099 struct net_device *filter_dev,
4100 struct mlx5_eswitch_rep *in_rep,
71129676 4101 struct mlx5_core_dev *in_mdev)
a88780a9 4102{
f9e30088 4103 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4104 struct netlink_ext_ack *extack = f->common.extack;
4105 struct mlx5e_tc_flow_parse_attr *parse_attr;
4106 struct mlx5e_tc_flow *flow;
4107 int attr_size, err;
e3a2b7ed 4108
226f2ca3 4109 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4110 attr_size = sizeof(struct mlx5_esw_flow_attr);
4111 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4112 &parse_attr, &flow);
4113 if (err)
4114 goto out;
988ab9c7 4115
d11afc26 4116 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 4117 mlx5e_flow_esw_attr_init(flow->esw_attr,
4118 priv, parse_attr,
4119 f, in_rep, in_mdev);
4120
54c177ca
OS		 4121 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4122 f, filter_dev);
d11afc26
OS		 4123 if (err)
4124 goto err_free;
a88780a9 4125
6f9af8ff 4126 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 4127 if (err)
4128 goto err_free;
4129
4c3844d9
PB		 4130 err = mlx5_tc_ct_parse_match(priv, &parse_attr->spec, f, extack);
4131 if (err)
4132 goto err_free;
4133
7040632d 4134 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4135 complete_all(&flow->init_done);
ef06c9ee
RD		 4136 if (err) {
4137 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4138 goto err_free;
4139
b4a23329 4140 add_unready_flow(flow);
ef06c9ee 4141 }
e3a2b7ed 4142
71129676 4143 return flow;
a88780a9
RD		 4144
4145err_free:
5a7e5bcb 4146 mlx5e_flow_put(priv, flow);
a88780a9 4147out:
71129676 4148 return ERR_PTR(err);
a88780a9
RD		 4149}
4150
f9e30088 4151static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4152 struct mlx5e_tc_flow *flow,
226f2ca3 4153 unsigned long flow_flags)
04de7dda
RD		 4154{
4155 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4156 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
4157 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4158 struct mlx5e_tc_flow_parse_attr *parse_attr;
4159 struct mlx5e_rep_priv *peer_urpriv;
4160 struct mlx5e_tc_flow *peer_flow;
4161 struct mlx5_core_dev *in_mdev;
4162 int err = 0;
4163
4164 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4165 if (!peer_esw)
4166 return -ENODEV;
4167
4168 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4169 peer_priv = netdev_priv(peer_urpriv->netdev);
4170
4171 /* in_mdev is assigned of which the packet originated from.
4172 * So packets redirected to uplink use the same mdev of the
4173 * original flow and packets redirected from uplink use the
4174 * peer mdev.
4175 */
b05af6aa 4176 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4177 in_mdev = peer_priv->mdev;
4178 else
4179 in_mdev = priv->mdev;
4180
4181 parse_attr = flow->esw_attr->parse_attr;
95dc1902 4182 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 4183 parse_attr->filter_dev,
4184 flow->esw_attr->in_rep, in_mdev);
4185 if (IS_ERR(peer_flow)) {
4186 err = PTR_ERR(peer_flow);
04de7dda 4187 goto out;
71129676 4188 }
04de7dda
RD		 4189
4190 flow->peer_flow = peer_flow;
226f2ca3 4191 flow_flag_set(flow, DUP);
04de7dda
RD		 4192 mutex_lock(&esw->offloads.peer_mutex);
4193 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4194 mutex_unlock(&esw->offloads.peer_mutex);
4195
4196out:
4197 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4198 return err;
4199}
4200
4201static int
4202mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4203 struct flow_cls_offload *f,
226f2ca3 4204 unsigned long flow_flags,
04de7dda
RD		 4205 struct net_device *filter_dev,
4206 struct mlx5e_tc_flow **__flow)
4207{
4208 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4209 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4210 struct mlx5_core_dev *in_mdev = priv->mdev;
4211 struct mlx5e_tc_flow *flow;
4212 int err;
4213
71129676
JG		 4214 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4215 in_mdev);
4216 if (IS_ERR(flow))
4217 return PTR_ERR(flow);
04de7dda
RD		 4218
4219 if (is_peer_flow_needed(flow)) {
95dc1902 4220 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4221 if (err) {
4222 mlx5e_tc_del_fdb_flow(priv, flow);
4223 goto out;
4224 }
4225 }
4226
4227 *__flow = flow;
4228
4229 return 0;
4230
4231out:
4232 return err;
4233}
4234
a88780a9
RD		 4235static int
4236mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4237 struct flow_cls_offload *f,
226f2ca3 4238 unsigned long flow_flags,
d11afc26 4239 struct net_device *filter_dev,
a88780a9
RD		 4240 struct mlx5e_tc_flow **__flow)
4241{
f9e30088 4242 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4243 struct netlink_ext_ack *extack = f->common.extack;
4244 struct mlx5e_tc_flow_parse_attr *parse_attr;
4245 struct mlx5e_tc_flow *flow;
4246 int attr_size, err;
4247
bf07aa73
PB		 4248 /* multi-chain not supported for NIC rules */
4249 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4250 return -EOPNOTSUPP;
4251
226f2ca3 4252 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4253 attr_size = sizeof(struct mlx5_nic_flow_attr);
4254 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4255 &parse_attr, &flow);
4256 if (err)
4257 goto out;
4258
d11afc26 4259 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 4260 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4261 f, filter_dev);
d11afc26
OS		 4262 if (err)
4263 goto err_free;
4264
73867881 4265 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4266 if (err)
4267 goto err_free;
4268
4269 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4270 if (err)
4271 goto err_free;
4272
226f2ca3 4273 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4274 kvfree(parse_attr);
4275 *__flow = flow;
4276
4277 return 0;
e3a2b7ed 4278
e3a2b7ed 4279err_free:
5a7e5bcb 4280 mlx5e_flow_put(priv, flow);
17091853 4281 kvfree(parse_attr);
a88780a9
RD		 4282out:
4283 return err;
4284}
4285
4286static int
4287mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4288 struct flow_cls_offload *f,
226f2ca3 4289 unsigned long flags,
d11afc26 4290 struct net_device *filter_dev,
a88780a9
RD		 4291 struct mlx5e_tc_flow **flow)
4292{
4293 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4294 unsigned long flow_flags;
a88780a9
RD		 4295 int err;
4296
4297 get_flags(flags, &flow_flags);
4298
bf07aa73
PB		 4299 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4300 return -EOPNOTSUPP;
4301
f6455de0 4302 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4303 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4304 filter_dev, flow);
a88780a9 4305 else
d11afc26
OS		 4306 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4307 filter_dev, flow);
a88780a9
RD		 4308
4309 return err;
4310}
4311
71d82d2a 4312int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4313 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4314{
4315 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4316 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 4317 struct mlx5e_tc_flow *flow;
4318 int err = 0;
4319
c5d326b2
VB		 4320 rcu_read_lock();
4321 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4322 rcu_read_unlock();
a88780a9
RD		 4323 if (flow) {
4324 NL_SET_ERR_MSG_MOD(extack,
4325 "flow cookie already exists, ignoring");
4326 netdev_warn_once(priv->netdev,
4327 "flow cookie %lx already exists, ignoring\n",
4328 f->cookie);
0e1c1a2f 4329 err = -EEXIST;
a88780a9
RD		 4330 goto out;
4331 }
4332
7a978759 4333 trace_mlx5e_configure_flower(f);
d11afc26 4334 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4335 if (err)
4336 goto out;
4337
c5d326b2 4338 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4339 if (err)
4340 goto err_free;
4341
4342 return 0;
4343
4344err_free:
5a7e5bcb 4345 mlx5e_flow_put(priv, flow);
a88780a9 4346out:
e3a2b7ed
AV		 4347 return err;
4348}
4349
8f8ae895
OG		 4350static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4351{
226f2ca3
VB		 4352 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4353 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4354
226f2ca3
VB		 4355 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4356 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4357}
4358
71d82d2a 4359int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4360 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4361{
d9ee0491 4362 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4363 struct mlx5e_tc_flow *flow;
c5d326b2 4364 int err;
e3a2b7ed 4365
c5d326b2 4366 rcu_read_lock();
ab818362 4367 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4368 if (!flow || !same_flow_direction(flow, flags)) {
4369 err = -EINVAL;
4370 goto errout;
4371 }
e3a2b7ed 4372
c5d326b2
VB		 4373 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4374 * set.
4375 */
4376 if (flow_flag_test_and_set(flow, DELETED)) {
4377 err = -EINVAL;
4378 goto errout;
4379 }
05866c82 4380 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4381 rcu_read_unlock();
e3a2b7ed 4382
7a978759 4383 trace_mlx5e_delete_flower(f);
5a7e5bcb 4384 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 4385
4386 return 0;
c5d326b2
VB		 4387
4388errout:
4389 rcu_read_unlock();
4390 return err;
e3a2b7ed
AV		 4391}
4392
71d82d2a 4393int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4394 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4395{
04de7dda 4396 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4397 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4398 struct mlx5_eswitch *peer_esw;
aad7e08d 4399 struct mlx5e_tc_flow *flow;
aad7e08d 4400 struct mlx5_fc *counter;
316d5f72
RD		 4401 u64 lastuse = 0;
4402 u64 packets = 0;
4403 u64 bytes = 0;
5a7e5bcb 4404 int err = 0;
aad7e08d 4405
c5d326b2
VB		 4406 rcu_read_lock();
4407 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4408 tc_ht_params));
4409 rcu_read_unlock();
5a7e5bcb
VB		 4410 if (IS_ERR(flow))
4411 return PTR_ERR(flow);
4412
4413 if (!same_flow_direction(flow, flags)) {
4414 err = -EINVAL;
4415 goto errout;
4416 }
aad7e08d 4417
4c3844d9 4418 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4419 counter = mlx5e_tc_get_counter(flow);
4420 if (!counter)
5a7e5bcb 4421 goto errout;
aad7e08d 4422
316d5f72
RD		 4423 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4424 }
aad7e08d 4425
316d5f72
RD		 4426 /* Under multipath it's possible for one rule to be currently
4427 * un-offloaded while the other rule is offloaded.
4428 */
04de7dda
RD		 4429 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4430 if (!peer_esw)
4431 goto out;
4432
226f2ca3
VB		 4433 if (flow_flag_test(flow, DUP) &&
4434 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4435 u64 bytes2;
4436 u64 packets2;
4437 u64 lastuse2;
4438
4439 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4440 if (!counter)
4441 goto no_peer_counter;
04de7dda
RD		 4442 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4443
4444 bytes += bytes2;
4445 packets += packets2;
4446 lastuse = max_t(u64, lastuse, lastuse2);
4447 }
4448
316d5f72 4449no_peer_counter:
04de7dda 4450 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4451out:
3b1903ef 4452 flow_stats_update(&f->stats, bytes, packets, lastuse);
7a978759 4453 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4454errout:
4455 mlx5e_flow_put(priv, flow);
4456 return err;
aad7e08d
AV		 4457}
4458
fcb64c0f
EC		 4459static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4460 struct netlink_ext_ack *extack)
4461{
4462 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4463 struct mlx5_eswitch *esw;
4464 u16 vport_num;
4465 u32 rate_mbps;
4466 int err;
4467
e401a184
EC		 4468 vport_num = rpriv->rep->vport;
4469 if (vport_num >= MLX5_VPORT_ECPF) {
4470 NL_SET_ERR_MSG_MOD(extack,
4471 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4472 return -EOPNOTSUPP;
4473 }
4474
fcb64c0f
EC		 4475 esw = priv->mdev->priv.eswitch;
4476 /* rate is given in bytes/sec.
4477 * First convert to bits/sec and then round to the nearest mbit/secs.
4478 * mbit means million bits.
4479 * Moreover, if rate is non zero we choose to configure to a minimum of
4480 * 1 mbit/sec.
4481 */
4482 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
fcb64c0f
EC		 4483 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4484 if (err)
4485 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4486
4487 return err;
4488}
4489
4490static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4491 struct flow_action *flow_action,
4492 struct netlink_ext_ack *extack)
4493{
4494 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4495 const struct flow_action_entry *act;
4496 int err;
4497 int i;
4498
4499 if (!flow_action_has_entries(flow_action)) {
4500 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4501 return -EINVAL;
4502 }
4503
4504 if (!flow_offload_has_one_action(flow_action)) {
4505 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4506 return -EOPNOTSUPP;
4507 }
4508
319a1d19
JP		 4509 if (!flow_action_basic_hw_stats_types_check(flow_action, extack))
4510 return -EOPNOTSUPP;
4511
fcb64c0f
EC		 4512 flow_action_for_each(i, act, flow_action) {
4513 switch (act->id) {
4514 case FLOW_ACTION_POLICE:
4515 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4516 if (err)
4517 return err;
4518
4519 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4520 break;
4521 default:
4522 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4523 return -EOPNOTSUPP;
4524 }
4525 }
4526
4527 return 0;
4528}
4529
4530int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4531 struct tc_cls_matchall_offload *ma)
4532{
4533 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4534
7b83355f 4535 if (ma->common.prio != 1) {
fcb64c0f
EC		 4536 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4537 return -EINVAL;
4538 }
4539
4540 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4541}
4542
4543int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4544 struct tc_cls_matchall_offload *ma)
4545{
4546 struct netlink_ext_ack *extack = ma->common.extack;
4547
4548 return apply_police_params(priv, 0, extack);
4549}
4550
4551void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4552 struct tc_cls_matchall_offload *ma)
4553{
4554 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4555 struct rtnl_link_stats64 cur_stats;
4556 u64 dbytes;
4557 u64 dpkts;
4558
4559 cur_stats = priv->stats.vf_vport;
4560 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4561 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4562 rpriv->prev_vf_vport_stats = cur_stats;
4563 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
4564}
4565
4d8fcf21
AH		 4566static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4567 struct mlx5e_priv *peer_priv)
4568{
4569 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4570 struct mlx5e_hairpin_entry *hpe, *tmp;
4571 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4572 u16 peer_vhca_id;
4573 int bkt;
4574
4575 if (!same_hw_devs(priv, peer_priv))
4576 return;
4577
4578 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4579
b32accda 4580 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4581 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4582 if (refcount_inc_not_zero(&hpe->refcnt))
4583 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4584 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4585
4586 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4587 wait_for_completion(&hpe->res_ready);
4588 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 4589 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 4590
4591 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4592 }
4593}
4594
4595static int mlx5e_tc_netdev_event(struct notifier_block *this,
4596 unsigned long event, void *ptr)
4597{
4598 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4599 struct mlx5e_flow_steering *fs;
4600 struct mlx5e_priv *peer_priv;
4601 struct mlx5e_tc_table *tc;
4602 struct mlx5e_priv *priv;
4603
4604 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4605 event != NETDEV_UNREGISTER ||
4606 ndev->reg_state == NETREG_REGISTERED)
4607 return NOTIFY_DONE;
4608
4609 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4610 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4611 priv = container_of(fs, struct mlx5e_priv, fs);
4612 peer_priv = netdev_priv(ndev);
4613 if (priv == peer_priv ||
4614 !(priv->netdev->features & NETIF_F_HW_TC))
4615 return NOTIFY_DONE;
4616
4617 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4618
4619 return NOTIFY_DONE;
4620}
4621
655dc3d2 4622int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4623{
acff797c 4624 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 4625 int err;
e8f887ac 4626
b6fac0b4 4627 mutex_init(&tc->t_lock);
d2faae25 4628 mutex_init(&tc->mod_hdr.lock);
dd58edc3 4629 hash_init(tc->mod_hdr.hlist);
b32accda 4630 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4631 hash_init(tc->hairpin_tbl);
11c9c548 4632
4d8fcf21
AH		 4633 err = rhashtable_init(&tc->ht, &tc_ht_params);
4634 if (err)
4635 return err;
4636
4637 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4638 err = register_netdevice_notifier_dev_net(priv->netdev,
4639 &tc->netdevice_nb,
4640 &tc->netdevice_nn);
4641 if (err) {
4d8fcf21
AH		 4642 tc->netdevice_nb.notifier_call = NULL;
4643 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4644 }
4645
4646 return err;
e8f887ac
AV		 4647}
4648
4649static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4650{
4651 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4652 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4653
961e8979 4654 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4655 kfree(flow);
4656}
4657
655dc3d2 4658void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4659{
acff797c 4660 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4661
4d8fcf21 4662 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4663 unregister_netdevice_notifier_dev_net(priv->netdev,
4664 &tc->netdevice_nb,
4665 &tc->netdevice_nn);
4d8fcf21 4666
d2faae25 4667 mutex_destroy(&tc->mod_hdr.lock);
b32accda
VB		 4668 mutex_destroy(&tc->hairpin_tbl_lock);
4669
d9ee0491 4670 rhashtable_destroy(&tc->ht);
e8f887ac 4671
acff797c
MG		 4672 if (!IS_ERR_OR_NULL(tc->t)) {
4673 mlx5_destroy_flow_table(tc->t);
4674 tc->t = NULL;
e8f887ac 4675 }
b6fac0b4 4676 mutex_destroy(&tc->t_lock);
e8f887ac 4677}
655dc3d2
OG		 4678
4679int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4680{
0a7fcb78
PB		 4681 const size_t sz_enc_opts = sizeof(struct flow_dissector_key_enc_opts);
4682 struct mlx5_rep_uplink_priv *uplink_priv;
4683 struct mlx5e_rep_priv *priv;
4684 struct mapping_ctx *mapping;
4685 int err;
4686
4687 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4688 priv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4689
4c3844d9
PB		 4690 err = mlx5_tc_ct_init(uplink_priv);
4691 if (err)
4692 goto err_ct;
4693
0a7fcb78
PB		 4694 mapping = mapping_create(sizeof(struct tunnel_match_key),
4695 TUNNEL_INFO_BITS_MASK, true);
4696 if (IS_ERR(mapping)) {
4697 err = PTR_ERR(mapping);
4698 goto err_tun_mapping;
4699 }
4700 uplink_priv->tunnel_mapping = mapping;
4701
4702 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
4703 if (IS_ERR(mapping)) {
4704 err = PTR_ERR(mapping);
4705 goto err_enc_opts_mapping;
4706 }
4707 uplink_priv->tunnel_enc_opts_mapping = mapping;
4708
4709 err = rhashtable_init(tc_ht, &tc_ht_params);
4710 if (err)
4711 goto err_ht_init;
4712
4713 return err;
4714
4715err_ht_init:
4716 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4717err_enc_opts_mapping:
4718 mapping_destroy(uplink_priv->tunnel_mapping);
4719err_tun_mapping:
4c3844d9
PB		 4720 mlx5_tc_ct_clean(uplink_priv);
4721err_ct:
0a7fcb78
PB		 4722 netdev_warn(priv->netdev,
4723 "Failed to initialize tc (eswitch), err: %d", err);
4724 return err;
655dc3d2
OG		 4725}
4726
4727void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4728{
0a7fcb78
PB		 4729 struct mlx5_rep_uplink_priv *uplink_priv;
4730
655dc3d2 4731 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
0a7fcb78
PB		 4732
4733 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4734 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4735 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9
PB		 4736
4737 mlx5_tc_ct_clean(uplink_priv);
655dc3d2 4738}
01252a27 4739
226f2ca3 4740int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4741{
d9ee0491 4742 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4743
4744 return atomic_read(&tc_ht->nelems);
4745}
04de7dda
RD		 4746
4747void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4748{
4749 struct mlx5e_tc_flow *flow, *tmp;
4750
4751 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4752 __mlx5e_tc_del_fdb_peer_flow(flow);
4753}
b4a23329
RD		 4754
4755void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4756{
4757 struct mlx5_rep_uplink_priv *rpriv =
4758 container_of(work, struct mlx5_rep_uplink_priv,
4759 reoffload_flows_work);
4760 struct mlx5e_tc_flow *flow, *tmp;
4761
ad86755b 4762 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4763 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4764 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4765 unready_flow_del(flow);
b4a23329 4766 }
ad86755b 4767 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4768}
d6d27782 4769
b8ce9037
PB		 4770#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
4771static bool mlx5e_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
4772 struct mlx5e_tc_update_priv *tc_priv,
4773 u32 tunnel_id)
4774{
4775 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4776 struct flow_dissector_key_enc_opts enc_opts = {};
4777 struct mlx5_rep_uplink_priv *uplink_priv;
4778 struct mlx5e_rep_priv *uplink_rpriv;
4779 struct metadata_dst *tun_dst;
4780 struct tunnel_match_key key;
4781 u32 tun_id, enc_opts_id;
4782 struct net_device *dev;
4783 int err;
4784
4785 enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
4786 tun_id = tunnel_id >> ENC_OPTS_BITS;
4787
4788 if (!tun_id)
4789 return true;
4790
4791 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4792 uplink_priv = &uplink_rpriv->uplink_priv;
4793
4794 err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
4795 if (err) {
4796 WARN_ON_ONCE(true);
4797 netdev_dbg(priv->netdev,
4798 "Couldn't find tunnel for tun_id: %d, err: %d\n",
4799 tun_id, err);
4800 return false;
4801 }
4802
4803 if (enc_opts_id) {
4804 err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
4805 enc_opts_id, &enc_opts);
4806 if (err) {
4807 netdev_dbg(priv->netdev,
4808 "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
4809 enc_opts_id, err);
4810 return false;
4811 }
4812 }
4813
4814 tun_dst = tun_rx_dst(enc_opts.len);
4815 if (!tun_dst) {
4816 WARN_ON_ONCE(true);
4817 return false;
4818 }
4819
4820 ip_tunnel_key_init(&tun_dst->u.tun_info.key,
4821 key.enc_ipv4.src, key.enc_ipv4.dst,
4822 key.enc_ip.tos, key.enc_ip.ttl,
4823 0, /* label */
4824 key.enc_tp.src, key.enc_tp.dst,
4825 key32_to_tunnel_id(key.enc_key_id.keyid),
4826 TUNNEL_KEY);
4827
4828 if (enc_opts.len)
4829 ip_tunnel_info_opts_set(&tun_dst->u.tun_info, enc_opts.data,
4830 enc_opts.len, enc_opts.dst_opt_type);
4831
4832 skb_dst_set(skb, (struct dst_entry *)tun_dst);
4833 dev = dev_get_by_index(&init_net, key.filter_ifindex);
4834 if (!dev) {
4835 netdev_dbg(priv->netdev,
4836 "Couldn't find tunnel device with ifindex: %d\n",
4837 key.filter_ifindex);
4838 return false;
4839 }
4840
4841 /* Set tun_dev so we do dev_put() after datapath */
4842 tc_priv->tun_dev = dev;
4843
4844 skb->dev = dev;
4845
4846 return true;
4847}
4848#endif /* CONFIG_NET_TC_SKB_EXT */
4849
d6d27782 4850bool mlx5e_tc_rep_update_skb(struct mlx5_cqe64 *cqe,
b8ce9037
PB		 4851 struct sk_buff *skb,
4852 struct mlx5e_tc_update_priv *tc_priv)
d6d27782
PB		 4853{
4854#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
5c6b9460
PB		 4855 u32 chain = 0, reg_c0, reg_c1, tunnel_id, tuple_id;
4856 struct mlx5_rep_uplink_priv *uplink_priv;
4857 struct mlx5e_rep_priv *uplink_rpriv;
d6d27782
PB		 4858 struct tc_skb_ext *tc_skb_ext;
4859 struct mlx5_eswitch *esw;
4860 struct mlx5e_priv *priv;
b8ce9037 4861 int tunnel_moffset;
d6d27782
PB		 4862 int err;
4863
4864 reg_c0 = (be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK);
4865 if (reg_c0 == MLX5_FS_DEFAULT_FLOW_TAG)
4866 reg_c0 = 0;
b8ce9037 4867 reg_c1 = be32_to_cpu(cqe->imm_inval_pkey);
d6d27782
PB		 4868
4869 if (!reg_c0)
4870 return true;
4871
4872 priv = netdev_priv(skb->dev);
4873 esw = priv->mdev->priv.eswitch;
4874
4875 err = mlx5_eswitch_get_chain_for_tag(esw, reg_c0, &chain);
4876 if (err) {
4877 netdev_dbg(priv->netdev,
4878 "Couldn't find chain for chain tag: %d, err: %d\n",
4879 reg_c0, err);
4880 return false;
4881 }
4882
b8ce9037
PB		 4883 if (chain) {
4884 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
4885 if (!tc_skb_ext) {
4886 WARN_ON(1);
4887 return false;
4888 }
d6d27782 4889
b8ce9037 4890 tc_skb_ext->chain = chain;
5c6b9460
PB		 4891
4892 tuple_id = reg_c1 & TUPLE_ID_MAX;
4893
4894 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4895 uplink_priv = &uplink_rpriv->uplink_priv;
4896 if (!mlx5e_tc_ct_restore_flow(uplink_priv, skb, tuple_id))
4897 return false;
d6d27782
PB		 4898 }
4899
b8ce9037
PB		 4900 tunnel_moffset = mlx5e_tc_attr_to_reg_mappings[TUNNEL_TO_REG].moffset;
4901 tunnel_id = reg_c1 >> (8 * tunnel_moffset);
4902 return mlx5e_restore_tunnel(priv, skb, tc_priv, tunnel_id);
d6d27782
PB		 4903#endif /* CONFIG_NET_TC_SKB_EXT */
4904
4905 return true;
4906}
b8ce9037
PB		 4907
4908void mlx5_tc_rep_post_napi_receive(struct mlx5e_tc_update_priv *tc_priv)
4909{
4910 if (tc_priv->tun_dev)
4911 dev_put(tc_priv->tun_dev);
4912}
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