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e586b3b0 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include "en.h" | |
34 | ||
35 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq) | |
36 | { | |
37 | struct mlx5_cqwq *wq = &cq->wq; | |
38 | u32 ci = mlx5_cqwq_get_ci(wq); | |
39 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci); | |
40 | int cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK; | |
41 | int sw_ownership_val = mlx5_cqwq_get_wrap_cnt(wq) & 1; | |
42 | ||
43 | if (cqe_ownership_bit != sw_ownership_val) | |
44 | return NULL; | |
45 | ||
e586b3b0 AV |
46 | /* ensure cqe content is read after cqe ownership bit */ |
47 | rmb(); | |
48 | ||
49 | return cqe; | |
50 | } | |
51 | ||
d3c9bc27 TT |
52 | static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq) |
53 | { | |
6e8dd6d6 | 54 | struct mlx5e_sq *sq = container_of(cq, struct mlx5e_sq, cq); |
d3c9bc27 TT |
55 | struct mlx5_wq_cyc *wq; |
56 | struct mlx5_cqe64 *cqe; | |
d3c9bc27 TT |
57 | u16 sqcc; |
58 | ||
c0f1147d | 59 | if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) |
6e8dd6d6 SM |
60 | return; |
61 | ||
d3c9bc27 TT |
62 | cqe = mlx5e_get_cqe(cq); |
63 | if (likely(!cqe)) | |
64 | return; | |
65 | ||
d3c9bc27 TT |
66 | wq = &sq->wq; |
67 | ||
68 | /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), | |
69 | * otherwise a cq overrun may occur | |
70 | */ | |
71 | sqcc = sq->cc; | |
72 | ||
73 | do { | |
74 | u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; | |
b5503b99 | 75 | struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; |
d3c9bc27 TT |
76 | |
77 | mlx5_cqwq_pop(&cq->wq); | |
78 | sqcc += icowi->num_wqebbs; | |
79 | ||
80 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { | |
81 | WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n", | |
82 | cqe->op_own); | |
83 | break; | |
84 | } | |
85 | ||
86 | switch (icowi->opcode) { | |
87 | case MLX5_OPCODE_NOP: | |
88 | break; | |
bc77b240 | 89 | case MLX5_OPCODE_UMR: |
7e426671 | 90 | mlx5e_post_rx_mpwqe(&sq->channel->rq); |
bc77b240 | 91 | break; |
d3c9bc27 TT |
92 | default: |
93 | WARN_ONCE(true, | |
94 | "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n", | |
95 | icowi->opcode); | |
96 | } | |
97 | ||
98 | } while ((cqe = mlx5e_get_cqe(cq))); | |
99 | ||
100 | mlx5_cqwq_update_db_record(&cq->wq); | |
101 | ||
102 | /* ensure cq space is freed before enabling more cqes */ | |
103 | wmb(); | |
104 | ||
105 | sq->cc = sqcc; | |
106 | } | |
107 | ||
b5503b99 SM |
108 | static inline bool mlx5e_poll_xdp_tx_cq(struct mlx5e_cq *cq) |
109 | { | |
110 | struct mlx5e_sq *sq; | |
111 | u16 sqcc; | |
112 | int i; | |
113 | ||
114 | sq = container_of(cq, struct mlx5e_sq, cq); | |
115 | ||
c0f1147d | 116 | if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) |
b5503b99 SM |
117 | return false; |
118 | ||
119 | /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), | |
120 | * otherwise a cq overrun may occur | |
121 | */ | |
122 | sqcc = sq->cc; | |
123 | ||
124 | for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) { | |
125 | struct mlx5_cqe64 *cqe; | |
126 | u16 wqe_counter; | |
127 | bool last_wqe; | |
128 | ||
129 | cqe = mlx5e_get_cqe(cq); | |
130 | if (!cqe) | |
131 | break; | |
132 | ||
133 | mlx5_cqwq_pop(&cq->wq); | |
134 | ||
135 | wqe_counter = be16_to_cpu(cqe->wqe_counter); | |
136 | ||
137 | do { | |
138 | struct mlx5e_sq_wqe_info *wi; | |
139 | struct mlx5e_dma_info *di; | |
140 | u16 ci; | |
141 | ||
142 | last_wqe = (sqcc == wqe_counter); | |
143 | ||
144 | ci = sqcc & sq->wq.sz_m1; | |
145 | di = &sq->db.xdp.di[ci]; | |
146 | wi = &sq->db.xdp.wqe_info[ci]; | |
147 | ||
148 | if (unlikely(wi->opcode == MLX5_OPCODE_NOP)) { | |
149 | sqcc++; | |
150 | continue; | |
151 | } | |
152 | ||
153 | sqcc += wi->num_wqebbs; | |
154 | /* Recycle RX page */ | |
155 | mlx5e_page_release(&sq->channel->rq, di, true); | |
156 | } while (!last_wqe); | |
157 | } | |
158 | ||
159 | mlx5_cqwq_update_db_record(&cq->wq); | |
160 | ||
161 | /* ensure cq space is freed before enabling more cqes */ | |
162 | wmb(); | |
163 | ||
164 | sq->cc = sqcc; | |
165 | return (i == MLX5E_TX_CQ_POLL_BUDGET); | |
166 | } | |
167 | ||
e586b3b0 AV |
168 | int mlx5e_napi_poll(struct napi_struct *napi, int budget) |
169 | { | |
170 | struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel, | |
171 | napi); | |
172 | bool busy = false; | |
44fb6fbb | 173 | int work_done; |
e586b3b0 AV |
174 | int i; |
175 | ||
176 | clear_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags); | |
177 | ||
178 | for (i = 0; i < c->num_tc; i++) | |
8ec736e5 | 179 | busy |= mlx5e_poll_tx_cq(&c->sq[i].cq, budget); |
e586b3b0 | 180 | |
44fb6fbb ED |
181 | work_done = mlx5e_poll_rx_cq(&c->rq.cq, budget); |
182 | busy |= work_done == budget; | |
d3c9bc27 | 183 | |
b5503b99 SM |
184 | if (c->xdp) |
185 | busy |= mlx5e_poll_xdp_tx_cq(&c->xdp_sq.cq); | |
186 | ||
d3c9bc27 TT |
187 | mlx5e_poll_ico_cq(&c->icosq.cq); |
188 | ||
e3391054 | 189 | busy |= mlx5e_post_rx_wqes(&c->rq); |
e586b3b0 AV |
190 | |
191 | if (busy) | |
192 | return budget; | |
193 | ||
44fb6fbb | 194 | napi_complete_done(napi, work_done); |
e586b3b0 AV |
195 | |
196 | /* avoid losing completion event during/after polling cqs */ | |
197 | if (test_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags)) { | |
198 | napi_schedule(napi); | |
44fb6fbb | 199 | return work_done; |
e586b3b0 AV |
200 | } |
201 | ||
202 | for (i = 0; i < c->num_tc; i++) | |
203 | mlx5e_cq_arm(&c->sq[i].cq); | |
cb3c7fd4 GR |
204 | |
205 | if (test_bit(MLX5E_RQ_STATE_AM, &c->rq.state)) | |
206 | mlx5e_rx_am(&c->rq); | |
207 | ||
e586b3b0 | 208 | mlx5e_cq_arm(&c->rq.cq); |
d3c9bc27 | 209 | mlx5e_cq_arm(&c->icosq.cq); |
e586b3b0 | 210 | |
44fb6fbb | 211 | return work_done; |
e586b3b0 AV |
212 | } |
213 | ||
214 | void mlx5e_completion_event(struct mlx5_core_cq *mcq) | |
215 | { | |
216 | struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq); | |
217 | ||
cb3c7fd4 | 218 | cq->event_ctr++; |
e586b3b0 | 219 | set_bit(MLX5E_CHANNEL_NAPI_SCHED, &cq->channel->flags); |
e586b3b0 AV |
220 | napi_schedule(cq->napi); |
221 | } | |
222 | ||
223 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event) | |
224 | { | |
225 | struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq); | |
226 | struct mlx5e_channel *c = cq->channel; | |
227 | struct mlx5e_priv *priv = c->priv; | |
228 | struct net_device *netdev = priv->netdev; | |
229 | ||
230 | netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n", | |
231 | __func__, mcq->cqn, event); | |
232 | } |