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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
525e84be | 38 | #include <linux/atomic.h> |
84ae9c1f | 39 | #include <linux/xarray.h> |
feae9087 | 40 | #include <net/devlink.h> |
073bb189 | 41 | #include <linux/mlx5/device.h> |
57cbd893 | 42 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 43 | #include <linux/mlx5/vport.h> |
cc495188 | 44 | #include <linux/mlx5/fs.h> |
eeb66cdb | 45 | #include "lib/mpfs.h" |
ae430332 | 46 | #include "lib/fs_chains.h" |
d7f33a45 | 47 | #include "sf/sf.h" |
4c3844d9 | 48 | #include "en/tc_ct.h" |
41c2fd94 | 49 | #include "esw/sample.h" |
073bb189 | 50 | |
a91d98a0 CM |
51 | enum mlx5_mapped_obj_type { |
52 | MLX5_MAPPED_OBJ_CHAIN, | |
be9dc004 | 53 | MLX5_MAPPED_OBJ_SAMPLE, |
a91d98a0 CM |
54 | }; |
55 | ||
56 | struct mlx5_mapped_obj { | |
57 | enum mlx5_mapped_obj_type type; | |
58 | union { | |
59 | u32 chain; | |
be9dc004 CM |
60 | struct { |
61 | u32 group_id; | |
62 | u32 rate; | |
63 | u32 trunc_size; | |
64 | } sample; | |
a91d98a0 CM |
65 | }; |
66 | }; | |
67 | ||
e80541ec SM |
68 | #ifdef CONFIG_MLX5_ESWITCH |
69 | ||
87dac697 JL |
70 | #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 |
71 | ||
073bb189 SM |
72 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
73 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
74 | ||
75 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
76 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
77 | ||
c9497c98 MHY |
78 | #define MLX5_MIN_BW_SHARE 1 |
79 | ||
80 | #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \ | |
81 | min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit) | |
82 | ||
a842dd04 CM |
83 | #define mlx5_esw_has_fwd_fdb(dev) \ |
84 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
85 | ||
ae430332 AL |
86 | #define esw_chains(esw) \ |
87 | ((esw)->fdb_table.offloads.esw_chains_priv) | |
88 | ||
5742df0f MHY |
89 | struct vport_ingress { |
90 | struct mlx5_flow_table *acl; | |
10652f39 | 91 | struct mlx5_flow_handle *allow_rule; |
853b5352 | 92 | struct { |
10652f39 PP |
93 | struct mlx5_flow_group *allow_spoofchk_only_grp; |
94 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
95 | struct mlx5_flow_group *allow_untagged_only_grp; | |
96 | struct mlx5_flow_group *drop_grp; | |
853b5352 PP |
97 | struct mlx5_flow_handle *drop_rule; |
98 | struct mlx5_fc *drop_counter; | |
99 | } legacy; | |
d68316b5 | 100 | struct { |
b7826076 PP |
101 | /* Optional group to add an FTE to do internal priority |
102 | * tagging on ingress packets. | |
103 | */ | |
104 | struct mlx5_flow_group *metadata_prio_tag_grp; | |
105 | /* Group to add default match-all FTE entry to tag ingress | |
106 | * packet with metadata. | |
107 | */ | |
108 | struct mlx5_flow_group *metadata_allmatch_grp; | |
d68316b5 PP |
109 | struct mlx5_modify_hdr *modify_metadata; |
110 | struct mlx5_flow_handle *modify_metadata_rule; | |
111 | } offloads; | |
5742df0f MHY |
112 | }; |
113 | ||
114 | struct vport_egress { | |
115 | struct mlx5_flow_table *acl; | |
74491de9 | 116 | struct mlx5_flow_handle *allowed_vlan; |
ea651a86 | 117 | struct mlx5_flow_group *vlan_grp; |
bf773dc0 VP |
118 | union { |
119 | struct { | |
120 | struct mlx5_flow_group *drop_grp; | |
121 | struct mlx5_flow_handle *drop_rule; | |
122 | struct mlx5_fc *drop_counter; | |
123 | } legacy; | |
124 | struct { | |
125 | struct mlx5_flow_group *fwd_grp; | |
126 | struct mlx5_flow_handle *fwd_rule; | |
127 | } offloads; | |
128 | }; | |
b8a0dbe3 EE |
129 | }; |
130 | ||
131 | struct mlx5_vport_drop_stats { | |
132 | u64 rx_dropped; | |
133 | u64 tx_dropped; | |
5742df0f MHY |
134 | }; |
135 | ||
1ab2068a MHY |
136 | struct mlx5_vport_info { |
137 | u8 mac[ETH_ALEN]; | |
138 | u16 vlan; | |
1ab2068a MHY |
139 | u64 node_guid; |
140 | int link_state; | |
cadb129f PP |
141 | u8 qos; |
142 | u8 spoofchk: 1; | |
143 | u8 trusted: 1; | |
1ab2068a MHY |
144 | }; |
145 | ||
5019833d PP |
146 | /* Vport context events */ |
147 | enum mlx5_eswitch_vport_event { | |
148 | MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), | |
149 | MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), | |
150 | MLX5_VPORT_PROMISC_CHANGE = BIT(3), | |
151 | }; | |
152 | ||
073bb189 SM |
153 | struct mlx5_vport { |
154 | struct mlx5_core_dev *dev; | |
073bb189 | 155 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; |
81848731 | 156 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
157 | struct mlx5_flow_handle *promisc_rule; |
158 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
159 | struct work_struct vport_change_handler; |
160 | ||
5742df0f MHY |
161 | struct vport_ingress ingress; |
162 | struct vport_egress egress; | |
133dcfc5 VP |
163 | u32 default_metadata; |
164 | u32 metadata; | |
5742df0f | 165 | |
1ab2068a MHY |
166 | struct mlx5_vport_info info; |
167 | ||
1bd27b11 MHY |
168 | struct { |
169 | bool enabled; | |
170 | u32 esw_tsar_ix; | |
c9497c98 | 171 | u32 bw_share; |
e591605f PP |
172 | u32 min_rate; |
173 | u32 max_rate; | |
1bd27b11 MHY |
174 | } qos; |
175 | ||
6308a5f0 | 176 | u16 vport; |
073bb189 | 177 | bool enabled; |
5019833d | 178 | enum mlx5_eswitch_vport_event enabled_events; |
47dd7e60 | 179 | int index; |
c7eddc60 | 180 | struct devlink_port *dl_port; |
073bb189 SM |
181 | }; |
182 | ||
34ca6535 VB |
183 | struct mlx5_esw_indir_table; |
184 | ||
81848731 | 185 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
186 | union { |
187 | struct legacy_fdb { | |
52fff327 | 188 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
189 | struct mlx5_flow_group *addr_grp; |
190 | struct mlx5_flow_group *allmulti_grp; | |
191 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
192 | struct mlx5_flow_table *vepa_fdb; |
193 | struct mlx5_flow_handle *vepa_uplink_rule; | |
194 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 195 | } legacy; |
69697b6e OG |
196 | |
197 | struct offloads_fdb { | |
8463daf1 | 198 | struct mlx5_flow_namespace *ns; |
ec3be887 | 199 | struct mlx5_flow_table *tc_miss_table; |
52fff327 | 200 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 201 | struct mlx5_flow_group *send_to_vport_grp; |
8e404fef | 202 | struct mlx5_flow_group *send_to_vport_meta_grp; |
ac004b83 RD |
203 | struct mlx5_flow_group *peer_miss_grp; |
204 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 205 | struct mlx5_flow_group *miss_grp; |
8e404fef | 206 | struct mlx5_flow_handle **send_to_vport_meta_rules; |
f80be543 MB |
207 | struct mlx5_flow_handle *miss_rule_uni; |
208 | struct mlx5_flow_handle *miss_rule_multi; | |
f5f82476 | 209 | int vlan_push_pop_refcount; |
e52c2802 | 210 | |
ae430332 | 211 | struct mlx5_fs_chains *esw_chains_priv; |
96e32687 EC |
212 | struct { |
213 | DECLARE_HASHTABLE(table, 8); | |
214 | /* Protects vports.table */ | |
215 | struct mutex lock; | |
216 | } vports; | |
217 | ||
34ca6535 VB |
218 | struct mlx5_esw_indir_table *indir; |
219 | ||
69697b6e | 220 | } offloads; |
6ab36e35 | 221 | }; |
e52c2802 | 222 | u32 flags; |
6ab36e35 OG |
223 | }; |
224 | ||
c116c6ee | 225 | struct mlx5_esw_offload { |
11b717d6 PB |
226 | struct mlx5_flow_table *ft_offloads_restore; |
227 | struct mlx5_flow_group *restore_group; | |
6724e66b | 228 | struct mlx5_modify_hdr *restore_copy_hdr_id; |
c9355682 | 229 | struct mapping_ctx *reg_c0_obj_pool; |
11b717d6 | 230 | |
c116c6ee | 231 | struct mlx5_flow_table *ft_offloads; |
fed9ce22 | 232 | struct mlx5_flow_group *vport_rx_group; |
47dd7e60 | 233 | struct xarray vport_reps; |
04de7dda RD |
234 | struct list_head peer_flows; |
235 | struct mutex peer_mutex; | |
61086f39 | 236 | struct mutex encap_tbl_lock; /* protects encap_tbl */ |
a54e20b4 | 237 | DECLARE_HASHTABLE(encap_tbl, 8); |
14e6b038 EC |
238 | struct mutex decap_tbl_lock; /* protects decap_tbl */ |
239 | DECLARE_HASHTABLE(decap_tbl, 8); | |
dd58edc3 | 240 | struct mod_hdr_tbl mod_hdr; |
10caabda OS |
241 | DECLARE_HASHTABLE(termtbl_tbl, 8); |
242 | struct mutex termtbl_mutex; /* protects termtbl hash */ | |
84ae9c1f | 243 | struct xarray vhca_map; |
8693115a | 244 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 245 | u8 inline_mode; |
525e84be | 246 | atomic64_t num_flows; |
98fdbea5 | 247 | enum devlink_eswitch_encap_mode encap; |
133dcfc5 | 248 | struct ida vport_metadata_ida; |
a53cf949 | 249 | unsigned int host_number; /* ECPF supports one external host */ |
c116c6ee OG |
250 | }; |
251 | ||
0a0ab1d2 EC |
252 | /* E-Switch MC FDB table hash node */ |
253 | struct esw_mc_addr { /* SRIOV only */ | |
254 | struct l2addr_node node; | |
255 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
256 | u32 refcnt; | |
257 | }; | |
258 | ||
a3888f33 BW |
259 | struct mlx5_host_work { |
260 | struct work_struct work; | |
261 | struct mlx5_eswitch *esw; | |
262 | }; | |
263 | ||
cd56f929 | 264 | struct mlx5_esw_functions { |
a3888f33 BW |
265 | struct mlx5_nb nb; |
266 | u16 num_vfs; | |
267 | }; | |
268 | ||
7445cfb1 JL |
269 | enum { |
270 | MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), | |
5b7cb745 | 271 | MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1), |
7445cfb1 JL |
272 | }; |
273 | ||
073bb189 SM |
274 | struct mlx5_eswitch { |
275 | struct mlx5_core_dev *dev; | |
6933a937 | 276 | struct mlx5_nb nb; |
81848731 | 277 | struct mlx5_eswitch_fdb fdb_table; |
99ecd646 | 278 | /* legacy data structures */ |
81848731 | 279 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; |
131ce701 PP |
280 | struct esw_mc_addr mc_promisc; |
281 | /* end of legacy */ | |
073bb189 | 282 | struct workqueue_struct *work_queue; |
47dd7e60 | 283 | struct xarray vports; |
7445cfb1 | 284 | u32 flags; |
073bb189 | 285 | int total_vports; |
81848731 | 286 | int enabled_vports; |
dfcb1ed3 MHY |
287 | /* Synchronize between vport change events |
288 | * and async SRIOV admin state changes | |
289 | */ | |
290 | struct mutex state_lock; | |
1bd27b11 | 291 | |
8e0aa4bc PP |
292 | /* Protects eswitch mode change that occurs via one or more |
293 | * user commands, i.e. sriov state change, devlink commands. | |
294 | */ | |
c55479d0 | 295 | struct rw_semaphore mode_lock; |
7dc84de9 | 296 | atomic64_t user_count; |
8e0aa4bc | 297 | |
1bd27b11 MHY |
298 | struct { |
299 | bool enabled; | |
300 | u32 root_tsar_id; | |
301 | } qos; | |
302 | ||
c116c6ee | 303 | struct mlx5_esw_offload offloads; |
6ab36e35 | 304 | int mode; |
a1b3839a | 305 | u16 manager_vport; |
411ec9e0 | 306 | u16 first_host_vport; |
cd56f929 | 307 | struct mlx5_esw_functions esw_funcs; |
87dac697 JL |
308 | struct { |
309 | u32 large_group_num; | |
310 | } params; | |
8f010541 | 311 | struct blocking_notifier_head n_head; |
073bb189 SM |
312 | }; |
313 | ||
5896b972 PP |
314 | void esw_offloads_disable(struct mlx5_eswitch *esw); |
315 | int esw_offloads_enable(struct mlx5_eswitch *esw); | |
e8d31c4d MB |
316 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw); |
317 | int esw_offloads_init_reps(struct mlx5_eswitch *esw); | |
ea651a86 | 318 | |
7bf481d7 PP |
319 | bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw); |
320 | int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable); | |
133dcfc5 VP |
321 | u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw); |
322 | void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata); | |
323 | ||
fcb64c0f EC |
324 | int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, |
325 | u32 rate_mbps); | |
766a0e97 | 326 | |
073bb189 SM |
327 | /* E-Switch API */ |
328 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
329 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
ebf77bb8 PP |
330 | |
331 | #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1) | |
8e0aa4bc PP |
332 | int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int mode, int num_vfs); |
333 | int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs); | |
334 | void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw, bool clear_vf); | |
556b9d16 | 335 | void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf); |
77256579 | 336 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
fa997825 | 337 | u16 vport, const u8 *mac); |
77256579 | 338 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, |
02f3afd9 | 339 | u16 vport, int link_state); |
9e7ea352 | 340 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 341 | u16 vport, u16 vlan, u8 qos); |
f942380c | 342 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
02f3afd9 | 343 | u16 vport, bool spoofchk); |
1edc57e2 | 344 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
02f3afd9 PP |
345 | u16 vport_num, bool setting); |
346 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, | |
c9497c98 | 347 | u32 max_rate, u32 min_rate); |
8da202b2 HN |
348 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
349 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 | 350 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
02f3afd9 | 351 | u16 vport, struct ifla_vf_info *ivi); |
3b751a2a | 352 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
02f3afd9 | 353 | u16 vport, |
3b751a2a | 354 | struct ifla_vf_stats *vf_stats); |
159fe639 | 355 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 356 | |
238302fa | 357 | int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport, |
e08a6832 | 358 | bool other_vport, void *in); |
57843868 | 359 | |
3d80d1a2 | 360 | struct mlx5_flow_spec; |
776b12b6 | 361 | struct mlx5_esw_flow_attr; |
10caabda OS |
362 | struct mlx5_termtbl_handle; |
363 | ||
364 | bool | |
365 | mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, | |
c620b772 | 366 | struct mlx5_flow_attr *attr, |
10caabda OS |
367 | struct mlx5_flow_act *flow_act, |
368 | struct mlx5_flow_spec *spec); | |
369 | ||
370 | struct mlx5_flow_handle * | |
371 | mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, | |
372 | struct mlx5_flow_table *ft, | |
373 | struct mlx5_flow_spec *spec, | |
374 | struct mlx5_esw_flow_attr *attr, | |
375 | struct mlx5_flow_act *flow_act, | |
376 | struct mlx5_flow_destination *dest, | |
377 | int num_dest); | |
378 | ||
379 | void | |
380 | mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, | |
381 | struct mlx5_termtbl_handle *tt); | |
3d80d1a2 | 382 | |
f94d6389 CM |
383 | void |
384 | mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec); | |
385 | ||
74491de9 | 386 | struct mlx5_flow_handle * |
3d80d1a2 OG |
387 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
388 | struct mlx5_flow_spec *spec, | |
c620b772 | 389 | struct mlx5_flow_attr *attr); |
e4ad91f2 CM |
390 | struct mlx5_flow_handle * |
391 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
392 | struct mlx5_flow_spec *spec, | |
c620b772 | 393 | struct mlx5_flow_attr *attr); |
d85cdccb OG |
394 | void |
395 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
396 | struct mlx5_flow_handle *rule, | |
c620b772 | 397 | struct mlx5_flow_attr *attr); |
48265006 OG |
398 | void |
399 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
400 | struct mlx5_flow_handle *rule, | |
c620b772 | 401 | struct mlx5_flow_attr *attr); |
d85cdccb | 402 | |
74491de9 | 403 | struct mlx5_flow_handle * |
02f3afd9 | 404 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 405 | struct mlx5_flow_destination *dest); |
fed9ce22 | 406 | |
e33dfe31 OG |
407 | enum { |
408 | SET_VLAN_STRIP = BIT(0), | |
409 | SET_VLAN_INSERT = BIT(1) | |
410 | }; | |
411 | ||
d708f902 OG |
412 | enum mlx5_flow_match_level { |
413 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
414 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
415 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
416 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
417 | }; | |
418 | ||
592d3651 CM |
419 | /* current maximum for flow based vport multicasting */ |
420 | #define MLX5_MAX_FLOW_FWD_VPORTS 2 | |
421 | ||
f493f155 EB |
422 | enum { |
423 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 424 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
10742efc | 425 | MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE = BIT(2), |
f493f155 EB |
426 | }; |
427 | ||
39ac237c PB |
428 | enum { |
429 | MLX5_ESW_ATTR_FLAG_VLAN_HANDLED = BIT(0), | |
430 | MLX5_ESW_ATTR_FLAG_SLOW_PATH = BIT(1), | |
6fb0701a | 431 | MLX5_ESW_ATTR_FLAG_NO_IN_PORT = BIT(2), |
10742efc | 432 | MLX5_ESW_ATTR_FLAG_SRC_REWRITE = BIT(3), |
f94d6389 | 433 | MLX5_ESW_ATTR_FLAG_SAMPLE = BIT(4), |
39ac237c PB |
434 | }; |
435 | ||
776b12b6 OG |
436 | struct mlx5_esw_flow_attr { |
437 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 438 | struct mlx5_core_dev *in_mdev; |
f9392795 | 439 | struct mlx5_core_dev *counter_dev; |
776b12b6 | 440 | |
e85e02ba | 441 | int split_count; |
592d3651 CM |
442 | int out_count; |
443 | ||
cc495188 JL |
444 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
445 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
446 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
447 | u8 total_vlan; | |
df65a573 | 448 | struct { |
f493f155 | 449 | u32 flags; |
df65a573 | 450 | struct mlx5_eswitch_rep *rep; |
2b688ea5 | 451 | struct mlx5_pkt_reformat *pkt_reformat; |
df65a573 | 452 | struct mlx5_core_dev *mdev; |
10caabda | 453 | struct mlx5_termtbl_handle *termtbl; |
8914add2 | 454 | int src_port_rewrite_act_id; |
df65a573 | 455 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
34ca6535 | 456 | struct mlx5_rx_tun_attr *rx_tun_attr; |
14e6b038 | 457 | struct mlx5_pkt_reformat *decap_pkt_reformat; |
41c2fd94 | 458 | struct mlx5_sample_attr *sample; |
776b12b6 OG |
459 | }; |
460 | ||
db7ff19e EB |
461 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
462 | struct netlink_ext_ack *extack); | |
feae9087 | 463 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
464 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
465 | struct netlink_ext_ack *extack); | |
bffaa916 | 466 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
98fdbea5 LR |
467 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
468 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 469 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
470 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
471 | enum devlink_eswitch_encap_mode *encap); | |
f099fde1 PP |
472 | int mlx5_devlink_port_function_hw_addr_get(struct devlink *devlink, |
473 | struct devlink_port *port, | |
474 | u8 *hw_addr, int *hw_addr_len, | |
475 | struct netlink_ext_ack *extack); | |
330077d1 PP |
476 | int mlx5_devlink_port_function_hw_addr_set(struct devlink *devlink, |
477 | struct devlink_port *port, | |
478 | const u8 *hw_addr, int hw_addr_len, | |
479 | struct netlink_ext_ack *extack); | |
f099fde1 | 480 | |
a4b97ab4 | 481 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 482 | |
f5f82476 | 483 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, |
c620b772 | 484 | struct mlx5_flow_attr *attr); |
f5f82476 | 485 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, |
c620b772 | 486 | struct mlx5_flow_attr *attr); |
f5f82476 | 487 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 488 | u16 vport, u16 vlan, u8 qos, u8 set_flags); |
f5f82476 | 489 | |
b5f814cc EC |
490 | static inline bool mlx5_esw_qos_enabled(struct mlx5_eswitch *esw) |
491 | { | |
492 | return esw->qos.enabled; | |
493 | } | |
494 | ||
cc495188 JL |
495 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
496 | u8 vlan_depth) | |
6acfbf38 | 497 | { |
cc495188 JL |
498 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
499 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
500 | ||
501 | if (vlan_depth == 1) | |
502 | return ret; | |
503 | ||
504 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
505 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
506 | } |
507 | ||
eff849b2 RL |
508 | bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, |
509 | struct mlx5_core_dev *dev1); | |
544fe7c2 RD |
510 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
511 | struct mlx5_core_dev *dev1); | |
eff849b2 | 512 | |
dd28087c | 513 | const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); |
cd56f929 | 514 | |
69697b6e OG |
515 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
516 | ||
27b942fb PP |
517 | #define esw_info(__dev, format, ...) \ |
518 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 519 | |
27b942fb PP |
520 | #define esw_warn(__dev, format, ...) \ |
521 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
522 | |
523 | #define esw_debug(dev, format, ...) \ | |
524 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a | 525 | |
b16f2bb6 PP |
526 | static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw) |
527 | { | |
528 | return esw && MLX5_ESWITCH_MANAGER(esw->dev); | |
529 | } | |
530 | ||
a1b3839a BW |
531 | /* The returned number is valid only when the dev is eswitch manager. */ |
532 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
533 | { | |
534 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
535 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
536 | } | |
537 | ||
ea2300e0 PP |
538 | static inline bool |
539 | mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) | |
540 | { | |
541 | return esw->manager_vport == vport_num; | |
542 | } | |
543 | ||
411ec9e0 BW |
544 | static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) |
545 | { | |
546 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
547 | MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; | |
548 | } | |
549 | ||
3d5f41ca | 550 | static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev) |
6706a3b9 | 551 | { |
3d5f41ca | 552 | return mlx5_core_is_ecpf_esw_manager(dev); |
6706a3b9 VP |
553 | } |
554 | ||
443bf36e PP |
555 | static inline unsigned int |
556 | mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, | |
557 | u16 vport_num) | |
558 | { | |
559 | return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num; | |
560 | } | |
561 | ||
f099fde1 PP |
562 | static inline u16 |
563 | mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index) | |
564 | { | |
565 | return dl_port_index & 0xffff; | |
566 | } | |
567 | ||
ee576ec1 SM |
568 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
569 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
570 | ||
47dd7e60 PP |
571 | /* Each mark identifies eswitch vport type. |
572 | * MLX5_ESW_VPT_HOST_FN is used to identify both PF and VF ports using | |
573 | * a single mark. | |
574 | * MLX5_ESW_VPT_VF identifies a SRIOV VF vport. | |
575 | * MLX5_ESW_VPT_SF identifies SF vport. | |
786ef904 | 576 | */ |
47dd7e60 PP |
577 | #define MLX5_ESW_VPT_HOST_FN XA_MARK_0 |
578 | #define MLX5_ESW_VPT_VF XA_MARK_1 | |
579 | #define MLX5_ESW_VPT_SF XA_MARK_2 | |
580 | ||
581 | /* The vport iterator is valid only after vport are initialized in mlx5_eswitch_init. | |
582 | * Borrowed the idea from xa_for_each_marked() but with support for desired last element. | |
786ef904 | 583 | */ |
47dd7e60 PP |
584 | |
585 | #define mlx5_esw_for_each_vport(esw, index, vport) \ | |
586 | xa_for_each(&((esw)->vports), index, vport) | |
587 | ||
588 | #define mlx5_esw_for_each_entry_marked(xa, index, entry, last, filter) \ | |
589 | for (index = 0, entry = xa_find(xa, &index, last, filter); \ | |
590 | entry; entry = xa_find_after(xa, &index, last, filter)) | |
591 | ||
592 | #define mlx5_esw_for_each_vport_marked(esw, index, vport, last, filter) \ | |
593 | mlx5_esw_for_each_entry_marked(&((esw)->vports), index, vport, last, filter) | |
594 | ||
595 | #define mlx5_esw_for_each_vf_vport(esw, index, vport, last) \ | |
596 | mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_VF) | |
597 | ||
598 | #define mlx5_esw_for_each_host_func_vport(esw, index, vport, last) \ | |
599 | mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_HOST_FN) | |
d7f33a45 | 600 | |
bd939753 | 601 | struct mlx5_eswitch *mlx5_devlink_eswitch_get(struct devlink *devlink); |
5d9986a3 BW |
602 | struct mlx5_vport *__must_check |
603 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
604 | ||
47dd7e60 PP |
605 | bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); |
606 | bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
91d6291c | 607 | |
16fff98a | 608 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); |
062f4bf4 | 609 | |
925a6acc | 610 | int |
5019833d PP |
611 | mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, |
612 | enum mlx5_eswitch_vport_event enabled_events); | |
613 | void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); | |
614 | ||
d970812b PP |
615 | int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, u16 vport_num, |
616 | enum mlx5_eswitch_vport_event enabled_events); | |
617 | void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, u16 vport_num); | |
618 | ||
748da30b VP |
619 | int |
620 | esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, | |
621 | struct mlx5_vport *vport); | |
622 | void | |
623 | esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, | |
624 | struct mlx5_vport *vport); | |
625 | ||
c796bb7c CM |
626 | struct esw_vport_tbl_namespace { |
627 | int max_fte; | |
628 | int max_num_groups; | |
629 | u32 flags; | |
630 | }; | |
631 | ||
4c7f4028 CM |
632 | struct mlx5_vport_tbl_attr { |
633 | u16 chain; | |
634 | u16 prio; | |
635 | u16 vport; | |
c796bb7c | 636 | const struct esw_vport_tbl_namespace *vport_ns; |
4c7f4028 CM |
637 | }; |
638 | ||
639 | struct mlx5_flow_table * | |
0a9e2307 | 640 | mlx5_esw_vporttbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); |
4c7f4028 | 641 | void |
0a9e2307 | 642 | mlx5_esw_vporttbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); |
96e32687 | 643 | |
11b717d6 PB |
644 | struct mlx5_flow_handle * |
645 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag); | |
11b717d6 | 646 | |
c2d7712c BW |
647 | int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num); |
648 | void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num); | |
649 | ||
d970812b PP |
650 | int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num); |
651 | void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num); | |
652 | ||
23bb50cf BW |
653 | int mlx5_eswitch_load_vport(struct mlx5_eswitch *esw, u16 vport_num, |
654 | enum mlx5_eswitch_vport_event enabled_events); | |
655 | void mlx5_eswitch_unload_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
656 | ||
657 | int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs, | |
658 | enum mlx5_eswitch_vport_event enabled_events); | |
659 | void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs); | |
660 | ||
c7eddc60 PP |
661 | int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, u16 vport_num); |
662 | void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_eswitch *esw, u16 vport_num); | |
663 | struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num); | |
d970812b PP |
664 | |
665 | int mlx5_esw_devlink_sf_port_register(struct mlx5_eswitch *esw, struct devlink_port *dl_port, | |
f1b9acd3 | 666 | u16 vport_num, u32 controller, u32 sfnum); |
d970812b PP |
667 | void mlx5_esw_devlink_sf_port_unregister(struct mlx5_eswitch *esw, u16 vport_num); |
668 | ||
669 | int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port, | |
f1b9acd3 | 670 | u16 vport_num, u32 controller, u32 sfnum); |
d970812b | 671 | void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num); |
87bd418e | 672 | int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, u16 *sf_base_id); |
d970812b | 673 | |
84ae9c1f VB |
674 | int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num); |
675 | void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num); | |
676 | int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num); | |
677 | ||
8f010541 PP |
678 | /** |
679 | * mlx5_esw_event_info - Indicates eswitch mode changed/changing. | |
680 | * | |
681 | * @new_mode: New mode of eswitch. | |
682 | */ | |
683 | struct mlx5_esw_event_info { | |
684 | u16 new_mode; | |
685 | }; | |
686 | ||
687 | int mlx5_esw_event_notifier_register(struct mlx5_eswitch *esw, struct notifier_block *n); | |
688 | void mlx5_esw_event_notifier_unregister(struct mlx5_eswitch *esw, struct notifier_block *n); | |
7dc84de9 RD |
689 | |
690 | bool mlx5_esw_hold(struct mlx5_core_dev *dev); | |
691 | void mlx5_esw_release(struct mlx5_core_dev *dev); | |
692 | void mlx5_esw_get(struct mlx5_core_dev *dev); | |
693 | void mlx5_esw_put(struct mlx5_core_dev *dev); | |
694 | int mlx5_esw_try_lock(struct mlx5_eswitch *esw); | |
695 | void mlx5_esw_unlock(struct mlx5_eswitch *esw); | |
696 | ||
b55b3538 PP |
697 | void esw_vport_change_handle_locked(struct mlx5_vport *vport); |
698 | ||
f1b9acd3 PP |
699 | bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller); |
700 | ||
e80541ec SM |
701 | #else /* CONFIG_MLX5_ESWITCH */ |
702 | /* eswitch API stubs */ | |
703 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
704 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
8e0aa4bc | 705 | static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; } |
556b9d16 | 706 | static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf) {} |
eff849b2 | 707 | static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; } |
6706a3b9 | 708 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
7d0314b1 RD |
709 | static inline |
710 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; } | |
dd28087c | 711 | static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) |
10ee82ce | 712 | { |
dd28087c | 713 | return ERR_PTR(-EOPNOTSUPP); |
10ee82ce | 714 | } |
328edb49 | 715 | |
9d3faa51 | 716 | static inline struct mlx5_flow_handle * |
11b717d6 PB |
717 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) |
718 | { | |
719 | return ERR_PTR(-EOPNOTSUPP); | |
720 | } | |
5a65d85d RD |
721 | |
722 | static inline unsigned int | |
723 | mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, | |
724 | u16 vport_num) | |
725 | { | |
726 | return vport_num; | |
727 | } | |
e80541ec SM |
728 | #endif /* CONFIG_MLX5_ESWITCH */ |
729 | ||
073bb189 | 730 | #endif /* __MLX5_ESWITCH_H__ */ |