[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / health.c

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/random.h>
#include <linux/vmalloc.h>
#include <linux/hardirq.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/cmd.h>
#include "mlx5_core.h"

enum {
	MLX5_HEALTH_POLL_INTERVAL	= 2 * HZ,
	MAX_MISSES			= 3,
};

enum {
	MLX5_HEALTH_SYNDR_FW_ERR		= 0x1,
	MLX5_HEALTH_SYNDR_IRISC_ERR		= 0x7,
	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR	= 0x8,
	MLX5_HEALTH_SYNDR_CRC_ERR		= 0x9,
	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR		= 0xa,
	MLX5_HEALTH_SYNDR_HW_FTL_ERR		= 0xb,
	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR	= 0xc,
	MLX5_HEALTH_SYNDR_EQ_ERR		= 0xd,
	MLX5_HEALTH_SYNDR_EQ_INV		= 0xe,
	MLX5_HEALTH_SYNDR_FFSER_ERR		= 0xf,
	MLX5_HEALTH_SYNDR_HIGH_TEMP		= 0x10
};

enum {
	MLX5_NIC_IFC_FULL		= 0,
	MLX5_NIC_IFC_DISABLED		= 1,
	MLX5_NIC_IFC_NO_DRAM_NIC	= 2,
	MLX5_NIC_IFC_INVALID		= 3
};

enum {
	MLX5_DROP_NEW_HEALTH_WORK,
	MLX5_DROP_NEW_RECOVERY_WORK,
};

static u8 get_nic_state(struct mlx5_core_dev *dev)
{
	return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 3;
}

static void trigger_cmd_completions(struct mlx5_core_dev *dev)
{
	unsigned long flags;
	u64 vector;

	/* wait for pending handlers to complete */
	synchronize_irq(pci_irq_vector(dev->pdev, MLX5_EQ_VEC_CMD));
	spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
	vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
	if (!vector)
		goto no_trig;

	vector |= MLX5_TRIGGERED_CMD_COMP;
	spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);

	mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
	mlx5_cmd_comp_handler(dev, vector, true);
	return;

no_trig:
	spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
}

static int in_fatal(struct mlx5_core_dev *dev)
{
	struct mlx5_core_health *health = &dev->priv.health;
	struct health_buffer __iomem *h = health->health;

	if (get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
		return 1;

	if (ioread32be(&h->fw_ver) == 0xffffffff)
		return 1;

	return 0;
}

void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force)
{
	mutex_lock(&dev->intf_state_mutex);
	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
		goto unlock;

	mlx5_core_err(dev, "start\n");
	if (pci_channel_offline(dev->pdev) || in_fatal(dev) || force) {
		dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
		trigger_cmd_completions(dev);
	}

	mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 0);
	mlx5_core_err(dev, "end\n");

unlock:
	mutex_unlock(&dev->intf_state_mutex);
}

static void mlx5_handle_bad_state(struct mlx5_core_dev *dev)
{
	u8 nic_interface = get_nic_state(dev);

	switch (nic_interface) {
	case MLX5_NIC_IFC_FULL:
		mlx5_core_warn(dev, "Expected to see disabled NIC but it is full driver\n");
		break;

	case MLX5_NIC_IFC_DISABLED:
		mlx5_core_warn(dev, "starting teardown\n");
		break;

	case MLX5_NIC_IFC_NO_DRAM_NIC:
		mlx5_core_warn(dev, "Expected to see disabled NIC but it is no dram nic\n");
		break;
	default:
		mlx5_core_warn(dev, "Expected to see disabled NIC but it is has invalid value %d\n",
			       nic_interface);
	}

	mlx5_disable_device(dev);
}

static void health_recover(struct work_struct *work)
{
	struct mlx5_core_health *health;
	struct delayed_work *dwork;
	struct mlx5_core_dev *dev;
	struct mlx5_priv *priv;
	u8 nic_state;

	dwork = container_of(work, struct delayed_work, work);
	health = container_of(dwork, struct mlx5_core_health, recover_work);
	priv = container_of(health, struct mlx5_priv, health);
	dev = container_of(priv, struct mlx5_core_dev, priv);

	nic_state = get_nic_state(dev);
	if (nic_state == MLX5_NIC_IFC_INVALID) {
		dev_err(&dev->pdev->dev, "health recovery flow aborted since the nic state is invalid\n");
		return;
	}

	dev_err(&dev->pdev->dev, "starting health recovery flow\n");
	mlx5_recover_device(dev);
}

/* How much time to wait until health resetting the driver (in msecs) */
#define MLX5_RECOVERY_DELAY_MSECS 60000
static void health_care(struct work_struct *work)
{
	unsigned long recover_delay = msecs_to_jiffies(MLX5_RECOVERY_DELAY_MSECS);
	struct mlx5_core_health *health;
	struct mlx5_core_dev *dev;
	struct mlx5_priv *priv;
	unsigned long flags;

	health = container_of(work, struct mlx5_core_health, work);
	priv = container_of(health, struct mlx5_priv, health);
	dev = container_of(priv, struct mlx5_core_dev, priv);
	mlx5_core_warn(dev, "handling bad device here\n");
	mlx5_handle_bad_state(dev);

	spin_lock_irqsave(&health->wq_lock, flags);
	if (!test_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags))
		schedule_delayed_work(&health->recover_work, recover_delay);
	else
		dev_err(&dev->pdev->dev,
			"new health works are not permitted at this stage\n");
	spin_unlock_irqrestore(&health->wq_lock, flags);
}

static const char *hsynd_str(u8 synd)
{
	switch (synd) {
	case MLX5_HEALTH_SYNDR_FW_ERR:
		return "firmware internal error";
	case MLX5_HEALTH_SYNDR_IRISC_ERR:
		return "irisc not responding";
	case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR:
		return "unrecoverable hardware error";
	case MLX5_HEALTH_SYNDR_CRC_ERR:
		return "firmware CRC error";
	case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR:
		return "ICM fetch PCI error";
	case MLX5_HEALTH_SYNDR_HW_FTL_ERR:
		return "HW fatal error\n";
	case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR:
		return "async EQ buffer overrun";
	case MLX5_HEALTH_SYNDR_EQ_ERR:
		return "EQ error";
	case MLX5_HEALTH_SYNDR_EQ_INV:
		return "Invalid EQ referenced";
	case MLX5_HEALTH_SYNDR_FFSER_ERR:
		return "FFSER error";
	case MLX5_HEALTH_SYNDR_HIGH_TEMP:
		return "High temperature";
	default:
		return "unrecognized error";
	}
}

static void print_health_info(struct mlx5_core_dev *dev)
{
	struct mlx5_core_health *health = &dev->priv.health;
	struct health_buffer __iomem *h = health->health;
	char fw_str[18];
	u32 fw;
	int i;

	/* If the syndrome is 0, the device is OK and no need to print buffer */
	if (!ioread8(&h->synd))
		return;

	for (i = 0; i < ARRAY_SIZE(h->assert_var); i++)
		dev_err(&dev->pdev->dev, "assert_var[%d] 0x%08x\n", i, ioread32be(h->assert_var + i));

	dev_err(&dev->pdev->dev, "assert_exit_ptr 0x%08x\n", ioread32be(&h->assert_exit_ptr));
	dev_err(&dev->pdev->dev, "assert_callra 0x%08x\n", ioread32be(&h->assert_callra));
	sprintf(fw_str, "%d.%d.%d", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
	dev_err(&dev->pdev->dev, "fw_ver %s\n", fw_str);
	dev_err(&dev->pdev->dev, "hw_id 0x%08x\n", ioread32be(&h->hw_id));
	dev_err(&dev->pdev->dev, "irisc_index %d\n", ioread8(&h->irisc_index));
	dev_err(&dev->pdev->dev, "synd 0x%x: %s\n", ioread8(&h->synd), hsynd_str(ioread8(&h->synd)));
	dev_err(&dev->pdev->dev, "ext_synd 0x%04x\n", ioread16be(&h->ext_synd));
	fw = ioread32be(&h->fw_ver);
	dev_err(&dev->pdev->dev, "raw fw_ver 0x%08x\n", fw);
}

static unsigned long get_next_poll_jiffies(void)
{
	unsigned long next;

	get_random_bytes(&next, sizeof(next));
	next %= HZ;
	next += jiffies + MLX5_HEALTH_POLL_INTERVAL;

	return next;
}

void mlx5_trigger_health_work(struct mlx5_core_dev *dev)
{
	struct mlx5_core_health *health = &dev->priv.health;
	unsigned long flags;

	spin_lock_irqsave(&health->wq_lock, flags);
	if (!test_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags))
		queue_work(health->wq, &health->work);
	else
		dev_err(&dev->pdev->dev,
			"new health works are not permitted at this stage\n");
	spin_unlock_irqrestore(&health->wq_lock, flags);
}

static void poll_health(struct timer_list *t)
{
	struct mlx5_core_dev *dev = from_timer(dev, t, priv.health.timer);
	struct mlx5_core_health *health = &dev->priv.health;
	u32 count;

	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
		goto out;

	count = ioread32be(health->health_counter);
	if (count == health->prev)
		++health->miss_counter;
	else
		health->miss_counter = 0;

	health->prev = count;
	if (health->miss_counter == MAX_MISSES) {
		dev_err(&dev->pdev->dev, "device's health compromised - reached miss count\n");
		print_health_info(dev);
	}

	if (in_fatal(dev) && !health->sick) {
		health->sick = true;
		print_health_info(dev);
		mlx5_trigger_health_work(dev);
	}

out:
	mod_timer(&health->timer, get_next_poll_jiffies());
}

void mlx5_start_health_poll(struct mlx5_core_dev *dev)
{
	struct mlx5_core_health *health = &dev->priv.health;

	timer_setup(&health->timer, poll_health, 0);
	health->sick = 0;
	clear_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
	clear_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
	health->health = &dev->iseg->health;
	health->health_counter = &dev->iseg->health_counter;

	health->timer.expires = round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL);
	add_timer(&health->timer);
}

void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health)
{
	struct mlx5_core_health *health = &dev->priv.health;
	unsigned long flags;

	if (disable_health) {
		spin_lock_irqsave(&health->wq_lock, flags);
		set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
		set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
		spin_unlock_irqrestore(&health->wq_lock, flags);
	}

	del_timer_sync(&health->timer);
}

void mlx5_drain_health_wq(struct mlx5_core_dev *dev)
{
	struct mlx5_core_health *health = &dev->priv.health;
	unsigned long flags;

	spin_lock_irqsave(&health->wq_lock, flags);
	set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
	set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
	spin_unlock_irqrestore(&health->wq_lock, flags);
	cancel_delayed_work_sync(&health->recover_work);
	cancel_work_sync(&health->work);
}

void mlx5_drain_health_recovery(struct mlx5_core_dev *dev)
{
	struct mlx5_core_health *health = &dev->priv.health;
	unsigned long flags;

	spin_lock_irqsave(&health->wq_lock, flags);
	set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
	spin_unlock_irqrestore(&health->wq_lock, flags);
	cancel_delayed_work_sync(&dev->priv.health.recover_work);
}

void mlx5_health_cleanup(struct mlx5_core_dev *dev)
{
	struct mlx5_core_health *health = &dev->priv.health;

	destroy_workqueue(health->wq);
}

int mlx5_health_init(struct mlx5_core_dev *dev)
{
	struct mlx5_core_health *health;
	char *name;

	health = &dev->priv.health;
	name = kmalloc(64, GFP_KERNEL);
	if (!name)
		return -ENOMEM;

	strcpy(name, "mlx5_health");
	strcat(name, dev_name(&dev->pdev->dev));
	health->wq = create_singlethread_workqueue(name);
	kfree(name);
	if (!health->wq)
		return -ENOMEM;
	spin_lock_init(&health->wq_lock);
	INIT_WORK(&health->work, health_care);
	INIT_DELAYED_WORK(&health->recover_work, health_recover);

	return 0;
}
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/random.h>
	36	#include <linux/vmalloc.h>
89d44f0a	37	#include <linux/hardirq.h>
e126ba97 EC	38	#include <linux/mlx5/driver.h>
	39	#include <linux/mlx5/cmd.h>
	40	#include "mlx5_core.h"
	41
	42	enum {
	43	MLX5_HEALTH_POLL_INTERVAL = 2 * HZ,
	44	MAX_MISSES = 3,
	45	};
	46
	47	enum {
	48	MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
	49	MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
171bb2c5	50	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
e126ba97 EC	51	MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
	52	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
	53	MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
	54	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
	55	MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
171bb2c5	56	MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
e126ba97	57	MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
171bb2c5	58	MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10
e126ba97 EC	59	};
e126ba97 EC	60
fd76ee4d EC	61	enum {
	62	MLX5_NIC_IFC_FULL = 0,
	63	MLX5_NIC_IFC_DISABLED = 1,
04c0c1ab MHY	64	MLX5_NIC_IFC_NO_DRAM_NIC = 2,
04c0c1ab MHY	65	MLX5_NIC_IFC_INVALID = 3
fd76ee4d EC	66	};
fd76ee4d EC	67
05ac2c0b MHY	68	enum {
05ac2c0b MHY	69	MLX5_DROP_NEW_HEALTH_WORK,
2a0165a0	70	MLX5_DROP_NEW_RECOVERY_WORK,
05ac2c0b MHY	71	};
05ac2c0b MHY	72
04c0c1ab	73	static u8 get_nic_state(struct mlx5_core_dev *dev)
fd76ee4d EC	74	{
	75	return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 3;
	76	}
	77
89d44f0a MD	78	static void trigger_cmd_completions(struct mlx5_core_dev *dev)
	79	{
	80	unsigned long flags;
	81	u64 vector;
	82
	83	/* wait for pending handlers to complete */
78249c42	84	synchronize_irq(pci_irq_vector(dev->pdev, MLX5_EQ_VEC_CMD));
89d44f0a MD	85	spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
	86	vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
	87	if (!vector)
	88	goto no_trig;
	89
	90	vector \|= MLX5_TRIGGERED_CMD_COMP;
	91	spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
	92
	93	mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
73dd3a48	94	mlx5_cmd_comp_handler(dev, vector, true);
89d44f0a MD	95	return;
	96
	97	no_trig:
	98	spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
	99	}
	100
fd76ee4d EC	101	static int in_fatal(struct mlx5_core_dev *dev)
	102	{
	103	struct mlx5_core_health *health = &dev->priv.health;
	104	struct health_buffer __iomem *h = health->health;
	105
04c0c1ab	106	if (get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
fd76ee4d EC	107	return 1;
	108
	109	if (ioread32be(&h->fw_ver) == 0xffffffff)
	110	return 1;
	111
	112	return 0;
	113	}
	114
8812c24d	115	void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force)
89d44f0a	116	{
c1d4d2e9	117	mutex_lock(&dev->intf_state_mutex);
89d44f0a	118	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
c1d4d2e9	119	goto unlock;
89d44f0a MD	120
89d44f0a MD	121	mlx5_core_err(dev, "start\n");
8812c24d	122	if (pci_channel_offline(dev->pdev) \|\| in_fatal(dev) \|\| force) {
89d44f0a	123	dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
c1d4d2e9 MHY	124	trigger_cmd_completions(dev);
c1d4d2e9 MHY	125	}
89d44f0a MD	126
	127	mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 0);
	128	mlx5_core_err(dev, "end\n");
c1d4d2e9 MHY	129
	130	unlock:
	131	mutex_unlock(&dev->intf_state_mutex);
89d44f0a MD	132	}
	133
	134	static void mlx5_handle_bad_state(struct mlx5_core_dev *dev)
	135	{
04c0c1ab	136	u8 nic_interface = get_nic_state(dev);
89d44f0a MD	137
	138	switch (nic_interface) {
	139	case MLX5_NIC_IFC_FULL:
	140	mlx5_core_warn(dev, "Expected to see disabled NIC but it is full driver\n");
	141	break;
	142
	143	case MLX5_NIC_IFC_DISABLED:
	144	mlx5_core_warn(dev, "starting teardown\n");
	145	break;
	146
	147	case MLX5_NIC_IFC_NO_DRAM_NIC:
	148	mlx5_core_warn(dev, "Expected to see disabled NIC but it is no dram nic\n");
	149	break;
	150	default:
	151	mlx5_core_warn(dev, "Expected to see disabled NIC but it is has invalid value %d\n",
	152	nic_interface);
	153	}
	154
	155	mlx5_disable_device(dev);
	156	}
	157
04c0c1ab MHY	158	static void health_recover(struct work_struct *work)
	159	{
	160	struct mlx5_core_health *health;
	161	struct delayed_work *dwork;
	162	struct mlx5_core_dev *dev;
	163	struct mlx5_priv *priv;
	164	u8 nic_state;
	165
	166	dwork = container_of(work, struct delayed_work, work);
	167	health = container_of(dwork, struct mlx5_core_health, recover_work);
	168	priv = container_of(health, struct mlx5_priv, health);
	169	dev = container_of(priv, struct mlx5_core_dev, priv);
	170
	171	nic_state = get_nic_state(dev);
	172	if (nic_state == MLX5_NIC_IFC_INVALID) {
	173	dev_err(&dev->pdev->dev, "health recovery flow aborted since the nic state is invalid\n");
	174	return;
	175	}
	176
	177	dev_err(&dev->pdev->dev, "starting health recovery flow\n");
	178	mlx5_recover_device(dev);
	179	}
	180
	181	/* How much time to wait until health resetting the driver (in msecs) */
	182	#define MLX5_RECOVERY_DELAY_MSECS 60000
e126ba97 EC	183	static void health_care(struct work_struct *work)
e126ba97 EC	184	{
04c0c1ab	185	unsigned long recover_delay = msecs_to_jiffies(MLX5_RECOVERY_DELAY_MSECS);
ac6ea6e8	186	struct mlx5_core_health *health;
e126ba97 EC	187	struct mlx5_core_dev *dev;
e126ba97 EC	188	struct mlx5_priv *priv;
0179720d	189	unsigned long flags;
e126ba97	190
ac6ea6e8 EC	191	health = container_of(work, struct mlx5_core_health, work);
	192	priv = container_of(health, struct mlx5_priv, health);
	193	dev = container_of(priv, struct mlx5_core_dev, priv);
	194	mlx5_core_warn(dev, "handling bad device here\n");
89d44f0a	195	mlx5_handle_bad_state(dev);
04c0c1ab	196
0179720d	197	spin_lock_irqsave(&health->wq_lock, flags);
2a0165a0	198	if (!test_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags))
04c0c1ab MHY	199	schedule_delayed_work(&health->recover_work, recover_delay);
	200	else
	201	dev_err(&dev->pdev->dev,
	202	"new health works are not permitted at this stage\n");
0179720d	203	spin_unlock_irqrestore(&health->wq_lock, flags);
e126ba97 EC	204	}
	205
	206	static const char *hsynd_str(u8 synd)
	207	{
	208	switch (synd) {
	209	case MLX5_HEALTH_SYNDR_FW_ERR:
	210	return "firmware internal error";
	211	case MLX5_HEALTH_SYNDR_IRISC_ERR:
	212	return "irisc not responding";
171bb2c5 EC	213	case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR:
171bb2c5 EC	214	return "unrecoverable hardware error";
e126ba97 EC	215	case MLX5_HEALTH_SYNDR_CRC_ERR:
	216	return "firmware CRC error";
	217	case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR:
	218	return "ICM fetch PCI error";
	219	case MLX5_HEALTH_SYNDR_HW_FTL_ERR:
	220	return "HW fatal error\n";
	221	case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR:
	222	return "async EQ buffer overrun";
	223	case MLX5_HEALTH_SYNDR_EQ_ERR:
	224	return "EQ error";
171bb2c5	225	case MLX5_HEALTH_SYNDR_EQ_INV:
c01e0159	226	return "Invalid EQ referenced";
e126ba97 EC	227	case MLX5_HEALTH_SYNDR_FFSER_ERR:
e126ba97 EC	228	return "FFSER error";
171bb2c5	229	case MLX5_HEALTH_SYNDR_HIGH_TEMP:
c01e0159	230	return "High temperature";
e126ba97 EC	231	default:
	232	return "unrecognized error";
	233	}
	234	}
	235
	236	static void print_health_info(struct mlx5_core_dev *dev)
	237	{
	238	struct mlx5_core_health *health = &dev->priv.health;
	239	struct health_buffer __iomem *h = health->health;
0144a95e EC	240	char fw_str[18];
0144a95e EC	241	u32 fw;
e126ba97 EC	242	int i;
e126ba97 EC	243
777ec2b2	244	/* If the syndrome is 0, the device is OK and no need to print buffer */
89d44f0a MD	245	if (!ioread8(&h->synd))
	246	return;
	247
e126ba97	248	for (i = 0; i < ARRAY_SIZE(h->assert_var); i++)
0144a95e EC	249	dev_err(&dev->pdev->dev, "assert_var[%d] 0x%08x\n", i, ioread32be(h->assert_var + i));
	250
	251	dev_err(&dev->pdev->dev, "assert_exit_ptr 0x%08x\n", ioread32be(&h->assert_exit_ptr));
	252	dev_err(&dev->pdev->dev, "assert_callra 0x%08x\n", ioread32be(&h->assert_callra));
712bfef6	253	sprintf(fw_str, "%d.%d.%d", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
0144a95e EC	254	dev_err(&dev->pdev->dev, "fw_ver %s\n", fw_str);
	255	dev_err(&dev->pdev->dev, "hw_id 0x%08x\n", ioread32be(&h->hw_id));
	256	dev_err(&dev->pdev->dev, "irisc_index %d\n", ioread8(&h->irisc_index));
	257	dev_err(&dev->pdev->dev, "synd 0x%x: %s\n", ioread8(&h->synd), hsynd_str(ioread8(&h->synd)));
	258	dev_err(&dev->pdev->dev, "ext_synd 0x%04x\n", ioread16be(&h->ext_synd));
712bfef6 EC	259	fw = ioread32be(&h->fw_ver);
712bfef6 EC	260	dev_err(&dev->pdev->dev, "raw fw_ver 0x%08x\n", fw);
e126ba97 EC	261	}
e126ba97 EC	262
fd76ee4d EC	263	static unsigned long get_next_poll_jiffies(void)
	264	{
	265	unsigned long next;
	266
	267	get_random_bytes(&next, sizeof(next));
	268	next %= HZ;
	269	next += jiffies + MLX5_HEALTH_POLL_INTERVAL;
	270
	271	return next;
	272	}
	273
0179720d IT	274	void mlx5_trigger_health_work(struct mlx5_core_dev *dev)
	275	{
	276	struct mlx5_core_health *health = &dev->priv.health;
	277	unsigned long flags;
	278
	279	spin_lock_irqsave(&health->wq_lock, flags);
	280	if (!test_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags))
	281	queue_work(health->wq, &health->work);
	282	else
	283	dev_err(&dev->pdev->dev,
	284	"new health works are not permitted at this stage\n");
	285	spin_unlock_irqrestore(&health->wq_lock, flags);
	286	}
	287
0365b047	288	static void poll_health(struct timer_list *t)
e126ba97	289	{
0365b047	290	struct mlx5_core_dev *dev = from_timer(dev, t, priv.health.timer);
e126ba97	291	struct mlx5_core_health *health = &dev->priv.health;
e126ba97 EC	292	u32 count;
e126ba97 EC	293
3fece5d6 MHY	294	if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
3fece5d6 MHY	295	goto out;
89d44f0a	296
e126ba97 EC	297	count = ioread32be(health->health_counter);
	298	if (count == health->prev)
	299	++health->miss_counter;
	300	else
	301	health->miss_counter = 0;
	302
	303	health->prev = count;
	304	if (health->miss_counter == MAX_MISSES) {
fd76ee4d	305	dev_err(&dev->pdev->dev, "device's health compromised - reached miss count\n");
e126ba97	306	print_health_info(dev);
fd76ee4d EC	307	}
	308
	309	if (in_fatal(dev) && !health->sick) {
	310	health->sick = true;
	311	print_health_info(dev);
0179720d	312	mlx5_trigger_health_work(dev);
e126ba97	313	}
3fece5d6 MHY	314
	315	out:
	316	mod_timer(&health->timer, get_next_poll_jiffies());
e126ba97 EC	317	}
	318
	319	void mlx5_start_health_poll(struct mlx5_core_dev *dev)
	320	{
	321	struct mlx5_core_health *health = &dev->priv.health;
	322
0365b047	323	timer_setup(&health->timer, poll_health, 0);
2241007b	324	health->sick = 0;
05ac2c0b	325	clear_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
2a0165a0	326	clear_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
e126ba97 EC	327	health->health = &dev->iseg->health;
	328	health->health_counter = &dev->iseg->health_counter;
	329
e126ba97 EC	330	health->timer.expires = round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL);
	331	add_timer(&health->timer);
	332	}
	333
17254682	334	void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health)
e126ba97 EC	335	{
e126ba97 EC	336	struct mlx5_core_health *health = &dev->priv.health;
17254682 JM	337	unsigned long flags;
	338
	339	if (disable_health) {
	340	spin_lock_irqsave(&health->wq_lock, flags);
	341	set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
	342	set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
	343	spin_unlock_irqrestore(&health->wq_lock, flags);
	344	}
e126ba97 EC	345
e126ba97 EC	346	del_timer_sync(&health->timer);
e126ba97 EC	347	}
e126ba97 EC	348
05ac2c0b MHY	349	void mlx5_drain_health_wq(struct mlx5_core_dev *dev)
	350	{
	351	struct mlx5_core_health *health = &dev->priv.health;
0179720d	352	unsigned long flags;
05ac2c0b	353
0179720d	354	spin_lock_irqsave(&health->wq_lock, flags);
05ac2c0b	355	set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
2a0165a0	356	set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
0179720d	357	spin_unlock_irqrestore(&health->wq_lock, flags);
04c0c1ab	358	cancel_delayed_work_sync(&health->recover_work);
05ac2c0b MHY	359	cancel_work_sync(&health->work);
	360	}
	361
2a0165a0 MHY	362	void mlx5_drain_health_recovery(struct mlx5_core_dev *dev)
	363	{
	364	struct mlx5_core_health *health = &dev->priv.health;
6377ed0b	365	unsigned long flags;
2a0165a0	366
6377ed0b	367	spin_lock_irqsave(&health->wq_lock, flags);
2a0165a0	368	set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
6377ed0b	369	spin_unlock_irqrestore(&health->wq_lock, flags);
2a0165a0 MHY	370	cancel_delayed_work_sync(&dev->priv.health.recover_work);
	371	}
	372
ac6ea6e8	373	void mlx5_health_cleanup(struct mlx5_core_dev *dev)
e126ba97	374	{
ac6ea6e8 EC	375	struct mlx5_core_health *health = &dev->priv.health;
ac6ea6e8 EC	376
05ac2c0b	377	destroy_workqueue(health->wq);
e126ba97 EC	378	}
e126ba97 EC	379
ac6ea6e8	380	int mlx5_health_init(struct mlx5_core_dev *dev)
e126ba97	381	{
ac6ea6e8 EC	382	struct mlx5_core_health *health;
	383	char *name;
	384
	385	health = &dev->priv.health;
	386	name = kmalloc(64, GFP_KERNEL);
	387	if (!name)
	388	return -ENOMEM;
	389
	390	strcpy(name, "mlx5_health");
	391	strcat(name, dev_name(&dev->pdev->dev));
05ac2c0b	392	health->wq = create_singlethread_workqueue(name);
ac6ea6e8	393	kfree(name);
05ac2c0b MHY	394	if (!health->wq)
	395	return -ENOMEM;
	396	spin_lock_init(&health->wq_lock);
ac6ea6e8	397	INIT_WORK(&health->work, health_care);
04c0c1ab	398	INIT_DELAYED_WORK(&health->recover_work, health_recover);
ac6ea6e8 EC	399
ac6ea6e8 EC	400	return 0;
e126ba97	401	}