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7f966452 SC |
1 | #ifndef __QLCNIC_83XX_HW_H |
2 | #define __QLCNIC_83XX_HW_H | |
3 | ||
4 | #include <linux/types.h> | |
5 | #include <linux/etherdevice.h> | |
6 | #include "qlcnic_hw.h" | |
7 | ||
8 | /* Directly mapped registers */ | |
9 | #define QLC_83XX_CRB_WIN_BASE 0x3800 | |
10 | #define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4)) | |
11 | #define QLC_83XX_SEM_LOCK_BASE 0x3840 | |
12 | #define QLC_83XX_SEM_UNLOCK_BASE 0x3844 | |
13 | #define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8)) | |
14 | #define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8)) | |
15 | #define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0)) | |
16 | #define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4)) | |
17 | #define QLC_83XX_LINK_SPEED_FACTOR 10 | |
18 | #define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4))) | |
19 | #define QLC_83XX_INTX_PTR 0x38C0 | |
20 | #define QLC_83XX_INTX_TRGR 0x38C4 | |
21 | #define QLC_83XX_INTX_MASK 0x38C8 | |
22 | ||
23 | #define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100 | |
24 | #define QLC_83XX_DRV_LOCK_WAIT_DELAY 20 | |
25 | #define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1 | |
26 | #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2 | |
27 | #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3 | |
28 | #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200 | |
29 | #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3 | |
30 | ||
31 | #define QLC_83XX_NO_NIC_RESOURCE 0x5 | |
32 | #define QLC_83XX_MAC_PRESENT 0xC | |
33 | #define QLC_83XX_MAC_ABSENT 0xD | |
34 | ||
35 | ||
36 | #define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024) | |
37 | ||
38 | /* PEG status definitions */ | |
39 | #define QLC_83XX_CMDPEG_COMPLETE 0xff01 | |
40 | #define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30) | |
41 | #define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31) | |
42 | #define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF) | |
43 | #define QLC_83XX_LEGACY_INTX_MAX_RETRY 100 | |
44 | #define QLC_83XX_LEGACY_INTX_DELAY 4 | |
45 | #define QLC_83XX_REG_DESC 1 | |
46 | #define QLC_83XX_LRO_DESC 2 | |
47 | #define QLC_83XX_CTRL_DESC 3 | |
48 | #define QLC_83XX_FW_CAPABILITY_TSO BIT_6 | |
49 | #define QLC_83XX_FW_CAP_LRO_MSS BIT_17 | |
50 | #define QLC_83XX_HOST_RDS_MODE_UNIQUE 0 | |
51 | #define QLC_83XX_HOST_SDS_MBX_IDX 8 | |
52 | ||
53 | #define QLCNIC_HOST_RDS_MBX_IDX 88 | |
54 | #define QLCNIC_MAX_RING_SETS 8 | |
55 | ||
629263ac SC |
56 | /* Pause control registers */ |
57 | #define QLC_83XX_SRE_SHIM_REG 0x0D200284 | |
58 | #define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4 | |
59 | #define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4 | |
60 | #define QLC_83XX_PORT0_TC_MC_REG 0x0B200388 | |
61 | #define QLC_83XX_PORT1_TC_MC_REG 0x0B201388 | |
62 | #define QLC_83XX_PORT0_TC_STATS 0x0B20039C | |
63 | #define QLC_83XX_PORT1_TC_STATS 0x0B20139C | |
64 | #define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704 | |
65 | #define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704 | |
66 | ||
67 | /* Peg PC status registers */ | |
68 | #define QLC_83XX_CRB_PEG_NET_0 0x3400003c | |
69 | #define QLC_83XX_CRB_PEG_NET_1 0x3410003c | |
70 | #define QLC_83XX_CRB_PEG_NET_2 0x3420003c | |
71 | #define QLC_83XX_CRB_PEG_NET_3 0x3430003c | |
72 | #define QLC_83XX_CRB_PEG_NET_4 0x34b0003c | |
73 | ||
74 | /* Firmware image definitions */ | |
75 | #define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000 | |
76 | #define QLC_83XX_FW_FILE_NAME "83xx_fw.bin" | |
77 | #define QLC_83XX_BOOT_FROM_FLASH 0 | |
78 | #define QLC_83XX_BOOT_FROM_FILE 0x12345678 | |
79 | ||
7f966452 SC |
80 | struct qlcnic_intrpt_config { |
81 | u8 type; | |
82 | u8 enabled; | |
83 | u16 id; | |
84 | u32 src; | |
85 | }; | |
86 | ||
87 | struct qlcnic_macvlan_mbx { | |
88 | u8 mac[ETH_ALEN]; | |
89 | u16 vlan; | |
90 | }; | |
91 | ||
629263ac SC |
92 | struct qlc_83xx_fw_info { |
93 | const struct firmware *fw; | |
94 | u16 major_fw_version; | |
95 | u8 minor_fw_version; | |
96 | u8 sub_fw_version; | |
97 | u8 fw_build_num; | |
98 | u8 load_from_file; | |
99 | }; | |
100 | ||
101 | #define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1 | |
102 | #define QLC_83XX_IDC_GRACEFULL_RESET 0x2 | |
103 | #define QLC_83XX_IDC_TIMESTAMP 0 | |
104 | #define QLC_83XX_IDC_DURATION 1 | |
105 | #define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30 | |
106 | #define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10 | |
107 | #define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10 | |
108 | #define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20 | |
109 | #define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ) | |
110 | #define QLC_83XX_IDC_FW_FAIL_THRESH 2 | |
111 | #define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8 | |
112 | #define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16 | |
113 | #define QLC_83XX_IDC_MAJOR_VERSION 1 | |
114 | #define QLC_83XX_IDC_MINOR_VERSION 0 | |
115 | #define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020 | |
116 | ||
117 | /* Mailbox process AEN count */ | |
118 | #define QLC_83XX_MBX_AEN_CNT 5 | |
119 | ||
120 | struct qlcnic_adapter; | |
121 | struct qlc_83xx_idc { | |
122 | int (*state_entry) (struct qlcnic_adapter *); | |
123 | u64 sec_counter; | |
124 | u64 delay; | |
125 | unsigned long status; | |
126 | int err_code; | |
127 | int collect_dump; | |
128 | u8 curr_state; | |
129 | u8 prev_state; | |
130 | u8 vnic_state; | |
131 | u8 vnic_wait_limit; | |
132 | u8 quiesce_req; | |
133 | char **name; | |
134 | }; | |
7f966452 SC |
135 | |
136 | /* Mailbox process AEN count */ | |
137 | #define QLC_83XX_IDC_COMP_AEN 3 | |
138 | #define QLC_83XX_MBX_AEN_CNT 5 | |
139 | #define QLC_83XX_MODULE_LOADED 1 | |
140 | #define QLC_83XX_MBX_READY 2 | |
141 | #define QLC_83XX_MBX_AEN_ACK 3 | |
142 | #define QLC_83XX_SFP_PRESENT(data) ((data) & 3) | |
143 | #define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3) | |
144 | #define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F) | |
145 | #define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16)) | |
146 | #define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10) | |
147 | #define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11) | |
148 | #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0) | |
149 | #define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7) | |
150 | #define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3) | |
151 | #define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7) | |
152 | #define QLC_83XX_LINK_FEC(data) ((data) & BIT_12) | |
153 | #define QLC_83XX_LINK_EEE(data) ((data) & BIT_13) | |
154 | #define QLC_83XX_DCBX(data) (((data) >> 28) & 7) | |
155 | #define QLC_83XX_AUTONEG(data) ((data) & BIT_15) | |
156 | #define QLC_83XX_CFG_STD_PAUSE (1 << 5) | |
157 | #define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20) | |
158 | #define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20) | |
159 | #define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20) | |
160 | #define QLC_83XX_ENABLE_AUTONEG (1 << 15) | |
161 | #define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1) | |
162 | #define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1) | |
163 | #define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1) | |
164 | ||
165 | /* LED configuration settings */ | |
166 | #define QLC_83XX_ENABLE_BEACON 0xe | |
167 | #define QLC_83XX_LED_RATE 0xff | |
168 | #define QLC_83XX_LED_ACT (1 << 10) | |
169 | #define QLC_83XX_LED_MOD (0 << 13) | |
170 | #define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \ | |
171 | QLC_83XX_LED_MOD) | |
172 | ||
173 | #define QLC_83XX_10M_LINK 1 | |
174 | #define QLC_83XX_100M_LINK 2 | |
175 | #define QLC_83XX_1G_LINK 3 | |
176 | #define QLC_83XX_10G_LINK 4 | |
177 | #define QLC_83XX_STAT_TX 3 | |
178 | #define QLC_83XX_STAT_RX 2 | |
179 | #define QLC_83XX_STAT_MAC 1 | |
180 | #define QLC_83XX_TX_STAT_REGS 14 | |
181 | #define QLC_83XX_RX_STAT_REGS 40 | |
182 | #define QLC_83XX_MAC_STAT_REGS 80 | |
183 | ||
184 | #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) | |
185 | #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) | |
186 | #define QLC_83XX_DEFAULT_OPMODE 0x55555555 | |
187 | #define QLC_83XX_PRIVLEGED_FUNC 0x1 | |
188 | #define QLC_83XX_VIRTUAL_FUNC 0x2 | |
189 | ||
190 | #define QLC_83XX_LB_MAX_FILTERS 2048 | |
191 | #define QLC_83XX_LB_BUCKET_SIZE 256 | |
192 | #define QLC_83XX_MINIMUM_VECTOR 3 | |
193 | ||
194 | #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000) | |
195 | #define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20) | |
196 | #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) | |
197 | #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) | |
198 | #define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400) | |
199 | #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000) | |
200 | #define QLC_83XX_VIRTUAL_NIC_MODE 0xFF | |
201 | #define QLC_83XX_DEFAULT_MODE 0x0 | |
202 | #define QLCNIC_BRDTYPE_83XX_10G 0x0083 | |
203 | ||
d865ebb4 SC |
204 | #define QLC_83XX_FLASH_SPI_STATUS 0x2808E010 |
205 | #define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014 | |
206 | #define QLC_83XX_FLASH_STATUS 0x42100004 | |
207 | #define QLC_83XX_FLASH_CONTROL 0x42110004 | |
208 | #define QLC_83XX_FLASH_ADDR 0x42110008 | |
209 | #define QLC_83XX_FLASH_WRDATA 0x4211000C | |
210 | #define QLC_83XX_FLASH_RDDATA 0x42110018 | |
211 | #define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030 | |
212 | #define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA)) | |
213 | #define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef | |
214 | #define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda | |
215 | #define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca | |
216 | #define QLC_83XX_FLASH_READ_RETRY_COUNT 5000 | |
217 | #define QLC_83XX_FLASH_STATUS_READY 0x6 | |
218 | #define QLC_83XX_FLASH_BULK_WRITE_MIN 2 | |
219 | #define QLC_83XX_FLASH_BULK_WRITE_MAX 64 | |
220 | #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1 | |
221 | #define QLC_83XX_ERASE_MODE 1 | |
222 | #define QLC_83XX_WRITE_MODE 2 | |
223 | #define QLC_83XX_BULK_WRITE_MODE 3 | |
224 | #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100 | |
225 | #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300 | |
226 | #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F | |
227 | #define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8 | |
228 | #define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101 | |
229 | #define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005 | |
230 | #define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000 | |
231 | #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001 | |
232 | #define QLC_83XX_FLASH_WRDATA_DEF 0x0 | |
233 | #define QLC_83XX_FLASH_READ_CTRL 0x3F | |
234 | #define QLC_83XX_FLASH_SPI_CTRL 0x4 | |
235 | #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2 | |
236 | #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5 | |
237 | #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D | |
238 | #define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43 | |
239 | #define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F | |
240 | #define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D | |
241 | #define QLC_83xx_FLASH_MAX_WAIT_USEC 100 | |
242 | #define QLC_83XX_FLASH_LOCK_TIMEOUT 10000 | |
243 | ||
7f966452 SC |
244 | /* Additional registers in 83xx */ |
245 | enum qlc_83xx_ext_regs { | |
246 | QLCNIC_GLOBAL_RESET = 0, | |
247 | QLCNIC_WILDCARD, | |
248 | QLCNIC_INFORMANT, | |
249 | QLCNIC_HOST_MBX_CTRL, | |
250 | QLCNIC_FW_MBX_CTRL, | |
251 | QLCNIC_BOOTLOADER_ADDR, | |
252 | QLCNIC_BOOTLOADER_SIZE, | |
253 | QLCNIC_FW_IMAGE_ADDR, | |
254 | QLCNIC_MBX_INTR_ENBL, | |
255 | QLCNIC_DEF_INT_MASK, | |
256 | QLCNIC_DEF_INT_ID, | |
257 | QLC_83XX_IDC_MAJ_VERSION, | |
258 | QLC_83XX_IDC_DEV_STATE, | |
259 | QLC_83XX_IDC_DRV_PRESENCE, | |
260 | QLC_83XX_IDC_DRV_ACK, | |
261 | QLC_83XX_IDC_CTRL, | |
262 | QLC_83XX_IDC_DRV_AUDIT, | |
263 | QLC_83XX_IDC_MIN_VERSION, | |
264 | QLC_83XX_RECOVER_DRV_LOCK, | |
265 | QLC_83XX_IDC_PF_0, | |
266 | QLC_83XX_IDC_PF_1, | |
267 | QLC_83XX_IDC_PF_2, | |
268 | QLC_83XX_IDC_PF_3, | |
269 | QLC_83XX_IDC_PF_4, | |
270 | QLC_83XX_IDC_PF_5, | |
271 | QLC_83XX_IDC_PF_6, | |
272 | QLC_83XX_IDC_PF_7, | |
273 | QLC_83XX_IDC_PF_8, | |
274 | QLC_83XX_IDC_PF_9, | |
275 | QLC_83XX_IDC_PF_10, | |
276 | QLC_83XX_IDC_PF_11, | |
277 | QLC_83XX_IDC_PF_12, | |
278 | QLC_83XX_IDC_PF_13, | |
279 | QLC_83XX_IDC_PF_14, | |
280 | QLC_83XX_IDC_PF_15, | |
281 | QLC_83XX_IDC_DEV_PARTITION_INFO_1, | |
282 | QLC_83XX_IDC_DEV_PARTITION_INFO_2, | |
283 | QLC_83XX_DRV_OP_MODE, | |
284 | QLC_83XX_VNIC_STATE, | |
285 | QLC_83XX_DRV_LOCK, | |
286 | QLC_83XX_DRV_UNLOCK, | |
287 | QLC_83XX_DRV_LOCK_ID, | |
288 | QLC_83XX_ASIC_TEMP, | |
289 | }; | |
290 | ||
291 | /* 83xx funcitons */ | |
292 | int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *); | |
293 | int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
294 | int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8); | |
295 | void qlcnic_83xx_get_func_no(struct qlcnic_adapter *); | |
296 | int qlcnic_83xx_cam_lock(struct qlcnic_adapter *); | |
297 | void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *); | |
298 | int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32); | |
319ecf12 SC |
299 | void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *); |
300 | void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *); | |
7f966452 SC |
301 | void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); |
302 | void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); | |
303 | int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong); | |
304 | int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32); | |
4be41e92 | 305 | void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []); |
7f966452 SC |
306 | int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32); |
307 | int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8); | |
308 | int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8); | |
309 | int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int); | |
310 | int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int); | |
311 | int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *); | |
312 | void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, __le16); | |
313 | int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *); | |
314 | int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); | |
315 | void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int); | |
316 | ||
4be41e92 SC |
317 | int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *); |
318 | void qlcnic_83xx_napi_del(struct qlcnic_adapter *); | |
319 | void qlcnic_83xx_napi_enable(struct qlcnic_adapter *); | |
320 | void qlcnic_83xx_napi_disable(struct qlcnic_adapter *); | |
319ecf12 | 321 | int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32); |
7f966452 SC |
322 | void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32); |
323 | int qlcnic_ind_rd(struct qlcnic_adapter *, u32); | |
324 | void qlcnic_83xx_get_stats(struct qlcnic_adapter *, | |
325 | struct ethtool_stats *, u64 *); | |
326 | int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *); | |
327 | int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *, | |
328 | struct qlcnic_host_tx_ring *, int); | |
329 | int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); | |
330 | int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int); | |
331 | void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *); | |
332 | int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool); | |
333 | int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8); | |
334 | int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *); | |
335 | void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8, | |
336 | struct qlcnic_cmd_args *); | |
337 | int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *, | |
338 | struct qlcnic_adapter *, u32); | |
339 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *); | |
340 | void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *, | |
341 | struct qlcnic_info *); | |
342 | void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *); | |
343 | irqreturn_t qlcnic_83xx_handle_aen(int, void *); | |
344 | int qlcnic_83xx_get_port_info(struct qlcnic_adapter *); | |
345 | void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *); | |
346 | irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *); | |
347 | irqreturn_t qlcnic_83xx_tmp_intr(int, void *); | |
348 | void qlcnic_83xx_enable_intr(struct qlcnic_adapter *, | |
349 | struct qlcnic_host_sds_ring *); | |
350 | void qlcnic_83xx_check_vf(struct qlcnic_adapter *, | |
351 | const struct pci_device_id *); | |
352 | void qlcnic_83xx_process_aen(struct qlcnic_adapter *); | |
353 | int qlcnic_83xx_get_port_config(struct qlcnic_adapter *); | |
354 | int qlcnic_83xx_set_port_config(struct qlcnic_adapter *); | |
355 | int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8); | |
356 | int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *); | |
357 | int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *); | |
358 | int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *); | |
359 | void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *); | |
360 | void qlcnic_83xx_register_map(struct qlcnic_hardware_context *); | |
361 | void qlcnic_83xx_idc_aen_work(struct work_struct *); | |
362 | void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int); | |
d865ebb4 SC |
363 | |
364 | int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32); | |
365 | int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int); | |
366 | int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *); | |
367 | int qlcnic_83xx_lock_flash(struct qlcnic_adapter *); | |
368 | void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *); | |
369 | int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *); | |
370 | int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int); | |
371 | int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *); | |
372 | int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *); | |
629263ac SC |
373 | int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int); |
374 | int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *, | |
375 | u32, u8 *, int); | |
376 | int qlcnic_83xx_init(struct qlcnic_adapter *); | |
377 | int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *); | |
378 | int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev); | |
379 | void qlcnic_83xx_idc_poll_dev_state(struct work_struct *); | |
380 | void qlcnic_83xx_idc_exit(struct qlcnic_adapter *); | |
381 | void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32); | |
382 | int qlcnic_83xx_lock_driver(struct qlcnic_adapter *); | |
383 | void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *); | |
384 | int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *); | |
385 | int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32); | |
7f966452 | 386 | #endif |