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577ae39d JK |
1 | /* |
2 | * QLogic qlcnic NIC Driver | |
3 | * Copyright (c) 2009-2013 QLogic Corporation | |
4 | * | |
5 | * See LICENSE.qlcnic for copyright and licensing details. | |
6 | */ | |
7 | ||
7f966452 SC |
8 | #ifndef __QLCNIC_83XX_HW_H |
9 | #define __QLCNIC_83XX_HW_H | |
10 | ||
11 | #include <linux/types.h> | |
12 | #include <linux/etherdevice.h> | |
13 | #include "qlcnic_hw.h" | |
14 | ||
a520030e HM |
15 | #define QLCNIC_83XX_BAR0_LENGTH 0x4000 |
16 | ||
7f966452 SC |
17 | /* Directly mapped registers */ |
18 | #define QLC_83XX_CRB_WIN_BASE 0x3800 | |
19 | #define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4)) | |
20 | #define QLC_83XX_SEM_LOCK_BASE 0x3840 | |
21 | #define QLC_83XX_SEM_UNLOCK_BASE 0x3844 | |
22 | #define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8)) | |
23 | #define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8)) | |
24 | #define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0)) | |
25 | #define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4)) | |
26 | #define QLC_83XX_LINK_SPEED_FACTOR 10 | |
27 | #define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4))) | |
28 | #define QLC_83XX_INTX_PTR 0x38C0 | |
29 | #define QLC_83XX_INTX_TRGR 0x38C4 | |
30 | #define QLC_83XX_INTX_MASK 0x38C8 | |
31 | ||
32 | #define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100 | |
33 | #define QLC_83XX_DRV_LOCK_WAIT_DELAY 20 | |
34 | #define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1 | |
35 | #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2 | |
36 | #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3 | |
37 | #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200 | |
38 | #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3 | |
2c4a7878 JK |
39 | #define QLC_83XX_LB_WAIT_COUNT 250 |
40 | #define QLC_83XX_LB_MSLEEP_COUNT 20 | |
7f966452 SC |
41 | #define QLC_83XX_NO_NIC_RESOURCE 0x5 |
42 | #define QLC_83XX_MAC_PRESENT 0xC | |
43 | #define QLC_83XX_MAC_ABSENT 0xD | |
44 | ||
45 | ||
46 | #define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024) | |
47 | ||
48 | /* PEG status definitions */ | |
49 | #define QLC_83XX_CMDPEG_COMPLETE 0xff01 | |
50 | #define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30) | |
51 | #define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31) | |
52 | #define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF) | |
53 | #define QLC_83XX_LEGACY_INTX_MAX_RETRY 100 | |
54 | #define QLC_83XX_LEGACY_INTX_DELAY 4 | |
55 | #define QLC_83XX_REG_DESC 1 | |
56 | #define QLC_83XX_LRO_DESC 2 | |
57 | #define QLC_83XX_CTRL_DESC 3 | |
58 | #define QLC_83XX_FW_CAPABILITY_TSO BIT_6 | |
59 | #define QLC_83XX_FW_CAP_LRO_MSS BIT_17 | |
60 | #define QLC_83XX_HOST_RDS_MODE_UNIQUE 0 | |
61 | #define QLC_83XX_HOST_SDS_MBX_IDX 8 | |
62 | ||
63 | #define QLCNIC_HOST_RDS_MBX_IDX 88 | |
64 | #define QLCNIC_MAX_RING_SETS 8 | |
65 | ||
629263ac SC |
66 | /* Pause control registers */ |
67 | #define QLC_83XX_SRE_SHIM_REG 0x0D200284 | |
68 | #define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4 | |
69 | #define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4 | |
70 | #define QLC_83XX_PORT0_TC_MC_REG 0x0B200388 | |
71 | #define QLC_83XX_PORT1_TC_MC_REG 0x0B201388 | |
72 | #define QLC_83XX_PORT0_TC_STATS 0x0B20039C | |
73 | #define QLC_83XX_PORT1_TC_STATS 0x0B20139C | |
74 | #define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704 | |
75 | #define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704 | |
76 | ||
77 | /* Peg PC status registers */ | |
78 | #define QLC_83XX_CRB_PEG_NET_0 0x3400003c | |
79 | #define QLC_83XX_CRB_PEG_NET_1 0x3410003c | |
80 | #define QLC_83XX_CRB_PEG_NET_2 0x3420003c | |
81 | #define QLC_83XX_CRB_PEG_NET_3 0x3430003c | |
82 | #define QLC_83XX_CRB_PEG_NET_4 0x34b0003c | |
83 | ||
84 | /* Firmware image definitions */ | |
85 | #define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000 | |
86 | #define QLC_83XX_FW_FILE_NAME "83xx_fw.bin" | |
fef349ce | 87 | #define QLC_84XX_FW_FILE_NAME "84xx_fw.bin" |
629263ac SC |
88 | #define QLC_83XX_BOOT_FROM_FLASH 0 |
89 | #define QLC_83XX_BOOT_FROM_FILE 0x12345678 | |
90 | ||
fef349ce | 91 | #define QLC_FW_FILE_NAME_LEN 20 |
81d0aeb0 SC |
92 | #define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16 |
93 | ||
e5c4e6c6 MC |
94 | #define QLC_83XX_MBX_POST_BC_OP 0x1 |
95 | #define QLC_83XX_MBX_COMPLETION 0x0 | |
96 | #define QLC_83XX_MBX_REQUEST 0x1 | |
97 | ||
98 | #define QLC_83XX_MBX_TIMEOUT (5 * HZ) | |
99 | #define QLC_83XX_MBX_CMD_LOOP 5000000 | |
100 | ||
7cb03b23 RB |
101 | /* status descriptor mailbox data |
102 | * @phy_addr_{low|high}: physical address of buffer | |
103 | * @sds_ring_size: buffer size | |
104 | * @intrpt_id: interrupt id | |
105 | * @intrpt_val: source of interrupt | |
106 | */ | |
107 | struct qlcnic_sds_mbx { | |
108 | u32 phy_addr_low; | |
109 | u32 phy_addr_high; | |
110 | u32 rsvd1[4]; | |
111 | #if defined(__LITTLE_ENDIAN) | |
112 | u16 sds_ring_size; | |
113 | u16 rsvd2; | |
114 | u16 rsvd3[2]; | |
115 | u16 intrpt_id; | |
116 | u8 intrpt_val; | |
117 | u8 rsvd4; | |
118 | #elif defined(__BIG_ENDIAN) | |
119 | u16 rsvd2; | |
120 | u16 sds_ring_size; | |
121 | u16 rsvd3[2]; | |
122 | u8 rsvd4; | |
123 | u8 intrpt_val; | |
124 | u16 intrpt_id; | |
125 | #endif | |
126 | u32 rsvd5; | |
127 | } __packed; | |
128 | ||
129 | /* receive descriptor buffer data | |
130 | * phy_addr_reg_{low|high}: physical address of regular buffer | |
131 | * phy_addr_jmb_{low|high}: physical address of jumbo buffer | |
132 | * reg_ring_sz: size of regular buffer | |
133 | * reg_ring_len: no. of entries in regular buffer | |
134 | * jmb_ring_len: no. of entries in jumbo buffer | |
135 | * jmb_ring_sz: size of jumbo buffer | |
136 | */ | |
137 | struct qlcnic_rds_mbx { | |
138 | u32 phy_addr_reg_low; | |
139 | u32 phy_addr_reg_high; | |
140 | u32 phy_addr_jmb_low; | |
141 | u32 phy_addr_jmb_high; | |
142 | #if defined(__LITTLE_ENDIAN) | |
143 | u16 reg_ring_sz; | |
144 | u16 reg_ring_len; | |
145 | u16 jmb_ring_sz; | |
146 | u16 jmb_ring_len; | |
147 | #elif defined(__BIG_ENDIAN) | |
148 | u16 reg_ring_len; | |
149 | u16 reg_ring_sz; | |
150 | u16 jmb_ring_len; | |
151 | u16 jmb_ring_sz; | |
152 | #endif | |
153 | } __packed; | |
154 | ||
155 | /* host producers for regular and jumbo rings */ | |
156 | struct __host_producer_mbx { | |
157 | u32 reg_buf; | |
158 | u32 jmb_buf; | |
159 | } __packed; | |
160 | ||
161 | /* Receive context mailbox data outbox registers | |
162 | * @state: state of the context | |
163 | * @vport_id: virtual port id | |
164 | * @context_id: receive context id | |
165 | * @num_pci_func: number of pci functions of the port | |
166 | * @phy_port: physical port id | |
167 | */ | |
168 | struct qlcnic_rcv_mbx_out { | |
169 | #if defined(__LITTLE_ENDIAN) | |
170 | u8 rcv_num; | |
171 | u8 sts_num; | |
172 | u16 ctx_id; | |
173 | u8 state; | |
174 | u8 num_pci_func; | |
175 | u8 phy_port; | |
176 | u8 vport_id; | |
177 | #elif defined(__BIG_ENDIAN) | |
178 | u16 ctx_id; | |
179 | u8 sts_num; | |
180 | u8 rcv_num; | |
181 | u8 vport_id; | |
182 | u8 phy_port; | |
183 | u8 num_pci_func; | |
184 | u8 state; | |
185 | #endif | |
186 | u32 host_csmr[QLCNIC_MAX_RING_SETS]; | |
187 | struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS]; | |
188 | } __packed; | |
189 | ||
190 | struct qlcnic_add_rings_mbx_out { | |
191 | #if defined(__LITTLE_ENDIAN) | |
192 | u8 rcv_num; | |
193 | u8 sts_num; | |
194 | u16 ctx_id; | |
195 | #elif defined(__BIG_ENDIAN) | |
196 | u16 ctx_id; | |
197 | u8 sts_num; | |
198 | u8 rcv_num; | |
199 | #endif | |
200 | u32 host_csmr[QLCNIC_MAX_RING_SETS]; | |
201 | struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS]; | |
202 | } __packed; | |
203 | ||
204 | /* Transmit context mailbox inbox registers | |
205 | * @phys_addr_{low|high}: DMA address of the transmit buffer | |
206 | * @cnsmr_index_{low|high}: host consumer index | |
207 | * @size: legth of transmit buffer ring | |
208 | * @intr_id: interrput id | |
209 | * @src: src of interrupt | |
210 | */ | |
211 | struct qlcnic_tx_mbx { | |
212 | u32 phys_addr_low; | |
213 | u32 phys_addr_high; | |
214 | u32 cnsmr_index_low; | |
215 | u32 cnsmr_index_high; | |
216 | #if defined(__LITTLE_ENDIAN) | |
217 | u16 size; | |
218 | u16 intr_id; | |
219 | u8 src; | |
220 | u8 rsvd[3]; | |
221 | #elif defined(__BIG_ENDIAN) | |
222 | u16 intr_id; | |
223 | u16 size; | |
224 | u8 rsvd[3]; | |
225 | u8 src; | |
226 | #endif | |
227 | } __packed; | |
228 | ||
229 | /* Transmit context mailbox outbox registers | |
230 | * @host_prod: host producer index | |
231 | * @ctx_id: transmit context id | |
232 | * @state: state of the transmit context | |
233 | */ | |
234 | ||
235 | struct qlcnic_tx_mbx_out { | |
236 | u32 host_prod; | |
237 | #if defined(__LITTLE_ENDIAN) | |
238 | u16 ctx_id; | |
239 | u8 state; | |
240 | u8 rsvd; | |
241 | #elif defined(__BIG_ENDIAN) | |
242 | u8 rsvd; | |
243 | u8 state; | |
244 | u16 ctx_id; | |
245 | #endif | |
246 | } __packed; | |
247 | ||
7f966452 SC |
248 | struct qlcnic_intrpt_config { |
249 | u8 type; | |
250 | u8 enabled; | |
251 | u16 id; | |
252 | u32 src; | |
253 | }; | |
254 | ||
255 | struct qlcnic_macvlan_mbx { | |
a96227e6 SS |
256 | #if defined(__LITTLE_ENDIAN) |
257 | u8 mac_addr0; | |
258 | u8 mac_addr1; | |
259 | u8 mac_addr2; | |
260 | u8 mac_addr3; | |
261 | u8 mac_addr4; | |
262 | u8 mac_addr5; | |
7f966452 | 263 | u16 vlan; |
a96227e6 SS |
264 | #elif defined(__BIG_ENDIAN) |
265 | u8 mac_addr3; | |
266 | u8 mac_addr2; | |
267 | u8 mac_addr1; | |
268 | u8 mac_addr0; | |
269 | u16 vlan; | |
270 | u8 mac_addr5; | |
271 | u8 mac_addr4; | |
272 | #endif | |
7f966452 SC |
273 | }; |
274 | ||
629263ac SC |
275 | struct qlc_83xx_fw_info { |
276 | const struct firmware *fw; | |
7000078a | 277 | char fw_file_name[QLC_FW_FILE_NAME_LEN]; |
629263ac SC |
278 | }; |
279 | ||
81d0aeb0 SC |
280 | struct qlc_83xx_reset { |
281 | struct qlc_83xx_reset_hdr *hdr; | |
282 | int seq_index; | |
283 | int seq_error; | |
284 | int array_index; | |
285 | u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES]; | |
286 | u8 *buff; | |
287 | u8 *stop_offset; | |
288 | u8 *start_offset; | |
289 | u8 *init_offset; | |
290 | u8 seq_end; | |
291 | u8 template_end; | |
292 | }; | |
293 | ||
629263ac SC |
294 | #define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1 |
295 | #define QLC_83XX_IDC_GRACEFULL_RESET 0x2 | |
890b6e02 | 296 | #define QLC_83XX_IDC_DISABLE_FW_DUMP 0x4 |
629263ac SC |
297 | #define QLC_83XX_IDC_TIMESTAMP 0 |
298 | #define QLC_83XX_IDC_DURATION 1 | |
299 | #define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30 | |
300 | #define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10 | |
301 | #define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10 | |
302 | #define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20 | |
303 | #define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ) | |
304 | #define QLC_83XX_IDC_FW_FAIL_THRESH 2 | |
305 | #define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8 | |
306 | #define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16 | |
307 | #define QLC_83XX_IDC_MAJOR_VERSION 1 | |
308 | #define QLC_83XX_IDC_MINOR_VERSION 0 | |
309 | #define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020 | |
310 | ||
629263ac SC |
311 | struct qlcnic_adapter; |
312 | struct qlc_83xx_idc { | |
313 | int (*state_entry) (struct qlcnic_adapter *); | |
314 | u64 sec_counter; | |
315 | u64 delay; | |
316 | unsigned long status; | |
317 | int err_code; | |
318 | int collect_dump; | |
319 | u8 curr_state; | |
320 | u8 prev_state; | |
321 | u8 vnic_state; | |
322 | u8 vnic_wait_limit; | |
323 | u8 quiesce_req; | |
099907fa | 324 | u8 delay_reset; |
629263ac SC |
325 | char **name; |
326 | }; | |
7f966452 | 327 | |
f036e4f4 RB |
328 | /* Device States */ |
329 | enum qlcnic_83xx_states { | |
330 | QLC_83XX_IDC_DEV_UNKNOWN, | |
331 | QLC_83XX_IDC_DEV_COLD, | |
332 | QLC_83XX_IDC_DEV_INIT, | |
333 | QLC_83XX_IDC_DEV_READY, | |
334 | QLC_83XX_IDC_DEV_NEED_RESET, | |
335 | QLC_83XX_IDC_DEV_NEED_QUISCENT, | |
336 | QLC_83XX_IDC_DEV_FAILED, | |
337 | QLC_83XX_IDC_DEV_QUISCENT | |
338 | }; | |
339 | ||
483202d5 JK |
340 | #define QLCNIC_MBX_RSP(reg) LSW(reg) |
341 | #define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF) | |
342 | #define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F) | |
343 | #define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4)) | |
344 | #define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4)) | |
345 | ||
7f966452 SC |
346 | /* Mailbox process AEN count */ |
347 | #define QLC_83XX_IDC_COMP_AEN 3 | |
348 | #define QLC_83XX_MBX_AEN_CNT 5 | |
349 | #define QLC_83XX_MODULE_LOADED 1 | |
350 | #define QLC_83XX_MBX_READY 2 | |
351 | #define QLC_83XX_MBX_AEN_ACK 3 | |
352 | #define QLC_83XX_SFP_PRESENT(data) ((data) & 3) | |
353 | #define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3) | |
354 | #define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F) | |
355 | #define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16)) | |
356 | #define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10) | |
357 | #define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11) | |
358 | #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0) | |
359 | #define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7) | |
360 | #define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3) | |
361 | #define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7) | |
362 | #define QLC_83XX_LINK_FEC(data) ((data) & BIT_12) | |
363 | #define QLC_83XX_LINK_EEE(data) ((data) & BIT_13) | |
364 | #define QLC_83XX_DCBX(data) (((data) >> 28) & 7) | |
365 | #define QLC_83XX_AUTONEG(data) ((data) & BIT_15) | |
6177a95a JK |
366 | #define QLC_83XX_TX_PAUSE 0x10 |
367 | #define QLC_83XX_RX_PAUSE 0x20 | |
368 | #define QLC_83XX_TX_RX_PAUSE 0x30 | |
7f966452 SC |
369 | #define QLC_83XX_CFG_STD_PAUSE (1 << 5) |
370 | #define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20) | |
371 | #define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20) | |
372 | #define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20) | |
373 | #define QLC_83XX_ENABLE_AUTONEG (1 << 15) | |
374 | #define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1) | |
375 | #define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1) | |
376 | #define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1) | |
377 | ||
378 | /* LED configuration settings */ | |
379 | #define QLC_83XX_ENABLE_BEACON 0xe | |
380 | #define QLC_83XX_LED_RATE 0xff | |
381 | #define QLC_83XX_LED_ACT (1 << 10) | |
382 | #define QLC_83XX_LED_MOD (0 << 13) | |
383 | #define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \ | |
384 | QLC_83XX_LED_MOD) | |
385 | ||
386 | #define QLC_83XX_10M_LINK 1 | |
387 | #define QLC_83XX_100M_LINK 2 | |
388 | #define QLC_83XX_1G_LINK 3 | |
389 | #define QLC_83XX_10G_LINK 4 | |
390 | #define QLC_83XX_STAT_TX 3 | |
391 | #define QLC_83XX_STAT_RX 2 | |
392 | #define QLC_83XX_STAT_MAC 1 | |
393 | #define QLC_83XX_TX_STAT_REGS 14 | |
394 | #define QLC_83XX_RX_STAT_REGS 40 | |
52290740 | 395 | #define QLC_83XX_MAC_STAT_REGS 94 |
7f966452 SC |
396 | |
397 | #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) | |
398 | #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) | |
399 | #define QLC_83XX_DEFAULT_OPMODE 0x55555555 | |
400 | #define QLC_83XX_PRIVLEGED_FUNC 0x1 | |
401 | #define QLC_83XX_VIRTUAL_FUNC 0x2 | |
402 | ||
403 | #define QLC_83XX_LB_MAX_FILTERS 2048 | |
404 | #define QLC_83XX_LB_BUCKET_SIZE 256 | |
405 | #define QLC_83XX_MINIMUM_VECTOR 3 | |
52e493d0 JK |
406 | #define QLC_83XX_MAX_MC_COUNT 38 |
407 | #define QLC_83XX_MAX_UC_COUNT 4096 | |
7f966452 | 408 | |
58945e1b | 409 | #define QLC_83XX_PVID_STRIP_CAPABILITY BIT_22 |
7f966452 SC |
410 | #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000) |
411 | #define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20) | |
412 | #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) | |
413 | #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) | |
414 | #define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400) | |
415 | #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000) | |
99e85879 | 416 | #define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000) |
35dafcb0 | 417 | #define QLC_83XX_ESWITCH_CAPABILITY BIT_23 |
7f966452 SC |
418 | #define QLC_83XX_VIRTUAL_NIC_MODE 0xFF |
419 | #define QLC_83XX_DEFAULT_MODE 0x0 | |
02feda17 | 420 | #define QLC_83XX_SRIOV_MODE 0x1 |
7f966452 SC |
421 | #define QLCNIC_BRDTYPE_83XX_10G 0x0083 |
422 | ||
d865ebb4 SC |
423 | #define QLC_83XX_FLASH_SPI_STATUS 0x2808E010 |
424 | #define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014 | |
425 | #define QLC_83XX_FLASH_STATUS 0x42100004 | |
426 | #define QLC_83XX_FLASH_CONTROL 0x42110004 | |
427 | #define QLC_83XX_FLASH_ADDR 0x42110008 | |
428 | #define QLC_83XX_FLASH_WRDATA 0x4211000C | |
429 | #define QLC_83XX_FLASH_RDDATA 0x42110018 | |
430 | #define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030 | |
431 | #define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA)) | |
432 | #define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef | |
433 | #define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda | |
434 | #define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca | |
435 | #define QLC_83XX_FLASH_READ_RETRY_COUNT 5000 | |
436 | #define QLC_83XX_FLASH_STATUS_READY 0x6 | |
a520030e HM |
437 | #define QLC_83XX_FLASH_WRITE_MIN 2 |
438 | #define QLC_83XX_FLASH_WRITE_MAX 64 | |
d865ebb4 SC |
439 | #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1 |
440 | #define QLC_83XX_ERASE_MODE 1 | |
441 | #define QLC_83XX_WRITE_MODE 2 | |
442 | #define QLC_83XX_BULK_WRITE_MODE 3 | |
443 | #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100 | |
444 | #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300 | |
445 | #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F | |
446 | #define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8 | |
447 | #define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101 | |
448 | #define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005 | |
449 | #define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000 | |
450 | #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001 | |
451 | #define QLC_83XX_FLASH_WRDATA_DEF 0x0 | |
452 | #define QLC_83XX_FLASH_READ_CTRL 0x3F | |
453 | #define QLC_83XX_FLASH_SPI_CTRL 0x4 | |
454 | #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2 | |
455 | #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5 | |
456 | #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D | |
457 | #define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43 | |
458 | #define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F | |
459 | #define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D | |
460 | #define QLC_83xx_FLASH_MAX_WAIT_USEC 100 | |
461 | #define QLC_83XX_FLASH_LOCK_TIMEOUT 10000 | |
462 | ||
e5c4e6c6 MC |
463 | enum qlc_83xx_mbx_cmd_type { |
464 | QLC_83XX_MBX_CMD_WAIT = 0, | |
465 | QLC_83XX_MBX_CMD_NO_WAIT, | |
466 | QLC_83XX_MBX_CMD_BUSY_WAIT, | |
467 | }; | |
468 | ||
469 | enum qlc_83xx_mbx_response_states { | |
470 | QLC_83XX_MBX_RESPONSE_WAIT = 0, | |
471 | QLC_83XX_MBX_RESPONSE_ARRIVED, | |
472 | }; | |
473 | ||
474 | #define QLC_83XX_MBX_RESPONSE_FAILED 0x2 | |
475 | #define QLC_83XX_MBX_RESPONSE_UNKNOWN 0x3 | |
476 | ||
7f966452 SC |
477 | /* Additional registers in 83xx */ |
478 | enum qlc_83xx_ext_regs { | |
479 | QLCNIC_GLOBAL_RESET = 0, | |
480 | QLCNIC_WILDCARD, | |
481 | QLCNIC_INFORMANT, | |
482 | QLCNIC_HOST_MBX_CTRL, | |
483 | QLCNIC_FW_MBX_CTRL, | |
484 | QLCNIC_BOOTLOADER_ADDR, | |
485 | QLCNIC_BOOTLOADER_SIZE, | |
486 | QLCNIC_FW_IMAGE_ADDR, | |
487 | QLCNIC_MBX_INTR_ENBL, | |
488 | QLCNIC_DEF_INT_MASK, | |
489 | QLCNIC_DEF_INT_ID, | |
490 | QLC_83XX_IDC_MAJ_VERSION, | |
491 | QLC_83XX_IDC_DEV_STATE, | |
492 | QLC_83XX_IDC_DRV_PRESENCE, | |
493 | QLC_83XX_IDC_DRV_ACK, | |
494 | QLC_83XX_IDC_CTRL, | |
495 | QLC_83XX_IDC_DRV_AUDIT, | |
496 | QLC_83XX_IDC_MIN_VERSION, | |
497 | QLC_83XX_RECOVER_DRV_LOCK, | |
498 | QLC_83XX_IDC_PF_0, | |
499 | QLC_83XX_IDC_PF_1, | |
500 | QLC_83XX_IDC_PF_2, | |
501 | QLC_83XX_IDC_PF_3, | |
502 | QLC_83XX_IDC_PF_4, | |
503 | QLC_83XX_IDC_PF_5, | |
504 | QLC_83XX_IDC_PF_6, | |
505 | QLC_83XX_IDC_PF_7, | |
506 | QLC_83XX_IDC_PF_8, | |
507 | QLC_83XX_IDC_PF_9, | |
508 | QLC_83XX_IDC_PF_10, | |
509 | QLC_83XX_IDC_PF_11, | |
510 | QLC_83XX_IDC_PF_12, | |
511 | QLC_83XX_IDC_PF_13, | |
512 | QLC_83XX_IDC_PF_14, | |
513 | QLC_83XX_IDC_PF_15, | |
514 | QLC_83XX_IDC_DEV_PARTITION_INFO_1, | |
515 | QLC_83XX_IDC_DEV_PARTITION_INFO_2, | |
516 | QLC_83XX_DRV_OP_MODE, | |
517 | QLC_83XX_VNIC_STATE, | |
518 | QLC_83XX_DRV_LOCK, | |
519 | QLC_83XX_DRV_UNLOCK, | |
520 | QLC_83XX_DRV_LOCK_ID, | |
521 | QLC_83XX_ASIC_TEMP, | |
522 | }; | |
523 | ||
524 | /* 83xx funcitons */ | |
525 | int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *); | |
e5c4e6c6 | 526 | int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *, struct qlcnic_cmd_args *); |
aa4a1f7d | 527 | int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8, int); |
7f966452 SC |
528 | void qlcnic_83xx_get_func_no(struct qlcnic_adapter *); |
529 | int qlcnic_83xx_cam_lock(struct qlcnic_adapter *); | |
530 | void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *); | |
531 | int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32); | |
319ecf12 SC |
532 | void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *); |
533 | void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *); | |
7f966452 SC |
534 | void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); |
535 | void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); | |
4bd8e738 | 536 | int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *); |
7f966452 | 537 | int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32); |
4be41e92 | 538 | void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []); |
7f966452 SC |
539 | int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32); |
540 | int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8); | |
541 | int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8); | |
542 | int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int); | |
543 | int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int); | |
544 | int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *); | |
f80bc8fe | 545 | void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, u16); |
7f966452 SC |
546 | int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *); |
547 | int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); | |
548 | void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int); | |
549 | ||
4be41e92 SC |
550 | int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *); |
551 | void qlcnic_83xx_napi_del(struct qlcnic_adapter *); | |
552 | void qlcnic_83xx_napi_enable(struct qlcnic_adapter *); | |
553 | void qlcnic_83xx_napi_disable(struct qlcnic_adapter *); | |
319ecf12 | 554 | int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32); |
7f966452 SC |
555 | void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32); |
556 | int qlcnic_ind_rd(struct qlcnic_adapter *, u32); | |
7f966452 SC |
557 | int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *); |
558 | int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *, | |
559 | struct qlcnic_host_tx_ring *, int); | |
7cb03b23 RB |
560 | void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *); |
561 | void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *, | |
562 | struct qlcnic_host_tx_ring *); | |
7f966452 SC |
563 | int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); |
564 | int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int); | |
565 | void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *); | |
566 | int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool); | |
f80bc8fe | 567 | int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8); |
07a251c8 | 568 | int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *, u8); |
7f966452 SC |
569 | void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8, |
570 | struct qlcnic_cmd_args *); | |
571 | int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *, | |
572 | struct qlcnic_adapter *, u32); | |
573 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *); | |
574 | void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *, | |
575 | struct qlcnic_info *); | |
576 | void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *); | |
577 | irqreturn_t qlcnic_83xx_handle_aen(int, void *); | |
578 | int qlcnic_83xx_get_port_info(struct qlcnic_adapter *); | |
e5c4e6c6 | 579 | void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *); |
f036e4f4 | 580 | void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *); |
7f966452 | 581 | irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *); |
ac166700 | 582 | irqreturn_t qlcnic_83xx_intr(int, void *); |
7f966452 SC |
583 | irqreturn_t qlcnic_83xx_tmp_intr(int, void *); |
584 | void qlcnic_83xx_enable_intr(struct qlcnic_adapter *, | |
585 | struct qlcnic_host_sds_ring *); | |
ac166700 HM |
586 | void qlcnic_83xx_disable_intr(struct qlcnic_adapter *, |
587 | struct qlcnic_host_sds_ring *); | |
7f966452 SC |
588 | void qlcnic_83xx_check_vf(struct qlcnic_adapter *, |
589 | const struct pci_device_id *); | |
d1a1105e | 590 | void __qlcnic_83xx_process_aen(struct qlcnic_adapter *); |
7f966452 SC |
591 | int qlcnic_83xx_get_port_config(struct qlcnic_adapter *); |
592 | int qlcnic_83xx_set_port_config(struct qlcnic_adapter *); | |
593 | int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8); | |
594 | int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *); | |
595 | int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *); | |
596 | int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *); | |
597 | void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *); | |
598 | void qlcnic_83xx_register_map(struct qlcnic_hardware_context *); | |
599 | void qlcnic_83xx_idc_aen_work(struct work_struct *); | |
600 | void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int); | |
d865ebb4 SC |
601 | |
602 | int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32); | |
603 | int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int); | |
604 | int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *); | |
605 | int qlcnic_83xx_lock_flash(struct qlcnic_adapter *); | |
606 | void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *); | |
607 | int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *); | |
608 | int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int); | |
609 | int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *); | |
610 | int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *); | |
629263ac SC |
611 | int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int); |
612 | int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *, | |
613 | u32, u8 *, int); | |
f8468331 | 614 | int qlcnic_83xx_init(struct qlcnic_adapter *, int); |
629263ac SC |
615 | int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *); |
616 | int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev); | |
617 | void qlcnic_83xx_idc_poll_dev_state(struct work_struct *); | |
81d0aeb0 | 618 | int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *); |
629263ac SC |
619 | void qlcnic_83xx_idc_exit(struct qlcnic_adapter *); |
620 | void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32); | |
621 | int qlcnic_83xx_lock_driver(struct qlcnic_adapter *); | |
622 | void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *); | |
623 | int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *); | |
624 | int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32); | |
d71170fb SC |
625 | int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *); |
626 | int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int); | |
627 | int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int); | |
628 | int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *); | |
629 | int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *, | |
630 | struct qlcnic_info *, u8); | |
631 | int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *); | |
4c776aad | 632 | int qlcnic_83xx_set_port_eswitch_status(struct qlcnic_adapter *, int, int *); |
4e60ac46 SC |
633 | |
634 | void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *); | |
7e38d04b | 635 | void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data); |
b938662d | 636 | int qlcnic_83xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *); |
7e38d04b SC |
637 | int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *); |
638 | void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *, | |
639 | struct ethtool_pauseparam *); | |
640 | int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *, | |
641 | struct ethtool_pauseparam *); | |
642 | int qlcnic_83xx_test_link(struct qlcnic_adapter *); | |
643 | int qlcnic_83xx_reg_test(struct qlcnic_adapter *); | |
644 | int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *); | |
645 | int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *); | |
ba4468db | 646 | int qlcnic_83xx_loopback_test(struct net_device *, u8); |
58ead415 | 647 | int qlcnic_83xx_interrupt_test(struct net_device *); |
d16951d9 | 648 | int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state); |
7e38d04b | 649 | int qlcnic_83xx_flash_test(struct qlcnic_adapter *); |
a520030e HM |
650 | int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *); |
651 | int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *); | |
7ed3ce48 RB |
652 | void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *); |
653 | void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *); | |
52e493d0 | 654 | void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *); |
486a5bc7 RB |
655 | int qlcnic_83xx_shutdown(struct pci_dev *); |
656 | int qlcnic_83xx_resume(struct qlcnic_adapter *); | |
657 | int qlcnic_83xx_idc_init(struct qlcnic_adapter *); | |
658 | int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *); | |
659 | int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *); | |
660 | int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *); | |
9ce226fa PP |
661 | void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *); |
662 | int qlcnic_83xx_aer_reset(struct qlcnic_adapter *); | |
663 | void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *); | |
664 | pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *, | |
665 | pci_channel_state_t); | |
666 | pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *); | |
667 | void qlcnic_83xx_io_resume(struct pci_dev *); | |
7f966452 | 668 | #endif |