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629263ac SC |
1 | #include "qlcnic.h" |
2 | #include "qlcnic_hw.h" | |
3 | ||
81d0aeb0 SC |
4 | /* Reset template definitions */ |
5 | #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000 | |
6 | #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000 | |
7 | #define QLC_83XX_RESET_SEQ_VERSION 0x0101 | |
8 | ||
9 | #define QLC_83XX_OPCODE_NOP 0x0000 | |
10 | #define QLC_83XX_OPCODE_WRITE_LIST 0x0001 | |
11 | #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002 | |
12 | #define QLC_83XX_OPCODE_POLL_LIST 0x0004 | |
13 | #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008 | |
14 | #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010 | |
15 | #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020 | |
16 | #define QLC_83XX_OPCODE_SEQ_END 0x0040 | |
17 | #define QLC_83XX_OPCODE_TMPL_END 0x0080 | |
18 | #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100 | |
19 | ||
629263ac SC |
20 | static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter); |
21 | static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); | |
22 | static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev); | |
23 | static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter); | |
24 | ||
81d0aeb0 SC |
25 | /* Template header */ |
26 | struct qlc_83xx_reset_hdr { | |
27 | u16 version; | |
28 | u16 signature; | |
29 | u16 size; | |
30 | u16 entries; | |
31 | u16 hdr_size; | |
32 | u16 checksum; | |
33 | u16 init_offset; | |
34 | u16 start_offset; | |
35 | } __packed; | |
36 | ||
37 | /* Command entry header. */ | |
38 | struct qlc_83xx_entry_hdr { | |
39 | u16 cmd; | |
40 | u16 size; | |
41 | u16 count; | |
42 | u16 delay; | |
43 | } __packed; | |
44 | ||
45 | /* Generic poll command */ | |
46 | struct qlc_83xx_poll { | |
47 | u32 mask; | |
48 | u32 status; | |
49 | } __packed; | |
50 | ||
51 | /* Read modify write command */ | |
52 | struct qlc_83xx_rmw { | |
53 | u32 mask; | |
54 | u32 xor_value; | |
55 | u32 or_value; | |
56 | u8 shl; | |
57 | u8 shr; | |
58 | u8 index_a; | |
59 | u8 rsvd; | |
60 | } __packed; | |
61 | ||
62 | /* Generic command with 2 DWORD */ | |
63 | struct qlc_83xx_entry { | |
64 | u32 arg1; | |
65 | u32 arg2; | |
66 | } __packed; | |
67 | ||
68 | /* Generic command with 4 DWORD */ | |
69 | struct qlc_83xx_quad_entry { | |
70 | u32 dr_addr; | |
71 | u32 dr_value; | |
72 | u32 ar_addr; | |
73 | u32 ar_value; | |
74 | } __packed; | |
629263ac SC |
75 | static const char *const qlc_83xx_idc_states[] = { |
76 | "Unknown", | |
77 | "Cold", | |
78 | "Init", | |
79 | "Ready", | |
80 | "Need Reset", | |
81 | "Need Quiesce", | |
82 | "Failed", | |
83 | "Quiesce" | |
84 | }; | |
85 | ||
86 | /* Device States */ | |
87 | enum qlcnic_83xx_states { | |
88 | QLC_83XX_IDC_DEV_UNKNOWN, | |
89 | QLC_83XX_IDC_DEV_COLD, | |
90 | QLC_83XX_IDC_DEV_INIT, | |
91 | QLC_83XX_IDC_DEV_READY, | |
92 | QLC_83XX_IDC_DEV_NEED_RESET, | |
93 | QLC_83XX_IDC_DEV_NEED_QUISCENT, | |
94 | QLC_83XX_IDC_DEV_FAILED, | |
95 | QLC_83XX_IDC_DEV_QUISCENT | |
96 | }; | |
97 | ||
98 | static int | |
99 | qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter) | |
100 | { | |
101 | u32 val; | |
102 | ||
103 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); | |
104 | if ((val & 0xFFFF)) | |
105 | return 1; | |
106 | else | |
107 | return 0; | |
108 | } | |
109 | ||
110 | static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter) | |
111 | { | |
112 | u32 cur, prev; | |
113 | cur = adapter->ahw->idc.curr_state; | |
114 | prev = adapter->ahw->idc.prev_state; | |
115 | ||
116 | dev_info(&adapter->pdev->dev, | |
117 | "current state = %s, prev state = %s\n", | |
118 | adapter->ahw->idc.name[cur], | |
119 | adapter->ahw->idc.name[prev]); | |
120 | } | |
121 | ||
122 | static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter, | |
123 | u8 mode, int lock) | |
124 | { | |
125 | u32 val; | |
126 | int seconds; | |
127 | ||
128 | if (lock) { | |
129 | if (qlcnic_83xx_lock_driver(adapter)) | |
130 | return -EBUSY; | |
131 | } | |
132 | ||
133 | val = adapter->portnum & 0xf; | |
134 | val |= mode << 7; | |
135 | if (mode) | |
136 | seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; | |
137 | else | |
138 | seconds = jiffies / HZ; | |
139 | ||
140 | val |= seconds << 8; | |
141 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); | |
142 | adapter->ahw->idc.sec_counter = jiffies / HZ; | |
143 | ||
144 | if (lock) | |
145 | qlcnic_83xx_unlock_driver(adapter); | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
150 | static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter) | |
151 | { | |
152 | u32 val; | |
153 | ||
154 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); | |
155 | val = val & ~(0x3 << (adapter->portnum * 2)); | |
156 | val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); | |
157 | QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); | |
158 | } | |
159 | ||
160 | static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter, | |
161 | int lock) | |
162 | { | |
163 | u32 val; | |
164 | ||
165 | if (lock) { | |
166 | if (qlcnic_83xx_lock_driver(adapter)) | |
167 | return -EBUSY; | |
168 | } | |
169 | ||
170 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); | |
171 | val = val & ~0xFF; | |
172 | val = val | QLC_83XX_IDC_MAJOR_VERSION; | |
173 | QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); | |
174 | ||
175 | if (lock) | |
176 | qlcnic_83xx_unlock_driver(adapter); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static int | |
182 | qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter, | |
183 | int status, int lock) | |
184 | { | |
185 | u32 val; | |
186 | ||
187 | if (lock) { | |
188 | if (qlcnic_83xx_lock_driver(adapter)) | |
189 | return -EBUSY; | |
190 | } | |
191 | ||
192 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); | |
193 | ||
194 | if (status) | |
195 | val = val | (1 << adapter->portnum); | |
196 | else | |
197 | val = val & ~(1 << adapter->portnum); | |
198 | ||
199 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); | |
200 | qlcnic_83xx_idc_update_minor_version(adapter); | |
201 | ||
202 | if (lock) | |
203 | qlcnic_83xx_unlock_driver(adapter); | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter) | |
209 | { | |
210 | u32 val; | |
211 | u8 version; | |
212 | ||
213 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); | |
214 | version = val & 0xFF; | |
215 | ||
216 | if (version != QLC_83XX_IDC_MAJOR_VERSION) { | |
217 | dev_info(&adapter->pdev->dev, | |
218 | "%s:mismatch. version 0x%x, expected version 0x%x\n", | |
219 | __func__, version, QLC_83XX_IDC_MAJOR_VERSION); | |
220 | return -EIO; | |
221 | } | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter, | |
227 | int lock) | |
228 | { | |
229 | u32 val; | |
230 | ||
231 | if (lock) { | |
232 | if (qlcnic_83xx_lock_driver(adapter)) | |
233 | return -EBUSY; | |
234 | } | |
235 | ||
236 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0); | |
237 | /* Clear gracefull reset bit */ | |
238 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); | |
239 | val &= ~QLC_83XX_IDC_GRACEFULL_RESET; | |
240 | QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); | |
241 | ||
242 | if (lock) | |
243 | qlcnic_83xx_unlock_driver(adapter); | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter, | |
249 | int flag, int lock) | |
250 | { | |
251 | u32 val; | |
252 | ||
253 | if (lock) { | |
254 | if (qlcnic_83xx_lock_driver(adapter)) | |
255 | return -EBUSY; | |
256 | } | |
257 | ||
258 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); | |
259 | if (flag) | |
260 | val = val | (1 << adapter->portnum); | |
261 | else | |
262 | val = val & ~(1 << adapter->portnum); | |
263 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); | |
264 | ||
265 | if (lock) | |
266 | qlcnic_83xx_unlock_driver(adapter); | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter, | |
272 | int time_limit) | |
273 | { | |
274 | u64 seconds; | |
275 | ||
276 | seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; | |
277 | if (seconds <= time_limit) | |
278 | return 0; | |
279 | else | |
280 | return -EBUSY; | |
281 | } | |
282 | ||
283 | /** | |
284 | * qlcnic_83xx_idc_check_reset_ack_reg | |
285 | * | |
286 | * @adapter: adapter structure | |
287 | * | |
288 | * Check ACK wait limit and clear the functions which failed to ACK | |
289 | * | |
290 | * Return 0 if all functions have acknowledged the reset request. | |
291 | **/ | |
292 | static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter) | |
293 | { | |
294 | int timeout; | |
295 | u32 ack, presence, val; | |
296 | ||
297 | timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS; | |
298 | ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); | |
299 | presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); | |
300 | dev_info(&adapter->pdev->dev, | |
301 | "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence); | |
302 | if (!((ack & presence) == presence)) { | |
303 | if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) { | |
304 | /* Clear functions which failed to ACK */ | |
305 | dev_info(&adapter->pdev->dev, | |
306 | "%s: ACK wait exceeds time limit\n", __func__); | |
307 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); | |
308 | val = val & ~(ack ^ presence); | |
309 | if (qlcnic_83xx_lock_driver(adapter)) | |
310 | return -EBUSY; | |
311 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); | |
312 | dev_info(&adapter->pdev->dev, | |
313 | "%s: updated drv presence reg = 0x%x\n", | |
314 | __func__, val); | |
315 | qlcnic_83xx_unlock_driver(adapter); | |
316 | return 0; | |
317 | ||
318 | } else { | |
319 | return 1; | |
320 | } | |
321 | } else { | |
322 | dev_info(&adapter->pdev->dev, | |
323 | "%s: Reset ACK received from all functions\n", | |
324 | __func__); | |
325 | return 0; | |
326 | } | |
327 | } | |
328 | ||
329 | /** | |
330 | * qlcnic_83xx_idc_tx_soft_reset | |
331 | * | |
332 | * @adapter: adapter structure | |
333 | * | |
334 | * Handle context deletion and recreation request from transmit routine | |
335 | * | |
336 | * Returns -EBUSY or Success (0) | |
337 | * | |
338 | **/ | |
339 | static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter) | |
340 | { | |
341 | struct net_device *netdev = adapter->netdev; | |
342 | ||
343 | if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) | |
344 | return -EBUSY; | |
345 | ||
346 | netif_device_detach(netdev); | |
347 | qlcnic_down(adapter, netdev); | |
348 | qlcnic_up(adapter, netdev); | |
349 | netif_device_attach(netdev); | |
350 | clear_bit(__QLCNIC_RESETTING, &adapter->state); | |
351 | dev_err(&adapter->pdev->dev, "%s:\n", __func__); | |
352 | ||
353 | adapter->netdev->trans_start = jiffies; | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | /** | |
359 | * qlcnic_83xx_idc_detach_driver | |
360 | * | |
361 | * @adapter: adapter structure | |
362 | * Detach net interface, stop TX and cleanup resources before the HW reset. | |
363 | * Returns: None | |
364 | * | |
365 | **/ | |
366 | static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter) | |
367 | { | |
368 | int i; | |
369 | struct net_device *netdev = adapter->netdev; | |
370 | ||
371 | netif_device_detach(netdev); | |
372 | /* Disable mailbox interrupt */ | |
373 | QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0); | |
374 | qlcnic_down(adapter, netdev); | |
375 | for (i = 0; i < adapter->ahw->num_msix; i++) { | |
376 | adapter->ahw->intr_tbl[i].id = i; | |
377 | adapter->ahw->intr_tbl[i].enabled = 0; | |
378 | adapter->ahw->intr_tbl[i].src = 0; | |
379 | } | |
380 | } | |
381 | ||
382 | /** | |
383 | * qlcnic_83xx_idc_attach_driver | |
384 | * | |
385 | * @adapter: adapter structure | |
386 | * | |
387 | * Re-attach and re-enable net interface | |
388 | * Returns: None | |
389 | * | |
390 | **/ | |
391 | static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter) | |
392 | { | |
393 | struct net_device *netdev = adapter->netdev; | |
394 | ||
395 | if (netif_running(netdev)) { | |
396 | if (qlcnic_up(adapter, netdev)) | |
397 | goto done; | |
398 | qlcnic_restore_indev_addr(netdev, NETDEV_UP); | |
399 | } | |
400 | done: | |
401 | netif_device_attach(netdev); | |
402 | if (netif_running(netdev)) { | |
403 | netif_carrier_on(netdev); | |
404 | netif_wake_queue(netdev); | |
405 | } | |
406 | } | |
407 | ||
408 | static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter, | |
409 | int lock) | |
410 | { | |
411 | if (lock) { | |
412 | if (qlcnic_83xx_lock_driver(adapter)) | |
413 | return -EBUSY; | |
414 | } | |
415 | ||
416 | qlcnic_83xx_idc_clear_registers(adapter, 0); | |
417 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED); | |
418 | if (lock) | |
419 | qlcnic_83xx_unlock_driver(adapter); | |
420 | ||
421 | qlcnic_83xx_idc_log_state_history(adapter); | |
422 | dev_info(&adapter->pdev->dev, "Device will enter failed state\n"); | |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
427 | static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter, | |
428 | int lock) | |
429 | { | |
430 | if (lock) { | |
431 | if (qlcnic_83xx_lock_driver(adapter)) | |
432 | return -EBUSY; | |
433 | } | |
434 | ||
435 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT); | |
436 | ||
437 | if (lock) | |
438 | qlcnic_83xx_unlock_driver(adapter); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter, | |
444 | int lock) | |
445 | { | |
446 | if (lock) { | |
447 | if (qlcnic_83xx_lock_driver(adapter)) | |
448 | return -EBUSY; | |
449 | } | |
450 | ||
451 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, | |
452 | QLC_83XX_IDC_DEV_NEED_QUISCENT); | |
453 | ||
454 | if (lock) | |
455 | qlcnic_83xx_unlock_driver(adapter); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static int | |
461 | qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock) | |
462 | { | |
463 | if (lock) { | |
464 | if (qlcnic_83xx_lock_driver(adapter)) | |
465 | return -EBUSY; | |
466 | } | |
467 | ||
468 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, | |
469 | QLC_83XX_IDC_DEV_NEED_RESET); | |
470 | ||
471 | if (lock) | |
472 | qlcnic_83xx_unlock_driver(adapter); | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter, | |
478 | int lock) | |
479 | { | |
480 | if (lock) { | |
481 | if (qlcnic_83xx_lock_driver(adapter)) | |
482 | return -EBUSY; | |
483 | } | |
484 | ||
485 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY); | |
486 | if (lock) | |
487 | qlcnic_83xx_unlock_driver(adapter); | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | /** | |
493 | * qlcnic_83xx_idc_find_reset_owner_id | |
494 | * | |
495 | * @adapter: adapter structure | |
496 | * | |
497 | * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE. | |
498 | * Within the same class, function with lowest PCI ID assumes ownership | |
499 | * | |
500 | * Returns: reset owner id or failure indication (-EIO) | |
501 | * | |
502 | **/ | |
503 | static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter) | |
504 | { | |
505 | u32 reg, reg1, reg2, i, j, owner, class; | |
506 | ||
507 | reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); | |
508 | reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); | |
509 | owner = QLCNIC_TYPE_NIC; | |
510 | i = 0; | |
511 | j = 0; | |
512 | reg = reg1; | |
513 | ||
514 | do { | |
515 | class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); | |
516 | if (class == owner) | |
517 | break; | |
518 | if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) { | |
519 | reg = reg2; | |
520 | j = 0; | |
521 | } else { | |
522 | j++; | |
523 | } | |
524 | ||
525 | if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) { | |
526 | if (owner == QLCNIC_TYPE_NIC) | |
527 | owner = QLCNIC_TYPE_ISCSI; | |
528 | else if (owner == QLCNIC_TYPE_ISCSI) | |
529 | owner = QLCNIC_TYPE_FCOE; | |
530 | else if (owner == QLCNIC_TYPE_FCOE) | |
531 | return -EIO; | |
532 | reg = reg1; | |
533 | j = 0; | |
534 | i = 0; | |
535 | } | |
536 | } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS); | |
537 | ||
538 | return i; | |
539 | } | |
540 | ||
541 | static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock) | |
542 | { | |
543 | int ret = 0; | |
544 | ||
545 | ret = qlcnic_83xx_restart_hw(adapter); | |
546 | ||
547 | if (ret) { | |
548 | qlcnic_83xx_idc_enter_failed_state(adapter, lock); | |
549 | } else { | |
550 | qlcnic_83xx_idc_clear_registers(adapter, lock); | |
551 | ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock); | |
552 | } | |
553 | ||
554 | return ret; | |
555 | } | |
556 | ||
557 | static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter) | |
558 | { | |
559 | u32 status; | |
560 | ||
561 | status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1); | |
562 | ||
563 | if (status & QLCNIC_RCODE_FATAL_ERROR) { | |
564 | dev_err(&adapter->pdev->dev, | |
565 | "peg halt status1=0x%x\n", status); | |
566 | if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) { | |
567 | dev_err(&adapter->pdev->dev, | |
568 | "On board active cooling fan failed. " | |
569 | "Device has been halted.\n"); | |
570 | dev_err(&adapter->pdev->dev, | |
571 | "Replace the adapter.\n"); | |
572 | return -EIO; | |
573 | } | |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter) | |
580 | { | |
581 | qlcnic_83xx_enable_mbx_intrpt(adapter); | |
582 | if ((adapter->flags & QLCNIC_MSIX_ENABLED)) { | |
583 | if (qlcnic_83xx_config_intrpt(adapter, 1)) { | |
584 | netdev_err(adapter->netdev, | |
585 | "Failed to enable mbx intr\n"); | |
586 | return -EIO; | |
587 | } | |
588 | } | |
589 | ||
590 | if (qlcnic_83xx_configure_opmode(adapter)) { | |
591 | qlcnic_83xx_idc_enter_failed_state(adapter, 1); | |
592 | return -EIO; | |
593 | } | |
594 | ||
595 | if (adapter->nic_ops->init_driver(adapter)) { | |
596 | qlcnic_83xx_idc_enter_failed_state(adapter, 1); | |
597 | return -EIO; | |
598 | } | |
599 | ||
600 | qlcnic_83xx_idc_attach_driver(adapter); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter) | |
606 | { | |
607 | qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1); | |
608 | clear_bit(__QLCNIC_RESETTING, &adapter->state); | |
609 | set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); | |
610 | qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); | |
611 | set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); | |
612 | adapter->ahw->idc.quiesce_req = 0; | |
613 | adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; | |
614 | adapter->ahw->idc.err_code = 0; | |
615 | adapter->ahw->idc.collect_dump = 0; | |
616 | } | |
617 | ||
618 | /** | |
619 | * qlcnic_83xx_idc_ready_state_entry | |
620 | * | |
621 | * @adapter: adapter structure | |
622 | * | |
623 | * Perform ready state initialization, this routine will get invoked only | |
624 | * once from READY state. | |
625 | * | |
626 | * Returns: Error code or Success(0) | |
627 | * | |
628 | **/ | |
629 | int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter) | |
630 | { | |
631 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
632 | ||
633 | if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) { | |
634 | qlcnic_83xx_idc_update_idc_params(adapter); | |
635 | /* Re-attach the device if required */ | |
636 | if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || | |
637 | (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) { | |
638 | if (qlcnic_83xx_idc_reattach_driver(adapter)) | |
639 | return -EIO; | |
640 | } | |
641 | } | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
d71170fb SC |
646 | /** |
647 | * qlcnic_83xx_idc_vnic_pf_entry | |
648 | * | |
649 | * @adapter: adapter structure | |
650 | * | |
651 | * Ensure vNIC mode privileged function starts only after vNIC mode is | |
652 | * enabled by management function. | |
653 | * If vNIC mode is ready, start initialization. | |
654 | * | |
655 | * Returns: -EIO or 0 | |
656 | * | |
657 | **/ | |
658 | int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter) | |
659 | { | |
660 | u32 state; | |
661 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
662 | ||
663 | /* Privileged function waits till mgmt function enables VNIC mode */ | |
664 | state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE); | |
665 | if (state != QLCNIC_DEV_NPAR_OPER) { | |
666 | if (!ahw->idc.vnic_wait_limit--) { | |
667 | qlcnic_83xx_idc_enter_failed_state(adapter, 1); | |
668 | return -EIO; | |
669 | } | |
670 | dev_info(&adapter->pdev->dev, "vNIC mode disabled\n"); | |
671 | return -EIO; | |
672 | ||
673 | } else { | |
674 | /* Perform one time initialization from ready state */ | |
675 | if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) { | |
676 | qlcnic_83xx_idc_update_idc_params(adapter); | |
677 | ||
678 | /* If the previous state is UNKNOWN, device will be | |
679 | already attached properly by Init routine*/ | |
680 | if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) { | |
681 | if (qlcnic_83xx_idc_reattach_driver(adapter)) | |
682 | return -EIO; | |
683 | } | |
684 | adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER; | |
685 | dev_info(&adapter->pdev->dev, "vNIC mode enabled\n"); | |
686 | } | |
687 | } | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
629263ac SC |
692 | static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter) |
693 | { | |
694 | adapter->ahw->idc.err_code = -EIO; | |
695 | dev_err(&adapter->pdev->dev, | |
696 | "%s: Device in unknown state\n", __func__); | |
697 | return 0; | |
698 | } | |
699 | ||
700 | /** | |
701 | * qlcnic_83xx_idc_cold_state | |
702 | * | |
703 | * @adapter: adapter structure | |
704 | * | |
705 | * If HW is up and running device will enter READY state. | |
706 | * If firmware image from host needs to be loaded, device is | |
707 | * forced to start with the file firmware image. | |
708 | * | |
709 | * Returns: Error code or Success(0) | |
710 | * | |
711 | **/ | |
712 | static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter) | |
713 | { | |
714 | qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0); | |
715 | qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0); | |
716 | ||
717 | if (qlcnic_load_fw_file) { | |
718 | qlcnic_83xx_idc_restart_hw(adapter, 0); | |
719 | } else { | |
720 | if (qlcnic_83xx_check_hw_status(adapter)) { | |
721 | qlcnic_83xx_idc_enter_failed_state(adapter, 0); | |
722 | return -EIO; | |
723 | } else { | |
724 | qlcnic_83xx_idc_enter_ready_state(adapter, 0); | |
725 | } | |
726 | } | |
727 | return 0; | |
728 | } | |
729 | ||
730 | /** | |
731 | * qlcnic_83xx_idc_init_state | |
732 | * | |
733 | * @adapter: adapter structure | |
734 | * | |
735 | * Reset owner will restart the device from this state. | |
736 | * Device will enter failed state if it remains | |
737 | * in this state for more than DEV_INIT time limit. | |
738 | * | |
739 | * Returns: Error code or Success(0) | |
740 | * | |
741 | **/ | |
742 | static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter) | |
743 | { | |
744 | int timeout, ret = 0; | |
745 | u32 owner; | |
746 | ||
747 | timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS; | |
748 | if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) { | |
749 | owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); | |
750 | if (adapter->ahw->pci_func == owner) | |
751 | ret = qlcnic_83xx_idc_restart_hw(adapter, 1); | |
752 | } else { | |
753 | ret = qlcnic_83xx_idc_check_timeout(adapter, timeout); | |
754 | return ret; | |
755 | } | |
756 | ||
757 | return ret; | |
758 | } | |
759 | ||
760 | /** | |
761 | * qlcnic_83xx_idc_ready_state | |
762 | * | |
763 | * @adapter: adapter structure | |
764 | * | |
765 | * Perform IDC protocol specicifed actions after monitoring device state and | |
766 | * events. | |
767 | * | |
768 | * Returns: Error code or Success(0) | |
769 | * | |
770 | **/ | |
771 | static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter) | |
772 | { | |
773 | u32 val; | |
774 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
775 | int ret = 0; | |
776 | ||
777 | /* Perform NIC configuration based ready state entry actions */ | |
778 | if (ahw->idc.state_entry(adapter)) | |
779 | return -EIO; | |
780 | ||
781 | if (qlcnic_check_temp(adapter)) { | |
782 | if (ahw->temp == QLCNIC_TEMP_PANIC) { | |
783 | qlcnic_83xx_idc_check_fan_failure(adapter); | |
784 | dev_err(&adapter->pdev->dev, | |
785 | "Error: device temperature %d above limits\n", | |
786 | adapter->ahw->temp); | |
787 | clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status); | |
788 | set_bit(__QLCNIC_RESETTING, &adapter->state); | |
789 | qlcnic_83xx_idc_detach_driver(adapter); | |
790 | qlcnic_83xx_idc_enter_failed_state(adapter, 1); | |
791 | return -EIO; | |
792 | } | |
793 | } | |
794 | ||
795 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); | |
796 | ret = qlcnic_83xx_check_heartbeat(adapter); | |
797 | if (ret) { | |
798 | adapter->flags |= QLCNIC_FW_HANG; | |
799 | if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { | |
800 | clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status); | |
801 | set_bit(__QLCNIC_RESETTING, &adapter->state); | |
802 | qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); | |
803 | } | |
804 | return -EIO; | |
805 | } | |
806 | ||
807 | if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { | |
808 | /* Move to need reset state and prepare for reset */ | |
809 | qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); | |
810 | return ret; | |
811 | } | |
812 | ||
813 | /* Check for soft reset request */ | |
814 | if (ahw->reset_context && | |
815 | !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { | |
816 | qlcnic_83xx_idc_tx_soft_reset(adapter); | |
817 | return ret; | |
818 | } | |
819 | ||
820 | /* Move to need quiesce state if requested */ | |
821 | if (adapter->ahw->idc.quiesce_req) { | |
822 | qlcnic_83xx_idc_enter_need_quiesce(adapter, 1); | |
823 | qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); | |
824 | return ret; | |
825 | } | |
826 | ||
827 | return ret; | |
828 | } | |
829 | ||
830 | /** | |
831 | * qlcnic_83xx_idc_need_reset_state | |
832 | * | |
833 | * @adapter: adapter structure | |
834 | * | |
835 | * Device will remain in this state until: | |
836 | * Reset request ACK's are recieved from all the functions | |
837 | * Wait time exceeds max time limit | |
838 | * | |
839 | * Returns: Error code or Success(0) | |
840 | * | |
841 | **/ | |
842 | static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter) | |
843 | { | |
844 | int ret = 0; | |
845 | ||
846 | if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) { | |
847 | qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); | |
848 | qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); | |
849 | set_bit(__QLCNIC_RESETTING, &adapter->state); | |
850 | clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); | |
d71170fb SC |
851 | if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) |
852 | qlcnic_83xx_disable_vnic_mode(adapter, 1); | |
629263ac SC |
853 | qlcnic_83xx_idc_detach_driver(adapter); |
854 | } | |
855 | ||
856 | /* Check ACK from other functions */ | |
857 | ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter); | |
858 | if (ret) { | |
859 | dev_info(&adapter->pdev->dev, | |
860 | "%s: Waiting for reset ACK\n", __func__); | |
861 | return 0; | |
862 | } | |
863 | ||
864 | /* Transit to INIT state and restart the HW */ | |
865 | qlcnic_83xx_idc_enter_init_state(adapter, 1); | |
866 | ||
867 | return ret; | |
868 | } | |
869 | ||
870 | static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter) | |
871 | { | |
872 | dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__); | |
873 | return 0; | |
874 | } | |
875 | ||
876 | static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter) | |
877 | { | |
878 | dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__); | |
879 | adapter->ahw->idc.err_code = -EIO; | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter) | |
885 | { | |
886 | dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__); | |
887 | return 0; | |
888 | } | |
889 | ||
890 | static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter, | |
891 | u32 state) | |
892 | { | |
893 | u32 cur, prev, next; | |
894 | ||
895 | cur = adapter->ahw->idc.curr_state; | |
896 | prev = adapter->ahw->idc.prev_state; | |
897 | next = state; | |
898 | ||
899 | if ((next < QLC_83XX_IDC_DEV_COLD) || | |
900 | (next > QLC_83XX_IDC_DEV_QUISCENT)) { | |
901 | dev_err(&adapter->pdev->dev, | |
902 | "%s: curr %d, prev %d, next state %d is invalid\n", | |
903 | __func__, cur, prev, state); | |
904 | return 1; | |
905 | } | |
906 | ||
907 | if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) && | |
908 | (prev == QLC_83XX_IDC_DEV_UNKNOWN)) { | |
909 | if ((next != QLC_83XX_IDC_DEV_COLD) && | |
910 | (next != QLC_83XX_IDC_DEV_READY)) { | |
911 | dev_err(&adapter->pdev->dev, | |
912 | "%s: failed, cur %d prev %d next %d\n", | |
913 | __func__, cur, prev, next); | |
914 | return 1; | |
915 | } | |
916 | } | |
917 | ||
918 | if (next == QLC_83XX_IDC_DEV_INIT) { | |
919 | if ((prev != QLC_83XX_IDC_DEV_INIT) && | |
920 | (prev != QLC_83XX_IDC_DEV_COLD) && | |
921 | (prev != QLC_83XX_IDC_DEV_NEED_RESET)) { | |
922 | dev_err(&adapter->pdev->dev, | |
923 | "%s: failed, cur %d prev %d next %d\n", | |
924 | __func__, cur, prev, next); | |
925 | return 1; | |
926 | } | |
927 | } | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter) | |
933 | { | |
934 | if (adapter->fhash.fnum) | |
935 | qlcnic_prune_lb_filters(adapter); | |
936 | } | |
937 | ||
938 | /** | |
939 | * qlcnic_83xx_idc_poll_dev_state | |
940 | * | |
941 | * @work: kernel work queue structure used to schedule the function | |
942 | * | |
943 | * Poll device state periodically and perform state specific | |
944 | * actions defined by Inter Driver Communication (IDC) protocol. | |
945 | * | |
946 | * Returns: None | |
947 | * | |
948 | **/ | |
949 | void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work) | |
950 | { | |
951 | struct qlcnic_adapter *adapter; | |
952 | u32 state; | |
953 | ||
954 | adapter = container_of(work, struct qlcnic_adapter, fw_work.work); | |
955 | state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); | |
956 | ||
957 | if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { | |
958 | qlcnic_83xx_idc_log_state_history(adapter); | |
959 | adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; | |
960 | } else { | |
961 | adapter->ahw->idc.curr_state = state; | |
962 | } | |
963 | ||
964 | switch (adapter->ahw->idc.curr_state) { | |
965 | case QLC_83XX_IDC_DEV_READY: | |
966 | qlcnic_83xx_idc_ready_state(adapter); | |
967 | break; | |
968 | case QLC_83XX_IDC_DEV_NEED_RESET: | |
969 | qlcnic_83xx_idc_need_reset_state(adapter); | |
970 | break; | |
971 | case QLC_83XX_IDC_DEV_NEED_QUISCENT: | |
972 | qlcnic_83xx_idc_need_quiesce_state(adapter); | |
973 | break; | |
974 | case QLC_83XX_IDC_DEV_FAILED: | |
975 | qlcnic_83xx_idc_failed_state(adapter); | |
976 | return; | |
977 | case QLC_83XX_IDC_DEV_INIT: | |
978 | qlcnic_83xx_idc_init_state(adapter); | |
979 | break; | |
980 | case QLC_83XX_IDC_DEV_QUISCENT: | |
981 | qlcnic_83xx_idc_quiesce_state(adapter); | |
982 | break; | |
983 | default: | |
984 | qlcnic_83xx_idc_unknown_state(adapter); | |
985 | return; | |
986 | } | |
987 | adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state; | |
988 | qlcnic_83xx_periodic_tasks(adapter); | |
989 | ||
990 | /* Re-schedule the function */ | |
991 | if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status)) | |
992 | qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, | |
993 | adapter->ahw->idc.delay); | |
994 | } | |
995 | ||
996 | static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter) | |
997 | { | |
998 | u32 idc_params, val; | |
999 | ||
1000 | if (qlcnic_83xx_lockless_flash_read32(adapter, | |
1001 | QLC_83XX_IDC_FLASH_PARAM_ADDR, | |
1002 | (u8 *)&idc_params, 1)) { | |
1003 | dev_info(&adapter->pdev->dev, | |
1004 | "%s:failed to get IDC params from flash\n", __func__); | |
1005 | adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS; | |
1006 | adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS; | |
1007 | } else { | |
1008 | adapter->dev_init_timeo = idc_params & 0xFFFF; | |
1009 | adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF); | |
1010 | } | |
1011 | ||
1012 | adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; | |
1013 | adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN; | |
1014 | adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; | |
1015 | adapter->ahw->idc.err_code = 0; | |
1016 | adapter->ahw->idc.collect_dump = 0; | |
1017 | adapter->ahw->idc.name = (char **)qlc_83xx_idc_states; | |
1018 | ||
1019 | clear_bit(__QLCNIC_RESETTING, &adapter->state); | |
1020 | set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); | |
1021 | set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); | |
1022 | ||
1023 | /* Check if reset recovery is disabled */ | |
1024 | if (!qlcnic_auto_fw_reset) { | |
1025 | /* Propagate do not reset request to other functions */ | |
1026 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); | |
1027 | val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; | |
1028 | QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | static int | |
1033 | qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter) | |
1034 | { | |
1035 | u32 state, val; | |
1036 | ||
1037 | if (qlcnic_83xx_lock_driver(adapter)) | |
1038 | return -EIO; | |
1039 | ||
1040 | /* Clear driver lock register */ | |
1041 | QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0); | |
1042 | if (qlcnic_83xx_idc_update_major_version(adapter, 0)) { | |
1043 | qlcnic_83xx_unlock_driver(adapter); | |
1044 | return -EIO; | |
1045 | } | |
1046 | ||
1047 | state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); | |
1048 | if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { | |
1049 | qlcnic_83xx_unlock_driver(adapter); | |
1050 | return -EIO; | |
1051 | } | |
1052 | ||
1053 | if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) { | |
1054 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, | |
1055 | QLC_83XX_IDC_DEV_COLD); | |
1056 | state = QLC_83XX_IDC_DEV_COLD; | |
1057 | } | |
1058 | ||
1059 | adapter->ahw->idc.curr_state = state; | |
1060 | /* First to load function should cold boot the device */ | |
1061 | if (state == QLC_83XX_IDC_DEV_COLD) | |
1062 | qlcnic_83xx_idc_cold_state_handler(adapter); | |
1063 | ||
1064 | /* Check if reset recovery is enabled */ | |
1065 | if (qlcnic_auto_fw_reset) { | |
1066 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); | |
1067 | val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; | |
1068 | QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); | |
1069 | } | |
1070 | ||
1071 | qlcnic_83xx_unlock_driver(adapter); | |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter) | |
1077 | { | |
81d0aeb0 SC |
1078 | int ret = -EIO; |
1079 | ||
629263ac SC |
1080 | qlcnic_83xx_setup_idc_parameters(adapter); |
1081 | ||
81d0aeb0 SC |
1082 | if (qlcnic_83xx_get_reset_instruction_template(adapter)) |
1083 | return ret; | |
1084 | ||
629263ac SC |
1085 | if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) { |
1086 | if (qlcnic_83xx_idc_first_to_load_function_handler(adapter)) | |
1087 | return -EIO; | |
1088 | } else { | |
1089 | if (qlcnic_83xx_idc_check_major_version(adapter)) | |
1090 | return -EIO; | |
1091 | } | |
1092 | ||
1093 | qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); | |
1094 | ||
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter) | |
1099 | { | |
1100 | int id; | |
1101 | u32 val; | |
1102 | ||
1103 | while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) | |
1104 | usleep_range(10000, 11000); | |
1105 | ||
1106 | id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); | |
1107 | id = id & 0xFF; | |
1108 | ||
1109 | if (id == adapter->portnum) { | |
1110 | dev_err(&adapter->pdev->dev, | |
1111 | "%s: wait for lock recovery.. %d\n", __func__, id); | |
1112 | msleep(20); | |
1113 | id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); | |
1114 | id = id & 0xFF; | |
1115 | } | |
1116 | ||
1117 | /* Clear driver presence bit */ | |
1118 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); | |
1119 | val = val & ~(1 << adapter->portnum); | |
1120 | QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); | |
1121 | clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); | |
1122 | clear_bit(__QLCNIC_RESETTING, &adapter->state); | |
1123 | ||
1124 | cancel_delayed_work_sync(&adapter->fw_work); | |
1125 | } | |
1126 | ||
1127 | void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key) | |
1128 | { | |
1129 | u32 val; | |
1130 | ||
1131 | if (qlcnic_83xx_lock_driver(adapter)) { | |
1132 | dev_err(&adapter->pdev->dev, | |
1133 | "%s:failed, please retry\n", __func__); | |
1134 | return; | |
1135 | } | |
1136 | ||
1137 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); | |
1138 | if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) || | |
1139 | !qlcnic_auto_fw_reset) { | |
1140 | dev_err(&adapter->pdev->dev, | |
1141 | "%s:failed, device in non reset mode\n", __func__); | |
1142 | qlcnic_83xx_unlock_driver(adapter); | |
1143 | return; | |
1144 | } | |
1145 | ||
1146 | if (key == QLCNIC_FORCE_FW_RESET) { | |
1147 | val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); | |
1148 | val = val | QLC_83XX_IDC_GRACEFULL_RESET; | |
1149 | QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); | |
1150 | } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) { | |
1151 | adapter->ahw->idc.collect_dump = 1; | |
1152 | } | |
1153 | ||
1154 | qlcnic_83xx_unlock_driver(adapter); | |
1155 | return; | |
1156 | } | |
1157 | ||
1158 | static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter) | |
1159 | { | |
1160 | u8 *p_cache; | |
1161 | u32 src, size; | |
1162 | u64 dest; | |
1163 | int ret = -EIO; | |
1164 | ||
1165 | src = QLC_83XX_BOOTLOADER_FLASH_ADDR; | |
1166 | dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR); | |
1167 | size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE); | |
1168 | ||
1169 | /* alignment check */ | |
1170 | if (size & 0xF) | |
1171 | size = (size + 16) & ~0xF; | |
1172 | ||
1173 | p_cache = kzalloc(size, GFP_KERNEL); | |
1174 | ||
1175 | if (p_cache == NULL) { | |
1176 | dev_err(&adapter->pdev->dev, | |
1177 | "Failed to allocate memory for boot loader cache\n"); | |
1178 | return -ENOMEM; | |
1179 | } | |
1180 | ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache, | |
1181 | size / sizeof(u32)); | |
1182 | if (ret) { | |
1183 | kfree(p_cache); | |
1184 | return ret; | |
1185 | } | |
1186 | /* 16 byte write to MS memory */ | |
1187 | ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache, | |
1188 | size / 16); | |
1189 | if (ret) { | |
1190 | kfree(p_cache); | |
1191 | return ret; | |
1192 | } | |
1193 | kfree(p_cache); | |
1194 | ||
1195 | return ret; | |
1196 | } | |
1197 | ||
1198 | static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) | |
1199 | { | |
1200 | u32 dest, *p_cache; | |
1201 | u64 addr; | |
1202 | u8 data[16]; | |
1203 | size_t size; | |
1204 | int i, ret = -EIO; | |
1205 | ||
1206 | dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR); | |
1207 | size = (adapter->ahw->fw_info.fw->size & ~0xF); | |
1208 | p_cache = (u32 *)adapter->ahw->fw_info.fw->data; | |
1209 | addr = (u64)dest; | |
1210 | ||
1211 | ret = qlcnic_83xx_ms_mem_write128(adapter, addr, | |
1212 | (u32 *)p_cache, size / 16); | |
1213 | if (ret) { | |
1214 | dev_err(&adapter->pdev->dev, "MS memory write failed\n"); | |
1215 | release_firmware(adapter->ahw->fw_info.fw); | |
1216 | adapter->ahw->fw_info.fw = NULL; | |
1217 | return -EIO; | |
1218 | } | |
1219 | ||
1220 | /* alignment check */ | |
1221 | if (adapter->ahw->fw_info.fw->size & 0xF) { | |
1222 | addr = dest + size; | |
1223 | for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++) | |
1224 | data[i] = adapter->ahw->fw_info.fw->data[size + i]; | |
1225 | for (; i < 16; i++) | |
1226 | data[i] = 0; | |
1227 | ret = qlcnic_83xx_ms_mem_write128(adapter, addr, | |
1228 | (u32 *)data, 1); | |
1229 | if (ret) { | |
1230 | dev_err(&adapter->pdev->dev, | |
1231 | "MS memory write failed\n"); | |
1232 | release_firmware(adapter->ahw->fw_info.fw); | |
1233 | adapter->ahw->fw_info.fw = NULL; | |
1234 | return -EIO; | |
1235 | } | |
1236 | } | |
1237 | release_firmware(adapter->ahw->fw_info.fw); | |
1238 | adapter->ahw->fw_info.fw = NULL; | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) | |
1244 | { | |
1245 | int i, j; | |
1246 | u32 val = 0, val1 = 0, reg = 0; | |
1247 | ||
1248 | val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG); | |
1249 | dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); | |
1250 | ||
1251 | for (j = 0; j < 2; j++) { | |
1252 | if (j == 0) { | |
1253 | dev_info(&adapter->pdev->dev, | |
1254 | "Port 0 RxB Pause Threshold Regs[TC7..TC0]:"); | |
1255 | reg = QLC_83XX_PORT0_THRESHOLD; | |
1256 | } else if (j == 1) { | |
1257 | dev_info(&adapter->pdev->dev, | |
1258 | "Port 1 RxB Pause Threshold Regs[TC7..TC0]:"); | |
1259 | reg = QLC_83XX_PORT1_THRESHOLD; | |
1260 | } | |
1261 | for (i = 0; i < 8; i++) { | |
1262 | val = QLCRD32(adapter, reg + (i * 0x4)); | |
1263 | dev_info(&adapter->pdev->dev, "0x%x ", val); | |
1264 | } | |
1265 | dev_info(&adapter->pdev->dev, "\n"); | |
1266 | } | |
1267 | ||
1268 | for (j = 0; j < 2; j++) { | |
1269 | if (j == 0) { | |
1270 | dev_info(&adapter->pdev->dev, | |
1271 | "Port 0 RxB TC Max Cell Registers[4..1]:"); | |
1272 | reg = QLC_83XX_PORT0_TC_MC_REG; | |
1273 | } else if (j == 1) { | |
1274 | dev_info(&adapter->pdev->dev, | |
1275 | "Port 1 RxB TC Max Cell Registers[4..1]:"); | |
1276 | reg = QLC_83XX_PORT1_TC_MC_REG; | |
1277 | } | |
1278 | for (i = 0; i < 4; i++) { | |
1279 | val = QLCRD32(adapter, reg + (i * 0x4)); | |
1280 | dev_info(&adapter->pdev->dev, "0x%x ", val); | |
1281 | } | |
1282 | dev_info(&adapter->pdev->dev, "\n"); | |
1283 | } | |
1284 | ||
1285 | for (j = 0; j < 2; j++) { | |
1286 | if (j == 0) { | |
1287 | dev_info(&adapter->pdev->dev, | |
1288 | "Port 0 RxB Rx TC Stats[TC7..TC0]:"); | |
1289 | reg = QLC_83XX_PORT0_TC_STATS; | |
1290 | } else if (j == 1) { | |
1291 | dev_info(&adapter->pdev->dev, | |
1292 | "Port 1 RxB Rx TC Stats[TC7..TC0]:"); | |
1293 | reg = QLC_83XX_PORT1_TC_STATS; | |
1294 | } | |
1295 | for (i = 7; i >= 0; i--) { | |
1296 | val = QLCRD32(adapter, reg); | |
1297 | val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ | |
1298 | QLCWR32(adapter, reg, (val | (i << 29))); | |
1299 | val = QLCRD32(adapter, reg); | |
1300 | dev_info(&adapter->pdev->dev, "0x%x ", val); | |
1301 | } | |
1302 | dev_info(&adapter->pdev->dev, "\n"); | |
1303 | } | |
1304 | ||
1305 | val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD); | |
1306 | val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD); | |
1307 | dev_info(&adapter->pdev->dev, | |
1308 | "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", | |
1309 | val, val1); | |
1310 | } | |
1311 | ||
81d0aeb0 | 1312 | |
629263ac SC |
1313 | static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter) |
1314 | { | |
1315 | u32 reg = 0, i, j; | |
1316 | ||
1317 | if (qlcnic_83xx_lock_driver(adapter)) { | |
1318 | dev_err(&adapter->pdev->dev, | |
1319 | "%s:failed to acquire driver lock\n", __func__); | |
1320 | return; | |
1321 | } | |
1322 | ||
1323 | qlcnic_83xx_dump_pause_control_regs(adapter); | |
1324 | QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0); | |
1325 | ||
1326 | for (j = 0; j < 2; j++) { | |
1327 | if (j == 0) | |
1328 | reg = QLC_83XX_PORT0_THRESHOLD; | |
1329 | else if (j == 1) | |
1330 | reg = QLC_83XX_PORT1_THRESHOLD; | |
1331 | ||
1332 | for (i = 0; i < 8; i++) | |
1333 | QLCWR32(adapter, reg + (i * 0x4), 0x0); | |
1334 | } | |
1335 | ||
1336 | for (j = 0; j < 2; j++) { | |
1337 | if (j == 0) | |
1338 | reg = QLC_83XX_PORT0_TC_MC_REG; | |
1339 | else if (j == 1) | |
1340 | reg = QLC_83XX_PORT1_TC_MC_REG; | |
1341 | ||
1342 | for (i = 0; i < 4; i++) | |
1343 | QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); | |
1344 | } | |
1345 | ||
1346 | QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0); | |
1347 | QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0); | |
1348 | dev_info(&adapter->pdev->dev, | |
1349 | "Disabled pause frames successfully on all ports\n"); | |
1350 | qlcnic_83xx_unlock_driver(adapter); | |
1351 | } | |
1352 | ||
1353 | static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) | |
1354 | { | |
1355 | u32 heartbeat, peg_status; | |
1356 | int retries, ret = -EIO; | |
1357 | ||
1358 | retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; | |
1359 | p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, | |
1360 | QLCNIC_PEG_ALIVE_COUNTER); | |
1361 | ||
1362 | do { | |
1363 | msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS); | |
1364 | heartbeat = QLC_SHARED_REG_RD32(p_dev, | |
1365 | QLCNIC_PEG_ALIVE_COUNTER); | |
1366 | if (heartbeat != p_dev->heartbeat) { | |
1367 | ret = QLCNIC_RCODE_SUCCESS; | |
1368 | break; | |
1369 | } | |
1370 | } while (--retries); | |
1371 | ||
1372 | if (ret) { | |
1373 | dev_err(&p_dev->pdev->dev, "firmware hang detected\n"); | |
1374 | qlcnic_83xx_disable_pause_frames(p_dev); | |
1375 | peg_status = QLC_SHARED_REG_RD32(p_dev, | |
1376 | QLCNIC_PEG_HALT_STATUS1); | |
1377 | dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n" | |
1378 | "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" | |
1379 | "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" | |
1380 | "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" | |
1381 | "PEG_NET_4_PC: 0x%x\n", peg_status, | |
1382 | QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), | |
1383 | QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0), | |
1384 | QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1), | |
1385 | QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2), | |
1386 | QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3), | |
1387 | QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4)); | |
1388 | ||
1389 | if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) | |
1390 | dev_err(&p_dev->pdev->dev, | |
1391 | "Device is being reset err code 0x00006700.\n"); | |
1392 | } | |
1393 | ||
1394 | return ret; | |
1395 | } | |
1396 | ||
1397 | static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev) | |
1398 | { | |
1399 | int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT; | |
1400 | u32 val; | |
1401 | ||
1402 | do { | |
1403 | val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); | |
1404 | if (val == QLC_83XX_CMDPEG_COMPLETE) | |
1405 | return 0; | |
1406 | msleep(QLCNIC_CMDPEG_CHECK_DELAY); | |
1407 | } while (--retries); | |
1408 | ||
1409 | dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); | |
1410 | return -EIO; | |
1411 | } | |
1412 | ||
1413 | int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) | |
1414 | { | |
1415 | int err; | |
1416 | ||
1417 | err = qlcnic_83xx_check_cmd_peg_status(p_dev); | |
1418 | if (err) | |
1419 | return err; | |
1420 | ||
1421 | err = qlcnic_83xx_check_heartbeat(p_dev); | |
1422 | if (err) | |
1423 | return err; | |
1424 | ||
1425 | return err; | |
1426 | } | |
1427 | ||
81d0aeb0 SC |
1428 | static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, |
1429 | int duration, u32 mask, u32 status) | |
1430 | { | |
1431 | u32 value; | |
1432 | int timeout_error; | |
1433 | u8 retries; | |
1434 | ||
1435 | value = qlcnic_83xx_rd_reg_indirect(p_dev, addr); | |
1436 | retries = duration / 10; | |
1437 | ||
1438 | do { | |
1439 | if ((value & mask) != status) { | |
1440 | timeout_error = 1; | |
1441 | msleep(duration / 10); | |
1442 | value = qlcnic_83xx_rd_reg_indirect(p_dev, addr); | |
1443 | } else { | |
1444 | timeout_error = 0; | |
1445 | break; | |
1446 | } | |
1447 | } while (retries--); | |
1448 | ||
1449 | if (timeout_error) { | |
1450 | p_dev->ahw->reset.seq_error++; | |
1451 | dev_err(&p_dev->pdev->dev, | |
1452 | "%s: Timeout Err, entry_num = %d\n", | |
1453 | __func__, p_dev->ahw->reset.seq_index); | |
1454 | dev_err(&p_dev->pdev->dev, | |
1455 | "0x%08x 0x%08x 0x%08x\n", | |
1456 | value, mask, status); | |
1457 | } | |
1458 | ||
1459 | return timeout_error; | |
1460 | } | |
1461 | ||
1462 | static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev) | |
1463 | { | |
1464 | u32 sum = 0; | |
1465 | u16 *buff = (u16 *)p_dev->ahw->reset.buff; | |
1466 | int count = p_dev->ahw->reset.hdr->size / sizeof(u16); | |
1467 | ||
1468 | while (count-- > 0) | |
1469 | sum += *buff++; | |
1470 | ||
1471 | while (sum >> 16) | |
1472 | sum = (sum & 0xFFFF) + (sum >> 16); | |
1473 | ||
1474 | if (~sum) { | |
1475 | return 0; | |
1476 | } else { | |
1477 | dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); | |
1478 | return -1; | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) | |
1483 | { | |
1484 | u8 *p_buff; | |
1485 | u32 addr, count; | |
1486 | struct qlcnic_hardware_context *ahw = p_dev->ahw; | |
1487 | ||
1488 | ahw->reset.seq_error = 0; | |
1489 | ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); | |
1490 | ||
1491 | if (p_dev->ahw->reset.buff == NULL) { | |
1492 | dev_err(&p_dev->pdev->dev, | |
1493 | "%s: resource allocation failed\n", __func__); | |
1494 | return -ENOMEM; | |
1495 | } | |
1496 | p_buff = p_dev->ahw->reset.buff; | |
1497 | addr = QLC_83XX_RESET_TEMPLATE_ADDR; | |
1498 | count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32); | |
1499 | ||
1500 | /* Copy template header from flash */ | |
1501 | if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { | |
1502 | dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); | |
1503 | return -EIO; | |
1504 | } | |
1505 | ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; | |
1506 | addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; | |
1507 | p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; | |
1508 | count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); | |
1509 | ||
1510 | /* Copy rest of the template */ | |
1511 | if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { | |
1512 | dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); | |
1513 | return -EIO; | |
1514 | } | |
1515 | ||
1516 | if (qlcnic_83xx_reset_template_checksum(p_dev)) | |
1517 | return -EIO; | |
1518 | /* Get Stop, Start and Init command offsets */ | |
1519 | ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; | |
1520 | ahw->reset.start_offset = ahw->reset.buff + | |
1521 | ahw->reset.hdr->start_offset; | |
1522 | ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; | |
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | /* Read Write HW register command */ | |
1527 | static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, | |
1528 | u32 raddr, u32 waddr) | |
1529 | { | |
1530 | int value; | |
1531 | ||
1532 | value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr); | |
1533 | qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); | |
1534 | } | |
1535 | ||
1536 | /* Read Modify Write HW register command */ | |
1537 | static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, | |
1538 | u32 raddr, u32 waddr, | |
1539 | struct qlc_83xx_rmw *p_rmw_hdr) | |
1540 | { | |
1541 | int value; | |
1542 | ||
1543 | if (p_rmw_hdr->index_a) | |
1544 | value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; | |
1545 | else | |
1546 | value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr); | |
1547 | ||
1548 | value &= p_rmw_hdr->mask; | |
1549 | value <<= p_rmw_hdr->shl; | |
1550 | value >>= p_rmw_hdr->shr; | |
1551 | value |= p_rmw_hdr->or_value; | |
1552 | value ^= p_rmw_hdr->xor_value; | |
1553 | qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); | |
1554 | } | |
1555 | ||
1556 | /* Write HW register command */ | |
1557 | static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev, | |
1558 | struct qlc_83xx_entry_hdr *p_hdr) | |
1559 | { | |
1560 | int i; | |
1561 | struct qlc_83xx_entry *entry; | |
1562 | ||
1563 | entry = (struct qlc_83xx_entry *)((char *)p_hdr + | |
1564 | sizeof(struct qlc_83xx_entry_hdr)); | |
1565 | ||
1566 | for (i = 0; i < p_hdr->count; i++, entry++) { | |
1567 | qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1, | |
1568 | entry->arg2); | |
1569 | if (p_hdr->delay) | |
1570 | udelay((u32)(p_hdr->delay)); | |
1571 | } | |
1572 | } | |
1573 | ||
1574 | /* Read and Write instruction */ | |
1575 | static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev, | |
1576 | struct qlc_83xx_entry_hdr *p_hdr) | |
1577 | { | |
1578 | int i; | |
1579 | struct qlc_83xx_entry *entry; | |
1580 | ||
1581 | entry = (struct qlc_83xx_entry *)((char *)p_hdr + | |
1582 | sizeof(struct qlc_83xx_entry_hdr)); | |
1583 | ||
1584 | for (i = 0; i < p_hdr->count; i++, entry++) { | |
1585 | qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1, | |
1586 | entry->arg2); | |
1587 | if (p_hdr->delay) | |
1588 | udelay((u32)(p_hdr->delay)); | |
1589 | } | |
1590 | } | |
1591 | ||
1592 | /* Poll HW register command */ | |
1593 | static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, | |
1594 | struct qlc_83xx_entry_hdr *p_hdr) | |
1595 | { | |
1596 | long delay; | |
1597 | struct qlc_83xx_entry *entry; | |
1598 | struct qlc_83xx_poll *poll; | |
1599 | int i; | |
1600 | unsigned long arg1, arg2; | |
1601 | ||
1602 | poll = (struct qlc_83xx_poll *)((char *)p_hdr + | |
1603 | sizeof(struct qlc_83xx_entry_hdr)); | |
1604 | ||
1605 | entry = (struct qlc_83xx_entry *)((char *)poll + | |
1606 | sizeof(struct qlc_83xx_poll)); | |
1607 | delay = (long)p_hdr->delay; | |
1608 | ||
1609 | if (!delay) { | |
1610 | for (i = 0; i < p_hdr->count; i++, entry++) | |
1611 | qlcnic_83xx_poll_reg(p_dev, entry->arg1, | |
1612 | delay, poll->mask, | |
1613 | poll->status); | |
1614 | } else { | |
1615 | for (i = 0; i < p_hdr->count; i++, entry++) { | |
1616 | arg1 = entry->arg1; | |
1617 | arg2 = entry->arg2; | |
1618 | if (delay) { | |
1619 | if (qlcnic_83xx_poll_reg(p_dev, | |
1620 | arg1, delay, | |
1621 | poll->mask, | |
1622 | poll->status)){ | |
1623 | qlcnic_83xx_rd_reg_indirect(p_dev, | |
1624 | arg1); | |
1625 | qlcnic_83xx_rd_reg_indirect(p_dev, | |
1626 | arg2); | |
1627 | } | |
1628 | } | |
1629 | } | |
1630 | } | |
1631 | } | |
1632 | ||
1633 | /* Poll and write HW register command */ | |
1634 | static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev, | |
1635 | struct qlc_83xx_entry_hdr *p_hdr) | |
1636 | { | |
1637 | int i; | |
1638 | long delay; | |
1639 | struct qlc_83xx_quad_entry *entry; | |
1640 | struct qlc_83xx_poll *poll; | |
1641 | ||
1642 | poll = (struct qlc_83xx_poll *)((char *)p_hdr + | |
1643 | sizeof(struct qlc_83xx_entry_hdr)); | |
1644 | entry = (struct qlc_83xx_quad_entry *)((char *)poll + | |
1645 | sizeof(struct qlc_83xx_poll)); | |
1646 | delay = (long)p_hdr->delay; | |
1647 | ||
1648 | for (i = 0; i < p_hdr->count; i++, entry++) { | |
1649 | qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr, | |
1650 | entry->dr_value); | |
1651 | qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, | |
1652 | entry->ar_value); | |
1653 | if (delay) | |
1654 | qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, | |
1655 | poll->mask, poll->status); | |
1656 | } | |
1657 | } | |
1658 | ||
1659 | /* Read Modify Write register command */ | |
1660 | static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev, | |
1661 | struct qlc_83xx_entry_hdr *p_hdr) | |
1662 | { | |
1663 | int i; | |
1664 | struct qlc_83xx_entry *entry; | |
1665 | struct qlc_83xx_rmw *rmw_hdr; | |
1666 | ||
1667 | rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr + | |
1668 | sizeof(struct qlc_83xx_entry_hdr)); | |
1669 | ||
1670 | entry = (struct qlc_83xx_entry *)((char *)rmw_hdr + | |
1671 | sizeof(struct qlc_83xx_rmw)); | |
1672 | ||
1673 | for (i = 0; i < p_hdr->count; i++, entry++) { | |
1674 | qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1, | |
1675 | entry->arg2, rmw_hdr); | |
1676 | if (p_hdr->delay) | |
1677 | udelay((u32)(p_hdr->delay)); | |
1678 | } | |
1679 | } | |
1680 | ||
1681 | static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr) | |
1682 | { | |
1683 | if (p_hdr->delay) | |
1684 | mdelay((u32)((long)p_hdr->delay)); | |
1685 | } | |
1686 | ||
1687 | /* Read and poll register command */ | |
1688 | static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, | |
1689 | struct qlc_83xx_entry_hdr *p_hdr) | |
1690 | { | |
1691 | long delay; | |
1692 | int index, i, j; | |
1693 | struct qlc_83xx_quad_entry *entry; | |
1694 | struct qlc_83xx_poll *poll; | |
1695 | unsigned long addr; | |
1696 | ||
1697 | poll = (struct qlc_83xx_poll *)((char *)p_hdr + | |
1698 | sizeof(struct qlc_83xx_entry_hdr)); | |
1699 | ||
1700 | entry = (struct qlc_83xx_quad_entry *)((char *)poll + | |
1701 | sizeof(struct qlc_83xx_poll)); | |
1702 | delay = (long)p_hdr->delay; | |
1703 | ||
1704 | for (i = 0; i < p_hdr->count; i++, entry++) { | |
1705 | qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, | |
1706 | entry->ar_value); | |
1707 | if (delay) { | |
1708 | if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, | |
1709 | poll->mask, poll->status)){ | |
1710 | index = p_dev->ahw->reset.array_index; | |
1711 | addr = entry->dr_addr; | |
1712 | j = qlcnic_83xx_rd_reg_indirect(p_dev, addr); | |
1713 | p_dev->ahw->reset.array[index++] = j; | |
1714 | ||
1715 | if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) | |
1716 | p_dev->ahw->reset.array_index = 1; | |
1717 | } | |
1718 | } | |
1719 | } | |
1720 | } | |
1721 | ||
1722 | static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev) | |
1723 | { | |
1724 | p_dev->ahw->reset.seq_end = 1; | |
1725 | } | |
1726 | ||
1727 | static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev) | |
1728 | { | |
1729 | p_dev->ahw->reset.template_end = 1; | |
1730 | if (p_dev->ahw->reset.seq_error == 0) | |
1731 | dev_err(&p_dev->pdev->dev, | |
1732 | "HW restart process completed successfully.\n"); | |
1733 | else | |
1734 | dev_err(&p_dev->pdev->dev, | |
1735 | "HW restart completed with timeout errors.\n"); | |
1736 | } | |
1737 | ||
1738 | /** | |
1739 | * qlcnic_83xx_exec_template_cmd | |
1740 | * | |
1741 | * @p_dev: adapter structure | |
1742 | * @p_buff: Poiter to instruction template | |
1743 | * | |
1744 | * Template provides instructions to stop, restart and initalize firmware. | |
1745 | * These instructions are abstracted as a series of read, write and | |
1746 | * poll operations on hardware registers. Register information and operation | |
1747 | * specifics are not exposed to the driver. Driver reads the template from | |
1748 | * flash and executes the instructions located at pre-defined offsets. | |
1749 | * | |
1750 | * Returns: None | |
1751 | * */ | |
1752 | static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev, | |
1753 | char *p_buff) | |
1754 | { | |
1755 | int index, entries; | |
1756 | struct qlc_83xx_entry_hdr *p_hdr; | |
1757 | char *entry = p_buff; | |
1758 | ||
1759 | p_dev->ahw->reset.seq_end = 0; | |
1760 | p_dev->ahw->reset.template_end = 0; | |
1761 | entries = p_dev->ahw->reset.hdr->entries; | |
1762 | index = p_dev->ahw->reset.seq_index; | |
1763 | ||
1764 | for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { | |
1765 | p_hdr = (struct qlc_83xx_entry_hdr *)entry; | |
1766 | ||
1767 | switch (p_hdr->cmd) { | |
1768 | case QLC_83XX_OPCODE_NOP: | |
1769 | break; | |
1770 | case QLC_83XX_OPCODE_WRITE_LIST: | |
1771 | qlcnic_83xx_write_list(p_dev, p_hdr); | |
1772 | break; | |
1773 | case QLC_83XX_OPCODE_READ_WRITE_LIST: | |
1774 | qlcnic_83xx_read_write_list(p_dev, p_hdr); | |
1775 | break; | |
1776 | case QLC_83XX_OPCODE_POLL_LIST: | |
1777 | qlcnic_83xx_poll_list(p_dev, p_hdr); | |
1778 | break; | |
1779 | case QLC_83XX_OPCODE_POLL_WRITE_LIST: | |
1780 | qlcnic_83xx_poll_write_list(p_dev, p_hdr); | |
1781 | break; | |
1782 | case QLC_83XX_OPCODE_READ_MODIFY_WRITE: | |
1783 | qlcnic_83xx_read_modify_write(p_dev, p_hdr); | |
1784 | break; | |
1785 | case QLC_83XX_OPCODE_SEQ_PAUSE: | |
1786 | qlcnic_83xx_pause(p_hdr); | |
1787 | break; | |
1788 | case QLC_83XX_OPCODE_SEQ_END: | |
1789 | qlcnic_83xx_seq_end(p_dev); | |
1790 | break; | |
1791 | case QLC_83XX_OPCODE_TMPL_END: | |
1792 | qlcnic_83xx_template_end(p_dev); | |
1793 | break; | |
1794 | case QLC_83XX_OPCODE_POLL_READ_LIST: | |
1795 | qlcnic_83xx_poll_read_list(p_dev, p_hdr); | |
1796 | break; | |
1797 | default: | |
1798 | dev_err(&p_dev->pdev->dev, | |
1799 | "%s: Unknown opcode 0x%04x in template %d\n", | |
1800 | __func__, p_hdr->cmd, index); | |
1801 | break; | |
1802 | } | |
1803 | entry += p_hdr->size; | |
1804 | } | |
1805 | p_dev->ahw->reset.seq_index = index; | |
1806 | } | |
1807 | ||
1808 | static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev) | |
1809 | { | |
1810 | p_dev->ahw->reset.seq_index = 0; | |
1811 | ||
1812 | qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); | |
1813 | if (p_dev->ahw->reset.seq_end != 1) | |
1814 | dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); | |
1815 | } | |
1816 | ||
1817 | static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev) | |
1818 | { | |
1819 | qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); | |
1820 | if (p_dev->ahw->reset.template_end != 1) | |
1821 | dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); | |
1822 | } | |
1823 | ||
1824 | static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev) | |
1825 | { | |
1826 | qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); | |
1827 | if (p_dev->ahw->reset.seq_end != 1) | |
1828 | dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); | |
1829 | } | |
1830 | ||
629263ac SC |
1831 | static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter) |
1832 | { | |
1833 | int err = -EIO; | |
1834 | ||
1835 | if (request_firmware(&adapter->ahw->fw_info.fw, | |
1836 | QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) { | |
1837 | dev_err(&adapter->pdev->dev, | |
1838 | "No file FW image, loading flash FW image.\n"); | |
1839 | QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, | |
1840 | QLC_83XX_BOOT_FROM_FLASH); | |
1841 | } else { | |
1842 | if (qlcnic_83xx_copy_fw_file(adapter)) | |
1843 | return err; | |
1844 | QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, | |
1845 | QLC_83XX_BOOT_FROM_FILE); | |
1846 | } | |
1847 | ||
1848 | return 0; | |
1849 | } | |
1850 | ||
1851 | static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter) | |
1852 | { | |
1853 | int err = -EIO; | |
1854 | ||
81d0aeb0 SC |
1855 | qlcnic_83xx_stop_hw(adapter); |
1856 | qlcnic_83xx_init_hw(adapter); | |
1857 | ||
629263ac SC |
1858 | if (qlcnic_83xx_copy_bootloader(adapter)) |
1859 | return err; | |
1860 | /* Boot either flash image or firmware image from host file system */ | |
1861 | if (qlcnic_load_fw_file) { | |
1862 | if (qlcnic_83xx_load_fw_image_from_host(adapter)) | |
1863 | return err; | |
1864 | } else { | |
1865 | QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, | |
1866 | QLC_83XX_BOOT_FROM_FLASH); | |
1867 | } | |
1868 | ||
81d0aeb0 | 1869 | qlcnic_83xx_start_hw(adapter); |
629263ac SC |
1870 | if (qlcnic_83xx_check_hw_status(adapter)) |
1871 | return -EIO; | |
1872 | ||
1873 | return 0; | |
1874 | } | |
1875 | ||
1876 | /** | |
1877 | * qlcnic_83xx_config_default_opmode | |
1878 | * | |
1879 | * @adapter: adapter structure | |
1880 | * | |
1881 | * Configure default driver operating mode | |
1882 | * | |
1883 | * Returns: Error code or Success(0) | |
1884 | * */ | |
1885 | int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter) | |
1886 | { | |
1887 | u32 op_mode; | |
1888 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
1889 | ||
1890 | qlcnic_get_func_no(adapter); | |
1891 | op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE); | |
1892 | ||
1893 | if (op_mode == QLC_83XX_DEFAULT_OPMODE) { | |
1894 | adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver; | |
1895 | ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; | |
1896 | } else { | |
1897 | return -EIO; | |
1898 | } | |
1899 | ||
1900 | return 0; | |
1901 | } | |
1902 | ||
1903 | int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter) | |
1904 | { | |
1905 | int err; | |
1906 | struct qlcnic_info nic_info; | |
1907 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
1908 | ||
1909 | memset(&nic_info, 0, sizeof(struct qlcnic_info)); | |
1910 | err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); | |
1911 | if (err) | |
1912 | return -EIO; | |
1913 | ||
1914 | ahw->physical_port = (u8) nic_info.phys_port; | |
1915 | ahw->switch_mode = nic_info.switch_mode; | |
1916 | ahw->max_tx_ques = nic_info.max_tx_ques; | |
1917 | ahw->max_rx_ques = nic_info.max_rx_ques; | |
1918 | ahw->capabilities = nic_info.capabilities; | |
1919 | ahw->max_mac_filters = nic_info.max_mac_filters; | |
1920 | ahw->max_mtu = nic_info.max_mtu; | |
1921 | ||
1922 | if (ahw->capabilities & BIT_23) | |
1923 | ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE; | |
1924 | else | |
1925 | ahw->nic_mode = QLC_83XX_DEFAULT_MODE; | |
1926 | ||
1927 | return ahw->nic_mode; | |
1928 | } | |
1929 | ||
1930 | static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter) | |
1931 | { | |
1932 | int ret; | |
1933 | ||
1934 | ret = qlcnic_83xx_get_nic_configuration(adapter); | |
1935 | if (ret == -EIO) | |
1936 | return -EIO; | |
1937 | ||
d71170fb SC |
1938 | if (ret == QLC_83XX_VIRTUAL_NIC_MODE) { |
1939 | if (qlcnic_83xx_config_vnic_opmode(adapter)) | |
1940 | return -EIO; | |
1941 | } else if (ret == QLC_83XX_DEFAULT_MODE) { | |
629263ac SC |
1942 | if (qlcnic_83xx_config_default_opmode(adapter)) |
1943 | return -EIO; | |
1944 | } | |
1945 | ||
1946 | return 0; | |
1947 | } | |
1948 | ||
1949 | static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter) | |
1950 | { | |
1951 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
1952 | ||
1953 | if (ahw->port_type == QLCNIC_XGBE) { | |
1954 | adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; | |
1955 | adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; | |
1956 | adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; | |
1957 | adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; | |
1958 | ||
1959 | } else if (ahw->port_type == QLCNIC_GBE) { | |
1960 | adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; | |
1961 | adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; | |
1962 | adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; | |
1963 | adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G; | |
1964 | } | |
1965 | adapter->num_txd = MAX_CMD_DESCRIPTORS; | |
1966 | adapter->max_rds_rings = MAX_RDS_RINGS; | |
1967 | } | |
1968 | ||
1969 | static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter) | |
1970 | { | |
1971 | int err = -EIO; | |
1972 | ||
1973 | if (qlcnic_83xx_get_port_info(adapter)) | |
1974 | return err; | |
1975 | ||
1976 | qlcnic_83xx_config_buff_descriptors(adapter); | |
1977 | adapter->ahw->msix_supported = !!qlcnic_use_msi_x; | |
1978 | adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; | |
1979 | ||
1980 | dev_info(&adapter->pdev->dev, "HAL Version: %d\n", | |
1981 | adapter->ahw->fw_hal_version); | |
1982 | ||
1983 | return 0; | |
1984 | } | |
1985 | ||
1986 | #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1)) | |
1987 | static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter) | |
1988 | { | |
1989 | struct qlcnic_cmd_args cmd; | |
1990 | u32 presence_mask, audit_mask; | |
1991 | int status; | |
1992 | ||
1993 | presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); | |
1994 | audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); | |
1995 | ||
1996 | if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) { | |
1997 | qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC); | |
1998 | cmd.req.arg[1] = BIT_31; | |
1999 | status = qlcnic_issue_cmd(adapter, &cmd); | |
2000 | if (status) | |
2001 | dev_err(&adapter->pdev->dev, | |
2002 | "Failed to clean up the function resources\n"); | |
2003 | qlcnic_free_mbx_args(&cmd); | |
2004 | } | |
2005 | } | |
2006 | ||
2007 | int qlcnic_83xx_init(struct qlcnic_adapter *adapter) | |
2008 | { | |
2009 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
2010 | ||
2011 | if (qlcnic_83xx_check_hw_status(adapter)) | |
2012 | return -EIO; | |
2013 | ||
2014 | /* Initilaize 83xx mailbox spinlock */ | |
2015 | spin_lock_init(&ahw->mbx_lock); | |
2016 | ||
2017 | set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status); | |
2018 | qlcnic_83xx_clear_function_resources(adapter); | |
2019 | ||
2020 | if (!qlcnic_83xx_read_flash_descriptor_table(adapter)) | |
2021 | qlcnic_83xx_read_flash_mfg_id(adapter); | |
2022 | ||
2023 | if (qlcnic_83xx_idc_init(adapter)) | |
2024 | return -EIO; | |
2025 | ||
2026 | /* Configure default, SR-IOV or Virtual NIC mode of operation */ | |
2027 | if (qlcnic_83xx_configure_opmode(adapter)) | |
2028 | return -EIO; | |
2029 | ||
2030 | /* Perform operating mode specific initialization */ | |
2031 | if (adapter->nic_ops->init_driver(adapter)) | |
2032 | return -EIO; | |
2033 | ||
2034 | INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); | |
2035 | ||
2036 | /* register for NIC IDC AEN Events */ | |
2037 | qlcnic_83xx_register_nic_idc_func(adapter, 1); | |
2038 | ||
2039 | /* Periodically monitor device status */ | |
2040 | qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work); | |
2041 | ||
2042 | return adapter->ahw->idc.err_code; | |
2043 | } |