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sh_eth: remove duplicate sh_eth_set_duplex() definitions
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
a3f109bd
SS		 5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
86a74ff2 24#include <linux/init.h>
0654011d
YS		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
6a27cded 28#include <linux/interrupt.h>
86a74ff2
NI		 29#include <linux/dma-mapping.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/mdio-bitbang.h>
34#include <linux/netdevice.h>
35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
86a74ff2
NI		 44
45#include "sh_eth.h"
46
dc19e4e5
NI		 47#define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
c0013f6f
SS		 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149};
150
a3f109bd
SS		 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
192 [FCFTR] = 0x0270,
193 [TRIMD] = 0x027c,
194};
195
c0013f6f
SS		 196static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
197 [ECMR] = 0x0100,
198 [RFLR] = 0x0108,
199 [ECSR] = 0x0110,
200 [ECSIPR] = 0x0118,
201 [PIR] = 0x0120,
202 [PSR] = 0x0128,
203 [RDMLR] = 0x0140,
204 [IPGR] = 0x0150,
205 [APR] = 0x0154,
206 [MPR] = 0x0158,
207 [TPAUSER] = 0x0164,
208 [RFCF] = 0x0160,
209 [TPAUSECR] = 0x0168,
210 [BCFRR] = 0x016c,
211 [MAHR] = 0x01c0,
212 [MALR] = 0x01c8,
213 [TROCR] = 0x01d0,
214 [CDCR] = 0x01d4,
215 [LCCR] = 0x01d8,
216 [CNDCR] = 0x01dc,
217 [CEFCR] = 0x01e4,
218 [FRECR] = 0x01e8,
219 [TSFRCR] = 0x01ec,
220 [TLFRCR] = 0x01f0,
221 [RFCR] = 0x01f4,
222 [MAFCR] = 0x01f8,
223 [RTRATE] = 0x01fc,
224
225 [EDMR] = 0x0000,
226 [EDTRR] = 0x0008,
227 [EDRRR] = 0x0010,
228 [TDLAR] = 0x0018,
229 [RDLAR] = 0x0020,
230 [EESR] = 0x0028,
231 [EESIPR] = 0x0030,
232 [TRSCER] = 0x0038,
233 [RMFCR] = 0x0040,
234 [TFTR] = 0x0048,
235 [FDR] = 0x0050,
236 [RMCR] = 0x0058,
237 [TFUCR] = 0x0064,
238 [RFOCR] = 0x0068,
239 [FCFTR] = 0x0070,
240 [RPADIR] = 0x0078,
241 [TRIMD] = 0x007c,
242 [RBWAR] = 0x00c8,
243 [RDFAR] = 0x00cc,
244 [TBRAR] = 0x00d4,
245 [TDFAR] = 0x00d8,
246};
247
248static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
249 [ECMR] = 0x0160,
250 [ECSR] = 0x0164,
251 [ECSIPR] = 0x0168,
252 [PIR] = 0x016c,
253 [MAHR] = 0x0170,
254 [MALR] = 0x0174,
255 [RFLR] = 0x0178,
256 [PSR] = 0x017c,
257 [TROCR] = 0x0180,
258 [CDCR] = 0x0184,
259 [LCCR] = 0x0188,
260 [CNDCR] = 0x018c,
261 [CEFCR] = 0x0194,
262 [FRECR] = 0x0198,
263 [TSFRCR] = 0x019c,
264 [TLFRCR] = 0x01a0,
265 [RFCR] = 0x01a4,
266 [MAFCR] = 0x01a8,
267 [IPGR] = 0x01b4,
268 [APR] = 0x01b8,
269 [MPR] = 0x01bc,
270 [TPAUSER] = 0x01c4,
271 [BCFR] = 0x01cc,
272
273 [ARSTR] = 0x0000,
274 [TSU_CTRST] = 0x0004,
275 [TSU_FWEN0] = 0x0010,
276 [TSU_FWEN1] = 0x0014,
277 [TSU_FCM] = 0x0018,
278 [TSU_BSYSL0] = 0x0020,
279 [TSU_BSYSL1] = 0x0024,
280 [TSU_PRISL0] = 0x0028,
281 [TSU_PRISL1] = 0x002c,
282 [TSU_FWSL0] = 0x0030,
283 [TSU_FWSL1] = 0x0034,
284 [TSU_FWSLC] = 0x0038,
285 [TSU_QTAGM0] = 0x0040,
286 [TSU_QTAGM1] = 0x0044,
287 [TSU_ADQT0] = 0x0048,
288 [TSU_ADQT1] = 0x004c,
289 [TSU_FWSR] = 0x0050,
290 [TSU_FWINMK] = 0x0054,
291 [TSU_ADSBSY] = 0x0060,
292 [TSU_TEN] = 0x0064,
293 [TSU_POST1] = 0x0070,
294 [TSU_POST2] = 0x0074,
295 [TSU_POST3] = 0x0078,
296 [TSU_POST4] = 0x007c,
297
298 [TXNLCR0] = 0x0080,
299 [TXALCR0] = 0x0084,
300 [RXNLCR0] = 0x0088,
301 [RXALCR0] = 0x008c,
302 [FWNLCR0] = 0x0090,
303 [FWALCR0] = 0x0094,
304 [TXNLCR1] = 0x00a0,
305 [TXALCR1] = 0x00a0,
306 [RXNLCR1] = 0x00a8,
307 [RXALCR1] = 0x00ac,
308 [FWNLCR1] = 0x00b0,
309 [FWALCR1] = 0x00b4,
310
311 [TSU_ADRH0] = 0x0100,
312 [TSU_ADRL0] = 0x0104,
313 [TSU_ADRL31] = 0x01fc,
314};
315
5e7a76be
NI		 316#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
317 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
318 defined(CONFIG_ARCH_R8A7740)
319static void sh_eth_select_mii(struct net_device *ndev)
320{
321 u32 value = 0x0;
322 struct sh_eth_private *mdp = netdev_priv(ndev);
323
324 switch (mdp->phy_interface) {
325 case PHY_INTERFACE_MODE_GMII:
326 value = 0x2;
327 break;
328 case PHY_INTERFACE_MODE_MII:
329 value = 0x1;
330 break;
331 case PHY_INTERFACE_MODE_RMII:
332 value = 0x0;
333 break;
334 default:
335 pr_warn("PHY interface mode was not setup. Set to MII.\n");
336 value = 0x1;
337 break;
338 }
339
340 sh_eth_write(ndev, value, RMII_MII);
341}
342#endif
343
04b0ed2a 344static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 345{
346 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 347
348 if (mdp->duplex) /* Full */
4a55530f 349 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 350 else /* Half */
4a55530f 351 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 352}
353
04b0ed2a
NI		 354/* There is CPU dependent code */
355#if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
356#define SH_ETH_RESET_DEFAULT 1
65ac8851
YS		 357static void sh_eth_set_rate(struct net_device *ndev)
358{
359 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 360
a3f109bd
SS		 361 switch (mdp->speed) {
362 case 10: /* 10BASE */
363 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
364 break;
365 case 100:/* 100BASE */
366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
367 break;
368 default:
369 break;
370 }
371}
372
674853b2 373/* R8A7778/9 */
a3f109bd
SS		 374static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
375 .set_duplex = sh_eth_set_duplex,
376 .set_rate = sh_eth_set_rate,
377
378 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
379 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
380 .eesipr_value = 0x01ff009f,
381
382 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
383 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
384 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
385 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
386
387 .apr = 1,
388 .mpr = 1,
389 .tpauser = 1,
390 .hw_swap = 1,
391};
392#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
393#define SH_ETH_RESET_DEFAULT 1
a3f109bd
SS		 394
395static void sh_eth_set_rate(struct net_device *ndev)
396{
397 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 398
399 switch (mdp->speed) {
400 case 10: /* 10BASE */
a3f109bd 401 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 402 break;
403 case 100:/* 100BASE */
a3f109bd 404 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 405 break;
406 default:
407 break;
408 }
409}
410
411/* SH7724 */
412static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
413 .set_duplex = sh_eth_set_duplex,
414 .set_rate = sh_eth_set_rate,
415
416 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
417 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
418 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
419
420 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
421 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
422 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
423 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
424
425 .apr = 1,
426 .mpr = 1,
427 .tpauser = 1,
428 .hw_swap = 1,
503914cf
MD		 429 .rpadir = 1,
430 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 431};
f29a3d04 432#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
8fcd4961
YS		 433#define SH_ETH_HAS_BOTH_MODULES 1
434#define SH_ETH_HAS_TSU 1
5cee1d37
NI		 435static int sh_eth_check_reset(struct net_device *ndev);
436
f29a3d04
YS		 437static void sh_eth_set_rate(struct net_device *ndev)
438{
439 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 440
441 switch (mdp->speed) {
442 case 10: /* 10BASE */
4a55530f 443 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 444 break;
445 case 100:/* 100BASE */
4a55530f 446 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 447 break;
448 default:
449 break;
450 }
451}
452
453/* SH7757 */
454static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
455 .set_duplex = sh_eth_set_duplex,
456 .set_rate = sh_eth_set_rate,
457
458 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
459 .rmcr_value = 0x00000001,
460
461 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
462 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
463 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
464 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
465
466 .apr = 1,
467 .mpr = 1,
468 .tpauser = 1,
469 .hw_swap = 1,
470 .no_ade = 1,
2e98e797
YS		 471 .rpadir = 1,
472 .rpadir_value = 2 << 16,
f29a3d04 473};
65ac8851 474
8fcd4961
YS		 475#define SH_GIGA_ETH_BASE 0xfee00000
476#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
477#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
478static void sh_eth_chip_reset_giga(struct net_device *ndev)
479{
480 int i;
481 unsigned long mahr[2], malr[2];
482
483 /* save MAHR and MALR */
484 for (i = 0; i < 2; i++) {
ae70644d
YS		 485 malr[i] = ioread32((void *)GIGA_MALR(i));
486 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 487 }
488
489 /* reset device */
ae70644d 490 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 491 mdelay(1);
492
493 /* restore MAHR and MALR */
494 for (i = 0; i < 2; i++) {
ae70644d
YS		 495 iowrite32(malr[i], (void *)GIGA_MALR(i));
496 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 497 }
498}
499
500static int sh_eth_is_gether(struct sh_eth_private *mdp);
5cee1d37 501static int sh_eth_reset(struct net_device *ndev)
8fcd4961
YS		 502{
503 struct sh_eth_private *mdp = netdev_priv(ndev);
5cee1d37 504 int ret = 0;
8fcd4961
YS		 505
506 if (sh_eth_is_gether(mdp)) {
ddcd91c6 507 sh_eth_write(ndev, EDSR_ENALL, EDSR);
8fcd4961
YS		 508 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
509 EDMR);
5cee1d37
NI		 510
511 ret = sh_eth_check_reset(ndev);
512 if (ret)
513 goto out;
8fcd4961
YS		 514
515 /* Table Init */
516 sh_eth_write(ndev, 0x0, TDLAR);
517 sh_eth_write(ndev, 0x0, TDFAR);
518 sh_eth_write(ndev, 0x0, TDFXR);
519 sh_eth_write(ndev, 0x0, TDFFR);
520 sh_eth_write(ndev, 0x0, RDLAR);
521 sh_eth_write(ndev, 0x0, RDFAR);
522 sh_eth_write(ndev, 0x0, RDFXR);
523 sh_eth_write(ndev, 0x0, RDFFR);
524 } else {
525 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
526 EDMR);
527 mdelay(3);
528 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
529 EDMR);
530 }
5cee1d37
NI		 531
532out:
533 return ret;
8fcd4961
YS		 534}
535
8fcd4961
YS		 536static void sh_eth_set_rate_giga(struct net_device *ndev)
537{
538 struct sh_eth_private *mdp = netdev_priv(ndev);
539
540 switch (mdp->speed) {
541 case 10: /* 10BASE */
542 sh_eth_write(ndev, 0x00000000, GECMR);
543 break;
544 case 100:/* 100BASE */
545 sh_eth_write(ndev, 0x00000010, GECMR);
546 break;
547 case 1000: /* 1000BASE */
548 sh_eth_write(ndev, 0x00000020, GECMR);
549 break;
550 default:
551 break;
552 }
553}
554
555/* SH7757(GETHERC) */
556static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
557 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 558 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 559 .set_rate = sh_eth_set_rate_giga,
560
561 .ecsr_value = ECSR_ICD | ECSR_MPD,
562 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
563 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
564
565 .tx_check = EESR_TC1 | EESR_FTC,
566 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
567 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
568 EESR_ECI,
569 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
570 EESR_TFE,
571 .fdr_value = 0x0000072f,
572 .rmcr_value = 0x00000001,
573
574 .apr = 1,
575 .mpr = 1,
576 .tpauser = 1,
577 .bculr = 1,
578 .hw_swap = 1,
579 .rpadir = 1,
580 .rpadir_value = 2 << 16,
581 .no_trimd = 1,
582 .no_ade = 1,
3acbc971 583 .tsu = 1,
8fcd4961
YS		 584};
585
586static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
587{
588 if (sh_eth_is_gether(mdp))
589 return &sh_eth_my_cpu_data_giga;
590 else
591 return &sh_eth_my_cpu_data;
592}
593
f0e81fec 594#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
380af9e3 595#define SH_ETH_HAS_TSU 1
5cee1d37 596static int sh_eth_check_reset(struct net_device *ndev);
f0e81fec 597static void sh_eth_reset_hw_crc(struct net_device *ndev);
5e7a76be 598
380af9e3
YS		 599static void sh_eth_chip_reset(struct net_device *ndev)
600{
4986b996
YS		 601 struct sh_eth_private *mdp = netdev_priv(ndev);
602
380af9e3 603 /* reset device */
4986b996 604 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 605 mdelay(1);
606}
607
380af9e3
YS		 608static void sh_eth_set_rate(struct net_device *ndev)
609{
610 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 611
612 switch (mdp->speed) {
613 case 10: /* 10BASE */
4a55530f 614 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 615 break;
616 case 100:/* 100BASE */
4a55530f 617 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 618 break;
619 case 1000: /* 1000BASE */
4a55530f 620 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 621 break;
622 default:
623 break;
624 }
625}
626
627/* sh7763 */
628static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
629 .chip_reset = sh_eth_chip_reset,
630 .set_duplex = sh_eth_set_duplex,
631 .set_rate = sh_eth_set_rate,
632
633 .ecsr_value = ECSR_ICD | ECSR_MPD,
634 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
635 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
636
637 .tx_check = EESR_TC1 | EESR_FTC,
638 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
639 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
640 EESR_ECI,
641 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
642 EESR_TFE,
643
644 .apr = 1,
645 .mpr = 1,
646 .tpauser = 1,
647 .bculr = 1,
648 .hw_swap = 1,
380af9e3
YS		 649 .no_trimd = 1,
650 .no_ade = 1,
4986b996 651 .tsu = 1,
f0e81fec
NI		 652#if defined(CONFIG_CPU_SUBTYPE_SH7734)
653 .hw_crc = 1,
5e7a76be 654 .select_mii = 1,
f0e81fec 655#endif
380af9e3
YS		 656};
657
5cee1d37 658static int sh_eth_reset(struct net_device *ndev)
5e7a76be 659{
5cee1d37 660 int ret = 0;
5e7a76be
NI		 661
662 sh_eth_write(ndev, EDSR_ENALL, EDSR);
663 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
5cee1d37
NI		 664
665 ret = sh_eth_check_reset(ndev);
666 if (ret)
667 goto out;
5e7a76be
NI		 668
669 /* Table Init */
670 sh_eth_write(ndev, 0x0, TDLAR);
671 sh_eth_write(ndev, 0x0, TDFAR);
672 sh_eth_write(ndev, 0x0, TDFXR);
673 sh_eth_write(ndev, 0x0, TDFFR);
674 sh_eth_write(ndev, 0x0, RDLAR);
675 sh_eth_write(ndev, 0x0, RDFAR);
676 sh_eth_write(ndev, 0x0, RDFXR);
677 sh_eth_write(ndev, 0x0, RDFFR);
678
679 /* Reset HW CRC register */
680 sh_eth_reset_hw_crc(ndev);
681
682 /* Select MII mode */
683 if (sh_eth_my_cpu_data.select_mii)
684 sh_eth_select_mii(ndev);
5cee1d37
NI		 685out:
686 return ret;
5e7a76be
NI		 687}
688
f0e81fec
NI		 689static void sh_eth_reset_hw_crc(struct net_device *ndev)
690{
691 if (sh_eth_my_cpu_data.hw_crc)
692 sh_eth_write(ndev, 0x0, CSMR);
693}
694
73a0d907
YS		 695#elif defined(CONFIG_ARCH_R8A7740)
696#define SH_ETH_HAS_TSU 1
5cee1d37
NI		 697static int sh_eth_check_reset(struct net_device *ndev);
698
73a0d907
YS		 699static void sh_eth_chip_reset(struct net_device *ndev)
700{
701 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 702
703 /* reset device */
704 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
705 mdelay(1);
706
5e7a76be 707 sh_eth_select_mii(ndev);
73a0d907
YS		 708}
709
5cee1d37 710static int sh_eth_reset(struct net_device *ndev)
73a0d907 711{
5cee1d37 712 int ret = 0;
73a0d907
YS		 713
714 sh_eth_write(ndev, EDSR_ENALL, EDSR);
715 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
5cee1d37
NI		 716
717 ret = sh_eth_check_reset(ndev);
718 if (ret)
719 goto out;
73a0d907
YS		 720
721 /* Table Init */
722 sh_eth_write(ndev, 0x0, TDLAR);
723 sh_eth_write(ndev, 0x0, TDFAR);
724 sh_eth_write(ndev, 0x0, TDFXR);
725 sh_eth_write(ndev, 0x0, TDFFR);
726 sh_eth_write(ndev, 0x0, RDLAR);
727 sh_eth_write(ndev, 0x0, RDFAR);
728 sh_eth_write(ndev, 0x0, RDFXR);
729 sh_eth_write(ndev, 0x0, RDFFR);
5cee1d37
NI		 730
731out:
732 return ret;
73a0d907
YS		 733}
734
73a0d907
YS		 735static void sh_eth_set_rate(struct net_device *ndev)
736{
737 struct sh_eth_private *mdp = netdev_priv(ndev);
738
739 switch (mdp->speed) {
740 case 10: /* 10BASE */
741 sh_eth_write(ndev, GECMR_10, GECMR);
742 break;
743 case 100:/* 100BASE */
744 sh_eth_write(ndev, GECMR_100, GECMR);
745 break;
746 case 1000: /* 1000BASE */
747 sh_eth_write(ndev, GECMR_1000, GECMR);
748 break;
749 default:
750 break;
751 }
752}
753
754/* R8A7740 */
755static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
756 .chip_reset = sh_eth_chip_reset,
757 .set_duplex = sh_eth_set_duplex,
758 .set_rate = sh_eth_set_rate,
759
760 .ecsr_value = ECSR_ICD | ECSR_MPD,
761 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
762 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
763
764 .tx_check = EESR_TC1 | EESR_FTC,
765 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
766 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
767 EESR_ECI,
768 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
769 EESR_TFE,
770
771 .apr = 1,
772 .mpr = 1,
773 .tpauser = 1,
774 .bculr = 1,
775 .hw_swap = 1,
776 .no_trimd = 1,
777 .no_ade = 1,
778 .tsu = 1,
5e7a76be 779 .select_mii = 1,
73a0d907
YS		 780};
781
380af9e3
YS		 782#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
783#define SH_ETH_RESET_DEFAULT 1
784static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
785 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
786
787 .apr = 1,
788 .mpr = 1,
789 .tpauser = 1,
790 .hw_swap = 1,
791};
792#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
793#define SH_ETH_RESET_DEFAULT 1
794#define SH_ETH_HAS_TSU 1
795static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
796 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 797 .tsu = 1,
380af9e3
YS		 798};
799#endif
800
801static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
802{
803 if (!cd->ecsr_value)
804 cd->ecsr_value = DEFAULT_ECSR_INIT;
805
806 if (!cd->ecsipr_value)
807 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
808
809 if (!cd->fcftr_value)
810 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
811 DEFAULT_FIFO_F_D_RFD;
812
813 if (!cd->fdr_value)
814 cd->fdr_value = DEFAULT_FDR_INIT;
815
816 if (!cd->rmcr_value)
817 cd->rmcr_value = DEFAULT_RMCR_VALUE;
818
819 if (!cd->tx_check)
820 cd->tx_check = DEFAULT_TX_CHECK;
821
822 if (!cd->eesr_err_check)
823 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
824
825 if (!cd->tx_error_check)
826 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
827}
828
829#if defined(SH_ETH_RESET_DEFAULT)
830/* Chip Reset */
5cee1d37 831static int sh_eth_reset(struct net_device *ndev)
380af9e3 832{
c5ed5368 833 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
380af9e3 834 mdelay(3);
c5ed5368 835 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
5cee1d37
NI		 836
837 return 0;
838}
839#else
840static int sh_eth_check_reset(struct net_device *ndev)
841{
842 int ret = 0;
843 int cnt = 100;
844
845 while (cnt > 0) {
846 if (!(sh_eth_read(ndev, EDMR) & 0x3))
847 break;
848 mdelay(1);
849 cnt--;
850 }
851 if (cnt < 0) {
14c3326a 852 pr_err("Device reset fail\n");
5cee1d37
NI		 853 ret = -ETIMEDOUT;
854 }
855 return ret;
380af9e3
YS		 856}
857#endif
858
73a0d907 859#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 860static void sh_eth_set_receive_align(struct sk_buff *skb)
861{
862 int reserve;
863
864 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
865 if (reserve)
866 skb_reserve(skb, reserve);
867}
868#else
869static void sh_eth_set_receive_align(struct sk_buff *skb)
870{
871 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
872}
873#endif
874
875
71557a37
YS		 876/* CPU <-> EDMAC endian convert */
877static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
878{
879 switch (mdp->edmac_endian) {
880 case EDMAC_LITTLE_ENDIAN:
881 return cpu_to_le32(x);
882 case EDMAC_BIG_ENDIAN:
883 return cpu_to_be32(x);
884 }
885 return x;
886}
887
888static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
889{
890 switch (mdp->edmac_endian) {
891 case EDMAC_LITTLE_ENDIAN:
892 return le32_to_cpu(x);
893 case EDMAC_BIG_ENDIAN:
894 return be32_to_cpu(x);
895 }
896 return x;
897}
898
86a74ff2
NI		 899/*
900 * Program the hardware MAC address from dev->dev_addr.
901 */
902static void update_mac_address(struct net_device *ndev)
903{
4a55530f
YS		 904 sh_eth_write(ndev,
905 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
906 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
907 sh_eth_write(ndev,
908 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 909}
910
911/*
912 * Get MAC address from SuperH MAC address register
913 *
914 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
915 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
916 * When you want use this device, you must set MAC address in bootloader.
917 *
918 */
748031f9 919static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 920{
748031f9
MD		 921 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
922 memcpy(ndev->dev_addr, mac, 6);
923 } else {
4a55530f
YS		 924 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
925 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
926 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
927 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
928 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
929 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 930 }
86a74ff2
NI		 931}
932
c5ed5368
YS		 933static int sh_eth_is_gether(struct sh_eth_private *mdp)
934{
935 if (mdp->reg_offset == sh_eth_offset_gigabit)
936 return 1;
937 else
938 return 0;
939}
940
941static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
942{
943 if (sh_eth_is_gether(mdp))
944 return EDTRR_TRNS_GETHER;
945 else
946 return EDTRR_TRNS_ETHER;
947}
948
86a74ff2 949struct bb_info {
ae70644d 950 void (*set_gate)(void *addr);
86a74ff2 951 struct mdiobb_ctrl ctrl;
ae70644d 952 void *addr;
86a74ff2
NI		 953 u32 mmd_msk;/* MMD */
954 u32 mdo_msk;
955 u32 mdi_msk;
956 u32 mdc_msk;
957};
958
959/* PHY bit set */
ae70644d 960static void bb_set(void *addr, u32 msk)
86a74ff2 961{
ae70644d 962 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 963}
964
965/* PHY bit clear */
ae70644d 966static void bb_clr(void *addr, u32 msk)
86a74ff2 967{
ae70644d 968 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 969}
970
971/* PHY bit read */
ae70644d 972static int bb_read(void *addr, u32 msk)
86a74ff2 973{
ae70644d 974 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 975}
976
977/* Data I/O pin control */
978static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
979{
980 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 981
982 if (bitbang->set_gate)
983 bitbang->set_gate(bitbang->addr);
984
86a74ff2
NI		 985 if (bit)
986 bb_set(bitbang->addr, bitbang->mmd_msk);
987 else
988 bb_clr(bitbang->addr, bitbang->mmd_msk);
989}
990
991/* Set bit data*/
992static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
993{
994 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
995
b3017e6a
YS		 996 if (bitbang->set_gate)
997 bitbang->set_gate(bitbang->addr);
998
86a74ff2
NI		 999 if (bit)
1000 bb_set(bitbang->addr, bitbang->mdo_msk);
1001 else
1002 bb_clr(bitbang->addr, bitbang->mdo_msk);
1003}
1004
1005/* Get bit data*/
1006static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1007{
1008 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1009
1010 if (bitbang->set_gate)
1011 bitbang->set_gate(bitbang->addr);
1012
86a74ff2
NI		 1013 return bb_read(bitbang->addr, bitbang->mdi_msk);
1014}
1015
1016/* MDC pin control */
1017static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1018{
1019 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1020
b3017e6a
YS		 1021 if (bitbang->set_gate)
1022 bitbang->set_gate(bitbang->addr);
1023
86a74ff2
NI		 1024 if (bit)
1025 bb_set(bitbang->addr, bitbang->mdc_msk);
1026 else
1027 bb_clr(bitbang->addr, bitbang->mdc_msk);
1028}
1029
1030/* mdio bus control struct */
1031static struct mdiobb_ops bb_ops = {
1032 .owner = THIS_MODULE,
1033 .set_mdc = sh_mdc_ctrl,
1034 .set_mdio_dir = sh_mmd_ctrl,
1035 .set_mdio_data = sh_set_mdio,
1036 .get_mdio_data = sh_get_mdio,
1037};
1038
86a74ff2
NI		 1039/* free skb and descriptor buffer */
1040static void sh_eth_ring_free(struct net_device *ndev)
1041{
1042 struct sh_eth_private *mdp = netdev_priv(ndev);
1043 int i;
1044
1045 /* Free Rx skb ringbuffer */
1046 if (mdp->rx_skbuff) {
525b8075 1047 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1048 if (mdp->rx_skbuff[i])
1049 dev_kfree_skb(mdp->rx_skbuff[i]);
1050 }
1051 }
1052 kfree(mdp->rx_skbuff);
91c77550 1053 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1054
1055 /* Free Tx skb ringbuffer */
1056 if (mdp->tx_skbuff) {
525b8075 1057 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1058 if (mdp->tx_skbuff[i])
1059 dev_kfree_skb(mdp->tx_skbuff[i]);
1060 }
1061 }
1062 kfree(mdp->tx_skbuff);
91c77550 1063 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1064}
1065
1066/* format skb and descriptor buffer */
1067static void sh_eth_ring_format(struct net_device *ndev)
1068{
1069 struct sh_eth_private *mdp = netdev_priv(ndev);
1070 int i;
1071 struct sk_buff *skb;
1072 struct sh_eth_rxdesc *rxdesc = NULL;
1073 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1074 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1075 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 1076
1077 mdp->cur_rx = mdp->cur_tx = 0;
1078 mdp->dirty_rx = mdp->dirty_tx = 0;
1079
1080 memset(mdp->rx_ring, 0, rx_ringsize);
1081
1082 /* build Rx ring buffer */
525b8075 1083 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1084 /* skb */
1085 mdp->rx_skbuff[i] = NULL;
dae2e9f4 1086 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1087 mdp->rx_skbuff[i] = skb;
1088 if (skb == NULL)
1089 break;
bb7d92e3 1090 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1091 DMA_FROM_DEVICE);
380af9e3
YS		 1092 sh_eth_set_receive_align(skb);
1093
86a74ff2
NI		 1094 /* RX descriptor */
1095 rxdesc = &mdp->rx_ring[i];
0029d64a 1096 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1097 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1098
1099 /* The size of the buffer is 16 byte boundary. */
0029d64a 1100 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1101 /* Rx descriptor address set */
1102 if (i == 0) {
4a55530f 1103 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 1104 if (sh_eth_is_gether(mdp))
1105 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1106 }
86a74ff2
NI		 1107 }
1108
525b8075 1109 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1110
1111 /* Mark the last entry as wrapping the ring. */
71557a37 1112 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1113
1114 memset(mdp->tx_ring, 0, tx_ringsize);
1115
1116 /* build Tx ring buffer */
525b8075 1117 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1118 mdp->tx_skbuff[i] = NULL;
1119 txdesc = &mdp->tx_ring[i];
71557a37 1120 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1121 txdesc->buffer_length = 0;
b0ca2a21 1122 if (i == 0) {
71557a37 1123 /* Tx descriptor address set */
4a55530f 1124 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 1125 if (sh_eth_is_gether(mdp))
1126 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1127 }
86a74ff2
NI		 1128 }
1129
71557a37 1130 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1131}
1132
1133/* Get skb and descriptor buffer */
1134static int sh_eth_ring_init(struct net_device *ndev)
1135{
1136 struct sh_eth_private *mdp = netdev_priv(ndev);
1137 int rx_ringsize, tx_ringsize, ret = 0;
1138
1139 /*
1140 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1141 * card needs room to do 8 byte alignment, +2 so we can reserve
1142 * the first 2 bytes, and +16 gets room for the status word from the
1143 * card.
1144 */
1145 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1146 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1147 if (mdp->cd->rpadir)
1148 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1149
1150 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1151 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1152 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1153 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1154 ret = -ENOMEM;
1155 return ret;
1156 }
1157
b2adaca9
JP		 1158 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1159 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1160 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1161 ret = -ENOMEM;
1162 goto skb_ring_free;
1163 }
1164
1165 /* Allocate all Rx descriptors. */
525b8075 1166 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1167 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1168 GFP_KERNEL);
86a74ff2 1169 if (!mdp->rx_ring) {
86a74ff2
NI		 1170 ret = -ENOMEM;
1171 goto desc_ring_free;
1172 }
1173
1174 mdp->dirty_rx = 0;
1175
1176 /* Allocate all Tx descriptors. */
525b8075 1177 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1178 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1179 GFP_KERNEL);
86a74ff2 1180 if (!mdp->tx_ring) {
86a74ff2
NI		 1181 ret = -ENOMEM;
1182 goto desc_ring_free;
1183 }
1184 return ret;
1185
1186desc_ring_free:
1187 /* free DMA buffer */
1188 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1189
1190skb_ring_free:
1191 /* Free Rx and Tx skb ring buffer */
1192 sh_eth_ring_free(ndev);
91c77550
YS		 1193 mdp->tx_ring = NULL;
1194 mdp->rx_ring = NULL;
86a74ff2
NI		 1195
1196 return ret;
1197}
1198
91c77550
YS		 1199static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1200{
1201 int ringsize;
1202
1203 if (mdp->rx_ring) {
525b8075 1204 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1205 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1206 mdp->rx_desc_dma);
1207 mdp->rx_ring = NULL;
1208 }
1209
1210 if (mdp->tx_ring) {
525b8075 1211 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1212 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1213 mdp->tx_desc_dma);
1214 mdp->tx_ring = NULL;
1215 }
1216}
1217
525b8075 1218static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1219{
1220 int ret = 0;
1221 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1222 u32 val;
1223
1224 /* Soft Reset */
5cee1d37
NI		 1225 ret = sh_eth_reset(ndev);
1226 if (ret)
1227 goto out;
86a74ff2 1228
b0ca2a21
NI		 1229 /* Descriptor format */
1230 sh_eth_ring_format(ndev);
380af9e3 1231 if (mdp->cd->rpadir)
4a55530f 1232 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1233
1234 /* all sh_eth int mask */
4a55530f 1235 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1236
10b9194f 1237#if defined(__LITTLE_ENDIAN)
380af9e3 1238 if (mdp->cd->hw_swap)
4a55530f 1239 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1240 else
b0ca2a21 1241#endif
4a55530f 1242 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1243
b0ca2a21 1244 /* FIFO size set */
4a55530f
YS		 1245 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1246 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1247
b0ca2a21 1248 /* Frame recv control */
4a55530f 1249 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 1250
2ecbb783 1251 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1252
380af9e3 1253 if (mdp->cd->bculr)
4a55530f 1254 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1255
4a55530f 1256 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1257
380af9e3 1258 if (!mdp->cd->no_trimd)
4a55530f 1259 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1260
b0ca2a21 1261 /* Recv frame limit set register */
fdb37a7f
YS		 1262 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1263 RFLR);
86a74ff2 1264
4a55530f 1265 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1266 if (start)
1267 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1268
1269 /* PAUSE Prohibition */
4a55530f 1270 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1271 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1272
4a55530f 1273 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1274
380af9e3
YS		 1275 if (mdp->cd->set_rate)
1276 mdp->cd->set_rate(ndev);
1277
b0ca2a21 1278 /* E-MAC Status Register clear */
4a55530f 1279 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1280
1281 /* E-MAC Interrupt Enable register */
525b8075
YS		 1282 if (start)
1283 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1284
1285 /* Set MAC address */
1286 update_mac_address(ndev);
1287
1288 /* mask reset */
380af9e3 1289 if (mdp->cd->apr)
4a55530f 1290 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1291 if (mdp->cd->mpr)
4a55530f 1292 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1293 if (mdp->cd->tpauser)
4a55530f 1294 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1295
525b8075
YS		 1296 if (start) {
1297 /* Setting the Rx mode will start the Rx process. */
1298 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1299
525b8075
YS		 1300 netif_start_queue(ndev);
1301 }
86a74ff2 1302
5cee1d37 1303out:
86a74ff2
NI		 1304 return ret;
1305}
1306
1307/* free Tx skb function */
1308static int sh_eth_txfree(struct net_device *ndev)
1309{
1310 struct sh_eth_private *mdp = netdev_priv(ndev);
1311 struct sh_eth_txdesc *txdesc;
1312 int freeNum = 0;
1313 int entry = 0;
1314
1315 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1316 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1317 txdesc = &mdp->tx_ring[entry];
71557a37 1318 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1319 break;
1320 /* Free the original skb. */
1321 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1322 dma_unmap_single(&ndev->dev, txdesc->addr,
1323 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1324 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1325 mdp->tx_skbuff[entry] = NULL;
1326 freeNum++;
1327 }
71557a37 1328 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1329 if (entry >= mdp->num_tx_ring - 1)
71557a37 1330 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1331
bb7d92e3
ED		 1332 ndev->stats.tx_packets++;
1333 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 1334 }
1335 return freeNum;
1336}
1337
1338/* Packet receive function */
a18e08bd 1339static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1340{
1341 struct sh_eth_private *mdp = netdev_priv(ndev);
1342 struct sh_eth_rxdesc *rxdesc;
1343
525b8075
YS		 1344 int entry = mdp->cur_rx % mdp->num_rx_ring;
1345 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2
NI		 1346 struct sk_buff *skb;
1347 u16 pkt_len = 0;
380af9e3 1348 u32 desc_status;
86a74ff2
NI		 1349
1350 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1351 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1352 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1353 pkt_len = rxdesc->frame_length;
1354
73a0d907
YS		 1355#if defined(CONFIG_ARCH_R8A7740)
1356 desc_status >>= 16;
1357#endif
1358
86a74ff2
NI		 1359 if (--boguscnt < 0)
1360 break;
1361
1362 if (!(desc_status & RDFEND))
bb7d92e3 1363 ndev->stats.rx_length_errors++;
86a74ff2
NI		 1364
1365 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1366 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1367 ndev->stats.rx_errors++;
86a74ff2 1368 if (desc_status & RD_RFS1)
bb7d92e3 1369 ndev->stats.rx_crc_errors++;
86a74ff2 1370 if (desc_status & RD_RFS2)
bb7d92e3 1371 ndev->stats.rx_frame_errors++;
86a74ff2 1372 if (desc_status & RD_RFS3)
bb7d92e3 1373 ndev->stats.rx_length_errors++;
86a74ff2 1374 if (desc_status & RD_RFS4)
bb7d92e3 1375 ndev->stats.rx_length_errors++;
86a74ff2 1376 if (desc_status & RD_RFS6)
bb7d92e3 1377 ndev->stats.rx_missed_errors++;
86a74ff2 1378 if (desc_status & RD_RFS10)
bb7d92e3 1379 ndev->stats.rx_over_errors++;
86a74ff2 1380 } else {
380af9e3
YS		 1381 if (!mdp->cd->hw_swap)
1382 sh_eth_soft_swap(
1383 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1384 pkt_len + 2);
86a74ff2
NI		 1385 skb = mdp->rx_skbuff[entry];
1386 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1387 if (mdp->cd->rpadir)
1388 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 1389 skb_put(skb, pkt_len);
1390 skb->protocol = eth_type_trans(skb, ndev);
1391 netif_rx(skb);
bb7d92e3
ED		 1392 ndev->stats.rx_packets++;
1393 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1394 }
71557a37 1395 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1396 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1397 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1398 }
1399
1400 /* Refill the Rx ring buffers. */
1401 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1402 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1403 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1404 /* The size of the buffer is 16 byte boundary. */
0029d64a 1405 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1406
86a74ff2 1407 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1408 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1409 mdp->rx_skbuff[entry] = skb;
1410 if (skb == NULL)
1411 break; /* Better luck next round. */
bb7d92e3 1412 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1413 DMA_FROM_DEVICE);
380af9e3
YS		 1414 sh_eth_set_receive_align(skb);
1415
bc8acf2c 1416 skb_checksum_none_assert(skb);
0029d64a 1417 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1418 }
525b8075 1419 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1420 rxdesc->status |=
71557a37 1421 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1422 else
1423 rxdesc->status |=
71557a37 1424 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1425 }
1426
1427 /* Restart Rx engine if stopped. */
1428 /* If we don't need to check status, don't. -KDU */
79fba9f5 1429 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd
YS		 1430 /* fix the values for the next receiving if RDE is set */
1431 if (intr_status & EESR_RDE)
1432 mdp->cur_rx = mdp->dirty_rx =
1433 (sh_eth_read(ndev, RDFAR) -
1434 sh_eth_read(ndev, RDLAR)) >> 4;
4a55530f 1435 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1436 }
86a74ff2
NI		 1437
1438 return 0;
1439}
1440
4a55530f 1441static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1442{
1443 /* disable tx and rx */
4a55530f
YS		 1444 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1445 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1446}
1447
4a55530f 1448static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1449{
1450 /* enable tx and rx */
4a55530f
YS		 1451 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1452 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1453}
1454
86a74ff2
NI		 1455/* error control function */
1456static void sh_eth_error(struct net_device *ndev, int intr_status)
1457{
1458 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1459 u32 felic_stat;
380af9e3
YS		 1460 u32 link_stat;
1461 u32 mask;
86a74ff2
NI		 1462
1463 if (intr_status & EESR_ECI) {
4a55530f
YS		 1464 felic_stat = sh_eth_read(ndev, ECSR);
1465 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1466 if (felic_stat & ECSR_ICD)
bb7d92e3 1467 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1468 if (felic_stat & ECSR_LCHNG) {
1469 /* Link Changed */
4923576b 1470 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1471 goto ignore_link;
380af9e3 1472 } else {
4a55530f 1473 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1474 if (mdp->ether_link_active_low)
1475 link_stat = ~link_stat;
380af9e3 1476 }
dc19e4e5 1477 if (!(link_stat & PHY_ST_LINK))
4a55530f 1478 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1479 else {
86a74ff2 1480 /* Link Up */
4a55530f
YS		 1481 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1482 ~DMAC_M_ECI, EESIPR);
86a74ff2 1483 /*clear int */
4a55530f
YS		 1484 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1485 ECSR);
1486 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1487 DMAC_M_ECI, EESIPR);
86a74ff2 1488 /* enable tx and rx */
4a55530f 1489 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1490 }
1491 }
1492 }
1493
1e1b812b 1494ignore_link:
86a74ff2
NI		 1495 if (intr_status & EESR_TWB) {
1496 /* Write buck end. unused write back interrupt */
1497 if (intr_status & EESR_TABT) /* Transmit Abort int */
bb7d92e3 1498 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1499 if (netif_msg_tx_err(mdp))
1500 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 1501 }
1502
1503 if (intr_status & EESR_RABT) {
1504 /* Receive Abort int */
1505 if (intr_status & EESR_RFRMER) {
1506 /* Receive Frame Overflow int */
bb7d92e3 1507 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1508 if (netif_msg_rx_err(mdp))
1509 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1510 }
1511 }
380af9e3 1512
dc19e4e5
NI		 1513 if (intr_status & EESR_TDE) {
1514 /* Transmit Descriptor Empty int */
bb7d92e3 1515 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1516 if (netif_msg_tx_err(mdp))
1517 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1518 }
1519
1520 if (intr_status & EESR_TFE) {
1521 /* FIFO under flow */
bb7d92e3 1522 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1523 if (netif_msg_tx_err(mdp))
1524 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1525 }
1526
1527 if (intr_status & EESR_RDE) {
1528 /* Receive Descriptor Empty int */
bb7d92e3 1529 ndev->stats.rx_over_errors++;
86a74ff2 1530
dc19e4e5
NI		 1531 if (netif_msg_rx_err(mdp))
1532 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1533 }
dc19e4e5 1534
86a74ff2
NI		 1535 if (intr_status & EESR_RFE) {
1536 /* Receive FIFO Overflow int */
bb7d92e3 1537 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1538 if (netif_msg_rx_err(mdp))
1539 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1540 }
1541
1542 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1543 /* Address Error */
bb7d92e3 1544 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1545 if (netif_msg_tx_err(mdp))
1546 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1547 }
380af9e3
YS		 1548
1549 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1550 if (mdp->cd->no_ade)
1551 mask &= ~EESR_ADE;
1552 if (intr_status & mask) {
86a74ff2 1553 /* Tx error */
4a55530f 1554 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1555 /* dmesg */
380af9e3
YS		 1556 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1557 intr_status, mdp->cur_tx);
1558 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1559 mdp->dirty_tx, (u32) ndev->state, edtrr);
1560 /* dirty buffer free */
1561 sh_eth_txfree(ndev);
1562
1563 /* SH7712 BUG */
c5ed5368 1564 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1565 /* tx dma start */
c5ed5368 1566 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1567 }
1568 /* wakeup */
1569 netif_wake_queue(ndev);
1570 }
1571}
1572
1573static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1574{
1575 struct net_device *ndev = netdev;
1576 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1577 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1578 irqreturn_t ret = IRQ_NONE;
3893b273 1579 unsigned long intr_status;
86a74ff2 1580
86a74ff2
NI		 1581 spin_lock(&mdp->lock);
1582
3893b273 1583 /* Get interrupt status */
4a55530f 1584 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1585 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1586 * enabled since it's the one that comes thru regardless of the mask,
1587 * and we need to fully handle it in sh_eth_error() in order to quench
1588 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1589 */
1590 intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
86a74ff2 1591 /* Clear interrupt */
0e0fde3c
NI		 1592 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1593 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 1594 cd->tx_check | cd->eesr_err_check)) {
4a55530f 1595 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 1596 ret = IRQ_HANDLED;
1597 } else
1598 goto other_irq;
86a74ff2 1599
b0ca2a21
NI		 1600 if (intr_status & (EESR_FRC | /* Frame recv*/
1601 EESR_RMAF | /* Multi cast address recv*/
1602 EESR_RRF | /* Bit frame recv */
1603 EESR_RTLF | /* Long frame recv*/
1604 EESR_RTSF | /* short frame recv */
1605 EESR_PRE | /* PHY-LSI recv error */
1606 EESR_CERF)){ /* recv frame CRC error */
a18e08bd 1607 sh_eth_rx(ndev, intr_status);
b0ca2a21 1608 }
86a74ff2 1609
b0ca2a21 1610 /* Tx Check */
380af9e3 1611 if (intr_status & cd->tx_check) {
86a74ff2
NI		 1612 sh_eth_txfree(ndev);
1613 netif_wake_queue(ndev);
1614 }
1615
380af9e3 1616 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 1617 sh_eth_error(ndev, intr_status);
1618
0e0fde3c 1619other_irq:
86a74ff2
NI		 1620 spin_unlock(&mdp->lock);
1621
0e0fde3c 1622 return ret;
86a74ff2
NI		 1623}
1624
86a74ff2
NI		 1625/* PHY state control function */
1626static void sh_eth_adjust_link(struct net_device *ndev)
1627{
1628 struct sh_eth_private *mdp = netdev_priv(ndev);
1629 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1630 int new_state = 0;
1631
3340d2aa 1632 if (phydev->link) {
86a74ff2
NI		 1633 if (phydev->duplex != mdp->duplex) {
1634 new_state = 1;
1635 mdp->duplex = phydev->duplex;
380af9e3
YS		 1636 if (mdp->cd->set_duplex)
1637 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1638 }
1639
1640 if (phydev->speed != mdp->speed) {
1641 new_state = 1;
1642 mdp->speed = phydev->speed;
380af9e3
YS		 1643 if (mdp->cd->set_rate)
1644 mdp->cd->set_rate(ndev);
86a74ff2 1645 }
3340d2aa 1646 if (!mdp->link) {
91a56152
YS		 1647 sh_eth_write(ndev,
1648 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1649 new_state = 1;
1650 mdp->link = phydev->link;
1e1b812b
SS		 1651 if (mdp->cd->no_psr || mdp->no_ether_link)
1652 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1653 }
1654 } else if (mdp->link) {
1655 new_state = 1;
3340d2aa 1656 mdp->link = 0;
86a74ff2
NI		 1657 mdp->speed = 0;
1658 mdp->duplex = -1;
1e1b812b
SS		 1659 if (mdp->cd->no_psr || mdp->no_ether_link)
1660 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1661 }
1662
dc19e4e5 1663 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1664 phy_print_status(phydev);
1665}
1666
1667/* PHY init function */
1668static int sh_eth_phy_init(struct net_device *ndev)
1669{
1670 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1671 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1672 struct phy_device *phydev = NULL;
1673
fb28ad35 1674 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1675 mdp->mii_bus->id , mdp->phy_id);
1676
3340d2aa 1677 mdp->link = 0;
86a74ff2
NI		 1678 mdp->speed = 0;
1679 mdp->duplex = -1;
1680
1681 /* Try connect to PHY */
c061b18d 1682 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
f9a8f83b 1683 mdp->phy_interface);
86a74ff2
NI		 1684 if (IS_ERR(phydev)) {
1685 dev_err(&ndev->dev, "phy_connect failed\n");
1686 return PTR_ERR(phydev);
1687 }
380af9e3 1688
86a74ff2 1689 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1690 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1691
1692 mdp->phydev = phydev;
1693
1694 return 0;
1695}
1696
1697/* PHY control start function */
1698static int sh_eth_phy_start(struct net_device *ndev)
1699{
1700 struct sh_eth_private *mdp = netdev_priv(ndev);
1701 int ret;
1702
1703 ret = sh_eth_phy_init(ndev);
1704 if (ret)
1705 return ret;
1706
1707 /* reset phy - this also wakes it from PDOWN */
1708 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1709 phy_start(mdp->phydev);
1710
1711 return 0;
1712}
1713
dc19e4e5
NI		 1714static int sh_eth_get_settings(struct net_device *ndev,
1715 struct ethtool_cmd *ecmd)
1716{
1717 struct sh_eth_private *mdp = netdev_priv(ndev);
1718 unsigned long flags;
1719 int ret;
1720
1721 spin_lock_irqsave(&mdp->lock, flags);
1722 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1723 spin_unlock_irqrestore(&mdp->lock, flags);
1724
1725 return ret;
1726}
1727
1728static int sh_eth_set_settings(struct net_device *ndev,
1729 struct ethtool_cmd *ecmd)
1730{
1731 struct sh_eth_private *mdp = netdev_priv(ndev);
1732 unsigned long flags;
1733 int ret;
dc19e4e5
NI		 1734
1735 spin_lock_irqsave(&mdp->lock, flags);
1736
1737 /* disable tx and rx */
4a55530f 1738 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1739
1740 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1741 if (ret)
1742 goto error_exit;
1743
1744 if (ecmd->duplex == DUPLEX_FULL)
1745 mdp->duplex = 1;
1746 else
1747 mdp->duplex = 0;
1748
1749 if (mdp->cd->set_duplex)
1750 mdp->cd->set_duplex(ndev);
1751
1752error_exit:
1753 mdelay(1);
1754
1755 /* enable tx and rx */
4a55530f 1756 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1757
1758 spin_unlock_irqrestore(&mdp->lock, flags);
1759
1760 return ret;
1761}
1762
1763static int sh_eth_nway_reset(struct net_device *ndev)
1764{
1765 struct sh_eth_private *mdp = netdev_priv(ndev);
1766 unsigned long flags;
1767 int ret;
1768
1769 spin_lock_irqsave(&mdp->lock, flags);
1770 ret = phy_start_aneg(mdp->phydev);
1771 spin_unlock_irqrestore(&mdp->lock, flags);
1772
1773 return ret;
1774}
1775
1776static u32 sh_eth_get_msglevel(struct net_device *ndev)
1777{
1778 struct sh_eth_private *mdp = netdev_priv(ndev);
1779 return mdp->msg_enable;
1780}
1781
1782static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1783{
1784 struct sh_eth_private *mdp = netdev_priv(ndev);
1785 mdp->msg_enable = value;
1786}
1787
1788static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1789 "rx_current", "tx_current",
1790 "rx_dirty", "tx_dirty",
1791};
1792#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1793
1794static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1795{
1796 switch (sset) {
1797 case ETH_SS_STATS:
1798 return SH_ETH_STATS_LEN;
1799 default:
1800 return -EOPNOTSUPP;
1801 }
1802}
1803
1804static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1805 struct ethtool_stats *stats, u64 *data)
1806{
1807 struct sh_eth_private *mdp = netdev_priv(ndev);
1808 int i = 0;
1809
1810 /* device-specific stats */
1811 data[i++] = mdp->cur_rx;
1812 data[i++] = mdp->cur_tx;
1813 data[i++] = mdp->dirty_rx;
1814 data[i++] = mdp->dirty_tx;
1815}
1816
1817static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1818{
1819 switch (stringset) {
1820 case ETH_SS_STATS:
1821 memcpy(data, *sh_eth_gstrings_stats,
1822 sizeof(sh_eth_gstrings_stats));
1823 break;
1824 }
1825}
1826
525b8075
YS		 1827static void sh_eth_get_ringparam(struct net_device *ndev,
1828 struct ethtool_ringparam *ring)
1829{
1830 struct sh_eth_private *mdp = netdev_priv(ndev);
1831
1832 ring->rx_max_pending = RX_RING_MAX;
1833 ring->tx_max_pending = TX_RING_MAX;
1834 ring->rx_pending = mdp->num_rx_ring;
1835 ring->tx_pending = mdp->num_tx_ring;
1836}
1837
1838static int sh_eth_set_ringparam(struct net_device *ndev,
1839 struct ethtool_ringparam *ring)
1840{
1841 struct sh_eth_private *mdp = netdev_priv(ndev);
1842 int ret;
1843
1844 if (ring->tx_pending > TX_RING_MAX ||
1845 ring->rx_pending > RX_RING_MAX ||
1846 ring->tx_pending < TX_RING_MIN ||
1847 ring->rx_pending < RX_RING_MIN)
1848 return -EINVAL;
1849 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1850 return -EINVAL;
1851
1852 if (netif_running(ndev)) {
1853 netif_tx_disable(ndev);
1854 /* Disable interrupts by clearing the interrupt mask. */
1855 sh_eth_write(ndev, 0x0000, EESIPR);
1856 /* Stop the chip's Tx and Rx processes. */
1857 sh_eth_write(ndev, 0, EDTRR);
1858 sh_eth_write(ndev, 0, EDRRR);
1859 synchronize_irq(ndev->irq);
1860 }
1861
1862 /* Free all the skbuffs in the Rx queue. */
1863 sh_eth_ring_free(ndev);
1864 /* Free DMA buffer */
1865 sh_eth_free_dma_buffer(mdp);
1866
1867 /* Set new parameters */
1868 mdp->num_rx_ring = ring->rx_pending;
1869 mdp->num_tx_ring = ring->tx_pending;
1870
1871 ret = sh_eth_ring_init(ndev);
1872 if (ret < 0) {
1873 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1874 return ret;
1875 }
1876 ret = sh_eth_dev_init(ndev, false);
1877 if (ret < 0) {
1878 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1879 return ret;
1880 }
1881
1882 if (netif_running(ndev)) {
1883 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1884 /* Setting the Rx mode will start the Rx process. */
1885 sh_eth_write(ndev, EDRRR_R, EDRRR);
1886 netif_wake_queue(ndev);
1887 }
1888
1889 return 0;
1890}
1891
9b07be4b 1892static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1893 .get_settings = sh_eth_get_settings,
1894 .set_settings = sh_eth_set_settings,
9b07be4b 1895 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1896 .get_msglevel = sh_eth_get_msglevel,
1897 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1898 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1899 .get_strings = sh_eth_get_strings,
1900 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1901 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 1902 .get_ringparam = sh_eth_get_ringparam,
1903 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 1904};
1905
86a74ff2
NI		 1906/* network device open function */
1907static int sh_eth_open(struct net_device *ndev)
1908{
1909 int ret = 0;
1910 struct sh_eth_private *mdp = netdev_priv(ndev);
1911
bcd5149d
MD		 1912 pm_runtime_get_sync(&mdp->pdev->dev);
1913
a0607fd3 1914 ret = request_irq(ndev->irq, sh_eth_interrupt,
f29a3d04 1915#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
dc19e4e5
NI		 1916 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1917 defined(CONFIG_CPU_SUBTYPE_SH7757)
0e0fde3c
NI		 1918 IRQF_SHARED,
1919#else
1920 0,
1921#endif
1922 ndev->name, ndev);
86a74ff2 1923 if (ret) {
380af9e3 1924 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1925 return ret;
1926 }
1927
1928 /* Descriptor set */
1929 ret = sh_eth_ring_init(ndev);
1930 if (ret)
1931 goto out_free_irq;
1932
1933 /* device init */
525b8075 1934 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1935 if (ret)
1936 goto out_free_irq;
1937
1938 /* PHY control start*/
1939 ret = sh_eth_phy_start(ndev);
1940 if (ret)
1941 goto out_free_irq;
1942
86a74ff2
NI		 1943 return ret;
1944
1945out_free_irq:
1946 free_irq(ndev->irq, ndev);
bcd5149d 1947 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1948 return ret;
1949}
1950
1951/* Timeout function */
1952static void sh_eth_tx_timeout(struct net_device *ndev)
1953{
1954 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1955 struct sh_eth_rxdesc *rxdesc;
1956 int i;
1957
1958 netif_stop_queue(ndev);
1959
dc19e4e5
NI		 1960 if (netif_msg_timer(mdp))
1961 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1962 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1963
1964 /* tx_errors count up */
bb7d92e3 1965 ndev->stats.tx_errors++;
86a74ff2 1966
86a74ff2 1967 /* Free all the skbuffs in the Rx queue. */
525b8075 1968 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1969 rxdesc = &mdp->rx_ring[i];
1970 rxdesc->status = 0;
1971 rxdesc->addr = 0xBADF00D0;
1972 if (mdp->rx_skbuff[i])
1973 dev_kfree_skb(mdp->rx_skbuff[i]);
1974 mdp->rx_skbuff[i] = NULL;
1975 }
525b8075 1976 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1977 if (mdp->tx_skbuff[i])
1978 dev_kfree_skb(mdp->tx_skbuff[i]);
1979 mdp->tx_skbuff[i] = NULL;
1980 }
1981
1982 /* device init */
525b8075 1983 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1984}
1985
1986/* Packet transmit function */
1987static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1988{
1989 struct sh_eth_private *mdp = netdev_priv(ndev);
1990 struct sh_eth_txdesc *txdesc;
1991 u32 entry;
fb5e2f9b 1992 unsigned long flags;
86a74ff2
NI		 1993
1994 spin_lock_irqsave(&mdp->lock, flags);
525b8075 1995 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 1996 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1997 if (netif_msg_tx_queued(mdp))
1998 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1999 netif_stop_queue(ndev);
2000 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2001 return NETDEV_TX_BUSY;
86a74ff2
NI		 2002 }
2003 }
2004 spin_unlock_irqrestore(&mdp->lock, flags);
2005
525b8075 2006 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2007 mdp->tx_skbuff[entry] = skb;
2008 txdesc = &mdp->tx_ring[entry];
86a74ff2 2009 /* soft swap. */
380af9e3
YS		 2010 if (!mdp->cd->hw_swap)
2011 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2012 skb->len + 2);
31fcb99d
YS		 2013 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2014 DMA_TO_DEVICE);
86a74ff2
NI		 2015 if (skb->len < ETHERSMALL)
2016 txdesc->buffer_length = ETHERSMALL;
2017 else
2018 txdesc->buffer_length = skb->len;
2019
525b8075 2020 if (entry >= mdp->num_tx_ring - 1)
71557a37 2021 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2022 else
71557a37 2023 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2024
2025 mdp->cur_tx++;
2026
c5ed5368
YS		 2027 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2028 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2029
6ed10654 2030 return NETDEV_TX_OK;
86a74ff2
NI		 2031}
2032
2033/* device close function */
2034static int sh_eth_close(struct net_device *ndev)
2035{
2036 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2037
2038 netif_stop_queue(ndev);
2039
2040 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 2041 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 2042
2043 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 2044 sh_eth_write(ndev, 0, EDTRR);
2045 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 2046
2047 /* PHY Disconnect */
2048 if (mdp->phydev) {
2049 phy_stop(mdp->phydev);
2050 phy_disconnect(mdp->phydev);
2051 }
2052
2053 free_irq(ndev->irq, ndev);
2054
86a74ff2
NI		 2055 /* Free all the skbuffs in the Rx queue. */
2056 sh_eth_ring_free(ndev);
2057
2058 /* free DMA buffer */
91c77550 2059 sh_eth_free_dma_buffer(mdp);
86a74ff2 2060
bcd5149d
MD		 2061 pm_runtime_put_sync(&mdp->pdev->dev);
2062
86a74ff2
NI		 2063 return 0;
2064}
2065
2066static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2067{
2068 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2069
bcd5149d
MD		 2070 pm_runtime_get_sync(&mdp->pdev->dev);
2071
bb7d92e3 2072 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 2073 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 2074 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 2075 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 2076 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 2077 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 2078 if (sh_eth_is_gether(mdp)) {
bb7d92e3 2079 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 2080 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 2081 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 2082 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2083 } else {
bb7d92e3 2084 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 2085 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2086 }
bcd5149d
MD		 2087 pm_runtime_put_sync(&mdp->pdev->dev);
2088
bb7d92e3 2089 return &ndev->stats;
86a74ff2
NI		 2090}
2091
bb7d92e3 2092/* ioctl to device function */
86a74ff2
NI		 2093static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2094 int cmd)
2095{
2096 struct sh_eth_private *mdp = netdev_priv(ndev);
2097 struct phy_device *phydev = mdp->phydev;
2098
2099 if (!netif_running(ndev))
2100 return -EINVAL;
2101
2102 if (!phydev)
2103 return -ENODEV;
2104
28b04113 2105 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2106}
2107
380af9e3 2108#if defined(SH_ETH_HAS_TSU)
6743fe6d
YS		 2109/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2110static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2111 int entry)
2112{
2113 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2114}
2115
2116static u32 sh_eth_tsu_get_post_mask(int entry)
2117{
2118 return 0x0f << (28 - ((entry % 8) * 4));
2119}
2120
2121static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2122{
2123 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2124}
2125
2126static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2127 int entry)
2128{
2129 struct sh_eth_private *mdp = netdev_priv(ndev);
2130 u32 tmp;
2131 void *reg_offset;
2132
2133 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2134 tmp = ioread32(reg_offset);
2135 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2136}
2137
2138static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2139 int entry)
2140{
2141 struct sh_eth_private *mdp = netdev_priv(ndev);
2142 u32 post_mask, ref_mask, tmp;
2143 void *reg_offset;
2144
2145 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2146 post_mask = sh_eth_tsu_get_post_mask(entry);
2147 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2148
2149 tmp = ioread32(reg_offset);
2150 iowrite32(tmp & ~post_mask, reg_offset);
2151
2152 /* If other port enables, the function returns "true" */
2153 return tmp & ref_mask;
2154}
2155
2156static int sh_eth_tsu_busy(struct net_device *ndev)
2157{
2158 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2159 struct sh_eth_private *mdp = netdev_priv(ndev);
2160
2161 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2162 udelay(10);
2163 timeout--;
2164 if (timeout <= 0) {
2165 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2166 return -ETIMEDOUT;
2167 }
2168 }
2169
2170 return 0;
2171}
2172
2173static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2174 const u8 *addr)
2175{
2176 u32 val;
2177
2178 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2179 iowrite32(val, reg);
2180 if (sh_eth_tsu_busy(ndev) < 0)
2181 return -EBUSY;
2182
2183 val = addr[4] << 8 | addr[5];
2184 iowrite32(val, reg + 4);
2185 if (sh_eth_tsu_busy(ndev) < 0)
2186 return -EBUSY;
2187
2188 return 0;
2189}
2190
2191static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2192{
2193 u32 val;
2194
2195 val = ioread32(reg);
2196 addr[0] = (val >> 24) & 0xff;
2197 addr[1] = (val >> 16) & 0xff;
2198 addr[2] = (val >> 8) & 0xff;
2199 addr[3] = val & 0xff;
2200 val = ioread32(reg + 4);
2201 addr[4] = (val >> 8) & 0xff;
2202 addr[5] = val & 0xff;
2203}
2204
2205
2206static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2207{
2208 struct sh_eth_private *mdp = netdev_priv(ndev);
2209 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2210 int i;
2211 u8 c_addr[ETH_ALEN];
2212
2213 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2214 sh_eth_tsu_read_entry(reg_offset, c_addr);
2215 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2216 return i;
2217 }
2218
2219 return -ENOENT;
2220}
2221
2222static int sh_eth_tsu_find_empty(struct net_device *ndev)
2223{
2224 u8 blank[ETH_ALEN];
2225 int entry;
2226
2227 memset(blank, 0, sizeof(blank));
2228 entry = sh_eth_tsu_find_entry(ndev, blank);
2229 return (entry < 0) ? -ENOMEM : entry;
2230}
2231
2232static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2233 int entry)
2234{
2235 struct sh_eth_private *mdp = netdev_priv(ndev);
2236 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2237 int ret;
2238 u8 blank[ETH_ALEN];
2239
2240 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2241 ~(1 << (31 - entry)), TSU_TEN);
2242
2243 memset(blank, 0, sizeof(blank));
2244 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2245 if (ret < 0)
2246 return ret;
2247 return 0;
2248}
2249
2250static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2251{
2252 struct sh_eth_private *mdp = netdev_priv(ndev);
2253 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2254 int i, ret;
2255
2256 if (!mdp->cd->tsu)
2257 return 0;
2258
2259 i = sh_eth_tsu_find_entry(ndev, addr);
2260 if (i < 0) {
2261 /* No entry found, create one */
2262 i = sh_eth_tsu_find_empty(ndev);
2263 if (i < 0)
2264 return -ENOMEM;
2265 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2266 if (ret < 0)
2267 return ret;
2268
2269 /* Enable the entry */
2270 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2271 (1 << (31 - i)), TSU_TEN);
2272 }
2273
2274 /* Entry found or created, enable POST */
2275 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2276
2277 return 0;
2278}
2279
2280static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2281{
2282 struct sh_eth_private *mdp = netdev_priv(ndev);
2283 int i, ret;
2284
2285 if (!mdp->cd->tsu)
2286 return 0;
2287
2288 i = sh_eth_tsu_find_entry(ndev, addr);
2289 if (i) {
2290 /* Entry found */
2291 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2292 goto done;
2293
2294 /* Disable the entry if both ports was disabled */
2295 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2296 if (ret < 0)
2297 return ret;
2298 }
2299done:
2300 return 0;
2301}
2302
2303static int sh_eth_tsu_purge_all(struct net_device *ndev)
2304{
2305 struct sh_eth_private *mdp = netdev_priv(ndev);
2306 int i, ret;
2307
2308 if (unlikely(!mdp->cd->tsu))
2309 return 0;
2310
2311 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2312 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2313 continue;
2314
2315 /* Disable the entry if both ports was disabled */
2316 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2317 if (ret < 0)
2318 return ret;
2319 }
2320
2321 return 0;
2322}
2323
2324static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2325{
2326 struct sh_eth_private *mdp = netdev_priv(ndev);
2327 u8 addr[ETH_ALEN];
2328 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2329 int i;
2330
2331 if (unlikely(!mdp->cd->tsu))
2332 return;
2333
2334 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2335 sh_eth_tsu_read_entry(reg_offset, addr);
2336 if (is_multicast_ether_addr(addr))
2337 sh_eth_tsu_del_entry(ndev, addr);
2338 }
2339}
2340
86a74ff2
NI		 2341/* Multicast reception directions set */
2342static void sh_eth_set_multicast_list(struct net_device *ndev)
2343{
6743fe6d
YS		 2344 struct sh_eth_private *mdp = netdev_priv(ndev);
2345 u32 ecmr_bits;
2346 int mcast_all = 0;
2347 unsigned long flags;
2348
2349 spin_lock_irqsave(&mdp->lock, flags);
2350 /*
2351 * Initial condition is MCT = 1, PRM = 0.
2352 * Depending on ndev->flags, set PRM or clear MCT
2353 */
2354 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2355
2356 if (!(ndev->flags & IFF_MULTICAST)) {
2357 sh_eth_tsu_purge_mcast(ndev);
2358 mcast_all = 1;
2359 }
2360 if (ndev->flags & IFF_ALLMULTI) {
2361 sh_eth_tsu_purge_mcast(ndev);
2362 ecmr_bits &= ~ECMR_MCT;
2363 mcast_all = 1;
2364 }
2365
86a74ff2 2366 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2367 sh_eth_tsu_purge_all(ndev);
2368 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2369 } else if (mdp->cd->tsu) {
2370 struct netdev_hw_addr *ha;
2371 netdev_for_each_mc_addr(ha, ndev) {
2372 if (mcast_all && is_multicast_ether_addr(ha->addr))
2373 continue;
2374
2375 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2376 if (!mcast_all) {
2377 sh_eth_tsu_purge_mcast(ndev);
2378 ecmr_bits &= ~ECMR_MCT;
2379 mcast_all = 1;
2380 }
2381 }
2382 }
86a74ff2
NI		 2383 } else {
2384 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2385 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2386 }
6743fe6d
YS		 2387
2388 /* update the ethernet mode */
2389 sh_eth_write(ndev, ecmr_bits, ECMR);
2390
2391 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2392}
71cc7c37
YS		 2393
2394static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2395{
2396 if (!mdp->port)
2397 return TSU_VTAG0;
2398 else
2399 return TSU_VTAG1;
2400}
2401
80d5c368
PM		 2402static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2403 __be16 proto, u16 vid)
71cc7c37
YS		 2404{
2405 struct sh_eth_private *mdp = netdev_priv(ndev);
2406 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2407
2408 if (unlikely(!mdp->cd->tsu))
2409 return -EPERM;
2410
2411 /* No filtering if vid = 0 */
2412 if (!vid)
2413 return 0;
2414
2415 mdp->vlan_num_ids++;
2416
2417 /*
2418 * The controller has one VLAN tag HW filter. So, if the filter is
2419 * already enabled, the driver disables it and the filte
2420 */
2421 if (mdp->vlan_num_ids > 1) {
2422 /* disable VLAN filter */
2423 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2424 return 0;
2425 }
2426
2427 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2428 vtag_reg_index);
2429
2430 return 0;
2431}
2432
80d5c368
PM		 2433static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2434 __be16 proto, u16 vid)
71cc7c37
YS		 2435{
2436 struct sh_eth_private *mdp = netdev_priv(ndev);
2437 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2438
2439 if (unlikely(!mdp->cd->tsu))
2440 return -EPERM;
2441
2442 /* No filtering if vid = 0 */
2443 if (!vid)
2444 return 0;
2445
2446 mdp->vlan_num_ids--;
2447 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2448
2449 return 0;
2450}
4986b996 2451#endif /* SH_ETH_HAS_TSU */
86a74ff2
NI		 2452
2453/* SuperH's TSU register init function */
4a55530f 2454static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2455{
4a55530f
YS		 2456 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2457 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2458 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2459 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2460 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2461 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2462 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2463 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2464 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2465 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2466 if (sh_eth_is_gether(mdp)) {
2467 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2468 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2469 } else {
2470 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2471 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2472 }
4a55530f
YS		 2473 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2474 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2475 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2476 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2477 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2478 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2479 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2480}
2481
2482/* MDIO bus release function */
2483static int sh_mdio_release(struct net_device *ndev)
2484{
2485 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2486
2487 /* unregister mdio bus */
2488 mdiobus_unregister(bus);
2489
2490 /* remove mdio bus info from net_device */
2491 dev_set_drvdata(&ndev->dev, NULL);
2492
2493 /* free bitbang info */
2494 free_mdio_bitbang(bus);
2495
2496 return 0;
2497}
2498
2499/* MDIO bus init function */
b3017e6a
YS		 2500static int sh_mdio_init(struct net_device *ndev, int id,
2501 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2502{
2503 int ret, i;
2504 struct bb_info *bitbang;
2505 struct sh_eth_private *mdp = netdev_priv(ndev);
2506
2507 /* create bit control struct for PHY */
d5e07e69
SS		 2508 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2509 GFP_KERNEL);
86a74ff2
NI		 2510 if (!bitbang) {
2511 ret = -ENOMEM;
2512 goto out;
2513 }
2514
2515 /* bitbang init */
ae70644d 2516 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2517 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2518 bitbang->mdi_msk = PIR_MDI;
2519 bitbang->mdo_msk = PIR_MDO;
2520 bitbang->mmd_msk = PIR_MMD;
2521 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2522 bitbang->ctrl.ops = &bb_ops;
2523
c2e07b3a 2524 /* MII controller setting */
86a74ff2
NI		 2525 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2526 if (!mdp->mii_bus) {
2527 ret = -ENOMEM;
d5e07e69 2528 goto out;
86a74ff2
NI		 2529 }
2530
2531 /* Hook up MII support for ethtool */
2532 mdp->mii_bus->name = "sh_mii";
18ee49dd 2533 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2534 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 2535 mdp->pdev->name, id);
86a74ff2
NI		 2536
2537 /* PHY IRQ */
d5e07e69
SS		 2538 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2539 sizeof(int) * PHY_MAX_ADDR,
2540 GFP_KERNEL);
86a74ff2
NI		 2541 if (!mdp->mii_bus->irq) {
2542 ret = -ENOMEM;
2543 goto out_free_bus;
2544 }
2545
2546 for (i = 0; i < PHY_MAX_ADDR; i++)
2547 mdp->mii_bus->irq[i] = PHY_POLL;
2548
8f6352f2 2549 /* register mdio bus */
86a74ff2
NI		 2550 ret = mdiobus_register(mdp->mii_bus);
2551 if (ret)
d5e07e69 2552 goto out_free_bus;
86a74ff2
NI		 2553
2554 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2555
2556 return 0;
2557
86a74ff2 2558out_free_bus:
298cf9be 2559 free_mdio_bitbang(mdp->mii_bus);
86a74ff2 2560
86a74ff2
NI		 2561out:
2562 return ret;
2563}
2564
4a55530f
YS		 2565static const u16 *sh_eth_get_register_offset(int register_type)
2566{
2567 const u16 *reg_offset = NULL;
2568
2569 switch (register_type) {
2570 case SH_ETH_REG_GIGABIT:
2571 reg_offset = sh_eth_offset_gigabit;
2572 break;
a3f109bd
SS		 2573 case SH_ETH_REG_FAST_RCAR:
2574 reg_offset = sh_eth_offset_fast_rcar;
2575 break;
4a55530f
YS		 2576 case SH_ETH_REG_FAST_SH4:
2577 reg_offset = sh_eth_offset_fast_sh4;
2578 break;
2579 case SH_ETH_REG_FAST_SH3_SH2:
2580 reg_offset = sh_eth_offset_fast_sh3_sh2;
2581 break;
2582 default:
14c3326a 2583 pr_err("Unknown register type (%d)\n", register_type);
4a55530f
YS		 2584 break;
2585 }
2586
2587 return reg_offset;
2588}
2589
ebf84eaa
AB		 2590static const struct net_device_ops sh_eth_netdev_ops = {
2591 .ndo_open = sh_eth_open,
2592 .ndo_stop = sh_eth_close,
2593 .ndo_start_xmit = sh_eth_start_xmit,
2594 .ndo_get_stats = sh_eth_get_stats,
380af9e3 2595#if defined(SH_ETH_HAS_TSU)
afc4b13d 2596 .ndo_set_rx_mode = sh_eth_set_multicast_list,
71cc7c37
YS		 2597 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2598 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
380af9e3 2599#endif
ebf84eaa
AB		 2600 .ndo_tx_timeout = sh_eth_tx_timeout,
2601 .ndo_do_ioctl = sh_eth_do_ioctl,
2602 .ndo_validate_addr = eth_validate_addr,
2603 .ndo_set_mac_address = eth_mac_addr,
2604 .ndo_change_mtu = eth_change_mtu,
2605};
2606
86a74ff2
NI		 2607static int sh_eth_drv_probe(struct platform_device *pdev)
2608{
9c38657c 2609 int ret, devno = 0;
86a74ff2
NI		 2610 struct resource *res;
2611 struct net_device *ndev = NULL;
ec0d7551 2612 struct sh_eth_private *mdp = NULL;
564044b0 2613 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
86a74ff2
NI		 2614
2615 /* get base addr */
2616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2617 if (unlikely(res == NULL)) {
2618 dev_err(&pdev->dev, "invalid resource\n");
2619 ret = -EINVAL;
2620 goto out;
2621 }
2622
2623 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2624 if (!ndev) {
86a74ff2
NI		 2625 ret = -ENOMEM;
2626 goto out;
2627 }
2628
2629 /* The sh Ether-specific entries in the device structure. */
2630 ndev->base_addr = res->start;
2631 devno = pdev->id;
2632 if (devno < 0)
2633 devno = 0;
2634
2635 ndev->dma = -1;
cc3c080d 2636 ret = platform_get_irq(pdev, 0);
2637 if (ret < 0) {
86a74ff2
NI		 2638 ret = -ENODEV;
2639 goto out_release;
2640 }
cc3c080d 2641 ndev->irq = ret;
86a74ff2
NI		 2642
2643 SET_NETDEV_DEV(ndev, &pdev->dev);
2644
2645 /* Fill in the fields of the device structure with ethernet values. */
2646 ether_setup(ndev);
2647
2648 mdp = netdev_priv(ndev);
525b8075
YS		 2649 mdp->num_tx_ring = TX_RING_SIZE;
2650 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2651 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2652 if (IS_ERR(mdp->addr)) {
2653 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2654 goto out_release;
2655 }
2656
86a74ff2 2657 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2658 mdp->pdev = pdev;
2659 pm_runtime_enable(&pdev->dev);
2660 pm_runtime_resume(&pdev->dev);
86a74ff2
NI		 2661
2662 /* get PHY ID */
71557a37 2663 mdp->phy_id = pd->phy;
e47c9052 2664 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2665 /* EDMAC endian */
2666 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2667 mdp->no_ether_link = pd->no_ether_link;
2668 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 2669 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 2670
380af9e3 2671 /* set cpu data */
8fcd4961
YS		 2672#if defined(SH_ETH_HAS_BOTH_MODULES)
2673 mdp->cd = sh_eth_get_cpu_data(mdp);
2674#else
380af9e3 2675 mdp->cd = &sh_eth_my_cpu_data;
8fcd4961 2676#endif
380af9e3
YS		 2677 sh_eth_set_default_cpu_data(mdp->cd);
2678
86a74ff2 2679 /* set function */
ebf84eaa 2680 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2681 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2682 ndev->watchdog_timeo = TX_TIMEOUT;
2683
dc19e4e5
NI		 2684 /* debug message level */
2685 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2686
2687 /* read and set MAC address */
748031f9 2688 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2689 if (!is_valid_ether_addr(ndev->dev_addr)) {
2690 dev_warn(&pdev->dev,
2691 "no valid MAC address supplied, using a random one.\n");
2692 eth_hw_addr_random(ndev);
2693 }
86a74ff2 2694
6ba88021
YS		 2695 /* ioremap the TSU registers */
2696 if (mdp->cd->tsu) {
2697 struct resource *rtsu;
2698 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2699 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2700 if (IS_ERR(mdp->tsu_addr)) {
2701 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2702 goto out_release;
2703 }
6743fe6d 2704 mdp->port = devno % 2;
f646968f 2705 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2706 }
2707
150647fb
YS		 2708 /* initialize first or needed device */
2709 if (!devno || pd->needs_init) {
380af9e3
YS		 2710 if (mdp->cd->chip_reset)
2711 mdp->cd->chip_reset(ndev);
86a74ff2 2712
4986b996
YS		 2713 if (mdp->cd->tsu) {
2714 /* TSU init (Init only)*/
2715 sh_eth_tsu_init(mdp);
2716 }
86a74ff2
NI		 2717 }
2718
2719 /* network device register */
2720 ret = register_netdev(ndev);
2721 if (ret)
2722 goto out_release;
2723
2724 /* mdio bus init */
b3017e6a 2725 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 2726 if (ret)
2727 goto out_unregister;
2728
25985edc 2729 /* print device information */
6cd9b49d
HS		 2730 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2731 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2732
2733 platform_set_drvdata(pdev, ndev);
2734
2735 return ret;
2736
2737out_unregister:
2738 unregister_netdev(ndev);
2739
2740out_release:
2741 /* net_dev free */
2742 if (ndev)
2743 free_netdev(ndev);
2744
2745out:
2746 return ret;
2747}
2748
2749static int sh_eth_drv_remove(struct platform_device *pdev)
2750{
2751 struct net_device *ndev = platform_get_drvdata(pdev);
2752
2753 sh_mdio_release(ndev);
2754 unregister_netdev(ndev);
bcd5149d 2755 pm_runtime_disable(&pdev->dev);
86a74ff2 2756 free_netdev(ndev);
86a74ff2
NI		 2757
2758 return 0;
2759}
2760
bcd5149d
MD		 2761static int sh_eth_runtime_nop(struct device *dev)
2762{
2763 /*
2764 * Runtime PM callback shared between ->runtime_suspend()
2765 * and ->runtime_resume(). Simply returns success.
2766 *
2767 * This driver re-initializes all registers after
2768 * pm_runtime_get_sync() anyway so there is no need
2769 * to save and restore registers here.
2770 */
2771 return 0;
2772}
2773
2774static struct dev_pm_ops sh_eth_dev_pm_ops = {
2775 .runtime_suspend = sh_eth_runtime_nop,
2776 .runtime_resume = sh_eth_runtime_nop,
2777};
2778
86a74ff2
NI		 2779static struct platform_driver sh_eth_driver = {
2780 .probe = sh_eth_drv_probe,
2781 .remove = sh_eth_drv_remove,
2782 .driver = {
2783 .name = CARDNAME,
bcd5149d 2784 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 2785 },
2786};
2787
db62f684 2788module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2789
2790MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2791MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2792MODULE_LICENSE("GPL v2");
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