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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
dc3273e0
AR		 53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
34813fe2
AR		 57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
dc3273e0
AR		 63/* Per-VLAN filters information */
64struct efx_ef10_filter_vlan {
34813fe2 65 struct list_head list;
b3a3c03c 66 u16 vid;
dc3273e0
AR		 67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
69 u16 ucdef;
70 u16 bcast;
71 u16 mcdef;
72};
73
822b96f8
DP		 74struct efx_ef10_dev_addr {
75 u8 addr[ETH_ALEN];
822b96f8
DP		 76};
77
8127d661 78struct efx_ef10_filter_table {
7ac0dd9d
AR		 79/* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags[
8127d661
BH		 81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
82 unsigned int rx_match_count;
83
84 struct {
85 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 86/* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 88 */
89#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 90#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 91#define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle; /* firmware handle */
93 } *entry;
94 wait_queue_head_t waitq;
95/* Shadow of net_device address lists, guarded by mac_lock */
822b96f8
DP		 96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 98 int dev_uc_count;
99 int dev_mc_count;
afa4ce12
AR		 100 bool uc_promisc;
101 bool mc_promisc;
b071c3a2
AR		 102/* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last;
4a53ea8a 104 bool vlan_filter;
34813fe2 105 struct list_head vlan_list;
8127d661
BH		 106};
107
108/* An arbitrary search limit for the software hash table */
109#define EFX_EF10_FILTER_SEARCH_LIMIT 200
110
8127d661
BH		 111static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
112static void efx_ef10_filter_table_remove(struct efx_nic *efx);
34813fe2
AR		 113static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
114static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
115 struct efx_ef10_filter_vlan *vlan);
116static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
8127d661
BH		 117
118static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
119{
120 efx_dword_t reg;
121
122 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
125}
126
127static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
128{
02246a7f
SS		 129 int bar;
130
131 bar = efx->type->mem_bar;
132 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 133}
134
7a186f47
DP		 135static bool efx_ef10_is_vf(struct efx_nic *efx)
136{
137 return efx->type->is_vf;
138}
139
1cd9ecbb
DP		 140static int efx_ef10_get_pf_index(struct efx_nic *efx)
141{
142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
143 struct efx_ef10_nic_data *nic_data = efx->nic_data;
144 size_t outlen;
145 int rc;
146
147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
148 sizeof(outbuf), &outlen);
149 if (rc)
150 return rc;
151 if (outlen < sizeof(outbuf))
152 return -EIO;
153
154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
155 return 0;
156}
157
88a37de6
SS		 158#ifdef CONFIG_SFC_SRIOV
159static int efx_ef10_get_vf_index(struct efx_nic *efx)
160{
161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
163 size_t outlen;
164 int rc;
165
166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
167 sizeof(outbuf), &outlen);
168 if (rc)
169 return rc;
170 if (outlen < sizeof(outbuf))
171 return -EIO;
172
173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
174 return 0;
175}
176#endif
177
e5a2538a 178static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 179{
ca889a05 180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
8127d661
BH		 181 struct efx_ef10_nic_data *nic_data = efx->nic_data;
182 size_t outlen;
183 int rc;
184
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
186
187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
188 outbuf, sizeof(outbuf), &outlen);
189 if (rc)
190 return rc;
ca889a05 191 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 192 netif_err(efx, drv, efx->net_dev,
193 "unable to read datapath firmware capabilities\n");
194 return -EIO;
195 }
196
197 nic_data->datapath_caps =
198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 199
c634700f 200 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
ca889a05
BK		 201 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
202 GET_CAPABILITIES_V2_OUT_FLAGS2);
c634700f
EC		 203 nic_data->piobuf_size = MCDI_WORD(outbuf,
204 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
205 } else {
ca889a05 206 nic_data->datapath_caps2 = 0;
c634700f
EC		 207 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
208 }
ca889a05 209
8d9f9dd4
DP		 210 /* record the DPCPU firmware IDs to determine VEB vswitching support.
211 */
212 nic_data->rx_dpcpu_fw_id =
213 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
214 nic_data->tx_dpcpu_fw_id =
215 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
216
e5a2538a
BH		 217 if (!(nic_data->datapath_caps &
218 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
219 netif_err(efx, probe, efx->net_dev,
220 "current firmware does not support an RX prefix\n");
221 return -ENODEV;
8127d661
BH		 222 }
223
224 return 0;
225}
226
227static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
228{
229 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
230 int rc;
231
232 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
233 outbuf, sizeof(outbuf), NULL);
234 if (rc)
235 return rc;
236 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
237 return rc > 0 ? rc : -ERANGE;
238}
239
d95e329a
BK		 240static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
241{
242 struct efx_ef10_nic_data *nic_data = efx->nic_data;
243 unsigned int implemented;
244 unsigned int enabled;
245 int rc;
246
247 nic_data->workaround_35388 = false;
248 nic_data->workaround_61265 = false;
249
250 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
251
252 if (rc == -ENOSYS) {
253 /* Firmware without GET_WORKAROUNDS - not a problem. */
254 rc = 0;
255 } else if (rc == 0) {
256 /* Bug61265 workaround is always enabled if implemented. */
257 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
258 nic_data->workaround_61265 = true;
259
260 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
261 nic_data->workaround_35388 = true;
262 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
263 /* Workaround is implemented but not enabled.
264 * Try to enable it.
265 */
266 rc = efx_mcdi_set_workaround(efx,
267 MC_CMD_WORKAROUND_BUG35388,
268 true, NULL);
269 if (rc == 0)
270 nic_data->workaround_35388 = true;
271 /* If we failed to set the workaround just carry on. */
272 rc = 0;
273 }
274 }
275
276 netif_dbg(efx, probe, efx->net_dev,
277 "workaround for bug 35388 is %sabled\n",
278 nic_data->workaround_35388 ? "en" : "dis");
279 netif_dbg(efx, probe, efx->net_dev,
280 "workaround for bug 61265 is %sabled\n",
281 nic_data->workaround_61265 ? "en" : "dis");
282
283 return rc;
284}
285
286static void efx_ef10_process_timer_config(struct efx_nic *efx,
287 const efx_dword_t *data)
288{
289 unsigned int max_count;
290
291 if (EFX_EF10_WORKAROUND_61265(efx)) {
292 efx->timer_quantum_ns = MCDI_DWORD(data,
293 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
294 efx->timer_max_ns = MCDI_DWORD(data,
295 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
296 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
297 efx->timer_quantum_ns = MCDI_DWORD(data,
298 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
299 max_count = MCDI_DWORD(data,
300 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
301 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
302 } else {
303 efx->timer_quantum_ns = MCDI_DWORD(data,
304 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
305 max_count = MCDI_DWORD(data,
306 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
307 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
308 }
309
310 netif_dbg(efx, probe, efx->net_dev,
311 "got timer properties from MC: quantum %u ns; max %u ns\n",
312 efx->timer_quantum_ns, efx->timer_max_ns);
313}
314
315static int efx_ef10_get_timer_config(struct efx_nic *efx)
316{
317 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
318 int rc;
319
320 rc = efx_ef10_get_timer_workarounds(efx);
321 if (rc)
322 return rc;
323
324 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
325 outbuf, sizeof(outbuf), NULL);
326
327 if (rc == 0) {
328 efx_ef10_process_timer_config(efx, outbuf);
329 } else if (rc == -ENOSYS || rc == -EPERM) {
330 /* Not available - fall back to Huntington defaults. */
331 unsigned int quantum;
332
333 rc = efx_ef10_get_sysclk_freq(efx);
334 if (rc < 0)
335 return rc;
336
337 quantum = 1536000 / rc; /* 1536 cycles */
338 efx->timer_quantum_ns = quantum;
339 efx->timer_max_ns = efx->type->timer_period_max * quantum;
340 rc = 0;
341 } else {
342 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
343 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
344 NULL, 0, rc);
345 }
346
347 return rc;
348}
349
0d5e0fbb 350static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 351{
352 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
353 size_t outlen;
354 int rc;
355
356 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
357
358 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
359 outbuf, sizeof(outbuf), &outlen);
360 if (rc)
361 return rc;
362 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
363 return -EIO;
364
cd84ff4d
EC		 365 ether_addr_copy(mac_address,
366 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 367 return 0;
368}
369
0d5e0fbb
DP		 370static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
371{
372 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
373 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
374 size_t outlen;
375 int num_addrs, rc;
376
377 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
378 EVB_PORT_ID_ASSIGNED);
379 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
380 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
381
382 if (rc)
383 return rc;
384 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
385 return -EIO;
386
387 num_addrs = MCDI_DWORD(outbuf,
388 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
389
390 WARN_ON(num_addrs != 1);
391
392 ether_addr_copy(mac_address,
393 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
394
395 return 0;
396}
397
0f5c0845
SS		 398static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
399 struct device_attribute *attr,
400 char *buf)
401{
402 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
403
404 return sprintf(buf, "%d\n",
405 ((efx->mcdi->fn_flags) &
406 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
407 ? 1 : 0);
408}
409
410static ssize_t efx_ef10_show_primary_flag(struct device *dev,
411 struct device_attribute *attr,
412 char *buf)
413{
414 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
415
416 return sprintf(buf, "%d\n",
417 ((efx->mcdi->fn_flags) &
418 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
419 ? 1 : 0);
420}
421
34813fe2
AR		 422static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
423{
424 struct efx_ef10_nic_data *nic_data = efx->nic_data;
425 struct efx_ef10_vlan *vlan;
426
427 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
428
429 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
430 if (vlan->vid == vid)
431 return vlan;
432 }
433
434 return NULL;
435}
436
437static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
438{
439 struct efx_ef10_nic_data *nic_data = efx->nic_data;
440 struct efx_ef10_vlan *vlan;
441 int rc;
442
443 mutex_lock(&nic_data->vlan_lock);
444
445 vlan = efx_ef10_find_vlan(efx, vid);
446 if (vlan) {
4a53ea8a
AR		 447 /* We add VID 0 on init. 8021q adds it on module init
448 * for all interfaces with VLAN filtring feature.
449 */
450 if (vid == 0)
451 goto done_unlock;
34813fe2
AR		 452 netif_warn(efx, drv, efx->net_dev,
453 "VLAN %u already added\n", vid);
454 rc = -EALREADY;
455 goto fail_exist;
456 }
457
458 rc = -ENOMEM;
459 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
460 if (!vlan)
461 goto fail_alloc;
462
463 vlan->vid = vid;
464
465 list_add_tail(&vlan->list, &nic_data->vlan_list);
466
467 if (efx->filter_state) {
468 mutex_lock(&efx->mac_lock);
469 down_write(&efx->filter_sem);
470 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
471 up_write(&efx->filter_sem);
472 mutex_unlock(&efx->mac_lock);
473 if (rc)
474 goto fail_filter_add_vlan;
475 }
476
4a53ea8a 477done_unlock:
34813fe2
AR		 478 mutex_unlock(&nic_data->vlan_lock);
479 return 0;
480
481fail_filter_add_vlan:
482 list_del(&vlan->list);
483 kfree(vlan);
484fail_alloc:
485fail_exist:
486 mutex_unlock(&nic_data->vlan_lock);
487 return rc;
488}
489
490static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
491 struct efx_ef10_vlan *vlan)
492{
493 struct efx_ef10_nic_data *nic_data = efx->nic_data;
494
495 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
496
497 if (efx->filter_state) {
498 down_write(&efx->filter_sem);
499 efx_ef10_filter_del_vlan(efx, vlan->vid);
500 up_write(&efx->filter_sem);
501 }
502
503 list_del(&vlan->list);
504 kfree(vlan);
505}
506
4a53ea8a
AR		 507static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
508{
509 struct efx_ef10_nic_data *nic_data = efx->nic_data;
510 struct efx_ef10_vlan *vlan;
511 int rc = 0;
512
513 /* 8021q removes VID 0 on module unload for all interfaces
514 * with VLAN filtering feature. We need to keep it to receive
515 * untagged traffic.
516 */
517 if (vid == 0)
518 return 0;
519
520 mutex_lock(&nic_data->vlan_lock);
521
522 vlan = efx_ef10_find_vlan(efx, vid);
523 if (!vlan) {
524 netif_err(efx, drv, efx->net_dev,
525 "VLAN %u to be deleted not found\n", vid);
526 rc = -ENOENT;
527 } else {
528 efx_ef10_del_vlan_internal(efx, vlan);
529 }
530
531 mutex_unlock(&nic_data->vlan_lock);
532
533 return rc;
534}
535
34813fe2
AR		 536static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
537{
538 struct efx_ef10_nic_data *nic_data = efx->nic_data;
539 struct efx_ef10_vlan *vlan, *next_vlan;
540
541 mutex_lock(&nic_data->vlan_lock);
542 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
543 efx_ef10_del_vlan_internal(efx, vlan);
544 mutex_unlock(&nic_data->vlan_lock);
545}
546
0f5c0845
SS		 547static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
548 NULL);
549static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
550
8127d661
BH		 551static int efx_ef10_probe(struct efx_nic *efx)
552{
553 struct efx_ef10_nic_data *nic_data;
554 int i, rc;
555
aa3930ee
BH		 556 /* We can have one VI for each 8K region. However, until we
557 * use TX option descriptors we need two TX queues per channel.
8127d661 558 */
b0fbdae1
SS		 559 efx->max_channels = min_t(unsigned int,
560 EFX_MAX_CHANNELS,
561 efx_ef10_mem_map_size(efx) /
562 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
563 efx->max_tx_channels = efx->max_channels;
9fd3d3a4
EC		 564 if (WARN_ON(efx->max_channels == 0))
565 return -EIO;
8127d661
BH		 566
567 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
568 if (!nic_data)
569 return -ENOMEM;
570 efx->nic_data = nic_data;
571
75aba2a5
EC		 572 /* we assume later that we can copy from this buffer in dwords */
573 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
574
8127d661
BH		 575 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
576 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
577 if (rc)
578 goto fail1;
579
580 /* Get the MC's warm boot count. In case it's rebooting right
581 * now, be prepared to retry.
582 */
583 i = 0;
584 for (;;) {
585 rc = efx_ef10_get_warm_boot_count(efx);
586 if (rc >= 0)
587 break;
588 if (++i == 5)
589 goto fail2;
590 ssleep(1);
591 }
592 nic_data->warm_boot_count = rc;
593
594 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
595
45b2449e
DP		 596 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
597
8127d661
BH		 598 /* In case we're recovering from a crash (kexec), we want to
599 * cancel any outstanding request by the previous user of this
600 * function. We send a special message using the least
601 * significant bits of the 'high' (doorbell) register.
602 */
603 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
604
605 rc = efx_mcdi_init(efx);
606 if (rc)
607 goto fail2;
608
609 /* Reset (most) configuration for this function */
610 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
611 if (rc)
612 goto fail3;
613
614 /* Enable event logging */
615 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
616 if (rc)
617 goto fail3;
618
0f5c0845
SS		 619 rc = device_create_file(&efx->pci_dev->dev,
620 &dev_attr_link_control_flag);
1cd9ecbb
DP		 621 if (rc)
622 goto fail3;
623
0f5c0845
SS		 624 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
625 if (rc)
626 goto fail4;
627
628 rc = efx_ef10_get_pf_index(efx);
629 if (rc)
630 goto fail5;
631
e5a2538a 632 rc = efx_ef10_init_datapath_caps(efx);
8127d661 633 if (rc < 0)
0f5c0845 634 goto fail5;
8127d661
BH		 635
636 efx->rx_packet_len_offset =
637 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
638
8127d661
BH		 639 rc = efx_mcdi_port_get_number(efx);
640 if (rc < 0)
0f5c0845 641 goto fail5;
8127d661
BH		 642 efx->port_num = rc;
643
0d5e0fbb 644 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 645 if (rc)
0f5c0845 646 goto fail5;
8127d661 647
d95e329a 648 rc = efx_ef10_get_timer_config(efx);
8127d661 649 if (rc < 0)
0f5c0845 650 goto fail5;
8127d661 651
8127d661 652 rc = efx_mcdi_mon_probe(efx);
267d9d73 653 if (rc && rc != -EPERM)
0f5c0845 654 goto fail5;
8127d661 655
9aecda95
BH		 656 efx_ptp_probe(efx, NULL);
657
1d051e00
SS		 658#ifdef CONFIG_SFC_SRIOV
659 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
660 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
661 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
662
663 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
664 } else
665#endif
666 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
667
34813fe2
AR		 668 INIT_LIST_HEAD(&nic_data->vlan_list);
669 mutex_init(&nic_data->vlan_lock);
670
671 /* Add unspecified VID to support VLAN filtering being disabled */
672 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
673 if (rc)
674 goto fail_add_vid_unspec;
675
4a53ea8a
AR		 676 /* If VLAN filtering is enabled, we need VID 0 to get untagged
677 * traffic. It is added automatically if 8021q module is loaded,
678 * but we can't rely on it since module may be not loaded.
679 */
680 rc = efx_ef10_add_vlan(efx, 0);
681 if (rc)
682 goto fail_add_vid_0;
683
8127d661
BH		 684 return 0;
685
4a53ea8a
AR		 686fail_add_vid_0:
687 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 688fail_add_vid_unspec:
689 mutex_destroy(&nic_data->vlan_lock);
690 efx_ptp_remove(efx);
691 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 692fail5:
693 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
694fail4:
695 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 696fail3:
697 efx_mcdi_fini(efx);
698fail2:
699 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
700fail1:
701 kfree(nic_data);
702 efx->nic_data = NULL;
703 return rc;
704}
705
706static int efx_ef10_free_vis(struct efx_nic *efx)
707{
aa09a3da 708 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 709 size_t outlen;
710 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
711 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 712
713 /* -EALREADY means nothing to free, so ignore */
714 if (rc == -EALREADY)
715 rc = 0;
1e0b8120
EC		 716 if (rc)
717 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
718 rc);
8127d661
BH		 719 return rc;
720}
721
183233be
BH		 722#ifdef EFX_USE_PIO
723
724static void efx_ef10_free_piobufs(struct efx_nic *efx)
725{
726 struct efx_ef10_nic_data *nic_data = efx->nic_data;
727 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
728 unsigned int i;
729 int rc;
730
731 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
732
733 for (i = 0; i < nic_data->n_piobufs; i++) {
734 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
735 nic_data->piobuf_handle[i]);
736 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
737 NULL, 0, NULL);
738 WARN_ON(rc);
739 }
740
741 nic_data->n_piobufs = 0;
742}
743
744static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
745{
746 struct efx_ef10_nic_data *nic_data = efx->nic_data;
747 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
748 unsigned int i;
749 size_t outlen;
750 int rc = 0;
751
752 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
753
754 for (i = 0; i < n; i++) {
09a04204
BK		 755 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
756 outbuf, sizeof(outbuf), &outlen);
757 if (rc) {
758 /* Don't display the MC error if we didn't have space
759 * for a VF.
760 */
761 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
762 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
763 0, outbuf, outlen, rc);
183233be 764 break;
09a04204 765 }
183233be
BH		 766 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
767 rc = -EIO;
768 break;
769 }
770 nic_data->piobuf_handle[i] =
771 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
772 netif_dbg(efx, probe, efx->net_dev,
773 "allocated PIO buffer %u handle %x\n", i,
774 nic_data->piobuf_handle[i]);
775 }
776
777 nic_data->n_piobufs = i;
778 if (rc)
779 efx_ef10_free_piobufs(efx);
780 return rc;
781}
782
783static int efx_ef10_link_piobufs(struct efx_nic *efx)
784{
785 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 786 _MCDI_DECLARE_BUF(inbuf,
787 max(MC_CMD_LINK_PIOBUF_IN_LEN,
788 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 789 struct efx_channel *channel;
790 struct efx_tx_queue *tx_queue;
791 unsigned int offset, index;
792 int rc;
793
794 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
795 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
796
aa09a3da
JC		 797 memset(inbuf, 0, sizeof(inbuf));
798
183233be
BH		 799 /* Link a buffer to each VI in the write-combining mapping */
800 for (index = 0; index < nic_data->n_piobufs; ++index) {
801 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
802 nic_data->piobuf_handle[index]);
803 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
804 nic_data->pio_write_vi_base + index);
805 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
806 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
807 NULL, 0, NULL);
808 if (rc) {
809 netif_err(efx, drv, efx->net_dev,
810 "failed to link VI %u to PIO buffer %u (%d)\n",
811 nic_data->pio_write_vi_base + index, index,
812 rc);
813 goto fail;
814 }
815 netif_dbg(efx, probe, efx->net_dev,
816 "linked VI %u to PIO buffer %u\n",
817 nic_data->pio_write_vi_base + index, index);
818 }
819
820 /* Link a buffer to each TX queue */
821 efx_for_each_channel(channel, efx) {
822 efx_for_each_channel_tx_queue(tx_queue, channel) {
823 /* We assign the PIO buffers to queues in
824 * reverse order to allow for the following
825 * special case.
826 */
827 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
828 tx_queue->channel->channel - 1) *
829 efx_piobuf_size);
c634700f
EC		 830 index = offset / nic_data->piobuf_size;
831 offset = offset % nic_data->piobuf_size;
183233be
BH		 832
833 /* When the host page size is 4K, the first
834 * host page in the WC mapping may be within
835 * the same VI page as the last TX queue. We
836 * can only link one buffer to each VI.
837 */
838 if (tx_queue->queue == nic_data->pio_write_vi_base) {
839 BUG_ON(index != 0);
840 rc = 0;
841 } else {
842 MCDI_SET_DWORD(inbuf,
843 LINK_PIOBUF_IN_PIOBUF_HANDLE,
844 nic_data->piobuf_handle[index]);
845 MCDI_SET_DWORD(inbuf,
846 LINK_PIOBUF_IN_TXQ_INSTANCE,
847 tx_queue->queue);
848 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
849 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
850 NULL, 0, NULL);
851 }
852
853 if (rc) {
854 /* This is non-fatal; the TX path just
855 * won't use PIO for this queue
856 */
857 netif_err(efx, drv, efx->net_dev,
858 "failed to link VI %u to PIO buffer %u (%d)\n",
859 tx_queue->queue, index, rc);
860 tx_queue->piobuf = NULL;
861 } else {
862 tx_queue->piobuf =
863 nic_data->pio_write_base +
864 index * EFX_VI_PAGE_SIZE + offset;
865 tx_queue->piobuf_offset = offset;
866 netif_dbg(efx, probe, efx->net_dev,
867 "linked VI %u to PIO buffer %u offset %x addr %p\n",
868 tx_queue->queue, index,
869 tx_queue->piobuf_offset,
870 tx_queue->piobuf);
871 }
872 }
873 }
874
875 return 0;
876
877fail:
878 while (index--) {
879 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
880 nic_data->pio_write_vi_base + index);
881 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
882 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
883 NULL, 0, NULL);
884 }
885 return rc;
886}
887
c0795bf6
EC		 888static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
889{
890 struct efx_channel *channel;
891 struct efx_tx_queue *tx_queue;
892
893 /* All our existing PIO buffers went away */
894 efx_for_each_channel(channel, efx)
895 efx_for_each_channel_tx_queue(tx_queue, channel)
896 tx_queue->piobuf = NULL;
897}
898
183233be
BH		 899#else /* !EFX_USE_PIO */
900
901static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
902{
903 return n == 0 ? 0 : -ENOBUFS;
904}
905
906static int efx_ef10_link_piobufs(struct efx_nic *efx)
907{
908 return 0;
909}
910
911static void efx_ef10_free_piobufs(struct efx_nic *efx)
912{
913}
914
c0795bf6
EC		 915static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
916{
917}
918
183233be
BH		 919#endif /* EFX_USE_PIO */
920
8127d661
BH		 921static void efx_ef10_remove(struct efx_nic *efx)
922{
923 struct efx_ef10_nic_data *nic_data = efx->nic_data;
924 int rc;
925
f1122a34
SS		 926#ifdef CONFIG_SFC_SRIOV
927 struct efx_ef10_nic_data *nic_data_pf;
928 struct pci_dev *pci_dev_pf;
929 struct efx_nic *efx_pf;
930 struct ef10_vf *vf;
931
932 if (efx->pci_dev->is_virtfn) {
933 pci_dev_pf = efx->pci_dev->physfn;
934 if (pci_dev_pf) {
935 efx_pf = pci_get_drvdata(pci_dev_pf);
936 nic_data_pf = efx_pf->nic_data;
937 vf = nic_data_pf->vf + nic_data->vf_index;
938 vf->efx = NULL;
939 } else
940 netif_info(efx, drv, efx->net_dev,
941 "Could not get the PF id from VF\n");
942 }
943#endif
944
34813fe2
AR		 945 efx_ef10_cleanup_vlans(efx);
946 mutex_destroy(&nic_data->vlan_lock);
947
9aecda95
BH		 948 efx_ptp_remove(efx);
949
8127d661
BH		 950 efx_mcdi_mon_remove(efx);
951
8127d661
BH		 952 efx_ef10_rx_free_indir_table(efx);
953
183233be
BH		 954 if (nic_data->wc_membase)
955 iounmap(nic_data->wc_membase);
956
8127d661
BH		 957 rc = efx_ef10_free_vis(efx);
958 WARN_ON(rc != 0);
959
183233be
BH		 960 if (!nic_data->must_restore_piobufs)
961 efx_ef10_free_piobufs(efx);
962
0f5c0845
SS		 963 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
964 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
965
8127d661
BH		 966 efx_mcdi_fini(efx);
967 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
968 kfree(nic_data);
969}
970
88a37de6
SS		 971static int efx_ef10_probe_pf(struct efx_nic *efx)
972{
973 return efx_ef10_probe(efx);
974}
975
38d27f38
AR		 976int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
977 u32 *port_flags, u32 *vadaptor_flags,
978 unsigned int *vlan_tags)
979{
980 struct efx_ef10_nic_data *nic_data = efx->nic_data;
981 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
982 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
983 size_t outlen;
984 int rc;
985
986 if (nic_data->datapath_caps &
987 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
988 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
989 port_id);
990
991 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
992 outbuf, sizeof(outbuf), &outlen);
993 if (rc)
994 return rc;
995
996 if (outlen < sizeof(outbuf)) {
997 rc = -EIO;
998 return rc;
999 }
1000 }
1001
1002 if (port_flags)
1003 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1004 if (vadaptor_flags)
1005 *vadaptor_flags =
1006 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1007 if (vlan_tags)
1008 *vlan_tags =
1009 MCDI_DWORD(outbuf,
1010 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1011
1012 return 0;
1013}
1014
7a186f47
DP		 1015int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1016{
1017 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1018
1019 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1020 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1021 NULL, 0, NULL);
1022}
1023
1024int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1025{
1026 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1027
1028 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1029 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1030 NULL, 0, NULL);
1031}
1032
1033int efx_ef10_vport_add_mac(struct efx_nic *efx,
1034 unsigned int port_id, u8 *mac)
1035{
1036 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1037
1038 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1039 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1040
1041 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1042 sizeof(inbuf), NULL, 0, NULL);
1043}
1044
1045int efx_ef10_vport_del_mac(struct efx_nic *efx,
1046 unsigned int port_id, u8 *mac)
1047{
1048 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1049
1050 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1051 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1052
1053 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1054 sizeof(inbuf), NULL, 0, NULL);
1055}
1056
88a37de6
SS		 1057#ifdef CONFIG_SFC_SRIOV
1058static int efx_ef10_probe_vf(struct efx_nic *efx)
1059{
1060 int rc;
6598dad2
DP		 1061 struct pci_dev *pci_dev_pf;
1062
1063 /* If the parent PF has no VF data structure, it doesn't know about this
1064 * VF so fail probe. The VF needs to be re-created. This can happen
1065 * if the PF driver is unloaded while the VF is assigned to a guest.
1066 */
1067 pci_dev_pf = efx->pci_dev->physfn;
1068 if (pci_dev_pf) {
1069 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1070 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1071
1072 if (!nic_data_pf->vf) {
1073 netif_info(efx, drv, efx->net_dev,
1074 "The VF cannot link to its parent PF; "
1075 "please destroy and re-create the VF\n");
1076 return -EBUSY;
1077 }
1078 }
88a37de6
SS		 1079
1080 rc = efx_ef10_probe(efx);
1081 if (rc)
1082 return rc;
1083
1084 rc = efx_ef10_get_vf_index(efx);
1085 if (rc)
1086 goto fail;
1087
f1122a34
SS		 1088 if (efx->pci_dev->is_virtfn) {
1089 if (efx->pci_dev->physfn) {
1090 struct efx_nic *efx_pf =
1091 pci_get_drvdata(efx->pci_dev->physfn);
1092 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1093 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1094
1095 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1096 nic_data_p->vf[nic_data->vf_index].pci_dev =
1097 efx->pci_dev;
f1122a34
SS		 1098 } else
1099 netif_info(efx, drv, efx->net_dev,
1100 "Could not get the PF id from VF\n");
1101 }
1102
88a37de6
SS		 1103 return 0;
1104
1105fail:
1106 efx_ef10_remove(efx);
1107 return rc;
1108}
1109#else
1110static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1111{
1112 return 0;
1113}
1114#endif
1115
8127d661
BH		 1116static int efx_ef10_alloc_vis(struct efx_nic *efx,
1117 unsigned int min_vis, unsigned int max_vis)
1118{
1119 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1120 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1121 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1122 size_t outlen;
1123 int rc;
1124
1125 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1126 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1127 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1128 outbuf, sizeof(outbuf), &outlen);
1129 if (rc != 0)
1130 return rc;
1131
1132 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1133 return -EIO;
1134
1135 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1136 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1137
1138 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1139 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1140 return 0;
1141}
1142
183233be
BH		 1143/* Note that the failure path of this function does not free
1144 * resources, as this will be done by efx_ef10_remove().
1145 */
8127d661
BH		 1146static int efx_ef10_dimension_resources(struct efx_nic *efx)
1147{
183233be
BH		 1148 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1149 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 1150 unsigned int min_vis = max(EFX_TXQ_TYPES,
1151 efx_separate_tx_channels ? 2 : 1);
1152 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1153 void __iomem *membase;
1154 int rc;
1155
b0fbdae1 1156 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 1157
183233be
BH		 1158#ifdef EFX_USE_PIO
1159 /* Try to allocate PIO buffers if wanted and if the full
1160 * number of PIO buffers would be sufficient to allocate one
1161 * copy-buffer per TX channel. Failure is non-fatal, as there
1162 * are only a small number of PIO buffers shared between all
1163 * functions of the controller.
1164 */
1165 if (efx_piobuf_size != 0 &&
c634700f 1166 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
183233be
BH		 1167 efx->n_tx_channels) {
1168 unsigned int n_piobufs =
1169 DIV_ROUND_UP(efx->n_tx_channels,
c634700f 1170 nic_data->piobuf_size / efx_piobuf_size);
183233be
BH		 1171
1172 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
6eacfb54
TP		 1173 if (rc == -ENOSPC)
1174 netif_dbg(efx, probe, efx->net_dev,
1175 "out of PIO buffers; cannot allocate more\n");
1176 else if (rc == -EPERM)
1177 netif_dbg(efx, probe, efx->net_dev,
1178 "not permitted to allocate PIO buffers\n");
1179 else if (rc)
183233be
BH		 1180 netif_err(efx, probe, efx->net_dev,
1181 "failed to allocate PIO buffers (%d)\n", rc);
1182 else
1183 netif_dbg(efx, probe, efx->net_dev,
1184 "allocated %u PIO buffers\n", n_piobufs);
1185 }
1186#else
1187 nic_data->n_piobufs = 0;
1188#endif
1189
1190 /* PIO buffers should be mapped with write-combining enabled,
1191 * and we want to make single UC and WC mappings rather than
1192 * several of each (in fact that's the only option if host
1193 * page size is >4K). So we may allocate some extra VIs just
1194 * for writing PIO buffers through.
52ad762b 1195 *
b0fbdae1 1196 * The UC mapping contains (channel_vis - 1) complete VIs and the
52ad762b
DP		 1197 * first half of the next VI. Then the WC mapping begins with
1198 * the second half of this last VI.
183233be 1199 */
b0fbdae1 1200 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
183233be
BH		 1201 ER_DZ_TX_PIOBUF);
1202 if (nic_data->n_piobufs) {
52ad762b
DP		 1203 /* pio_write_vi_base rounds down to give the number of complete
1204 * VIs inside the UC mapping.
1205 */
183233be
BH		 1206 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1207 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1208 nic_data->n_piobufs) *
1209 EFX_VI_PAGE_SIZE) -
1210 uc_mem_map_size);
1211 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1212 } else {
1213 pio_write_vi_base = 0;
1214 wc_mem_map_size = 0;
b0fbdae1 1215 max_vis = channel_vis;
183233be
BH		 1216 }
1217
1218 /* In case the last attached driver failed to free VIs, do it now */
1219 rc = efx_ef10_free_vis(efx);
1220 if (rc != 0)
1221 return rc;
1222
1223 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1224 if (rc != 0)
1225 return rc;
1226
b0fbdae1
SS		 1227 if (nic_data->n_allocated_vis < channel_vis) {
1228 netif_info(efx, drv, efx->net_dev,
1229 "Could not allocate enough VIs to satisfy RSS"
1230 " requirements. Performance may not be optimal.\n");
1231 /* We didn't get the VIs to populate our channels.
1232 * We could keep what we got but then we'd have more
1233 * interrupts than we need.
1234 * Instead calculate new max_channels and restart
1235 */
1236 efx->max_channels = nic_data->n_allocated_vis;
1237 efx->max_tx_channels =
1238 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1239
1240 efx_ef10_free_vis(efx);
1241 return -EAGAIN;
1242 }
1243
183233be
BH		 1244 /* If we didn't get enough VIs to map all the PIO buffers, free the
1245 * PIO buffers
1246 */
1247 if (nic_data->n_piobufs &&
1248 nic_data->n_allocated_vis <
1249 pio_write_vi_base + nic_data->n_piobufs) {
1250 netif_dbg(efx, probe, efx->net_dev,
1251 "%u VIs are not sufficient to map %u PIO buffers\n",
1252 nic_data->n_allocated_vis, nic_data->n_piobufs);
1253 efx_ef10_free_piobufs(efx);
1254 }
1255
1256 /* Shrink the original UC mapping of the memory BAR */
1257 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1258 if (!membase) {
1259 netif_err(efx, probe, efx->net_dev,
1260 "could not shrink memory BAR to %x\n",
1261 uc_mem_map_size);
1262 return -ENOMEM;
1263 }
1264 iounmap(efx->membase);
1265 efx->membase = membase;
1266
1267 /* Set up the WC mapping if needed */
1268 if (wc_mem_map_size) {
1269 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1270 uc_mem_map_size,
1271 wc_mem_map_size);
1272 if (!nic_data->wc_membase) {
1273 netif_err(efx, probe, efx->net_dev,
1274 "could not allocate WC mapping of size %x\n",
1275 wc_mem_map_size);
1276 return -ENOMEM;
1277 }
1278 nic_data->pio_write_vi_base = pio_write_vi_base;
1279 nic_data->pio_write_base =
1280 nic_data->wc_membase +
1281 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1282 uc_mem_map_size);
1283
1284 rc = efx_ef10_link_piobufs(efx);
1285 if (rc)
1286 efx_ef10_free_piobufs(efx);
1287 }
1288
1289 netif_dbg(efx, probe, efx->net_dev,
1290 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1291 &efx->membase_phys, efx->membase, uc_mem_map_size,
1292 nic_data->wc_membase, wc_mem_map_size);
1293
1294 return 0;
8127d661
BH		 1295}
1296
1297static int efx_ef10_init_nic(struct efx_nic *efx)
1298{
1299 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1300 int rc;
1301
a915ccc9
BH		 1302 if (nic_data->must_check_datapath_caps) {
1303 rc = efx_ef10_init_datapath_caps(efx);
1304 if (rc)
1305 return rc;
1306 nic_data->must_check_datapath_caps = false;
1307 }
1308
8127d661
BH		 1309 if (nic_data->must_realloc_vis) {
1310 /* We cannot let the number of VIs change now */
1311 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1312 nic_data->n_allocated_vis);
1313 if (rc)
1314 return rc;
1315 nic_data->must_realloc_vis = false;
1316 }
1317
183233be
BH		 1318 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1319 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1320 if (rc == 0) {
1321 rc = efx_ef10_link_piobufs(efx);
1322 if (rc)
1323 efx_ef10_free_piobufs(efx);
1324 }
1325
6eacfb54
TP		 1326 /* Log an error on failure, but this is non-fatal.
1327 * Permission errors are less important - we've presumably
1328 * had the PIO buffer licence removed.
1329 */
1330 if (rc == -EPERM)
1331 netif_dbg(efx, drv, efx->net_dev,
1332 "not permitted to restore PIO buffers\n");
1333 else if (rc)
183233be
BH		 1334 netif_err(efx, drv, efx->net_dev,
1335 "failed to restore PIO buffers (%d)\n", rc);
1336 nic_data->must_restore_piobufs = false;
1337 }
1338
267c0157 1339 /* don't fail init if RSS setup doesn't work */
f74d1995 1340 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
4fdda958 1341 efx->rss_active = (rc == 0);
267c0157 1342
8127d661
BH		 1343 return 0;
1344}
1345
3e336261
JC		 1346static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1347{
1348 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1349#ifdef CONFIG_SFC_SRIOV
1350 unsigned int i;
1351#endif
3e336261
JC		 1352
1353 /* All our allocations have been reset */
1354 nic_data->must_realloc_vis = true;
1355 nic_data->must_restore_filters = true;
1356 nic_data->must_restore_piobufs = true;
c0795bf6 1357 efx_ef10_forget_old_piobufs(efx);
3e336261 1358 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1359
1360 /* Driver-created vswitches and vports must be re-created */
1361 nic_data->must_probe_vswitching = true;
1362 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1363#ifdef CONFIG_SFC_SRIOV
1364 if (nic_data->vf)
1365 for (i = 0; i < efx->vf_count; i++)
1366 nic_data->vf[i].vport_id = 0;
1367#endif
3e336261
JC		 1368}
1369
087e9025
JC		 1370static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1371{
1372 if (reason == RESET_TYPE_MC_FAILURE)
1373 return RESET_TYPE_DATAPATH;
1374
1375 return efx_mcdi_map_reset_reason(reason);
1376}
1377
8127d661
BH		 1378static int efx_ef10_map_reset_flags(u32 *flags)
1379{
1380 enum {
1381 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1382 ETH_RESET_SHARED_SHIFT),
1383 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1384 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1385 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1386 ETH_RESET_SHARED_SHIFT)
1387 };
1388
1389 /* We assume for now that our PCI function is permitted to
1390 * reset everything.
1391 */
1392
1393 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1394 *flags &= ~EF10_RESET_MC;
1395 return RESET_TYPE_WORLD;
1396 }
1397
1398 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1399 *flags &= ~EF10_RESET_PORT;
1400 return RESET_TYPE_ALL;
1401 }
1402
1403 /* no invisible reset implemented */
1404
1405 return -EINVAL;
1406}
1407
3e336261
JC		 1408static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1409{
1410 int rc = efx_mcdi_reset(efx, reset_type);
1411
27324820
DP		 1412 /* Unprivileged functions return -EPERM, but need to return success
1413 * here so that the datapath is brought back up.
1414 */
1415 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1416 rc = 0;
1417
3e336261
JC		 1418 /* If it was a port reset, trigger reallocation of MC resources.
1419 * Note that on an MC reset nothing needs to be done now because we'll
1420 * detect the MC reset later and handle it then.
e283546c
EC		 1421 * For an FLR, we never get an MC reset event, but the MC has reset all
1422 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1423 */
e283546c
EC		 1424 if ((reset_type == RESET_TYPE_ALL ||
1425 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1426 efx_ef10_reset_mc_allocations(efx);
1427 return rc;
1428}
1429
8127d661
BH		 1430#define EF10_DMA_STAT(ext_name, mcdi_name) \
1431 [EF10_STAT_ ## ext_name] = \
1432 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1433#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1434 [EF10_STAT_ ## int_name] = \
1435 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1436#define EF10_OTHER_STAT(ext_name) \
1437 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1438#define GENERIC_SW_STAT(ext_name) \
1439 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1440
1441static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1442 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1443 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1444 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1445 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1446 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1447 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1448 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1449 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1450 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1451 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1452 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1453 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1454 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1455 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1456 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1457 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1458 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1459 EF10_OTHER_STAT(port_rx_good_bytes),
1460 EF10_OTHER_STAT(port_rx_bad_bytes),
1461 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1462 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1463 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1464 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1465 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1466 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1467 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1468 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1469 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1470 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1471 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1472 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1473 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1474 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1475 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1476 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1477 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1478 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1479 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1480 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1481 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1482 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1483 GENERIC_SW_STAT(rx_nodesc_trunc),
1484 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1485 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1486 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1487 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1488 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1489 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1490 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1491 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1492 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1493 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1494 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1495 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1496 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1497 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1498 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1499 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1500 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1501 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1502 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1503 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1504 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1505 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1506 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1507 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1508 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1509 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1510 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1511 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1512 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1513 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1514 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1515};
1516
e80ca013
DP		 1517#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1518 (1ULL << EF10_STAT_port_tx_packets) | \
1519 (1ULL << EF10_STAT_port_tx_pause) | \
1520 (1ULL << EF10_STAT_port_tx_unicast) | \
1521 (1ULL << EF10_STAT_port_tx_multicast) | \
1522 (1ULL << EF10_STAT_port_tx_broadcast) | \
1523 (1ULL << EF10_STAT_port_rx_bytes) | \
1524 (1ULL << \
1525 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1526 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1527 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1528 (1ULL << EF10_STAT_port_rx_packets) | \
1529 (1ULL << EF10_STAT_port_rx_good) | \
1530 (1ULL << EF10_STAT_port_rx_bad) | \
1531 (1ULL << EF10_STAT_port_rx_pause) | \
1532 (1ULL << EF10_STAT_port_rx_control) | \
1533 (1ULL << EF10_STAT_port_rx_unicast) | \
1534 (1ULL << EF10_STAT_port_rx_multicast) | \
1535 (1ULL << EF10_STAT_port_rx_broadcast) | \
1536 (1ULL << EF10_STAT_port_rx_lt64) | \
1537 (1ULL << EF10_STAT_port_rx_64) | \
1538 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1539 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1540 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1541 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1542 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1543 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1544 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1545 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1546 (1ULL << EF10_STAT_port_rx_overflow) | \
1547 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1548 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1549 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661 1550
69b365c3
EC		 1551/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1552 * For a 10G/40G switchable port we do not expose these because they might
1553 * not include all the packets they should.
1554 * On 8000 series NICs these statistics are always provided.
8127d661 1555 */
e80ca013
DP		 1556#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1557 (1ULL << EF10_STAT_port_tx_lt64) | \
1558 (1ULL << EF10_STAT_port_tx_64) | \
1559 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1560 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1561 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1562 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1563 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1564 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1565
1566/* These statistics are only provided by the 40G MAC. For a 10G/40G
1567 * switchable port we do expose these because the errors will otherwise
1568 * be silent.
1569 */
e80ca013
DP		 1570#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1571 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1572
568d7a00
EC		 1573/* These statistics are only provided if the firmware supports the
1574 * capability PM_AND_RXDP_COUNTERS.
1575 */
1576#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1577 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1578 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1579 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1580 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1581 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1582 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1583 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1584 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1585 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1586 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1587 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1588 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1589
4bae913b 1590static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1591{
4bae913b 1592 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1593 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1594 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1595
3c36a2ad
DP		 1596 if (!(efx->mcdi->fn_flags &
1597 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1598 return 0;
1599
69b365c3 1600 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
4bae913b 1601 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
69b365c3
EC		 1602 /* 8000 series have everything even at 40G */
1603 if (nic_data->datapath_caps2 &
1604 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1605 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1606 } else {
4bae913b 1607 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
69b365c3 1608 }
568d7a00
EC		 1609
1610 if (nic_data->datapath_caps &
1611 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1612 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1613
4bae913b
EC		 1614 return raw_mask;
1615}
1616
1617static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1618{
d94619cd 1619 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1620 u64 raw_mask[2];
1621
1622 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1623
d94619cd
DP		 1624 /* Only show vadaptor stats when EVB capability is present */
1625 if (nic_data->datapath_caps &
1626 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1627 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1628 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1629 } else {
1630 raw_mask[1] = 0;
1631 }
4bae913b
EC		 1632
1633#if BITS_PER_LONG == 64
e70c70c3 1634 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
3c36a2ad
DP		 1635 mask[0] = raw_mask[0];
1636 mask[1] = raw_mask[1];
4bae913b 1637#else
e70c70c3 1638 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
3c36a2ad
DP		 1639 mask[0] = raw_mask[0] & 0xffffffff;
1640 mask[1] = raw_mask[0] >> 32;
1641 mask[2] = raw_mask[1] & 0xffffffff;
4bae913b 1642#endif
8127d661
BH		 1643}
1644
1645static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1646{
4bae913b
EC		 1647 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1648
1649 efx_ef10_get_stat_mask(efx, mask);
8127d661 1650 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1651 mask, names);
8127d661
BH		 1652}
1653
d7788196
DP		 1654static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1655 struct rtnl_link_stats64 *core_stats)
1656{
1657 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1658 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1659 u64 *stats = nic_data->stats;
1660 size_t stats_count = 0, index;
1661
1662 efx_ef10_get_stat_mask(efx, mask);
1663
1664 if (full_stats) {
1665 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1666 if (efx_ef10_stat_desc[index].name) {
1667 *full_stats++ = stats[index];
1668 ++stats_count;
1669 }
1670 }
1671 }
1672
fbe4307e
BK		 1673 if (!core_stats)
1674 return stats_count;
1675
1676 if (nic_data->datapath_caps &
1677 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1678 /* Use vadaptor stats. */
0fc95fca
DP		 1679 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1680 stats[EF10_STAT_rx_multicast] +
1681 stats[EF10_STAT_rx_broadcast];
1682 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1683 stats[EF10_STAT_tx_multicast] +
1684 stats[EF10_STAT_tx_broadcast];
1685 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1686 stats[EF10_STAT_rx_multicast_bytes] +
1687 stats[EF10_STAT_rx_broadcast_bytes];
1688 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1689 stats[EF10_STAT_tx_multicast_bytes] +
1690 stats[EF10_STAT_tx_broadcast_bytes];
1691 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1692 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1693 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1694 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1695 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1696 core_stats->rx_errors = core_stats->rx_crc_errors;
1697 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1698 } else {
1699 /* Use port stats. */
1700 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1701 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1702 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1703 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1704 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1705 stats[GENERIC_STAT_rx_nodesc_trunc] +
1706 stats[GENERIC_STAT_rx_noskb_drops];
1707 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1708 core_stats->rx_length_errors =
1709 stats[EF10_STAT_port_rx_gtjumbo] +
1710 stats[EF10_STAT_port_rx_length_error];
1711 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1712 core_stats->rx_frame_errors =
1713 stats[EF10_STAT_port_rx_align_error];
1714 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1715 core_stats->rx_errors = (core_stats->rx_length_errors +
1716 core_stats->rx_crc_errors +
1717 core_stats->rx_frame_errors);
d7788196
DP		 1718 }
1719
1720 return stats_count;
1721}
1722
1723static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1724{
1725 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1726 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1727 __le64 generation_start, generation_end;
1728 u64 *stats = nic_data->stats;
1729 __le64 *dma_stats;
1730
4bae913b
EC		 1731 efx_ef10_get_stat_mask(efx, mask);
1732
8127d661 1733 dma_stats = efx->stats_buffer.addr;
8127d661
BH		 1734
1735 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1736 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1737 return 0;
1738 rmb();
4bae913b 1739 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1740 stats, efx->stats_buffer.addr, false);
d546a893 1741 rmb();
8127d661
BH		 1742 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1743 if (generation_end != generation_start)
1744 return -EAGAIN;
1745
1746 /* Update derived statistics */
e80ca013
DP		 1747 efx_nic_fix_nodesc_drop_stat(efx,
1748 &stats[EF10_STAT_port_rx_nodesc_drops]);
1749 stats[EF10_STAT_port_rx_good_bytes] =
1750 stats[EF10_STAT_port_rx_bytes] -
1751 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1752 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1753 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1754 efx_update_sw_stats(efx, stats);
8127d661
BH		 1755 return 0;
1756}
1757
1758
d7788196
DP		 1759static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1760 struct rtnl_link_stats64 *core_stats)
8127d661 1761{
8127d661
BH		 1762 int retry;
1763
1764 /* If we're unlucky enough to read statistics during the DMA, wait
1765 * up to 10ms for it to finish (typically takes <500us)
1766 */
1767 for (retry = 0; retry < 100; ++retry) {
d7788196 1768 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1769 break;
1770 udelay(100);
1771 }
1772
d7788196
DP		 1773 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1774}
8127d661 1775
d7788196
DP		 1776static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1777{
1778 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1779 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1780 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1781 __le64 generation_start, generation_end;
1782 u64 *stats = nic_data->stats;
1783 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1784 struct efx_buffer stats_buf;
1785 __le64 *dma_stats;
1786 int rc;
1787
f00bf230
DP		 1788 spin_unlock_bh(&efx->stats_lock);
1789
1790 if (in_interrupt()) {
1791 /* If in atomic context, cannot update stats. Just update the
1792 * software stats and return so the caller can continue.
1793 */
1794 spin_lock_bh(&efx->stats_lock);
1795 efx_update_sw_stats(efx, stats);
1796 return 0;
1797 }
1798
d7788196
DP		 1799 efx_ef10_get_stat_mask(efx, mask);
1800
1801 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1802 if (rc) {
1803 spin_lock_bh(&efx->stats_lock);
d7788196 1804 return rc;
f00bf230 1805 }
d7788196
DP		 1806
1807 dma_stats = stats_buf.addr;
1808 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1809
1810 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1811 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1812 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1813 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1814 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1815
6dd4859b
DP		 1816 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1817 NULL, 0, NULL);
d7788196 1818 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1819 if (rc) {
1820 /* Expect ENOENT if DMA queues have not been set up */
1821 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1822 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1823 sizeof(inbuf), NULL, 0, rc);
d7788196 1824 goto out;
6dd4859b 1825 }
d7788196
DP		 1826
1827 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1828 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1829 WARN_ON_ONCE(1);
d7788196 1830 goto out;
0fc95fca 1831 }
d7788196
DP		 1832 rmb();
1833 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1834 stats, stats_buf.addr, false);
1835 rmb();
1836 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1837 if (generation_end != generation_start) {
1838 rc = -EAGAIN;
1839 goto out;
8127d661
BH		 1840 }
1841
d7788196
DP		 1842 efx_update_sw_stats(efx, stats);
1843out:
1844 efx_nic_free_buffer(efx, &stats_buf);
1845 return rc;
1846}
1847
1848static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1849 struct rtnl_link_stats64 *core_stats)
1850{
1851 if (efx_ef10_try_update_nic_stats_vf(efx))
1852 return 0;
1853
1854 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1855}
1856
1857static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1858{
1859 struct efx_nic *efx = channel->efx;
539de7c5 1860 unsigned int mode, usecs;
8127d661
BH		 1861 efx_dword_t timer_cmd;
1862
539de7c5 1863 if (channel->irq_moderation_us) {
8127d661 1864 mode = 3;
539de7c5 1865 usecs = channel->irq_moderation_us;
8127d661
BH		 1866 } else {
1867 mode = 0;
539de7c5 1868 usecs = 0;
8127d661
BH		 1869 }
1870
539de7c5
BK		 1871 if (EFX_EF10_WORKAROUND_61265(efx)) {
1872 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1873 unsigned int ns = usecs * 1000;
1874
1875 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1876 channel->channel);
1877 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1878 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1879 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1880
1881 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1882 inbuf, sizeof(inbuf), 0, NULL, 0);
1883 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1884 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1885
8127d661
BH		 1886 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1887 EFE_DD_EVQ_IND_TIMER_FLAGS,
1888 ERF_DD_EVQ_IND_TIMER_MODE, mode,
539de7c5 1889 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
8127d661
BH		 1890 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1891 channel->channel);
1892 } else {
539de7c5
BK		 1893 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1894
8127d661 1895 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
539de7c5 1896 ERF_DZ_TC_TIMER_VAL, ticks);
8127d661
BH		 1897 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1898 channel->channel);
1899 }
1900}
1901
02246a7f
SS		 1902static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1903 struct ethtool_wolinfo *wol) {}
1904
1905static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1906{
1907 return -EOPNOTSUPP;
1908}
1909
8127d661
BH		 1910static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1911{
1912 wol->supported = 0;
1913 wol->wolopts = 0;
1914 memset(&wol->sopass, 0, sizeof(wol->sopass));
1915}
1916
1917static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1918{
1919 if (type != 0)
1920 return -EINVAL;
1921 return 0;
1922}
1923
1924static void efx_ef10_mcdi_request(struct efx_nic *efx,
1925 const efx_dword_t *hdr, size_t hdr_len,
1926 const efx_dword_t *sdu, size_t sdu_len)
1927{
1928 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1929 u8 *pdu = nic_data->mcdi_buf.addr;
1930
1931 memcpy(pdu, hdr, hdr_len);
1932 memcpy(pdu + hdr_len, sdu, sdu_len);
1933 wmb();
1934
1935 /* The hardware provides 'low' and 'high' (doorbell) registers
1936 * for passing the 64-bit address of an MCDI request to
1937 * firmware. However the dwords are swapped by firmware. The
1938 * least significant bits of the doorbell are then 0 for all
1939 * MCDI requests due to alignment.
1940 */
1941 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1942 ER_DZ_MC_DB_LWRD);
1943 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1944 ER_DZ_MC_DB_HWRD);
1945}
1946
1947static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1948{
1949 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1950 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1951
1952 rmb();
1953 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1954}
1955
1956static void
1957efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1958 size_t offset, size_t outlen)
1959{
1960 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1961 const u8 *pdu = nic_data->mcdi_buf.addr;
1962
1963 memcpy(outbuf, pdu + offset, outlen);
1964}
1965
c577e59e
DP		 1966static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1967{
1968 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1969
1970 /* All our allocations have been reset */
1971 efx_ef10_reset_mc_allocations(efx);
1972
1973 /* The datapath firmware might have been changed */
1974 nic_data->must_check_datapath_caps = true;
1975
1976 /* MAC statistics have been cleared on the NIC; clear the local
1977 * statistic that we update with efx_update_diff_stat().
1978 */
1979 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1980}
1981
8127d661
BH		 1982static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1983{
1984 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1985 int rc;
1986
1987 rc = efx_ef10_get_warm_boot_count(efx);
1988 if (rc < 0) {
1989 /* The firmware is presumably in the process of
1990 * rebooting. However, we are supposed to report each
1991 * reboot just once, so we must only do that once we
1992 * can read and store the updated warm boot count.
1993 */
1994 return 0;
1995 }
1996
1997 if (rc == nic_data->warm_boot_count)
1998 return 0;
1999
2000 nic_data->warm_boot_count = rc;
c577e59e 2001 efx_ef10_mcdi_reboot_detected(efx);
869070c5 2002
8127d661
BH		 2003 return -EIO;
2004}
2005
2006/* Handle an MSI interrupt
2007 *
2008 * Handle an MSI hardware interrupt. This routine schedules event
2009 * queue processing. No interrupt acknowledgement cycle is necessary.
2010 * Also, we never need to check that the interrupt is for us, since
2011 * MSI interrupts cannot be shared.
2012 */
2013static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2014{
2015 struct efx_msi_context *context = dev_id;
2016 struct efx_nic *efx = context->efx;
2017
2018 netif_vdbg(efx, intr, efx->net_dev,
2019 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2020
2021 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2022 /* Note test interrupts */
2023 if (context->index == efx->irq_level)
2024 efx->last_irq_cpu = raw_smp_processor_id();
2025
2026 /* Schedule processing of the channel */
2027 efx_schedule_channel_irq(efx->channel[context->index]);
2028 }
2029
2030 return IRQ_HANDLED;
2031}
2032
2033static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2034{
2035 struct efx_nic *efx = dev_id;
2036 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2037 struct efx_channel *channel;
2038 efx_dword_t reg;
2039 u32 queues;
2040
2041 /* Read the ISR which also ACKs the interrupts */
2042 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2043 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2044
2045 if (queues == 0)
2046 return IRQ_NONE;
2047
2048 if (likely(soft_enabled)) {
2049 /* Note test interrupts */
2050 if (queues & (1U << efx->irq_level))
2051 efx->last_irq_cpu = raw_smp_processor_id();
2052
2053 efx_for_each_channel(channel, efx) {
2054 if (queues & 1)
2055 efx_schedule_channel_irq(channel);
2056 queues >>= 1;
2057 }
2058 }
2059
2060 netif_vdbg(efx, intr, efx->net_dev,
2061 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2062 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2063
2064 return IRQ_HANDLED;
2065}
2066
942e298e 2067static int efx_ef10_irq_test_generate(struct efx_nic *efx)
8127d661
BH		 2068{
2069 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2070
942e298e
JC		 2071 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2072 NULL) == 0)
2073 return -ENOTSUPP;
2074
8127d661
BH		 2075 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2076
2077 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
942e298e 2078 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
8127d661
BH		 2079 inbuf, sizeof(inbuf), NULL, 0, NULL);
2080}
2081
2082static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2083{
2084 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2085 (tx_queue->ptr_mask + 1) *
2086 sizeof(efx_qword_t),
2087 GFP_KERNEL);
2088}
2089
2090/* This writes to the TX_DESC_WPTR and also pushes data */
2091static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2092 const efx_qword_t *txd)
2093{
2094 unsigned int write_ptr;
2095 efx_oword_t reg;
2096
2097 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2098 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2099 reg.qword[0] = *txd;
2100 efx_writeo_page(tx_queue->efx, &reg,
2101 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2102}
2103
e9117e50
BK		 2104/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2105 */
2106static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2107 struct sk_buff *skb,
2108 bool *data_mapped)
2109{
2110 struct efx_tx_buffer *buffer;
2111 struct tcphdr *tcp;
2112 struct iphdr *ip;
2113
2114 u16 ipv4_id;
2115 u32 seqnum;
2116 u32 mss;
2117
e01b16a7 2118 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
e9117e50
BK		 2119
2120 mss = skb_shinfo(skb)->gso_size;
2121
2122 if (unlikely(mss < 4)) {
2123 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2124 return -EINVAL;
2125 }
2126
2127 ip = ip_hdr(skb);
2128 if (ip->version == 4) {
2129 /* Modify IPv4 header if needed. */
2130 ip->tot_len = 0;
2131 ip->check = 0;
2132 ipv4_id = ip->id;
2133 } else {
2134 /* Modify IPv6 header if needed. */
2135 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2136
2137 ipv6->payload_len = 0;
2138 ipv4_id = 0;
2139 }
2140
2141 tcp = tcp_hdr(skb);
2142 seqnum = ntohl(tcp->seq);
2143
2144 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2145
2146 buffer->flags = EFX_TX_BUF_OPTION;
2147 buffer->len = 0;
2148 buffer->unmap_len = 0;
2149 EFX_POPULATE_QWORD_5(buffer->option,
2150 ESF_DZ_TX_DESC_IS_OPT, 1,
2151 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2152 ESF_DZ_TX_TSO_OPTION_TYPE,
2153 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2154 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2155 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2156 );
2157 ++tx_queue->insert_count;
2158
2159 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2160
2161 buffer->flags = EFX_TX_BUF_OPTION;
2162 buffer->len = 0;
2163 buffer->unmap_len = 0;
2164 EFX_POPULATE_QWORD_4(buffer->option,
2165 ESF_DZ_TX_DESC_IS_OPT, 1,
2166 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2167 ESF_DZ_TX_TSO_OPTION_TYPE,
2168 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2169 ESF_DZ_TX_TSO_TCP_MSS, mss
2170 );
2171 ++tx_queue->insert_count;
2172
2173 return 0;
2174}
2175
46d1efd8
EC		 2176static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2177{
2178 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2179 u32 tso_versions = 0;
2180
2181 if (nic_data->datapath_caps &
2182 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2183 tso_versions |= BIT(1);
2184 if (nic_data->datapath_caps2 &
2185 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2186 tso_versions |= BIT(2);
2187 return tso_versions;
2188}
2189
8127d661
BH		 2190static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2191{
2192 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2193 EFX_BUF_SIZE));
8127d661
BH		 2194 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2195 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2196 struct efx_channel *channel = tx_queue->channel;
2197 struct efx_nic *efx = tx_queue->efx;
45b2449e 2198 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e9117e50 2199 bool tso_v2 = false;
aa09a3da 2200 size_t inlen;
8127d661
BH		 2201 dma_addr_t dma_addr;
2202 efx_qword_t *txd;
2203 int rc;
2204 int i;
aa09a3da 2205 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661 2206
e9117e50
BK		 2207 /* TSOv2 is a limited resource that can only be configured on a limited
2208 * number of queues. TSO without checksum offload is not really a thing,
2209 * so we only enable it for those queues.
e9117e50
BK		 2210 */
2211 if (csum_offload && (nic_data->datapath_caps2 &
2212 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2213 tso_v2 = true;
2214 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2215 channel->channel);
2216 }
2217
8127d661
BH		 2218 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2219 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2220 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2221 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
8127d661 2222 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 2223 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2224
2225 dma_addr = tx_queue->txd.buf.dma_addr;
2226
2227 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2228 tx_queue->queue, entries, (u64)dma_addr);
2229
2230 for (i = 0; i < entries; ++i) {
2231 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2232 dma_addr += EFX_BUF_SIZE;
2233 }
2234
2235 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2236
e638ee1d
EC		 2237 do {
2238 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2239 /* This flag was removed from mcdi_pcol.h for
2240 * the non-_EXT version of INIT_TXQ. However,
2241 * firmware still honours it.
2242 */
2243 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2244 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2245 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2246
2247 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2248 NULL, 0, NULL);
2249 if (rc == -ENOSPC && tso_v2) {
2250 /* Retry without TSOv2 if we're short on contexts. */
2251 tso_v2 = false;
2252 netif_warn(efx, probe, efx->net_dev,
2253 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2254 } else if (rc) {
2255 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2256 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2257 NULL, 0, rc);
2258 goto fail;
2259 }
2260 } while (rc);
8127d661
BH		 2261
2262 /* A previous user of this TX queue might have set us up the
2263 * bomb by writing a descriptor to the TX push collector but
2264 * not the doorbell. (Each collector belongs to a port, not a
2265 * queue or function, so cannot easily be reset.) We must
2266 * attempt to push a no-op descriptor in its place.
2267 */
2268 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2269 tx_queue->insert_count = 1;
2270 txd = efx_tx_desc(tx_queue, 0);
2271 EFX_POPULATE_QWORD_4(*txd,
2272 ESF_DZ_TX_DESC_IS_OPT, true,
2273 ESF_DZ_TX_OPTION_TYPE,
2274 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2275 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2276 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2277 tx_queue->write_count = 1;
93171b14 2278
e9117e50
BK		 2279 if (tso_v2) {
2280 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2281 tx_queue->tso_version = 2;
2282 } else if (nic_data->datapath_caps &
2283 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
93171b14
BK		 2284 tx_queue->tso_version = 1;
2285 }
2286
8127d661
BH		 2287 wmb();
2288 efx_ef10_push_tx_desc(tx_queue, txd);
2289
2290 return;
2291
2292fail:
48ce5634
BH		 2293 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2294 tx_queue->queue);
8127d661
BH		 2295}
2296
2297static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2298{
2299 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 2300 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2301 struct efx_nic *efx = tx_queue->efx;
2302 size_t outlen;
2303 int rc;
2304
2305 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2306 tx_queue->queue);
2307
1e0b8120 2308 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2309 outbuf, sizeof(outbuf), &outlen);
2310
2311 if (rc && rc != -EALREADY)
2312 goto fail;
2313
2314 return;
2315
2316fail:
1e0b8120
EC		 2317 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2318 outbuf, outlen, rc);
8127d661
BH		 2319}
2320
2321static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2322{
2323 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2324}
2325
2326/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2327static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2328{
2329 unsigned int write_ptr;
2330 efx_dword_t reg;
2331
2332 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2333 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2334 efx_writed_page(tx_queue->efx, &reg,
2335 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2336}
2337
e9117e50
BK		 2338#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2339
2340static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2341 dma_addr_t dma_addr, unsigned int len)
2342{
2343 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2344 /* If we need to break across multiple descriptors we should
2345 * stop at a page boundary. This assumes the length limit is
2346 * greater than the page size.
2347 */
2348 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2349
2350 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2351 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2352 }
2353
2354 return len;
2355}
2356
8127d661
BH		 2357static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2358{
2359 unsigned int old_write_count = tx_queue->write_count;
2360 struct efx_tx_buffer *buffer;
2361 unsigned int write_ptr;
2362 efx_qword_t *txd;
2363
b2663a4f
MH		 2364 tx_queue->xmit_more_available = false;
2365 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2366 return;
8127d661
BH		 2367
2368 do {
2369 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2370 buffer = &tx_queue->buffer[write_ptr];
2371 txd = efx_tx_desc(tx_queue, write_ptr);
2372 ++tx_queue->write_count;
2373
2374 /* Create TX descriptor ring entry */
2375 if (buffer->flags & EFX_TX_BUF_OPTION) {
2376 *txd = buffer->option;
de1deff9
EC		 2377 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2378 /* PIO descriptor */
2379 tx_queue->packet_write_count = tx_queue->write_count;
8127d661 2380 } else {
de1deff9 2381 tx_queue->packet_write_count = tx_queue->write_count;
8127d661
BH		 2382 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2383 EFX_POPULATE_QWORD_3(
2384 *txd,
2385 ESF_DZ_TX_KER_CONT,
2386 buffer->flags & EFX_TX_BUF_CONT,
2387 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2388 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2389 }
2390 } while (tx_queue->write_count != tx_queue->insert_count);
2391
2392 wmb(); /* Ensure descriptors are written before they are fetched */
2393
2394 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2395 txd = efx_tx_desc(tx_queue,
2396 old_write_count & tx_queue->ptr_mask);
2397 efx_ef10_push_tx_desc(tx_queue, txd);
2398 ++tx_queue->pushes;
2399 } else {
2400 efx_ef10_notify_tx_desc(tx_queue);
2401 }
2402}
2403
a33a4c73
EC		 2404#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2405 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2406#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2407 1 << RSS_MODE_HASH_DST_PORT_LBN)
2408#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2409 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2410 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2411 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2412 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2413 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2414 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2415 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2416 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2417 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2418
2419static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2420{
2421 /* Firmware had a bug (sfc bug 61952) where it would not actually
2422 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2423 * This meant that it would always contain whatever was previously
2424 * in the MCDI buffer. Fortunately, all firmware versions with
2425 * this bug have the same default flags value for a newly-allocated
2426 * RSS context, and the only time we want to get the flags is just
2427 * after allocating. Moreover, the response has a 32-bit hole
2428 * where the context ID would be in the request, so we can use an
2429 * overlength buffer in the request and pre-fill the flags field
2430 * with what we believe the default to be. Thus if the firmware
2431 * has the bug, it will leave our pre-filled value in the flags
2432 * field of the response, and we will get the right answer.
2433 *
2434 * However, this does mean that this function should NOT be used if
2435 * the RSS context flags might not be their defaults - it is ONLY
2436 * reliably correct for a newly-allocated RSS context.
2437 */
2438 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2439 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2440 size_t outlen;
2441 int rc;
2442
2443 /* Check we have a hole for the context ID */
2444 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2445 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2446 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2447 RSS_CONTEXT_FLAGS_DEFAULT);
2448 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2449 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2450 if (rc == 0) {
2451 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2452 rc = -EIO;
2453 else
2454 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2455 }
2456 return rc;
2457}
2458
2459/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2460 * If we fail, we just leave the RSS context at its default hash settings,
2461 * which is safe but may slightly reduce performance.
2462 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2463 * just need to set the UDP ports flags (for both IP versions).
2464 */
2465static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2466{
2467 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2468 u32 flags;
2469
2470 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2471
2472 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2473 return;
2474 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2475 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2476 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2477 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
b718c88a
EC		 2478 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2479 NULL, 0, NULL))
2480 /* Succeeded, so UDP 4-tuple is now enabled */
2481 efx->rx_hash_udp_4tuple = true;
a33a4c73
EC		 2482}
2483
267c0157
JC		 2484static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2485 bool exclusive, unsigned *context_size)
8127d661
BH		 2486{
2487 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2488 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 2489 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 2490 size_t outlen;
2491 int rc;
267c0157
JC		 2492 u32 alloc_type = exclusive ?
2493 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2494 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2495 unsigned rss_spread = exclusive ?
2496 efx->rss_spread :
2497 min(rounddown_pow_of_two(efx->rss_spread),
2498 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2499
2500 if (!exclusive && rss_spread == 1) {
2501 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2502 if (context_size)
2503 *context_size = 1;
2504 return 0;
2505 }
8127d661 2506
dcb4123c
JC		 2507 if (nic_data->datapath_caps &
2508 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2509 return -EOPNOTSUPP;
2510
8127d661 2511 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 2512 nic_data->vport_id);
267c0157
JC		 2513 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2514 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 2515
2516 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2517 outbuf, sizeof(outbuf), &outlen);
2518 if (rc != 0)
2519 return rc;
2520
2521 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2522 return -EIO;
2523
2524 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2525
267c0157
JC		 2526 if (context_size)
2527 *context_size = rss_spread;
2528
a33a4c73
EC		 2529 if (nic_data->datapath_caps &
2530 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2531 efx_ef10_set_rss_flags(efx, *context);
2532
8127d661
BH		 2533 return 0;
2534}
2535
2536static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2537{
2538 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2539 int rc;
2540
2541 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2542 context);
2543
2544 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2545 NULL, 0, NULL);
2546 WARN_ON(rc != 0);
2547}
2548
267c0157 2549static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
f74d1995 2550 const u32 *rx_indir_table, const u8 *key)
8127d661
BH		 2551{
2552 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2553 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2554 int i, rc;
2555
2556 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2557 context);
2558 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2559 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2560
f74d1995
EC		 2561 /* This iterates over the length of efx->rx_indir_table, but copies
2562 * bytes from rx_indir_table. That's because the latter is a pointer
2563 * rather than an array, but should have the same length.
2564 * The efx->rx_hash_key loop below is similar.
2565 */
8127d661
BH		 2566 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2567 MCDI_PTR(tablebuf,
2568 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 2569 (u8) rx_indir_table[i];
8127d661
BH		 2570
2571 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2572 sizeof(tablebuf), NULL, 0, NULL);
2573 if (rc != 0)
2574 return rc;
2575
2576 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2577 context);
2578 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2579 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2580 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
f74d1995 2581 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
8127d661
BH		 2582
2583 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2584 sizeof(keybuf), NULL, 0, NULL);
2585}
2586
2587static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2588{
2589 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2590
2591 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2592 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2593 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2594}
2595
267c0157
JC		 2596static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2597 unsigned *context_size)
8127d661 2598{
267c0157 2599 u32 new_rx_rss_context;
8127d661 2600 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 2601 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2602 false, context_size);
2603
2604 if (rc != 0)
2605 return rc;
8127d661 2606
267c0157
JC		 2607 nic_data->rx_rss_context = new_rx_rss_context;
2608 nic_data->rx_rss_context_exclusive = false;
2609 efx_set_default_rx_indir_table(efx);
2610 return 0;
2611}
8127d661 2612
267c0157 2613static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
f74d1995
EC		 2614 const u32 *rx_indir_table,
2615 const u8 *key)
267c0157
JC		 2616{
2617 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2618 int rc;
2619 u32 new_rx_rss_context;
2620
2621 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2622 !nic_data->rx_rss_context_exclusive) {
2623 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2624 true, NULL);
2625 if (rc == -EOPNOTSUPP)
2626 return rc;
2627 else if (rc != 0)
2628 goto fail1;
2629 } else {
2630 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2631 }
2632
267c0157 2633 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
f74d1995 2634 rx_indir_table, key);
8127d661 2635 if (rc != 0)
267c0157 2636 goto fail2;
8127d661 2637
267c0157
JC		 2638 if (nic_data->rx_rss_context != new_rx_rss_context)
2639 efx_ef10_rx_free_indir_table(efx);
2640 nic_data->rx_rss_context = new_rx_rss_context;
2641 nic_data->rx_rss_context_exclusive = true;
2642 if (rx_indir_table != efx->rx_indir_table)
2643 memcpy(efx->rx_indir_table, rx_indir_table,
2644 sizeof(efx->rx_indir_table));
f74d1995
EC		 2645 if (key != efx->rx_hash_key)
2646 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2647
267c0157 2648 return 0;
8127d661 2649
267c0157
JC		 2650fail2:
2651 if (new_rx_rss_context != nic_data->rx_rss_context)
2652 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2653fail1:
8127d661 2654 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2655 return rc;
2656}
2657
a707d188
EC		 2658static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2659{
2660 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2661 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2662 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2663 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2664 size_t outlen;
2665 int rc, i;
2666
2667 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2668 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2669
2670 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2671 return -ENOENT;
2672
2673 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2674 nic_data->rx_rss_context);
2675 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2676 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2677 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2678 tablebuf, sizeof(tablebuf), &outlen);
2679 if (rc != 0)
2680 return rc;
2681
2682 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2683 return -EIO;
2684
2685 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2686 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2687 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2688
2689 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2690 nic_data->rx_rss_context);
2691 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2692 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2693 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2694 keybuf, sizeof(keybuf), &outlen);
2695 if (rc != 0)
2696 return rc;
2697
2698 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2699 return -EIO;
2700
2701 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2702 efx->rx_hash_key[i] = MCDI_PTR(
2703 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2704
2705 return 0;
2706}
2707
267c0157 2708static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
f74d1995
EC		 2709 const u32 *rx_indir_table,
2710 const u8 *key)
267c0157
JC		 2711{
2712 int rc;
2713
2714 if (efx->rss_spread == 1)
2715 return 0;
2716
f74d1995
EC		 2717 if (!key)
2718 key = efx->rx_hash_key;
2719
2720 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
267c0157
JC		 2721
2722 if (rc == -ENOBUFS && !user) {
2723 unsigned context_size;
2724 bool mismatch = false;
2725 size_t i;
2726
2727 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2728 i++)
2729 mismatch = rx_indir_table[i] !=
2730 ethtool_rxfh_indir_default(i, efx->rss_spread);
2731
2732 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2733 if (rc == 0) {
2734 if (context_size != efx->rss_spread)
2735 netif_warn(efx, probe, efx->net_dev,
2736 "Could not allocate an exclusive RSS"
2737 " context; allocated a shared one of"
2738 " different size."
2739 " Wanted %u, got %u.\n",
2740 efx->rss_spread, context_size);
2741 else if (mismatch)
2742 netif_warn(efx, probe, efx->net_dev,
2743 "Could not allocate an exclusive RSS"
2744 " context; allocated a shared one but"
2745 " could not apply custom"
2746 " indirection.\n");
2747 else
2748 netif_info(efx, probe, efx->net_dev,
2749 "Could not allocate an exclusive RSS"
2750 " context; allocated a shared one.\n");
2751 }
2752 }
2753 return rc;
2754}
2755
2756static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2757 const u32 *rx_indir_table
f74d1995
EC		 2758 __attribute__ ((unused)),
2759 const u8 *key
267c0157
JC		 2760 __attribute__ ((unused)))
2761{
2762 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2763
2764 if (user)
2765 return -EOPNOTSUPP;
2766 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2767 return 0;
2768 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2769}
2770
2771static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2772{
2773 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2774 (rx_queue->ptr_mask + 1) *
2775 sizeof(efx_qword_t),
2776 GFP_KERNEL);
2777}
2778
2779static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2780{
2781 MCDI_DECLARE_BUF(inbuf,
2782 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2783 EFX_BUF_SIZE));
8127d661
BH		 2784 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2785 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2786 struct efx_nic *efx = rx_queue->efx;
45b2449e 2787 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2788 size_t inlen;
8127d661
BH		 2789 dma_addr_t dma_addr;
2790 int rc;
2791 int i;
aa09a3da 2792 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2793
2794 rx_queue->scatter_n = 0;
2795 rx_queue->scatter_len = 0;
2796
2797 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2798 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2799 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2800 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2801 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2802 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2803 INIT_RXQ_IN_FLAG_PREFIX, 1,
2804 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2805 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2806 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2807
2808 dma_addr = rx_queue->rxd.buf.dma_addr;
2809
2810 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2811 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2812
2813 for (i = 0; i < entries; ++i) {
2814 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2815 dma_addr += EFX_BUF_SIZE;
2816 }
2817
2818 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2819
2820 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2821 NULL, 0, NULL);
48ce5634
BH		 2822 if (rc)
2823 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2824 efx_rx_queue_index(rx_queue));
8127d661
BH		 2825}
2826
2827static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2828{
2829 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2830 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2831 struct efx_nic *efx = rx_queue->efx;
2832 size_t outlen;
2833 int rc;
2834
2835 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2836 efx_rx_queue_index(rx_queue));
2837
1e0b8120 2838 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2839 outbuf, sizeof(outbuf), &outlen);
2840
2841 if (rc && rc != -EALREADY)
2842 goto fail;
2843
2844 return;
2845
2846fail:
1e0b8120
EC		 2847 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2848 outbuf, outlen, rc);
8127d661
BH		 2849}
2850
2851static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2852{
2853 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2854}
2855
2856/* This creates an entry in the RX descriptor queue */
2857static inline void
2858efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2859{
2860 struct efx_rx_buffer *rx_buf;
2861 efx_qword_t *rxd;
2862
2863 rxd = efx_rx_desc(rx_queue, index);
2864 rx_buf = efx_rx_buffer(rx_queue, index);
2865 EFX_POPULATE_QWORD_2(*rxd,
2866 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2867 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2868}
2869
2870static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2871{
2872 struct efx_nic *efx = rx_queue->efx;
2873 unsigned int write_count;
2874 efx_dword_t reg;
2875
2876 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2877 write_count = rx_queue->added_count & ~7;
2878 if (rx_queue->notified_count == write_count)
2879 return;
2880
2881 do
2882 efx_ef10_build_rx_desc(
2883 rx_queue,
2884 rx_queue->notified_count & rx_queue->ptr_mask);
2885 while (++rx_queue->notified_count != write_count);
2886
2887 wmb();
2888 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2889 write_count & rx_queue->ptr_mask);
2890 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2891 efx_rx_queue_index(rx_queue));
2892}
2893
2894static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2895
2896static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2897{
2898 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2899 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2900 efx_qword_t event;
2901
2902 EFX_POPULATE_QWORD_2(event,
2903 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2904 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2905
2906 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2907
2908 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2909 * already swapped the data to little-endian order.
2910 */
2911 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2912 sizeof(efx_qword_t));
2913
2914 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2915 inbuf, sizeof(inbuf), 0,
2916 efx_ef10_rx_defer_refill_complete, 0);
2917}
2918
2919static void
2920efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2921 int rc, efx_dword_t *outbuf,
2922 size_t outlen_actual)
2923{
2924 /* nothing to do */
2925}
2926
2927static int efx_ef10_ev_probe(struct efx_channel *channel)
2928{
2929 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2930 (channel->eventq_mask + 1) *
2931 sizeof(efx_qword_t),
2932 GFP_KERNEL);
2933}
2934
46e612b0
DP		 2935static void efx_ef10_ev_fini(struct efx_channel *channel)
2936{
2937 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2938 MCDI_DECLARE_BUF_ERR(outbuf);
2939 struct efx_nic *efx = channel->efx;
2940 size_t outlen;
2941 int rc;
2942
2943 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2944
2945 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2946 outbuf, sizeof(outbuf), &outlen);
2947
2948 if (rc && rc != -EALREADY)
2949 goto fail;
2950
2951 return;
2952
2953fail:
2954 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2955 outbuf, outlen, rc);
2956}
2957
8127d661
BH		 2958static int efx_ef10_ev_init(struct efx_channel *channel)
2959{
2960 MCDI_DECLARE_BUF(inbuf,
a995560a
BK		 2961 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2962 EFX_BUF_SIZE));
2963 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
8127d661
BH		 2964 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2965 struct efx_nic *efx = channel->efx;
2966 struct efx_ef10_nic_data *nic_data;
8127d661 2967 size_t inlen, outlen;
46e612b0 2968 unsigned int enabled, implemented;
8127d661
BH		 2969 dma_addr_t dma_addr;
2970 int rc;
2971 int i;
2972
2973 nic_data = efx->nic_data;
8127d661
BH		 2974
2975 /* Fill event queue with all ones (i.e. empty events) */
2976 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2977
2978 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2979 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2980 /* INIT_EVQ expects index in vector table, not absolute */
2981 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
8127d661
BH		 2982 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2983 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2984 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2985 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2986 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2987 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2988 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2989
a995560a
BK		 2990 if (nic_data->datapath_caps2 &
2991 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
2992 /* Use the new generic approach to specifying event queue
2993 * configuration, requesting lower latency or higher throughput.
2994 * The options that actually get used appear in the output.
2995 */
2996 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
2997 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
2998 INIT_EVQ_V2_IN_FLAG_TYPE,
2999 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3000 } else {
3001 bool cut_thru = !(nic_data->datapath_caps &
3002 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3003
3004 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3005 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3006 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3007 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3008 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3009 }
3010
8127d661
BH		 3011 dma_addr = channel->eventq.buf.dma_addr;
3012 for (i = 0; i < entries; ++i) {
3013 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3014 dma_addr += EFX_BUF_SIZE;
3015 }
3016
3017 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3018
3019 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3020 outbuf, sizeof(outbuf), &outlen);
a995560a
BK		 3021
3022 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3023 netif_dbg(efx, drv, efx->net_dev,
3024 "Channel %d using event queue flags %08x\n",
3025 channel->channel,
3026 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3027
8127d661 3028 /* IRQ return is ignored */
46e612b0
DP		 3029 if (channel->channel || rc)
3030 return rc;
8127d661 3031
46e612b0
DP		 3032 /* Successfully created event queue on channel 0 */
3033 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed 3034 if (rc == -ENOSYS) {
d95e329a
BK		 3035 /* GET_WORKAROUNDS was implemented before this workaround,
3036 * thus it must be unavailable in this firmware.
832dc9ed
EC		 3037 */
3038 nic_data->workaround_26807 = false;
3039 rc = 0;
3040 } else if (rc) {
8127d661 3041 goto fail;
832dc9ed
EC		 3042 } else {
3043 nic_data->workaround_26807 =
3044 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3045
3046 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3047 !nic_data->workaround_26807) {
5a55a72a
DP		 3048 unsigned int flags;
3049
34ccfe6f
DP		 3050 rc = efx_mcdi_set_workaround(efx,
3051 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 3052 true, &flags);
3053
3054 if (!rc) {
3055 if (flags &
3056 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3057 netif_info(efx, drv, efx->net_dev,
3058 "other functions on NIC have been reset\n");
abd86a55
DP		 3059
3060 /* With MCFW v4.6.x and earlier, the
3061 * boot count will have incremented,
3062 * so re-read the warm_boot_count
3063 * value now to ensure this function
3064 * doesn't think it has changed next
3065 * time it checks.
3066 */
3067 rc = efx_ef10_get_warm_boot_count(efx);
3068 if (rc >= 0) {
3069 nic_data->warm_boot_count = rc;
3070 rc = 0;
3071 }
5a55a72a 3072 }
832dc9ed 3073 nic_data->workaround_26807 = true;
5a55a72a 3074 } else if (rc == -EPERM) {
832dc9ed 3075 rc = 0;
5a55a72a 3076 }
832dc9ed 3077 }
46e612b0
DP		 3078 }
3079
3080 if (!rc)
3081 return 0;
8127d661
BH		 3082
3083fail:
46e612b0
DP		 3084 efx_ef10_ev_fini(channel);
3085 return rc;
8127d661
BH		 3086}
3087
3088static void efx_ef10_ev_remove(struct efx_channel *channel)
3089{
3090 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3091}
3092
3093static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3094 unsigned int rx_queue_label)
3095{
3096 struct efx_nic *efx = rx_queue->efx;
3097
3098 netif_info(efx, hw, efx->net_dev,
3099 "rx event arrived on queue %d labeled as queue %u\n",
3100 efx_rx_queue_index(rx_queue), rx_queue_label);
3101
3102 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3103}
3104
3105static void
3106efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3107 unsigned int actual, unsigned int expected)
3108{
3109 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3110 struct efx_nic *efx = rx_queue->efx;
3111
3112 netif_info(efx, hw, efx->net_dev,
3113 "dropped %d events (index=%d expected=%d)\n",
3114 dropped, actual, expected);
3115
3116 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3117}
3118
3119/* partially received RX was aborted. clean up. */
3120static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3121{
3122 unsigned int rx_desc_ptr;
3123
8127d661
BH		 3124 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3125 "scattered RX aborted (dropping %u buffers)\n",
3126 rx_queue->scatter_n);
3127
3128 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3129
3130 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3131 0, EFX_RX_PKT_DISCARD);
3132
3133 rx_queue->removed_count += rx_queue->scatter_n;
3134 rx_queue->scatter_n = 0;
3135 rx_queue->scatter_len = 0;
3136 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3137}
3138
3139static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3140 const efx_qword_t *event)
3141{
3142 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
3143 unsigned int n_descs, n_packets, i;
3144 struct efx_nic *efx = channel->efx;
3145 struct efx_rx_queue *rx_queue;
3146 bool rx_cont;
3147 u16 flags = 0;
3148
3149 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3150 return 0;
3151
3152 /* Basic packet information */
3153 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3154 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3155 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3156 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3157 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3158
48ce5634
BH		 3159 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3160 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3161 EFX_QWORD_FMT "\n",
3162 EFX_QWORD_VAL(*event));
8127d661
BH		 3163
3164 rx_queue = efx_channel_get_rx_queue(channel);
3165
3166 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3167 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3168
3169 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3170 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3171
3172 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 3173 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3174
8127d661
BH		 3175 /* detect rx abort */
3176 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 3177 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3178 netdev_WARN(efx->net_dev,
3179 "invalid RX abort: scatter_n=%u event="
3180 EFX_QWORD_FMT "\n",
3181 rx_queue->scatter_n,
3182 EFX_QWORD_VAL(*event));
8127d661
BH		 3183 efx_ef10_handle_rx_abort(rx_queue);
3184 return 0;
3185 }
3186
92a04168
BH		 3187 /* Check that RX completion merging is valid, i.e.
3188 * the current firmware supports it and this is a
3189 * non-scattered packet.
3190 */
3191 if (!(nic_data->datapath_caps &
3192 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3193 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 3194 efx_ef10_handle_rx_bad_lbits(
3195 rx_queue, next_ptr_lbits,
3196 (rx_queue->removed_count +
3197 rx_queue->scatter_n + 1) &
3198 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3199 return 0;
3200 }
3201
3202 /* Merged completion for multiple non-scattered packets */
3203 rx_queue->scatter_n = 1;
3204 rx_queue->scatter_len = 0;
3205 n_packets = n_descs;
3206 ++channel->n_rx_merge_events;
3207 channel->n_rx_merge_packets += n_packets;
3208 flags |= EFX_RX_PKT_PREFIX_LEN;
3209 } else {
3210 ++rx_queue->scatter_n;
3211 rx_queue->scatter_len += rx_bytes;
3212 if (rx_cont)
3213 return 0;
3214 n_packets = 1;
3215 }
3216
3217 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
3218 flags |= EFX_RX_PKT_DISCARD;
3219
3220 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
3221 channel->n_rx_ip_hdr_chksum_err += n_packets;
3222 } else if (unlikely(EFX_QWORD_FIELD(*event,
3223 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
3224 channel->n_rx_tcp_udp_chksum_err += n_packets;
3225 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3226 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
3227 flags |= EFX_RX_PKT_CSUMMED;
3228 }
3229
3230 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3231 flags |= EFX_RX_PKT_TCP;
3232
3233 channel->irq_mod_score += 2 * n_packets;
3234
3235 /* Handle received packet(s) */
3236 for (i = 0; i < n_packets; i++) {
3237 efx_rx_packet(rx_queue,
3238 rx_queue->removed_count & rx_queue->ptr_mask,
3239 rx_queue->scatter_n, rx_queue->scatter_len,
3240 flags);
3241 rx_queue->removed_count += rx_queue->scatter_n;
3242 }
3243
3244 rx_queue->scatter_n = 0;
3245 rx_queue->scatter_len = 0;
3246
3247 return n_packets;
3248}
3249
3250static int
3251efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3252{
3253 struct efx_nic *efx = channel->efx;
3254 struct efx_tx_queue *tx_queue;
3255 unsigned int tx_ev_desc_ptr;
3256 unsigned int tx_ev_q_label;
3257 int tx_descs = 0;
3258
3259 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3260 return 0;
3261
3262 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3263 return 0;
3264
3265 /* Transmit completion */
3266 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3267 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3268 tx_queue = efx_channel_get_tx_queue(channel,
3269 tx_ev_q_label % EFX_TXQ_TYPES);
3270 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3271 tx_queue->ptr_mask);
3272 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3273
3274 return tx_descs;
3275}
3276
3277static void
3278efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3279{
3280 struct efx_nic *efx = channel->efx;
3281 int subcode;
3282
3283 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3284
3285 switch (subcode) {
3286 case ESE_DZ_DRV_TIMER_EV:
3287 case ESE_DZ_DRV_WAKE_UP_EV:
3288 break;
3289 case ESE_DZ_DRV_START_UP_EV:
3290 /* event queue init complete. ok. */
3291 break;
3292 default:
3293 netif_err(efx, hw, efx->net_dev,
3294 "channel %d unknown driver event type %d"
3295 " (data " EFX_QWORD_FMT ")\n",
3296 channel->channel, subcode,
3297 EFX_QWORD_VAL(*event));
3298
3299 }
3300}
3301
3302static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3303 efx_qword_t *event)
3304{
3305 struct efx_nic *efx = channel->efx;
3306 u32 subcode;
3307
3308 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3309
3310 switch (subcode) {
3311 case EFX_EF10_TEST:
3312 channel->event_test_cpu = raw_smp_processor_id();
3313 break;
3314 case EFX_EF10_REFILL:
3315 /* The queue must be empty, so we won't receive any rx
3316 * events, so efx_process_channel() won't refill the
3317 * queue. Refill it here
3318 */
cce28794 3319 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 3320 break;
3321 default:
3322 netif_err(efx, hw, efx->net_dev,
3323 "channel %d unknown driver event type %u"
3324 " (data " EFX_QWORD_FMT ")\n",
3325 channel->channel, (unsigned) subcode,
3326 EFX_QWORD_VAL(*event));
3327 }
3328}
3329
3330static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3331{
3332 struct efx_nic *efx = channel->efx;
3333 efx_qword_t event, *p_event;
3334 unsigned int read_ptr;
3335 int ev_code;
3336 int tx_descs = 0;
3337 int spent = 0;
3338
75363a46
EB		 3339 if (quota <= 0)
3340 return spent;
3341
8127d661
BH		 3342 read_ptr = channel->eventq_read_ptr;
3343
3344 for (;;) {
3345 p_event = efx_event(channel, read_ptr);
3346 event = *p_event;
3347
3348 if (!efx_event_present(&event))
3349 break;
3350
3351 EFX_SET_QWORD(*p_event);
3352
3353 ++read_ptr;
3354
3355 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3356
3357 netif_vdbg(efx, drv, efx->net_dev,
3358 "processing event on %d " EFX_QWORD_FMT "\n",
3359 channel->channel, EFX_QWORD_VAL(event));
3360
3361 switch (ev_code) {
3362 case ESE_DZ_EV_CODE_MCDI_EV:
3363 efx_mcdi_process_event(channel, &event);
3364 break;
3365 case ESE_DZ_EV_CODE_RX_EV:
3366 spent += efx_ef10_handle_rx_event(channel, &event);
3367 if (spent >= quota) {
3368 /* XXX can we split a merged event to
3369 * avoid going over-quota?
3370 */
3371 spent = quota;
3372 goto out;
3373 }
3374 break;
3375 case ESE_DZ_EV_CODE_TX_EV:
3376 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3377 if (tx_descs > efx->txq_entries) {
3378 spent = quota;
3379 goto out;
3380 } else if (++spent == quota) {
3381 goto out;
3382 }
3383 break;
3384 case ESE_DZ_EV_CODE_DRIVER_EV:
3385 efx_ef10_handle_driver_event(channel, &event);
3386 if (++spent == quota)
3387 goto out;
3388 break;
3389 case EFX_EF10_DRVGEN_EV:
3390 efx_ef10_handle_driver_generated_event(channel, &event);
3391 break;
3392 default:
3393 netif_err(efx, hw, efx->net_dev,
3394 "channel %d unknown event type %d"
3395 " (data " EFX_QWORD_FMT ")\n",
3396 channel->channel, ev_code,
3397 EFX_QWORD_VAL(event));
3398 }
3399 }
3400
3401out:
3402 channel->eventq_read_ptr = read_ptr;
3403 return spent;
3404}
3405
3406static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3407{
3408 struct efx_nic *efx = channel->efx;
3409 efx_dword_t rptr;
3410
3411 if (EFX_EF10_WORKAROUND_35388(efx)) {
3412 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3413 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3414 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3415 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3416
3417 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3418 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3419 ERF_DD_EVQ_IND_RPTR,
3420 (channel->eventq_read_ptr &
3421 channel->eventq_mask) >>
3422 ERF_DD_EVQ_IND_RPTR_WIDTH);
3423 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3424 channel->channel);
3425 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3426 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3427 ERF_DD_EVQ_IND_RPTR,
3428 channel->eventq_read_ptr &
3429 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3430 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3431 channel->channel);
3432 } else {
3433 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3434 channel->eventq_read_ptr &
3435 channel->eventq_mask);
3436 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3437 }
3438}
3439
3440static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3441{
3442 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3443 struct efx_nic *efx = channel->efx;
3444 efx_qword_t event;
3445 int rc;
3446
3447 EFX_POPULATE_QWORD_2(event,
3448 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3449 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3450
3451 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3452
3453 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3454 * already swapped the data to little-endian order.
3455 */
3456 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3457 sizeof(efx_qword_t));
3458
3459 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3460 NULL, 0, NULL);
3461 if (rc != 0)
3462 goto fail;
3463
3464 return;
3465
3466fail:
3467 WARN_ON(true);
3468 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3469}
3470
3471void efx_ef10_handle_drain_event(struct efx_nic *efx)
3472{
3473 if (atomic_dec_and_test(&efx->active_queues))
3474 wake_up(&efx->flush_wq);
3475
3476 WARN_ON(atomic_read(&efx->active_queues) < 0);
3477}
3478
3479static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3480{
3481 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3482 struct efx_channel *channel;
3483 struct efx_tx_queue *tx_queue;
3484 struct efx_rx_queue *rx_queue;
3485 int pending;
3486
3487 /* If the MC has just rebooted, the TX/RX queues will have already been
3488 * torn down, but efx->active_queues needs to be set to zero.
3489 */
3490 if (nic_data->must_realloc_vis) {
3491 atomic_set(&efx->active_queues, 0);
3492 return 0;
3493 }
3494
3495 /* Do not attempt to write to the NIC during EEH recovery */
3496 if (efx->state != STATE_RECOVERY) {
3497 efx_for_each_channel(channel, efx) {
3498 efx_for_each_channel_rx_queue(rx_queue, channel)
3499 efx_ef10_rx_fini(rx_queue);
3500 efx_for_each_channel_tx_queue(tx_queue, channel)
3501 efx_ef10_tx_fini(tx_queue);
3502 }
3503
3504 wait_event_timeout(efx->flush_wq,
3505 atomic_read(&efx->active_queues) == 0,
3506 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3507 pending = atomic_read(&efx->active_queues);
3508 if (pending) {
3509 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3510 pending);
3511 return -ETIMEDOUT;
3512 }
3513 }
3514
3515 return 0;
3516}
3517
e283546c
EC		 3518static void efx_ef10_prepare_flr(struct efx_nic *efx)
3519{
3520 atomic_set(&efx->active_queues, 0);
3521}
3522
8127d661
BH		 3523static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3524 const struct efx_filter_spec *right)
3525{
3526 if ((left->match_flags ^ right->match_flags) |
3527 ((left->flags ^ right->flags) &
3528 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3529 return false;
3530
3531 return memcmp(&left->outer_vid, &right->outer_vid,
3532 sizeof(struct efx_filter_spec) -
3533 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3534}
3535
3536static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3537{
3538 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3539 return jhash2((const u32 *)&spec->outer_vid,
3540 (sizeof(struct efx_filter_spec) -
3541 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3542 0);
3543 /* XXX should we randomise the initval? */
3544}
3545
3546/* Decide whether a filter should be exclusive or else should allow
3547 * delivery to additional recipients. Currently we decide that
3548 * filters for specific local unicast MAC and IP addresses are
3549 * exclusive.
3550 */
3551static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3552{
3553 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3554 !is_multicast_ether_addr(spec->loc_mac))
3555 return true;
3556
3557 if ((spec->match_flags &
3558 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3559 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3560 if (spec->ether_type == htons(ETH_P_IP) &&
3561 !ipv4_is_multicast(spec->loc_host[0]))
3562 return true;
3563 if (spec->ether_type == htons(ETH_P_IPV6) &&
3564 ((const u8 *)spec->loc_host)[0] != 0xff)
3565 return true;
3566 }
3567
3568 return false;
3569}
3570
3571static struct efx_filter_spec *
3572efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3573 unsigned int filter_idx)
3574{
3575 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3576 ~EFX_EF10_FILTER_FLAGS);
3577}
3578
3579static unsigned int
3580efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3581 unsigned int filter_idx)
3582{
3583 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3584}
3585
3586static void
3587efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3588 unsigned int filter_idx,
3589 const struct efx_filter_spec *spec,
3590 unsigned int flags)
3591{
3592 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3593}
3594
3595static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3596 const struct efx_filter_spec *spec,
3597 efx_dword_t *inbuf, u64 handle,
3598 bool replacing)
3599{
3600 struct efx_ef10_nic_data *nic_data = efx->nic_data;
dcb4123c 3601 u32 flags = spec->flags;
8127d661
BH		 3602
3603 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3604
dcb4123c
JC		 3605 /* Remove RSS flag if we don't have an RSS context. */
3606 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3607 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3608 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3609 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3610
8127d661
BH		 3611 if (replacing) {
3612 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3613 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3614 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3615 } else {
3616 u32 match_fields = 0;
3617
3618 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3619 efx_ef10_filter_is_exclusive(spec) ?
3620 MC_CMD_FILTER_OP_IN_OP_INSERT :
3621 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3622
3623 /* Convert match flags and values. Unlike almost
3624 * everything else in MCDI, these fields are in
3625 * network byte order.
3626 */
3627 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3628 match_fields |=
3629 is_multicast_ether_addr(spec->loc_mac) ?
3630 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3631 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3632#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3633 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3634 match_fields |= \
3635 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3636 mcdi_field ## _LBN; \
3637 BUILD_BUG_ON( \
3638 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3639 sizeof(spec->gen_field)); \
3640 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3641 &spec->gen_field, sizeof(spec->gen_field)); \
3642 }
3643 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3644 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3645 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3646 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3647 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3648 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3649 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3650 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3651 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3652 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3653#undef COPY_FIELD
3654 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3655 match_fields);
3656 }
3657
45b2449e 3658 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 3659 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3660 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3661 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3662 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 3663 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 3664 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3665 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 3666 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3667 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3668 0 : spec->dmaq_id);
8127d661 3669 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
dcb4123c 3670 (flags & EFX_FILTER_FLAG_RX_RSS) ?
8127d661
BH		 3671 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3672 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
dcb4123c 3673 if (flags & EFX_FILTER_FLAG_RX_RSS)
8127d661
BH		 3674 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3675 spec->rss_context !=
3676 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3677 spec->rss_context : nic_data->rx_rss_context);
3678}
3679
3680static int efx_ef10_filter_push(struct efx_nic *efx,
3681 const struct efx_filter_spec *spec,
3682 u64 *handle, bool replacing)
3683{
3684 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3685 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3686 int rc;
3687
3688 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3689 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3690 outbuf, sizeof(outbuf), NULL);
3691 if (rc == 0)
3692 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 3693 if (rc == -ENOSPC)
3694 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 3695 return rc;
3696}
3697
7ac0dd9d 3698static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
8127d661 3699{
7ac0dd9d
AR		 3700 unsigned int match_flags = spec->match_flags;
3701 u32 mcdi_flags = 0;
3702
3703 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3704 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3705 mcdi_flags |=
3706 is_multicast_ether_addr(spec->loc_mac) ?
3707 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3708 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3709 }
3710
3711#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3712 unsigned int old_match_flags = match_flags; \
3713 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3714 if (match_flags != old_match_flags) \
3715 mcdi_flags |= \
3716 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3717 mcdi_field ## _LBN); \
3718 }
3719 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3720 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3721 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3722 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3723 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3724 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3725 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3726 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3727 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3728 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3729#undef MAP_FILTER_TO_MCDI_FLAG
3730
3731 /* Did we map them all? */
3732 WARN_ON_ONCE(match_flags);
3733
3734 return mcdi_flags;
3735}
3736
3737static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3738 const struct efx_filter_spec *spec)
3739{
3740 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
8127d661
BH		 3741 unsigned int match_pri;
3742
3743 for (match_pri = 0;
3744 match_pri < table->rx_match_count;
3745 match_pri++)
7ac0dd9d 3746 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
8127d661
BH		 3747 return match_pri;
3748
3749 return -EPROTONOSUPPORT;
3750}
3751
3752static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3753 struct efx_filter_spec *spec,
3754 bool replace_equal)
3755{
3756 struct efx_ef10_filter_table *table = efx->filter_state;
3757 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3758 struct efx_filter_spec *saved_spec;
3759 unsigned int match_pri, hash;
3760 unsigned int priv_flags;
3761 bool replacing = false;
3762 int ins_index = -1;
3763 DEFINE_WAIT(wait);
3764 bool is_mc_recip;
3765 s32 rc;
3766
3767 /* For now, only support RX filters */
3768 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3769 EFX_FILTER_FLAG_RX)
3770 return -EINVAL;
3771
7ac0dd9d 3772 rc = efx_ef10_filter_pri(table, spec);
8127d661
BH		 3773 if (rc < 0)
3774 return rc;
3775 match_pri = rc;
3776
3777 hash = efx_ef10_filter_hash(spec);
3778 is_mc_recip = efx_filter_is_mc_recipient(spec);
3779 if (is_mc_recip)
3780 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3781
3782 /* Find any existing filters with the same match tuple or
3783 * else a free slot to insert at. If any of them are busy,
3784 * we have to wait and retry.
3785 */
3786 for (;;) {
3787 unsigned int depth = 1;
3788 unsigned int i;
3789
3790 spin_lock_bh(&efx->filter_lock);
3791
3792 for (;;) {
3793 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3794 saved_spec = efx_ef10_filter_entry_spec(table, i);
3795
3796 if (!saved_spec) {
3797 if (ins_index < 0)
3798 ins_index = i;
3799 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3800 if (table->entry[i].spec &
3801 EFX_EF10_FILTER_FLAG_BUSY)
3802 break;
3803 if (spec->priority < saved_spec->priority &&
7665d1ab 3804 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3805 rc = -EPERM;
3806 goto out_unlock;
3807 }
3808 if (!is_mc_recip) {
3809 /* This is the only one */
3810 if (spec->priority ==
3811 saved_spec->priority &&
3812 !replace_equal) {
3813 rc = -EEXIST;
3814 goto out_unlock;
3815 }
3816 ins_index = i;
3817 goto found;
3818 } else if (spec->priority >
3819 saved_spec->priority ||
3820 (spec->priority ==
3821 saved_spec->priority &&
3822 replace_equal)) {
3823 if (ins_index < 0)
3824 ins_index = i;
3825 else
3826 __set_bit(depth, mc_rem_map);
3827 }
3828 }
3829
3830 /* Once we reach the maximum search depth, use
3831 * the first suitable slot or return -EBUSY if
3832 * there was none
3833 */
3834 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3835 if (ins_index < 0) {
3836 rc = -EBUSY;
3837 goto out_unlock;
3838 }
3839 goto found;
3840 }
3841
3842 ++depth;
3843 }
3844
3845 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3846 spin_unlock_bh(&efx->filter_lock);
3847 schedule();
3848 }
3849
3850found:
3851 /* Create a software table entry if necessary, and mark it
3852 * busy. We might yet fail to insert, but any attempt to
3853 * insert a conflicting filter while we're waiting for the
3854 * firmware must find the busy entry.
3855 */
3856 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3857 if (saved_spec) {
7665d1ab
BH		 3858 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3859 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3860 /* Just make sure it won't be removed */
7665d1ab
BH		 3861 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3862 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3863 table->entry[ins_index].spec &=
b59e6ef8 3864 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3865 rc = ins_index;
3866 goto out_unlock;
3867 }
3868 replacing = true;
3869 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3870 } else {
3871 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3872 if (!saved_spec) {
3873 rc = -ENOMEM;
3874 goto out_unlock;
3875 }
3876 *saved_spec = *spec;
3877 priv_flags = 0;
3878 }
3879 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3880 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3881
3882 /* Mark lower-priority multicast recipients busy prior to removal */
3883 if (is_mc_recip) {
3884 unsigned int depth, i;
3885
3886 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3887 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3888 if (test_bit(depth, mc_rem_map))
3889 table->entry[i].spec |=
3890 EFX_EF10_FILTER_FLAG_BUSY;
3891 }
3892 }
3893
3894 spin_unlock_bh(&efx->filter_lock);
3895
3896 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3897 replacing);
3898
3899 /* Finalise the software table entry */
3900 spin_lock_bh(&efx->filter_lock);
3901 if (rc == 0) {
3902 if (replacing) {
3903 /* Update the fields that may differ */
7665d1ab
BH		 3904 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3905 saved_spec->flags |=
3906 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3907 saved_spec->priority = spec->priority;
7665d1ab 3908 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 3909 saved_spec->flags |= spec->flags;
3910 saved_spec->rss_context = spec->rss_context;
3911 saved_spec->dmaq_id = spec->dmaq_id;
3912 }
3913 } else if (!replacing) {
3914 kfree(saved_spec);
3915 saved_spec = NULL;
3916 }
3917 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3918
3919 /* Remove and finalise entries for lower-priority multicast
3920 * recipients
3921 */
3922 if (is_mc_recip) {
3923 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3924 unsigned int depth, i;
3925
3926 memset(inbuf, 0, sizeof(inbuf));
3927
3928 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3929 if (!test_bit(depth, mc_rem_map))
3930 continue;
3931
3932 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3933 saved_spec = efx_ef10_filter_entry_spec(table, i);
3934 priv_flags = efx_ef10_filter_entry_flags(table, i);
3935
3936 if (rc == 0) {
3937 spin_unlock_bh(&efx->filter_lock);
3938 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3939 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3940 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3941 table->entry[i].handle);
3942 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3943 inbuf, sizeof(inbuf),
3944 NULL, 0, NULL);
3945 spin_lock_bh(&efx->filter_lock);
3946 }
3947
3948 if (rc == 0) {
3949 kfree(saved_spec);
3950 saved_spec = NULL;
3951 priv_flags = 0;
3952 } else {
3953 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3954 }
3955 efx_ef10_filter_set_entry(table, i, saved_spec,
3956 priv_flags);
3957 }
3958 }
3959
3960 /* If successful, return the inserted filter ID */
3961 if (rc == 0)
3962 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3963
3964 wake_up_all(&table->waitq);
3965out_unlock:
3966 spin_unlock_bh(&efx->filter_lock);
3967 finish_wait(&table->waitq, &wait);
3968 return rc;
3969}
3970
9fd8095d 3971static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 3972{
3973 /* no need to do anything here on EF10 */
3974}
3975
3976/* Remove a filter.
b59e6ef8
BH		 3977 * If !by_index, remove by ID
3978 * If by_index, remove by index
8127d661
BH		 3979 * Filter ID may come from userland and must be range-checked.
3980 */
3981static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 3982 unsigned int priority_mask,
b59e6ef8 3983 u32 filter_id, bool by_index)
8127d661
BH		 3984{
3985 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3986 struct efx_ef10_filter_table *table = efx->filter_state;
3987 MCDI_DECLARE_BUF(inbuf,
3988 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3989 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3990 struct efx_filter_spec *spec;
3991 DEFINE_WAIT(wait);
3992 int rc;
3993
3994 /* Find the software table entry and mark it busy. Don't
3995 * remove it yet; any attempt to update while we're waiting
3996 * for the firmware must find the busy entry.
3997 */
3998 for (;;) {
3999 spin_lock_bh(&efx->filter_lock);
4000 if (!(table->entry[filter_idx].spec &
4001 EFX_EF10_FILTER_FLAG_BUSY))
4002 break;
4003 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4004 spin_unlock_bh(&efx->filter_lock);
4005 schedule();
4006 }
7665d1ab 4007
8127d661 4008 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 4009 if (!spec ||
b59e6ef8 4010 (!by_index &&
7ac0dd9d 4011 efx_ef10_filter_pri(table, spec) !=
8127d661
BH		 4012 filter_id / HUNT_FILTER_TBL_ROWS)) {
4013 rc = -ENOENT;
4014 goto out_unlock;
4015 }
7665d1ab
BH		 4016
4017 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 4018 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 4019 /* Just remove flags */
4020 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 4021 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 4022 rc = 0;
4023 goto out_unlock;
4024 }
4025
fbd79120 4026 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 4027 rc = -ENOENT;
4028 goto out_unlock;
4029 }
4030
8127d661
BH		 4031 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4032 spin_unlock_bh(&efx->filter_lock);
4033
7665d1ab 4034 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 4035 /* Reset to an automatic filter */
8127d661
BH		 4036
4037 struct efx_filter_spec new_spec = *spec;
4038
7665d1ab 4039 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 4040 new_spec.flags = (EFX_FILTER_FLAG_RX |
f1c2ef40
BK		 4041 (efx_rss_enabled(efx) ?
4042 EFX_FILTER_FLAG_RX_RSS : 0));
8127d661
BH		 4043 new_spec.dmaq_id = 0;
4044 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4045 rc = efx_ef10_filter_push(efx, &new_spec,
4046 &table->entry[filter_idx].handle,
4047 true);
4048
4049 spin_lock_bh(&efx->filter_lock);
4050 if (rc == 0)
4051 *spec = new_spec;
4052 } else {
4053 /* Really remove the filter */
4054
4055 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4056 efx_ef10_filter_is_exclusive(spec) ?
4057 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4058 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4059 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4060 table->entry[filter_idx].handle);
4061 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4062 inbuf, sizeof(inbuf), NULL, 0, NULL);
4063
4064 spin_lock_bh(&efx->filter_lock);
4065 if (rc == 0) {
4066 kfree(spec);
4067 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4068 }
4069 }
7665d1ab 4070
8127d661
BH		 4071 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4072 wake_up_all(&table->waitq);
4073out_unlock:
4074 spin_unlock_bh(&efx->filter_lock);
4075 finish_wait(&table->waitq, &wait);
4076 return rc;
4077}
4078
4079static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4080 enum efx_filter_priority priority,
4081 u32 filter_id)
4082{
fbd79120
BH		 4083 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4084 filter_id, false);
8127d661
BH		 4085}
4086
12fb0da4
EC		 4087static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
4088{
4089 return filter_id % HUNT_FILTER_TBL_ROWS;
4090}
4091
8c915620
EC		 4092static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4093 enum efx_filter_priority priority,
4094 u32 filter_id)
12fb0da4 4095{
8c915620
EC		 4096 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4097 return;
4098 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
12fb0da4
EC		 4099}
4100
8127d661
BH		 4101static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4102 enum efx_filter_priority priority,
4103 u32 filter_id, struct efx_filter_spec *spec)
4104{
4105 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
4106 struct efx_ef10_filter_table *table = efx->filter_state;
4107 const struct efx_filter_spec *saved_spec;
4108 int rc;
4109
4110 spin_lock_bh(&efx->filter_lock);
4111 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4112 if (saved_spec && saved_spec->priority == priority &&
7ac0dd9d 4113 efx_ef10_filter_pri(table, saved_spec) ==
8127d661
BH		 4114 filter_id / HUNT_FILTER_TBL_ROWS) {
4115 *spec = *saved_spec;
4116 rc = 0;
4117 } else {
4118 rc = -ENOENT;
4119 }
4120 spin_unlock_bh(&efx->filter_lock);
4121 return rc;
4122}
4123
fbd79120 4124static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 4125 enum efx_filter_priority priority)
4126{
fbd79120
BH		 4127 unsigned int priority_mask;
4128 unsigned int i;
4129 int rc;
4130
4131 priority_mask = (((1U << (priority + 1)) - 1) &
4132 ~(1U << EFX_FILTER_PRI_AUTO));
4133
4134 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4135 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4136 i, true);
4137 if (rc && rc != -ENOENT)
4138 return rc;
4139 }
4140
4141 return 0;
8127d661
BH		 4142}
4143
4144static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4145 enum efx_filter_priority priority)
4146{
4147 struct efx_ef10_filter_table *table = efx->filter_state;
4148 unsigned int filter_idx;
4149 s32 count = 0;
4150
4151 spin_lock_bh(&efx->filter_lock);
4152 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4153 if (table->entry[filter_idx].spec &&
4154 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4155 priority)
4156 ++count;
4157 }
4158 spin_unlock_bh(&efx->filter_lock);
4159 return count;
4160}
4161
4162static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4163{
4164 struct efx_ef10_filter_table *table = efx->filter_state;
4165
4166 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
4167}
4168
4169static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4170 enum efx_filter_priority priority,
4171 u32 *buf, u32 size)
4172{
4173 struct efx_ef10_filter_table *table = efx->filter_state;
4174 struct efx_filter_spec *spec;
4175 unsigned int filter_idx;
4176 s32 count = 0;
4177
4178 spin_lock_bh(&efx->filter_lock);
4179 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4180 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4181 if (spec && spec->priority == priority) {
4182 if (count == size) {
4183 count = -EMSGSIZE;
4184 break;
4185 }
7ac0dd9d 4186 buf[count++] = (efx_ef10_filter_pri(table, spec) *
8127d661
BH		 4187 HUNT_FILTER_TBL_ROWS +
4188 filter_idx);
4189 }
4190 }
4191 spin_unlock_bh(&efx->filter_lock);
4192 return count;
4193}
4194
4195#ifdef CONFIG_RFS_ACCEL
4196
4197static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4198
4199static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4200 struct efx_filter_spec *spec)
4201{
4202 struct efx_ef10_filter_table *table = efx->filter_state;
4203 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4204 struct efx_filter_spec *saved_spec;
4205 unsigned int hash, i, depth = 1;
4206 bool replacing = false;
4207 int ins_index = -1;
4208 u64 cookie;
4209 s32 rc;
4210
4211 /* Must be an RX filter without RSS and not for a multicast
4212 * destination address (RFS only works for connected sockets).
4213 * These restrictions allow us to pass only a tiny amount of
4214 * data through to the completion function.
4215 */
4216 EFX_WARN_ON_PARANOID(spec->flags !=
4217 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4218 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4219 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4220
4221 hash = efx_ef10_filter_hash(spec);
4222
4223 spin_lock_bh(&efx->filter_lock);
4224
4225 /* Find any existing filter with the same match tuple or else
4226 * a free slot to insert at. If an existing filter is busy,
4227 * we have to give up.
4228 */
4229 for (;;) {
4230 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4231 saved_spec = efx_ef10_filter_entry_spec(table, i);
4232
4233 if (!saved_spec) {
4234 if (ins_index < 0)
4235 ins_index = i;
4236 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4237 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4238 rc = -EBUSY;
4239 goto fail_unlock;
4240 }
8127d661
BH		 4241 if (spec->priority < saved_spec->priority) {
4242 rc = -EPERM;
4243 goto fail_unlock;
4244 }
4245 ins_index = i;
4246 break;
4247 }
4248
4249 /* Once we reach the maximum search depth, use the
4250 * first suitable slot or return -EBUSY if there was
4251 * none
4252 */
4253 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4254 if (ins_index < 0) {
4255 rc = -EBUSY;
4256 goto fail_unlock;
4257 }
4258 break;
4259 }
4260
4261 ++depth;
4262 }
4263
4264 /* Create a software table entry if necessary, and mark it
4265 * busy. We might yet fail to insert, but any attempt to
4266 * insert a conflicting filter while we're waiting for the
4267 * firmware must find the busy entry.
4268 */
4269 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4270 if (saved_spec) {
4271 replacing = true;
4272 } else {
4273 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4274 if (!saved_spec) {
4275 rc = -ENOMEM;
4276 goto fail_unlock;
4277 }
4278 *saved_spec = *spec;
4279 }
4280 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4281 EFX_EF10_FILTER_FLAG_BUSY);
4282
4283 spin_unlock_bh(&efx->filter_lock);
4284
4285 /* Pack up the variables needed on completion */
4286 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4287
4288 efx_ef10_filter_push_prep(efx, spec, inbuf,
4289 table->entry[ins_index].handle, replacing);
4290 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4291 MC_CMD_FILTER_OP_OUT_LEN,
4292 efx_ef10_filter_rfs_insert_complete, cookie);
4293
4294 return ins_index;
4295
4296fail_unlock:
4297 spin_unlock_bh(&efx->filter_lock);
4298 return rc;
4299}
4300
4301static void
4302efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4303 int rc, efx_dword_t *outbuf,
4304 size_t outlen_actual)
4305{
4306 struct efx_ef10_filter_table *table = efx->filter_state;
4307 unsigned int ins_index, dmaq_id;
4308 struct efx_filter_spec *spec;
4309 bool replacing;
4310
4311 /* Unpack the cookie */
4312 replacing = cookie >> 31;
4313 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4314 dmaq_id = cookie & 0xffff;
4315
4316 spin_lock_bh(&efx->filter_lock);
4317 spec = efx_ef10_filter_entry_spec(table, ins_index);
4318 if (rc == 0) {
4319 table->entry[ins_index].handle =
4320 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4321 if (replacing)
4322 spec->dmaq_id = dmaq_id;
4323 } else if (!replacing) {
4324 kfree(spec);
4325 spec = NULL;
4326 }
4327 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4328 spin_unlock_bh(&efx->filter_lock);
4329
4330 wake_up_all(&table->waitq);
4331}
4332
4333static void
4334efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4335 unsigned long filter_idx,
4336 int rc, efx_dword_t *outbuf,
4337 size_t outlen_actual);
4338
4339static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4340 unsigned int filter_idx)
4341{
4342 struct efx_ef10_filter_table *table = efx->filter_state;
4343 struct efx_filter_spec *spec =
4344 efx_ef10_filter_entry_spec(table, filter_idx);
4345 MCDI_DECLARE_BUF(inbuf,
4346 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4347 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4348
4349 if (!spec ||
4350 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4351 spec->priority != EFX_FILTER_PRI_HINT ||
4352 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4353 flow_id, filter_idx))
4354 return false;
4355
4356 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4357 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4358 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4359 table->entry[filter_idx].handle);
4360 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4361 efx_ef10_filter_rfs_expire_complete, filter_idx))
4362 return false;
4363
4364 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4365 return true;
4366}
4367
4368static void
4369efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4370 unsigned long filter_idx,
4371 int rc, efx_dword_t *outbuf,
4372 size_t outlen_actual)
4373{
4374 struct efx_ef10_filter_table *table = efx->filter_state;
4375 struct efx_filter_spec *spec =
4376 efx_ef10_filter_entry_spec(table, filter_idx);
4377
4378 spin_lock_bh(&efx->filter_lock);
4379 if (rc == 0) {
4380 kfree(spec);
4381 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4382 }
4383 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4384 wake_up_all(&table->waitq);
4385 spin_unlock_bh(&efx->filter_lock);
4386}
4387
4388#endif /* CONFIG_RFS_ACCEL */
4389
4390static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
4391{
4392 int match_flags = 0;
4393
4394#define MAP_FLAG(gen_flag, mcdi_field) { \
4395 u32 old_mcdi_flags = mcdi_flags; \
4396 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
4397 mcdi_field ## _LBN); \
4398 if (mcdi_flags != old_mcdi_flags) \
4399 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4400 }
4401 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4402 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4403 MAP_FLAG(REM_HOST, SRC_IP);
4404 MAP_FLAG(LOC_HOST, DST_IP);
4405 MAP_FLAG(REM_MAC, SRC_MAC);
4406 MAP_FLAG(REM_PORT, SRC_PORT);
4407 MAP_FLAG(LOC_MAC, DST_MAC);
4408 MAP_FLAG(LOC_PORT, DST_PORT);
4409 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4410 MAP_FLAG(INNER_VID, INNER_VLAN);
4411 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4412 MAP_FLAG(IP_PROTO, IP_PROTO);
4413#undef MAP_FLAG
4414
4415 /* Did we map them all? */
4416 if (mcdi_flags)
4417 return -EINVAL;
4418
4419 return match_flags;
4420}
4421
34813fe2
AR		 4422static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4423{
4424 struct efx_ef10_filter_table *table = efx->filter_state;
4425 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4426
4427 /* See comment in efx_ef10_filter_table_remove() */
4428 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4429 return;
4430
4431 if (!table)
4432 return;
4433
4434 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4435 efx_ef10_filter_del_vlan_internal(efx, vlan);
4436}
4437
7ac0dd9d
AR		 4438static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4439 enum efx_filter_match_flags match_flags)
4440{
4441 unsigned int match_pri;
4442 int mf;
4443
4444 for (match_pri = 0;
4445 match_pri < table->rx_match_count;
4446 match_pri++) {
4447 mf = efx_ef10_filter_match_flags_from_mcdi(
4448 table->rx_match_mcdi_flags[match_pri]);
4449 if (mf == match_flags)
4450 return true;
4451 }
4452
4453 return false;
4454}
4455
8127d661
BH		 4456static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4457{
4458 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4459 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
34813fe2 4460 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e4478ad1 4461 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 4462 unsigned int pd_match_pri, pd_match_count;
4463 struct efx_ef10_filter_table *table;
34813fe2 4464 struct efx_ef10_vlan *vlan;
8127d661
BH		 4465 size_t outlen;
4466 int rc;
4467
dd98708c
EC		 4468 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4469 return -EINVAL;
4470
4471 if (efx->filter_state) /* already probed */
4472 return 0;
4473
8127d661
BH		 4474 table = kzalloc(sizeof(*table), GFP_KERNEL);
4475 if (!table)
4476 return -ENOMEM;
4477
4478 /* Find out which RX filter types are supported, and their priorities */
4479 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4480 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4481 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4482 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4483 &outlen);
4484 if (rc)
4485 goto fail;
4486 pd_match_count = MCDI_VAR_ARRAY_LEN(
4487 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4488 table->rx_match_count = 0;
4489
4490 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4491 u32 mcdi_flags =
4492 MCDI_ARRAY_DWORD(
4493 outbuf,
4494 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4495 pd_match_pri);
4496 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4497 if (rc < 0) {
4498 netif_dbg(efx, probe, efx->net_dev,
4499 "%s: fw flags %#x pri %u not supported in driver\n",
4500 __func__, mcdi_flags, pd_match_pri);
4501 } else {
4502 netif_dbg(efx, probe, efx->net_dev,
4503 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4504 __func__, mcdi_flags, pd_match_pri,
4505 rc, table->rx_match_count);
7ac0dd9d
AR		 4506 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4507 table->rx_match_count++;
8127d661
BH		 4508 }
4509 }
4510
e4478ad1
MH		 4511 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4512 !(efx_ef10_filter_match_supported(table,
4513 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4514 efx_ef10_filter_match_supported(table,
4515 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4516 netif_info(efx, probe, net_dev,
4517 "VLAN filters are not supported in this firmware variant\n");
4518 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4519 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4520 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4521 }
4522
8127d661
BH		 4523 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4524 if (!table->entry) {
4525 rc = -ENOMEM;
4526 goto fail;
4527 }
4528
b071c3a2 4529 table->mc_promisc_last = false;
4a53ea8a
AR		 4530 table->vlan_filter =
4531 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
34813fe2 4532 INIT_LIST_HEAD(&table->vlan_list);
12fb0da4 4533
8127d661
BH		 4534 efx->filter_state = table;
4535 init_waitqueue_head(&table->waitq);
34813fe2
AR		 4536
4537 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4538 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4539 if (rc)
4540 goto fail_add_vlan;
4541 }
4542
8127d661
BH		 4543 return 0;
4544
34813fe2
AR		 4545fail_add_vlan:
4546 efx_ef10_filter_cleanup_vlans(efx);
4547 efx->filter_state = NULL;
8127d661
BH		 4548fail:
4549 kfree(table);
4550 return rc;
4551}
4552
0d322413
EC		 4553/* Caller must hold efx->filter_sem for read if race against
4554 * efx_ef10_filter_table_remove() is possible
4555 */
8127d661
BH		 4556static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4557{
4558 struct efx_ef10_filter_table *table = efx->filter_state;
4559 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4560 struct efx_filter_spec *spec;
4561 unsigned int filter_idx;
4562 bool failed = false;
4563 int rc;
4564
0d322413
EC		 4565 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4566
8127d661
BH		 4567 if (!nic_data->must_restore_filters)
4568 return;
4569
0d322413
EC		 4570 if (!table)
4571 return;
4572
8127d661
BH		 4573 spin_lock_bh(&efx->filter_lock);
4574
4575 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4576 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4577 if (!spec)
4578 continue;
4579
4580 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4581 spin_unlock_bh(&efx->filter_lock);
4582
4583 rc = efx_ef10_filter_push(efx, spec,
4584 &table->entry[filter_idx].handle,
4585 false);
4586 if (rc)
4587 failed = true;
4588
4589 spin_lock_bh(&efx->filter_lock);
4590 if (rc) {
4591 kfree(spec);
4592 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4593 } else {
4594 table->entry[filter_idx].spec &=
4595 ~EFX_EF10_FILTER_FLAG_BUSY;
4596 }
4597 }
4598
4599 spin_unlock_bh(&efx->filter_lock);
4600
4601 if (failed)
4602 netif_err(efx, hw, efx->net_dev,
4603 "unable to restore all filters\n");
4604 else
4605 nic_data->must_restore_filters = false;
4606}
4607
4608static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4609{
4610 struct efx_ef10_filter_table *table = efx->filter_state;
4611 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4612 struct efx_filter_spec *spec;
4613 unsigned int filter_idx;
4614 int rc;
4615
34813fe2 4616 efx_ef10_filter_cleanup_vlans(efx);
0d322413 4617 efx->filter_state = NULL;
dd98708c
EC		 4618 /* If we were called without locking, then it's not safe to free
4619 * the table as others might be using it. So we just WARN, leak
4620 * the memory, and potentially get an inconsistent filter table
4621 * state.
4622 * This should never actually happen.
4623 */
4624 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4625 return;
4626
0d322413
EC		 4627 if (!table)
4628 return;
4629
8127d661
BH		 4630 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4631 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4632 if (!spec)
4633 continue;
4634
4635 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4636 efx_ef10_filter_is_exclusive(spec) ?
4637 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4638 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4639 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4640 table->entry[filter_idx].handle);
e65a5109
BK		 4641 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4642 sizeof(inbuf), NULL, 0, NULL);
48ce5634 4643 if (rc)
e65a5109
BK		 4644 netif_info(efx, drv, efx->net_dev,
4645 "%s: filter %04x remove failed\n",
4646 __func__, filter_idx);
8127d661
BH		 4647 kfree(spec);
4648 }
4649
4650 vfree(table->entry);
4651 kfree(table);
4652}
4653
6a37958b
AR		 4654static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4655{
4656 struct efx_ef10_filter_table *table = efx->filter_state;
4657 unsigned int filter_idx;
4658
4659 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4660 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4661 if (!table->entry[filter_idx].spec)
4662 netif_dbg(efx, drv, efx->net_dev,
4663 "marked null spec old %04x:%04x\n", *id,
4664 filter_idx);
4665 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4666 *id = EFX_EF10_FILTER_ID_INVALID;
e65a5109 4667 }
6a37958b
AR		 4668}
4669
b3a3c03c
AR		 4670/* Mark old per-VLAN filters that may need to be removed */
4671static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4672 struct efx_ef10_filter_vlan *vlan)
8127d661
BH		 4673{
4674 struct efx_ef10_filter_table *table = efx->filter_state;
6a37958b 4675 unsigned int i;
8127d661 4676
12fb0da4 4677 for (i = 0; i < table->dev_uc_count; i++)
dc3273e0 4678 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
12fb0da4 4679 for (i = 0; i < table->dev_mc_count; i++)
dc3273e0
AR		 4680 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4681 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4682 efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4683 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
b3a3c03c
AR		 4684}
4685
34813fe2
AR		 4686/* Mark old filters that may need to be removed.
4687 * Caller must hold efx->filter_sem for read if race against
4688 * efx_ef10_filter_table_remove() is possible
4689 */
b3a3c03c
AR		 4690static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4691{
4692 struct efx_ef10_filter_table *table = efx->filter_state;
34813fe2 4693 struct efx_ef10_filter_vlan *vlan;
b3a3c03c
AR		 4694
4695 spin_lock_bh(&efx->filter_lock);
34813fe2
AR		 4696 list_for_each_entry(vlan, &table->vlan_list, list)
4697 _efx_ef10_filter_vlan_mark_old(efx, vlan);
8127d661 4698 spin_unlock_bh(&efx->filter_lock);
822b96f8
DP		 4699}
4700
afa4ce12 4701static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4702{
4703 struct efx_ef10_filter_table *table = efx->filter_state;
4704 struct net_device *net_dev = efx->net_dev;
4705 struct netdev_hw_addr *uc;
12fb0da4 4706 int addr_count;
822b96f8 4707 unsigned int i;
8127d661 4708
12fb0da4 4709 addr_count = netdev_uc_count(net_dev);
afa4ce12 4710 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
12fb0da4 4711 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 4712 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4713 i = 1;
4714 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4 4715 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
afa4ce12 4716 table->uc_promisc = true;
12fb0da4
EC		 4717 break;
4718 }
822b96f8
DP		 4719 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4720 i++;
4721 }
4722}
4723
afa4ce12 4724static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4725{
4726 struct efx_ef10_filter_table *table = efx->filter_state;
4727 struct net_device *net_dev = efx->net_dev;
4728 struct netdev_hw_addr *mc;
ab8b1f7c 4729 unsigned int i, addr_count;
822b96f8 4730
afa4ce12 4731 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
ab8b1f7c 4732
12fb0da4
EC		 4733 addr_count = netdev_mc_count(net_dev);
4734 i = 0;
ab8b1f7c 4735 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4 4736 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
afa4ce12 4737 table->mc_promisc = true;
12fb0da4
EC		 4738 break;
4739 }
ab8b1f7c
DP		 4740 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4741 i++;
8127d661 4742 }
12fb0da4
EC		 4743
4744 table->dev_mc_count = i;
822b96f8 4745}
8127d661 4746
12fb0da4 4747static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
b3a3c03c
AR		 4748 struct efx_ef10_filter_vlan *vlan,
4749 bool multicast, bool rollback)
822b96f8
DP		 4750{
4751 struct efx_ef10_filter_table *table = efx->filter_state;
4752 struct efx_ef10_dev_addr *addr_list;
f1c2ef40 4753 enum efx_filter_flags filter_flags;
822b96f8 4754 struct efx_filter_spec spec;
12fb0da4
EC		 4755 u8 baddr[ETH_ALEN];
4756 unsigned int i, j;
4757 int addr_count;
dc3273e0 4758 u16 *ids;
822b96f8
DP		 4759 int rc;
4760
4761 if (multicast) {
4762 addr_list = table->dev_mc_list;
12fb0da4 4763 addr_count = table->dev_mc_count;
dc3273e0 4764 ids = vlan->mc;
822b96f8
DP		 4765 } else {
4766 addr_list = table->dev_uc_list;
12fb0da4 4767 addr_count = table->dev_uc_count;
dc3273e0 4768 ids = vlan->uc;
8127d661
BH		 4769 }
4770
f1c2ef40
BK		 4771 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4772
822b96f8 4773 /* Insert/renew filters */
12fb0da4 4774 for (i = 0; i < addr_count; i++) {
f1c2ef40 4775 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
b3a3c03c 4776 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
b6f568e2
JC		 4777 rc = efx_ef10_filter_insert(efx, &spec, true);
4778 if (rc < 0) {
12fb0da4
EC		 4779 if (rollback) {
4780 netif_info(efx, drv, efx->net_dev,
4781 "efx_ef10_filter_insert failed rc=%d\n",
4782 rc);
4783 /* Fall back to promiscuous */
4784 for (j = 0; j < i; j++) {
12fb0da4
EC		 4785 efx_ef10_filter_remove_unsafe(
4786 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4787 ids[j]);
4788 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4789 }
4790 return rc;
4791 } else {
4792 /* mark as not inserted, and carry on */
4793 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 4794 }
8127d661 4795 }
dc3273e0 4796 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 4797 }
822b96f8 4798
12fb0da4
EC		 4799 if (multicast && rollback) {
4800 /* Also need an Ethernet broadcast filter */
f1c2ef40 4801 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4 4802 eth_broadcast_addr(baddr);
b3a3c03c 4803 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
8127d661 4804 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 4805 if (rc < 0) {
822b96f8 4806 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 4807 "Broadcast filter insert failed rc=%d\n", rc);
4808 /* Fall back to promiscuous */
4809 for (j = 0; j < i; j++) {
12fb0da4
EC		 4810 efx_ef10_filter_remove_unsafe(
4811 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4812 ids[j]);
4813 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4814 }
4815 return rc;
4816 } else {
dc3273e0 4817 EFX_WARN_ON_PARANOID(vlan->bcast !=
6a37958b 4818 EFX_EF10_FILTER_ID_INVALID);
dc3273e0 4819 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4 4820 }
8127d661 4821 }
12fb0da4
EC		 4822
4823 return 0;
4824}
4825
b3a3c03c
AR		 4826static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4827 struct efx_ef10_filter_vlan *vlan,
4828 bool multicast, bool rollback)
12fb0da4 4829{
12fb0da4 4830 struct efx_ef10_nic_data *nic_data = efx->nic_data;
f1c2ef40 4831 enum efx_filter_flags filter_flags;
12fb0da4
EC		 4832 struct efx_filter_spec spec;
4833 u8 baddr[ETH_ALEN];
4834 int rc;
4835
f1c2ef40
BK		 4836 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4837
4838 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4
EC		 4839
4840 if (multicast)
4841 efx_filter_set_mc_def(&spec);
4842 else
4843 efx_filter_set_uc_def(&spec);
4844
b3a3c03c
AR		 4845 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4846 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4847
12fb0da4
EC		 4848 rc = efx_ef10_filter_insert(efx, &spec, true);
4849 if (rc < 0) {
09a04204
BK		 4850 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4851 efx->net_dev,
4852 "%scast mismatch filter insert failed rc=%d\n",
4853 multicast ? "Multi" : "Uni", rc);
12fb0da4 4854 } else if (multicast) {
dc3273e0
AR		 4855 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4856 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 4857 if (!nic_data->workaround_26807) {
4858 /* Also need an Ethernet broadcast filter */
4859 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
f1c2ef40 4860 filter_flags, 0);
12fb0da4 4861 eth_broadcast_addr(baddr);
b3a3c03c 4862 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
12fb0da4
EC		 4863 rc = efx_ef10_filter_insert(efx, &spec, true);
4864 if (rc < 0) {
4865 netif_warn(efx, drv, efx->net_dev,
4866 "Broadcast filter insert failed rc=%d\n",
4867 rc);
4868 if (rollback) {
4869 /* Roll back the mc_def filter */
4870 efx_ef10_filter_remove_unsafe(
4871 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4872 vlan->mcdef);
4873 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4874 return rc;
4875 }
4876 } else {
dc3273e0 4877 EFX_WARN_ON_PARANOID(vlan->bcast !=
6a37958b 4878 EFX_EF10_FILTER_ID_INVALID);
dc3273e0 4879 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 4880 }
4881 }
4882 rc = 0;
4883 } else {
dc3273e0
AR		 4884 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4885 vlan->ucdef = rc;
12fb0da4
EC		 4886 rc = 0;
4887 }
4888 return rc;
822b96f8
DP		 4889}
4890
4891/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4892 * flag or removes these filters, we don't need to hold the filter_lock while
4893 * scanning for these filters.
4894 */
4895static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4896{
4897 struct efx_ef10_filter_table *table = efx->filter_state;
e65a5109
BK		 4898 int remove_failed = 0;
4899 int remove_noent = 0;
4900 int rc;
822b96f8 4901 int i;
8127d661 4902
8127d661
BH		 4903 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4904 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 4905 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
e65a5109
BK		 4906 rc = efx_ef10_filter_remove_internal(efx,
4907 1U << EFX_FILTER_PRI_AUTO, i, true);
4908 if (rc == -ENOENT)
4909 remove_noent++;
4910 else if (rc)
4911 remove_failed++;
8127d661
BH		 4912 }
4913 }
e65a5109
BK		 4914
4915 if (remove_failed)
4916 netif_info(efx, drv, efx->net_dev,
4917 "%s: failed to remove %d filters\n",
4918 __func__, remove_failed);
4919 if (remove_noent)
4920 netif_info(efx, drv, efx->net_dev,
4921 "%s: failed to remove %d non-existent filters\n",
4922 __func__, remove_noent);
8127d661
BH		 4923}
4924
7a186f47
DP		 4925static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4926{
4927 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4928 u8 mac_old[ETH_ALEN];
4929 int rc, rc2;
4930
4931 /* Only reconfigure a PF-created vport */
4932 if (is_zero_ether_addr(nic_data->vport_mac))
4933 return 0;
4934
4935 efx_device_detach_sync(efx);
4936 efx_net_stop(efx->net_dev);
4937 down_write(&efx->filter_sem);
4938 efx_ef10_filter_table_remove(efx);
4939 up_write(&efx->filter_sem);
4940
4941 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4942 if (rc)
4943 goto restore_filters;
4944
4945 ether_addr_copy(mac_old, nic_data->vport_mac);
4946 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4947 nic_data->vport_mac);
4948 if (rc)
4949 goto restore_vadaptor;
4950
4951 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4952 efx->net_dev->dev_addr);
4953 if (!rc) {
4954 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4955 } else {
4956 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4957 if (rc2) {
4958 /* Failed to add original MAC, so clear vport_mac */
4959 eth_zero_addr(nic_data->vport_mac);
4960 goto reset_nic;
4961 }
4962 }
4963
4964restore_vadaptor:
4965 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4966 if (rc2)
4967 goto reset_nic;
4968restore_filters:
4969 down_write(&efx->filter_sem);
4970 rc2 = efx_ef10_filter_table_probe(efx);
4971 up_write(&efx->filter_sem);
4972 if (rc2)
4973 goto reset_nic;
4974
4975 rc2 = efx_net_open(efx->net_dev);
4976 if (rc2)
4977 goto reset_nic;
4978
4979 netif_device_attach(efx->net_dev);
4980
4981 return rc;
4982
4983reset_nic:
4984 netif_err(efx, drv, efx->net_dev,
4985 "Failed to restore when changing MAC address - scheduling reset\n");
4986 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4987
4988 return rc ? rc : rc2;
4989}
4990
822b96f8
DP		 4991/* Caller must hold efx->filter_sem for read if race against
4992 * efx_ef10_filter_table_remove() is possible
4993 */
34813fe2
AR		 4994static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4995 struct efx_ef10_filter_vlan *vlan)
822b96f8
DP		 4996{
4997 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 4998 struct efx_ef10_nic_data *nic_data = efx->nic_data;
b3a3c03c 4999
4a53ea8a
AR		 5000 /* Do not install unspecified VID if VLAN filtering is enabled.
5001 * Do not install all specified VIDs if VLAN filtering is disabled.
5002 */
5003 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5004 return;
5005
12fb0da4 5006 /* Insert/renew unicast filters */
afa4ce12 5007 if (table->uc_promisc) {
b3a3c03c
AR		 5008 efx_ef10_filter_insert_def(efx, vlan, false, false);
5009 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
12fb0da4
EC		 5010 } else {
5011 /* If any of the filters failed to insert, fall back to
5012 * promiscuous mode - add in the uc_def filter. But keep
5013 * our individual unicast filters.
5014 */
b3a3c03c
AR		 5015 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5016 efx_ef10_filter_insert_def(efx, vlan, false, false);
12fb0da4 5017 }
ab8b1f7c 5018
12fb0da4 5019 /* Insert/renew multicast filters */
ab8b1f7c
DP		 5020 /* If changing promiscuous state with cascaded multicast filters, remove
5021 * old filters first, so that packets are dropped rather than duplicated
5022 */
afa4ce12
AR		 5023 if (nic_data->workaround_26807 &&
5024 table->mc_promisc_last != table->mc_promisc)
ab8b1f7c 5025 efx_ef10_filter_remove_old(efx);
afa4ce12 5026 if (table->mc_promisc) {
12fb0da4
EC		 5027 if (nic_data->workaround_26807) {
5028 /* If we failed to insert promiscuous filters, rollback
5029 * and fall back to individual multicast filters
5030 */
b3a3c03c 5031 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
12fb0da4
EC		 5032 /* Changing promisc state, so remove old filters */
5033 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 5034 efx_ef10_filter_insert_addr_list(efx, vlan,
5035 true, false);
12fb0da4
EC		 5036 }
5037 } else {
5038 /* If we failed to insert promiscuous filters, don't
5039 * rollback. Regardless, also insert the mc_list
5040 */
b3a3c03c
AR		 5041 efx_ef10_filter_insert_def(efx, vlan, true, false);
5042 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
12fb0da4
EC		 5043 }
5044 } else {
5045 /* If any filters failed to insert, rollback and fall back to
5046 * promiscuous mode - mc_def filter and maybe broadcast. If
5047 * that fails, roll back again and insert as many of our
5048 * individual multicast filters as we can.
5049 */
b3a3c03c 5050 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
12fb0da4
EC		 5051 /* Changing promisc state, so remove old filters */
5052 if (nic_data->workaround_26807)
5053 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 5054 if (efx_ef10_filter_insert_def(efx, vlan, true, true))
5055 efx_ef10_filter_insert_addr_list(efx, vlan,
5056 true, false);
12fb0da4
EC		 5057 }
5058 }
34813fe2
AR		 5059}
5060
5061/* Caller must hold efx->filter_sem for read if race against
5062 * efx_ef10_filter_table_remove() is possible
5063 */
5064static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5065{
5066 struct efx_ef10_filter_table *table = efx->filter_state;
5067 struct net_device *net_dev = efx->net_dev;
5068 struct efx_ef10_filter_vlan *vlan;
4a53ea8a 5069 bool vlan_filter;
34813fe2
AR		 5070
5071 if (!efx_dev_registered(efx))
5072 return;
5073
5074 if (!table)
5075 return;
5076
5077 efx_ef10_filter_mark_old(efx);
5078
5079 /* Copy/convert the address lists; add the primary station
5080 * address and broadcast address
5081 */
5082 netif_addr_lock_bh(net_dev);
5083 efx_ef10_filter_uc_addr_list(efx);
5084 efx_ef10_filter_mc_addr_list(efx);
5085 netif_addr_unlock_bh(net_dev);
5086
4a53ea8a
AR		 5087 /* If VLAN filtering changes, all old filters are finally removed.
5088 * Do it in advance to avoid conflicts for unicast untagged and
5089 * VLAN 0 tagged filters.
5090 */
5091 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5092 if (table->vlan_filter != vlan_filter) {
5093 table->vlan_filter = vlan_filter;
5094 efx_ef10_filter_remove_old(efx);
5095 }
5096
34813fe2
AR		 5097 list_for_each_entry(vlan, &table->vlan_list, list)
5098 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
822b96f8
DP		 5099
5100 efx_ef10_filter_remove_old(efx);
afa4ce12 5101 table->mc_promisc_last = table->mc_promisc;
822b96f8
DP		 5102}
5103
34813fe2
AR		 5104static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5105{
5106 struct efx_ef10_filter_table *table = efx->filter_state;
5107 struct efx_ef10_filter_vlan *vlan;
5108
5109 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5110
5111 list_for_each_entry(vlan, &table->vlan_list, list) {
5112 if (vlan->vid == vid)
5113 return vlan;
5114 }
5115
5116 return NULL;
5117}
5118
5119static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5120{
5121 struct efx_ef10_filter_table *table = efx->filter_state;
5122 struct efx_ef10_filter_vlan *vlan;
5123 unsigned int i;
5124
5125 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5126 return -EINVAL;
5127
5128 vlan = efx_ef10_filter_find_vlan(efx, vid);
5129 if (WARN_ON(vlan)) {
5130 netif_err(efx, drv, efx->net_dev,
5131 "VLAN %u already added\n", vid);
5132 return -EALREADY;
5133 }
5134
5135 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5136 if (!vlan)
5137 return -ENOMEM;
5138
5139 vlan->vid = vid;
5140
5141 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5142 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5143 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5144 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5145 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
5146 vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
5147 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
5148
5149 list_add_tail(&vlan->list, &table->vlan_list);
5150
5151 if (efx_dev_registered(efx))
5152 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5153
5154 return 0;
5155}
5156
5157static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5158 struct efx_ef10_filter_vlan *vlan)
5159{
5160 unsigned int i;
5161
5162 /* See comment in efx_ef10_filter_table_remove() */
5163 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5164 return;
5165
5166 list_del(&vlan->list);
5167
8c915620 5168 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
34813fe2 5169 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 5170 vlan->uc[i]);
5171 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
34813fe2 5172 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 5173 vlan->mc[i]);
5174 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
5175 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
5176 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
34813fe2
AR		 5177
5178 kfree(vlan);
5179}
5180
5181static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5182{
5183 struct efx_ef10_filter_vlan *vlan;
5184
5185 /* See comment in efx_ef10_filter_table_remove() */
5186 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5187 return;
5188
5189 vlan = efx_ef10_filter_find_vlan(efx, vid);
5190 if (!vlan) {
5191 netif_err(efx, drv, efx->net_dev,
5192 "VLAN %u not found in filter state\n", vid);
5193 return;
5194 }
5195
5196 efx_ef10_filter_del_vlan_internal(efx, vlan);
5197}
5198
910c8789
SS		 5199static int efx_ef10_set_mac_address(struct efx_nic *efx)
5200{
5201 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5202 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5203 bool was_enabled = efx->port_enabled;
5204 int rc;
5205
5206 efx_device_detach_sync(efx);
5207 efx_net_stop(efx->net_dev);
d248953a
MH		 5208
5209 mutex_lock(&efx->mac_lock);
910c8789
SS		 5210 down_write(&efx->filter_sem);
5211 efx_ef10_filter_table_remove(efx);
5212
5213 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5214 efx->net_dev->dev_addr);
5215 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5216 nic_data->vport_id);
535a6177
DP		 5217 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5218 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 5219
5220 efx_ef10_filter_table_probe(efx);
5221 up_write(&efx->filter_sem);
d248953a
MH		 5222 mutex_unlock(&efx->mac_lock);
5223
910c8789
SS		 5224 if (was_enabled)
5225 efx_net_open(efx->net_dev);
5226 netif_device_attach(efx->net_dev);
5227
9e9f665a
DP		 5228#ifdef CONFIG_SFC_SRIOV
5229 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 5230 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5231
9e9f665a
DP		 5232 if (rc == -EPERM) {
5233 struct efx_nic *efx_pf;
910c8789 5234
9e9f665a
DP		 5235 /* Switch to PF and change MAC address on vport */
5236 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 5237
9e9f665a
DP		 5238 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5239 nic_data->vf_index,
5240 efx->net_dev->dev_addr);
5241 } else if (!rc) {
910c8789
SS		 5242 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5243 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5244 unsigned int i;
5245
9e9f665a
DP		 5246 /* MAC address successfully changed by VF (with MAC
5247 * spoofing) so update the parent PF if possible.
5248 */
910c8789
SS		 5249 for (i = 0; i < efx_pf->vf_count; ++i) {
5250 struct ef10_vf *vf = nic_data->vf + i;
5251
5252 if (vf->efx == efx) {
5253 ether_addr_copy(vf->mac,
5254 efx->net_dev->dev_addr);
5255 return 0;
5256 }
5257 }
5258 }
9e9f665a 5259 } else
910c8789 5260#endif
9e9f665a
DP		 5261 if (rc == -EPERM) {
5262 netif_err(efx, drv, efx->net_dev,
5263 "Cannot change MAC address; use sfboot to enable"
5264 " mac-spoofing on this interface\n");
7a186f47
DP		 5265 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5266 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5267 * fall-back to the method of changing the MAC address on the
5268 * vport. This only applies to PFs because such versions of
5269 * MCFW do not support VFs.
5270 */
5271 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 5272 } else {
5273 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5274 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 5275 }
5276
910c8789
SS		 5277 return rc;
5278}
5279
8127d661
BH		 5280static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5281{
5282 efx_ef10_filter_sync_rx_mode(efx);
5283
5284 return efx_mcdi_set_mac(efx);
5285}
5286
862f894c
SS		 5287static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5288{
5289 efx_ef10_filter_sync_rx_mode(efx);
5290
5291 return 0;
5292}
5293
74cd60a4
JC		 5294static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5295{
5296 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5297
5298 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5299 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5300 NULL, 0, NULL);
5301}
5302
5303/* MC BISTs follow a different poll mechanism to phy BISTs.
5304 * The BIST is done in the poll handler on the MC, and the MCDI command
5305 * will block until the BIST is done.
5306 */
5307static int efx_ef10_poll_bist(struct efx_nic *efx)
5308{
5309 int rc;
5310 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5311 size_t outlen;
5312 u32 result;
5313
5314 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5315 outbuf, sizeof(outbuf), &outlen);
5316 if (rc != 0)
5317 return rc;
5318
5319 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5320 return -EIO;
5321
5322 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5323 switch (result) {
5324 case MC_CMD_POLL_BIST_PASSED:
5325 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5326 return 0;
5327 case MC_CMD_POLL_BIST_TIMEOUT:
5328 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5329 return -EIO;
5330 case MC_CMD_POLL_BIST_FAILED:
5331 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5332 return -EIO;
5333 default:
5334 netif_err(efx, hw, efx->net_dev,
5335 "BIST returned unknown result %u", result);
5336 return -EIO;
5337 }
5338}
5339
5340static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5341{
5342 int rc;
5343
5344 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5345
5346 rc = efx_ef10_start_bist(efx, bist_type);
5347 if (rc != 0)
5348 return rc;
5349
5350 return efx_ef10_poll_bist(efx);
5351}
5352
5353static int
5354efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5355{
5356 int rc, rc2;
5357
5358 efx_reset_down(efx, RESET_TYPE_WORLD);
5359
5360 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5361 NULL, 0, NULL, 0, NULL);
5362 if (rc != 0)
5363 goto out;
5364
5365 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5366 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5367
5368 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5369
5370out:
27324820
DP		 5371 if (rc == -EPERM)
5372 rc = 0;
74cd60a4
JC		 5373 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5374 return rc ? rc : rc2;
5375}
5376
8127d661
BH		 5377#ifdef CONFIG_SFC_MTD
5378
5379struct efx_ef10_nvram_type_info {
5380 u16 type, type_mask;
5381 u8 port;
5382 const char *name;
5383};
5384
5385static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5386 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5387 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5388 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5389 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5390 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5391 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5392 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5393 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5394 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 5395 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 5396 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5397};
5398
5399static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5400 struct efx_mcdi_mtd_partition *part,
5401 unsigned int type)
5402{
5403 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5404 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5405 const struct efx_ef10_nvram_type_info *info;
5406 size_t size, erase_size, outlen;
5407 bool protected;
5408 int rc;
5409
5410 for (info = efx_ef10_nvram_types; ; info++) {
5411 if (info ==
5412 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5413 return -ENODEV;
5414 if ((type & ~info->type_mask) == info->type)
5415 break;
5416 }
5417 if (info->port != efx_port_num(efx))
5418 return -ENODEV;
5419
5420 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5421 if (rc)
5422 return rc;
5423 if (protected)
5424 return -ENODEV; /* hide it */
5425
5426 part->nvram_type = type;
5427
5428 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5429 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5430 outbuf, sizeof(outbuf), &outlen);
5431 if (rc)
5432 return rc;
5433 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5434 return -EIO;
5435 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5436 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5437 part->fw_subtype = MCDI_DWORD(outbuf,
5438 NVRAM_METADATA_OUT_SUBTYPE);
5439
5440 part->common.dev_type_name = "EF10 NVRAM manager";
5441 part->common.type_name = info->name;
5442
5443 part->common.mtd.type = MTD_NORFLASH;
5444 part->common.mtd.flags = MTD_CAP_NORFLASH;
5445 part->common.mtd.size = size;
5446 part->common.mtd.erasesize = erase_size;
5447
5448 return 0;
5449}
5450
5451static int efx_ef10_mtd_probe(struct efx_nic *efx)
5452{
5453 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5454 struct efx_mcdi_mtd_partition *parts;
5455 size_t outlen, n_parts_total, i, n_parts;
5456 unsigned int type;
5457 int rc;
5458
5459 ASSERT_RTNL();
5460
5461 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5462 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5463 outbuf, sizeof(outbuf), &outlen);
5464 if (rc)
5465 return rc;
5466 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5467 return -EIO;
5468
5469 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5470 if (n_parts_total >
5471 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5472 return -EIO;
5473
5474 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5475 if (!parts)
5476 return -ENOMEM;
5477
5478 n_parts = 0;
5479 for (i = 0; i < n_parts_total; i++) {
5480 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5481 i);
5482 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5483 if (rc == 0)
5484 n_parts++;
5485 else if (rc != -ENODEV)
5486 goto fail;
5487 }
5488
5489 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5490fail:
5491 if (rc)
5492 kfree(parts);
5493 return rc;
5494}
5495
5496#endif /* CONFIG_SFC_MTD */
5497
5498static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5499{
5500 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5501}
5502
02246a7f
SS		 5503static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5504 u32 host_time) {}
5505
bd9a265d
JC		 5506static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5507 bool temp)
5508{
5509 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5510 int rc;
5511
5512 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5513 channel->sync_events_state == SYNC_EVENTS_VALID ||
5514 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5515 return 0;
5516 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5517
5518 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5519 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5520 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5521 channel->channel);
5522
5523 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5524 inbuf, sizeof(inbuf), NULL, 0, NULL);
5525
5526 if (rc != 0)
5527 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5528 SYNC_EVENTS_DISABLED;
5529
5530 return rc;
5531}
5532
5533static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5534 bool temp)
5535{
5536 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5537 int rc;
5538
5539 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5540 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5541 return 0;
5542 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5543 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5544 return 0;
5545 }
5546 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5547 SYNC_EVENTS_DISABLED;
5548
5549 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5550 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5551 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5552 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5553 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5554 channel->channel);
5555
5556 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5557 inbuf, sizeof(inbuf), NULL, 0, NULL);
5558
5559 return rc;
5560}
5561
5562static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5563 bool temp)
5564{
5565 int (*set)(struct efx_channel *channel, bool temp);
5566 struct efx_channel *channel;
5567
5568 set = en ?
5569 efx_ef10_rx_enable_timestamping :
5570 efx_ef10_rx_disable_timestamping;
5571
5572 efx_for_each_channel(channel, efx) {
5573 int rc = set(channel, temp);
5574 if (en && rc != 0) {
5575 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5576 return rc;
5577 }
5578 }
5579
5580 return 0;
5581}
5582
02246a7f
SS		 5583static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5584 struct hwtstamp_config *init)
5585{
5586 return -EOPNOTSUPP;
5587}
5588
bd9a265d
JC		 5589static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5590 struct hwtstamp_config *init)
5591{
5592 int rc;
5593
5594 switch (init->rx_filter) {
5595 case HWTSTAMP_FILTER_NONE:
5596 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5597 /* if TX timestamping is still requested then leave PTP on */
5598 return efx_ptp_change_mode(efx,
5599 init->tx_type != HWTSTAMP_TX_OFF, 0);
5600 case HWTSTAMP_FILTER_ALL:
5601 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5602 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5603 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5604 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5605 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5606 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5607 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5608 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5609 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5610 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5611 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5612 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5613 init->rx_filter = HWTSTAMP_FILTER_ALL;
5614 rc = efx_ptp_change_mode(efx, true, 0);
5615 if (!rc)
5616 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5617 if (rc)
5618 efx_ptp_change_mode(efx, false, 0);
5619 return rc;
5620 default:
5621 return -ERANGE;
5622 }
5623}
5624
08a7b29b
BK		 5625static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
5626 struct netdev_phys_item_id *ppid)
5627{
5628 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5629
5630 if (!is_valid_ether_addr(nic_data->port_id))
5631 return -EOPNOTSUPP;
5632
5633 ppid->id_len = ETH_ALEN;
5634 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
5635
5636 return 0;
5637}
5638
4a53ea8a
AR		 5639static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5640{
5641 if (proto != htons(ETH_P_8021Q))
5642 return -EINVAL;
5643
5644 return efx_ef10_add_vlan(efx, vid);
5645}
5646
5647static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5648{
5649 if (proto != htons(ETH_P_8021Q))
5650 return -EINVAL;
5651
5652 return efx_ef10_del_vlan(efx, vid);
5653}
5654
100a9db5
AR		 5655#define EF10_OFFLOAD_FEATURES \
5656 (NETIF_F_IP_CSUM | \
4a53ea8a 5657 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 5658 NETIF_F_IPV6_CSUM | \
5659 NETIF_F_RXHASH | \
5660 NETIF_F_NTUPLE)
5661
02246a7f 5662const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 5663 .is_vf = true,
02246a7f
SS		 5664 .mem_bar = EFX_MEM_VF_BAR,
5665 .mem_map_size = efx_ef10_mem_map_size,
5666 .probe = efx_ef10_probe_vf,
5667 .remove = efx_ef10_remove,
5668 .dimension_resources = efx_ef10_dimension_resources,
5669 .init = efx_ef10_init_nic,
5670 .fini = efx_port_dummy_op_void,
087e9025 5671 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 5672 .map_reset_flags = efx_ef10_map_reset_flags,
5673 .reset = efx_ef10_reset,
5674 .probe_port = efx_mcdi_port_probe,
5675 .remove_port = efx_mcdi_port_remove,
5676 .fini_dmaq = efx_ef10_fini_dmaq,
5677 .prepare_flr = efx_ef10_prepare_flr,
5678 .finish_flr = efx_port_dummy_op_void,
5679 .describe_stats = efx_ef10_describe_stats,
d7788196 5680 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 5681 .start_stats = efx_port_dummy_op_void,
5682 .pull_stats = efx_port_dummy_op_void,
5683 .stop_stats = efx_port_dummy_op_void,
5684 .set_id_led = efx_mcdi_set_id_led,
5685 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 5686 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 5687 .check_mac_fault = efx_mcdi_mac_check_fault,
5688 .reconfigure_port = efx_mcdi_port_reconfigure,
5689 .get_wol = efx_ef10_get_wol_vf,
5690 .set_wol = efx_ef10_set_wol_vf,
5691 .resume_wol = efx_port_dummy_op_void,
5692 .mcdi_request = efx_ef10_mcdi_request,
5693 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5694 .mcdi_read_response = efx_ef10_mcdi_read_response,
5695 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5696 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 5697 .irq_enable_master = efx_port_dummy_op_void,
5698 .irq_test_generate = efx_ef10_irq_test_generate,
5699 .irq_disable_non_ev = efx_port_dummy_op_void,
5700 .irq_handle_msi = efx_ef10_msi_interrupt,
5701 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5702 .tx_probe = efx_ef10_tx_probe,
5703 .tx_init = efx_ef10_tx_init,
5704 .tx_remove = efx_ef10_tx_remove,
5705 .tx_write = efx_ef10_tx_write,
e9117e50 5706 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 5707 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
a707d188 5708 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
02246a7f
SS		 5709 .rx_probe = efx_ef10_rx_probe,
5710 .rx_init = efx_ef10_rx_init,
5711 .rx_remove = efx_ef10_rx_remove,
5712 .rx_write = efx_ef10_rx_write,
5713 .rx_defer_refill = efx_ef10_rx_defer_refill,
5714 .ev_probe = efx_ef10_ev_probe,
5715 .ev_init = efx_ef10_ev_init,
5716 .ev_fini = efx_ef10_ev_fini,
5717 .ev_remove = efx_ef10_ev_remove,
5718 .ev_process = efx_ef10_ev_process,
5719 .ev_read_ack = efx_ef10_ev_read_ack,
5720 .ev_test_generate = efx_ef10_ev_test_generate,
5721 .filter_table_probe = efx_ef10_filter_table_probe,
5722 .filter_table_restore = efx_ef10_filter_table_restore,
5723 .filter_table_remove = efx_ef10_filter_table_remove,
5724 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5725 .filter_insert = efx_ef10_filter_insert,
5726 .filter_remove_safe = efx_ef10_filter_remove_safe,
5727 .filter_get_safe = efx_ef10_filter_get_safe,
5728 .filter_clear_rx = efx_ef10_filter_clear_rx,
5729 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5730 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5731 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5732#ifdef CONFIG_RFS_ACCEL
5733 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5734 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5735#endif
5736#ifdef CONFIG_SFC_MTD
5737 .mtd_probe = efx_port_dummy_op_int,
5738#endif
5739 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5740 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 5741 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5742 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 5743#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 5744 .vswitching_probe = efx_ef10_vswitching_probe_vf,
5745 .vswitching_restore = efx_ef10_vswitching_restore_vf,
5746 .vswitching_remove = efx_ef10_vswitching_remove_vf,
02246a7f 5747#endif
0d5e0fbb 5748 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 5749 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 5750
08a7b29b 5751 .get_phys_port_id = efx_ef10_get_phys_port_id,
02246a7f
SS		 5752 .revision = EFX_REV_HUNT_A0,
5753 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5754 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5755 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5756 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5757 .can_rx_scatter = true,
5758 .always_rx_scatter = true,
5759 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5760 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 5761 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f
SS		 5762 .mcdi_max_ver = 2,
5763 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5764 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5765 1 << HWTSTAMP_FILTER_ALL,
f74d1995 5766 .rx_hash_key_size = 40,
02246a7f
SS		 5767};
5768
8127d661 5769const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 5770 .is_vf = false,
02246a7f 5771 .mem_bar = EFX_MEM_BAR,
8127d661 5772 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 5773 .probe = efx_ef10_probe_pf,
8127d661
BH		 5774 .remove = efx_ef10_remove,
5775 .dimension_resources = efx_ef10_dimension_resources,
5776 .init = efx_ef10_init_nic,
5777 .fini = efx_port_dummy_op_void,
087e9025 5778 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 5779 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 5780 .reset = efx_ef10_reset,
8127d661
BH		 5781 .probe_port = efx_mcdi_port_probe,
5782 .remove_port = efx_mcdi_port_remove,
5783 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 5784 .prepare_flr = efx_ef10_prepare_flr,
5785 .finish_flr = efx_port_dummy_op_void,
8127d661 5786 .describe_stats = efx_ef10_describe_stats,
d7788196 5787 .update_stats = efx_ef10_update_stats_pf,
8127d661 5788 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 5789 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 5790 .stop_stats = efx_mcdi_mac_stop_stats,
5791 .set_id_led = efx_mcdi_set_id_led,
5792 .push_irq_moderation = efx_ef10_push_irq_moderation,
5793 .reconfigure_mac = efx_ef10_mac_reconfigure,
5794 .check_mac_fault = efx_mcdi_mac_check_fault,
5795 .reconfigure_port = efx_mcdi_port_reconfigure,
5796 .get_wol = efx_ef10_get_wol,
5797 .set_wol = efx_ef10_set_wol,
5798 .resume_wol = efx_port_dummy_op_void,
74cd60a4 5799 .test_chip = efx_ef10_test_chip,
8127d661
BH		 5800 .test_nvram = efx_mcdi_nvram_test_all,
5801 .mcdi_request = efx_ef10_mcdi_request,
5802 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5803 .mcdi_read_response = efx_ef10_mcdi_read_response,
5804 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5805 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 5806 .irq_enable_master = efx_port_dummy_op_void,
5807 .irq_test_generate = efx_ef10_irq_test_generate,
5808 .irq_disable_non_ev = efx_port_dummy_op_void,
5809 .irq_handle_msi = efx_ef10_msi_interrupt,
5810 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5811 .tx_probe = efx_ef10_tx_probe,
5812 .tx_init = efx_ef10_tx_init,
5813 .tx_remove = efx_ef10_tx_remove,
5814 .tx_write = efx_ef10_tx_write,
e9117e50 5815 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 5816 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
a707d188 5817 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
8127d661
BH		 5818 .rx_probe = efx_ef10_rx_probe,
5819 .rx_init = efx_ef10_rx_init,
5820 .rx_remove = efx_ef10_rx_remove,
5821 .rx_write = efx_ef10_rx_write,
5822 .rx_defer_refill = efx_ef10_rx_defer_refill,
5823 .ev_probe = efx_ef10_ev_probe,
5824 .ev_init = efx_ef10_ev_init,
5825 .ev_fini = efx_ef10_ev_fini,
5826 .ev_remove = efx_ef10_ev_remove,
5827 .ev_process = efx_ef10_ev_process,
5828 .ev_read_ack = efx_ef10_ev_read_ack,
5829 .ev_test_generate = efx_ef10_ev_test_generate,
5830 .filter_table_probe = efx_ef10_filter_table_probe,
5831 .filter_table_restore = efx_ef10_filter_table_restore,
5832 .filter_table_remove = efx_ef10_filter_table_remove,
5833 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5834 .filter_insert = efx_ef10_filter_insert,
5835 .filter_remove_safe = efx_ef10_filter_remove_safe,
5836 .filter_get_safe = efx_ef10_filter_get_safe,
5837 .filter_clear_rx = efx_ef10_filter_clear_rx,
5838 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5839 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5840 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5841#ifdef CONFIG_RFS_ACCEL
5842 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5843 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5844#endif
5845#ifdef CONFIG_SFC_MTD
5846 .mtd_probe = efx_ef10_mtd_probe,
5847 .mtd_rename = efx_mcdi_mtd_rename,
5848 .mtd_read = efx_mcdi_mtd_read,
5849 .mtd_erase = efx_mcdi_mtd_erase,
5850 .mtd_write = efx_mcdi_mtd_write,
5851 .mtd_sync = efx_mcdi_mtd_sync,
5852#endif
5853 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 5854 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5855 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 5856 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5857 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
7fa8d547 5858#ifdef CONFIG_SFC_SRIOV
834e23dd 5859 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 5860 .sriov_init = efx_ef10_sriov_init,
5861 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 5862 .sriov_wanted = efx_ef10_sriov_wanted,
5863 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 5864 .sriov_flr = efx_ef10_sriov_flr,
5865 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5866 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5867 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5868 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 5869 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 5870 .vswitching_probe = efx_ef10_vswitching_probe_pf,
5871 .vswitching_restore = efx_ef10_vswitching_restore_pf,
5872 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 5873#endif
0d5e0fbb 5874 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 5875 .set_mac_address = efx_ef10_set_mac_address,
46d1efd8 5876 .tso_versions = efx_ef10_tso_versions,
8127d661 5877
08a7b29b 5878 .get_phys_port_id = efx_ef10_get_phys_port_id,
8127d661
BH		 5879 .revision = EFX_REV_HUNT_A0,
5880 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5881 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5882 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 5883 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 5884 .can_rx_scatter = true,
5885 .always_rx_scatter = true,
de1deff9 5886 .option_descriptors = true,
8127d661
BH		 5887 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5888 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 5889 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661
BH		 5890 .mcdi_max_ver = 2,
5891 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 5892 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5893 1 << HWTSTAMP_FILTER_ALL,
f74d1995 5894 .rx_hash_key_size = 40,
8127d661 5895};
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