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sctp: remove useless code from sctp_apply_peer_addr_params
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
dc3273e0
AR		 53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
34813fe2
AR		 57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
dc3273e0
AR		 63/* Per-VLAN filters information */
64struct efx_ef10_filter_vlan {
34813fe2 65 struct list_head list;
b3a3c03c 66 u16 vid;
dc3273e0
AR		 67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
69 u16 ucdef;
70 u16 bcast;
71 u16 mcdef;
72};
73
822b96f8
DP		 74struct efx_ef10_dev_addr {
75 u8 addr[ETH_ALEN];
822b96f8
DP		 76};
77
8127d661 78struct efx_ef10_filter_table {
7ac0dd9d
AR		 79/* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags[
8127d661
BH		 81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
82 unsigned int rx_match_count;
83
84 struct {
85 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 86/* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 88 */
89#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 90#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 91#define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle; /* firmware handle */
93 } *entry;
94 wait_queue_head_t waitq;
95/* Shadow of net_device address lists, guarded by mac_lock */
822b96f8
DP		 96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 98 int dev_uc_count;
99 int dev_mc_count;
afa4ce12
AR		 100 bool uc_promisc;
101 bool mc_promisc;
b071c3a2
AR		 102/* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last;
4a53ea8a 104 bool vlan_filter;
34813fe2 105 struct list_head vlan_list;
8127d661
BH		 106};
107
108/* An arbitrary search limit for the software hash table */
109#define EFX_EF10_FILTER_SEARCH_LIMIT 200
110
8127d661
BH		 111static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
112static void efx_ef10_filter_table_remove(struct efx_nic *efx);
34813fe2
AR		 113static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
114static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
115 struct efx_ef10_filter_vlan *vlan);
116static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
8127d661
BH		 117
118static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
119{
120 efx_dword_t reg;
121
122 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
125}
126
127static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
128{
02246a7f
SS		 129 int bar;
130
131 bar = efx->type->mem_bar;
132 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 133}
134
7a186f47
DP		 135static bool efx_ef10_is_vf(struct efx_nic *efx)
136{
137 return efx->type->is_vf;
138}
139
1cd9ecbb
DP		 140static int efx_ef10_get_pf_index(struct efx_nic *efx)
141{
142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
143 struct efx_ef10_nic_data *nic_data = efx->nic_data;
144 size_t outlen;
145 int rc;
146
147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
148 sizeof(outbuf), &outlen);
149 if (rc)
150 return rc;
151 if (outlen < sizeof(outbuf))
152 return -EIO;
153
154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
155 return 0;
156}
157
88a37de6
SS		 158#ifdef CONFIG_SFC_SRIOV
159static int efx_ef10_get_vf_index(struct efx_nic *efx)
160{
161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
163 size_t outlen;
164 int rc;
165
166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
167 sizeof(outbuf), &outlen);
168 if (rc)
169 return rc;
170 if (outlen < sizeof(outbuf))
171 return -EIO;
172
173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
174 return 0;
175}
176#endif
177
e5a2538a 178static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 179{
ca889a05 180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
8127d661
BH		 181 struct efx_ef10_nic_data *nic_data = efx->nic_data;
182 size_t outlen;
183 int rc;
184
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
186
187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
188 outbuf, sizeof(outbuf), &outlen);
189 if (rc)
190 return rc;
ca889a05 191 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 192 netif_err(efx, drv, efx->net_dev,
193 "unable to read datapath firmware capabilities\n");
194 return -EIO;
195 }
196
197 nic_data->datapath_caps =
198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 199
ca889a05
BK		 200 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
201 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
202 GET_CAPABILITIES_V2_OUT_FLAGS2);
203 else
204 nic_data->datapath_caps2 = 0;
205
8d9f9dd4
DP		 206 /* record the DPCPU firmware IDs to determine VEB vswitching support.
207 */
208 nic_data->rx_dpcpu_fw_id =
209 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
210 nic_data->tx_dpcpu_fw_id =
211 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
212
e5a2538a
BH		 213 if (!(nic_data->datapath_caps &
214 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
215 netif_err(efx, probe, efx->net_dev,
216 "current firmware does not support an RX prefix\n");
217 return -ENODEV;
8127d661
BH		 218 }
219
220 return 0;
221}
222
223static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
224{
225 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
226 int rc;
227
228 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
229 outbuf, sizeof(outbuf), NULL);
230 if (rc)
231 return rc;
232 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
233 return rc > 0 ? rc : -ERANGE;
234}
235
d95e329a
BK		 236static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
237{
238 struct efx_ef10_nic_data *nic_data = efx->nic_data;
239 unsigned int implemented;
240 unsigned int enabled;
241 int rc;
242
243 nic_data->workaround_35388 = false;
244 nic_data->workaround_61265 = false;
245
246 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
247
248 if (rc == -ENOSYS) {
249 /* Firmware without GET_WORKAROUNDS - not a problem. */
250 rc = 0;
251 } else if (rc == 0) {
252 /* Bug61265 workaround is always enabled if implemented. */
253 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
254 nic_data->workaround_61265 = true;
255
256 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
257 nic_data->workaround_35388 = true;
258 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
259 /* Workaround is implemented but not enabled.
260 * Try to enable it.
261 */
262 rc = efx_mcdi_set_workaround(efx,
263 MC_CMD_WORKAROUND_BUG35388,
264 true, NULL);
265 if (rc == 0)
266 nic_data->workaround_35388 = true;
267 /* If we failed to set the workaround just carry on. */
268 rc = 0;
269 }
270 }
271
272 netif_dbg(efx, probe, efx->net_dev,
273 "workaround for bug 35388 is %sabled\n",
274 nic_data->workaround_35388 ? "en" : "dis");
275 netif_dbg(efx, probe, efx->net_dev,
276 "workaround for bug 61265 is %sabled\n",
277 nic_data->workaround_61265 ? "en" : "dis");
278
279 return rc;
280}
281
282static void efx_ef10_process_timer_config(struct efx_nic *efx,
283 const efx_dword_t *data)
284{
285 unsigned int max_count;
286
287 if (EFX_EF10_WORKAROUND_61265(efx)) {
288 efx->timer_quantum_ns = MCDI_DWORD(data,
289 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
290 efx->timer_max_ns = MCDI_DWORD(data,
291 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
292 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
293 efx->timer_quantum_ns = MCDI_DWORD(data,
294 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
295 max_count = MCDI_DWORD(data,
296 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
297 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
298 } else {
299 efx->timer_quantum_ns = MCDI_DWORD(data,
300 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
301 max_count = MCDI_DWORD(data,
302 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
303 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
304 }
305
306 netif_dbg(efx, probe, efx->net_dev,
307 "got timer properties from MC: quantum %u ns; max %u ns\n",
308 efx->timer_quantum_ns, efx->timer_max_ns);
309}
310
311static int efx_ef10_get_timer_config(struct efx_nic *efx)
312{
313 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
314 int rc;
315
316 rc = efx_ef10_get_timer_workarounds(efx);
317 if (rc)
318 return rc;
319
320 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
321 outbuf, sizeof(outbuf), NULL);
322
323 if (rc == 0) {
324 efx_ef10_process_timer_config(efx, outbuf);
325 } else if (rc == -ENOSYS || rc == -EPERM) {
326 /* Not available - fall back to Huntington defaults. */
327 unsigned int quantum;
328
329 rc = efx_ef10_get_sysclk_freq(efx);
330 if (rc < 0)
331 return rc;
332
333 quantum = 1536000 / rc; /* 1536 cycles */
334 efx->timer_quantum_ns = quantum;
335 efx->timer_max_ns = efx->type->timer_period_max * quantum;
336 rc = 0;
337 } else {
338 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
339 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
340 NULL, 0, rc);
341 }
342
343 return rc;
344}
345
0d5e0fbb 346static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 347{
348 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
349 size_t outlen;
350 int rc;
351
352 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
353
354 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
355 outbuf, sizeof(outbuf), &outlen);
356 if (rc)
357 return rc;
358 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
359 return -EIO;
360
cd84ff4d
EC		 361 ether_addr_copy(mac_address,
362 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 363 return 0;
364}
365
0d5e0fbb
DP		 366static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
367{
368 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
369 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
370 size_t outlen;
371 int num_addrs, rc;
372
373 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
374 EVB_PORT_ID_ASSIGNED);
375 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
376 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
377
378 if (rc)
379 return rc;
380 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
381 return -EIO;
382
383 num_addrs = MCDI_DWORD(outbuf,
384 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
385
386 WARN_ON(num_addrs != 1);
387
388 ether_addr_copy(mac_address,
389 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
390
391 return 0;
392}
393
0f5c0845
SS		 394static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
395 struct device_attribute *attr,
396 char *buf)
397{
398 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
399
400 return sprintf(buf, "%d\n",
401 ((efx->mcdi->fn_flags) &
402 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
403 ? 1 : 0);
404}
405
406static ssize_t efx_ef10_show_primary_flag(struct device *dev,
407 struct device_attribute *attr,
408 char *buf)
409{
410 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
411
412 return sprintf(buf, "%d\n",
413 ((efx->mcdi->fn_flags) &
414 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
415 ? 1 : 0);
416}
417
34813fe2
AR		 418static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
419{
420 struct efx_ef10_nic_data *nic_data = efx->nic_data;
421 struct efx_ef10_vlan *vlan;
422
423 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
424
425 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
426 if (vlan->vid == vid)
427 return vlan;
428 }
429
430 return NULL;
431}
432
433static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
434{
435 struct efx_ef10_nic_data *nic_data = efx->nic_data;
436 struct efx_ef10_vlan *vlan;
437 int rc;
438
439 mutex_lock(&nic_data->vlan_lock);
440
441 vlan = efx_ef10_find_vlan(efx, vid);
442 if (vlan) {
4a53ea8a
AR		 443 /* We add VID 0 on init. 8021q adds it on module init
444 * for all interfaces with VLAN filtring feature.
445 */
446 if (vid == 0)
447 goto done_unlock;
34813fe2
AR		 448 netif_warn(efx, drv, efx->net_dev,
449 "VLAN %u already added\n", vid);
450 rc = -EALREADY;
451 goto fail_exist;
452 }
453
454 rc = -ENOMEM;
455 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
456 if (!vlan)
457 goto fail_alloc;
458
459 vlan->vid = vid;
460
461 list_add_tail(&vlan->list, &nic_data->vlan_list);
462
463 if (efx->filter_state) {
464 mutex_lock(&efx->mac_lock);
465 down_write(&efx->filter_sem);
466 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
467 up_write(&efx->filter_sem);
468 mutex_unlock(&efx->mac_lock);
469 if (rc)
470 goto fail_filter_add_vlan;
471 }
472
4a53ea8a 473done_unlock:
34813fe2
AR		 474 mutex_unlock(&nic_data->vlan_lock);
475 return 0;
476
477fail_filter_add_vlan:
478 list_del(&vlan->list);
479 kfree(vlan);
480fail_alloc:
481fail_exist:
482 mutex_unlock(&nic_data->vlan_lock);
483 return rc;
484}
485
486static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
487 struct efx_ef10_vlan *vlan)
488{
489 struct efx_ef10_nic_data *nic_data = efx->nic_data;
490
491 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
492
493 if (efx->filter_state) {
494 down_write(&efx->filter_sem);
495 efx_ef10_filter_del_vlan(efx, vlan->vid);
496 up_write(&efx->filter_sem);
497 }
498
499 list_del(&vlan->list);
500 kfree(vlan);
501}
502
4a53ea8a
AR		 503static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
504{
505 struct efx_ef10_nic_data *nic_data = efx->nic_data;
506 struct efx_ef10_vlan *vlan;
507 int rc = 0;
508
509 /* 8021q removes VID 0 on module unload for all interfaces
510 * with VLAN filtering feature. We need to keep it to receive
511 * untagged traffic.
512 */
513 if (vid == 0)
514 return 0;
515
516 mutex_lock(&nic_data->vlan_lock);
517
518 vlan = efx_ef10_find_vlan(efx, vid);
519 if (!vlan) {
520 netif_err(efx, drv, efx->net_dev,
521 "VLAN %u to be deleted not found\n", vid);
522 rc = -ENOENT;
523 } else {
524 efx_ef10_del_vlan_internal(efx, vlan);
525 }
526
527 mutex_unlock(&nic_data->vlan_lock);
528
529 return rc;
530}
531
34813fe2
AR		 532static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
533{
534 struct efx_ef10_nic_data *nic_data = efx->nic_data;
535 struct efx_ef10_vlan *vlan, *next_vlan;
536
537 mutex_lock(&nic_data->vlan_lock);
538 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
539 efx_ef10_del_vlan_internal(efx, vlan);
540 mutex_unlock(&nic_data->vlan_lock);
541}
542
0f5c0845
SS		 543static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
544 NULL);
545static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
546
8127d661
BH		 547static int efx_ef10_probe(struct efx_nic *efx)
548{
549 struct efx_ef10_nic_data *nic_data;
550 int i, rc;
551
aa3930ee
BH		 552 /* We can have one VI for each 8K region. However, until we
553 * use TX option descriptors we need two TX queues per channel.
8127d661 554 */
b0fbdae1
SS		 555 efx->max_channels = min_t(unsigned int,
556 EFX_MAX_CHANNELS,
557 efx_ef10_mem_map_size(efx) /
558 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
559 efx->max_tx_channels = efx->max_channels;
9fd3d3a4
EC		 560 if (WARN_ON(efx->max_channels == 0))
561 return -EIO;
8127d661
BH		 562
563 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
564 if (!nic_data)
565 return -ENOMEM;
566 efx->nic_data = nic_data;
567
75aba2a5
EC		 568 /* we assume later that we can copy from this buffer in dwords */
569 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
570
8127d661
BH		 571 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
572 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
573 if (rc)
574 goto fail1;
575
576 /* Get the MC's warm boot count. In case it's rebooting right
577 * now, be prepared to retry.
578 */
579 i = 0;
580 for (;;) {
581 rc = efx_ef10_get_warm_boot_count(efx);
582 if (rc >= 0)
583 break;
584 if (++i == 5)
585 goto fail2;
586 ssleep(1);
587 }
588 nic_data->warm_boot_count = rc;
589
590 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
591
45b2449e
DP		 592 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
593
8127d661
BH		 594 /* In case we're recovering from a crash (kexec), we want to
595 * cancel any outstanding request by the previous user of this
596 * function. We send a special message using the least
597 * significant bits of the 'high' (doorbell) register.
598 */
599 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
600
601 rc = efx_mcdi_init(efx);
602 if (rc)
603 goto fail2;
604
605 /* Reset (most) configuration for this function */
606 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
607 if (rc)
608 goto fail3;
609
610 /* Enable event logging */
611 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
612 if (rc)
613 goto fail3;
614
0f5c0845
SS		 615 rc = device_create_file(&efx->pci_dev->dev,
616 &dev_attr_link_control_flag);
1cd9ecbb
DP		 617 if (rc)
618 goto fail3;
619
0f5c0845
SS		 620 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
621 if (rc)
622 goto fail4;
623
624 rc = efx_ef10_get_pf_index(efx);
625 if (rc)
626 goto fail5;
627
e5a2538a 628 rc = efx_ef10_init_datapath_caps(efx);
8127d661 629 if (rc < 0)
0f5c0845 630 goto fail5;
8127d661
BH		 631
632 efx->rx_packet_len_offset =
633 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
634
8127d661
BH		 635 rc = efx_mcdi_port_get_number(efx);
636 if (rc < 0)
0f5c0845 637 goto fail5;
8127d661
BH		 638 efx->port_num = rc;
639
0d5e0fbb 640 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 641 if (rc)
0f5c0845 642 goto fail5;
8127d661 643
d95e329a 644 rc = efx_ef10_get_timer_config(efx);
8127d661 645 if (rc < 0)
0f5c0845 646 goto fail5;
8127d661 647
8127d661 648 rc = efx_mcdi_mon_probe(efx);
267d9d73 649 if (rc && rc != -EPERM)
0f5c0845 650 goto fail5;
8127d661 651
9aecda95
BH		 652 efx_ptp_probe(efx, NULL);
653
1d051e00
SS		 654#ifdef CONFIG_SFC_SRIOV
655 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
656 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
657 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
658
659 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
660 } else
661#endif
662 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
663
34813fe2
AR		 664 INIT_LIST_HEAD(&nic_data->vlan_list);
665 mutex_init(&nic_data->vlan_lock);
666
667 /* Add unspecified VID to support VLAN filtering being disabled */
668 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
669 if (rc)
670 goto fail_add_vid_unspec;
671
4a53ea8a
AR		 672 /* If VLAN filtering is enabled, we need VID 0 to get untagged
673 * traffic. It is added automatically if 8021q module is loaded,
674 * but we can't rely on it since module may be not loaded.
675 */
676 rc = efx_ef10_add_vlan(efx, 0);
677 if (rc)
678 goto fail_add_vid_0;
679
8127d661
BH		 680 return 0;
681
4a53ea8a
AR		 682fail_add_vid_0:
683 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 684fail_add_vid_unspec:
685 mutex_destroy(&nic_data->vlan_lock);
686 efx_ptp_remove(efx);
687 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 688fail5:
689 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
690fail4:
691 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 692fail3:
693 efx_mcdi_fini(efx);
694fail2:
695 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
696fail1:
697 kfree(nic_data);
698 efx->nic_data = NULL;
699 return rc;
700}
701
702static int efx_ef10_free_vis(struct efx_nic *efx)
703{
aa09a3da 704 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 705 size_t outlen;
706 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
707 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 708
709 /* -EALREADY means nothing to free, so ignore */
710 if (rc == -EALREADY)
711 rc = 0;
1e0b8120
EC		 712 if (rc)
713 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
714 rc);
8127d661
BH		 715 return rc;
716}
717
183233be
BH		 718#ifdef EFX_USE_PIO
719
720static void efx_ef10_free_piobufs(struct efx_nic *efx)
721{
722 struct efx_ef10_nic_data *nic_data = efx->nic_data;
723 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
724 unsigned int i;
725 int rc;
726
727 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
728
729 for (i = 0; i < nic_data->n_piobufs; i++) {
730 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
731 nic_data->piobuf_handle[i]);
732 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
733 NULL, 0, NULL);
734 WARN_ON(rc);
735 }
736
737 nic_data->n_piobufs = 0;
738}
739
740static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
741{
742 struct efx_ef10_nic_data *nic_data = efx->nic_data;
743 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
744 unsigned int i;
745 size_t outlen;
746 int rc = 0;
747
748 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
749
750 for (i = 0; i < n; i++) {
09a04204
BK		 751 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
752 outbuf, sizeof(outbuf), &outlen);
753 if (rc) {
754 /* Don't display the MC error if we didn't have space
755 * for a VF.
756 */
757 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
758 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
759 0, outbuf, outlen, rc);
183233be 760 break;
09a04204 761 }
183233be
BH		 762 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
763 rc = -EIO;
764 break;
765 }
766 nic_data->piobuf_handle[i] =
767 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
768 netif_dbg(efx, probe, efx->net_dev,
769 "allocated PIO buffer %u handle %x\n", i,
770 nic_data->piobuf_handle[i]);
771 }
772
773 nic_data->n_piobufs = i;
774 if (rc)
775 efx_ef10_free_piobufs(efx);
776 return rc;
777}
778
779static int efx_ef10_link_piobufs(struct efx_nic *efx)
780{
781 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 782 _MCDI_DECLARE_BUF(inbuf,
783 max(MC_CMD_LINK_PIOBUF_IN_LEN,
784 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 785 struct efx_channel *channel;
786 struct efx_tx_queue *tx_queue;
787 unsigned int offset, index;
788 int rc;
789
790 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
791 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
792
aa09a3da
JC		 793 memset(inbuf, 0, sizeof(inbuf));
794
183233be
BH		 795 /* Link a buffer to each VI in the write-combining mapping */
796 for (index = 0; index < nic_data->n_piobufs; ++index) {
797 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
798 nic_data->piobuf_handle[index]);
799 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
800 nic_data->pio_write_vi_base + index);
801 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
802 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
803 NULL, 0, NULL);
804 if (rc) {
805 netif_err(efx, drv, efx->net_dev,
806 "failed to link VI %u to PIO buffer %u (%d)\n",
807 nic_data->pio_write_vi_base + index, index,
808 rc);
809 goto fail;
810 }
811 netif_dbg(efx, probe, efx->net_dev,
812 "linked VI %u to PIO buffer %u\n",
813 nic_data->pio_write_vi_base + index, index);
814 }
815
816 /* Link a buffer to each TX queue */
817 efx_for_each_channel(channel, efx) {
818 efx_for_each_channel_tx_queue(tx_queue, channel) {
819 /* We assign the PIO buffers to queues in
820 * reverse order to allow for the following
821 * special case.
822 */
823 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
824 tx_queue->channel->channel - 1) *
825 efx_piobuf_size);
826 index = offset / ER_DZ_TX_PIOBUF_SIZE;
827 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
828
829 /* When the host page size is 4K, the first
830 * host page in the WC mapping may be within
831 * the same VI page as the last TX queue. We
832 * can only link one buffer to each VI.
833 */
834 if (tx_queue->queue == nic_data->pio_write_vi_base) {
835 BUG_ON(index != 0);
836 rc = 0;
837 } else {
838 MCDI_SET_DWORD(inbuf,
839 LINK_PIOBUF_IN_PIOBUF_HANDLE,
840 nic_data->piobuf_handle[index]);
841 MCDI_SET_DWORD(inbuf,
842 LINK_PIOBUF_IN_TXQ_INSTANCE,
843 tx_queue->queue);
844 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
845 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
846 NULL, 0, NULL);
847 }
848
849 if (rc) {
850 /* This is non-fatal; the TX path just
851 * won't use PIO for this queue
852 */
853 netif_err(efx, drv, efx->net_dev,
854 "failed to link VI %u to PIO buffer %u (%d)\n",
855 tx_queue->queue, index, rc);
856 tx_queue->piobuf = NULL;
857 } else {
858 tx_queue->piobuf =
859 nic_data->pio_write_base +
860 index * EFX_VI_PAGE_SIZE + offset;
861 tx_queue->piobuf_offset = offset;
862 netif_dbg(efx, probe, efx->net_dev,
863 "linked VI %u to PIO buffer %u offset %x addr %p\n",
864 tx_queue->queue, index,
865 tx_queue->piobuf_offset,
866 tx_queue->piobuf);
867 }
868 }
869 }
870
871 return 0;
872
873fail:
874 while (index--) {
875 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
876 nic_data->pio_write_vi_base + index);
877 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
878 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
879 NULL, 0, NULL);
880 }
881 return rc;
882}
883
c0795bf6
EC		 884static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
885{
886 struct efx_channel *channel;
887 struct efx_tx_queue *tx_queue;
888
889 /* All our existing PIO buffers went away */
890 efx_for_each_channel(channel, efx)
891 efx_for_each_channel_tx_queue(tx_queue, channel)
892 tx_queue->piobuf = NULL;
893}
894
183233be
BH		 895#else /* !EFX_USE_PIO */
896
897static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
898{
899 return n == 0 ? 0 : -ENOBUFS;
900}
901
902static int efx_ef10_link_piobufs(struct efx_nic *efx)
903{
904 return 0;
905}
906
907static void efx_ef10_free_piobufs(struct efx_nic *efx)
908{
909}
910
c0795bf6
EC		 911static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
912{
913}
914
183233be
BH		 915#endif /* EFX_USE_PIO */
916
8127d661
BH		 917static void efx_ef10_remove(struct efx_nic *efx)
918{
919 struct efx_ef10_nic_data *nic_data = efx->nic_data;
920 int rc;
921
f1122a34
SS		 922#ifdef CONFIG_SFC_SRIOV
923 struct efx_ef10_nic_data *nic_data_pf;
924 struct pci_dev *pci_dev_pf;
925 struct efx_nic *efx_pf;
926 struct ef10_vf *vf;
927
928 if (efx->pci_dev->is_virtfn) {
929 pci_dev_pf = efx->pci_dev->physfn;
930 if (pci_dev_pf) {
931 efx_pf = pci_get_drvdata(pci_dev_pf);
932 nic_data_pf = efx_pf->nic_data;
933 vf = nic_data_pf->vf + nic_data->vf_index;
934 vf->efx = NULL;
935 } else
936 netif_info(efx, drv, efx->net_dev,
937 "Could not get the PF id from VF\n");
938 }
939#endif
940
34813fe2
AR		 941 efx_ef10_cleanup_vlans(efx);
942 mutex_destroy(&nic_data->vlan_lock);
943
9aecda95
BH		 944 efx_ptp_remove(efx);
945
8127d661
BH		 946 efx_mcdi_mon_remove(efx);
947
8127d661
BH		 948 efx_ef10_rx_free_indir_table(efx);
949
183233be
BH		 950 if (nic_data->wc_membase)
951 iounmap(nic_data->wc_membase);
952
8127d661
BH		 953 rc = efx_ef10_free_vis(efx);
954 WARN_ON(rc != 0);
955
183233be
BH		 956 if (!nic_data->must_restore_piobufs)
957 efx_ef10_free_piobufs(efx);
958
0f5c0845
SS		 959 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
960 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
961
8127d661
BH		 962 efx_mcdi_fini(efx);
963 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
964 kfree(nic_data);
965}
966
88a37de6
SS		 967static int efx_ef10_probe_pf(struct efx_nic *efx)
968{
969 return efx_ef10_probe(efx);
970}
971
38d27f38
AR		 972int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
973 u32 *port_flags, u32 *vadaptor_flags,
974 unsigned int *vlan_tags)
975{
976 struct efx_ef10_nic_data *nic_data = efx->nic_data;
977 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
978 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
979 size_t outlen;
980 int rc;
981
982 if (nic_data->datapath_caps &
983 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
984 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
985 port_id);
986
987 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
988 outbuf, sizeof(outbuf), &outlen);
989 if (rc)
990 return rc;
991
992 if (outlen < sizeof(outbuf)) {
993 rc = -EIO;
994 return rc;
995 }
996 }
997
998 if (port_flags)
999 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1000 if (vadaptor_flags)
1001 *vadaptor_flags =
1002 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1003 if (vlan_tags)
1004 *vlan_tags =
1005 MCDI_DWORD(outbuf,
1006 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1007
1008 return 0;
1009}
1010
7a186f47
DP		 1011int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1012{
1013 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1014
1015 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1016 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1017 NULL, 0, NULL);
1018}
1019
1020int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1021{
1022 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1023
1024 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1025 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1026 NULL, 0, NULL);
1027}
1028
1029int efx_ef10_vport_add_mac(struct efx_nic *efx,
1030 unsigned int port_id, u8 *mac)
1031{
1032 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1033
1034 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1035 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1036
1037 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1038 sizeof(inbuf), NULL, 0, NULL);
1039}
1040
1041int efx_ef10_vport_del_mac(struct efx_nic *efx,
1042 unsigned int port_id, u8 *mac)
1043{
1044 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1045
1046 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1047 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1048
1049 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1050 sizeof(inbuf), NULL, 0, NULL);
1051}
1052
88a37de6
SS		 1053#ifdef CONFIG_SFC_SRIOV
1054static int efx_ef10_probe_vf(struct efx_nic *efx)
1055{
1056 int rc;
6598dad2
DP		 1057 struct pci_dev *pci_dev_pf;
1058
1059 /* If the parent PF has no VF data structure, it doesn't know about this
1060 * VF so fail probe. The VF needs to be re-created. This can happen
1061 * if the PF driver is unloaded while the VF is assigned to a guest.
1062 */
1063 pci_dev_pf = efx->pci_dev->physfn;
1064 if (pci_dev_pf) {
1065 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1066 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1067
1068 if (!nic_data_pf->vf) {
1069 netif_info(efx, drv, efx->net_dev,
1070 "The VF cannot link to its parent PF; "
1071 "please destroy and re-create the VF\n");
1072 return -EBUSY;
1073 }
1074 }
88a37de6
SS		 1075
1076 rc = efx_ef10_probe(efx);
1077 if (rc)
1078 return rc;
1079
1080 rc = efx_ef10_get_vf_index(efx);
1081 if (rc)
1082 goto fail;
1083
f1122a34
SS		 1084 if (efx->pci_dev->is_virtfn) {
1085 if (efx->pci_dev->physfn) {
1086 struct efx_nic *efx_pf =
1087 pci_get_drvdata(efx->pci_dev->physfn);
1088 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1089 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1090
1091 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1092 nic_data_p->vf[nic_data->vf_index].pci_dev =
1093 efx->pci_dev;
f1122a34
SS		 1094 } else
1095 netif_info(efx, drv, efx->net_dev,
1096 "Could not get the PF id from VF\n");
1097 }
1098
88a37de6
SS		 1099 return 0;
1100
1101fail:
1102 efx_ef10_remove(efx);
1103 return rc;
1104}
1105#else
1106static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1107{
1108 return 0;
1109}
1110#endif
1111
8127d661
BH		 1112static int efx_ef10_alloc_vis(struct efx_nic *efx,
1113 unsigned int min_vis, unsigned int max_vis)
1114{
1115 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1116 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1117 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1118 size_t outlen;
1119 int rc;
1120
1121 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1122 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1123 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1124 outbuf, sizeof(outbuf), &outlen);
1125 if (rc != 0)
1126 return rc;
1127
1128 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1129 return -EIO;
1130
1131 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1132 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1133
1134 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1135 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1136 return 0;
1137}
1138
183233be
BH		 1139/* Note that the failure path of this function does not free
1140 * resources, as this will be done by efx_ef10_remove().
1141 */
8127d661
BH		 1142static int efx_ef10_dimension_resources(struct efx_nic *efx)
1143{
183233be
BH		 1144 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1145 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 1146 unsigned int min_vis = max(EFX_TXQ_TYPES,
1147 efx_separate_tx_channels ? 2 : 1);
1148 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1149 void __iomem *membase;
1150 int rc;
1151
b0fbdae1 1152 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 1153
183233be
BH		 1154#ifdef EFX_USE_PIO
1155 /* Try to allocate PIO buffers if wanted and if the full
1156 * number of PIO buffers would be sufficient to allocate one
1157 * copy-buffer per TX channel. Failure is non-fatal, as there
1158 * are only a small number of PIO buffers shared between all
1159 * functions of the controller.
1160 */
1161 if (efx_piobuf_size != 0 &&
1162 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1163 efx->n_tx_channels) {
1164 unsigned int n_piobufs =
1165 DIV_ROUND_UP(efx->n_tx_channels,
1166 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
1167
1168 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1169 if (rc)
1170 netif_err(efx, probe, efx->net_dev,
1171 "failed to allocate PIO buffers (%d)\n", rc);
1172 else
1173 netif_dbg(efx, probe, efx->net_dev,
1174 "allocated %u PIO buffers\n", n_piobufs);
1175 }
1176#else
1177 nic_data->n_piobufs = 0;
1178#endif
1179
1180 /* PIO buffers should be mapped with write-combining enabled,
1181 * and we want to make single UC and WC mappings rather than
1182 * several of each (in fact that's the only option if host
1183 * page size is >4K). So we may allocate some extra VIs just
1184 * for writing PIO buffers through.
52ad762b 1185 *
b0fbdae1 1186 * The UC mapping contains (channel_vis - 1) complete VIs and the
52ad762b
DP		 1187 * first half of the next VI. Then the WC mapping begins with
1188 * the second half of this last VI.
183233be 1189 */
b0fbdae1 1190 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
183233be
BH		 1191 ER_DZ_TX_PIOBUF);
1192 if (nic_data->n_piobufs) {
52ad762b
DP		 1193 /* pio_write_vi_base rounds down to give the number of complete
1194 * VIs inside the UC mapping.
1195 */
183233be
BH		 1196 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1197 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1198 nic_data->n_piobufs) *
1199 EFX_VI_PAGE_SIZE) -
1200 uc_mem_map_size);
1201 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1202 } else {
1203 pio_write_vi_base = 0;
1204 wc_mem_map_size = 0;
b0fbdae1 1205 max_vis = channel_vis;
183233be
BH		 1206 }
1207
1208 /* In case the last attached driver failed to free VIs, do it now */
1209 rc = efx_ef10_free_vis(efx);
1210 if (rc != 0)
1211 return rc;
1212
1213 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1214 if (rc != 0)
1215 return rc;
1216
b0fbdae1
SS		 1217 if (nic_data->n_allocated_vis < channel_vis) {
1218 netif_info(efx, drv, efx->net_dev,
1219 "Could not allocate enough VIs to satisfy RSS"
1220 " requirements. Performance may not be optimal.\n");
1221 /* We didn't get the VIs to populate our channels.
1222 * We could keep what we got but then we'd have more
1223 * interrupts than we need.
1224 * Instead calculate new max_channels and restart
1225 */
1226 efx->max_channels = nic_data->n_allocated_vis;
1227 efx->max_tx_channels =
1228 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1229
1230 efx_ef10_free_vis(efx);
1231 return -EAGAIN;
1232 }
1233
183233be
BH		 1234 /* If we didn't get enough VIs to map all the PIO buffers, free the
1235 * PIO buffers
1236 */
1237 if (nic_data->n_piobufs &&
1238 nic_data->n_allocated_vis <
1239 pio_write_vi_base + nic_data->n_piobufs) {
1240 netif_dbg(efx, probe, efx->net_dev,
1241 "%u VIs are not sufficient to map %u PIO buffers\n",
1242 nic_data->n_allocated_vis, nic_data->n_piobufs);
1243 efx_ef10_free_piobufs(efx);
1244 }
1245
1246 /* Shrink the original UC mapping of the memory BAR */
1247 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1248 if (!membase) {
1249 netif_err(efx, probe, efx->net_dev,
1250 "could not shrink memory BAR to %x\n",
1251 uc_mem_map_size);
1252 return -ENOMEM;
1253 }
1254 iounmap(efx->membase);
1255 efx->membase = membase;
1256
1257 /* Set up the WC mapping if needed */
1258 if (wc_mem_map_size) {
1259 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1260 uc_mem_map_size,
1261 wc_mem_map_size);
1262 if (!nic_data->wc_membase) {
1263 netif_err(efx, probe, efx->net_dev,
1264 "could not allocate WC mapping of size %x\n",
1265 wc_mem_map_size);
1266 return -ENOMEM;
1267 }
1268 nic_data->pio_write_vi_base = pio_write_vi_base;
1269 nic_data->pio_write_base =
1270 nic_data->wc_membase +
1271 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1272 uc_mem_map_size);
1273
1274 rc = efx_ef10_link_piobufs(efx);
1275 if (rc)
1276 efx_ef10_free_piobufs(efx);
1277 }
1278
1279 netif_dbg(efx, probe, efx->net_dev,
1280 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1281 &efx->membase_phys, efx->membase, uc_mem_map_size,
1282 nic_data->wc_membase, wc_mem_map_size);
1283
1284 return 0;
8127d661
BH		 1285}
1286
1287static int efx_ef10_init_nic(struct efx_nic *efx)
1288{
1289 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1290 int rc;
1291
a915ccc9
BH		 1292 if (nic_data->must_check_datapath_caps) {
1293 rc = efx_ef10_init_datapath_caps(efx);
1294 if (rc)
1295 return rc;
1296 nic_data->must_check_datapath_caps = false;
1297 }
1298
8127d661
BH		 1299 if (nic_data->must_realloc_vis) {
1300 /* We cannot let the number of VIs change now */
1301 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1302 nic_data->n_allocated_vis);
1303 if (rc)
1304 return rc;
1305 nic_data->must_realloc_vis = false;
1306 }
1307
183233be
BH		 1308 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1309 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1310 if (rc == 0) {
1311 rc = efx_ef10_link_piobufs(efx);
1312 if (rc)
1313 efx_ef10_free_piobufs(efx);
1314 }
1315
1316 /* Log an error on failure, but this is non-fatal */
1317 if (rc)
1318 netif_err(efx, drv, efx->net_dev,
1319 "failed to restore PIO buffers (%d)\n", rc);
1320 nic_data->must_restore_piobufs = false;
1321 }
1322
267c0157 1323 /* don't fail init if RSS setup doesn't work */
4fdda958
EC		 1324 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1325 efx->rss_active = (rc == 0);
267c0157 1326
8127d661
BH		 1327 return 0;
1328}
1329
3e336261
JC		 1330static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1331{
1332 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1333#ifdef CONFIG_SFC_SRIOV
1334 unsigned int i;
1335#endif
3e336261
JC		 1336
1337 /* All our allocations have been reset */
1338 nic_data->must_realloc_vis = true;
1339 nic_data->must_restore_filters = true;
1340 nic_data->must_restore_piobufs = true;
c0795bf6 1341 efx_ef10_forget_old_piobufs(efx);
3e336261 1342 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1343
1344 /* Driver-created vswitches and vports must be re-created */
1345 nic_data->must_probe_vswitching = true;
1346 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1347#ifdef CONFIG_SFC_SRIOV
1348 if (nic_data->vf)
1349 for (i = 0; i < efx->vf_count; i++)
1350 nic_data->vf[i].vport_id = 0;
1351#endif
3e336261
JC		 1352}
1353
087e9025
JC		 1354static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1355{
1356 if (reason == RESET_TYPE_MC_FAILURE)
1357 return RESET_TYPE_DATAPATH;
1358
1359 return efx_mcdi_map_reset_reason(reason);
1360}
1361
8127d661
BH		 1362static int efx_ef10_map_reset_flags(u32 *flags)
1363{
1364 enum {
1365 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1366 ETH_RESET_SHARED_SHIFT),
1367 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1368 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1369 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1370 ETH_RESET_SHARED_SHIFT)
1371 };
1372
1373 /* We assume for now that our PCI function is permitted to
1374 * reset everything.
1375 */
1376
1377 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1378 *flags &= ~EF10_RESET_MC;
1379 return RESET_TYPE_WORLD;
1380 }
1381
1382 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1383 *flags &= ~EF10_RESET_PORT;
1384 return RESET_TYPE_ALL;
1385 }
1386
1387 /* no invisible reset implemented */
1388
1389 return -EINVAL;
1390}
1391
3e336261
JC		 1392static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1393{
1394 int rc = efx_mcdi_reset(efx, reset_type);
1395
27324820
DP		 1396 /* Unprivileged functions return -EPERM, but need to return success
1397 * here so that the datapath is brought back up.
1398 */
1399 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1400 rc = 0;
1401
3e336261
JC		 1402 /* If it was a port reset, trigger reallocation of MC resources.
1403 * Note that on an MC reset nothing needs to be done now because we'll
1404 * detect the MC reset later and handle it then.
e283546c
EC		 1405 * For an FLR, we never get an MC reset event, but the MC has reset all
1406 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1407 */
e283546c
EC		 1408 if ((reset_type == RESET_TYPE_ALL ||
1409 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1410 efx_ef10_reset_mc_allocations(efx);
1411 return rc;
1412}
1413
8127d661
BH		 1414#define EF10_DMA_STAT(ext_name, mcdi_name) \
1415 [EF10_STAT_ ## ext_name] = \
1416 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1417#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1418 [EF10_STAT_ ## int_name] = \
1419 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1420#define EF10_OTHER_STAT(ext_name) \
1421 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1422#define GENERIC_SW_STAT(ext_name) \
1423 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1424
1425static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1426 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1427 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1428 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1429 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1430 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1431 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1432 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1433 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1434 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1435 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1436 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1437 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1438 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1439 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1440 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1441 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1442 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1443 EF10_OTHER_STAT(port_rx_good_bytes),
1444 EF10_OTHER_STAT(port_rx_bad_bytes),
1445 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1446 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1447 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1448 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1449 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1450 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1451 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1452 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1453 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1454 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1455 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1456 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1457 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1458 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1459 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1460 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1461 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1462 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1463 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1464 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1465 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1466 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1467 GENERIC_SW_STAT(rx_nodesc_trunc),
1468 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1469 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1470 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1471 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1472 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1473 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1474 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1475 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1476 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1477 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1478 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1479 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1480 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1481 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1482 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1483 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1484 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1485 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1486 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1487 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1488 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1489 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1490 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1491 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1492 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1493 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1494 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1495 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1496 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1497 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1498 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1499};
1500
e80ca013
DP		 1501#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1502 (1ULL << EF10_STAT_port_tx_packets) | \
1503 (1ULL << EF10_STAT_port_tx_pause) | \
1504 (1ULL << EF10_STAT_port_tx_unicast) | \
1505 (1ULL << EF10_STAT_port_tx_multicast) | \
1506 (1ULL << EF10_STAT_port_tx_broadcast) | \
1507 (1ULL << EF10_STAT_port_rx_bytes) | \
1508 (1ULL << \
1509 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1510 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1511 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1512 (1ULL << EF10_STAT_port_rx_packets) | \
1513 (1ULL << EF10_STAT_port_rx_good) | \
1514 (1ULL << EF10_STAT_port_rx_bad) | \
1515 (1ULL << EF10_STAT_port_rx_pause) | \
1516 (1ULL << EF10_STAT_port_rx_control) | \
1517 (1ULL << EF10_STAT_port_rx_unicast) | \
1518 (1ULL << EF10_STAT_port_rx_multicast) | \
1519 (1ULL << EF10_STAT_port_rx_broadcast) | \
1520 (1ULL << EF10_STAT_port_rx_lt64) | \
1521 (1ULL << EF10_STAT_port_rx_64) | \
1522 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1523 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1524 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1525 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1526 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1527 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1528 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1529 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1530 (1ULL << EF10_STAT_port_rx_overflow) | \
1531 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1532 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1533 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661 1534
69b365c3
EC		 1535/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1536 * For a 10G/40G switchable port we do not expose these because they might
1537 * not include all the packets they should.
1538 * On 8000 series NICs these statistics are always provided.
8127d661 1539 */
e80ca013
DP		 1540#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1541 (1ULL << EF10_STAT_port_tx_lt64) | \
1542 (1ULL << EF10_STAT_port_tx_64) | \
1543 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1544 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1545 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1546 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1547 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1548 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1549
1550/* These statistics are only provided by the 40G MAC. For a 10G/40G
1551 * switchable port we do expose these because the errors will otherwise
1552 * be silent.
1553 */
e80ca013
DP		 1554#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1555 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1556
568d7a00
EC		 1557/* These statistics are only provided if the firmware supports the
1558 * capability PM_AND_RXDP_COUNTERS.
1559 */
1560#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1561 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1562 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1563 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1564 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1565 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1566 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1567 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1568 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1569 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1570 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1571 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1572 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1573
4bae913b 1574static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1575{
4bae913b 1576 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1577 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1578 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1579
3c36a2ad
DP		 1580 if (!(efx->mcdi->fn_flags &
1581 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1582 return 0;
1583
69b365c3 1584 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
4bae913b 1585 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
69b365c3
EC		 1586 /* 8000 series have everything even at 40G */
1587 if (nic_data->datapath_caps2 &
1588 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1589 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1590 } else {
4bae913b 1591 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
69b365c3 1592 }
568d7a00
EC		 1593
1594 if (nic_data->datapath_caps &
1595 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1596 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1597
4bae913b
EC		 1598 return raw_mask;
1599}
1600
1601static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1602{
d94619cd 1603 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1604 u64 raw_mask[2];
1605
1606 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1607
d94619cd
DP		 1608 /* Only show vadaptor stats when EVB capability is present */
1609 if (nic_data->datapath_caps &
1610 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1611 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1612 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1613 } else {
1614 raw_mask[1] = 0;
1615 }
4bae913b
EC		 1616
1617#if BITS_PER_LONG == 64
e70c70c3 1618 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
3c36a2ad
DP		 1619 mask[0] = raw_mask[0];
1620 mask[1] = raw_mask[1];
4bae913b 1621#else
e70c70c3 1622 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
3c36a2ad
DP		 1623 mask[0] = raw_mask[0] & 0xffffffff;
1624 mask[1] = raw_mask[0] >> 32;
1625 mask[2] = raw_mask[1] & 0xffffffff;
4bae913b 1626#endif
8127d661
BH		 1627}
1628
1629static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1630{
4bae913b
EC		 1631 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1632
1633 efx_ef10_get_stat_mask(efx, mask);
8127d661 1634 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1635 mask, names);
8127d661
BH		 1636}
1637
d7788196
DP		 1638static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1639 struct rtnl_link_stats64 *core_stats)
1640{
1641 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1642 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1643 u64 *stats = nic_data->stats;
1644 size_t stats_count = 0, index;
1645
1646 efx_ef10_get_stat_mask(efx, mask);
1647
1648 if (full_stats) {
1649 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1650 if (efx_ef10_stat_desc[index].name) {
1651 *full_stats++ = stats[index];
1652 ++stats_count;
1653 }
1654 }
1655 }
1656
fbe4307e
BK		 1657 if (!core_stats)
1658 return stats_count;
1659
1660 if (nic_data->datapath_caps &
1661 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1662 /* Use vadaptor stats. */
0fc95fca
DP		 1663 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1664 stats[EF10_STAT_rx_multicast] +
1665 stats[EF10_STAT_rx_broadcast];
1666 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1667 stats[EF10_STAT_tx_multicast] +
1668 stats[EF10_STAT_tx_broadcast];
1669 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1670 stats[EF10_STAT_rx_multicast_bytes] +
1671 stats[EF10_STAT_rx_broadcast_bytes];
1672 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1673 stats[EF10_STAT_tx_multicast_bytes] +
1674 stats[EF10_STAT_tx_broadcast_bytes];
1675 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1676 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1677 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1678 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1679 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1680 core_stats->rx_errors = core_stats->rx_crc_errors;
1681 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1682 } else {
1683 /* Use port stats. */
1684 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1685 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1686 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1687 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1688 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1689 stats[GENERIC_STAT_rx_nodesc_trunc] +
1690 stats[GENERIC_STAT_rx_noskb_drops];
1691 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1692 core_stats->rx_length_errors =
1693 stats[EF10_STAT_port_rx_gtjumbo] +
1694 stats[EF10_STAT_port_rx_length_error];
1695 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1696 core_stats->rx_frame_errors =
1697 stats[EF10_STAT_port_rx_align_error];
1698 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1699 core_stats->rx_errors = (core_stats->rx_length_errors +
1700 core_stats->rx_crc_errors +
1701 core_stats->rx_frame_errors);
d7788196
DP		 1702 }
1703
1704 return stats_count;
1705}
1706
1707static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1708{
1709 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1710 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1711 __le64 generation_start, generation_end;
1712 u64 *stats = nic_data->stats;
1713 __le64 *dma_stats;
1714
4bae913b
EC		 1715 efx_ef10_get_stat_mask(efx, mask);
1716
8127d661 1717 dma_stats = efx->stats_buffer.addr;
8127d661
BH		 1718
1719 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1720 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1721 return 0;
1722 rmb();
4bae913b 1723 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1724 stats, efx->stats_buffer.addr, false);
d546a893 1725 rmb();
8127d661
BH		 1726 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1727 if (generation_end != generation_start)
1728 return -EAGAIN;
1729
1730 /* Update derived statistics */
e80ca013
DP		 1731 efx_nic_fix_nodesc_drop_stat(efx,
1732 &stats[EF10_STAT_port_rx_nodesc_drops]);
1733 stats[EF10_STAT_port_rx_good_bytes] =
1734 stats[EF10_STAT_port_rx_bytes] -
1735 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1736 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1737 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1738 efx_update_sw_stats(efx, stats);
8127d661
BH		 1739 return 0;
1740}
1741
1742
d7788196
DP		 1743static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1744 struct rtnl_link_stats64 *core_stats)
8127d661 1745{
8127d661
BH		 1746 int retry;
1747
1748 /* If we're unlucky enough to read statistics during the DMA, wait
1749 * up to 10ms for it to finish (typically takes <500us)
1750 */
1751 for (retry = 0; retry < 100; ++retry) {
d7788196 1752 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1753 break;
1754 udelay(100);
1755 }
1756
d7788196
DP		 1757 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1758}
8127d661 1759
d7788196
DP		 1760static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1761{
1762 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1763 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1764 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1765 __le64 generation_start, generation_end;
1766 u64 *stats = nic_data->stats;
1767 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1768 struct efx_buffer stats_buf;
1769 __le64 *dma_stats;
1770 int rc;
1771
f00bf230
DP		 1772 spin_unlock_bh(&efx->stats_lock);
1773
1774 if (in_interrupt()) {
1775 /* If in atomic context, cannot update stats. Just update the
1776 * software stats and return so the caller can continue.
1777 */
1778 spin_lock_bh(&efx->stats_lock);
1779 efx_update_sw_stats(efx, stats);
1780 return 0;
1781 }
1782
d7788196
DP		 1783 efx_ef10_get_stat_mask(efx, mask);
1784
1785 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1786 if (rc) {
1787 spin_lock_bh(&efx->stats_lock);
d7788196 1788 return rc;
f00bf230 1789 }
d7788196
DP		 1790
1791 dma_stats = stats_buf.addr;
1792 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1793
1794 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1795 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1796 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1797 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1798 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1799
6dd4859b
DP		 1800 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1801 NULL, 0, NULL);
d7788196 1802 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1803 if (rc) {
1804 /* Expect ENOENT if DMA queues have not been set up */
1805 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1806 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1807 sizeof(inbuf), NULL, 0, rc);
d7788196 1808 goto out;
6dd4859b 1809 }
d7788196
DP		 1810
1811 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1812 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1813 WARN_ON_ONCE(1);
d7788196 1814 goto out;
0fc95fca 1815 }
d7788196
DP		 1816 rmb();
1817 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1818 stats, stats_buf.addr, false);
1819 rmb();
1820 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1821 if (generation_end != generation_start) {
1822 rc = -EAGAIN;
1823 goto out;
8127d661
BH		 1824 }
1825
d7788196
DP		 1826 efx_update_sw_stats(efx, stats);
1827out:
1828 efx_nic_free_buffer(efx, &stats_buf);
1829 return rc;
1830}
1831
1832static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1833 struct rtnl_link_stats64 *core_stats)
1834{
1835 if (efx_ef10_try_update_nic_stats_vf(efx))
1836 return 0;
1837
1838 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1839}
1840
1841static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1842{
1843 struct efx_nic *efx = channel->efx;
539de7c5 1844 unsigned int mode, usecs;
8127d661
BH		 1845 efx_dword_t timer_cmd;
1846
539de7c5 1847 if (channel->irq_moderation_us) {
8127d661 1848 mode = 3;
539de7c5 1849 usecs = channel->irq_moderation_us;
8127d661
BH		 1850 } else {
1851 mode = 0;
539de7c5 1852 usecs = 0;
8127d661
BH		 1853 }
1854
539de7c5
BK		 1855 if (EFX_EF10_WORKAROUND_61265(efx)) {
1856 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1857 unsigned int ns = usecs * 1000;
1858
1859 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1860 channel->channel);
1861 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1862 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1863 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1864
1865 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1866 inbuf, sizeof(inbuf), 0, NULL, 0);
1867 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1868 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1869
8127d661
BH		 1870 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1871 EFE_DD_EVQ_IND_TIMER_FLAGS,
1872 ERF_DD_EVQ_IND_TIMER_MODE, mode,
539de7c5 1873 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
8127d661
BH		 1874 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1875 channel->channel);
1876 } else {
539de7c5
BK		 1877 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1878
8127d661 1879 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
539de7c5 1880 ERF_DZ_TC_TIMER_VAL, ticks);
8127d661
BH		 1881 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1882 channel->channel);
1883 }
1884}
1885
02246a7f
SS		 1886static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1887 struct ethtool_wolinfo *wol) {}
1888
1889static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1890{
1891 return -EOPNOTSUPP;
1892}
1893
8127d661
BH		 1894static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1895{
1896 wol->supported = 0;
1897 wol->wolopts = 0;
1898 memset(&wol->sopass, 0, sizeof(wol->sopass));
1899}
1900
1901static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1902{
1903 if (type != 0)
1904 return -EINVAL;
1905 return 0;
1906}
1907
1908static void efx_ef10_mcdi_request(struct efx_nic *efx,
1909 const efx_dword_t *hdr, size_t hdr_len,
1910 const efx_dword_t *sdu, size_t sdu_len)
1911{
1912 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1913 u8 *pdu = nic_data->mcdi_buf.addr;
1914
1915 memcpy(pdu, hdr, hdr_len);
1916 memcpy(pdu + hdr_len, sdu, sdu_len);
1917 wmb();
1918
1919 /* The hardware provides 'low' and 'high' (doorbell) registers
1920 * for passing the 64-bit address of an MCDI request to
1921 * firmware. However the dwords are swapped by firmware. The
1922 * least significant bits of the doorbell are then 0 for all
1923 * MCDI requests due to alignment.
1924 */
1925 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1926 ER_DZ_MC_DB_LWRD);
1927 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1928 ER_DZ_MC_DB_HWRD);
1929}
1930
1931static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1932{
1933 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1934 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1935
1936 rmb();
1937 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1938}
1939
1940static void
1941efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1942 size_t offset, size_t outlen)
1943{
1944 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1945 const u8 *pdu = nic_data->mcdi_buf.addr;
1946
1947 memcpy(outbuf, pdu + offset, outlen);
1948}
1949
c577e59e
DP		 1950static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1951{
1952 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1953
1954 /* All our allocations have been reset */
1955 efx_ef10_reset_mc_allocations(efx);
1956
1957 /* The datapath firmware might have been changed */
1958 nic_data->must_check_datapath_caps = true;
1959
1960 /* MAC statistics have been cleared on the NIC; clear the local
1961 * statistic that we update with efx_update_diff_stat().
1962 */
1963 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1964}
1965
8127d661
BH		 1966static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1967{
1968 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1969 int rc;
1970
1971 rc = efx_ef10_get_warm_boot_count(efx);
1972 if (rc < 0) {
1973 /* The firmware is presumably in the process of
1974 * rebooting. However, we are supposed to report each
1975 * reboot just once, so we must only do that once we
1976 * can read and store the updated warm boot count.
1977 */
1978 return 0;
1979 }
1980
1981 if (rc == nic_data->warm_boot_count)
1982 return 0;
1983
1984 nic_data->warm_boot_count = rc;
c577e59e 1985 efx_ef10_mcdi_reboot_detected(efx);
869070c5 1986
8127d661
BH		 1987 return -EIO;
1988}
1989
1990/* Handle an MSI interrupt
1991 *
1992 * Handle an MSI hardware interrupt. This routine schedules event
1993 * queue processing. No interrupt acknowledgement cycle is necessary.
1994 * Also, we never need to check that the interrupt is for us, since
1995 * MSI interrupts cannot be shared.
1996 */
1997static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1998{
1999 struct efx_msi_context *context = dev_id;
2000 struct efx_nic *efx = context->efx;
2001
2002 netif_vdbg(efx, intr, efx->net_dev,
2003 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2004
2005 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2006 /* Note test interrupts */
2007 if (context->index == efx->irq_level)
2008 efx->last_irq_cpu = raw_smp_processor_id();
2009
2010 /* Schedule processing of the channel */
2011 efx_schedule_channel_irq(efx->channel[context->index]);
2012 }
2013
2014 return IRQ_HANDLED;
2015}
2016
2017static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2018{
2019 struct efx_nic *efx = dev_id;
2020 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2021 struct efx_channel *channel;
2022 efx_dword_t reg;
2023 u32 queues;
2024
2025 /* Read the ISR which also ACKs the interrupts */
2026 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2027 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2028
2029 if (queues == 0)
2030 return IRQ_NONE;
2031
2032 if (likely(soft_enabled)) {
2033 /* Note test interrupts */
2034 if (queues & (1U << efx->irq_level))
2035 efx->last_irq_cpu = raw_smp_processor_id();
2036
2037 efx_for_each_channel(channel, efx) {
2038 if (queues & 1)
2039 efx_schedule_channel_irq(channel);
2040 queues >>= 1;
2041 }
2042 }
2043
2044 netif_vdbg(efx, intr, efx->net_dev,
2045 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2046 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2047
2048 return IRQ_HANDLED;
2049}
2050
942e298e 2051static int efx_ef10_irq_test_generate(struct efx_nic *efx)
8127d661
BH		 2052{
2053 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2054
942e298e
JC		 2055 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2056 NULL) == 0)
2057 return -ENOTSUPP;
2058
8127d661
BH		 2059 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2060
2061 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
942e298e 2062 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
8127d661
BH		 2063 inbuf, sizeof(inbuf), NULL, 0, NULL);
2064}
2065
2066static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2067{
2068 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2069 (tx_queue->ptr_mask + 1) *
2070 sizeof(efx_qword_t),
2071 GFP_KERNEL);
2072}
2073
2074/* This writes to the TX_DESC_WPTR and also pushes data */
2075static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2076 const efx_qword_t *txd)
2077{
2078 unsigned int write_ptr;
2079 efx_oword_t reg;
2080
2081 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2082 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2083 reg.qword[0] = *txd;
2084 efx_writeo_page(tx_queue->efx, &reg,
2085 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2086}
2087
e9117e50
BK		 2088/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2089 */
2090static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2091 struct sk_buff *skb,
2092 bool *data_mapped)
2093{
2094 struct efx_tx_buffer *buffer;
2095 struct tcphdr *tcp;
2096 struct iphdr *ip;
2097
2098 u16 ipv4_id;
2099 u32 seqnum;
2100 u32 mss;
2101
e01b16a7 2102 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
e9117e50
BK		 2103
2104 mss = skb_shinfo(skb)->gso_size;
2105
2106 if (unlikely(mss < 4)) {
2107 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2108 return -EINVAL;
2109 }
2110
2111 ip = ip_hdr(skb);
2112 if (ip->version == 4) {
2113 /* Modify IPv4 header if needed. */
2114 ip->tot_len = 0;
2115 ip->check = 0;
2116 ipv4_id = ip->id;
2117 } else {
2118 /* Modify IPv6 header if needed. */
2119 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2120
2121 ipv6->payload_len = 0;
2122 ipv4_id = 0;
2123 }
2124
2125 tcp = tcp_hdr(skb);
2126 seqnum = ntohl(tcp->seq);
2127
2128 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2129
2130 buffer->flags = EFX_TX_BUF_OPTION;
2131 buffer->len = 0;
2132 buffer->unmap_len = 0;
2133 EFX_POPULATE_QWORD_5(buffer->option,
2134 ESF_DZ_TX_DESC_IS_OPT, 1,
2135 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2136 ESF_DZ_TX_TSO_OPTION_TYPE,
2137 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2138 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2139 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2140 );
2141 ++tx_queue->insert_count;
2142
2143 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2144
2145 buffer->flags = EFX_TX_BUF_OPTION;
2146 buffer->len = 0;
2147 buffer->unmap_len = 0;
2148 EFX_POPULATE_QWORD_4(buffer->option,
2149 ESF_DZ_TX_DESC_IS_OPT, 1,
2150 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2151 ESF_DZ_TX_TSO_OPTION_TYPE,
2152 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2153 ESF_DZ_TX_TSO_TCP_MSS, mss
2154 );
2155 ++tx_queue->insert_count;
2156
2157 return 0;
2158}
2159
46d1efd8
EC		 2160static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2161{
2162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2163 u32 tso_versions = 0;
2164
2165 if (nic_data->datapath_caps &
2166 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2167 tso_versions |= BIT(1);
2168 if (nic_data->datapath_caps2 &
2169 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2170 tso_versions |= BIT(2);
2171 return tso_versions;
2172}
2173
8127d661
BH		 2174static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2175{
2176 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2177 EFX_BUF_SIZE));
8127d661
BH		 2178 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2179 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2180 struct efx_channel *channel = tx_queue->channel;
2181 struct efx_nic *efx = tx_queue->efx;
45b2449e 2182 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e9117e50 2183 bool tso_v2 = false;
aa09a3da 2184 size_t inlen;
8127d661
BH		 2185 dma_addr_t dma_addr;
2186 efx_qword_t *txd;
2187 int rc;
2188 int i;
aa09a3da 2189 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661 2190
e9117e50
BK		 2191 /* TSOv2 is a limited resource that can only be configured on a limited
2192 * number of queues. TSO without checksum offload is not really a thing,
2193 * so we only enable it for those queues.
e9117e50
BK		 2194 */
2195 if (csum_offload && (nic_data->datapath_caps2 &
2196 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2197 tso_v2 = true;
2198 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2199 channel->channel);
2200 }
2201
8127d661
BH		 2202 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2203 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2204 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2205 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
8127d661 2206 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 2207 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2208
2209 dma_addr = tx_queue->txd.buf.dma_addr;
2210
2211 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2212 tx_queue->queue, entries, (u64)dma_addr);
2213
2214 for (i = 0; i < entries; ++i) {
2215 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2216 dma_addr += EFX_BUF_SIZE;
2217 }
2218
2219 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2220
e638ee1d
EC		 2221 do {
2222 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2223 /* This flag was removed from mcdi_pcol.h for
2224 * the non-_EXT version of INIT_TXQ. However,
2225 * firmware still honours it.
2226 */
2227 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2228 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2229 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2230
2231 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2232 NULL, 0, NULL);
2233 if (rc == -ENOSPC && tso_v2) {
2234 /* Retry without TSOv2 if we're short on contexts. */
2235 tso_v2 = false;
2236 netif_warn(efx, probe, efx->net_dev,
2237 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2238 } else if (rc) {
2239 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2240 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2241 NULL, 0, rc);
2242 goto fail;
2243 }
2244 } while (rc);
8127d661
BH		 2245
2246 /* A previous user of this TX queue might have set us up the
2247 * bomb by writing a descriptor to the TX push collector but
2248 * not the doorbell. (Each collector belongs to a port, not a
2249 * queue or function, so cannot easily be reset.) We must
2250 * attempt to push a no-op descriptor in its place.
2251 */
2252 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2253 tx_queue->insert_count = 1;
2254 txd = efx_tx_desc(tx_queue, 0);
2255 EFX_POPULATE_QWORD_4(*txd,
2256 ESF_DZ_TX_DESC_IS_OPT, true,
2257 ESF_DZ_TX_OPTION_TYPE,
2258 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2259 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2260 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2261 tx_queue->write_count = 1;
93171b14 2262
e9117e50
BK		 2263 if (tso_v2) {
2264 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2265 tx_queue->tso_version = 2;
2266 } else if (nic_data->datapath_caps &
2267 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
93171b14
BK		 2268 tx_queue->tso_version = 1;
2269 }
2270
8127d661
BH		 2271 wmb();
2272 efx_ef10_push_tx_desc(tx_queue, txd);
2273
2274 return;
2275
2276fail:
48ce5634
BH		 2277 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2278 tx_queue->queue);
8127d661
BH		 2279}
2280
2281static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2282{
2283 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 2284 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2285 struct efx_nic *efx = tx_queue->efx;
2286 size_t outlen;
2287 int rc;
2288
2289 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2290 tx_queue->queue);
2291
1e0b8120 2292 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2293 outbuf, sizeof(outbuf), &outlen);
2294
2295 if (rc && rc != -EALREADY)
2296 goto fail;
2297
2298 return;
2299
2300fail:
1e0b8120
EC		 2301 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2302 outbuf, outlen, rc);
8127d661
BH		 2303}
2304
2305static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2306{
2307 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2308}
2309
2310/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2311static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2312{
2313 unsigned int write_ptr;
2314 efx_dword_t reg;
2315
2316 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2317 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2318 efx_writed_page(tx_queue->efx, &reg,
2319 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2320}
2321
e9117e50
BK		 2322#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2323
2324static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2325 dma_addr_t dma_addr, unsigned int len)
2326{
2327 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2328 /* If we need to break across multiple descriptors we should
2329 * stop at a page boundary. This assumes the length limit is
2330 * greater than the page size.
2331 */
2332 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2333
2334 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2335 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2336 }
2337
2338 return len;
2339}
2340
8127d661
BH		 2341static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2342{
2343 unsigned int old_write_count = tx_queue->write_count;
2344 struct efx_tx_buffer *buffer;
2345 unsigned int write_ptr;
2346 efx_qword_t *txd;
2347
b2663a4f
MH		 2348 tx_queue->xmit_more_available = false;
2349 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2350 return;
8127d661
BH		 2351
2352 do {
2353 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2354 buffer = &tx_queue->buffer[write_ptr];
2355 txd = efx_tx_desc(tx_queue, write_ptr);
2356 ++tx_queue->write_count;
2357
2358 /* Create TX descriptor ring entry */
2359 if (buffer->flags & EFX_TX_BUF_OPTION) {
2360 *txd = buffer->option;
2361 } else {
2362 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2363 EFX_POPULATE_QWORD_3(
2364 *txd,
2365 ESF_DZ_TX_KER_CONT,
2366 buffer->flags & EFX_TX_BUF_CONT,
2367 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2368 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2369 }
2370 } while (tx_queue->write_count != tx_queue->insert_count);
2371
2372 wmb(); /* Ensure descriptors are written before they are fetched */
2373
2374 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2375 txd = efx_tx_desc(tx_queue,
2376 old_write_count & tx_queue->ptr_mask);
2377 efx_ef10_push_tx_desc(tx_queue, txd);
2378 ++tx_queue->pushes;
2379 } else {
2380 efx_ef10_notify_tx_desc(tx_queue);
2381 }
2382}
2383
a33a4c73
EC		 2384#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2385 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2386#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2387 1 << RSS_MODE_HASH_DST_PORT_LBN)
2388#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2389 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2390 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2391 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2392 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2393 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2394 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2395 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2396 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2397 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2398
2399static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2400{
2401 /* Firmware had a bug (sfc bug 61952) where it would not actually
2402 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2403 * This meant that it would always contain whatever was previously
2404 * in the MCDI buffer. Fortunately, all firmware versions with
2405 * this bug have the same default flags value for a newly-allocated
2406 * RSS context, and the only time we want to get the flags is just
2407 * after allocating. Moreover, the response has a 32-bit hole
2408 * where the context ID would be in the request, so we can use an
2409 * overlength buffer in the request and pre-fill the flags field
2410 * with what we believe the default to be. Thus if the firmware
2411 * has the bug, it will leave our pre-filled value in the flags
2412 * field of the response, and we will get the right answer.
2413 *
2414 * However, this does mean that this function should NOT be used if
2415 * the RSS context flags might not be their defaults - it is ONLY
2416 * reliably correct for a newly-allocated RSS context.
2417 */
2418 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2419 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2420 size_t outlen;
2421 int rc;
2422
2423 /* Check we have a hole for the context ID */
2424 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2425 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2426 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2427 RSS_CONTEXT_FLAGS_DEFAULT);
2428 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2429 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2430 if (rc == 0) {
2431 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2432 rc = -EIO;
2433 else
2434 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2435 }
2436 return rc;
2437}
2438
2439/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2440 * If we fail, we just leave the RSS context at its default hash settings,
2441 * which is safe but may slightly reduce performance.
2442 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2443 * just need to set the UDP ports flags (for both IP versions).
2444 */
2445static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2446{
2447 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2448 u32 flags;
2449
2450 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2451
2452 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2453 return;
2454 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2455 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2456 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2457 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
b718c88a
EC		 2458 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2459 NULL, 0, NULL))
2460 /* Succeeded, so UDP 4-tuple is now enabled */
2461 efx->rx_hash_udp_4tuple = true;
a33a4c73
EC		 2462}
2463
267c0157
JC		 2464static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2465 bool exclusive, unsigned *context_size)
8127d661
BH		 2466{
2467 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2468 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 2469 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 2470 size_t outlen;
2471 int rc;
267c0157
JC		 2472 u32 alloc_type = exclusive ?
2473 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2474 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2475 unsigned rss_spread = exclusive ?
2476 efx->rss_spread :
2477 min(rounddown_pow_of_two(efx->rss_spread),
2478 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2479
2480 if (!exclusive && rss_spread == 1) {
2481 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2482 if (context_size)
2483 *context_size = 1;
2484 return 0;
2485 }
8127d661 2486
dcb4123c
JC		 2487 if (nic_data->datapath_caps &
2488 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2489 return -EOPNOTSUPP;
2490
8127d661 2491 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 2492 nic_data->vport_id);
267c0157
JC		 2493 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2494 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 2495
2496 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2497 outbuf, sizeof(outbuf), &outlen);
2498 if (rc != 0)
2499 return rc;
2500
2501 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2502 return -EIO;
2503
2504 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2505
267c0157
JC		 2506 if (context_size)
2507 *context_size = rss_spread;
2508
a33a4c73
EC		 2509 if (nic_data->datapath_caps &
2510 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2511 efx_ef10_set_rss_flags(efx, *context);
2512
8127d661
BH		 2513 return 0;
2514}
2515
2516static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2517{
2518 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2519 int rc;
2520
2521 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2522 context);
2523
2524 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2525 NULL, 0, NULL);
2526 WARN_ON(rc != 0);
2527}
2528
267c0157
JC		 2529static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2530 const u32 *rx_indir_table)
8127d661
BH		 2531{
2532 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2533 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2534 int i, rc;
2535
2536 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2537 context);
2538 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2539 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2540
2541 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2542 MCDI_PTR(tablebuf,
2543 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 2544 (u8) rx_indir_table[i];
8127d661
BH		 2545
2546 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2547 sizeof(tablebuf), NULL, 0, NULL);
2548 if (rc != 0)
2549 return rc;
2550
2551 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2552 context);
2553 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2554 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2555 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2556 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2557 efx->rx_hash_key[i];
2558
2559 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2560 sizeof(keybuf), NULL, 0, NULL);
2561}
2562
2563static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2564{
2565 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2566
2567 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2568 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2569 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2570}
2571
267c0157
JC		 2572static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2573 unsigned *context_size)
8127d661 2574{
267c0157 2575 u32 new_rx_rss_context;
8127d661 2576 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 2577 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2578 false, context_size);
2579
2580 if (rc != 0)
2581 return rc;
8127d661 2582
267c0157
JC		 2583 nic_data->rx_rss_context = new_rx_rss_context;
2584 nic_data->rx_rss_context_exclusive = false;
2585 efx_set_default_rx_indir_table(efx);
2586 return 0;
2587}
8127d661 2588
267c0157
JC		 2589static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2590 const u32 *rx_indir_table)
2591{
2592 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2593 int rc;
2594 u32 new_rx_rss_context;
2595
2596 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2597 !nic_data->rx_rss_context_exclusive) {
2598 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2599 true, NULL);
2600 if (rc == -EOPNOTSUPP)
2601 return rc;
2602 else if (rc != 0)
2603 goto fail1;
2604 } else {
2605 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2606 }
2607
267c0157
JC		 2608 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2609 rx_indir_table);
8127d661 2610 if (rc != 0)
267c0157 2611 goto fail2;
8127d661 2612
267c0157
JC		 2613 if (nic_data->rx_rss_context != new_rx_rss_context)
2614 efx_ef10_rx_free_indir_table(efx);
2615 nic_data->rx_rss_context = new_rx_rss_context;
2616 nic_data->rx_rss_context_exclusive = true;
2617 if (rx_indir_table != efx->rx_indir_table)
2618 memcpy(efx->rx_indir_table, rx_indir_table,
2619 sizeof(efx->rx_indir_table));
2620 return 0;
8127d661 2621
267c0157
JC		 2622fail2:
2623 if (new_rx_rss_context != nic_data->rx_rss_context)
2624 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2625fail1:
8127d661 2626 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2627 return rc;
2628}
2629
2630static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2631 const u32 *rx_indir_table)
2632{
2633 int rc;
2634
2635 if (efx->rss_spread == 1)
2636 return 0;
2637
2638 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2639
2640 if (rc == -ENOBUFS && !user) {
2641 unsigned context_size;
2642 bool mismatch = false;
2643 size_t i;
2644
2645 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2646 i++)
2647 mismatch = rx_indir_table[i] !=
2648 ethtool_rxfh_indir_default(i, efx->rss_spread);
2649
2650 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2651 if (rc == 0) {
2652 if (context_size != efx->rss_spread)
2653 netif_warn(efx, probe, efx->net_dev,
2654 "Could not allocate an exclusive RSS"
2655 " context; allocated a shared one of"
2656 " different size."
2657 " Wanted %u, got %u.\n",
2658 efx->rss_spread, context_size);
2659 else if (mismatch)
2660 netif_warn(efx, probe, efx->net_dev,
2661 "Could not allocate an exclusive RSS"
2662 " context; allocated a shared one but"
2663 " could not apply custom"
2664 " indirection.\n");
2665 else
2666 netif_info(efx, probe, efx->net_dev,
2667 "Could not allocate an exclusive RSS"
2668 " context; allocated a shared one.\n");
2669 }
2670 }
2671 return rc;
2672}
2673
2674static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2675 const u32 *rx_indir_table
2676 __attribute__ ((unused)))
2677{
2678 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2679
2680 if (user)
2681 return -EOPNOTSUPP;
2682 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2683 return 0;
2684 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2685}
2686
2687static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2688{
2689 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2690 (rx_queue->ptr_mask + 1) *
2691 sizeof(efx_qword_t),
2692 GFP_KERNEL);
2693}
2694
2695static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2696{
2697 MCDI_DECLARE_BUF(inbuf,
2698 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2699 EFX_BUF_SIZE));
8127d661
BH		 2700 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2701 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2702 struct efx_nic *efx = rx_queue->efx;
45b2449e 2703 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2704 size_t inlen;
8127d661
BH		 2705 dma_addr_t dma_addr;
2706 int rc;
2707 int i;
aa09a3da 2708 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2709
2710 rx_queue->scatter_n = 0;
2711 rx_queue->scatter_len = 0;
2712
2713 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2714 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2715 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2716 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2717 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2718 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2719 INIT_RXQ_IN_FLAG_PREFIX, 1,
2720 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2721 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2722 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2723
2724 dma_addr = rx_queue->rxd.buf.dma_addr;
2725
2726 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2727 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2728
2729 for (i = 0; i < entries; ++i) {
2730 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2731 dma_addr += EFX_BUF_SIZE;
2732 }
2733
2734 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2735
2736 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2737 NULL, 0, NULL);
48ce5634
BH		 2738 if (rc)
2739 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2740 efx_rx_queue_index(rx_queue));
8127d661
BH		 2741}
2742
2743static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2744{
2745 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2746 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2747 struct efx_nic *efx = rx_queue->efx;
2748 size_t outlen;
2749 int rc;
2750
2751 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2752 efx_rx_queue_index(rx_queue));
2753
1e0b8120 2754 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2755 outbuf, sizeof(outbuf), &outlen);
2756
2757 if (rc && rc != -EALREADY)
2758 goto fail;
2759
2760 return;
2761
2762fail:
1e0b8120
EC		 2763 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2764 outbuf, outlen, rc);
8127d661
BH		 2765}
2766
2767static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2768{
2769 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2770}
2771
2772/* This creates an entry in the RX descriptor queue */
2773static inline void
2774efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2775{
2776 struct efx_rx_buffer *rx_buf;
2777 efx_qword_t *rxd;
2778
2779 rxd = efx_rx_desc(rx_queue, index);
2780 rx_buf = efx_rx_buffer(rx_queue, index);
2781 EFX_POPULATE_QWORD_2(*rxd,
2782 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2783 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2784}
2785
2786static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2787{
2788 struct efx_nic *efx = rx_queue->efx;
2789 unsigned int write_count;
2790 efx_dword_t reg;
2791
2792 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2793 write_count = rx_queue->added_count & ~7;
2794 if (rx_queue->notified_count == write_count)
2795 return;
2796
2797 do
2798 efx_ef10_build_rx_desc(
2799 rx_queue,
2800 rx_queue->notified_count & rx_queue->ptr_mask);
2801 while (++rx_queue->notified_count != write_count);
2802
2803 wmb();
2804 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2805 write_count & rx_queue->ptr_mask);
2806 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2807 efx_rx_queue_index(rx_queue));
2808}
2809
2810static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2811
2812static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2813{
2814 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2815 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2816 efx_qword_t event;
2817
2818 EFX_POPULATE_QWORD_2(event,
2819 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2820 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2821
2822 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2823
2824 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2825 * already swapped the data to little-endian order.
2826 */
2827 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2828 sizeof(efx_qword_t));
2829
2830 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2831 inbuf, sizeof(inbuf), 0,
2832 efx_ef10_rx_defer_refill_complete, 0);
2833}
2834
2835static void
2836efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2837 int rc, efx_dword_t *outbuf,
2838 size_t outlen_actual)
2839{
2840 /* nothing to do */
2841}
2842
2843static int efx_ef10_ev_probe(struct efx_channel *channel)
2844{
2845 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2846 (channel->eventq_mask + 1) *
2847 sizeof(efx_qword_t),
2848 GFP_KERNEL);
2849}
2850
46e612b0
DP		 2851static void efx_ef10_ev_fini(struct efx_channel *channel)
2852{
2853 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2854 MCDI_DECLARE_BUF_ERR(outbuf);
2855 struct efx_nic *efx = channel->efx;
2856 size_t outlen;
2857 int rc;
2858
2859 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2860
2861 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2862 outbuf, sizeof(outbuf), &outlen);
2863
2864 if (rc && rc != -EALREADY)
2865 goto fail;
2866
2867 return;
2868
2869fail:
2870 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2871 outbuf, outlen, rc);
2872}
2873
8127d661
BH		 2874static int efx_ef10_ev_init(struct efx_channel *channel)
2875{
2876 MCDI_DECLARE_BUF(inbuf,
a995560a
BK		 2877 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2878 EFX_BUF_SIZE));
2879 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
8127d661
BH		 2880 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2881 struct efx_nic *efx = channel->efx;
2882 struct efx_ef10_nic_data *nic_data;
8127d661 2883 size_t inlen, outlen;
46e612b0 2884 unsigned int enabled, implemented;
8127d661
BH		 2885 dma_addr_t dma_addr;
2886 int rc;
2887 int i;
2888
2889 nic_data = efx->nic_data;
8127d661
BH		 2890
2891 /* Fill event queue with all ones (i.e. empty events) */
2892 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2893
2894 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2895 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2896 /* INIT_EVQ expects index in vector table, not absolute */
2897 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
8127d661
BH		 2898 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2899 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2900 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2901 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2902 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2903 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2904 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2905
a995560a
BK		 2906 if (nic_data->datapath_caps2 &
2907 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
2908 /* Use the new generic approach to specifying event queue
2909 * configuration, requesting lower latency or higher throughput.
2910 * The options that actually get used appear in the output.
2911 */
2912 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
2913 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
2914 INIT_EVQ_V2_IN_FLAG_TYPE,
2915 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
2916 } else {
2917 bool cut_thru = !(nic_data->datapath_caps &
2918 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2919
2920 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2921 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2922 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2923 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2924 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
2925 }
2926
8127d661
BH		 2927 dma_addr = channel->eventq.buf.dma_addr;
2928 for (i = 0; i < entries; ++i) {
2929 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2930 dma_addr += EFX_BUF_SIZE;
2931 }
2932
2933 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2934
2935 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2936 outbuf, sizeof(outbuf), &outlen);
a995560a
BK		 2937
2938 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
2939 netif_dbg(efx, drv, efx->net_dev,
2940 "Channel %d using event queue flags %08x\n",
2941 channel->channel,
2942 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
2943
8127d661 2944 /* IRQ return is ignored */
46e612b0
DP		 2945 if (channel->channel || rc)
2946 return rc;
8127d661 2947
46e612b0
DP		 2948 /* Successfully created event queue on channel 0 */
2949 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed 2950 if (rc == -ENOSYS) {
d95e329a
BK		 2951 /* GET_WORKAROUNDS was implemented before this workaround,
2952 * thus it must be unavailable in this firmware.
832dc9ed
EC		 2953 */
2954 nic_data->workaround_26807 = false;
2955 rc = 0;
2956 } else if (rc) {
8127d661 2957 goto fail;
832dc9ed
EC		 2958 } else {
2959 nic_data->workaround_26807 =
2960 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2961
2962 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2963 !nic_data->workaround_26807) {
5a55a72a
DP		 2964 unsigned int flags;
2965
34ccfe6f
DP		 2966 rc = efx_mcdi_set_workaround(efx,
2967 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 2968 true, &flags);
2969
2970 if (!rc) {
2971 if (flags &
2972 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2973 netif_info(efx, drv, efx->net_dev,
2974 "other functions on NIC have been reset\n");
abd86a55
DP		 2975
2976 /* With MCFW v4.6.x and earlier, the
2977 * boot count will have incremented,
2978 * so re-read the warm_boot_count
2979 * value now to ensure this function
2980 * doesn't think it has changed next
2981 * time it checks.
2982 */
2983 rc = efx_ef10_get_warm_boot_count(efx);
2984 if (rc >= 0) {
2985 nic_data->warm_boot_count = rc;
2986 rc = 0;
2987 }
5a55a72a 2988 }
832dc9ed 2989 nic_data->workaround_26807 = true;
5a55a72a 2990 } else if (rc == -EPERM) {
832dc9ed 2991 rc = 0;
5a55a72a 2992 }
832dc9ed 2993 }
46e612b0
DP		 2994 }
2995
2996 if (!rc)
2997 return 0;
8127d661
BH		 2998
2999fail:
46e612b0
DP		 3000 efx_ef10_ev_fini(channel);
3001 return rc;
8127d661
BH		 3002}
3003
3004static void efx_ef10_ev_remove(struct efx_channel *channel)
3005{
3006 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3007}
3008
3009static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3010 unsigned int rx_queue_label)
3011{
3012 struct efx_nic *efx = rx_queue->efx;
3013
3014 netif_info(efx, hw, efx->net_dev,
3015 "rx event arrived on queue %d labeled as queue %u\n",
3016 efx_rx_queue_index(rx_queue), rx_queue_label);
3017
3018 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3019}
3020
3021static void
3022efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3023 unsigned int actual, unsigned int expected)
3024{
3025 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3026 struct efx_nic *efx = rx_queue->efx;
3027
3028 netif_info(efx, hw, efx->net_dev,
3029 "dropped %d events (index=%d expected=%d)\n",
3030 dropped, actual, expected);
3031
3032 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3033}
3034
3035/* partially received RX was aborted. clean up. */
3036static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3037{
3038 unsigned int rx_desc_ptr;
3039
8127d661
BH		 3040 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3041 "scattered RX aborted (dropping %u buffers)\n",
3042 rx_queue->scatter_n);
3043
3044 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3045
3046 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3047 0, EFX_RX_PKT_DISCARD);
3048
3049 rx_queue->removed_count += rx_queue->scatter_n;
3050 rx_queue->scatter_n = 0;
3051 rx_queue->scatter_len = 0;
3052 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3053}
3054
3055static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3056 const efx_qword_t *event)
3057{
3058 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
3059 unsigned int n_descs, n_packets, i;
3060 struct efx_nic *efx = channel->efx;
3061 struct efx_rx_queue *rx_queue;
3062 bool rx_cont;
3063 u16 flags = 0;
3064
3065 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3066 return 0;
3067
3068 /* Basic packet information */
3069 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3070 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3071 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3072 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3073 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3074
48ce5634
BH		 3075 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3076 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3077 EFX_QWORD_FMT "\n",
3078 EFX_QWORD_VAL(*event));
8127d661
BH		 3079
3080 rx_queue = efx_channel_get_rx_queue(channel);
3081
3082 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3083 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3084
3085 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3086 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3087
3088 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 3089 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3090
8127d661
BH		 3091 /* detect rx abort */
3092 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 3093 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3094 netdev_WARN(efx->net_dev,
3095 "invalid RX abort: scatter_n=%u event="
3096 EFX_QWORD_FMT "\n",
3097 rx_queue->scatter_n,
3098 EFX_QWORD_VAL(*event));
8127d661
BH		 3099 efx_ef10_handle_rx_abort(rx_queue);
3100 return 0;
3101 }
3102
92a04168
BH		 3103 /* Check that RX completion merging is valid, i.e.
3104 * the current firmware supports it and this is a
3105 * non-scattered packet.
3106 */
3107 if (!(nic_data->datapath_caps &
3108 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3109 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 3110 efx_ef10_handle_rx_bad_lbits(
3111 rx_queue, next_ptr_lbits,
3112 (rx_queue->removed_count +
3113 rx_queue->scatter_n + 1) &
3114 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3115 return 0;
3116 }
3117
3118 /* Merged completion for multiple non-scattered packets */
3119 rx_queue->scatter_n = 1;
3120 rx_queue->scatter_len = 0;
3121 n_packets = n_descs;
3122 ++channel->n_rx_merge_events;
3123 channel->n_rx_merge_packets += n_packets;
3124 flags |= EFX_RX_PKT_PREFIX_LEN;
3125 } else {
3126 ++rx_queue->scatter_n;
3127 rx_queue->scatter_len += rx_bytes;
3128 if (rx_cont)
3129 return 0;
3130 n_packets = 1;
3131 }
3132
3133 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
3134 flags |= EFX_RX_PKT_DISCARD;
3135
3136 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
3137 channel->n_rx_ip_hdr_chksum_err += n_packets;
3138 } else if (unlikely(EFX_QWORD_FIELD(*event,
3139 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
3140 channel->n_rx_tcp_udp_chksum_err += n_packets;
3141 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3142 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
3143 flags |= EFX_RX_PKT_CSUMMED;
3144 }
3145
3146 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3147 flags |= EFX_RX_PKT_TCP;
3148
3149 channel->irq_mod_score += 2 * n_packets;
3150
3151 /* Handle received packet(s) */
3152 for (i = 0; i < n_packets; i++) {
3153 efx_rx_packet(rx_queue,
3154 rx_queue->removed_count & rx_queue->ptr_mask,
3155 rx_queue->scatter_n, rx_queue->scatter_len,
3156 flags);
3157 rx_queue->removed_count += rx_queue->scatter_n;
3158 }
3159
3160 rx_queue->scatter_n = 0;
3161 rx_queue->scatter_len = 0;
3162
3163 return n_packets;
3164}
3165
3166static int
3167efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3168{
3169 struct efx_nic *efx = channel->efx;
3170 struct efx_tx_queue *tx_queue;
3171 unsigned int tx_ev_desc_ptr;
3172 unsigned int tx_ev_q_label;
3173 int tx_descs = 0;
3174
3175 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3176 return 0;
3177
3178 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3179 return 0;
3180
3181 /* Transmit completion */
3182 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3183 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3184 tx_queue = efx_channel_get_tx_queue(channel,
3185 tx_ev_q_label % EFX_TXQ_TYPES);
3186 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3187 tx_queue->ptr_mask);
3188 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3189
3190 return tx_descs;
3191}
3192
3193static void
3194efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3195{
3196 struct efx_nic *efx = channel->efx;
3197 int subcode;
3198
3199 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3200
3201 switch (subcode) {
3202 case ESE_DZ_DRV_TIMER_EV:
3203 case ESE_DZ_DRV_WAKE_UP_EV:
3204 break;
3205 case ESE_DZ_DRV_START_UP_EV:
3206 /* event queue init complete. ok. */
3207 break;
3208 default:
3209 netif_err(efx, hw, efx->net_dev,
3210 "channel %d unknown driver event type %d"
3211 " (data " EFX_QWORD_FMT ")\n",
3212 channel->channel, subcode,
3213 EFX_QWORD_VAL(*event));
3214
3215 }
3216}
3217
3218static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3219 efx_qword_t *event)
3220{
3221 struct efx_nic *efx = channel->efx;
3222 u32 subcode;
3223
3224 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3225
3226 switch (subcode) {
3227 case EFX_EF10_TEST:
3228 channel->event_test_cpu = raw_smp_processor_id();
3229 break;
3230 case EFX_EF10_REFILL:
3231 /* The queue must be empty, so we won't receive any rx
3232 * events, so efx_process_channel() won't refill the
3233 * queue. Refill it here
3234 */
cce28794 3235 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 3236 break;
3237 default:
3238 netif_err(efx, hw, efx->net_dev,
3239 "channel %d unknown driver event type %u"
3240 " (data " EFX_QWORD_FMT ")\n",
3241 channel->channel, (unsigned) subcode,
3242 EFX_QWORD_VAL(*event));
3243 }
3244}
3245
3246static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3247{
3248 struct efx_nic *efx = channel->efx;
3249 efx_qword_t event, *p_event;
3250 unsigned int read_ptr;
3251 int ev_code;
3252 int tx_descs = 0;
3253 int spent = 0;
3254
75363a46
EB		 3255 if (quota <= 0)
3256 return spent;
3257
8127d661
BH		 3258 read_ptr = channel->eventq_read_ptr;
3259
3260 for (;;) {
3261 p_event = efx_event(channel, read_ptr);
3262 event = *p_event;
3263
3264 if (!efx_event_present(&event))
3265 break;
3266
3267 EFX_SET_QWORD(*p_event);
3268
3269 ++read_ptr;
3270
3271 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3272
3273 netif_vdbg(efx, drv, efx->net_dev,
3274 "processing event on %d " EFX_QWORD_FMT "\n",
3275 channel->channel, EFX_QWORD_VAL(event));
3276
3277 switch (ev_code) {
3278 case ESE_DZ_EV_CODE_MCDI_EV:
3279 efx_mcdi_process_event(channel, &event);
3280 break;
3281 case ESE_DZ_EV_CODE_RX_EV:
3282 spent += efx_ef10_handle_rx_event(channel, &event);
3283 if (spent >= quota) {
3284 /* XXX can we split a merged event to
3285 * avoid going over-quota?
3286 */
3287 spent = quota;
3288 goto out;
3289 }
3290 break;
3291 case ESE_DZ_EV_CODE_TX_EV:
3292 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3293 if (tx_descs > efx->txq_entries) {
3294 spent = quota;
3295 goto out;
3296 } else if (++spent == quota) {
3297 goto out;
3298 }
3299 break;
3300 case ESE_DZ_EV_CODE_DRIVER_EV:
3301 efx_ef10_handle_driver_event(channel, &event);
3302 if (++spent == quota)
3303 goto out;
3304 break;
3305 case EFX_EF10_DRVGEN_EV:
3306 efx_ef10_handle_driver_generated_event(channel, &event);
3307 break;
3308 default:
3309 netif_err(efx, hw, efx->net_dev,
3310 "channel %d unknown event type %d"
3311 " (data " EFX_QWORD_FMT ")\n",
3312 channel->channel, ev_code,
3313 EFX_QWORD_VAL(event));
3314 }
3315 }
3316
3317out:
3318 channel->eventq_read_ptr = read_ptr;
3319 return spent;
3320}
3321
3322static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3323{
3324 struct efx_nic *efx = channel->efx;
3325 efx_dword_t rptr;
3326
3327 if (EFX_EF10_WORKAROUND_35388(efx)) {
3328 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3329 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3330 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3331 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3332
3333 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3334 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3335 ERF_DD_EVQ_IND_RPTR,
3336 (channel->eventq_read_ptr &
3337 channel->eventq_mask) >>
3338 ERF_DD_EVQ_IND_RPTR_WIDTH);
3339 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3340 channel->channel);
3341 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3342 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3343 ERF_DD_EVQ_IND_RPTR,
3344 channel->eventq_read_ptr &
3345 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3346 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3347 channel->channel);
3348 } else {
3349 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3350 channel->eventq_read_ptr &
3351 channel->eventq_mask);
3352 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3353 }
3354}
3355
3356static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3357{
3358 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3359 struct efx_nic *efx = channel->efx;
3360 efx_qword_t event;
3361 int rc;
3362
3363 EFX_POPULATE_QWORD_2(event,
3364 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3365 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3366
3367 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3368
3369 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3370 * already swapped the data to little-endian order.
3371 */
3372 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3373 sizeof(efx_qword_t));
3374
3375 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3376 NULL, 0, NULL);
3377 if (rc != 0)
3378 goto fail;
3379
3380 return;
3381
3382fail:
3383 WARN_ON(true);
3384 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3385}
3386
3387void efx_ef10_handle_drain_event(struct efx_nic *efx)
3388{
3389 if (atomic_dec_and_test(&efx->active_queues))
3390 wake_up(&efx->flush_wq);
3391
3392 WARN_ON(atomic_read(&efx->active_queues) < 0);
3393}
3394
3395static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3396{
3397 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3398 struct efx_channel *channel;
3399 struct efx_tx_queue *tx_queue;
3400 struct efx_rx_queue *rx_queue;
3401 int pending;
3402
3403 /* If the MC has just rebooted, the TX/RX queues will have already been
3404 * torn down, but efx->active_queues needs to be set to zero.
3405 */
3406 if (nic_data->must_realloc_vis) {
3407 atomic_set(&efx->active_queues, 0);
3408 return 0;
3409 }
3410
3411 /* Do not attempt to write to the NIC during EEH recovery */
3412 if (efx->state != STATE_RECOVERY) {
3413 efx_for_each_channel(channel, efx) {
3414 efx_for_each_channel_rx_queue(rx_queue, channel)
3415 efx_ef10_rx_fini(rx_queue);
3416 efx_for_each_channel_tx_queue(tx_queue, channel)
3417 efx_ef10_tx_fini(tx_queue);
3418 }
3419
3420 wait_event_timeout(efx->flush_wq,
3421 atomic_read(&efx->active_queues) == 0,
3422 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3423 pending = atomic_read(&efx->active_queues);
3424 if (pending) {
3425 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3426 pending);
3427 return -ETIMEDOUT;
3428 }
3429 }
3430
3431 return 0;
3432}
3433
e283546c
EC		 3434static void efx_ef10_prepare_flr(struct efx_nic *efx)
3435{
3436 atomic_set(&efx->active_queues, 0);
3437}
3438
8127d661
BH		 3439static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3440 const struct efx_filter_spec *right)
3441{
3442 if ((left->match_flags ^ right->match_flags) |
3443 ((left->flags ^ right->flags) &
3444 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3445 return false;
3446
3447 return memcmp(&left->outer_vid, &right->outer_vid,
3448 sizeof(struct efx_filter_spec) -
3449 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3450}
3451
3452static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3453{
3454 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3455 return jhash2((const u32 *)&spec->outer_vid,
3456 (sizeof(struct efx_filter_spec) -
3457 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3458 0);
3459 /* XXX should we randomise the initval? */
3460}
3461
3462/* Decide whether a filter should be exclusive or else should allow
3463 * delivery to additional recipients. Currently we decide that
3464 * filters for specific local unicast MAC and IP addresses are
3465 * exclusive.
3466 */
3467static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3468{
3469 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3470 !is_multicast_ether_addr(spec->loc_mac))
3471 return true;
3472
3473 if ((spec->match_flags &
3474 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3475 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3476 if (spec->ether_type == htons(ETH_P_IP) &&
3477 !ipv4_is_multicast(spec->loc_host[0]))
3478 return true;
3479 if (spec->ether_type == htons(ETH_P_IPV6) &&
3480 ((const u8 *)spec->loc_host)[0] != 0xff)
3481 return true;
3482 }
3483
3484 return false;
3485}
3486
3487static struct efx_filter_spec *
3488efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3489 unsigned int filter_idx)
3490{
3491 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3492 ~EFX_EF10_FILTER_FLAGS);
3493}
3494
3495static unsigned int
3496efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3497 unsigned int filter_idx)
3498{
3499 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3500}
3501
3502static void
3503efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3504 unsigned int filter_idx,
3505 const struct efx_filter_spec *spec,
3506 unsigned int flags)
3507{
3508 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3509}
3510
3511static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3512 const struct efx_filter_spec *spec,
3513 efx_dword_t *inbuf, u64 handle,
3514 bool replacing)
3515{
3516 struct efx_ef10_nic_data *nic_data = efx->nic_data;
dcb4123c 3517 u32 flags = spec->flags;
8127d661
BH		 3518
3519 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3520
dcb4123c
JC		 3521 /* Remove RSS flag if we don't have an RSS context. */
3522 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3523 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3524 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3525 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3526
8127d661
BH		 3527 if (replacing) {
3528 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3529 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3530 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3531 } else {
3532 u32 match_fields = 0;
3533
3534 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3535 efx_ef10_filter_is_exclusive(spec) ?
3536 MC_CMD_FILTER_OP_IN_OP_INSERT :
3537 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3538
3539 /* Convert match flags and values. Unlike almost
3540 * everything else in MCDI, these fields are in
3541 * network byte order.
3542 */
3543 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3544 match_fields |=
3545 is_multicast_ether_addr(spec->loc_mac) ?
3546 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3547 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3548#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3549 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3550 match_fields |= \
3551 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3552 mcdi_field ## _LBN; \
3553 BUILD_BUG_ON( \
3554 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3555 sizeof(spec->gen_field)); \
3556 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3557 &spec->gen_field, sizeof(spec->gen_field)); \
3558 }
3559 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3560 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3561 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3562 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3563 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3564 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3565 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3566 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3567 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3568 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3569#undef COPY_FIELD
3570 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3571 match_fields);
3572 }
3573
45b2449e 3574 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 3575 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3576 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3577 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3578 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 3579 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 3580 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3581 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 3582 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3583 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3584 0 : spec->dmaq_id);
8127d661 3585 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
dcb4123c 3586 (flags & EFX_FILTER_FLAG_RX_RSS) ?
8127d661
BH		 3587 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3588 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
dcb4123c 3589 if (flags & EFX_FILTER_FLAG_RX_RSS)
8127d661
BH		 3590 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3591 spec->rss_context !=
3592 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3593 spec->rss_context : nic_data->rx_rss_context);
3594}
3595
3596static int efx_ef10_filter_push(struct efx_nic *efx,
3597 const struct efx_filter_spec *spec,
3598 u64 *handle, bool replacing)
3599{
3600 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3601 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3602 int rc;
3603
3604 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3605 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3606 outbuf, sizeof(outbuf), NULL);
3607 if (rc == 0)
3608 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 3609 if (rc == -ENOSPC)
3610 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 3611 return rc;
3612}
3613
7ac0dd9d 3614static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
8127d661 3615{
7ac0dd9d
AR		 3616 unsigned int match_flags = spec->match_flags;
3617 u32 mcdi_flags = 0;
3618
3619 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3620 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3621 mcdi_flags |=
3622 is_multicast_ether_addr(spec->loc_mac) ?
3623 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3624 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3625 }
3626
3627#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3628 unsigned int old_match_flags = match_flags; \
3629 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3630 if (match_flags != old_match_flags) \
3631 mcdi_flags |= \
3632 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3633 mcdi_field ## _LBN); \
3634 }
3635 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3636 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3637 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3638 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3639 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3640 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3641 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3642 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3643 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3644 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3645#undef MAP_FILTER_TO_MCDI_FLAG
3646
3647 /* Did we map them all? */
3648 WARN_ON_ONCE(match_flags);
3649
3650 return mcdi_flags;
3651}
3652
3653static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3654 const struct efx_filter_spec *spec)
3655{
3656 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
8127d661
BH		 3657 unsigned int match_pri;
3658
3659 for (match_pri = 0;
3660 match_pri < table->rx_match_count;
3661 match_pri++)
7ac0dd9d 3662 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
8127d661
BH		 3663 return match_pri;
3664
3665 return -EPROTONOSUPPORT;
3666}
3667
3668static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3669 struct efx_filter_spec *spec,
3670 bool replace_equal)
3671{
3672 struct efx_ef10_filter_table *table = efx->filter_state;
3673 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3674 struct efx_filter_spec *saved_spec;
3675 unsigned int match_pri, hash;
3676 unsigned int priv_flags;
3677 bool replacing = false;
3678 int ins_index = -1;
3679 DEFINE_WAIT(wait);
3680 bool is_mc_recip;
3681 s32 rc;
3682
3683 /* For now, only support RX filters */
3684 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3685 EFX_FILTER_FLAG_RX)
3686 return -EINVAL;
3687
7ac0dd9d 3688 rc = efx_ef10_filter_pri(table, spec);
8127d661
BH		 3689 if (rc < 0)
3690 return rc;
3691 match_pri = rc;
3692
3693 hash = efx_ef10_filter_hash(spec);
3694 is_mc_recip = efx_filter_is_mc_recipient(spec);
3695 if (is_mc_recip)
3696 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3697
3698 /* Find any existing filters with the same match tuple or
3699 * else a free slot to insert at. If any of them are busy,
3700 * we have to wait and retry.
3701 */
3702 for (;;) {
3703 unsigned int depth = 1;
3704 unsigned int i;
3705
3706 spin_lock_bh(&efx->filter_lock);
3707
3708 for (;;) {
3709 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3710 saved_spec = efx_ef10_filter_entry_spec(table, i);
3711
3712 if (!saved_spec) {
3713 if (ins_index < 0)
3714 ins_index = i;
3715 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3716 if (table->entry[i].spec &
3717 EFX_EF10_FILTER_FLAG_BUSY)
3718 break;
3719 if (spec->priority < saved_spec->priority &&
7665d1ab 3720 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3721 rc = -EPERM;
3722 goto out_unlock;
3723 }
3724 if (!is_mc_recip) {
3725 /* This is the only one */
3726 if (spec->priority ==
3727 saved_spec->priority &&
3728 !replace_equal) {
3729 rc = -EEXIST;
3730 goto out_unlock;
3731 }
3732 ins_index = i;
3733 goto found;
3734 } else if (spec->priority >
3735 saved_spec->priority ||
3736 (spec->priority ==
3737 saved_spec->priority &&
3738 replace_equal)) {
3739 if (ins_index < 0)
3740 ins_index = i;
3741 else
3742 __set_bit(depth, mc_rem_map);
3743 }
3744 }
3745
3746 /* Once we reach the maximum search depth, use
3747 * the first suitable slot or return -EBUSY if
3748 * there was none
3749 */
3750 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3751 if (ins_index < 0) {
3752 rc = -EBUSY;
3753 goto out_unlock;
3754 }
3755 goto found;
3756 }
3757
3758 ++depth;
3759 }
3760
3761 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3762 spin_unlock_bh(&efx->filter_lock);
3763 schedule();
3764 }
3765
3766found:
3767 /* Create a software table entry if necessary, and mark it
3768 * busy. We might yet fail to insert, but any attempt to
3769 * insert a conflicting filter while we're waiting for the
3770 * firmware must find the busy entry.
3771 */
3772 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3773 if (saved_spec) {
7665d1ab
BH		 3774 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3775 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3776 /* Just make sure it won't be removed */
7665d1ab
BH		 3777 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3778 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3779 table->entry[ins_index].spec &=
b59e6ef8 3780 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3781 rc = ins_index;
3782 goto out_unlock;
3783 }
3784 replacing = true;
3785 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3786 } else {
3787 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3788 if (!saved_spec) {
3789 rc = -ENOMEM;
3790 goto out_unlock;
3791 }
3792 *saved_spec = *spec;
3793 priv_flags = 0;
3794 }
3795 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3796 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3797
3798 /* Mark lower-priority multicast recipients busy prior to removal */
3799 if (is_mc_recip) {
3800 unsigned int depth, i;
3801
3802 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3803 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3804 if (test_bit(depth, mc_rem_map))
3805 table->entry[i].spec |=
3806 EFX_EF10_FILTER_FLAG_BUSY;
3807 }
3808 }
3809
3810 spin_unlock_bh(&efx->filter_lock);
3811
3812 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3813 replacing);
3814
3815 /* Finalise the software table entry */
3816 spin_lock_bh(&efx->filter_lock);
3817 if (rc == 0) {
3818 if (replacing) {
3819 /* Update the fields that may differ */
7665d1ab
BH		 3820 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3821 saved_spec->flags |=
3822 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3823 saved_spec->priority = spec->priority;
7665d1ab 3824 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 3825 saved_spec->flags |= spec->flags;
3826 saved_spec->rss_context = spec->rss_context;
3827 saved_spec->dmaq_id = spec->dmaq_id;
3828 }
3829 } else if (!replacing) {
3830 kfree(saved_spec);
3831 saved_spec = NULL;
3832 }
3833 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3834
3835 /* Remove and finalise entries for lower-priority multicast
3836 * recipients
3837 */
3838 if (is_mc_recip) {
3839 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3840 unsigned int depth, i;
3841
3842 memset(inbuf, 0, sizeof(inbuf));
3843
3844 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3845 if (!test_bit(depth, mc_rem_map))
3846 continue;
3847
3848 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3849 saved_spec = efx_ef10_filter_entry_spec(table, i);
3850 priv_flags = efx_ef10_filter_entry_flags(table, i);
3851
3852 if (rc == 0) {
3853 spin_unlock_bh(&efx->filter_lock);
3854 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3855 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3856 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3857 table->entry[i].handle);
3858 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3859 inbuf, sizeof(inbuf),
3860 NULL, 0, NULL);
3861 spin_lock_bh(&efx->filter_lock);
3862 }
3863
3864 if (rc == 0) {
3865 kfree(saved_spec);
3866 saved_spec = NULL;
3867 priv_flags = 0;
3868 } else {
3869 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3870 }
3871 efx_ef10_filter_set_entry(table, i, saved_spec,
3872 priv_flags);
3873 }
3874 }
3875
3876 /* If successful, return the inserted filter ID */
3877 if (rc == 0)
3878 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3879
3880 wake_up_all(&table->waitq);
3881out_unlock:
3882 spin_unlock_bh(&efx->filter_lock);
3883 finish_wait(&table->waitq, &wait);
3884 return rc;
3885}
3886
9fd8095d 3887static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 3888{
3889 /* no need to do anything here on EF10 */
3890}
3891
3892/* Remove a filter.
b59e6ef8
BH		 3893 * If !by_index, remove by ID
3894 * If by_index, remove by index
8127d661
BH		 3895 * Filter ID may come from userland and must be range-checked.
3896 */
3897static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 3898 unsigned int priority_mask,
b59e6ef8 3899 u32 filter_id, bool by_index)
8127d661
BH		 3900{
3901 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3902 struct efx_ef10_filter_table *table = efx->filter_state;
3903 MCDI_DECLARE_BUF(inbuf,
3904 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3905 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3906 struct efx_filter_spec *spec;
3907 DEFINE_WAIT(wait);
3908 int rc;
3909
3910 /* Find the software table entry and mark it busy. Don't
3911 * remove it yet; any attempt to update while we're waiting
3912 * for the firmware must find the busy entry.
3913 */
3914 for (;;) {
3915 spin_lock_bh(&efx->filter_lock);
3916 if (!(table->entry[filter_idx].spec &
3917 EFX_EF10_FILTER_FLAG_BUSY))
3918 break;
3919 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3920 spin_unlock_bh(&efx->filter_lock);
3921 schedule();
3922 }
7665d1ab 3923
8127d661 3924 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 3925 if (!spec ||
b59e6ef8 3926 (!by_index &&
7ac0dd9d 3927 efx_ef10_filter_pri(table, spec) !=
8127d661
BH		 3928 filter_id / HUNT_FILTER_TBL_ROWS)) {
3929 rc = -ENOENT;
3930 goto out_unlock;
3931 }
7665d1ab
BH		 3932
3933 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 3934 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 3935 /* Just remove flags */
3936 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 3937 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 3938 rc = 0;
3939 goto out_unlock;
3940 }
3941
fbd79120 3942 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 3943 rc = -ENOENT;
3944 goto out_unlock;
3945 }
3946
8127d661
BH		 3947 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3948 spin_unlock_bh(&efx->filter_lock);
3949
7665d1ab 3950 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 3951 /* Reset to an automatic filter */
8127d661
BH		 3952
3953 struct efx_filter_spec new_spec = *spec;
3954
7665d1ab 3955 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 3956 new_spec.flags = (EFX_FILTER_FLAG_RX |
f1c2ef40
BK		 3957 (efx_rss_enabled(efx) ?
3958 EFX_FILTER_FLAG_RX_RSS : 0));
8127d661
BH		 3959 new_spec.dmaq_id = 0;
3960 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3961 rc = efx_ef10_filter_push(efx, &new_spec,
3962 &table->entry[filter_idx].handle,
3963 true);
3964
3965 spin_lock_bh(&efx->filter_lock);
3966 if (rc == 0)
3967 *spec = new_spec;
3968 } else {
3969 /* Really remove the filter */
3970
3971 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3972 efx_ef10_filter_is_exclusive(spec) ?
3973 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3974 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3975 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3976 table->entry[filter_idx].handle);
3977 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3978 inbuf, sizeof(inbuf), NULL, 0, NULL);
3979
3980 spin_lock_bh(&efx->filter_lock);
3981 if (rc == 0) {
3982 kfree(spec);
3983 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3984 }
3985 }
7665d1ab 3986
8127d661
BH		 3987 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3988 wake_up_all(&table->waitq);
3989out_unlock:
3990 spin_unlock_bh(&efx->filter_lock);
3991 finish_wait(&table->waitq, &wait);
3992 return rc;
3993}
3994
3995static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3996 enum efx_filter_priority priority,
3997 u32 filter_id)
3998{
fbd79120
BH		 3999 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4000 filter_id, false);
8127d661
BH		 4001}
4002
12fb0da4
EC		 4003static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
4004{
4005 return filter_id % HUNT_FILTER_TBL_ROWS;
4006}
4007
8c915620
EC		 4008static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4009 enum efx_filter_priority priority,
4010 u32 filter_id)
12fb0da4 4011{
8c915620
EC		 4012 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4013 return;
4014 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
12fb0da4
EC		 4015}
4016
8127d661
BH		 4017static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4018 enum efx_filter_priority priority,
4019 u32 filter_id, struct efx_filter_spec *spec)
4020{
4021 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
4022 struct efx_ef10_filter_table *table = efx->filter_state;
4023 const struct efx_filter_spec *saved_spec;
4024 int rc;
4025
4026 spin_lock_bh(&efx->filter_lock);
4027 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4028 if (saved_spec && saved_spec->priority == priority &&
7ac0dd9d 4029 efx_ef10_filter_pri(table, saved_spec) ==
8127d661
BH		 4030 filter_id / HUNT_FILTER_TBL_ROWS) {
4031 *spec = *saved_spec;
4032 rc = 0;
4033 } else {
4034 rc = -ENOENT;
4035 }
4036 spin_unlock_bh(&efx->filter_lock);
4037 return rc;
4038}
4039
fbd79120 4040static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 4041 enum efx_filter_priority priority)
4042{
fbd79120
BH		 4043 unsigned int priority_mask;
4044 unsigned int i;
4045 int rc;
4046
4047 priority_mask = (((1U << (priority + 1)) - 1) &
4048 ~(1U << EFX_FILTER_PRI_AUTO));
4049
4050 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4051 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4052 i, true);
4053 if (rc && rc != -ENOENT)
4054 return rc;
4055 }
4056
4057 return 0;
8127d661
BH		 4058}
4059
4060static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4061 enum efx_filter_priority priority)
4062{
4063 struct efx_ef10_filter_table *table = efx->filter_state;
4064 unsigned int filter_idx;
4065 s32 count = 0;
4066
4067 spin_lock_bh(&efx->filter_lock);
4068 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4069 if (table->entry[filter_idx].spec &&
4070 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4071 priority)
4072 ++count;
4073 }
4074 spin_unlock_bh(&efx->filter_lock);
4075 return count;
4076}
4077
4078static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4079{
4080 struct efx_ef10_filter_table *table = efx->filter_state;
4081
4082 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
4083}
4084
4085static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4086 enum efx_filter_priority priority,
4087 u32 *buf, u32 size)
4088{
4089 struct efx_ef10_filter_table *table = efx->filter_state;
4090 struct efx_filter_spec *spec;
4091 unsigned int filter_idx;
4092 s32 count = 0;
4093
4094 spin_lock_bh(&efx->filter_lock);
4095 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4096 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4097 if (spec && spec->priority == priority) {
4098 if (count == size) {
4099 count = -EMSGSIZE;
4100 break;
4101 }
7ac0dd9d 4102 buf[count++] = (efx_ef10_filter_pri(table, spec) *
8127d661
BH		 4103 HUNT_FILTER_TBL_ROWS +
4104 filter_idx);
4105 }
4106 }
4107 spin_unlock_bh(&efx->filter_lock);
4108 return count;
4109}
4110
4111#ifdef CONFIG_RFS_ACCEL
4112
4113static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4114
4115static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4116 struct efx_filter_spec *spec)
4117{
4118 struct efx_ef10_filter_table *table = efx->filter_state;
4119 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4120 struct efx_filter_spec *saved_spec;
4121 unsigned int hash, i, depth = 1;
4122 bool replacing = false;
4123 int ins_index = -1;
4124 u64 cookie;
4125 s32 rc;
4126
4127 /* Must be an RX filter without RSS and not for a multicast
4128 * destination address (RFS only works for connected sockets).
4129 * These restrictions allow us to pass only a tiny amount of
4130 * data through to the completion function.
4131 */
4132 EFX_WARN_ON_PARANOID(spec->flags !=
4133 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4134 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4135 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4136
4137 hash = efx_ef10_filter_hash(spec);
4138
4139 spin_lock_bh(&efx->filter_lock);
4140
4141 /* Find any existing filter with the same match tuple or else
4142 * a free slot to insert at. If an existing filter is busy,
4143 * we have to give up.
4144 */
4145 for (;;) {
4146 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4147 saved_spec = efx_ef10_filter_entry_spec(table, i);
4148
4149 if (!saved_spec) {
4150 if (ins_index < 0)
4151 ins_index = i;
4152 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4153 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4154 rc = -EBUSY;
4155 goto fail_unlock;
4156 }
8127d661
BH		 4157 if (spec->priority < saved_spec->priority) {
4158 rc = -EPERM;
4159 goto fail_unlock;
4160 }
4161 ins_index = i;
4162 break;
4163 }
4164
4165 /* Once we reach the maximum search depth, use the
4166 * first suitable slot or return -EBUSY if there was
4167 * none
4168 */
4169 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4170 if (ins_index < 0) {
4171 rc = -EBUSY;
4172 goto fail_unlock;
4173 }
4174 break;
4175 }
4176
4177 ++depth;
4178 }
4179
4180 /* Create a software table entry if necessary, and mark it
4181 * busy. We might yet fail to insert, but any attempt to
4182 * insert a conflicting filter while we're waiting for the
4183 * firmware must find the busy entry.
4184 */
4185 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4186 if (saved_spec) {
4187 replacing = true;
4188 } else {
4189 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4190 if (!saved_spec) {
4191 rc = -ENOMEM;
4192 goto fail_unlock;
4193 }
4194 *saved_spec = *spec;
4195 }
4196 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4197 EFX_EF10_FILTER_FLAG_BUSY);
4198
4199 spin_unlock_bh(&efx->filter_lock);
4200
4201 /* Pack up the variables needed on completion */
4202 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4203
4204 efx_ef10_filter_push_prep(efx, spec, inbuf,
4205 table->entry[ins_index].handle, replacing);
4206 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4207 MC_CMD_FILTER_OP_OUT_LEN,
4208 efx_ef10_filter_rfs_insert_complete, cookie);
4209
4210 return ins_index;
4211
4212fail_unlock:
4213 spin_unlock_bh(&efx->filter_lock);
4214 return rc;
4215}
4216
4217static void
4218efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4219 int rc, efx_dword_t *outbuf,
4220 size_t outlen_actual)
4221{
4222 struct efx_ef10_filter_table *table = efx->filter_state;
4223 unsigned int ins_index, dmaq_id;
4224 struct efx_filter_spec *spec;
4225 bool replacing;
4226
4227 /* Unpack the cookie */
4228 replacing = cookie >> 31;
4229 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4230 dmaq_id = cookie & 0xffff;
4231
4232 spin_lock_bh(&efx->filter_lock);
4233 spec = efx_ef10_filter_entry_spec(table, ins_index);
4234 if (rc == 0) {
4235 table->entry[ins_index].handle =
4236 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4237 if (replacing)
4238 spec->dmaq_id = dmaq_id;
4239 } else if (!replacing) {
4240 kfree(spec);
4241 spec = NULL;
4242 }
4243 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4244 spin_unlock_bh(&efx->filter_lock);
4245
4246 wake_up_all(&table->waitq);
4247}
4248
4249static void
4250efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4251 unsigned long filter_idx,
4252 int rc, efx_dword_t *outbuf,
4253 size_t outlen_actual);
4254
4255static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4256 unsigned int filter_idx)
4257{
4258 struct efx_ef10_filter_table *table = efx->filter_state;
4259 struct efx_filter_spec *spec =
4260 efx_ef10_filter_entry_spec(table, filter_idx);
4261 MCDI_DECLARE_BUF(inbuf,
4262 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4263 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4264
4265 if (!spec ||
4266 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4267 spec->priority != EFX_FILTER_PRI_HINT ||
4268 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4269 flow_id, filter_idx))
4270 return false;
4271
4272 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4273 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4274 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4275 table->entry[filter_idx].handle);
4276 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4277 efx_ef10_filter_rfs_expire_complete, filter_idx))
4278 return false;
4279
4280 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4281 return true;
4282}
4283
4284static void
4285efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4286 unsigned long filter_idx,
4287 int rc, efx_dword_t *outbuf,
4288 size_t outlen_actual)
4289{
4290 struct efx_ef10_filter_table *table = efx->filter_state;
4291 struct efx_filter_spec *spec =
4292 efx_ef10_filter_entry_spec(table, filter_idx);
4293
4294 spin_lock_bh(&efx->filter_lock);
4295 if (rc == 0) {
4296 kfree(spec);
4297 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4298 }
4299 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4300 wake_up_all(&table->waitq);
4301 spin_unlock_bh(&efx->filter_lock);
4302}
4303
4304#endif /* CONFIG_RFS_ACCEL */
4305
4306static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
4307{
4308 int match_flags = 0;
4309
4310#define MAP_FLAG(gen_flag, mcdi_field) { \
4311 u32 old_mcdi_flags = mcdi_flags; \
4312 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
4313 mcdi_field ## _LBN); \
4314 if (mcdi_flags != old_mcdi_flags) \
4315 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4316 }
4317 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4318 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4319 MAP_FLAG(REM_HOST, SRC_IP);
4320 MAP_FLAG(LOC_HOST, DST_IP);
4321 MAP_FLAG(REM_MAC, SRC_MAC);
4322 MAP_FLAG(REM_PORT, SRC_PORT);
4323 MAP_FLAG(LOC_MAC, DST_MAC);
4324 MAP_FLAG(LOC_PORT, DST_PORT);
4325 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4326 MAP_FLAG(INNER_VID, INNER_VLAN);
4327 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4328 MAP_FLAG(IP_PROTO, IP_PROTO);
4329#undef MAP_FLAG
4330
4331 /* Did we map them all? */
4332 if (mcdi_flags)
4333 return -EINVAL;
4334
4335 return match_flags;
4336}
4337
34813fe2
AR		 4338static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4339{
4340 struct efx_ef10_filter_table *table = efx->filter_state;
4341 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4342
4343 /* See comment in efx_ef10_filter_table_remove() */
4344 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4345 return;
4346
4347 if (!table)
4348 return;
4349
4350 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4351 efx_ef10_filter_del_vlan_internal(efx, vlan);
4352}
4353
7ac0dd9d
AR		 4354static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4355 enum efx_filter_match_flags match_flags)
4356{
4357 unsigned int match_pri;
4358 int mf;
4359
4360 for (match_pri = 0;
4361 match_pri < table->rx_match_count;
4362 match_pri++) {
4363 mf = efx_ef10_filter_match_flags_from_mcdi(
4364 table->rx_match_mcdi_flags[match_pri]);
4365 if (mf == match_flags)
4366 return true;
4367 }
4368
4369 return false;
4370}
4371
8127d661
BH		 4372static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4373{
4374 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4375 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
34813fe2 4376 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e4478ad1 4377 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 4378 unsigned int pd_match_pri, pd_match_count;
4379 struct efx_ef10_filter_table *table;
34813fe2 4380 struct efx_ef10_vlan *vlan;
8127d661
BH		 4381 size_t outlen;
4382 int rc;
4383
dd98708c
EC		 4384 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4385 return -EINVAL;
4386
4387 if (efx->filter_state) /* already probed */
4388 return 0;
4389
8127d661
BH		 4390 table = kzalloc(sizeof(*table), GFP_KERNEL);
4391 if (!table)
4392 return -ENOMEM;
4393
4394 /* Find out which RX filter types are supported, and their priorities */
4395 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4396 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4397 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4398 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4399 &outlen);
4400 if (rc)
4401 goto fail;
4402 pd_match_count = MCDI_VAR_ARRAY_LEN(
4403 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4404 table->rx_match_count = 0;
4405
4406 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4407 u32 mcdi_flags =
4408 MCDI_ARRAY_DWORD(
4409 outbuf,
4410 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4411 pd_match_pri);
4412 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4413 if (rc < 0) {
4414 netif_dbg(efx, probe, efx->net_dev,
4415 "%s: fw flags %#x pri %u not supported in driver\n",
4416 __func__, mcdi_flags, pd_match_pri);
4417 } else {
4418 netif_dbg(efx, probe, efx->net_dev,
4419 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4420 __func__, mcdi_flags, pd_match_pri,
4421 rc, table->rx_match_count);
7ac0dd9d
AR		 4422 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4423 table->rx_match_count++;
8127d661
BH		 4424 }
4425 }
4426
e4478ad1
MH		 4427 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4428 !(efx_ef10_filter_match_supported(table,
4429 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4430 efx_ef10_filter_match_supported(table,
4431 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4432 netif_info(efx, probe, net_dev,
4433 "VLAN filters are not supported in this firmware variant\n");
4434 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4435 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4436 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4437 }
4438
8127d661
BH		 4439 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4440 if (!table->entry) {
4441 rc = -ENOMEM;
4442 goto fail;
4443 }
4444
b071c3a2 4445 table->mc_promisc_last = false;
4a53ea8a
AR		 4446 table->vlan_filter =
4447 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
34813fe2 4448 INIT_LIST_HEAD(&table->vlan_list);
12fb0da4 4449
8127d661
BH		 4450 efx->filter_state = table;
4451 init_waitqueue_head(&table->waitq);
34813fe2
AR		 4452
4453 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4454 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4455 if (rc)
4456 goto fail_add_vlan;
4457 }
4458
8127d661
BH		 4459 return 0;
4460
34813fe2
AR		 4461fail_add_vlan:
4462 efx_ef10_filter_cleanup_vlans(efx);
4463 efx->filter_state = NULL;
8127d661
BH		 4464fail:
4465 kfree(table);
4466 return rc;
4467}
4468
0d322413
EC		 4469/* Caller must hold efx->filter_sem for read if race against
4470 * efx_ef10_filter_table_remove() is possible
4471 */
8127d661
BH		 4472static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4473{
4474 struct efx_ef10_filter_table *table = efx->filter_state;
4475 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4476 struct efx_filter_spec *spec;
4477 unsigned int filter_idx;
4478 bool failed = false;
4479 int rc;
4480
0d322413
EC		 4481 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4482
8127d661
BH		 4483 if (!nic_data->must_restore_filters)
4484 return;
4485
0d322413
EC		 4486 if (!table)
4487 return;
4488
8127d661
BH		 4489 spin_lock_bh(&efx->filter_lock);
4490
4491 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4492 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4493 if (!spec)
4494 continue;
4495
4496 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4497 spin_unlock_bh(&efx->filter_lock);
4498
4499 rc = efx_ef10_filter_push(efx, spec,
4500 &table->entry[filter_idx].handle,
4501 false);
4502 if (rc)
4503 failed = true;
4504
4505 spin_lock_bh(&efx->filter_lock);
4506 if (rc) {
4507 kfree(spec);
4508 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4509 } else {
4510 table->entry[filter_idx].spec &=
4511 ~EFX_EF10_FILTER_FLAG_BUSY;
4512 }
4513 }
4514
4515 spin_unlock_bh(&efx->filter_lock);
4516
4517 if (failed)
4518 netif_err(efx, hw, efx->net_dev,
4519 "unable to restore all filters\n");
4520 else
4521 nic_data->must_restore_filters = false;
4522}
4523
4524static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4525{
4526 struct efx_ef10_filter_table *table = efx->filter_state;
4527 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4528 struct efx_filter_spec *spec;
4529 unsigned int filter_idx;
4530 int rc;
4531
34813fe2 4532 efx_ef10_filter_cleanup_vlans(efx);
0d322413 4533 efx->filter_state = NULL;
dd98708c
EC		 4534 /* If we were called without locking, then it's not safe to free
4535 * the table as others might be using it. So we just WARN, leak
4536 * the memory, and potentially get an inconsistent filter table
4537 * state.
4538 * This should never actually happen.
4539 */
4540 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4541 return;
4542
0d322413
EC		 4543 if (!table)
4544 return;
4545
8127d661
BH		 4546 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4547 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4548 if (!spec)
4549 continue;
4550
4551 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4552 efx_ef10_filter_is_exclusive(spec) ?
4553 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4554 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4555 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4556 table->entry[filter_idx].handle);
e65a5109
BK		 4557 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4558 sizeof(inbuf), NULL, 0, NULL);
48ce5634 4559 if (rc)
e65a5109
BK		 4560 netif_info(efx, drv, efx->net_dev,
4561 "%s: filter %04x remove failed\n",
4562 __func__, filter_idx);
8127d661
BH		 4563 kfree(spec);
4564 }
4565
4566 vfree(table->entry);
4567 kfree(table);
4568}
4569
6a37958b
AR		 4570static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4571{
4572 struct efx_ef10_filter_table *table = efx->filter_state;
4573 unsigned int filter_idx;
4574
4575 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4576 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4577 if (!table->entry[filter_idx].spec)
4578 netif_dbg(efx, drv, efx->net_dev,
4579 "marked null spec old %04x:%04x\n", *id,
4580 filter_idx);
4581 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4582 *id = EFX_EF10_FILTER_ID_INVALID;
e65a5109 4583 }
6a37958b
AR		 4584}
4585
b3a3c03c
AR		 4586/* Mark old per-VLAN filters that may need to be removed */
4587static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4588 struct efx_ef10_filter_vlan *vlan)
8127d661
BH		 4589{
4590 struct efx_ef10_filter_table *table = efx->filter_state;
6a37958b 4591 unsigned int i;
8127d661 4592
12fb0da4 4593 for (i = 0; i < table->dev_uc_count; i++)
dc3273e0 4594 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
12fb0da4 4595 for (i = 0; i < table->dev_mc_count; i++)
dc3273e0
AR		 4596 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4597 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4598 efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4599 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
b3a3c03c
AR		 4600}
4601
34813fe2
AR		 4602/* Mark old filters that may need to be removed.
4603 * Caller must hold efx->filter_sem for read if race against
4604 * efx_ef10_filter_table_remove() is possible
4605 */
b3a3c03c
AR		 4606static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4607{
4608 struct efx_ef10_filter_table *table = efx->filter_state;
34813fe2 4609 struct efx_ef10_filter_vlan *vlan;
b3a3c03c
AR		 4610
4611 spin_lock_bh(&efx->filter_lock);
34813fe2
AR		 4612 list_for_each_entry(vlan, &table->vlan_list, list)
4613 _efx_ef10_filter_vlan_mark_old(efx, vlan);
8127d661 4614 spin_unlock_bh(&efx->filter_lock);
822b96f8
DP		 4615}
4616
afa4ce12 4617static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4618{
4619 struct efx_ef10_filter_table *table = efx->filter_state;
4620 struct net_device *net_dev = efx->net_dev;
4621 struct netdev_hw_addr *uc;
12fb0da4 4622 int addr_count;
822b96f8 4623 unsigned int i;
8127d661 4624
12fb0da4 4625 addr_count = netdev_uc_count(net_dev);
afa4ce12 4626 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
12fb0da4 4627 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 4628 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4629 i = 1;
4630 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4 4631 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
afa4ce12 4632 table->uc_promisc = true;
12fb0da4
EC		 4633 break;
4634 }
822b96f8
DP		 4635 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4636 i++;
4637 }
4638}
4639
afa4ce12 4640static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4641{
4642 struct efx_ef10_filter_table *table = efx->filter_state;
4643 struct net_device *net_dev = efx->net_dev;
4644 struct netdev_hw_addr *mc;
ab8b1f7c 4645 unsigned int i, addr_count;
822b96f8 4646
afa4ce12 4647 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
ab8b1f7c 4648
12fb0da4
EC		 4649 addr_count = netdev_mc_count(net_dev);
4650 i = 0;
ab8b1f7c 4651 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4 4652 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
afa4ce12 4653 table->mc_promisc = true;
12fb0da4
EC		 4654 break;
4655 }
ab8b1f7c
DP		 4656 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4657 i++;
8127d661 4658 }
12fb0da4
EC		 4659
4660 table->dev_mc_count = i;
822b96f8 4661}
8127d661 4662
12fb0da4 4663static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
b3a3c03c
AR		 4664 struct efx_ef10_filter_vlan *vlan,
4665 bool multicast, bool rollback)
822b96f8
DP		 4666{
4667 struct efx_ef10_filter_table *table = efx->filter_state;
4668 struct efx_ef10_dev_addr *addr_list;
f1c2ef40 4669 enum efx_filter_flags filter_flags;
822b96f8 4670 struct efx_filter_spec spec;
12fb0da4
EC		 4671 u8 baddr[ETH_ALEN];
4672 unsigned int i, j;
4673 int addr_count;
dc3273e0 4674 u16 *ids;
822b96f8
DP		 4675 int rc;
4676
4677 if (multicast) {
4678 addr_list = table->dev_mc_list;
12fb0da4 4679 addr_count = table->dev_mc_count;
dc3273e0 4680 ids = vlan->mc;
822b96f8
DP		 4681 } else {
4682 addr_list = table->dev_uc_list;
12fb0da4 4683 addr_count = table->dev_uc_count;
dc3273e0 4684 ids = vlan->uc;
8127d661
BH		 4685 }
4686
f1c2ef40
BK		 4687 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4688
822b96f8 4689 /* Insert/renew filters */
12fb0da4 4690 for (i = 0; i < addr_count; i++) {
f1c2ef40 4691 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
b3a3c03c 4692 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
b6f568e2
JC		 4693 rc = efx_ef10_filter_insert(efx, &spec, true);
4694 if (rc < 0) {
12fb0da4
EC		 4695 if (rollback) {
4696 netif_info(efx, drv, efx->net_dev,
4697 "efx_ef10_filter_insert failed rc=%d\n",
4698 rc);
4699 /* Fall back to promiscuous */
4700 for (j = 0; j < i; j++) {
12fb0da4
EC		 4701 efx_ef10_filter_remove_unsafe(
4702 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4703 ids[j]);
4704 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4705 }
4706 return rc;
4707 } else {
4708 /* mark as not inserted, and carry on */
4709 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 4710 }
8127d661 4711 }
dc3273e0 4712 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 4713 }
822b96f8 4714
12fb0da4
EC		 4715 if (multicast && rollback) {
4716 /* Also need an Ethernet broadcast filter */
f1c2ef40 4717 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4 4718 eth_broadcast_addr(baddr);
b3a3c03c 4719 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
8127d661 4720 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 4721 if (rc < 0) {
822b96f8 4722 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 4723 "Broadcast filter insert failed rc=%d\n", rc);
4724 /* Fall back to promiscuous */
4725 for (j = 0; j < i; j++) {
12fb0da4
EC		 4726 efx_ef10_filter_remove_unsafe(
4727 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4728 ids[j]);
4729 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4730 }
4731 return rc;
4732 } else {
dc3273e0 4733 EFX_WARN_ON_PARANOID(vlan->bcast !=
6a37958b 4734 EFX_EF10_FILTER_ID_INVALID);
dc3273e0 4735 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4 4736 }
8127d661 4737 }
12fb0da4
EC		 4738
4739 return 0;
4740}
4741
b3a3c03c
AR		 4742static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4743 struct efx_ef10_filter_vlan *vlan,
4744 bool multicast, bool rollback)
12fb0da4 4745{
12fb0da4 4746 struct efx_ef10_nic_data *nic_data = efx->nic_data;
f1c2ef40 4747 enum efx_filter_flags filter_flags;
12fb0da4
EC		 4748 struct efx_filter_spec spec;
4749 u8 baddr[ETH_ALEN];
4750 int rc;
4751
f1c2ef40
BK		 4752 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4753
4754 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4
EC		 4755
4756 if (multicast)
4757 efx_filter_set_mc_def(&spec);
4758 else
4759 efx_filter_set_uc_def(&spec);
4760
b3a3c03c
AR		 4761 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4762 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4763
12fb0da4
EC		 4764 rc = efx_ef10_filter_insert(efx, &spec, true);
4765 if (rc < 0) {
09a04204
BK		 4766 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4767 efx->net_dev,
4768 "%scast mismatch filter insert failed rc=%d\n",
4769 multicast ? "Multi" : "Uni", rc);
12fb0da4 4770 } else if (multicast) {
dc3273e0
AR		 4771 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4772 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 4773 if (!nic_data->workaround_26807) {
4774 /* Also need an Ethernet broadcast filter */
4775 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
f1c2ef40 4776 filter_flags, 0);
12fb0da4 4777 eth_broadcast_addr(baddr);
b3a3c03c 4778 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
12fb0da4
EC		 4779 rc = efx_ef10_filter_insert(efx, &spec, true);
4780 if (rc < 0) {
4781 netif_warn(efx, drv, efx->net_dev,
4782 "Broadcast filter insert failed rc=%d\n",
4783 rc);
4784 if (rollback) {
4785 /* Roll back the mc_def filter */
4786 efx_ef10_filter_remove_unsafe(
4787 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4788 vlan->mcdef);
4789 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4790 return rc;
4791 }
4792 } else {
dc3273e0 4793 EFX_WARN_ON_PARANOID(vlan->bcast !=
6a37958b 4794 EFX_EF10_FILTER_ID_INVALID);
dc3273e0 4795 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 4796 }
4797 }
4798 rc = 0;
4799 } else {
dc3273e0
AR		 4800 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4801 vlan->ucdef = rc;
12fb0da4
EC		 4802 rc = 0;
4803 }
4804 return rc;
822b96f8
DP		 4805}
4806
4807/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4808 * flag or removes these filters, we don't need to hold the filter_lock while
4809 * scanning for these filters.
4810 */
4811static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4812{
4813 struct efx_ef10_filter_table *table = efx->filter_state;
e65a5109
BK		 4814 int remove_failed = 0;
4815 int remove_noent = 0;
4816 int rc;
822b96f8 4817 int i;
8127d661 4818
8127d661
BH		 4819 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4820 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 4821 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
e65a5109
BK		 4822 rc = efx_ef10_filter_remove_internal(efx,
4823 1U << EFX_FILTER_PRI_AUTO, i, true);
4824 if (rc == -ENOENT)
4825 remove_noent++;
4826 else if (rc)
4827 remove_failed++;
8127d661
BH		 4828 }
4829 }
e65a5109
BK		 4830
4831 if (remove_failed)
4832 netif_info(efx, drv, efx->net_dev,
4833 "%s: failed to remove %d filters\n",
4834 __func__, remove_failed);
4835 if (remove_noent)
4836 netif_info(efx, drv, efx->net_dev,
4837 "%s: failed to remove %d non-existent filters\n",
4838 __func__, remove_noent);
8127d661
BH		 4839}
4840
7a186f47
DP		 4841static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4842{
4843 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4844 u8 mac_old[ETH_ALEN];
4845 int rc, rc2;
4846
4847 /* Only reconfigure a PF-created vport */
4848 if (is_zero_ether_addr(nic_data->vport_mac))
4849 return 0;
4850
4851 efx_device_detach_sync(efx);
4852 efx_net_stop(efx->net_dev);
4853 down_write(&efx->filter_sem);
4854 efx_ef10_filter_table_remove(efx);
4855 up_write(&efx->filter_sem);
4856
4857 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4858 if (rc)
4859 goto restore_filters;
4860
4861 ether_addr_copy(mac_old, nic_data->vport_mac);
4862 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4863 nic_data->vport_mac);
4864 if (rc)
4865 goto restore_vadaptor;
4866
4867 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4868 efx->net_dev->dev_addr);
4869 if (!rc) {
4870 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4871 } else {
4872 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4873 if (rc2) {
4874 /* Failed to add original MAC, so clear vport_mac */
4875 eth_zero_addr(nic_data->vport_mac);
4876 goto reset_nic;
4877 }
4878 }
4879
4880restore_vadaptor:
4881 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4882 if (rc2)
4883 goto reset_nic;
4884restore_filters:
4885 down_write(&efx->filter_sem);
4886 rc2 = efx_ef10_filter_table_probe(efx);
4887 up_write(&efx->filter_sem);
4888 if (rc2)
4889 goto reset_nic;
4890
4891 rc2 = efx_net_open(efx->net_dev);
4892 if (rc2)
4893 goto reset_nic;
4894
4895 netif_device_attach(efx->net_dev);
4896
4897 return rc;
4898
4899reset_nic:
4900 netif_err(efx, drv, efx->net_dev,
4901 "Failed to restore when changing MAC address - scheduling reset\n");
4902 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4903
4904 return rc ? rc : rc2;
4905}
4906
822b96f8
DP		 4907/* Caller must hold efx->filter_sem for read if race against
4908 * efx_ef10_filter_table_remove() is possible
4909 */
34813fe2
AR		 4910static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4911 struct efx_ef10_filter_vlan *vlan)
822b96f8
DP		 4912{
4913 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 4914 struct efx_ef10_nic_data *nic_data = efx->nic_data;
b3a3c03c 4915
4a53ea8a
AR		 4916 /* Do not install unspecified VID if VLAN filtering is enabled.
4917 * Do not install all specified VIDs if VLAN filtering is disabled.
4918 */
4919 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4920 return;
4921
12fb0da4 4922 /* Insert/renew unicast filters */
afa4ce12 4923 if (table->uc_promisc) {
b3a3c03c
AR		 4924 efx_ef10_filter_insert_def(efx, vlan, false, false);
4925 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
12fb0da4
EC		 4926 } else {
4927 /* If any of the filters failed to insert, fall back to
4928 * promiscuous mode - add in the uc_def filter. But keep
4929 * our individual unicast filters.
4930 */
b3a3c03c
AR		 4931 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4932 efx_ef10_filter_insert_def(efx, vlan, false, false);
12fb0da4 4933 }
ab8b1f7c 4934
12fb0da4 4935 /* Insert/renew multicast filters */
ab8b1f7c
DP		 4936 /* If changing promiscuous state with cascaded multicast filters, remove
4937 * old filters first, so that packets are dropped rather than duplicated
4938 */
afa4ce12
AR		 4939 if (nic_data->workaround_26807 &&
4940 table->mc_promisc_last != table->mc_promisc)
ab8b1f7c 4941 efx_ef10_filter_remove_old(efx);
afa4ce12 4942 if (table->mc_promisc) {
12fb0da4
EC		 4943 if (nic_data->workaround_26807) {
4944 /* If we failed to insert promiscuous filters, rollback
4945 * and fall back to individual multicast filters
4946 */
b3a3c03c 4947 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
12fb0da4
EC		 4948 /* Changing promisc state, so remove old filters */
4949 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 4950 efx_ef10_filter_insert_addr_list(efx, vlan,
4951 true, false);
12fb0da4
EC		 4952 }
4953 } else {
4954 /* If we failed to insert promiscuous filters, don't
4955 * rollback. Regardless, also insert the mc_list
4956 */
b3a3c03c
AR		 4957 efx_ef10_filter_insert_def(efx, vlan, true, false);
4958 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
12fb0da4
EC		 4959 }
4960 } else {
4961 /* If any filters failed to insert, rollback and fall back to
4962 * promiscuous mode - mc_def filter and maybe broadcast. If
4963 * that fails, roll back again and insert as many of our
4964 * individual multicast filters as we can.
4965 */
b3a3c03c 4966 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
12fb0da4
EC		 4967 /* Changing promisc state, so remove old filters */
4968 if (nic_data->workaround_26807)
4969 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 4970 if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4971 efx_ef10_filter_insert_addr_list(efx, vlan,
4972 true, false);
12fb0da4
EC		 4973 }
4974 }
34813fe2
AR		 4975}
4976
4977/* Caller must hold efx->filter_sem for read if race against
4978 * efx_ef10_filter_table_remove() is possible
4979 */
4980static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4981{
4982 struct efx_ef10_filter_table *table = efx->filter_state;
4983 struct net_device *net_dev = efx->net_dev;
4984 struct efx_ef10_filter_vlan *vlan;
4a53ea8a 4985 bool vlan_filter;
34813fe2
AR		 4986
4987 if (!efx_dev_registered(efx))
4988 return;
4989
4990 if (!table)
4991 return;
4992
4993 efx_ef10_filter_mark_old(efx);
4994
4995 /* Copy/convert the address lists; add the primary station
4996 * address and broadcast address
4997 */
4998 netif_addr_lock_bh(net_dev);
4999 efx_ef10_filter_uc_addr_list(efx);
5000 efx_ef10_filter_mc_addr_list(efx);
5001 netif_addr_unlock_bh(net_dev);
5002
4a53ea8a
AR		 5003 /* If VLAN filtering changes, all old filters are finally removed.
5004 * Do it in advance to avoid conflicts for unicast untagged and
5005 * VLAN 0 tagged filters.
5006 */
5007 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5008 if (table->vlan_filter != vlan_filter) {
5009 table->vlan_filter = vlan_filter;
5010 efx_ef10_filter_remove_old(efx);
5011 }
5012
34813fe2
AR		 5013 list_for_each_entry(vlan, &table->vlan_list, list)
5014 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
822b96f8
DP		 5015
5016 efx_ef10_filter_remove_old(efx);
afa4ce12 5017 table->mc_promisc_last = table->mc_promisc;
822b96f8
DP		 5018}
5019
34813fe2
AR		 5020static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5021{
5022 struct efx_ef10_filter_table *table = efx->filter_state;
5023 struct efx_ef10_filter_vlan *vlan;
5024
5025 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5026
5027 list_for_each_entry(vlan, &table->vlan_list, list) {
5028 if (vlan->vid == vid)
5029 return vlan;
5030 }
5031
5032 return NULL;
5033}
5034
5035static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5036{
5037 struct efx_ef10_filter_table *table = efx->filter_state;
5038 struct efx_ef10_filter_vlan *vlan;
5039 unsigned int i;
5040
5041 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5042 return -EINVAL;
5043
5044 vlan = efx_ef10_filter_find_vlan(efx, vid);
5045 if (WARN_ON(vlan)) {
5046 netif_err(efx, drv, efx->net_dev,
5047 "VLAN %u already added\n", vid);
5048 return -EALREADY;
5049 }
5050
5051 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5052 if (!vlan)
5053 return -ENOMEM;
5054
5055 vlan->vid = vid;
5056
5057 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5058 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5059 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5060 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5061 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
5062 vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
5063 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
5064
5065 list_add_tail(&vlan->list, &table->vlan_list);
5066
5067 if (efx_dev_registered(efx))
5068 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5069
5070 return 0;
5071}
5072
5073static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5074 struct efx_ef10_filter_vlan *vlan)
5075{
5076 unsigned int i;
5077
5078 /* See comment in efx_ef10_filter_table_remove() */
5079 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5080 return;
5081
5082 list_del(&vlan->list);
5083
8c915620 5084 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
34813fe2 5085 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 5086 vlan->uc[i]);
5087 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
34813fe2 5088 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 5089 vlan->mc[i]);
5090 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
5091 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
5092 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
34813fe2
AR		 5093
5094 kfree(vlan);
5095}
5096
5097static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5098{
5099 struct efx_ef10_filter_vlan *vlan;
5100
5101 /* See comment in efx_ef10_filter_table_remove() */
5102 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5103 return;
5104
5105 vlan = efx_ef10_filter_find_vlan(efx, vid);
5106 if (!vlan) {
5107 netif_err(efx, drv, efx->net_dev,
5108 "VLAN %u not found in filter state\n", vid);
5109 return;
5110 }
5111
5112 efx_ef10_filter_del_vlan_internal(efx, vlan);
5113}
5114
910c8789
SS		 5115static int efx_ef10_set_mac_address(struct efx_nic *efx)
5116{
5117 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5118 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5119 bool was_enabled = efx->port_enabled;
5120 int rc;
5121
5122 efx_device_detach_sync(efx);
5123 efx_net_stop(efx->net_dev);
d248953a
MH		 5124
5125 mutex_lock(&efx->mac_lock);
910c8789
SS		 5126 down_write(&efx->filter_sem);
5127 efx_ef10_filter_table_remove(efx);
5128
5129 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5130 efx->net_dev->dev_addr);
5131 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5132 nic_data->vport_id);
535a6177
DP		 5133 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5134 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 5135
5136 efx_ef10_filter_table_probe(efx);
5137 up_write(&efx->filter_sem);
d248953a
MH		 5138 mutex_unlock(&efx->mac_lock);
5139
910c8789
SS		 5140 if (was_enabled)
5141 efx_net_open(efx->net_dev);
5142 netif_device_attach(efx->net_dev);
5143
9e9f665a
DP		 5144#ifdef CONFIG_SFC_SRIOV
5145 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 5146 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5147
9e9f665a
DP		 5148 if (rc == -EPERM) {
5149 struct efx_nic *efx_pf;
910c8789 5150
9e9f665a
DP		 5151 /* Switch to PF and change MAC address on vport */
5152 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 5153
9e9f665a
DP		 5154 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5155 nic_data->vf_index,
5156 efx->net_dev->dev_addr);
5157 } else if (!rc) {
910c8789
SS		 5158 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5159 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5160 unsigned int i;
5161
9e9f665a
DP		 5162 /* MAC address successfully changed by VF (with MAC
5163 * spoofing) so update the parent PF if possible.
5164 */
910c8789
SS		 5165 for (i = 0; i < efx_pf->vf_count; ++i) {
5166 struct ef10_vf *vf = nic_data->vf + i;
5167
5168 if (vf->efx == efx) {
5169 ether_addr_copy(vf->mac,
5170 efx->net_dev->dev_addr);
5171 return 0;
5172 }
5173 }
5174 }
9e9f665a 5175 } else
910c8789 5176#endif
9e9f665a
DP		 5177 if (rc == -EPERM) {
5178 netif_err(efx, drv, efx->net_dev,
5179 "Cannot change MAC address; use sfboot to enable"
5180 " mac-spoofing on this interface\n");
7a186f47
DP		 5181 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5182 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5183 * fall-back to the method of changing the MAC address on the
5184 * vport. This only applies to PFs because such versions of
5185 * MCFW do not support VFs.
5186 */
5187 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 5188 } else {
5189 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5190 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 5191 }
5192
910c8789
SS		 5193 return rc;
5194}
5195
8127d661
BH		 5196static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5197{
5198 efx_ef10_filter_sync_rx_mode(efx);
5199
5200 return efx_mcdi_set_mac(efx);
5201}
5202
862f894c
SS		 5203static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5204{
5205 efx_ef10_filter_sync_rx_mode(efx);
5206
5207 return 0;
5208}
5209
74cd60a4
JC		 5210static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5211{
5212 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5213
5214 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5215 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5216 NULL, 0, NULL);
5217}
5218
5219/* MC BISTs follow a different poll mechanism to phy BISTs.
5220 * The BIST is done in the poll handler on the MC, and the MCDI command
5221 * will block until the BIST is done.
5222 */
5223static int efx_ef10_poll_bist(struct efx_nic *efx)
5224{
5225 int rc;
5226 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5227 size_t outlen;
5228 u32 result;
5229
5230 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5231 outbuf, sizeof(outbuf), &outlen);
5232 if (rc != 0)
5233 return rc;
5234
5235 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5236 return -EIO;
5237
5238 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5239 switch (result) {
5240 case MC_CMD_POLL_BIST_PASSED:
5241 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5242 return 0;
5243 case MC_CMD_POLL_BIST_TIMEOUT:
5244 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5245 return -EIO;
5246 case MC_CMD_POLL_BIST_FAILED:
5247 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5248 return -EIO;
5249 default:
5250 netif_err(efx, hw, efx->net_dev,
5251 "BIST returned unknown result %u", result);
5252 return -EIO;
5253 }
5254}
5255
5256static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5257{
5258 int rc;
5259
5260 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5261
5262 rc = efx_ef10_start_bist(efx, bist_type);
5263 if (rc != 0)
5264 return rc;
5265
5266 return efx_ef10_poll_bist(efx);
5267}
5268
5269static int
5270efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5271{
5272 int rc, rc2;
5273
5274 efx_reset_down(efx, RESET_TYPE_WORLD);
5275
5276 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5277 NULL, 0, NULL, 0, NULL);
5278 if (rc != 0)
5279 goto out;
5280
5281 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5282 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5283
5284 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5285
5286out:
27324820
DP		 5287 if (rc == -EPERM)
5288 rc = 0;
74cd60a4
JC		 5289 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5290 return rc ? rc : rc2;
5291}
5292
8127d661
BH		 5293#ifdef CONFIG_SFC_MTD
5294
5295struct efx_ef10_nvram_type_info {
5296 u16 type, type_mask;
5297 u8 port;
5298 const char *name;
5299};
5300
5301static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5302 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5303 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5304 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5305 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5306 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5307 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5308 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5309 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5310 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 5311 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 5312 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5313};
5314
5315static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5316 struct efx_mcdi_mtd_partition *part,
5317 unsigned int type)
5318{
5319 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5320 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5321 const struct efx_ef10_nvram_type_info *info;
5322 size_t size, erase_size, outlen;
5323 bool protected;
5324 int rc;
5325
5326 for (info = efx_ef10_nvram_types; ; info++) {
5327 if (info ==
5328 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5329 return -ENODEV;
5330 if ((type & ~info->type_mask) == info->type)
5331 break;
5332 }
5333 if (info->port != efx_port_num(efx))
5334 return -ENODEV;
5335
5336 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5337 if (rc)
5338 return rc;
5339 if (protected)
5340 return -ENODEV; /* hide it */
5341
5342 part->nvram_type = type;
5343
5344 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5345 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5346 outbuf, sizeof(outbuf), &outlen);
5347 if (rc)
5348 return rc;
5349 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5350 return -EIO;
5351 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5352 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5353 part->fw_subtype = MCDI_DWORD(outbuf,
5354 NVRAM_METADATA_OUT_SUBTYPE);
5355
5356 part->common.dev_type_name = "EF10 NVRAM manager";
5357 part->common.type_name = info->name;
5358
5359 part->common.mtd.type = MTD_NORFLASH;
5360 part->common.mtd.flags = MTD_CAP_NORFLASH;
5361 part->common.mtd.size = size;
5362 part->common.mtd.erasesize = erase_size;
5363
5364 return 0;
5365}
5366
5367static int efx_ef10_mtd_probe(struct efx_nic *efx)
5368{
5369 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5370 struct efx_mcdi_mtd_partition *parts;
5371 size_t outlen, n_parts_total, i, n_parts;
5372 unsigned int type;
5373 int rc;
5374
5375 ASSERT_RTNL();
5376
5377 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5378 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5379 outbuf, sizeof(outbuf), &outlen);
5380 if (rc)
5381 return rc;
5382 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5383 return -EIO;
5384
5385 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5386 if (n_parts_total >
5387 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5388 return -EIO;
5389
5390 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5391 if (!parts)
5392 return -ENOMEM;
5393
5394 n_parts = 0;
5395 for (i = 0; i < n_parts_total; i++) {
5396 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5397 i);
5398 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5399 if (rc == 0)
5400 n_parts++;
5401 else if (rc != -ENODEV)
5402 goto fail;
5403 }
5404
5405 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5406fail:
5407 if (rc)
5408 kfree(parts);
5409 return rc;
5410}
5411
5412#endif /* CONFIG_SFC_MTD */
5413
5414static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5415{
5416 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5417}
5418
02246a7f
SS		 5419static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5420 u32 host_time) {}
5421
bd9a265d
JC		 5422static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5423 bool temp)
5424{
5425 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5426 int rc;
5427
5428 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5429 channel->sync_events_state == SYNC_EVENTS_VALID ||
5430 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5431 return 0;
5432 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5433
5434 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5435 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5436 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5437 channel->channel);
5438
5439 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5440 inbuf, sizeof(inbuf), NULL, 0, NULL);
5441
5442 if (rc != 0)
5443 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5444 SYNC_EVENTS_DISABLED;
5445
5446 return rc;
5447}
5448
5449static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5450 bool temp)
5451{
5452 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5453 int rc;
5454
5455 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5456 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5457 return 0;
5458 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5459 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5460 return 0;
5461 }
5462 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5463 SYNC_EVENTS_DISABLED;
5464
5465 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5466 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5467 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5468 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5469 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5470 channel->channel);
5471
5472 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5473 inbuf, sizeof(inbuf), NULL, 0, NULL);
5474
5475 return rc;
5476}
5477
5478static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5479 bool temp)
5480{
5481 int (*set)(struct efx_channel *channel, bool temp);
5482 struct efx_channel *channel;
5483
5484 set = en ?
5485 efx_ef10_rx_enable_timestamping :
5486 efx_ef10_rx_disable_timestamping;
5487
5488 efx_for_each_channel(channel, efx) {
5489 int rc = set(channel, temp);
5490 if (en && rc != 0) {
5491 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5492 return rc;
5493 }
5494 }
5495
5496 return 0;
5497}
5498
02246a7f
SS		 5499static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5500 struct hwtstamp_config *init)
5501{
5502 return -EOPNOTSUPP;
5503}
5504
bd9a265d
JC		 5505static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5506 struct hwtstamp_config *init)
5507{
5508 int rc;
5509
5510 switch (init->rx_filter) {
5511 case HWTSTAMP_FILTER_NONE:
5512 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5513 /* if TX timestamping is still requested then leave PTP on */
5514 return efx_ptp_change_mode(efx,
5515 init->tx_type != HWTSTAMP_TX_OFF, 0);
5516 case HWTSTAMP_FILTER_ALL:
5517 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5518 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5519 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5520 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5521 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5523 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5524 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5525 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5526 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5527 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5528 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5529 init->rx_filter = HWTSTAMP_FILTER_ALL;
5530 rc = efx_ptp_change_mode(efx, true, 0);
5531 if (!rc)
5532 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5533 if (rc)
5534 efx_ptp_change_mode(efx, false, 0);
5535 return rc;
5536 default:
5537 return -ERANGE;
5538 }
5539}
5540
08a7b29b
BK		 5541static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
5542 struct netdev_phys_item_id *ppid)
5543{
5544 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5545
5546 if (!is_valid_ether_addr(nic_data->port_id))
5547 return -EOPNOTSUPP;
5548
5549 ppid->id_len = ETH_ALEN;
5550 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
5551
5552 return 0;
5553}
5554
4a53ea8a
AR		 5555static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5556{
5557 if (proto != htons(ETH_P_8021Q))
5558 return -EINVAL;
5559
5560 return efx_ef10_add_vlan(efx, vid);
5561}
5562
5563static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5564{
5565 if (proto != htons(ETH_P_8021Q))
5566 return -EINVAL;
5567
5568 return efx_ef10_del_vlan(efx, vid);
5569}
5570
100a9db5
AR		 5571#define EF10_OFFLOAD_FEATURES \
5572 (NETIF_F_IP_CSUM | \
4a53ea8a 5573 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 5574 NETIF_F_IPV6_CSUM | \
5575 NETIF_F_RXHASH | \
5576 NETIF_F_NTUPLE)
5577
02246a7f 5578const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 5579 .is_vf = true,
02246a7f
SS		 5580 .mem_bar = EFX_MEM_VF_BAR,
5581 .mem_map_size = efx_ef10_mem_map_size,
5582 .probe = efx_ef10_probe_vf,
5583 .remove = efx_ef10_remove,
5584 .dimension_resources = efx_ef10_dimension_resources,
5585 .init = efx_ef10_init_nic,
5586 .fini = efx_port_dummy_op_void,
087e9025 5587 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 5588 .map_reset_flags = efx_ef10_map_reset_flags,
5589 .reset = efx_ef10_reset,
5590 .probe_port = efx_mcdi_port_probe,
5591 .remove_port = efx_mcdi_port_remove,
5592 .fini_dmaq = efx_ef10_fini_dmaq,
5593 .prepare_flr = efx_ef10_prepare_flr,
5594 .finish_flr = efx_port_dummy_op_void,
5595 .describe_stats = efx_ef10_describe_stats,
d7788196 5596 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 5597 .start_stats = efx_port_dummy_op_void,
5598 .pull_stats = efx_port_dummy_op_void,
5599 .stop_stats = efx_port_dummy_op_void,
5600 .set_id_led = efx_mcdi_set_id_led,
5601 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 5602 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 5603 .check_mac_fault = efx_mcdi_mac_check_fault,
5604 .reconfigure_port = efx_mcdi_port_reconfigure,
5605 .get_wol = efx_ef10_get_wol_vf,
5606 .set_wol = efx_ef10_set_wol_vf,
5607 .resume_wol = efx_port_dummy_op_void,
5608 .mcdi_request = efx_ef10_mcdi_request,
5609 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5610 .mcdi_read_response = efx_ef10_mcdi_read_response,
5611 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5612 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 5613 .irq_enable_master = efx_port_dummy_op_void,
5614 .irq_test_generate = efx_ef10_irq_test_generate,
5615 .irq_disable_non_ev = efx_port_dummy_op_void,
5616 .irq_handle_msi = efx_ef10_msi_interrupt,
5617 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5618 .tx_probe = efx_ef10_tx_probe,
5619 .tx_init = efx_ef10_tx_init,
5620 .tx_remove = efx_ef10_tx_remove,
5621 .tx_write = efx_ef10_tx_write,
e9117e50 5622 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 5623 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 5624 .rx_probe = efx_ef10_rx_probe,
5625 .rx_init = efx_ef10_rx_init,
5626 .rx_remove = efx_ef10_rx_remove,
5627 .rx_write = efx_ef10_rx_write,
5628 .rx_defer_refill = efx_ef10_rx_defer_refill,
5629 .ev_probe = efx_ef10_ev_probe,
5630 .ev_init = efx_ef10_ev_init,
5631 .ev_fini = efx_ef10_ev_fini,
5632 .ev_remove = efx_ef10_ev_remove,
5633 .ev_process = efx_ef10_ev_process,
5634 .ev_read_ack = efx_ef10_ev_read_ack,
5635 .ev_test_generate = efx_ef10_ev_test_generate,
5636 .filter_table_probe = efx_ef10_filter_table_probe,
5637 .filter_table_restore = efx_ef10_filter_table_restore,
5638 .filter_table_remove = efx_ef10_filter_table_remove,
5639 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5640 .filter_insert = efx_ef10_filter_insert,
5641 .filter_remove_safe = efx_ef10_filter_remove_safe,
5642 .filter_get_safe = efx_ef10_filter_get_safe,
5643 .filter_clear_rx = efx_ef10_filter_clear_rx,
5644 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5645 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5646 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5647#ifdef CONFIG_RFS_ACCEL
5648 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5649 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5650#endif
5651#ifdef CONFIG_SFC_MTD
5652 .mtd_probe = efx_port_dummy_op_int,
5653#endif
5654 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5655 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 5656 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5657 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 5658#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 5659 .vswitching_probe = efx_ef10_vswitching_probe_vf,
5660 .vswitching_restore = efx_ef10_vswitching_restore_vf,
5661 .vswitching_remove = efx_ef10_vswitching_remove_vf,
02246a7f 5662#endif
0d5e0fbb 5663 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 5664 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 5665
08a7b29b 5666 .get_phys_port_id = efx_ef10_get_phys_port_id,
02246a7f
SS		 5667 .revision = EFX_REV_HUNT_A0,
5668 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5669 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5670 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5671 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5672 .can_rx_scatter = true,
5673 .always_rx_scatter = true,
5674 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5675 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 5676 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f
SS		 5677 .mcdi_max_ver = 2,
5678 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5679 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5680 1 << HWTSTAMP_FILTER_ALL,
5681};
5682
8127d661 5683const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 5684 .is_vf = false,
02246a7f 5685 .mem_bar = EFX_MEM_BAR,
8127d661 5686 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 5687 .probe = efx_ef10_probe_pf,
8127d661
BH		 5688 .remove = efx_ef10_remove,
5689 .dimension_resources = efx_ef10_dimension_resources,
5690 .init = efx_ef10_init_nic,
5691 .fini = efx_port_dummy_op_void,
087e9025 5692 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 5693 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 5694 .reset = efx_ef10_reset,
8127d661
BH		 5695 .probe_port = efx_mcdi_port_probe,
5696 .remove_port = efx_mcdi_port_remove,
5697 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 5698 .prepare_flr = efx_ef10_prepare_flr,
5699 .finish_flr = efx_port_dummy_op_void,
8127d661 5700 .describe_stats = efx_ef10_describe_stats,
d7788196 5701 .update_stats = efx_ef10_update_stats_pf,
8127d661 5702 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 5703 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 5704 .stop_stats = efx_mcdi_mac_stop_stats,
5705 .set_id_led = efx_mcdi_set_id_led,
5706 .push_irq_moderation = efx_ef10_push_irq_moderation,
5707 .reconfigure_mac = efx_ef10_mac_reconfigure,
5708 .check_mac_fault = efx_mcdi_mac_check_fault,
5709 .reconfigure_port = efx_mcdi_port_reconfigure,
5710 .get_wol = efx_ef10_get_wol,
5711 .set_wol = efx_ef10_set_wol,
5712 .resume_wol = efx_port_dummy_op_void,
74cd60a4 5713 .test_chip = efx_ef10_test_chip,
8127d661
BH		 5714 .test_nvram = efx_mcdi_nvram_test_all,
5715 .mcdi_request = efx_ef10_mcdi_request,
5716 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5717 .mcdi_read_response = efx_ef10_mcdi_read_response,
5718 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5719 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 5720 .irq_enable_master = efx_port_dummy_op_void,
5721 .irq_test_generate = efx_ef10_irq_test_generate,
5722 .irq_disable_non_ev = efx_port_dummy_op_void,
5723 .irq_handle_msi = efx_ef10_msi_interrupt,
5724 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5725 .tx_probe = efx_ef10_tx_probe,
5726 .tx_init = efx_ef10_tx_init,
5727 .tx_remove = efx_ef10_tx_remove,
5728 .tx_write = efx_ef10_tx_write,
e9117e50 5729 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 5730 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 5731 .rx_probe = efx_ef10_rx_probe,
5732 .rx_init = efx_ef10_rx_init,
5733 .rx_remove = efx_ef10_rx_remove,
5734 .rx_write = efx_ef10_rx_write,
5735 .rx_defer_refill = efx_ef10_rx_defer_refill,
5736 .ev_probe = efx_ef10_ev_probe,
5737 .ev_init = efx_ef10_ev_init,
5738 .ev_fini = efx_ef10_ev_fini,
5739 .ev_remove = efx_ef10_ev_remove,
5740 .ev_process = efx_ef10_ev_process,
5741 .ev_read_ack = efx_ef10_ev_read_ack,
5742 .ev_test_generate = efx_ef10_ev_test_generate,
5743 .filter_table_probe = efx_ef10_filter_table_probe,
5744 .filter_table_restore = efx_ef10_filter_table_restore,
5745 .filter_table_remove = efx_ef10_filter_table_remove,
5746 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5747 .filter_insert = efx_ef10_filter_insert,
5748 .filter_remove_safe = efx_ef10_filter_remove_safe,
5749 .filter_get_safe = efx_ef10_filter_get_safe,
5750 .filter_clear_rx = efx_ef10_filter_clear_rx,
5751 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5752 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5753 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5754#ifdef CONFIG_RFS_ACCEL
5755 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5756 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5757#endif
5758#ifdef CONFIG_SFC_MTD
5759 .mtd_probe = efx_ef10_mtd_probe,
5760 .mtd_rename = efx_mcdi_mtd_rename,
5761 .mtd_read = efx_mcdi_mtd_read,
5762 .mtd_erase = efx_mcdi_mtd_erase,
5763 .mtd_write = efx_mcdi_mtd_write,
5764 .mtd_sync = efx_mcdi_mtd_sync,
5765#endif
5766 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 5767 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5768 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 5769 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5770 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
7fa8d547 5771#ifdef CONFIG_SFC_SRIOV
834e23dd 5772 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 5773 .sriov_init = efx_ef10_sriov_init,
5774 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 5775 .sriov_wanted = efx_ef10_sriov_wanted,
5776 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 5777 .sriov_flr = efx_ef10_sriov_flr,
5778 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5779 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5780 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5781 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 5782 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 5783 .vswitching_probe = efx_ef10_vswitching_probe_pf,
5784 .vswitching_restore = efx_ef10_vswitching_restore_pf,
5785 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 5786#endif
0d5e0fbb 5787 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 5788 .set_mac_address = efx_ef10_set_mac_address,
46d1efd8 5789 .tso_versions = efx_ef10_tso_versions,
8127d661 5790
08a7b29b 5791 .get_phys_port_id = efx_ef10_get_phys_port_id,
8127d661
BH		 5792 .revision = EFX_REV_HUNT_A0,
5793 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5794 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5795 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 5796 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 5797 .can_rx_scatter = true,
5798 .always_rx_scatter = true,
5799 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5800 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 5801 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661
BH		 5802 .mcdi_max_ver = 2,
5803 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 5804 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5805 1 << HWTSTAMP_FILTER_ALL,
8127d661 5806};
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