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sfc: Update EF10 register definitions
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
dc3273e0
AR		 53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
34813fe2
AR		 57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
dc3273e0
AR		 63/* Per-VLAN filters information */
64struct efx_ef10_filter_vlan {
34813fe2 65 struct list_head list;
b3a3c03c 66 u16 vid;
dc3273e0
AR		 67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
69 u16 ucdef;
70 u16 bcast;
71 u16 mcdef;
72};
73
822b96f8
DP		 74struct efx_ef10_dev_addr {
75 u8 addr[ETH_ALEN];
822b96f8
DP		 76};
77
8127d661 78struct efx_ef10_filter_table {
7ac0dd9d
AR		 79/* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags[
8127d661
BH		 81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
82 unsigned int rx_match_count;
83
84 struct {
85 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 86/* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 88 */
89#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 90#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 91#define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle; /* firmware handle */
93 } *entry;
94 wait_queue_head_t waitq;
95/* Shadow of net_device address lists, guarded by mac_lock */
822b96f8
DP		 96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 98 int dev_uc_count;
99 int dev_mc_count;
afa4ce12
AR		 100 bool uc_promisc;
101 bool mc_promisc;
b071c3a2
AR		 102/* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last;
4a53ea8a 104 bool vlan_filter;
34813fe2 105 struct list_head vlan_list;
8127d661
BH		 106};
107
108/* An arbitrary search limit for the software hash table */
109#define EFX_EF10_FILTER_SEARCH_LIMIT 200
110
8127d661
BH		 111static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
112static void efx_ef10_filter_table_remove(struct efx_nic *efx);
34813fe2
AR		 113static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
114static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
115 struct efx_ef10_filter_vlan *vlan);
116static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
8127d661
BH		 117
118static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
119{
120 efx_dword_t reg;
121
122 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
125}
126
127static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
128{
02246a7f
SS		 129 int bar;
130
131 bar = efx->type->mem_bar;
132 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 133}
134
7a186f47
DP		 135static bool efx_ef10_is_vf(struct efx_nic *efx)
136{
137 return efx->type->is_vf;
138}
139
1cd9ecbb
DP		 140static int efx_ef10_get_pf_index(struct efx_nic *efx)
141{
142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
143 struct efx_ef10_nic_data *nic_data = efx->nic_data;
144 size_t outlen;
145 int rc;
146
147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
148 sizeof(outbuf), &outlen);
149 if (rc)
150 return rc;
151 if (outlen < sizeof(outbuf))
152 return -EIO;
153
154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
155 return 0;
156}
157
88a37de6
SS		 158#ifdef CONFIG_SFC_SRIOV
159static int efx_ef10_get_vf_index(struct efx_nic *efx)
160{
161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
163 size_t outlen;
164 int rc;
165
166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
167 sizeof(outbuf), &outlen);
168 if (rc)
169 return rc;
170 if (outlen < sizeof(outbuf))
171 return -EIO;
172
173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
174 return 0;
175}
176#endif
177
e5a2538a 178static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 179{
ca889a05 180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
8127d661
BH		 181 struct efx_ef10_nic_data *nic_data = efx->nic_data;
182 size_t outlen;
183 int rc;
184
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
186
187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
188 outbuf, sizeof(outbuf), &outlen);
189 if (rc)
190 return rc;
ca889a05 191 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 192 netif_err(efx, drv, efx->net_dev,
193 "unable to read datapath firmware capabilities\n");
194 return -EIO;
195 }
196
197 nic_data->datapath_caps =
198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 199
ca889a05
BK		 200 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
201 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
202 GET_CAPABILITIES_V2_OUT_FLAGS2);
203 else
204 nic_data->datapath_caps2 = 0;
205
8d9f9dd4
DP		 206 /* record the DPCPU firmware IDs to determine VEB vswitching support.
207 */
208 nic_data->rx_dpcpu_fw_id =
209 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
210 nic_data->tx_dpcpu_fw_id =
211 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
212
e5a2538a
BH		 213 if (!(nic_data->datapath_caps &
214 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
215 netif_err(efx, probe, efx->net_dev,
216 "current firmware does not support an RX prefix\n");
217 return -ENODEV;
8127d661
BH		 218 }
219
220 return 0;
221}
222
223static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
224{
225 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
226 int rc;
227
228 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
229 outbuf, sizeof(outbuf), NULL);
230 if (rc)
231 return rc;
232 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
233 return rc > 0 ? rc : -ERANGE;
234}
235
d95e329a
BK		 236static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
237{
238 struct efx_ef10_nic_data *nic_data = efx->nic_data;
239 unsigned int implemented;
240 unsigned int enabled;
241 int rc;
242
243 nic_data->workaround_35388 = false;
244 nic_data->workaround_61265 = false;
245
246 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
247
248 if (rc == -ENOSYS) {
249 /* Firmware without GET_WORKAROUNDS - not a problem. */
250 rc = 0;
251 } else if (rc == 0) {
252 /* Bug61265 workaround is always enabled if implemented. */
253 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
254 nic_data->workaround_61265 = true;
255
256 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
257 nic_data->workaround_35388 = true;
258 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
259 /* Workaround is implemented but not enabled.
260 * Try to enable it.
261 */
262 rc = efx_mcdi_set_workaround(efx,
263 MC_CMD_WORKAROUND_BUG35388,
264 true, NULL);
265 if (rc == 0)
266 nic_data->workaround_35388 = true;
267 /* If we failed to set the workaround just carry on. */
268 rc = 0;
269 }
270 }
271
272 netif_dbg(efx, probe, efx->net_dev,
273 "workaround for bug 35388 is %sabled\n",
274 nic_data->workaround_35388 ? "en" : "dis");
275 netif_dbg(efx, probe, efx->net_dev,
276 "workaround for bug 61265 is %sabled\n",
277 nic_data->workaround_61265 ? "en" : "dis");
278
279 return rc;
280}
281
282static void efx_ef10_process_timer_config(struct efx_nic *efx,
283 const efx_dword_t *data)
284{
285 unsigned int max_count;
286
287 if (EFX_EF10_WORKAROUND_61265(efx)) {
288 efx->timer_quantum_ns = MCDI_DWORD(data,
289 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
290 efx->timer_max_ns = MCDI_DWORD(data,
291 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
292 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
293 efx->timer_quantum_ns = MCDI_DWORD(data,
294 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
295 max_count = MCDI_DWORD(data,
296 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
297 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
298 } else {
299 efx->timer_quantum_ns = MCDI_DWORD(data,
300 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
301 max_count = MCDI_DWORD(data,
302 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
303 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
304 }
305
306 netif_dbg(efx, probe, efx->net_dev,
307 "got timer properties from MC: quantum %u ns; max %u ns\n",
308 efx->timer_quantum_ns, efx->timer_max_ns);
309}
310
311static int efx_ef10_get_timer_config(struct efx_nic *efx)
312{
313 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
314 int rc;
315
316 rc = efx_ef10_get_timer_workarounds(efx);
317 if (rc)
318 return rc;
319
320 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
321 outbuf, sizeof(outbuf), NULL);
322
323 if (rc == 0) {
324 efx_ef10_process_timer_config(efx, outbuf);
325 } else if (rc == -ENOSYS || rc == -EPERM) {
326 /* Not available - fall back to Huntington defaults. */
327 unsigned int quantum;
328
329 rc = efx_ef10_get_sysclk_freq(efx);
330 if (rc < 0)
331 return rc;
332
333 quantum = 1536000 / rc; /* 1536 cycles */
334 efx->timer_quantum_ns = quantum;
335 efx->timer_max_ns = efx->type->timer_period_max * quantum;
336 rc = 0;
337 } else {
338 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
339 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
340 NULL, 0, rc);
341 }
342
343 return rc;
344}
345
0d5e0fbb 346static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 347{
348 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
349 size_t outlen;
350 int rc;
351
352 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
353
354 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
355 outbuf, sizeof(outbuf), &outlen);
356 if (rc)
357 return rc;
358 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
359 return -EIO;
360
cd84ff4d
EC		 361 ether_addr_copy(mac_address,
362 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 363 return 0;
364}
365
0d5e0fbb
DP		 366static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
367{
368 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
369 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
370 size_t outlen;
371 int num_addrs, rc;
372
373 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
374 EVB_PORT_ID_ASSIGNED);
375 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
376 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
377
378 if (rc)
379 return rc;
380 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
381 return -EIO;
382
383 num_addrs = MCDI_DWORD(outbuf,
384 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
385
386 WARN_ON(num_addrs != 1);
387
388 ether_addr_copy(mac_address,
389 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
390
391 return 0;
392}
393
0f5c0845
SS		 394static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
395 struct device_attribute *attr,
396 char *buf)
397{
398 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
399
400 return sprintf(buf, "%d\n",
401 ((efx->mcdi->fn_flags) &
402 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
403 ? 1 : 0);
404}
405
406static ssize_t efx_ef10_show_primary_flag(struct device *dev,
407 struct device_attribute *attr,
408 char *buf)
409{
410 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
411
412 return sprintf(buf, "%d\n",
413 ((efx->mcdi->fn_flags) &
414 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
415 ? 1 : 0);
416}
417
34813fe2
AR		 418static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
419{
420 struct efx_ef10_nic_data *nic_data = efx->nic_data;
421 struct efx_ef10_vlan *vlan;
422
423 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
424
425 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
426 if (vlan->vid == vid)
427 return vlan;
428 }
429
430 return NULL;
431}
432
433static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
434{
435 struct efx_ef10_nic_data *nic_data = efx->nic_data;
436 struct efx_ef10_vlan *vlan;
437 int rc;
438
439 mutex_lock(&nic_data->vlan_lock);
440
441 vlan = efx_ef10_find_vlan(efx, vid);
442 if (vlan) {
4a53ea8a
AR		 443 /* We add VID 0 on init. 8021q adds it on module init
444 * for all interfaces with VLAN filtring feature.
445 */
446 if (vid == 0)
447 goto done_unlock;
34813fe2
AR		 448 netif_warn(efx, drv, efx->net_dev,
449 "VLAN %u already added\n", vid);
450 rc = -EALREADY;
451 goto fail_exist;
452 }
453
454 rc = -ENOMEM;
455 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
456 if (!vlan)
457 goto fail_alloc;
458
459 vlan->vid = vid;
460
461 list_add_tail(&vlan->list, &nic_data->vlan_list);
462
463 if (efx->filter_state) {
464 mutex_lock(&efx->mac_lock);
465 down_write(&efx->filter_sem);
466 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
467 up_write(&efx->filter_sem);
468 mutex_unlock(&efx->mac_lock);
469 if (rc)
470 goto fail_filter_add_vlan;
471 }
472
4a53ea8a 473done_unlock:
34813fe2
AR		 474 mutex_unlock(&nic_data->vlan_lock);
475 return 0;
476
477fail_filter_add_vlan:
478 list_del(&vlan->list);
479 kfree(vlan);
480fail_alloc:
481fail_exist:
482 mutex_unlock(&nic_data->vlan_lock);
483 return rc;
484}
485
486static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
487 struct efx_ef10_vlan *vlan)
488{
489 struct efx_ef10_nic_data *nic_data = efx->nic_data;
490
491 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
492
493 if (efx->filter_state) {
494 down_write(&efx->filter_sem);
495 efx_ef10_filter_del_vlan(efx, vlan->vid);
496 up_write(&efx->filter_sem);
497 }
498
499 list_del(&vlan->list);
500 kfree(vlan);
501}
502
4a53ea8a
AR		 503static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
504{
505 struct efx_ef10_nic_data *nic_data = efx->nic_data;
506 struct efx_ef10_vlan *vlan;
507 int rc = 0;
508
509 /* 8021q removes VID 0 on module unload for all interfaces
510 * with VLAN filtering feature. We need to keep it to receive
511 * untagged traffic.
512 */
513 if (vid == 0)
514 return 0;
515
516 mutex_lock(&nic_data->vlan_lock);
517
518 vlan = efx_ef10_find_vlan(efx, vid);
519 if (!vlan) {
520 netif_err(efx, drv, efx->net_dev,
521 "VLAN %u to be deleted not found\n", vid);
522 rc = -ENOENT;
523 } else {
524 efx_ef10_del_vlan_internal(efx, vlan);
525 }
526
527 mutex_unlock(&nic_data->vlan_lock);
528
529 return rc;
530}
531
34813fe2
AR		 532static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
533{
534 struct efx_ef10_nic_data *nic_data = efx->nic_data;
535 struct efx_ef10_vlan *vlan, *next_vlan;
536
537 mutex_lock(&nic_data->vlan_lock);
538 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
539 efx_ef10_del_vlan_internal(efx, vlan);
540 mutex_unlock(&nic_data->vlan_lock);
541}
542
0f5c0845
SS		 543static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
544 NULL);
545static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
546
8127d661
BH		 547static int efx_ef10_probe(struct efx_nic *efx)
548{
549 struct efx_ef10_nic_data *nic_data;
8be41320 550 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 551 int i, rc;
552
aa3930ee
BH		 553 /* We can have one VI for each 8K region. However, until we
554 * use TX option descriptors we need two TX queues per channel.
8127d661 555 */
b0fbdae1
SS		 556 efx->max_channels = min_t(unsigned int,
557 EFX_MAX_CHANNELS,
558 efx_ef10_mem_map_size(efx) /
559 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
560 efx->max_tx_channels = efx->max_channels;
9fd3d3a4
EC		 561 if (WARN_ON(efx->max_channels == 0))
562 return -EIO;
8127d661
BH		 563
564 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
565 if (!nic_data)
566 return -ENOMEM;
567 efx->nic_data = nic_data;
568
75aba2a5
EC		 569 /* we assume later that we can copy from this buffer in dwords */
570 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
571
8127d661
BH		 572 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
573 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
574 if (rc)
575 goto fail1;
576
577 /* Get the MC's warm boot count. In case it's rebooting right
578 * now, be prepared to retry.
579 */
580 i = 0;
581 for (;;) {
582 rc = efx_ef10_get_warm_boot_count(efx);
583 if (rc >= 0)
584 break;
585 if (++i == 5)
586 goto fail2;
587 ssleep(1);
588 }
589 nic_data->warm_boot_count = rc;
590
591 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
592
45b2449e
DP		 593 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
594
8127d661
BH		 595 /* In case we're recovering from a crash (kexec), we want to
596 * cancel any outstanding request by the previous user of this
597 * function. We send a special message using the least
598 * significant bits of the 'high' (doorbell) register.
599 */
600 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
601
602 rc = efx_mcdi_init(efx);
603 if (rc)
604 goto fail2;
605
606 /* Reset (most) configuration for this function */
607 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
608 if (rc)
609 goto fail3;
610
611 /* Enable event logging */
612 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
613 if (rc)
614 goto fail3;
615
0f5c0845
SS		 616 rc = device_create_file(&efx->pci_dev->dev,
617 &dev_attr_link_control_flag);
1cd9ecbb
DP		 618 if (rc)
619 goto fail3;
620
0f5c0845
SS		 621 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
622 if (rc)
623 goto fail4;
624
625 rc = efx_ef10_get_pf_index(efx);
626 if (rc)
627 goto fail5;
628
e5a2538a 629 rc = efx_ef10_init_datapath_caps(efx);
8127d661 630 if (rc < 0)
0f5c0845 631 goto fail5;
8127d661
BH		 632
633 efx->rx_packet_len_offset =
634 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
635
8127d661
BH		 636 rc = efx_mcdi_port_get_number(efx);
637 if (rc < 0)
0f5c0845 638 goto fail5;
8127d661 639 efx->port_num = rc;
8be41320 640 net_dev->dev_port = rc;
8127d661 641
0d5e0fbb 642 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 643 if (rc)
0f5c0845 644 goto fail5;
8127d661 645
d95e329a 646 rc = efx_ef10_get_timer_config(efx);
8127d661 647 if (rc < 0)
0f5c0845 648 goto fail5;
8127d661 649
8127d661 650 rc = efx_mcdi_mon_probe(efx);
267d9d73 651 if (rc && rc != -EPERM)
0f5c0845 652 goto fail5;
8127d661 653
9aecda95
BH		 654 efx_ptp_probe(efx, NULL);
655
1d051e00
SS		 656#ifdef CONFIG_SFC_SRIOV
657 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
658 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
659 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
660
661 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
662 } else
663#endif
664 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
665
34813fe2
AR		 666 INIT_LIST_HEAD(&nic_data->vlan_list);
667 mutex_init(&nic_data->vlan_lock);
668
669 /* Add unspecified VID to support VLAN filtering being disabled */
670 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
671 if (rc)
672 goto fail_add_vid_unspec;
673
4a53ea8a
AR		 674 /* If VLAN filtering is enabled, we need VID 0 to get untagged
675 * traffic. It is added automatically if 8021q module is loaded,
676 * but we can't rely on it since module may be not loaded.
677 */
678 rc = efx_ef10_add_vlan(efx, 0);
679 if (rc)
680 goto fail_add_vid_0;
681
8127d661
BH		 682 return 0;
683
4a53ea8a
AR		 684fail_add_vid_0:
685 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 686fail_add_vid_unspec:
687 mutex_destroy(&nic_data->vlan_lock);
688 efx_ptp_remove(efx);
689 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 690fail5:
691 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
692fail4:
693 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 694fail3:
695 efx_mcdi_fini(efx);
696fail2:
697 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
698fail1:
699 kfree(nic_data);
700 efx->nic_data = NULL;
701 return rc;
702}
703
704static int efx_ef10_free_vis(struct efx_nic *efx)
705{
aa09a3da 706 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 707 size_t outlen;
708 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
709 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 710
711 /* -EALREADY means nothing to free, so ignore */
712 if (rc == -EALREADY)
713 rc = 0;
1e0b8120
EC		 714 if (rc)
715 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
716 rc);
8127d661
BH		 717 return rc;
718}
719
183233be
BH		 720#ifdef EFX_USE_PIO
721
722static void efx_ef10_free_piobufs(struct efx_nic *efx)
723{
724 struct efx_ef10_nic_data *nic_data = efx->nic_data;
725 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
726 unsigned int i;
727 int rc;
728
729 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
730
731 for (i = 0; i < nic_data->n_piobufs; i++) {
732 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
733 nic_data->piobuf_handle[i]);
734 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
735 NULL, 0, NULL);
736 WARN_ON(rc);
737 }
738
739 nic_data->n_piobufs = 0;
740}
741
742static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
743{
744 struct efx_ef10_nic_data *nic_data = efx->nic_data;
745 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
746 unsigned int i;
747 size_t outlen;
748 int rc = 0;
749
750 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
751
752 for (i = 0; i < n; i++) {
09a04204
BK		 753 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
754 outbuf, sizeof(outbuf), &outlen);
755 if (rc) {
756 /* Don't display the MC error if we didn't have space
757 * for a VF.
758 */
759 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
760 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
761 0, outbuf, outlen, rc);
183233be 762 break;
09a04204 763 }
183233be
BH		 764 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
765 rc = -EIO;
766 break;
767 }
768 nic_data->piobuf_handle[i] =
769 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
770 netif_dbg(efx, probe, efx->net_dev,
771 "allocated PIO buffer %u handle %x\n", i,
772 nic_data->piobuf_handle[i]);
773 }
774
775 nic_data->n_piobufs = i;
776 if (rc)
777 efx_ef10_free_piobufs(efx);
778 return rc;
779}
780
781static int efx_ef10_link_piobufs(struct efx_nic *efx)
782{
783 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 784 _MCDI_DECLARE_BUF(inbuf,
785 max(MC_CMD_LINK_PIOBUF_IN_LEN,
786 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 787 struct efx_channel *channel;
788 struct efx_tx_queue *tx_queue;
789 unsigned int offset, index;
790 int rc;
791
792 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
793 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
794
aa09a3da
JC		 795 memset(inbuf, 0, sizeof(inbuf));
796
183233be
BH		 797 /* Link a buffer to each VI in the write-combining mapping */
798 for (index = 0; index < nic_data->n_piobufs; ++index) {
799 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
800 nic_data->piobuf_handle[index]);
801 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
802 nic_data->pio_write_vi_base + index);
803 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
804 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
805 NULL, 0, NULL);
806 if (rc) {
807 netif_err(efx, drv, efx->net_dev,
808 "failed to link VI %u to PIO buffer %u (%d)\n",
809 nic_data->pio_write_vi_base + index, index,
810 rc);
811 goto fail;
812 }
813 netif_dbg(efx, probe, efx->net_dev,
814 "linked VI %u to PIO buffer %u\n",
815 nic_data->pio_write_vi_base + index, index);
816 }
817
818 /* Link a buffer to each TX queue */
819 efx_for_each_channel(channel, efx) {
820 efx_for_each_channel_tx_queue(tx_queue, channel) {
821 /* We assign the PIO buffers to queues in
822 * reverse order to allow for the following
823 * special case.
824 */
825 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
826 tx_queue->channel->channel - 1) *
827 efx_piobuf_size);
828 index = offset / ER_DZ_TX_PIOBUF_SIZE;
829 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
830
831 /* When the host page size is 4K, the first
832 * host page in the WC mapping may be within
833 * the same VI page as the last TX queue. We
834 * can only link one buffer to each VI.
835 */
836 if (tx_queue->queue == nic_data->pio_write_vi_base) {
837 BUG_ON(index != 0);
838 rc = 0;
839 } else {
840 MCDI_SET_DWORD(inbuf,
841 LINK_PIOBUF_IN_PIOBUF_HANDLE,
842 nic_data->piobuf_handle[index]);
843 MCDI_SET_DWORD(inbuf,
844 LINK_PIOBUF_IN_TXQ_INSTANCE,
845 tx_queue->queue);
846 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
847 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
848 NULL, 0, NULL);
849 }
850
851 if (rc) {
852 /* This is non-fatal; the TX path just
853 * won't use PIO for this queue
854 */
855 netif_err(efx, drv, efx->net_dev,
856 "failed to link VI %u to PIO buffer %u (%d)\n",
857 tx_queue->queue, index, rc);
858 tx_queue->piobuf = NULL;
859 } else {
860 tx_queue->piobuf =
861 nic_data->pio_write_base +
862 index * EFX_VI_PAGE_SIZE + offset;
863 tx_queue->piobuf_offset = offset;
864 netif_dbg(efx, probe, efx->net_dev,
865 "linked VI %u to PIO buffer %u offset %x addr %p\n",
866 tx_queue->queue, index,
867 tx_queue->piobuf_offset,
868 tx_queue->piobuf);
869 }
870 }
871 }
872
873 return 0;
874
875fail:
876 while (index--) {
877 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
878 nic_data->pio_write_vi_base + index);
879 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
880 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
881 NULL, 0, NULL);
882 }
883 return rc;
884}
885
c0795bf6
EC		 886static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
887{
888 struct efx_channel *channel;
889 struct efx_tx_queue *tx_queue;
890
891 /* All our existing PIO buffers went away */
892 efx_for_each_channel(channel, efx)
893 efx_for_each_channel_tx_queue(tx_queue, channel)
894 tx_queue->piobuf = NULL;
895}
896
183233be
BH		 897#else /* !EFX_USE_PIO */
898
899static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
900{
901 return n == 0 ? 0 : -ENOBUFS;
902}
903
904static int efx_ef10_link_piobufs(struct efx_nic *efx)
905{
906 return 0;
907}
908
909static void efx_ef10_free_piobufs(struct efx_nic *efx)
910{
911}
912
c0795bf6
EC		 913static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
914{
915}
916
183233be
BH		 917#endif /* EFX_USE_PIO */
918
8127d661
BH		 919static void efx_ef10_remove(struct efx_nic *efx)
920{
921 struct efx_ef10_nic_data *nic_data = efx->nic_data;
922 int rc;
923
f1122a34
SS		 924#ifdef CONFIG_SFC_SRIOV
925 struct efx_ef10_nic_data *nic_data_pf;
926 struct pci_dev *pci_dev_pf;
927 struct efx_nic *efx_pf;
928 struct ef10_vf *vf;
929
930 if (efx->pci_dev->is_virtfn) {
931 pci_dev_pf = efx->pci_dev->physfn;
932 if (pci_dev_pf) {
933 efx_pf = pci_get_drvdata(pci_dev_pf);
934 nic_data_pf = efx_pf->nic_data;
935 vf = nic_data_pf->vf + nic_data->vf_index;
936 vf->efx = NULL;
937 } else
938 netif_info(efx, drv, efx->net_dev,
939 "Could not get the PF id from VF\n");
940 }
941#endif
942
34813fe2
AR		 943 efx_ef10_cleanup_vlans(efx);
944 mutex_destroy(&nic_data->vlan_lock);
945
9aecda95
BH		 946 efx_ptp_remove(efx);
947
8127d661
BH		 948 efx_mcdi_mon_remove(efx);
949
8127d661
BH		 950 efx_ef10_rx_free_indir_table(efx);
951
183233be
BH		 952 if (nic_data->wc_membase)
953 iounmap(nic_data->wc_membase);
954
8127d661
BH		 955 rc = efx_ef10_free_vis(efx);
956 WARN_ON(rc != 0);
957
183233be
BH		 958 if (!nic_data->must_restore_piobufs)
959 efx_ef10_free_piobufs(efx);
960
0f5c0845
SS		 961 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
962 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
963
8127d661
BH		 964 efx_mcdi_fini(efx);
965 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
966 kfree(nic_data);
967}
968
88a37de6
SS		 969static int efx_ef10_probe_pf(struct efx_nic *efx)
970{
971 return efx_ef10_probe(efx);
972}
973
38d27f38
AR		 974int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
975 u32 *port_flags, u32 *vadaptor_flags,
976 unsigned int *vlan_tags)
977{
978 struct efx_ef10_nic_data *nic_data = efx->nic_data;
979 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
980 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
981 size_t outlen;
982 int rc;
983
984 if (nic_data->datapath_caps &
985 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
986 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
987 port_id);
988
989 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
990 outbuf, sizeof(outbuf), &outlen);
991 if (rc)
992 return rc;
993
994 if (outlen < sizeof(outbuf)) {
995 rc = -EIO;
996 return rc;
997 }
998 }
999
1000 if (port_flags)
1001 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1002 if (vadaptor_flags)
1003 *vadaptor_flags =
1004 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1005 if (vlan_tags)
1006 *vlan_tags =
1007 MCDI_DWORD(outbuf,
1008 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1009
1010 return 0;
1011}
1012
7a186f47
DP		 1013int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1014{
1015 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1016
1017 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1018 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1019 NULL, 0, NULL);
1020}
1021
1022int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1023{
1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1025
1026 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1027 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1028 NULL, 0, NULL);
1029}
1030
1031int efx_ef10_vport_add_mac(struct efx_nic *efx,
1032 unsigned int port_id, u8 *mac)
1033{
1034 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1035
1036 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1037 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1038
1039 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1040 sizeof(inbuf), NULL, 0, NULL);
1041}
1042
1043int efx_ef10_vport_del_mac(struct efx_nic *efx,
1044 unsigned int port_id, u8 *mac)
1045{
1046 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1047
1048 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1049 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1050
1051 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1052 sizeof(inbuf), NULL, 0, NULL);
1053}
1054
88a37de6
SS		 1055#ifdef CONFIG_SFC_SRIOV
1056static int efx_ef10_probe_vf(struct efx_nic *efx)
1057{
1058 int rc;
6598dad2
DP		 1059 struct pci_dev *pci_dev_pf;
1060
1061 /* If the parent PF has no VF data structure, it doesn't know about this
1062 * VF so fail probe. The VF needs to be re-created. This can happen
1063 * if the PF driver is unloaded while the VF is assigned to a guest.
1064 */
1065 pci_dev_pf = efx->pci_dev->physfn;
1066 if (pci_dev_pf) {
1067 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1068 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1069
1070 if (!nic_data_pf->vf) {
1071 netif_info(efx, drv, efx->net_dev,
1072 "The VF cannot link to its parent PF; "
1073 "please destroy and re-create the VF\n");
1074 return -EBUSY;
1075 }
1076 }
88a37de6
SS		 1077
1078 rc = efx_ef10_probe(efx);
1079 if (rc)
1080 return rc;
1081
1082 rc = efx_ef10_get_vf_index(efx);
1083 if (rc)
1084 goto fail;
1085
f1122a34
SS		 1086 if (efx->pci_dev->is_virtfn) {
1087 if (efx->pci_dev->physfn) {
1088 struct efx_nic *efx_pf =
1089 pci_get_drvdata(efx->pci_dev->physfn);
1090 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1091 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1092
1093 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1094 nic_data_p->vf[nic_data->vf_index].pci_dev =
1095 efx->pci_dev;
f1122a34
SS		 1096 } else
1097 netif_info(efx, drv, efx->net_dev,
1098 "Could not get the PF id from VF\n");
1099 }
1100
88a37de6
SS		 1101 return 0;
1102
1103fail:
1104 efx_ef10_remove(efx);
1105 return rc;
1106}
1107#else
1108static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1109{
1110 return 0;
1111}
1112#endif
1113
8127d661
BH		 1114static int efx_ef10_alloc_vis(struct efx_nic *efx,
1115 unsigned int min_vis, unsigned int max_vis)
1116{
1117 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1118 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1120 size_t outlen;
1121 int rc;
1122
1123 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1124 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1125 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1126 outbuf, sizeof(outbuf), &outlen);
1127 if (rc != 0)
1128 return rc;
1129
1130 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1131 return -EIO;
1132
1133 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1134 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1135
1136 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1137 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1138 return 0;
1139}
1140
183233be
BH		 1141/* Note that the failure path of this function does not free
1142 * resources, as this will be done by efx_ef10_remove().
1143 */
8127d661
BH		 1144static int efx_ef10_dimension_resources(struct efx_nic *efx)
1145{
183233be
BH		 1146 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1147 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 1148 unsigned int min_vis = max(EFX_TXQ_TYPES,
1149 efx_separate_tx_channels ? 2 : 1);
1150 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1151 void __iomem *membase;
1152 int rc;
1153
b0fbdae1 1154 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 1155
183233be
BH		 1156#ifdef EFX_USE_PIO
1157 /* Try to allocate PIO buffers if wanted and if the full
1158 * number of PIO buffers would be sufficient to allocate one
1159 * copy-buffer per TX channel. Failure is non-fatal, as there
1160 * are only a small number of PIO buffers shared between all
1161 * functions of the controller.
1162 */
1163 if (efx_piobuf_size != 0 &&
1164 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1165 efx->n_tx_channels) {
1166 unsigned int n_piobufs =
1167 DIV_ROUND_UP(efx->n_tx_channels,
1168 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
1169
1170 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1171 if (rc)
1172 netif_err(efx, probe, efx->net_dev,
1173 "failed to allocate PIO buffers (%d)\n", rc);
1174 else
1175 netif_dbg(efx, probe, efx->net_dev,
1176 "allocated %u PIO buffers\n", n_piobufs);
1177 }
1178#else
1179 nic_data->n_piobufs = 0;
1180#endif
1181
1182 /* PIO buffers should be mapped with write-combining enabled,
1183 * and we want to make single UC and WC mappings rather than
1184 * several of each (in fact that's the only option if host
1185 * page size is >4K). So we may allocate some extra VIs just
1186 * for writing PIO buffers through.
52ad762b 1187 *
b0fbdae1 1188 * The UC mapping contains (channel_vis - 1) complete VIs and the
52ad762b
DP		 1189 * first half of the next VI. Then the WC mapping begins with
1190 * the second half of this last VI.
183233be 1191 */
b0fbdae1 1192 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
183233be
BH		 1193 ER_DZ_TX_PIOBUF);
1194 if (nic_data->n_piobufs) {
52ad762b
DP		 1195 /* pio_write_vi_base rounds down to give the number of complete
1196 * VIs inside the UC mapping.
1197 */
183233be
BH		 1198 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1199 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1200 nic_data->n_piobufs) *
1201 EFX_VI_PAGE_SIZE) -
1202 uc_mem_map_size);
1203 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1204 } else {
1205 pio_write_vi_base = 0;
1206 wc_mem_map_size = 0;
b0fbdae1 1207 max_vis = channel_vis;
183233be
BH		 1208 }
1209
1210 /* In case the last attached driver failed to free VIs, do it now */
1211 rc = efx_ef10_free_vis(efx);
1212 if (rc != 0)
1213 return rc;
1214
1215 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1216 if (rc != 0)
1217 return rc;
1218
b0fbdae1
SS		 1219 if (nic_data->n_allocated_vis < channel_vis) {
1220 netif_info(efx, drv, efx->net_dev,
1221 "Could not allocate enough VIs to satisfy RSS"
1222 " requirements. Performance may not be optimal.\n");
1223 /* We didn't get the VIs to populate our channels.
1224 * We could keep what we got but then we'd have more
1225 * interrupts than we need.
1226 * Instead calculate new max_channels and restart
1227 */
1228 efx->max_channels = nic_data->n_allocated_vis;
1229 efx->max_tx_channels =
1230 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1231
1232 efx_ef10_free_vis(efx);
1233 return -EAGAIN;
1234 }
1235
183233be
BH		 1236 /* If we didn't get enough VIs to map all the PIO buffers, free the
1237 * PIO buffers
1238 */
1239 if (nic_data->n_piobufs &&
1240 nic_data->n_allocated_vis <
1241 pio_write_vi_base + nic_data->n_piobufs) {
1242 netif_dbg(efx, probe, efx->net_dev,
1243 "%u VIs are not sufficient to map %u PIO buffers\n",
1244 nic_data->n_allocated_vis, nic_data->n_piobufs);
1245 efx_ef10_free_piobufs(efx);
1246 }
1247
1248 /* Shrink the original UC mapping of the memory BAR */
1249 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1250 if (!membase) {
1251 netif_err(efx, probe, efx->net_dev,
1252 "could not shrink memory BAR to %x\n",
1253 uc_mem_map_size);
1254 return -ENOMEM;
1255 }
1256 iounmap(efx->membase);
1257 efx->membase = membase;
1258
1259 /* Set up the WC mapping if needed */
1260 if (wc_mem_map_size) {
1261 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1262 uc_mem_map_size,
1263 wc_mem_map_size);
1264 if (!nic_data->wc_membase) {
1265 netif_err(efx, probe, efx->net_dev,
1266 "could not allocate WC mapping of size %x\n",
1267 wc_mem_map_size);
1268 return -ENOMEM;
1269 }
1270 nic_data->pio_write_vi_base = pio_write_vi_base;
1271 nic_data->pio_write_base =
1272 nic_data->wc_membase +
1273 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1274 uc_mem_map_size);
1275
1276 rc = efx_ef10_link_piobufs(efx);
1277 if (rc)
1278 efx_ef10_free_piobufs(efx);
1279 }
1280
1281 netif_dbg(efx, probe, efx->net_dev,
1282 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1283 &efx->membase_phys, efx->membase, uc_mem_map_size,
1284 nic_data->wc_membase, wc_mem_map_size);
1285
1286 return 0;
8127d661
BH		 1287}
1288
1289static int efx_ef10_init_nic(struct efx_nic *efx)
1290{
1291 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1292 int rc;
1293
a915ccc9
BH		 1294 if (nic_data->must_check_datapath_caps) {
1295 rc = efx_ef10_init_datapath_caps(efx);
1296 if (rc)
1297 return rc;
1298 nic_data->must_check_datapath_caps = false;
1299 }
1300
8127d661
BH		 1301 if (nic_data->must_realloc_vis) {
1302 /* We cannot let the number of VIs change now */
1303 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1304 nic_data->n_allocated_vis);
1305 if (rc)
1306 return rc;
1307 nic_data->must_realloc_vis = false;
1308 }
1309
183233be
BH		 1310 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1311 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1312 if (rc == 0) {
1313 rc = efx_ef10_link_piobufs(efx);
1314 if (rc)
1315 efx_ef10_free_piobufs(efx);
1316 }
1317
1318 /* Log an error on failure, but this is non-fatal */
1319 if (rc)
1320 netif_err(efx, drv, efx->net_dev,
1321 "failed to restore PIO buffers (%d)\n", rc);
1322 nic_data->must_restore_piobufs = false;
1323 }
1324
267c0157
JC		 1325 /* don't fail init if RSS setup doesn't work */
1326 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1327
8127d661
BH		 1328 return 0;
1329}
1330
3e336261
JC		 1331static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1332{
1333 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1334#ifdef CONFIG_SFC_SRIOV
1335 unsigned int i;
1336#endif
3e336261
JC		 1337
1338 /* All our allocations have been reset */
1339 nic_data->must_realloc_vis = true;
1340 nic_data->must_restore_filters = true;
1341 nic_data->must_restore_piobufs = true;
c0795bf6 1342 efx_ef10_forget_old_piobufs(efx);
3e336261 1343 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1344
1345 /* Driver-created vswitches and vports must be re-created */
1346 nic_data->must_probe_vswitching = true;
1347 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1348#ifdef CONFIG_SFC_SRIOV
1349 if (nic_data->vf)
1350 for (i = 0; i < efx->vf_count; i++)
1351 nic_data->vf[i].vport_id = 0;
1352#endif
3e336261
JC		 1353}
1354
087e9025
JC		 1355static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1356{
1357 if (reason == RESET_TYPE_MC_FAILURE)
1358 return RESET_TYPE_DATAPATH;
1359
1360 return efx_mcdi_map_reset_reason(reason);
1361}
1362
8127d661
BH		 1363static int efx_ef10_map_reset_flags(u32 *flags)
1364{
1365 enum {
1366 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1367 ETH_RESET_SHARED_SHIFT),
1368 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1369 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1370 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1371 ETH_RESET_SHARED_SHIFT)
1372 };
1373
1374 /* We assume for now that our PCI function is permitted to
1375 * reset everything.
1376 */
1377
1378 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1379 *flags &= ~EF10_RESET_MC;
1380 return RESET_TYPE_WORLD;
1381 }
1382
1383 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1384 *flags &= ~EF10_RESET_PORT;
1385 return RESET_TYPE_ALL;
1386 }
1387
1388 /* no invisible reset implemented */
1389
1390 return -EINVAL;
1391}
1392
3e336261
JC		 1393static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1394{
1395 int rc = efx_mcdi_reset(efx, reset_type);
1396
27324820
DP		 1397 /* Unprivileged functions return -EPERM, but need to return success
1398 * here so that the datapath is brought back up.
1399 */
1400 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1401 rc = 0;
1402
3e336261
JC		 1403 /* If it was a port reset, trigger reallocation of MC resources.
1404 * Note that on an MC reset nothing needs to be done now because we'll
1405 * detect the MC reset later and handle it then.
e283546c
EC		 1406 * For an FLR, we never get an MC reset event, but the MC has reset all
1407 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1408 */
e283546c
EC		 1409 if ((reset_type == RESET_TYPE_ALL ||
1410 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1411 efx_ef10_reset_mc_allocations(efx);
1412 return rc;
1413}
1414
8127d661
BH		 1415#define EF10_DMA_STAT(ext_name, mcdi_name) \
1416 [EF10_STAT_ ## ext_name] = \
1417 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1418#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1419 [EF10_STAT_ ## int_name] = \
1420 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1421#define EF10_OTHER_STAT(ext_name) \
1422 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1423#define GENERIC_SW_STAT(ext_name) \
1424 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1425
1426static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1427 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1428 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1429 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1430 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1431 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1432 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1433 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1434 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1435 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1436 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1437 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1438 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1439 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1440 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1441 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1442 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1443 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1444 EF10_OTHER_STAT(port_rx_good_bytes),
1445 EF10_OTHER_STAT(port_rx_bad_bytes),
1446 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1447 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1448 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1449 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1450 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1451 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1452 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1453 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1454 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1455 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1456 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1457 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1458 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1459 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1460 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1461 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1462 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1463 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1464 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1465 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1466 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1467 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1468 GENERIC_SW_STAT(rx_nodesc_trunc),
1469 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1470 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1471 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1472 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1473 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1474 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1475 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1476 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1477 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1478 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1479 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1480 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1481 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1482 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1483 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1484 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1485 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1486 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1487 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1488 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1489 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1490 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1491 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1492 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1493 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1494 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1495 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1496 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1497 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1498 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1499 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1500};
1501
e80ca013
DP		 1502#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1503 (1ULL << EF10_STAT_port_tx_packets) | \
1504 (1ULL << EF10_STAT_port_tx_pause) | \
1505 (1ULL << EF10_STAT_port_tx_unicast) | \
1506 (1ULL << EF10_STAT_port_tx_multicast) | \
1507 (1ULL << EF10_STAT_port_tx_broadcast) | \
1508 (1ULL << EF10_STAT_port_rx_bytes) | \
1509 (1ULL << \
1510 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1511 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1512 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1513 (1ULL << EF10_STAT_port_rx_packets) | \
1514 (1ULL << EF10_STAT_port_rx_good) | \
1515 (1ULL << EF10_STAT_port_rx_bad) | \
1516 (1ULL << EF10_STAT_port_rx_pause) | \
1517 (1ULL << EF10_STAT_port_rx_control) | \
1518 (1ULL << EF10_STAT_port_rx_unicast) | \
1519 (1ULL << EF10_STAT_port_rx_multicast) | \
1520 (1ULL << EF10_STAT_port_rx_broadcast) | \
1521 (1ULL << EF10_STAT_port_rx_lt64) | \
1522 (1ULL << EF10_STAT_port_rx_64) | \
1523 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1524 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1525 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1526 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1527 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1528 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1529 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1530 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1531 (1ULL << EF10_STAT_port_rx_overflow) | \
1532 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1533 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1534 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661 1535
69b365c3
EC		 1536/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1537 * For a 10G/40G switchable port we do not expose these because they might
1538 * not include all the packets they should.
1539 * On 8000 series NICs these statistics are always provided.
8127d661 1540 */
e80ca013
DP		 1541#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1542 (1ULL << EF10_STAT_port_tx_lt64) | \
1543 (1ULL << EF10_STAT_port_tx_64) | \
1544 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1545 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1546 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1547 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1548 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1549 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1550
1551/* These statistics are only provided by the 40G MAC. For a 10G/40G
1552 * switchable port we do expose these because the errors will otherwise
1553 * be silent.
1554 */
e80ca013
DP		 1555#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1556 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1557
568d7a00
EC		 1558/* These statistics are only provided if the firmware supports the
1559 * capability PM_AND_RXDP_COUNTERS.
1560 */
1561#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1562 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1563 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1564 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1565 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1566 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1567 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1568 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1569 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1570 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1571 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1572 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1573 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1574
4bae913b 1575static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1576{
4bae913b 1577 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1578 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1579 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1580
3c36a2ad
DP		 1581 if (!(efx->mcdi->fn_flags &
1582 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1583 return 0;
1584
69b365c3 1585 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
4bae913b 1586 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
69b365c3
EC		 1587 /* 8000 series have everything even at 40G */
1588 if (nic_data->datapath_caps2 &
1589 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1590 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1591 } else {
4bae913b 1592 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
69b365c3 1593 }
568d7a00
EC		 1594
1595 if (nic_data->datapath_caps &
1596 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1597 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1598
4bae913b
EC		 1599 return raw_mask;
1600}
1601
1602static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1603{
d94619cd 1604 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1605 u64 raw_mask[2];
1606
1607 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1608
d94619cd
DP		 1609 /* Only show vadaptor stats when EVB capability is present */
1610 if (nic_data->datapath_caps &
1611 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1612 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1613 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1614 } else {
1615 raw_mask[1] = 0;
1616 }
4bae913b
EC		 1617
1618#if BITS_PER_LONG == 64
e70c70c3 1619 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
3c36a2ad
DP		 1620 mask[0] = raw_mask[0];
1621 mask[1] = raw_mask[1];
4bae913b 1622#else
e70c70c3 1623 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
3c36a2ad
DP		 1624 mask[0] = raw_mask[0] & 0xffffffff;
1625 mask[1] = raw_mask[0] >> 32;
1626 mask[2] = raw_mask[1] & 0xffffffff;
4bae913b 1627#endif
8127d661
BH		 1628}
1629
1630static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1631{
4bae913b
EC		 1632 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1633
1634 efx_ef10_get_stat_mask(efx, mask);
8127d661 1635 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1636 mask, names);
8127d661
BH		 1637}
1638
d7788196
DP		 1639static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1640 struct rtnl_link_stats64 *core_stats)
1641{
1642 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1643 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1644 u64 *stats = nic_data->stats;
1645 size_t stats_count = 0, index;
1646
1647 efx_ef10_get_stat_mask(efx, mask);
1648
1649 if (full_stats) {
1650 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1651 if (efx_ef10_stat_desc[index].name) {
1652 *full_stats++ = stats[index];
1653 ++stats_count;
1654 }
1655 }
1656 }
1657
fbe4307e
BK		 1658 if (!core_stats)
1659 return stats_count;
1660
1661 if (nic_data->datapath_caps &
1662 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1663 /* Use vadaptor stats. */
0fc95fca
DP		 1664 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1665 stats[EF10_STAT_rx_multicast] +
1666 stats[EF10_STAT_rx_broadcast];
1667 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1668 stats[EF10_STAT_tx_multicast] +
1669 stats[EF10_STAT_tx_broadcast];
1670 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1671 stats[EF10_STAT_rx_multicast_bytes] +
1672 stats[EF10_STAT_rx_broadcast_bytes];
1673 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1674 stats[EF10_STAT_tx_multicast_bytes] +
1675 stats[EF10_STAT_tx_broadcast_bytes];
1676 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1677 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1678 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1679 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1680 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1681 core_stats->rx_errors = core_stats->rx_crc_errors;
1682 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1683 } else {
1684 /* Use port stats. */
1685 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1686 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1687 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1688 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1689 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1690 stats[GENERIC_STAT_rx_nodesc_trunc] +
1691 stats[GENERIC_STAT_rx_noskb_drops];
1692 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1693 core_stats->rx_length_errors =
1694 stats[EF10_STAT_port_rx_gtjumbo] +
1695 stats[EF10_STAT_port_rx_length_error];
1696 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1697 core_stats->rx_frame_errors =
1698 stats[EF10_STAT_port_rx_align_error];
1699 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1700 core_stats->rx_errors = (core_stats->rx_length_errors +
1701 core_stats->rx_crc_errors +
1702 core_stats->rx_frame_errors);
d7788196
DP		 1703 }
1704
1705 return stats_count;
1706}
1707
1708static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1709{
1710 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1711 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1712 __le64 generation_start, generation_end;
1713 u64 *stats = nic_data->stats;
1714 __le64 *dma_stats;
1715
4bae913b
EC		 1716 efx_ef10_get_stat_mask(efx, mask);
1717
8127d661 1718 dma_stats = efx->stats_buffer.addr;
8127d661
BH		 1719
1720 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1721 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1722 return 0;
1723 rmb();
4bae913b 1724 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1725 stats, efx->stats_buffer.addr, false);
d546a893 1726 rmb();
8127d661
BH		 1727 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1728 if (generation_end != generation_start)
1729 return -EAGAIN;
1730
1731 /* Update derived statistics */
e80ca013
DP		 1732 efx_nic_fix_nodesc_drop_stat(efx,
1733 &stats[EF10_STAT_port_rx_nodesc_drops]);
1734 stats[EF10_STAT_port_rx_good_bytes] =
1735 stats[EF10_STAT_port_rx_bytes] -
1736 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1737 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1738 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1739 efx_update_sw_stats(efx, stats);
8127d661
BH		 1740 return 0;
1741}
1742
1743
d7788196
DP		 1744static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1745 struct rtnl_link_stats64 *core_stats)
8127d661 1746{
8127d661
BH		 1747 int retry;
1748
1749 /* If we're unlucky enough to read statistics during the DMA, wait
1750 * up to 10ms for it to finish (typically takes <500us)
1751 */
1752 for (retry = 0; retry < 100; ++retry) {
d7788196 1753 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1754 break;
1755 udelay(100);
1756 }
1757
d7788196
DP		 1758 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1759}
8127d661 1760
d7788196
DP		 1761static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1762{
1763 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1764 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1765 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1766 __le64 generation_start, generation_end;
1767 u64 *stats = nic_data->stats;
1768 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1769 struct efx_buffer stats_buf;
1770 __le64 *dma_stats;
1771 int rc;
1772
f00bf230
DP		 1773 spin_unlock_bh(&efx->stats_lock);
1774
1775 if (in_interrupt()) {
1776 /* If in atomic context, cannot update stats. Just update the
1777 * software stats and return so the caller can continue.
1778 */
1779 spin_lock_bh(&efx->stats_lock);
1780 efx_update_sw_stats(efx, stats);
1781 return 0;
1782 }
1783
d7788196
DP		 1784 efx_ef10_get_stat_mask(efx, mask);
1785
1786 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1787 if (rc) {
1788 spin_lock_bh(&efx->stats_lock);
d7788196 1789 return rc;
f00bf230 1790 }
d7788196
DP		 1791
1792 dma_stats = stats_buf.addr;
1793 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1794
1795 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1796 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1797 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1798 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1799 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1800
6dd4859b
DP		 1801 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1802 NULL, 0, NULL);
d7788196 1803 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1804 if (rc) {
1805 /* Expect ENOENT if DMA queues have not been set up */
1806 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1807 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1808 sizeof(inbuf), NULL, 0, rc);
d7788196 1809 goto out;
6dd4859b 1810 }
d7788196
DP		 1811
1812 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1813 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1814 WARN_ON_ONCE(1);
d7788196 1815 goto out;
0fc95fca 1816 }
d7788196
DP		 1817 rmb();
1818 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1819 stats, stats_buf.addr, false);
1820 rmb();
1821 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1822 if (generation_end != generation_start) {
1823 rc = -EAGAIN;
1824 goto out;
8127d661
BH		 1825 }
1826
d7788196
DP		 1827 efx_update_sw_stats(efx, stats);
1828out:
1829 efx_nic_free_buffer(efx, &stats_buf);
1830 return rc;
1831}
1832
1833static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1834 struct rtnl_link_stats64 *core_stats)
1835{
1836 if (efx_ef10_try_update_nic_stats_vf(efx))
1837 return 0;
1838
1839 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1840}
1841
1842static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1843{
1844 struct efx_nic *efx = channel->efx;
539de7c5 1845 unsigned int mode, usecs;
8127d661
BH		 1846 efx_dword_t timer_cmd;
1847
539de7c5 1848 if (channel->irq_moderation_us) {
8127d661 1849 mode = 3;
539de7c5 1850 usecs = channel->irq_moderation_us;
8127d661
BH		 1851 } else {
1852 mode = 0;
539de7c5 1853 usecs = 0;
8127d661
BH		 1854 }
1855
539de7c5
BK		 1856 if (EFX_EF10_WORKAROUND_61265(efx)) {
1857 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1858 unsigned int ns = usecs * 1000;
1859
1860 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1861 channel->channel);
1862 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1863 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1864 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1865
1866 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1867 inbuf, sizeof(inbuf), 0, NULL, 0);
1868 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1869 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1870
8127d661
BH		 1871 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1872 EFE_DD_EVQ_IND_TIMER_FLAGS,
1873 ERF_DD_EVQ_IND_TIMER_MODE, mode,
539de7c5 1874 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
8127d661
BH		 1875 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1876 channel->channel);
1877 } else {
539de7c5
BK		 1878 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1879
8127d661 1880 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
539de7c5 1881 ERF_DZ_TC_TIMER_VAL, ticks);
8127d661
BH		 1882 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1883 channel->channel);
1884 }
1885}
1886
02246a7f
SS		 1887static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1888 struct ethtool_wolinfo *wol) {}
1889
1890static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1891{
1892 return -EOPNOTSUPP;
1893}
1894
8127d661
BH		 1895static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1896{
1897 wol->supported = 0;
1898 wol->wolopts = 0;
1899 memset(&wol->sopass, 0, sizeof(wol->sopass));
1900}
1901
1902static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1903{
1904 if (type != 0)
1905 return -EINVAL;
1906 return 0;
1907}
1908
1909static void efx_ef10_mcdi_request(struct efx_nic *efx,
1910 const efx_dword_t *hdr, size_t hdr_len,
1911 const efx_dword_t *sdu, size_t sdu_len)
1912{
1913 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1914 u8 *pdu = nic_data->mcdi_buf.addr;
1915
1916 memcpy(pdu, hdr, hdr_len);
1917 memcpy(pdu + hdr_len, sdu, sdu_len);
1918 wmb();
1919
1920 /* The hardware provides 'low' and 'high' (doorbell) registers
1921 * for passing the 64-bit address of an MCDI request to
1922 * firmware. However the dwords are swapped by firmware. The
1923 * least significant bits of the doorbell are then 0 for all
1924 * MCDI requests due to alignment.
1925 */
1926 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1927 ER_DZ_MC_DB_LWRD);
1928 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1929 ER_DZ_MC_DB_HWRD);
1930}
1931
1932static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1933{
1934 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1935 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1936
1937 rmb();
1938 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1939}
1940
1941static void
1942efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1943 size_t offset, size_t outlen)
1944{
1945 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1946 const u8 *pdu = nic_data->mcdi_buf.addr;
1947
1948 memcpy(outbuf, pdu + offset, outlen);
1949}
1950
c577e59e
DP		 1951static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1952{
1953 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1954
1955 /* All our allocations have been reset */
1956 efx_ef10_reset_mc_allocations(efx);
1957
1958 /* The datapath firmware might have been changed */
1959 nic_data->must_check_datapath_caps = true;
1960
1961 /* MAC statistics have been cleared on the NIC; clear the local
1962 * statistic that we update with efx_update_diff_stat().
1963 */
1964 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1965}
1966
8127d661
BH		 1967static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1968{
1969 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1970 int rc;
1971
1972 rc = efx_ef10_get_warm_boot_count(efx);
1973 if (rc < 0) {
1974 /* The firmware is presumably in the process of
1975 * rebooting. However, we are supposed to report each
1976 * reboot just once, so we must only do that once we
1977 * can read and store the updated warm boot count.
1978 */
1979 return 0;
1980 }
1981
1982 if (rc == nic_data->warm_boot_count)
1983 return 0;
1984
1985 nic_data->warm_boot_count = rc;
c577e59e 1986 efx_ef10_mcdi_reboot_detected(efx);
869070c5 1987
8127d661
BH		 1988 return -EIO;
1989}
1990
1991/* Handle an MSI interrupt
1992 *
1993 * Handle an MSI hardware interrupt. This routine schedules event
1994 * queue processing. No interrupt acknowledgement cycle is necessary.
1995 * Also, we never need to check that the interrupt is for us, since
1996 * MSI interrupts cannot be shared.
1997 */
1998static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1999{
2000 struct efx_msi_context *context = dev_id;
2001 struct efx_nic *efx = context->efx;
2002
2003 netif_vdbg(efx, intr, efx->net_dev,
2004 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2005
2006 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2007 /* Note test interrupts */
2008 if (context->index == efx->irq_level)
2009 efx->last_irq_cpu = raw_smp_processor_id();
2010
2011 /* Schedule processing of the channel */
2012 efx_schedule_channel_irq(efx->channel[context->index]);
2013 }
2014
2015 return IRQ_HANDLED;
2016}
2017
2018static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2019{
2020 struct efx_nic *efx = dev_id;
2021 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2022 struct efx_channel *channel;
2023 efx_dword_t reg;
2024 u32 queues;
2025
2026 /* Read the ISR which also ACKs the interrupts */
2027 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2028 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2029
2030 if (queues == 0)
2031 return IRQ_NONE;
2032
2033 if (likely(soft_enabled)) {
2034 /* Note test interrupts */
2035 if (queues & (1U << efx->irq_level))
2036 efx->last_irq_cpu = raw_smp_processor_id();
2037
2038 efx_for_each_channel(channel, efx) {
2039 if (queues & 1)
2040 efx_schedule_channel_irq(channel);
2041 queues >>= 1;
2042 }
2043 }
2044
2045 netif_vdbg(efx, intr, efx->net_dev,
2046 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2047 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2048
2049 return IRQ_HANDLED;
2050}
2051
942e298e 2052static int efx_ef10_irq_test_generate(struct efx_nic *efx)
8127d661
BH		 2053{
2054 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2055
942e298e
JC		 2056 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2057 NULL) == 0)
2058 return -ENOTSUPP;
2059
8127d661
BH		 2060 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2061
2062 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
942e298e 2063 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
8127d661
BH		 2064 inbuf, sizeof(inbuf), NULL, 0, NULL);
2065}
2066
2067static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2068{
2069 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2070 (tx_queue->ptr_mask + 1) *
2071 sizeof(efx_qword_t),
2072 GFP_KERNEL);
2073}
2074
2075/* This writes to the TX_DESC_WPTR and also pushes data */
2076static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2077 const efx_qword_t *txd)
2078{
2079 unsigned int write_ptr;
2080 efx_oword_t reg;
2081
2082 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2083 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2084 reg.qword[0] = *txd;
2085 efx_writeo_page(tx_queue->efx, &reg,
2086 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2087}
2088
2089static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2090{
2091 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2092 EFX_BUF_SIZE));
8127d661
BH		 2093 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2094 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2095 struct efx_channel *channel = tx_queue->channel;
2096 struct efx_nic *efx = tx_queue->efx;
45b2449e 2097 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2098 size_t inlen;
8127d661
BH		 2099 dma_addr_t dma_addr;
2100 efx_qword_t *txd;
2101 int rc;
2102 int i;
aa09a3da 2103 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661
BH		 2104
2105 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2106 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2107 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2108 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2109 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
2110 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2111 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2112 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 2113 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2114
2115 dma_addr = tx_queue->txd.buf.dma_addr;
2116
2117 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2118 tx_queue->queue, entries, (u64)dma_addr);
2119
2120 for (i = 0; i < entries; ++i) {
2121 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2122 dma_addr += EFX_BUF_SIZE;
2123 }
2124
2125 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2126
2127 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
aa09a3da 2128 NULL, 0, NULL);
8127d661
BH		 2129 if (rc)
2130 goto fail;
2131
2132 /* A previous user of this TX queue might have set us up the
2133 * bomb by writing a descriptor to the TX push collector but
2134 * not the doorbell. (Each collector belongs to a port, not a
2135 * queue or function, so cannot easily be reset.) We must
2136 * attempt to push a no-op descriptor in its place.
2137 */
2138 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2139 tx_queue->insert_count = 1;
2140 txd = efx_tx_desc(tx_queue, 0);
2141 EFX_POPULATE_QWORD_4(*txd,
2142 ESF_DZ_TX_DESC_IS_OPT, true,
2143 ESF_DZ_TX_OPTION_TYPE,
2144 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2145 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2146 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2147 tx_queue->write_count = 1;
93171b14
BK		 2148
2149 if (nic_data->datapath_caps &
2150 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2151 tx_queue->tso_version = 1;
2152 }
2153
8127d661
BH		 2154 wmb();
2155 efx_ef10_push_tx_desc(tx_queue, txd);
2156
2157 return;
2158
2159fail:
48ce5634
BH		 2160 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2161 tx_queue->queue);
8127d661
BH		 2162}
2163
2164static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2165{
2166 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 2167 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2168 struct efx_nic *efx = tx_queue->efx;
2169 size_t outlen;
2170 int rc;
2171
2172 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2173 tx_queue->queue);
2174
1e0b8120 2175 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2176 outbuf, sizeof(outbuf), &outlen);
2177
2178 if (rc && rc != -EALREADY)
2179 goto fail;
2180
2181 return;
2182
2183fail:
1e0b8120
EC		 2184 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2185 outbuf, outlen, rc);
8127d661
BH		 2186}
2187
2188static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2189{
2190 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2191}
2192
2193/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2194static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2195{
2196 unsigned int write_ptr;
2197 efx_dword_t reg;
2198
2199 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2200 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2201 efx_writed_page(tx_queue->efx, &reg,
2202 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2203}
2204
2205static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2206{
2207 unsigned int old_write_count = tx_queue->write_count;
2208 struct efx_tx_buffer *buffer;
2209 unsigned int write_ptr;
2210 efx_qword_t *txd;
2211
b2663a4f
MH		 2212 tx_queue->xmit_more_available = false;
2213 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2214 return;
8127d661
BH		 2215
2216 do {
2217 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2218 buffer = &tx_queue->buffer[write_ptr];
2219 txd = efx_tx_desc(tx_queue, write_ptr);
2220 ++tx_queue->write_count;
2221
2222 /* Create TX descriptor ring entry */
2223 if (buffer->flags & EFX_TX_BUF_OPTION) {
2224 *txd = buffer->option;
2225 } else {
2226 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2227 EFX_POPULATE_QWORD_3(
2228 *txd,
2229 ESF_DZ_TX_KER_CONT,
2230 buffer->flags & EFX_TX_BUF_CONT,
2231 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2232 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2233 }
2234 } while (tx_queue->write_count != tx_queue->insert_count);
2235
2236 wmb(); /* Ensure descriptors are written before they are fetched */
2237
2238 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2239 txd = efx_tx_desc(tx_queue,
2240 old_write_count & tx_queue->ptr_mask);
2241 efx_ef10_push_tx_desc(tx_queue, txd);
2242 ++tx_queue->pushes;
2243 } else {
2244 efx_ef10_notify_tx_desc(tx_queue);
2245 }
2246}
2247
a33a4c73
EC		 2248#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2249 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2250#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2251 1 << RSS_MODE_HASH_DST_PORT_LBN)
2252#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2253 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2254 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2255 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2256 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2257 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2258 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2259 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2260 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2261 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2262
2263static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2264{
2265 /* Firmware had a bug (sfc bug 61952) where it would not actually
2266 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2267 * This meant that it would always contain whatever was previously
2268 * in the MCDI buffer. Fortunately, all firmware versions with
2269 * this bug have the same default flags value for a newly-allocated
2270 * RSS context, and the only time we want to get the flags is just
2271 * after allocating. Moreover, the response has a 32-bit hole
2272 * where the context ID would be in the request, so we can use an
2273 * overlength buffer in the request and pre-fill the flags field
2274 * with what we believe the default to be. Thus if the firmware
2275 * has the bug, it will leave our pre-filled value in the flags
2276 * field of the response, and we will get the right answer.
2277 *
2278 * However, this does mean that this function should NOT be used if
2279 * the RSS context flags might not be their defaults - it is ONLY
2280 * reliably correct for a newly-allocated RSS context.
2281 */
2282 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2283 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2284 size_t outlen;
2285 int rc;
2286
2287 /* Check we have a hole for the context ID */
2288 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2289 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2290 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2291 RSS_CONTEXT_FLAGS_DEFAULT);
2292 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2293 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2294 if (rc == 0) {
2295 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2296 rc = -EIO;
2297 else
2298 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2299 }
2300 return rc;
2301}
2302
2303/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2304 * If we fail, we just leave the RSS context at its default hash settings,
2305 * which is safe but may slightly reduce performance.
2306 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2307 * just need to set the UDP ports flags (for both IP versions).
2308 */
2309static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2310{
2311 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2312 u32 flags;
2313
2314 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2315
2316 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2317 return;
2318 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2319 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2320 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2321 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
b718c88a
EC		 2322 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2323 NULL, 0, NULL))
2324 /* Succeeded, so UDP 4-tuple is now enabled */
2325 efx->rx_hash_udp_4tuple = true;
a33a4c73
EC		 2326}
2327
267c0157
JC		 2328static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2329 bool exclusive, unsigned *context_size)
8127d661
BH		 2330{
2331 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2332 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 2333 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 2334 size_t outlen;
2335 int rc;
267c0157
JC		 2336 u32 alloc_type = exclusive ?
2337 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2338 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2339 unsigned rss_spread = exclusive ?
2340 efx->rss_spread :
2341 min(rounddown_pow_of_two(efx->rss_spread),
2342 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2343
2344 if (!exclusive && rss_spread == 1) {
2345 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2346 if (context_size)
2347 *context_size = 1;
2348 return 0;
2349 }
8127d661 2350
dcb4123c
JC		 2351 if (nic_data->datapath_caps &
2352 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2353 return -EOPNOTSUPP;
2354
8127d661 2355 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 2356 nic_data->vport_id);
267c0157
JC		 2357 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2358 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 2359
2360 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2361 outbuf, sizeof(outbuf), &outlen);
2362 if (rc != 0)
2363 return rc;
2364
2365 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2366 return -EIO;
2367
2368 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2369
267c0157
JC		 2370 if (context_size)
2371 *context_size = rss_spread;
2372
a33a4c73
EC		 2373 if (nic_data->datapath_caps &
2374 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2375 efx_ef10_set_rss_flags(efx, *context);
2376
8127d661
BH		 2377 return 0;
2378}
2379
2380static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2381{
2382 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2383 int rc;
2384
2385 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2386 context);
2387
2388 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2389 NULL, 0, NULL);
2390 WARN_ON(rc != 0);
2391}
2392
267c0157
JC		 2393static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2394 const u32 *rx_indir_table)
8127d661
BH		 2395{
2396 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2397 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2398 int i, rc;
2399
2400 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2401 context);
2402 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2403 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2404
2405 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2406 MCDI_PTR(tablebuf,
2407 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 2408 (u8) rx_indir_table[i];
8127d661
BH		 2409
2410 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2411 sizeof(tablebuf), NULL, 0, NULL);
2412 if (rc != 0)
2413 return rc;
2414
2415 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2416 context);
2417 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2418 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2419 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2420 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2421 efx->rx_hash_key[i];
2422
2423 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2424 sizeof(keybuf), NULL, 0, NULL);
2425}
2426
2427static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2428{
2429 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2430
2431 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2432 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2433 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2434}
2435
267c0157
JC		 2436static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2437 unsigned *context_size)
8127d661 2438{
267c0157 2439 u32 new_rx_rss_context;
8127d661 2440 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 2441 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2442 false, context_size);
2443
2444 if (rc != 0)
2445 return rc;
8127d661 2446
267c0157
JC		 2447 nic_data->rx_rss_context = new_rx_rss_context;
2448 nic_data->rx_rss_context_exclusive = false;
2449 efx_set_default_rx_indir_table(efx);
2450 return 0;
2451}
8127d661 2452
267c0157
JC		 2453static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2454 const u32 *rx_indir_table)
2455{
2456 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2457 int rc;
2458 u32 new_rx_rss_context;
2459
2460 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2461 !nic_data->rx_rss_context_exclusive) {
2462 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2463 true, NULL);
2464 if (rc == -EOPNOTSUPP)
2465 return rc;
2466 else if (rc != 0)
2467 goto fail1;
2468 } else {
2469 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2470 }
2471
267c0157
JC		 2472 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2473 rx_indir_table);
8127d661 2474 if (rc != 0)
267c0157 2475 goto fail2;
8127d661 2476
267c0157
JC		 2477 if (nic_data->rx_rss_context != new_rx_rss_context)
2478 efx_ef10_rx_free_indir_table(efx);
2479 nic_data->rx_rss_context = new_rx_rss_context;
2480 nic_data->rx_rss_context_exclusive = true;
2481 if (rx_indir_table != efx->rx_indir_table)
2482 memcpy(efx->rx_indir_table, rx_indir_table,
2483 sizeof(efx->rx_indir_table));
2484 return 0;
8127d661 2485
267c0157
JC		 2486fail2:
2487 if (new_rx_rss_context != nic_data->rx_rss_context)
2488 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2489fail1:
8127d661 2490 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2491 return rc;
2492}
2493
2494static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2495 const u32 *rx_indir_table)
2496{
2497 int rc;
2498
2499 if (efx->rss_spread == 1)
2500 return 0;
2501
2502 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2503
2504 if (rc == -ENOBUFS && !user) {
2505 unsigned context_size;
2506 bool mismatch = false;
2507 size_t i;
2508
2509 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2510 i++)
2511 mismatch = rx_indir_table[i] !=
2512 ethtool_rxfh_indir_default(i, efx->rss_spread);
2513
2514 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2515 if (rc == 0) {
2516 if (context_size != efx->rss_spread)
2517 netif_warn(efx, probe, efx->net_dev,
2518 "Could not allocate an exclusive RSS"
2519 " context; allocated a shared one of"
2520 " different size."
2521 " Wanted %u, got %u.\n",
2522 efx->rss_spread, context_size);
2523 else if (mismatch)
2524 netif_warn(efx, probe, efx->net_dev,
2525 "Could not allocate an exclusive RSS"
2526 " context; allocated a shared one but"
2527 " could not apply custom"
2528 " indirection.\n");
2529 else
2530 netif_info(efx, probe, efx->net_dev,
2531 "Could not allocate an exclusive RSS"
2532 " context; allocated a shared one.\n");
2533 }
2534 }
2535 return rc;
2536}
2537
2538static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2539 const u32 *rx_indir_table
2540 __attribute__ ((unused)))
2541{
2542 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2543
2544 if (user)
2545 return -EOPNOTSUPP;
2546 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2547 return 0;
2548 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2549}
2550
2551static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2552{
2553 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2554 (rx_queue->ptr_mask + 1) *
2555 sizeof(efx_qword_t),
2556 GFP_KERNEL);
2557}
2558
2559static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2560{
2561 MCDI_DECLARE_BUF(inbuf,
2562 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2563 EFX_BUF_SIZE));
8127d661
BH		 2564 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2565 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2566 struct efx_nic *efx = rx_queue->efx;
45b2449e 2567 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2568 size_t inlen;
8127d661
BH		 2569 dma_addr_t dma_addr;
2570 int rc;
2571 int i;
aa09a3da 2572 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2573
2574 rx_queue->scatter_n = 0;
2575 rx_queue->scatter_len = 0;
2576
2577 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2578 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2579 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2580 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2581 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2582 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2583 INIT_RXQ_IN_FLAG_PREFIX, 1,
2584 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2585 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2586 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2587
2588 dma_addr = rx_queue->rxd.buf.dma_addr;
2589
2590 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2591 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2592
2593 for (i = 0; i < entries; ++i) {
2594 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2595 dma_addr += EFX_BUF_SIZE;
2596 }
2597
2598 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2599
2600 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2601 NULL, 0, NULL);
48ce5634
BH		 2602 if (rc)
2603 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2604 efx_rx_queue_index(rx_queue));
8127d661
BH		 2605}
2606
2607static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2608{
2609 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2610 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2611 struct efx_nic *efx = rx_queue->efx;
2612 size_t outlen;
2613 int rc;
2614
2615 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2616 efx_rx_queue_index(rx_queue));
2617
1e0b8120 2618 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2619 outbuf, sizeof(outbuf), &outlen);
2620
2621 if (rc && rc != -EALREADY)
2622 goto fail;
2623
2624 return;
2625
2626fail:
1e0b8120
EC		 2627 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2628 outbuf, outlen, rc);
8127d661
BH		 2629}
2630
2631static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2632{
2633 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2634}
2635
2636/* This creates an entry in the RX descriptor queue */
2637static inline void
2638efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2639{
2640 struct efx_rx_buffer *rx_buf;
2641 efx_qword_t *rxd;
2642
2643 rxd = efx_rx_desc(rx_queue, index);
2644 rx_buf = efx_rx_buffer(rx_queue, index);
2645 EFX_POPULATE_QWORD_2(*rxd,
2646 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2647 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2648}
2649
2650static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2651{
2652 struct efx_nic *efx = rx_queue->efx;
2653 unsigned int write_count;
2654 efx_dword_t reg;
2655
2656 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2657 write_count = rx_queue->added_count & ~7;
2658 if (rx_queue->notified_count == write_count)
2659 return;
2660
2661 do
2662 efx_ef10_build_rx_desc(
2663 rx_queue,
2664 rx_queue->notified_count & rx_queue->ptr_mask);
2665 while (++rx_queue->notified_count != write_count);
2666
2667 wmb();
2668 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2669 write_count & rx_queue->ptr_mask);
2670 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2671 efx_rx_queue_index(rx_queue));
2672}
2673
2674static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2675
2676static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2677{
2678 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2679 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2680 efx_qword_t event;
2681
2682 EFX_POPULATE_QWORD_2(event,
2683 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2684 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2685
2686 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2687
2688 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2689 * already swapped the data to little-endian order.
2690 */
2691 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2692 sizeof(efx_qword_t));
2693
2694 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2695 inbuf, sizeof(inbuf), 0,
2696 efx_ef10_rx_defer_refill_complete, 0);
2697}
2698
2699static void
2700efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2701 int rc, efx_dword_t *outbuf,
2702 size_t outlen_actual)
2703{
2704 /* nothing to do */
2705}
2706
2707static int efx_ef10_ev_probe(struct efx_channel *channel)
2708{
2709 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2710 (channel->eventq_mask + 1) *
2711 sizeof(efx_qword_t),
2712 GFP_KERNEL);
2713}
2714
46e612b0
DP		 2715static void efx_ef10_ev_fini(struct efx_channel *channel)
2716{
2717 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2718 MCDI_DECLARE_BUF_ERR(outbuf);
2719 struct efx_nic *efx = channel->efx;
2720 size_t outlen;
2721 int rc;
2722
2723 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2724
2725 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2726 outbuf, sizeof(outbuf), &outlen);
2727
2728 if (rc && rc != -EALREADY)
2729 goto fail;
2730
2731 return;
2732
2733fail:
2734 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2735 outbuf, outlen, rc);
2736}
2737
8127d661
BH		 2738static int efx_ef10_ev_init(struct efx_channel *channel)
2739{
2740 MCDI_DECLARE_BUF(inbuf,
a995560a
BK		 2741 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2742 EFX_BUF_SIZE));
2743 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
8127d661
BH		 2744 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2745 struct efx_nic *efx = channel->efx;
2746 struct efx_ef10_nic_data *nic_data;
8127d661 2747 size_t inlen, outlen;
46e612b0 2748 unsigned int enabled, implemented;
8127d661
BH		 2749 dma_addr_t dma_addr;
2750 int rc;
2751 int i;
2752
2753 nic_data = efx->nic_data;
8127d661
BH		 2754
2755 /* Fill event queue with all ones (i.e. empty events) */
2756 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2757
2758 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2759 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2760 /* INIT_EVQ expects index in vector table, not absolute */
2761 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
8127d661
BH		 2762 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2763 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2764 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2765 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2766 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2767 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2768 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2769
a995560a
BK		 2770 if (nic_data->datapath_caps2 &
2771 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
2772 /* Use the new generic approach to specifying event queue
2773 * configuration, requesting lower latency or higher throughput.
2774 * The options that actually get used appear in the output.
2775 */
2776 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
2777 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
2778 INIT_EVQ_V2_IN_FLAG_TYPE,
2779 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
2780 } else {
2781 bool cut_thru = !(nic_data->datapath_caps &
2782 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2783
2784 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2785 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2786 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2787 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2788 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
2789 }
2790
8127d661
BH		 2791 dma_addr = channel->eventq.buf.dma_addr;
2792 for (i = 0; i < entries; ++i) {
2793 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2794 dma_addr += EFX_BUF_SIZE;
2795 }
2796
2797 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2798
2799 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2800 outbuf, sizeof(outbuf), &outlen);
a995560a
BK		 2801
2802 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
2803 netif_dbg(efx, drv, efx->net_dev,
2804 "Channel %d using event queue flags %08x\n",
2805 channel->channel,
2806 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
2807
8127d661 2808 /* IRQ return is ignored */
46e612b0
DP		 2809 if (channel->channel || rc)
2810 return rc;
8127d661 2811
46e612b0
DP		 2812 /* Successfully created event queue on channel 0 */
2813 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed 2814 if (rc == -ENOSYS) {
d95e329a
BK		 2815 /* GET_WORKAROUNDS was implemented before this workaround,
2816 * thus it must be unavailable in this firmware.
832dc9ed
EC		 2817 */
2818 nic_data->workaround_26807 = false;
2819 rc = 0;
2820 } else if (rc) {
8127d661 2821 goto fail;
832dc9ed
EC		 2822 } else {
2823 nic_data->workaround_26807 =
2824 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2825
2826 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2827 !nic_data->workaround_26807) {
5a55a72a
DP		 2828 unsigned int flags;
2829
34ccfe6f
DP		 2830 rc = efx_mcdi_set_workaround(efx,
2831 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 2832 true, &flags);
2833
2834 if (!rc) {
2835 if (flags &
2836 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2837 netif_info(efx, drv, efx->net_dev,
2838 "other functions on NIC have been reset\n");
abd86a55
DP		 2839
2840 /* With MCFW v4.6.x and earlier, the
2841 * boot count will have incremented,
2842 * so re-read the warm_boot_count
2843 * value now to ensure this function
2844 * doesn't think it has changed next
2845 * time it checks.
2846 */
2847 rc = efx_ef10_get_warm_boot_count(efx);
2848 if (rc >= 0) {
2849 nic_data->warm_boot_count = rc;
2850 rc = 0;
2851 }
5a55a72a 2852 }
832dc9ed 2853 nic_data->workaround_26807 = true;
5a55a72a 2854 } else if (rc == -EPERM) {
832dc9ed 2855 rc = 0;
5a55a72a 2856 }
832dc9ed 2857 }
46e612b0
DP		 2858 }
2859
2860 if (!rc)
2861 return 0;
8127d661
BH		 2862
2863fail:
46e612b0
DP		 2864 efx_ef10_ev_fini(channel);
2865 return rc;
8127d661
BH		 2866}
2867
2868static void efx_ef10_ev_remove(struct efx_channel *channel)
2869{
2870 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2871}
2872
2873static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2874 unsigned int rx_queue_label)
2875{
2876 struct efx_nic *efx = rx_queue->efx;
2877
2878 netif_info(efx, hw, efx->net_dev,
2879 "rx event arrived on queue %d labeled as queue %u\n",
2880 efx_rx_queue_index(rx_queue), rx_queue_label);
2881
2882 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2883}
2884
2885static void
2886efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2887 unsigned int actual, unsigned int expected)
2888{
2889 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2890 struct efx_nic *efx = rx_queue->efx;
2891
2892 netif_info(efx, hw, efx->net_dev,
2893 "dropped %d events (index=%d expected=%d)\n",
2894 dropped, actual, expected);
2895
2896 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2897}
2898
2899/* partially received RX was aborted. clean up. */
2900static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2901{
2902 unsigned int rx_desc_ptr;
2903
8127d661
BH		 2904 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2905 "scattered RX aborted (dropping %u buffers)\n",
2906 rx_queue->scatter_n);
2907
2908 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2909
2910 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2911 0, EFX_RX_PKT_DISCARD);
2912
2913 rx_queue->removed_count += rx_queue->scatter_n;
2914 rx_queue->scatter_n = 0;
2915 rx_queue->scatter_len = 0;
2916 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2917}
2918
2919static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2920 const efx_qword_t *event)
2921{
2922 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2923 unsigned int n_descs, n_packets, i;
2924 struct efx_nic *efx = channel->efx;
2925 struct efx_rx_queue *rx_queue;
2926 bool rx_cont;
2927 u16 flags = 0;
2928
2929 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2930 return 0;
2931
2932 /* Basic packet information */
2933 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2934 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2935 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2936 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2937 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2938
48ce5634
BH		 2939 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2940 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2941 EFX_QWORD_FMT "\n",
2942 EFX_QWORD_VAL(*event));
8127d661
BH		 2943
2944 rx_queue = efx_channel_get_rx_queue(channel);
2945
2946 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2947 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2948
2949 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2950 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2951
2952 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 2953 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2954
8127d661
BH		 2955 /* detect rx abort */
2956 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2957 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2958 netdev_WARN(efx->net_dev,
2959 "invalid RX abort: scatter_n=%u event="
2960 EFX_QWORD_FMT "\n",
2961 rx_queue->scatter_n,
2962 EFX_QWORD_VAL(*event));
8127d661
BH		 2963 efx_ef10_handle_rx_abort(rx_queue);
2964 return 0;
2965 }
2966
92a04168
BH		 2967 /* Check that RX completion merging is valid, i.e.
2968 * the current firmware supports it and this is a
2969 * non-scattered packet.
2970 */
2971 if (!(nic_data->datapath_caps &
2972 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2973 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2974 efx_ef10_handle_rx_bad_lbits(
2975 rx_queue, next_ptr_lbits,
2976 (rx_queue->removed_count +
2977 rx_queue->scatter_n + 1) &
2978 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2979 return 0;
2980 }
2981
2982 /* Merged completion for multiple non-scattered packets */
2983 rx_queue->scatter_n = 1;
2984 rx_queue->scatter_len = 0;
2985 n_packets = n_descs;
2986 ++channel->n_rx_merge_events;
2987 channel->n_rx_merge_packets += n_packets;
2988 flags |= EFX_RX_PKT_PREFIX_LEN;
2989 } else {
2990 ++rx_queue->scatter_n;
2991 rx_queue->scatter_len += rx_bytes;
2992 if (rx_cont)
2993 return 0;
2994 n_packets = 1;
2995 }
2996
2997 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2998 flags |= EFX_RX_PKT_DISCARD;
2999
3000 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
3001 channel->n_rx_ip_hdr_chksum_err += n_packets;
3002 } else if (unlikely(EFX_QWORD_FIELD(*event,
3003 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
3004 channel->n_rx_tcp_udp_chksum_err += n_packets;
3005 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3006 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
3007 flags |= EFX_RX_PKT_CSUMMED;
3008 }
3009
3010 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3011 flags |= EFX_RX_PKT_TCP;
3012
3013 channel->irq_mod_score += 2 * n_packets;
3014
3015 /* Handle received packet(s) */
3016 for (i = 0; i < n_packets; i++) {
3017 efx_rx_packet(rx_queue,
3018 rx_queue->removed_count & rx_queue->ptr_mask,
3019 rx_queue->scatter_n, rx_queue->scatter_len,
3020 flags);
3021 rx_queue->removed_count += rx_queue->scatter_n;
3022 }
3023
3024 rx_queue->scatter_n = 0;
3025 rx_queue->scatter_len = 0;
3026
3027 return n_packets;
3028}
3029
3030static int
3031efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3032{
3033 struct efx_nic *efx = channel->efx;
3034 struct efx_tx_queue *tx_queue;
3035 unsigned int tx_ev_desc_ptr;
3036 unsigned int tx_ev_q_label;
3037 int tx_descs = 0;
3038
3039 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3040 return 0;
3041
3042 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3043 return 0;
3044
3045 /* Transmit completion */
3046 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3047 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3048 tx_queue = efx_channel_get_tx_queue(channel,
3049 tx_ev_q_label % EFX_TXQ_TYPES);
3050 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3051 tx_queue->ptr_mask);
3052 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3053
3054 return tx_descs;
3055}
3056
3057static void
3058efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3059{
3060 struct efx_nic *efx = channel->efx;
3061 int subcode;
3062
3063 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3064
3065 switch (subcode) {
3066 case ESE_DZ_DRV_TIMER_EV:
3067 case ESE_DZ_DRV_WAKE_UP_EV:
3068 break;
3069 case ESE_DZ_DRV_START_UP_EV:
3070 /* event queue init complete. ok. */
3071 break;
3072 default:
3073 netif_err(efx, hw, efx->net_dev,
3074 "channel %d unknown driver event type %d"
3075 " (data " EFX_QWORD_FMT ")\n",
3076 channel->channel, subcode,
3077 EFX_QWORD_VAL(*event));
3078
3079 }
3080}
3081
3082static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3083 efx_qword_t *event)
3084{
3085 struct efx_nic *efx = channel->efx;
3086 u32 subcode;
3087
3088 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3089
3090 switch (subcode) {
3091 case EFX_EF10_TEST:
3092 channel->event_test_cpu = raw_smp_processor_id();
3093 break;
3094 case EFX_EF10_REFILL:
3095 /* The queue must be empty, so we won't receive any rx
3096 * events, so efx_process_channel() won't refill the
3097 * queue. Refill it here
3098 */
cce28794 3099 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 3100 break;
3101 default:
3102 netif_err(efx, hw, efx->net_dev,
3103 "channel %d unknown driver event type %u"
3104 " (data " EFX_QWORD_FMT ")\n",
3105 channel->channel, (unsigned) subcode,
3106 EFX_QWORD_VAL(*event));
3107 }
3108}
3109
3110static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3111{
3112 struct efx_nic *efx = channel->efx;
3113 efx_qword_t event, *p_event;
3114 unsigned int read_ptr;
3115 int ev_code;
3116 int tx_descs = 0;
3117 int spent = 0;
3118
75363a46
EB		 3119 if (quota <= 0)
3120 return spent;
3121
8127d661
BH		 3122 read_ptr = channel->eventq_read_ptr;
3123
3124 for (;;) {
3125 p_event = efx_event(channel, read_ptr);
3126 event = *p_event;
3127
3128 if (!efx_event_present(&event))
3129 break;
3130
3131 EFX_SET_QWORD(*p_event);
3132
3133 ++read_ptr;
3134
3135 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3136
3137 netif_vdbg(efx, drv, efx->net_dev,
3138 "processing event on %d " EFX_QWORD_FMT "\n",
3139 channel->channel, EFX_QWORD_VAL(event));
3140
3141 switch (ev_code) {
3142 case ESE_DZ_EV_CODE_MCDI_EV:
3143 efx_mcdi_process_event(channel, &event);
3144 break;
3145 case ESE_DZ_EV_CODE_RX_EV:
3146 spent += efx_ef10_handle_rx_event(channel, &event);
3147 if (spent >= quota) {
3148 /* XXX can we split a merged event to
3149 * avoid going over-quota?
3150 */
3151 spent = quota;
3152 goto out;
3153 }
3154 break;
3155 case ESE_DZ_EV_CODE_TX_EV:
3156 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3157 if (tx_descs > efx->txq_entries) {
3158 spent = quota;
3159 goto out;
3160 } else if (++spent == quota) {
3161 goto out;
3162 }
3163 break;
3164 case ESE_DZ_EV_CODE_DRIVER_EV:
3165 efx_ef10_handle_driver_event(channel, &event);
3166 if (++spent == quota)
3167 goto out;
3168 break;
3169 case EFX_EF10_DRVGEN_EV:
3170 efx_ef10_handle_driver_generated_event(channel, &event);
3171 break;
3172 default:
3173 netif_err(efx, hw, efx->net_dev,
3174 "channel %d unknown event type %d"
3175 " (data " EFX_QWORD_FMT ")\n",
3176 channel->channel, ev_code,
3177 EFX_QWORD_VAL(event));
3178 }
3179 }
3180
3181out:
3182 channel->eventq_read_ptr = read_ptr;
3183 return spent;
3184}
3185
3186static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3187{
3188 struct efx_nic *efx = channel->efx;
3189 efx_dword_t rptr;
3190
3191 if (EFX_EF10_WORKAROUND_35388(efx)) {
3192 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3193 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3194 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3195 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3196
3197 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3198 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3199 ERF_DD_EVQ_IND_RPTR,
3200 (channel->eventq_read_ptr &
3201 channel->eventq_mask) >>
3202 ERF_DD_EVQ_IND_RPTR_WIDTH);
3203 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3204 channel->channel);
3205 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3206 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3207 ERF_DD_EVQ_IND_RPTR,
3208 channel->eventq_read_ptr &
3209 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3210 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3211 channel->channel);
3212 } else {
3213 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3214 channel->eventq_read_ptr &
3215 channel->eventq_mask);
3216 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3217 }
3218}
3219
3220static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3221{
3222 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3223 struct efx_nic *efx = channel->efx;
3224 efx_qword_t event;
3225 int rc;
3226
3227 EFX_POPULATE_QWORD_2(event,
3228 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3229 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3230
3231 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3232
3233 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3234 * already swapped the data to little-endian order.
3235 */
3236 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3237 sizeof(efx_qword_t));
3238
3239 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3240 NULL, 0, NULL);
3241 if (rc != 0)
3242 goto fail;
3243
3244 return;
3245
3246fail:
3247 WARN_ON(true);
3248 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3249}
3250
3251void efx_ef10_handle_drain_event(struct efx_nic *efx)
3252{
3253 if (atomic_dec_and_test(&efx->active_queues))
3254 wake_up(&efx->flush_wq);
3255
3256 WARN_ON(atomic_read(&efx->active_queues) < 0);
3257}
3258
3259static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3260{
3261 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3262 struct efx_channel *channel;
3263 struct efx_tx_queue *tx_queue;
3264 struct efx_rx_queue *rx_queue;
3265 int pending;
3266
3267 /* If the MC has just rebooted, the TX/RX queues will have already been
3268 * torn down, but efx->active_queues needs to be set to zero.
3269 */
3270 if (nic_data->must_realloc_vis) {
3271 atomic_set(&efx->active_queues, 0);
3272 return 0;
3273 }
3274
3275 /* Do not attempt to write to the NIC during EEH recovery */
3276 if (efx->state != STATE_RECOVERY) {
3277 efx_for_each_channel(channel, efx) {
3278 efx_for_each_channel_rx_queue(rx_queue, channel)
3279 efx_ef10_rx_fini(rx_queue);
3280 efx_for_each_channel_tx_queue(tx_queue, channel)
3281 efx_ef10_tx_fini(tx_queue);
3282 }
3283
3284 wait_event_timeout(efx->flush_wq,
3285 atomic_read(&efx->active_queues) == 0,
3286 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3287 pending = atomic_read(&efx->active_queues);
3288 if (pending) {
3289 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3290 pending);
3291 return -ETIMEDOUT;
3292 }
3293 }
3294
3295 return 0;
3296}
3297
e283546c
EC		 3298static void efx_ef10_prepare_flr(struct efx_nic *efx)
3299{
3300 atomic_set(&efx->active_queues, 0);
3301}
3302
8127d661
BH		 3303static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3304 const struct efx_filter_spec *right)
3305{
3306 if ((left->match_flags ^ right->match_flags) |
3307 ((left->flags ^ right->flags) &
3308 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3309 return false;
3310
3311 return memcmp(&left->outer_vid, &right->outer_vid,
3312 sizeof(struct efx_filter_spec) -
3313 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3314}
3315
3316static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3317{
3318 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3319 return jhash2((const u32 *)&spec->outer_vid,
3320 (sizeof(struct efx_filter_spec) -
3321 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3322 0);
3323 /* XXX should we randomise the initval? */
3324}
3325
3326/* Decide whether a filter should be exclusive or else should allow
3327 * delivery to additional recipients. Currently we decide that
3328 * filters for specific local unicast MAC and IP addresses are
3329 * exclusive.
3330 */
3331static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3332{
3333 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3334 !is_multicast_ether_addr(spec->loc_mac))
3335 return true;
3336
3337 if ((spec->match_flags &
3338 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3339 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3340 if (spec->ether_type == htons(ETH_P_IP) &&
3341 !ipv4_is_multicast(spec->loc_host[0]))
3342 return true;
3343 if (spec->ether_type == htons(ETH_P_IPV6) &&
3344 ((const u8 *)spec->loc_host)[0] != 0xff)
3345 return true;
3346 }
3347
3348 return false;
3349}
3350
3351static struct efx_filter_spec *
3352efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3353 unsigned int filter_idx)
3354{
3355 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3356 ~EFX_EF10_FILTER_FLAGS);
3357}
3358
3359static unsigned int
3360efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3361 unsigned int filter_idx)
3362{
3363 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3364}
3365
3366static void
3367efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3368 unsigned int filter_idx,
3369 const struct efx_filter_spec *spec,
3370 unsigned int flags)
3371{
3372 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3373}
3374
3375static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3376 const struct efx_filter_spec *spec,
3377 efx_dword_t *inbuf, u64 handle,
3378 bool replacing)
3379{
3380 struct efx_ef10_nic_data *nic_data = efx->nic_data;
dcb4123c 3381 u32 flags = spec->flags;
8127d661
BH		 3382
3383 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3384
dcb4123c
JC		 3385 /* Remove RSS flag if we don't have an RSS context. */
3386 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3387 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3388 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3389 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3390
8127d661
BH		 3391 if (replacing) {
3392 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3393 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3394 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3395 } else {
3396 u32 match_fields = 0;
3397
3398 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3399 efx_ef10_filter_is_exclusive(spec) ?
3400 MC_CMD_FILTER_OP_IN_OP_INSERT :
3401 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3402
3403 /* Convert match flags and values. Unlike almost
3404 * everything else in MCDI, these fields are in
3405 * network byte order.
3406 */
3407 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3408 match_fields |=
3409 is_multicast_ether_addr(spec->loc_mac) ?
3410 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3411 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3412#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3413 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3414 match_fields |= \
3415 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3416 mcdi_field ## _LBN; \
3417 BUILD_BUG_ON( \
3418 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3419 sizeof(spec->gen_field)); \
3420 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3421 &spec->gen_field, sizeof(spec->gen_field)); \
3422 }
3423 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3424 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3425 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3426 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3427 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3428 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3429 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3430 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3431 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3432 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3433#undef COPY_FIELD
3434 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3435 match_fields);
3436 }
3437
45b2449e 3438 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 3439 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3440 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3441 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3442 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 3443 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 3444 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3445 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 3446 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3447 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3448 0 : spec->dmaq_id);
8127d661 3449 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
dcb4123c 3450 (flags & EFX_FILTER_FLAG_RX_RSS) ?
8127d661
BH		 3451 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3452 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
dcb4123c 3453 if (flags & EFX_FILTER_FLAG_RX_RSS)
8127d661
BH		 3454 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3455 spec->rss_context !=
3456 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3457 spec->rss_context : nic_data->rx_rss_context);
3458}
3459
3460static int efx_ef10_filter_push(struct efx_nic *efx,
3461 const struct efx_filter_spec *spec,
3462 u64 *handle, bool replacing)
3463{
3464 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3465 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3466 int rc;
3467
3468 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3469 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3470 outbuf, sizeof(outbuf), NULL);
3471 if (rc == 0)
3472 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 3473 if (rc == -ENOSPC)
3474 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 3475 return rc;
3476}
3477
7ac0dd9d 3478static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
8127d661 3479{
7ac0dd9d
AR		 3480 unsigned int match_flags = spec->match_flags;
3481 u32 mcdi_flags = 0;
3482
3483 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3484 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3485 mcdi_flags |=
3486 is_multicast_ether_addr(spec->loc_mac) ?
3487 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3488 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3489 }
3490
3491#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3492 unsigned int old_match_flags = match_flags; \
3493 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3494 if (match_flags != old_match_flags) \
3495 mcdi_flags |= \
3496 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3497 mcdi_field ## _LBN); \
3498 }
3499 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3500 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3501 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3502 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3503 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3504 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3505 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3506 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3507 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3508 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3509#undef MAP_FILTER_TO_MCDI_FLAG
3510
3511 /* Did we map them all? */
3512 WARN_ON_ONCE(match_flags);
3513
3514 return mcdi_flags;
3515}
3516
3517static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3518 const struct efx_filter_spec *spec)
3519{
3520 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
8127d661
BH		 3521 unsigned int match_pri;
3522
3523 for (match_pri = 0;
3524 match_pri < table->rx_match_count;
3525 match_pri++)
7ac0dd9d 3526 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
8127d661
BH		 3527 return match_pri;
3528
3529 return -EPROTONOSUPPORT;
3530}
3531
3532static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3533 struct efx_filter_spec *spec,
3534 bool replace_equal)
3535{
3536 struct efx_ef10_filter_table *table = efx->filter_state;
3537 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3538 struct efx_filter_spec *saved_spec;
3539 unsigned int match_pri, hash;
3540 unsigned int priv_flags;
3541 bool replacing = false;
3542 int ins_index = -1;
3543 DEFINE_WAIT(wait);
3544 bool is_mc_recip;
3545 s32 rc;
3546
3547 /* For now, only support RX filters */
3548 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3549 EFX_FILTER_FLAG_RX)
3550 return -EINVAL;
3551
7ac0dd9d 3552 rc = efx_ef10_filter_pri(table, spec);
8127d661
BH		 3553 if (rc < 0)
3554 return rc;
3555 match_pri = rc;
3556
3557 hash = efx_ef10_filter_hash(spec);
3558 is_mc_recip = efx_filter_is_mc_recipient(spec);
3559 if (is_mc_recip)
3560 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3561
3562 /* Find any existing filters with the same match tuple or
3563 * else a free slot to insert at. If any of them are busy,
3564 * we have to wait and retry.
3565 */
3566 for (;;) {
3567 unsigned int depth = 1;
3568 unsigned int i;
3569
3570 spin_lock_bh(&efx->filter_lock);
3571
3572 for (;;) {
3573 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3574 saved_spec = efx_ef10_filter_entry_spec(table, i);
3575
3576 if (!saved_spec) {
3577 if (ins_index < 0)
3578 ins_index = i;
3579 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3580 if (table->entry[i].spec &
3581 EFX_EF10_FILTER_FLAG_BUSY)
3582 break;
3583 if (spec->priority < saved_spec->priority &&
7665d1ab 3584 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3585 rc = -EPERM;
3586 goto out_unlock;
3587 }
3588 if (!is_mc_recip) {
3589 /* This is the only one */
3590 if (spec->priority ==
3591 saved_spec->priority &&
3592 !replace_equal) {
3593 rc = -EEXIST;
3594 goto out_unlock;
3595 }
3596 ins_index = i;
3597 goto found;
3598 } else if (spec->priority >
3599 saved_spec->priority ||
3600 (spec->priority ==
3601 saved_spec->priority &&
3602 replace_equal)) {
3603 if (ins_index < 0)
3604 ins_index = i;
3605 else
3606 __set_bit(depth, mc_rem_map);
3607 }
3608 }
3609
3610 /* Once we reach the maximum search depth, use
3611 * the first suitable slot or return -EBUSY if
3612 * there was none
3613 */
3614 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3615 if (ins_index < 0) {
3616 rc = -EBUSY;
3617 goto out_unlock;
3618 }
3619 goto found;
3620 }
3621
3622 ++depth;
3623 }
3624
3625 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3626 spin_unlock_bh(&efx->filter_lock);
3627 schedule();
3628 }
3629
3630found:
3631 /* Create a software table entry if necessary, and mark it
3632 * busy. We might yet fail to insert, but any attempt to
3633 * insert a conflicting filter while we're waiting for the
3634 * firmware must find the busy entry.
3635 */
3636 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3637 if (saved_spec) {
7665d1ab
BH		 3638 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3639 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3640 /* Just make sure it won't be removed */
7665d1ab
BH		 3641 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3642 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3643 table->entry[ins_index].spec &=
b59e6ef8 3644 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3645 rc = ins_index;
3646 goto out_unlock;
3647 }
3648 replacing = true;
3649 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3650 } else {
3651 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3652 if (!saved_spec) {
3653 rc = -ENOMEM;
3654 goto out_unlock;
3655 }
3656 *saved_spec = *spec;
3657 priv_flags = 0;
3658 }
3659 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3660 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3661
3662 /* Mark lower-priority multicast recipients busy prior to removal */
3663 if (is_mc_recip) {
3664 unsigned int depth, i;
3665
3666 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3667 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3668 if (test_bit(depth, mc_rem_map))
3669 table->entry[i].spec |=
3670 EFX_EF10_FILTER_FLAG_BUSY;
3671 }
3672 }
3673
3674 spin_unlock_bh(&efx->filter_lock);
3675
3676 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3677 replacing);
3678
3679 /* Finalise the software table entry */
3680 spin_lock_bh(&efx->filter_lock);
3681 if (rc == 0) {
3682 if (replacing) {
3683 /* Update the fields that may differ */
7665d1ab
BH		 3684 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3685 saved_spec->flags |=
3686 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3687 saved_spec->priority = spec->priority;
7665d1ab 3688 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 3689 saved_spec->flags |= spec->flags;
3690 saved_spec->rss_context = spec->rss_context;
3691 saved_spec->dmaq_id = spec->dmaq_id;
3692 }
3693 } else if (!replacing) {
3694 kfree(saved_spec);
3695 saved_spec = NULL;
3696 }
3697 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3698
3699 /* Remove and finalise entries for lower-priority multicast
3700 * recipients
3701 */
3702 if (is_mc_recip) {
3703 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3704 unsigned int depth, i;
3705
3706 memset(inbuf, 0, sizeof(inbuf));
3707
3708 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3709 if (!test_bit(depth, mc_rem_map))
3710 continue;
3711
3712 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3713 saved_spec = efx_ef10_filter_entry_spec(table, i);
3714 priv_flags = efx_ef10_filter_entry_flags(table, i);
3715
3716 if (rc == 0) {
3717 spin_unlock_bh(&efx->filter_lock);
3718 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3719 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3720 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3721 table->entry[i].handle);
3722 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3723 inbuf, sizeof(inbuf),
3724 NULL, 0, NULL);
3725 spin_lock_bh(&efx->filter_lock);
3726 }
3727
3728 if (rc == 0) {
3729 kfree(saved_spec);
3730 saved_spec = NULL;
3731 priv_flags = 0;
3732 } else {
3733 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3734 }
3735 efx_ef10_filter_set_entry(table, i, saved_spec,
3736 priv_flags);
3737 }
3738 }
3739
3740 /* If successful, return the inserted filter ID */
3741 if (rc == 0)
3742 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3743
3744 wake_up_all(&table->waitq);
3745out_unlock:
3746 spin_unlock_bh(&efx->filter_lock);
3747 finish_wait(&table->waitq, &wait);
3748 return rc;
3749}
3750
9fd8095d 3751static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 3752{
3753 /* no need to do anything here on EF10 */
3754}
3755
3756/* Remove a filter.
b59e6ef8
BH		 3757 * If !by_index, remove by ID
3758 * If by_index, remove by index
8127d661
BH		 3759 * Filter ID may come from userland and must be range-checked.
3760 */
3761static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 3762 unsigned int priority_mask,
b59e6ef8 3763 u32 filter_id, bool by_index)
8127d661
BH		 3764{
3765 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3766 struct efx_ef10_filter_table *table = efx->filter_state;
3767 MCDI_DECLARE_BUF(inbuf,
3768 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3769 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3770 struct efx_filter_spec *spec;
3771 DEFINE_WAIT(wait);
3772 int rc;
3773
3774 /* Find the software table entry and mark it busy. Don't
3775 * remove it yet; any attempt to update while we're waiting
3776 * for the firmware must find the busy entry.
3777 */
3778 for (;;) {
3779 spin_lock_bh(&efx->filter_lock);
3780 if (!(table->entry[filter_idx].spec &
3781 EFX_EF10_FILTER_FLAG_BUSY))
3782 break;
3783 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3784 spin_unlock_bh(&efx->filter_lock);
3785 schedule();
3786 }
7665d1ab 3787
8127d661 3788 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 3789 if (!spec ||
b59e6ef8 3790 (!by_index &&
7ac0dd9d 3791 efx_ef10_filter_pri(table, spec) !=
8127d661
BH		 3792 filter_id / HUNT_FILTER_TBL_ROWS)) {
3793 rc = -ENOENT;
3794 goto out_unlock;
3795 }
7665d1ab
BH		 3796
3797 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 3798 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 3799 /* Just remove flags */
3800 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 3801 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 3802 rc = 0;
3803 goto out_unlock;
3804 }
3805
fbd79120 3806 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 3807 rc = -ENOENT;
3808 goto out_unlock;
3809 }
3810
8127d661
BH		 3811 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3812 spin_unlock_bh(&efx->filter_lock);
3813
7665d1ab 3814 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 3815 /* Reset to an automatic filter */
8127d661
BH		 3816
3817 struct efx_filter_spec new_spec = *spec;
3818
7665d1ab 3819 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 3820 new_spec.flags = (EFX_FILTER_FLAG_RX |
f1c2ef40
BK		 3821 (efx_rss_enabled(efx) ?
3822 EFX_FILTER_FLAG_RX_RSS : 0));
8127d661
BH		 3823 new_spec.dmaq_id = 0;
3824 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3825 rc = efx_ef10_filter_push(efx, &new_spec,
3826 &table->entry[filter_idx].handle,
3827 true);
3828
3829 spin_lock_bh(&efx->filter_lock);
3830 if (rc == 0)
3831 *spec = new_spec;
3832 } else {
3833 /* Really remove the filter */
3834
3835 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3836 efx_ef10_filter_is_exclusive(spec) ?
3837 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3838 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3839 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3840 table->entry[filter_idx].handle);
3841 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3842 inbuf, sizeof(inbuf), NULL, 0, NULL);
3843
3844 spin_lock_bh(&efx->filter_lock);
3845 if (rc == 0) {
3846 kfree(spec);
3847 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3848 }
3849 }
7665d1ab 3850
8127d661
BH		 3851 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3852 wake_up_all(&table->waitq);
3853out_unlock:
3854 spin_unlock_bh(&efx->filter_lock);
3855 finish_wait(&table->waitq, &wait);
3856 return rc;
3857}
3858
3859static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3860 enum efx_filter_priority priority,
3861 u32 filter_id)
3862{
fbd79120
BH		 3863 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3864 filter_id, false);
8127d661
BH		 3865}
3866
12fb0da4
EC		 3867static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3868{
3869 return filter_id % HUNT_FILTER_TBL_ROWS;
3870}
3871
8c915620
EC		 3872static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3873 enum efx_filter_priority priority,
3874 u32 filter_id)
12fb0da4 3875{
8c915620
EC		 3876 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
3877 return;
3878 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
12fb0da4
EC		 3879}
3880
8127d661
BH		 3881static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3882 enum efx_filter_priority priority,
3883 u32 filter_id, struct efx_filter_spec *spec)
3884{
3885 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3886 struct efx_ef10_filter_table *table = efx->filter_state;
3887 const struct efx_filter_spec *saved_spec;
3888 int rc;
3889
3890 spin_lock_bh(&efx->filter_lock);
3891 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3892 if (saved_spec && saved_spec->priority == priority &&
7ac0dd9d 3893 efx_ef10_filter_pri(table, saved_spec) ==
8127d661
BH		 3894 filter_id / HUNT_FILTER_TBL_ROWS) {
3895 *spec = *saved_spec;
3896 rc = 0;
3897 } else {
3898 rc = -ENOENT;
3899 }
3900 spin_unlock_bh(&efx->filter_lock);
3901 return rc;
3902}
3903
fbd79120 3904static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 3905 enum efx_filter_priority priority)
3906{
fbd79120
BH		 3907 unsigned int priority_mask;
3908 unsigned int i;
3909 int rc;
3910
3911 priority_mask = (((1U << (priority + 1)) - 1) &
3912 ~(1U << EFX_FILTER_PRI_AUTO));
3913
3914 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3915 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3916 i, true);
3917 if (rc && rc != -ENOENT)
3918 return rc;
3919 }
3920
3921 return 0;
8127d661
BH		 3922}
3923
3924static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3925 enum efx_filter_priority priority)
3926{
3927 struct efx_ef10_filter_table *table = efx->filter_state;
3928 unsigned int filter_idx;
3929 s32 count = 0;
3930
3931 spin_lock_bh(&efx->filter_lock);
3932 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3933 if (table->entry[filter_idx].spec &&
3934 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3935 priority)
3936 ++count;
3937 }
3938 spin_unlock_bh(&efx->filter_lock);
3939 return count;
3940}
3941
3942static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3943{
3944 struct efx_ef10_filter_table *table = efx->filter_state;
3945
3946 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3947}
3948
3949static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3950 enum efx_filter_priority priority,
3951 u32 *buf, u32 size)
3952{
3953 struct efx_ef10_filter_table *table = efx->filter_state;
3954 struct efx_filter_spec *spec;
3955 unsigned int filter_idx;
3956 s32 count = 0;
3957
3958 spin_lock_bh(&efx->filter_lock);
3959 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3960 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3961 if (spec && spec->priority == priority) {
3962 if (count == size) {
3963 count = -EMSGSIZE;
3964 break;
3965 }
7ac0dd9d 3966 buf[count++] = (efx_ef10_filter_pri(table, spec) *
8127d661
BH		 3967 HUNT_FILTER_TBL_ROWS +
3968 filter_idx);
3969 }
3970 }
3971 spin_unlock_bh(&efx->filter_lock);
3972 return count;
3973}
3974
3975#ifdef CONFIG_RFS_ACCEL
3976
3977static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3978
3979static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3980 struct efx_filter_spec *spec)
3981{
3982 struct efx_ef10_filter_table *table = efx->filter_state;
3983 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3984 struct efx_filter_spec *saved_spec;
3985 unsigned int hash, i, depth = 1;
3986 bool replacing = false;
3987 int ins_index = -1;
3988 u64 cookie;
3989 s32 rc;
3990
3991 /* Must be an RX filter without RSS and not for a multicast
3992 * destination address (RFS only works for connected sockets).
3993 * These restrictions allow us to pass only a tiny amount of
3994 * data through to the completion function.
3995 */
3996 EFX_WARN_ON_PARANOID(spec->flags !=
3997 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3998 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3999 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4000
4001 hash = efx_ef10_filter_hash(spec);
4002
4003 spin_lock_bh(&efx->filter_lock);
4004
4005 /* Find any existing filter with the same match tuple or else
4006 * a free slot to insert at. If an existing filter is busy,
4007 * we have to give up.
4008 */
4009 for (;;) {
4010 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4011 saved_spec = efx_ef10_filter_entry_spec(table, i);
4012
4013 if (!saved_spec) {
4014 if (ins_index < 0)
4015 ins_index = i;
4016 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4017 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4018 rc = -EBUSY;
4019 goto fail_unlock;
4020 }
8127d661
BH		 4021 if (spec->priority < saved_spec->priority) {
4022 rc = -EPERM;
4023 goto fail_unlock;
4024 }
4025 ins_index = i;
4026 break;
4027 }
4028
4029 /* Once we reach the maximum search depth, use the
4030 * first suitable slot or return -EBUSY if there was
4031 * none
4032 */
4033 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4034 if (ins_index < 0) {
4035 rc = -EBUSY;
4036 goto fail_unlock;
4037 }
4038 break;
4039 }
4040
4041 ++depth;
4042 }
4043
4044 /* Create a software table entry if necessary, and mark it
4045 * busy. We might yet fail to insert, but any attempt to
4046 * insert a conflicting filter while we're waiting for the
4047 * firmware must find the busy entry.
4048 */
4049 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4050 if (saved_spec) {
4051 replacing = true;
4052 } else {
4053 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4054 if (!saved_spec) {
4055 rc = -ENOMEM;
4056 goto fail_unlock;
4057 }
4058 *saved_spec = *spec;
4059 }
4060 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4061 EFX_EF10_FILTER_FLAG_BUSY);
4062
4063 spin_unlock_bh(&efx->filter_lock);
4064
4065 /* Pack up the variables needed on completion */
4066 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4067
4068 efx_ef10_filter_push_prep(efx, spec, inbuf,
4069 table->entry[ins_index].handle, replacing);
4070 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4071 MC_CMD_FILTER_OP_OUT_LEN,
4072 efx_ef10_filter_rfs_insert_complete, cookie);
4073
4074 return ins_index;
4075
4076fail_unlock:
4077 spin_unlock_bh(&efx->filter_lock);
4078 return rc;
4079}
4080
4081static void
4082efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4083 int rc, efx_dword_t *outbuf,
4084 size_t outlen_actual)
4085{
4086 struct efx_ef10_filter_table *table = efx->filter_state;
4087 unsigned int ins_index, dmaq_id;
4088 struct efx_filter_spec *spec;
4089 bool replacing;
4090
4091 /* Unpack the cookie */
4092 replacing = cookie >> 31;
4093 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4094 dmaq_id = cookie & 0xffff;
4095
4096 spin_lock_bh(&efx->filter_lock);
4097 spec = efx_ef10_filter_entry_spec(table, ins_index);
4098 if (rc == 0) {
4099 table->entry[ins_index].handle =
4100 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4101 if (replacing)
4102 spec->dmaq_id = dmaq_id;
4103 } else if (!replacing) {
4104 kfree(spec);
4105 spec = NULL;
4106 }
4107 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4108 spin_unlock_bh(&efx->filter_lock);
4109
4110 wake_up_all(&table->waitq);
4111}
4112
4113static void
4114efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4115 unsigned long filter_idx,
4116 int rc, efx_dword_t *outbuf,
4117 size_t outlen_actual);
4118
4119static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4120 unsigned int filter_idx)
4121{
4122 struct efx_ef10_filter_table *table = efx->filter_state;
4123 struct efx_filter_spec *spec =
4124 efx_ef10_filter_entry_spec(table, filter_idx);
4125 MCDI_DECLARE_BUF(inbuf,
4126 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4127 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4128
4129 if (!spec ||
4130 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4131 spec->priority != EFX_FILTER_PRI_HINT ||
4132 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4133 flow_id, filter_idx))
4134 return false;
4135
4136 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4137 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4138 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4139 table->entry[filter_idx].handle);
4140 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4141 efx_ef10_filter_rfs_expire_complete, filter_idx))
4142 return false;
4143
4144 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4145 return true;
4146}
4147
4148static void
4149efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4150 unsigned long filter_idx,
4151 int rc, efx_dword_t *outbuf,
4152 size_t outlen_actual)
4153{
4154 struct efx_ef10_filter_table *table = efx->filter_state;
4155 struct efx_filter_spec *spec =
4156 efx_ef10_filter_entry_spec(table, filter_idx);
4157
4158 spin_lock_bh(&efx->filter_lock);
4159 if (rc == 0) {
4160 kfree(spec);
4161 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4162 }
4163 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4164 wake_up_all(&table->waitq);
4165 spin_unlock_bh(&efx->filter_lock);
4166}
4167
4168#endif /* CONFIG_RFS_ACCEL */
4169
4170static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
4171{
4172 int match_flags = 0;
4173
4174#define MAP_FLAG(gen_flag, mcdi_field) { \
4175 u32 old_mcdi_flags = mcdi_flags; \
4176 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
4177 mcdi_field ## _LBN); \
4178 if (mcdi_flags != old_mcdi_flags) \
4179 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4180 }
4181 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4182 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4183 MAP_FLAG(REM_HOST, SRC_IP);
4184 MAP_FLAG(LOC_HOST, DST_IP);
4185 MAP_FLAG(REM_MAC, SRC_MAC);
4186 MAP_FLAG(REM_PORT, SRC_PORT);
4187 MAP_FLAG(LOC_MAC, DST_MAC);
4188 MAP_FLAG(LOC_PORT, DST_PORT);
4189 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4190 MAP_FLAG(INNER_VID, INNER_VLAN);
4191 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4192 MAP_FLAG(IP_PROTO, IP_PROTO);
4193#undef MAP_FLAG
4194
4195 /* Did we map them all? */
4196 if (mcdi_flags)
4197 return -EINVAL;
4198
4199 return match_flags;
4200}
4201
34813fe2
AR		 4202static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4203{
4204 struct efx_ef10_filter_table *table = efx->filter_state;
4205 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4206
4207 /* See comment in efx_ef10_filter_table_remove() */
4208 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4209 return;
4210
4211 if (!table)
4212 return;
4213
4214 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4215 efx_ef10_filter_del_vlan_internal(efx, vlan);
4216}
4217
7ac0dd9d
AR		 4218static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4219 enum efx_filter_match_flags match_flags)
4220{
4221 unsigned int match_pri;
4222 int mf;
4223
4224 for (match_pri = 0;
4225 match_pri < table->rx_match_count;
4226 match_pri++) {
4227 mf = efx_ef10_filter_match_flags_from_mcdi(
4228 table->rx_match_mcdi_flags[match_pri]);
4229 if (mf == match_flags)
4230 return true;
4231 }
4232
4233 return false;
4234}
4235
8127d661
BH		 4236static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4237{
4238 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4239 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
34813fe2 4240 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e4478ad1 4241 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 4242 unsigned int pd_match_pri, pd_match_count;
4243 struct efx_ef10_filter_table *table;
34813fe2 4244 struct efx_ef10_vlan *vlan;
8127d661
BH		 4245 size_t outlen;
4246 int rc;
4247
dd98708c
EC		 4248 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4249 return -EINVAL;
4250
4251 if (efx->filter_state) /* already probed */
4252 return 0;
4253
8127d661
BH		 4254 table = kzalloc(sizeof(*table), GFP_KERNEL);
4255 if (!table)
4256 return -ENOMEM;
4257
4258 /* Find out which RX filter types are supported, and their priorities */
4259 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4260 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4261 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4262 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4263 &outlen);
4264 if (rc)
4265 goto fail;
4266 pd_match_count = MCDI_VAR_ARRAY_LEN(
4267 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4268 table->rx_match_count = 0;
4269
4270 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4271 u32 mcdi_flags =
4272 MCDI_ARRAY_DWORD(
4273 outbuf,
4274 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4275 pd_match_pri);
4276 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4277 if (rc < 0) {
4278 netif_dbg(efx, probe, efx->net_dev,
4279 "%s: fw flags %#x pri %u not supported in driver\n",
4280 __func__, mcdi_flags, pd_match_pri);
4281 } else {
4282 netif_dbg(efx, probe, efx->net_dev,
4283 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4284 __func__, mcdi_flags, pd_match_pri,
4285 rc, table->rx_match_count);
7ac0dd9d
AR		 4286 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4287 table->rx_match_count++;
8127d661
BH		 4288 }
4289 }
4290
e4478ad1
MH		 4291 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4292 !(efx_ef10_filter_match_supported(table,
4293 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4294 efx_ef10_filter_match_supported(table,
4295 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4296 netif_info(efx, probe, net_dev,
4297 "VLAN filters are not supported in this firmware variant\n");
4298 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4299 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4300 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4301 }
4302
8127d661
BH		 4303 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4304 if (!table->entry) {
4305 rc = -ENOMEM;
4306 goto fail;
4307 }
4308
b071c3a2 4309 table->mc_promisc_last = false;
4a53ea8a
AR		 4310 table->vlan_filter =
4311 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
34813fe2 4312 INIT_LIST_HEAD(&table->vlan_list);
12fb0da4 4313
8127d661
BH		 4314 efx->filter_state = table;
4315 init_waitqueue_head(&table->waitq);
34813fe2
AR		 4316
4317 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4318 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4319 if (rc)
4320 goto fail_add_vlan;
4321 }
4322
8127d661
BH		 4323 return 0;
4324
34813fe2
AR		 4325fail_add_vlan:
4326 efx_ef10_filter_cleanup_vlans(efx);
4327 efx->filter_state = NULL;
8127d661
BH		 4328fail:
4329 kfree(table);
4330 return rc;
4331}
4332
0d322413
EC		 4333/* Caller must hold efx->filter_sem for read if race against
4334 * efx_ef10_filter_table_remove() is possible
4335 */
8127d661
BH		 4336static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4337{
4338 struct efx_ef10_filter_table *table = efx->filter_state;
4339 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4340 struct efx_filter_spec *spec;
4341 unsigned int filter_idx;
4342 bool failed = false;
4343 int rc;
4344
0d322413
EC		 4345 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4346
8127d661
BH		 4347 if (!nic_data->must_restore_filters)
4348 return;
4349
0d322413
EC		 4350 if (!table)
4351 return;
4352
8127d661
BH		 4353 spin_lock_bh(&efx->filter_lock);
4354
4355 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4356 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4357 if (!spec)
4358 continue;
4359
4360 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4361 spin_unlock_bh(&efx->filter_lock);
4362
4363 rc = efx_ef10_filter_push(efx, spec,
4364 &table->entry[filter_idx].handle,
4365 false);
4366 if (rc)
4367 failed = true;
4368
4369 spin_lock_bh(&efx->filter_lock);
4370 if (rc) {
4371 kfree(spec);
4372 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4373 } else {
4374 table->entry[filter_idx].spec &=
4375 ~EFX_EF10_FILTER_FLAG_BUSY;
4376 }
4377 }
4378
4379 spin_unlock_bh(&efx->filter_lock);
4380
4381 if (failed)
4382 netif_err(efx, hw, efx->net_dev,
4383 "unable to restore all filters\n");
4384 else
4385 nic_data->must_restore_filters = false;
4386}
4387
4388static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4389{
4390 struct efx_ef10_filter_table *table = efx->filter_state;
4391 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4392 struct efx_filter_spec *spec;
4393 unsigned int filter_idx;
4394 int rc;
4395
34813fe2 4396 efx_ef10_filter_cleanup_vlans(efx);
0d322413 4397 efx->filter_state = NULL;
dd98708c
EC		 4398 /* If we were called without locking, then it's not safe to free
4399 * the table as others might be using it. So we just WARN, leak
4400 * the memory, and potentially get an inconsistent filter table
4401 * state.
4402 * This should never actually happen.
4403 */
4404 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4405 return;
4406
0d322413
EC		 4407 if (!table)
4408 return;
4409
8127d661
BH		 4410 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4411 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4412 if (!spec)
4413 continue;
4414
4415 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4416 efx_ef10_filter_is_exclusive(spec) ?
4417 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4418 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4419 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4420 table->entry[filter_idx].handle);
e65a5109
BK		 4421 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4422 sizeof(inbuf), NULL, 0, NULL);
48ce5634 4423 if (rc)
e65a5109
BK		 4424 netif_info(efx, drv, efx->net_dev,
4425 "%s: filter %04x remove failed\n",
4426 __func__, filter_idx);
8127d661
BH		 4427 kfree(spec);
4428 }
4429
4430 vfree(table->entry);
4431 kfree(table);
4432}
4433
6a37958b
AR		 4434static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4435{
4436 struct efx_ef10_filter_table *table = efx->filter_state;
4437 unsigned int filter_idx;
4438
4439 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4440 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4441 if (!table->entry[filter_idx].spec)
4442 netif_dbg(efx, drv, efx->net_dev,
4443 "marked null spec old %04x:%04x\n", *id,
4444 filter_idx);
4445 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4446 *id = EFX_EF10_FILTER_ID_INVALID;
e65a5109 4447 }
6a37958b
AR		 4448}
4449
b3a3c03c
AR		 4450/* Mark old per-VLAN filters that may need to be removed */
4451static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4452 struct efx_ef10_filter_vlan *vlan)
8127d661
BH		 4453{
4454 struct efx_ef10_filter_table *table = efx->filter_state;
6a37958b 4455 unsigned int i;
8127d661 4456
12fb0da4 4457 for (i = 0; i < table->dev_uc_count; i++)
dc3273e0 4458 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
12fb0da4 4459 for (i = 0; i < table->dev_mc_count; i++)
dc3273e0
AR		 4460 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4461 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4462 efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4463 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
b3a3c03c
AR		 4464}
4465
34813fe2
AR		 4466/* Mark old filters that may need to be removed.
4467 * Caller must hold efx->filter_sem for read if race against
4468 * efx_ef10_filter_table_remove() is possible
4469 */
b3a3c03c
AR		 4470static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4471{
4472 struct efx_ef10_filter_table *table = efx->filter_state;
34813fe2 4473 struct efx_ef10_filter_vlan *vlan;
b3a3c03c
AR		 4474
4475 spin_lock_bh(&efx->filter_lock);
34813fe2
AR		 4476 list_for_each_entry(vlan, &table->vlan_list, list)
4477 _efx_ef10_filter_vlan_mark_old(efx, vlan);
8127d661 4478 spin_unlock_bh(&efx->filter_lock);
822b96f8
DP		 4479}
4480
afa4ce12 4481static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4482{
4483 struct efx_ef10_filter_table *table = efx->filter_state;
4484 struct net_device *net_dev = efx->net_dev;
4485 struct netdev_hw_addr *uc;
12fb0da4 4486 int addr_count;
822b96f8 4487 unsigned int i;
8127d661 4488
12fb0da4 4489 addr_count = netdev_uc_count(net_dev);
afa4ce12 4490 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
12fb0da4 4491 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 4492 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4493 i = 1;
4494 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4 4495 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
afa4ce12 4496 table->uc_promisc = true;
12fb0da4
EC		 4497 break;
4498 }
822b96f8
DP		 4499 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4500 i++;
4501 }
4502}
4503
afa4ce12 4504static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4505{
4506 struct efx_ef10_filter_table *table = efx->filter_state;
4507 struct net_device *net_dev = efx->net_dev;
4508 struct netdev_hw_addr *mc;
ab8b1f7c 4509 unsigned int i, addr_count;
822b96f8 4510
afa4ce12 4511 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
ab8b1f7c 4512
12fb0da4
EC		 4513 addr_count = netdev_mc_count(net_dev);
4514 i = 0;
ab8b1f7c 4515 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4 4516 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
afa4ce12 4517 table->mc_promisc = true;
12fb0da4
EC		 4518 break;
4519 }
ab8b1f7c
DP		 4520 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4521 i++;
8127d661 4522 }
12fb0da4
EC		 4523
4524 table->dev_mc_count = i;
822b96f8 4525}
8127d661 4526
12fb0da4 4527static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
b3a3c03c
AR		 4528 struct efx_ef10_filter_vlan *vlan,
4529 bool multicast, bool rollback)
822b96f8
DP		 4530{
4531 struct efx_ef10_filter_table *table = efx->filter_state;
4532 struct efx_ef10_dev_addr *addr_list;
f1c2ef40 4533 enum efx_filter_flags filter_flags;
822b96f8 4534 struct efx_filter_spec spec;
12fb0da4
EC		 4535 u8 baddr[ETH_ALEN];
4536 unsigned int i, j;
4537 int addr_count;
dc3273e0 4538 u16 *ids;
822b96f8
DP		 4539 int rc;
4540
4541 if (multicast) {
4542 addr_list = table->dev_mc_list;
12fb0da4 4543 addr_count = table->dev_mc_count;
dc3273e0 4544 ids = vlan->mc;
822b96f8
DP		 4545 } else {
4546 addr_list = table->dev_uc_list;
12fb0da4 4547 addr_count = table->dev_uc_count;
dc3273e0 4548 ids = vlan->uc;
8127d661
BH		 4549 }
4550
f1c2ef40
BK		 4551 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4552
822b96f8 4553 /* Insert/renew filters */
12fb0da4 4554 for (i = 0; i < addr_count; i++) {
f1c2ef40 4555 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
b3a3c03c 4556 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
b6f568e2
JC		 4557 rc = efx_ef10_filter_insert(efx, &spec, true);
4558 if (rc < 0) {
12fb0da4
EC		 4559 if (rollback) {
4560 netif_info(efx, drv, efx->net_dev,
4561 "efx_ef10_filter_insert failed rc=%d\n",
4562 rc);
4563 /* Fall back to promiscuous */
4564 for (j = 0; j < i; j++) {
12fb0da4
EC		 4565 efx_ef10_filter_remove_unsafe(
4566 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4567 ids[j]);
4568 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4569 }
4570 return rc;
4571 } else {
4572 /* mark as not inserted, and carry on */
4573 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 4574 }
8127d661 4575 }
dc3273e0 4576 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 4577 }
822b96f8 4578
12fb0da4
EC		 4579 if (multicast && rollback) {
4580 /* Also need an Ethernet broadcast filter */
f1c2ef40 4581 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4 4582 eth_broadcast_addr(baddr);
b3a3c03c 4583 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
8127d661 4584 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 4585 if (rc < 0) {
822b96f8 4586 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 4587 "Broadcast filter insert failed rc=%d\n", rc);
4588 /* Fall back to promiscuous */
4589 for (j = 0; j < i; j++) {
12fb0da4
EC		 4590 efx_ef10_filter_remove_unsafe(
4591 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4592 ids[j]);
4593 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4594 }
4595 return rc;
4596 } else {
dc3273e0 4597 EFX_WARN_ON_PARANOID(vlan->bcast !=
6a37958b 4598 EFX_EF10_FILTER_ID_INVALID);
dc3273e0 4599 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4 4600 }
8127d661 4601 }
12fb0da4
EC		 4602
4603 return 0;
4604}
4605
b3a3c03c
AR		 4606static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4607 struct efx_ef10_filter_vlan *vlan,
4608 bool multicast, bool rollback)
12fb0da4 4609{
12fb0da4 4610 struct efx_ef10_nic_data *nic_data = efx->nic_data;
f1c2ef40 4611 enum efx_filter_flags filter_flags;
12fb0da4
EC		 4612 struct efx_filter_spec spec;
4613 u8 baddr[ETH_ALEN];
4614 int rc;
4615
f1c2ef40
BK		 4616 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4617
4618 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4
EC		 4619
4620 if (multicast)
4621 efx_filter_set_mc_def(&spec);
4622 else
4623 efx_filter_set_uc_def(&spec);
4624
b3a3c03c
AR		 4625 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4626 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4627
12fb0da4
EC		 4628 rc = efx_ef10_filter_insert(efx, &spec, true);
4629 if (rc < 0) {
09a04204
BK		 4630 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4631 efx->net_dev,
4632 "%scast mismatch filter insert failed rc=%d\n",
4633 multicast ? "Multi" : "Uni", rc);
12fb0da4 4634 } else if (multicast) {
dc3273e0
AR		 4635 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4636 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 4637 if (!nic_data->workaround_26807) {
4638 /* Also need an Ethernet broadcast filter */
4639 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
f1c2ef40 4640 filter_flags, 0);
12fb0da4 4641 eth_broadcast_addr(baddr);
b3a3c03c 4642 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
12fb0da4
EC		 4643 rc = efx_ef10_filter_insert(efx, &spec, true);
4644 if (rc < 0) {
4645 netif_warn(efx, drv, efx->net_dev,
4646 "Broadcast filter insert failed rc=%d\n",
4647 rc);
4648 if (rollback) {
4649 /* Roll back the mc_def filter */
4650 efx_ef10_filter_remove_unsafe(
4651 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4652 vlan->mcdef);
4653 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4654 return rc;
4655 }
4656 } else {
dc3273e0 4657 EFX_WARN_ON_PARANOID(vlan->bcast !=
6a37958b 4658 EFX_EF10_FILTER_ID_INVALID);
dc3273e0 4659 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 4660 }
4661 }
4662 rc = 0;
4663 } else {
dc3273e0
AR		 4664 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4665 vlan->ucdef = rc;
12fb0da4
EC		 4666 rc = 0;
4667 }
4668 return rc;
822b96f8
DP		 4669}
4670
4671/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4672 * flag or removes these filters, we don't need to hold the filter_lock while
4673 * scanning for these filters.
4674 */
4675static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4676{
4677 struct efx_ef10_filter_table *table = efx->filter_state;
e65a5109
BK		 4678 int remove_failed = 0;
4679 int remove_noent = 0;
4680 int rc;
822b96f8 4681 int i;
8127d661 4682
8127d661
BH		 4683 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4684 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 4685 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
e65a5109
BK		 4686 rc = efx_ef10_filter_remove_internal(efx,
4687 1U << EFX_FILTER_PRI_AUTO, i, true);
4688 if (rc == -ENOENT)
4689 remove_noent++;
4690 else if (rc)
4691 remove_failed++;
8127d661
BH		 4692 }
4693 }
e65a5109
BK		 4694
4695 if (remove_failed)
4696 netif_info(efx, drv, efx->net_dev,
4697 "%s: failed to remove %d filters\n",
4698 __func__, remove_failed);
4699 if (remove_noent)
4700 netif_info(efx, drv, efx->net_dev,
4701 "%s: failed to remove %d non-existent filters\n",
4702 __func__, remove_noent);
8127d661
BH		 4703}
4704
7a186f47
DP		 4705static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4706{
4707 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4708 u8 mac_old[ETH_ALEN];
4709 int rc, rc2;
4710
4711 /* Only reconfigure a PF-created vport */
4712 if (is_zero_ether_addr(nic_data->vport_mac))
4713 return 0;
4714
4715 efx_device_detach_sync(efx);
4716 efx_net_stop(efx->net_dev);
4717 down_write(&efx->filter_sem);
4718 efx_ef10_filter_table_remove(efx);
4719 up_write(&efx->filter_sem);
4720
4721 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4722 if (rc)
4723 goto restore_filters;
4724
4725 ether_addr_copy(mac_old, nic_data->vport_mac);
4726 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4727 nic_data->vport_mac);
4728 if (rc)
4729 goto restore_vadaptor;
4730
4731 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4732 efx->net_dev->dev_addr);
4733 if (!rc) {
4734 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4735 } else {
4736 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4737 if (rc2) {
4738 /* Failed to add original MAC, so clear vport_mac */
4739 eth_zero_addr(nic_data->vport_mac);
4740 goto reset_nic;
4741 }
4742 }
4743
4744restore_vadaptor:
4745 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4746 if (rc2)
4747 goto reset_nic;
4748restore_filters:
4749 down_write(&efx->filter_sem);
4750 rc2 = efx_ef10_filter_table_probe(efx);
4751 up_write(&efx->filter_sem);
4752 if (rc2)
4753 goto reset_nic;
4754
4755 rc2 = efx_net_open(efx->net_dev);
4756 if (rc2)
4757 goto reset_nic;
4758
4759 netif_device_attach(efx->net_dev);
4760
4761 return rc;
4762
4763reset_nic:
4764 netif_err(efx, drv, efx->net_dev,
4765 "Failed to restore when changing MAC address - scheduling reset\n");
4766 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4767
4768 return rc ? rc : rc2;
4769}
4770
822b96f8
DP		 4771/* Caller must hold efx->filter_sem for read if race against
4772 * efx_ef10_filter_table_remove() is possible
4773 */
34813fe2
AR		 4774static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4775 struct efx_ef10_filter_vlan *vlan)
822b96f8
DP		 4776{
4777 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 4778 struct efx_ef10_nic_data *nic_data = efx->nic_data;
b3a3c03c 4779
4a53ea8a
AR		 4780 /* Do not install unspecified VID if VLAN filtering is enabled.
4781 * Do not install all specified VIDs if VLAN filtering is disabled.
4782 */
4783 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4784 return;
4785
12fb0da4 4786 /* Insert/renew unicast filters */
afa4ce12 4787 if (table->uc_promisc) {
b3a3c03c
AR		 4788 efx_ef10_filter_insert_def(efx, vlan, false, false);
4789 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
12fb0da4
EC		 4790 } else {
4791 /* If any of the filters failed to insert, fall back to
4792 * promiscuous mode - add in the uc_def filter. But keep
4793 * our individual unicast filters.
4794 */
b3a3c03c
AR		 4795 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4796 efx_ef10_filter_insert_def(efx, vlan, false, false);
12fb0da4 4797 }
ab8b1f7c 4798
12fb0da4 4799 /* Insert/renew multicast filters */
ab8b1f7c
DP		 4800 /* If changing promiscuous state with cascaded multicast filters, remove
4801 * old filters first, so that packets are dropped rather than duplicated
4802 */
afa4ce12
AR		 4803 if (nic_data->workaround_26807 &&
4804 table->mc_promisc_last != table->mc_promisc)
ab8b1f7c 4805 efx_ef10_filter_remove_old(efx);
afa4ce12 4806 if (table->mc_promisc) {
12fb0da4
EC		 4807 if (nic_data->workaround_26807) {
4808 /* If we failed to insert promiscuous filters, rollback
4809 * and fall back to individual multicast filters
4810 */
b3a3c03c 4811 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
12fb0da4
EC		 4812 /* Changing promisc state, so remove old filters */
4813 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 4814 efx_ef10_filter_insert_addr_list(efx, vlan,
4815 true, false);
12fb0da4
EC		 4816 }
4817 } else {
4818 /* If we failed to insert promiscuous filters, don't
4819 * rollback. Regardless, also insert the mc_list
4820 */
b3a3c03c
AR		 4821 efx_ef10_filter_insert_def(efx, vlan, true, false);
4822 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
12fb0da4
EC		 4823 }
4824 } else {
4825 /* If any filters failed to insert, rollback and fall back to
4826 * promiscuous mode - mc_def filter and maybe broadcast. If
4827 * that fails, roll back again and insert as many of our
4828 * individual multicast filters as we can.
4829 */
b3a3c03c 4830 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
12fb0da4
EC		 4831 /* Changing promisc state, so remove old filters */
4832 if (nic_data->workaround_26807)
4833 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 4834 if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4835 efx_ef10_filter_insert_addr_list(efx, vlan,
4836 true, false);
12fb0da4
EC		 4837 }
4838 }
34813fe2
AR		 4839}
4840
4841/* Caller must hold efx->filter_sem for read if race against
4842 * efx_ef10_filter_table_remove() is possible
4843 */
4844static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4845{
4846 struct efx_ef10_filter_table *table = efx->filter_state;
4847 struct net_device *net_dev = efx->net_dev;
4848 struct efx_ef10_filter_vlan *vlan;
4a53ea8a 4849 bool vlan_filter;
34813fe2
AR		 4850
4851 if (!efx_dev_registered(efx))
4852 return;
4853
4854 if (!table)
4855 return;
4856
4857 efx_ef10_filter_mark_old(efx);
4858
4859 /* Copy/convert the address lists; add the primary station
4860 * address and broadcast address
4861 */
4862 netif_addr_lock_bh(net_dev);
4863 efx_ef10_filter_uc_addr_list(efx);
4864 efx_ef10_filter_mc_addr_list(efx);
4865 netif_addr_unlock_bh(net_dev);
4866
4a53ea8a
AR		 4867 /* If VLAN filtering changes, all old filters are finally removed.
4868 * Do it in advance to avoid conflicts for unicast untagged and
4869 * VLAN 0 tagged filters.
4870 */
4871 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4872 if (table->vlan_filter != vlan_filter) {
4873 table->vlan_filter = vlan_filter;
4874 efx_ef10_filter_remove_old(efx);
4875 }
4876
34813fe2
AR		 4877 list_for_each_entry(vlan, &table->vlan_list, list)
4878 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
822b96f8
DP		 4879
4880 efx_ef10_filter_remove_old(efx);
afa4ce12 4881 table->mc_promisc_last = table->mc_promisc;
822b96f8
DP		 4882}
4883
34813fe2
AR		 4884static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
4885{
4886 struct efx_ef10_filter_table *table = efx->filter_state;
4887 struct efx_ef10_filter_vlan *vlan;
4888
4889 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4890
4891 list_for_each_entry(vlan, &table->vlan_list, list) {
4892 if (vlan->vid == vid)
4893 return vlan;
4894 }
4895
4896 return NULL;
4897}
4898
4899static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
4900{
4901 struct efx_ef10_filter_table *table = efx->filter_state;
4902 struct efx_ef10_filter_vlan *vlan;
4903 unsigned int i;
4904
4905 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4906 return -EINVAL;
4907
4908 vlan = efx_ef10_filter_find_vlan(efx, vid);
4909 if (WARN_ON(vlan)) {
4910 netif_err(efx, drv, efx->net_dev,
4911 "VLAN %u already added\n", vid);
4912 return -EALREADY;
4913 }
4914
4915 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
4916 if (!vlan)
4917 return -ENOMEM;
4918
4919 vlan->vid = vid;
4920
4921 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4922 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
4923 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4924 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
4925 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
4926 vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
4927 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4928
4929 list_add_tail(&vlan->list, &table->vlan_list);
4930
4931 if (efx_dev_registered(efx))
4932 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4933
4934 return 0;
4935}
4936
4937static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
4938 struct efx_ef10_filter_vlan *vlan)
4939{
4940 unsigned int i;
4941
4942 /* See comment in efx_ef10_filter_table_remove() */
4943 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4944 return;
4945
4946 list_del(&vlan->list);
4947
8c915620 4948 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
34813fe2 4949 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 4950 vlan->uc[i]);
4951 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
34813fe2 4952 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 4953 vlan->mc[i]);
4954 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
4955 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
4956 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
34813fe2
AR		 4957
4958 kfree(vlan);
4959}
4960
4961static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
4962{
4963 struct efx_ef10_filter_vlan *vlan;
4964
4965 /* See comment in efx_ef10_filter_table_remove() */
4966 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4967 return;
4968
4969 vlan = efx_ef10_filter_find_vlan(efx, vid);
4970 if (!vlan) {
4971 netif_err(efx, drv, efx->net_dev,
4972 "VLAN %u not found in filter state\n", vid);
4973 return;
4974 }
4975
4976 efx_ef10_filter_del_vlan_internal(efx, vlan);
4977}
4978
910c8789
SS		 4979static int efx_ef10_set_mac_address(struct efx_nic *efx)
4980{
4981 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4982 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4983 bool was_enabled = efx->port_enabled;
4984 int rc;
4985
4986 efx_device_detach_sync(efx);
4987 efx_net_stop(efx->net_dev);
d248953a
MH		 4988
4989 mutex_lock(&efx->mac_lock);
910c8789
SS		 4990 down_write(&efx->filter_sem);
4991 efx_ef10_filter_table_remove(efx);
4992
4993 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4994 efx->net_dev->dev_addr);
4995 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4996 nic_data->vport_id);
535a6177
DP		 4997 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4998 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 4999
5000 efx_ef10_filter_table_probe(efx);
5001 up_write(&efx->filter_sem);
d248953a
MH		 5002 mutex_unlock(&efx->mac_lock);
5003
910c8789
SS		 5004 if (was_enabled)
5005 efx_net_open(efx->net_dev);
5006 netif_device_attach(efx->net_dev);
5007
9e9f665a
DP		 5008#ifdef CONFIG_SFC_SRIOV
5009 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 5010 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5011
9e9f665a
DP		 5012 if (rc == -EPERM) {
5013 struct efx_nic *efx_pf;
910c8789 5014
9e9f665a
DP		 5015 /* Switch to PF and change MAC address on vport */
5016 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 5017
9e9f665a
DP		 5018 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5019 nic_data->vf_index,
5020 efx->net_dev->dev_addr);
5021 } else if (!rc) {
910c8789
SS		 5022 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5023 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5024 unsigned int i;
5025
9e9f665a
DP		 5026 /* MAC address successfully changed by VF (with MAC
5027 * spoofing) so update the parent PF if possible.
5028 */
910c8789
SS		 5029 for (i = 0; i < efx_pf->vf_count; ++i) {
5030 struct ef10_vf *vf = nic_data->vf + i;
5031
5032 if (vf->efx == efx) {
5033 ether_addr_copy(vf->mac,
5034 efx->net_dev->dev_addr);
5035 return 0;
5036 }
5037 }
5038 }
9e9f665a 5039 } else
910c8789 5040#endif
9e9f665a
DP		 5041 if (rc == -EPERM) {
5042 netif_err(efx, drv, efx->net_dev,
5043 "Cannot change MAC address; use sfboot to enable"
5044 " mac-spoofing on this interface\n");
7a186f47
DP		 5045 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5046 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5047 * fall-back to the method of changing the MAC address on the
5048 * vport. This only applies to PFs because such versions of
5049 * MCFW do not support VFs.
5050 */
5051 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 5052 } else {
5053 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5054 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 5055 }
5056
910c8789
SS		 5057 return rc;
5058}
5059
8127d661
BH		 5060static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5061{
5062 efx_ef10_filter_sync_rx_mode(efx);
5063
5064 return efx_mcdi_set_mac(efx);
5065}
5066
862f894c
SS		 5067static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5068{
5069 efx_ef10_filter_sync_rx_mode(efx);
5070
5071 return 0;
5072}
5073
74cd60a4
JC		 5074static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5075{
5076 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5077
5078 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5079 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5080 NULL, 0, NULL);
5081}
5082
5083/* MC BISTs follow a different poll mechanism to phy BISTs.
5084 * The BIST is done in the poll handler on the MC, and the MCDI command
5085 * will block until the BIST is done.
5086 */
5087static int efx_ef10_poll_bist(struct efx_nic *efx)
5088{
5089 int rc;
5090 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5091 size_t outlen;
5092 u32 result;
5093
5094 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5095 outbuf, sizeof(outbuf), &outlen);
5096 if (rc != 0)
5097 return rc;
5098
5099 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5100 return -EIO;
5101
5102 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5103 switch (result) {
5104 case MC_CMD_POLL_BIST_PASSED:
5105 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5106 return 0;
5107 case MC_CMD_POLL_BIST_TIMEOUT:
5108 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5109 return -EIO;
5110 case MC_CMD_POLL_BIST_FAILED:
5111 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5112 return -EIO;
5113 default:
5114 netif_err(efx, hw, efx->net_dev,
5115 "BIST returned unknown result %u", result);
5116 return -EIO;
5117 }
5118}
5119
5120static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5121{
5122 int rc;
5123
5124 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5125
5126 rc = efx_ef10_start_bist(efx, bist_type);
5127 if (rc != 0)
5128 return rc;
5129
5130 return efx_ef10_poll_bist(efx);
5131}
5132
5133static int
5134efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5135{
5136 int rc, rc2;
5137
5138 efx_reset_down(efx, RESET_TYPE_WORLD);
5139
5140 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5141 NULL, 0, NULL, 0, NULL);
5142 if (rc != 0)
5143 goto out;
5144
5145 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5146 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5147
5148 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5149
5150out:
27324820
DP		 5151 if (rc == -EPERM)
5152 rc = 0;
74cd60a4
JC		 5153 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5154 return rc ? rc : rc2;
5155}
5156
8127d661
BH		 5157#ifdef CONFIG_SFC_MTD
5158
5159struct efx_ef10_nvram_type_info {
5160 u16 type, type_mask;
5161 u8 port;
5162 const char *name;
5163};
5164
5165static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5166 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5167 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5168 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5169 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5170 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5171 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5172 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5173 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5174 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 5175 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 5176 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5177};
5178
5179static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5180 struct efx_mcdi_mtd_partition *part,
5181 unsigned int type)
5182{
5183 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5184 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5185 const struct efx_ef10_nvram_type_info *info;
5186 size_t size, erase_size, outlen;
5187 bool protected;
5188 int rc;
5189
5190 for (info = efx_ef10_nvram_types; ; info++) {
5191 if (info ==
5192 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5193 return -ENODEV;
5194 if ((type & ~info->type_mask) == info->type)
5195 break;
5196 }
5197 if (info->port != efx_port_num(efx))
5198 return -ENODEV;
5199
5200 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5201 if (rc)
5202 return rc;
5203 if (protected)
5204 return -ENODEV; /* hide it */
5205
5206 part->nvram_type = type;
5207
5208 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5209 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5210 outbuf, sizeof(outbuf), &outlen);
5211 if (rc)
5212 return rc;
5213 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5214 return -EIO;
5215 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5216 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5217 part->fw_subtype = MCDI_DWORD(outbuf,
5218 NVRAM_METADATA_OUT_SUBTYPE);
5219
5220 part->common.dev_type_name = "EF10 NVRAM manager";
5221 part->common.type_name = info->name;
5222
5223 part->common.mtd.type = MTD_NORFLASH;
5224 part->common.mtd.flags = MTD_CAP_NORFLASH;
5225 part->common.mtd.size = size;
5226 part->common.mtd.erasesize = erase_size;
5227
5228 return 0;
5229}
5230
5231static int efx_ef10_mtd_probe(struct efx_nic *efx)
5232{
5233 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5234 struct efx_mcdi_mtd_partition *parts;
5235 size_t outlen, n_parts_total, i, n_parts;
5236 unsigned int type;
5237 int rc;
5238
5239 ASSERT_RTNL();
5240
5241 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5242 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5243 outbuf, sizeof(outbuf), &outlen);
5244 if (rc)
5245 return rc;
5246 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5247 return -EIO;
5248
5249 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5250 if (n_parts_total >
5251 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5252 return -EIO;
5253
5254 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5255 if (!parts)
5256 return -ENOMEM;
5257
5258 n_parts = 0;
5259 for (i = 0; i < n_parts_total; i++) {
5260 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5261 i);
5262 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5263 if (rc == 0)
5264 n_parts++;
5265 else if (rc != -ENODEV)
5266 goto fail;
5267 }
5268
5269 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5270fail:
5271 if (rc)
5272 kfree(parts);
5273 return rc;
5274}
5275
5276#endif /* CONFIG_SFC_MTD */
5277
5278static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5279{
5280 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5281}
5282
02246a7f
SS		 5283static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5284 u32 host_time) {}
5285
bd9a265d
JC		 5286static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5287 bool temp)
5288{
5289 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5290 int rc;
5291
5292 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5293 channel->sync_events_state == SYNC_EVENTS_VALID ||
5294 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5295 return 0;
5296 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5297
5298 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5299 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5300 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5301 channel->channel);
5302
5303 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5304 inbuf, sizeof(inbuf), NULL, 0, NULL);
5305
5306 if (rc != 0)
5307 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5308 SYNC_EVENTS_DISABLED;
5309
5310 return rc;
5311}
5312
5313static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5314 bool temp)
5315{
5316 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5317 int rc;
5318
5319 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5320 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5321 return 0;
5322 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5323 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5324 return 0;
5325 }
5326 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5327 SYNC_EVENTS_DISABLED;
5328
5329 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5330 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5331 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5332 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5333 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5334 channel->channel);
5335
5336 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5337 inbuf, sizeof(inbuf), NULL, 0, NULL);
5338
5339 return rc;
5340}
5341
5342static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5343 bool temp)
5344{
5345 int (*set)(struct efx_channel *channel, bool temp);
5346 struct efx_channel *channel;
5347
5348 set = en ?
5349 efx_ef10_rx_enable_timestamping :
5350 efx_ef10_rx_disable_timestamping;
5351
5352 efx_for_each_channel(channel, efx) {
5353 int rc = set(channel, temp);
5354 if (en && rc != 0) {
5355 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5356 return rc;
5357 }
5358 }
5359
5360 return 0;
5361}
5362
02246a7f
SS		 5363static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5364 struct hwtstamp_config *init)
5365{
5366 return -EOPNOTSUPP;
5367}
5368
bd9a265d
JC		 5369static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5370 struct hwtstamp_config *init)
5371{
5372 int rc;
5373
5374 switch (init->rx_filter) {
5375 case HWTSTAMP_FILTER_NONE:
5376 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5377 /* if TX timestamping is still requested then leave PTP on */
5378 return efx_ptp_change_mode(efx,
5379 init->tx_type != HWTSTAMP_TX_OFF, 0);
5380 case HWTSTAMP_FILTER_ALL:
5381 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5382 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5383 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5384 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5385 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5386 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5387 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5388 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5389 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5390 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5391 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5392 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5393 init->rx_filter = HWTSTAMP_FILTER_ALL;
5394 rc = efx_ptp_change_mode(efx, true, 0);
5395 if (!rc)
5396 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5397 if (rc)
5398 efx_ptp_change_mode(efx, false, 0);
5399 return rc;
5400 default:
5401 return -ERANGE;
5402 }
5403}
5404
4a53ea8a
AR		 5405static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5406{
5407 if (proto != htons(ETH_P_8021Q))
5408 return -EINVAL;
5409
5410 return efx_ef10_add_vlan(efx, vid);
5411}
5412
5413static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5414{
5415 if (proto != htons(ETH_P_8021Q))
5416 return -EINVAL;
5417
5418 return efx_ef10_del_vlan(efx, vid);
5419}
5420
100a9db5
AR		 5421#define EF10_OFFLOAD_FEATURES \
5422 (NETIF_F_IP_CSUM | \
4a53ea8a 5423 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 5424 NETIF_F_IPV6_CSUM | \
5425 NETIF_F_RXHASH | \
5426 NETIF_F_NTUPLE)
5427
02246a7f 5428const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 5429 .is_vf = true,
02246a7f
SS		 5430 .mem_bar = EFX_MEM_VF_BAR,
5431 .mem_map_size = efx_ef10_mem_map_size,
5432 .probe = efx_ef10_probe_vf,
5433 .remove = efx_ef10_remove,
5434 .dimension_resources = efx_ef10_dimension_resources,
5435 .init = efx_ef10_init_nic,
5436 .fini = efx_port_dummy_op_void,
087e9025 5437 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 5438 .map_reset_flags = efx_ef10_map_reset_flags,
5439 .reset = efx_ef10_reset,
5440 .probe_port = efx_mcdi_port_probe,
5441 .remove_port = efx_mcdi_port_remove,
5442 .fini_dmaq = efx_ef10_fini_dmaq,
5443 .prepare_flr = efx_ef10_prepare_flr,
5444 .finish_flr = efx_port_dummy_op_void,
5445 .describe_stats = efx_ef10_describe_stats,
d7788196 5446 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 5447 .start_stats = efx_port_dummy_op_void,
5448 .pull_stats = efx_port_dummy_op_void,
5449 .stop_stats = efx_port_dummy_op_void,
5450 .set_id_led = efx_mcdi_set_id_led,
5451 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 5452 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 5453 .check_mac_fault = efx_mcdi_mac_check_fault,
5454 .reconfigure_port = efx_mcdi_port_reconfigure,
5455 .get_wol = efx_ef10_get_wol_vf,
5456 .set_wol = efx_ef10_set_wol_vf,
5457 .resume_wol = efx_port_dummy_op_void,
5458 .mcdi_request = efx_ef10_mcdi_request,
5459 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5460 .mcdi_read_response = efx_ef10_mcdi_read_response,
5461 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5462 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 5463 .irq_enable_master = efx_port_dummy_op_void,
5464 .irq_test_generate = efx_ef10_irq_test_generate,
5465 .irq_disable_non_ev = efx_port_dummy_op_void,
5466 .irq_handle_msi = efx_ef10_msi_interrupt,
5467 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5468 .tx_probe = efx_ef10_tx_probe,
5469 .tx_init = efx_ef10_tx_init,
5470 .tx_remove = efx_ef10_tx_remove,
5471 .tx_write = efx_ef10_tx_write,
267c0157 5472 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 5473 .rx_probe = efx_ef10_rx_probe,
5474 .rx_init = efx_ef10_rx_init,
5475 .rx_remove = efx_ef10_rx_remove,
5476 .rx_write = efx_ef10_rx_write,
5477 .rx_defer_refill = efx_ef10_rx_defer_refill,
5478 .ev_probe = efx_ef10_ev_probe,
5479 .ev_init = efx_ef10_ev_init,
5480 .ev_fini = efx_ef10_ev_fini,
5481 .ev_remove = efx_ef10_ev_remove,
5482 .ev_process = efx_ef10_ev_process,
5483 .ev_read_ack = efx_ef10_ev_read_ack,
5484 .ev_test_generate = efx_ef10_ev_test_generate,
5485 .filter_table_probe = efx_ef10_filter_table_probe,
5486 .filter_table_restore = efx_ef10_filter_table_restore,
5487 .filter_table_remove = efx_ef10_filter_table_remove,
5488 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5489 .filter_insert = efx_ef10_filter_insert,
5490 .filter_remove_safe = efx_ef10_filter_remove_safe,
5491 .filter_get_safe = efx_ef10_filter_get_safe,
5492 .filter_clear_rx = efx_ef10_filter_clear_rx,
5493 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5494 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5495 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5496#ifdef CONFIG_RFS_ACCEL
5497 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5498 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5499#endif
5500#ifdef CONFIG_SFC_MTD
5501 .mtd_probe = efx_port_dummy_op_int,
5502#endif
5503 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5504 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 5505 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5506 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 5507#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 5508 .vswitching_probe = efx_ef10_vswitching_probe_vf,
5509 .vswitching_restore = efx_ef10_vswitching_restore_vf,
5510 .vswitching_remove = efx_ef10_vswitching_remove_vf,
1d051e00 5511 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
02246a7f 5512#endif
0d5e0fbb 5513 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 5514 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 5515
02246a7f
SS		 5516 .revision = EFX_REV_HUNT_A0,
5517 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5518 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5519 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5520 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5521 .can_rx_scatter = true,
5522 .always_rx_scatter = true,
5523 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5524 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 5525 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f
SS		 5526 .mcdi_max_ver = 2,
5527 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5528 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5529 1 << HWTSTAMP_FILTER_ALL,
5530};
5531
8127d661 5532const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 5533 .is_vf = false,
02246a7f 5534 .mem_bar = EFX_MEM_BAR,
8127d661 5535 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 5536 .probe = efx_ef10_probe_pf,
8127d661
BH		 5537 .remove = efx_ef10_remove,
5538 .dimension_resources = efx_ef10_dimension_resources,
5539 .init = efx_ef10_init_nic,
5540 .fini = efx_port_dummy_op_void,
087e9025 5541 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 5542 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 5543 .reset = efx_ef10_reset,
8127d661
BH		 5544 .probe_port = efx_mcdi_port_probe,
5545 .remove_port = efx_mcdi_port_remove,
5546 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 5547 .prepare_flr = efx_ef10_prepare_flr,
5548 .finish_flr = efx_port_dummy_op_void,
8127d661 5549 .describe_stats = efx_ef10_describe_stats,
d7788196 5550 .update_stats = efx_ef10_update_stats_pf,
8127d661 5551 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 5552 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 5553 .stop_stats = efx_mcdi_mac_stop_stats,
5554 .set_id_led = efx_mcdi_set_id_led,
5555 .push_irq_moderation = efx_ef10_push_irq_moderation,
5556 .reconfigure_mac = efx_ef10_mac_reconfigure,
5557 .check_mac_fault = efx_mcdi_mac_check_fault,
5558 .reconfigure_port = efx_mcdi_port_reconfigure,
5559 .get_wol = efx_ef10_get_wol,
5560 .set_wol = efx_ef10_set_wol,
5561 .resume_wol = efx_port_dummy_op_void,
74cd60a4 5562 .test_chip = efx_ef10_test_chip,
8127d661
BH		 5563 .test_nvram = efx_mcdi_nvram_test_all,
5564 .mcdi_request = efx_ef10_mcdi_request,
5565 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5566 .mcdi_read_response = efx_ef10_mcdi_read_response,
5567 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5568 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 5569 .irq_enable_master = efx_port_dummy_op_void,
5570 .irq_test_generate = efx_ef10_irq_test_generate,
5571 .irq_disable_non_ev = efx_port_dummy_op_void,
5572 .irq_handle_msi = efx_ef10_msi_interrupt,
5573 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5574 .tx_probe = efx_ef10_tx_probe,
5575 .tx_init = efx_ef10_tx_init,
5576 .tx_remove = efx_ef10_tx_remove,
5577 .tx_write = efx_ef10_tx_write,
267c0157 5578 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 5579 .rx_probe = efx_ef10_rx_probe,
5580 .rx_init = efx_ef10_rx_init,
5581 .rx_remove = efx_ef10_rx_remove,
5582 .rx_write = efx_ef10_rx_write,
5583 .rx_defer_refill = efx_ef10_rx_defer_refill,
5584 .ev_probe = efx_ef10_ev_probe,
5585 .ev_init = efx_ef10_ev_init,
5586 .ev_fini = efx_ef10_ev_fini,
5587 .ev_remove = efx_ef10_ev_remove,
5588 .ev_process = efx_ef10_ev_process,
5589 .ev_read_ack = efx_ef10_ev_read_ack,
5590 .ev_test_generate = efx_ef10_ev_test_generate,
5591 .filter_table_probe = efx_ef10_filter_table_probe,
5592 .filter_table_restore = efx_ef10_filter_table_restore,
5593 .filter_table_remove = efx_ef10_filter_table_remove,
5594 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5595 .filter_insert = efx_ef10_filter_insert,
5596 .filter_remove_safe = efx_ef10_filter_remove_safe,
5597 .filter_get_safe = efx_ef10_filter_get_safe,
5598 .filter_clear_rx = efx_ef10_filter_clear_rx,
5599 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5600 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5601 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5602#ifdef CONFIG_RFS_ACCEL
5603 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5604 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5605#endif
5606#ifdef CONFIG_SFC_MTD
5607 .mtd_probe = efx_ef10_mtd_probe,
5608 .mtd_rename = efx_mcdi_mtd_rename,
5609 .mtd_read = efx_mcdi_mtd_read,
5610 .mtd_erase = efx_mcdi_mtd_erase,
5611 .mtd_write = efx_mcdi_mtd_write,
5612 .mtd_sync = efx_mcdi_mtd_sync,
5613#endif
5614 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 5615 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5616 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 5617 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5618 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
7fa8d547 5619#ifdef CONFIG_SFC_SRIOV
834e23dd 5620 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 5621 .sriov_init = efx_ef10_sriov_init,
5622 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 5623 .sriov_wanted = efx_ef10_sriov_wanted,
5624 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 5625 .sriov_flr = efx_ef10_sriov_flr,
5626 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5627 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5628 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5629 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 5630 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 5631 .vswitching_probe = efx_ef10_vswitching_probe_pf,
5632 .vswitching_restore = efx_ef10_vswitching_restore_pf,
5633 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 5634#endif
0d5e0fbb 5635 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 5636 .set_mac_address = efx_ef10_set_mac_address,
8127d661
BH		 5637
5638 .revision = EFX_REV_HUNT_A0,
5639 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5640 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5641 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 5642 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 5643 .can_rx_scatter = true,
5644 .always_rx_scatter = true,
5645 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5646 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 5647 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661
BH		 5648 .mcdi_max_ver = 2,
5649 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 5650 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5651 1 << HWTSTAMP_FILTER_ALL,
8127d661 5652};
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