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atm: solos-pci: Replace simple_strtol by kstrtoint
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
822b96f8
DP		 53struct efx_ef10_dev_addr {
54 u8 addr[ETH_ALEN];
55 u16 id;
56};
57
8127d661
BH		 58struct efx_ef10_filter_table {
59/* The RX match field masks supported by this fw & hw, in order of priority */
60 enum efx_filter_match_flags rx_match_flags[
61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
62 unsigned int rx_match_count;
63
64 struct {
65 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 66/* BUSY flag indicates that an update is in progress. AUTO_OLD is
67 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 68 */
69#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 70#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 71#define EFX_EF10_FILTER_FLAGS 3UL
72 u64 handle; /* firmware handle */
73 } *entry;
74 wait_queue_head_t waitq;
75/* Shadow of net_device address lists, guarded by mac_lock */
b59e6ef8
BH		 76#define EFX_EF10_FILTER_DEV_UC_MAX 32
77#define EFX_EF10_FILTER_DEV_MC_MAX 256
822b96f8
DP		 78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 80 int dev_uc_count;
81 int dev_mc_count;
82/* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
83 u16 ucdef_id;
84 u16 bcast_id;
85 u16 mcdef_id;
8127d661
BH		 86};
87
88/* An arbitrary search limit for the software hash table */
89#define EFX_EF10_FILTER_SEARCH_LIMIT 200
90
8127d661
BH		 91static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
92static void efx_ef10_filter_table_remove(struct efx_nic *efx);
93
94static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
95{
96 efx_dword_t reg;
97
98 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
101}
102
103static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
104{
02246a7f
SS		 105 int bar;
106
107 bar = efx->type->mem_bar;
108 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 109}
110
7a186f47
DP		 111static bool efx_ef10_is_vf(struct efx_nic *efx)
112{
113 return efx->type->is_vf;
114}
115
1cd9ecbb
DP		 116static int efx_ef10_get_pf_index(struct efx_nic *efx)
117{
118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
120 size_t outlen;
121 int rc;
122
123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
124 sizeof(outbuf), &outlen);
125 if (rc)
126 return rc;
127 if (outlen < sizeof(outbuf))
128 return -EIO;
129
130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
131 return 0;
132}
133
88a37de6
SS		 134#ifdef CONFIG_SFC_SRIOV
135static int efx_ef10_get_vf_index(struct efx_nic *efx)
136{
137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
138 struct efx_ef10_nic_data *nic_data = efx->nic_data;
139 size_t outlen;
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
143 sizeof(outbuf), &outlen);
144 if (rc)
145 return rc;
146 if (outlen < sizeof(outbuf))
147 return -EIO;
148
149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
150 return 0;
151}
152#endif
153
e5a2538a 154static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 155{
156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
157 struct efx_ef10_nic_data *nic_data = efx->nic_data;
158 size_t outlen;
159 int rc;
160
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
162
163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
164 outbuf, sizeof(outbuf), &outlen);
165 if (rc)
166 return rc;
e5a2538a
BH		 167 if (outlen < sizeof(outbuf)) {
168 netif_err(efx, drv, efx->net_dev,
169 "unable to read datapath firmware capabilities\n");
170 return -EIO;
171 }
172
173 nic_data->datapath_caps =
174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 175
8d9f9dd4
DP		 176 /* record the DPCPU firmware IDs to determine VEB vswitching support.
177 */
178 nic_data->rx_dpcpu_fw_id =
179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
180 nic_data->tx_dpcpu_fw_id =
181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
182
e5a2538a
BH		 183 if (!(nic_data->datapath_caps &
184 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
185 netif_err(efx, probe, efx->net_dev,
186 "current firmware does not support an RX prefix\n");
187 return -ENODEV;
8127d661
BH		 188 }
189
190 return 0;
191}
192
193static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
194{
195 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
196 int rc;
197
198 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
199 outbuf, sizeof(outbuf), NULL);
200 if (rc)
201 return rc;
202 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
203 return rc > 0 ? rc : -ERANGE;
204}
205
0d5e0fbb 206static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 207{
208 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
209 size_t outlen;
210 int rc;
211
212 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
213
214 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
215 outbuf, sizeof(outbuf), &outlen);
216 if (rc)
217 return rc;
218 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
219 return -EIO;
220
cd84ff4d
EC		 221 ether_addr_copy(mac_address,
222 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 223 return 0;
224}
225
0d5e0fbb
DP		 226static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
227{
228 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
229 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
230 size_t outlen;
231 int num_addrs, rc;
232
233 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
234 EVB_PORT_ID_ASSIGNED);
235 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
236 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
237
238 if (rc)
239 return rc;
240 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
241 return -EIO;
242
243 num_addrs = MCDI_DWORD(outbuf,
244 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
245
246 WARN_ON(num_addrs != 1);
247
248 ether_addr_copy(mac_address,
249 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
250
251 return 0;
252}
253
0f5c0845
SS		 254static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
255 struct device_attribute *attr,
256 char *buf)
257{
258 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
259
260 return sprintf(buf, "%d\n",
261 ((efx->mcdi->fn_flags) &
262 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
263 ? 1 : 0);
264}
265
266static ssize_t efx_ef10_show_primary_flag(struct device *dev,
267 struct device_attribute *attr,
268 char *buf)
269{
270 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
271
272 return sprintf(buf, "%d\n",
273 ((efx->mcdi->fn_flags) &
274 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
275 ? 1 : 0);
276}
277
278static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
279 NULL);
280static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
281
8127d661
BH		 282static int efx_ef10_probe(struct efx_nic *efx)
283{
284 struct efx_ef10_nic_data *nic_data;
8be41320 285 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 286 int i, rc;
287
aa3930ee
BH		 288 /* We can have one VI for each 8K region. However, until we
289 * use TX option descriptors we need two TX queues per channel.
8127d661 290 */
b0fbdae1
SS		 291 efx->max_channels = min_t(unsigned int,
292 EFX_MAX_CHANNELS,
293 efx_ef10_mem_map_size(efx) /
294 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
295 efx->max_tx_channels = efx->max_channels;
9fd3d3a4
EC		 296 if (WARN_ON(efx->max_channels == 0))
297 return -EIO;
8127d661
BH		 298
299 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
300 if (!nic_data)
301 return -ENOMEM;
302 efx->nic_data = nic_data;
303
75aba2a5
EC		 304 /* we assume later that we can copy from this buffer in dwords */
305 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
306
8127d661
BH		 307 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
308 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
309 if (rc)
310 goto fail1;
311
312 /* Get the MC's warm boot count. In case it's rebooting right
313 * now, be prepared to retry.
314 */
315 i = 0;
316 for (;;) {
317 rc = efx_ef10_get_warm_boot_count(efx);
318 if (rc >= 0)
319 break;
320 if (++i == 5)
321 goto fail2;
322 ssleep(1);
323 }
324 nic_data->warm_boot_count = rc;
325
326 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
327
45b2449e
DP		 328 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
329
8127d661
BH		 330 /* In case we're recovering from a crash (kexec), we want to
331 * cancel any outstanding request by the previous user of this
332 * function. We send a special message using the least
333 * significant bits of the 'high' (doorbell) register.
334 */
335 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
336
337 rc = efx_mcdi_init(efx);
338 if (rc)
339 goto fail2;
340
341 /* Reset (most) configuration for this function */
342 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
343 if (rc)
344 goto fail3;
345
346 /* Enable event logging */
347 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
348 if (rc)
349 goto fail3;
350
0f5c0845
SS		 351 rc = device_create_file(&efx->pci_dev->dev,
352 &dev_attr_link_control_flag);
1cd9ecbb
DP		 353 if (rc)
354 goto fail3;
355
0f5c0845
SS		 356 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
357 if (rc)
358 goto fail4;
359
360 rc = efx_ef10_get_pf_index(efx);
361 if (rc)
362 goto fail5;
363
e5a2538a 364 rc = efx_ef10_init_datapath_caps(efx);
8127d661 365 if (rc < 0)
0f5c0845 366 goto fail5;
8127d661
BH		 367
368 efx->rx_packet_len_offset =
369 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
370
8127d661
BH		 371 rc = efx_mcdi_port_get_number(efx);
372 if (rc < 0)
0f5c0845 373 goto fail5;
8127d661 374 efx->port_num = rc;
8be41320 375 net_dev->dev_port = rc;
8127d661 376
0d5e0fbb 377 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 378 if (rc)
0f5c0845 379 goto fail5;
8127d661
BH		 380
381 rc = efx_ef10_get_sysclk_freq(efx);
382 if (rc < 0)
0f5c0845 383 goto fail5;
8127d661
BH		 384 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
385
267d9d73
EC		 386 /* Check whether firmware supports bug 35388 workaround.
387 * First try to enable it, then if we get EPERM, just
388 * ask if it's already enabled
389 */
34ccfe6f 390 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
c9012e00 391 if (rc == 0) {
8127d661 392 nic_data->workaround_35388 = true;
c9012e00 393 } else if (rc == -EPERM) {
267d9d73
EC		 394 unsigned int enabled;
395
396 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
397 if (rc)
398 goto fail3;
399 nic_data->workaround_35388 = enabled &
400 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
c9012e00 401 } else if (rc != -ENOSYS && rc != -ENOENT) {
0f5c0845 402 goto fail5;
c9012e00 403 }
8127d661
BH		 404 netif_dbg(efx, probe, efx->net_dev,
405 "workaround for bug 35388 is %sabled\n",
406 nic_data->workaround_35388 ? "en" : "dis");
407
408 rc = efx_mcdi_mon_probe(efx);
267d9d73 409 if (rc && rc != -EPERM)
0f5c0845 410 goto fail5;
8127d661 411
9aecda95
BH		 412 efx_ptp_probe(efx, NULL);
413
1d051e00
SS		 414#ifdef CONFIG_SFC_SRIOV
415 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
416 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
417 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
418
419 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
420 } else
421#endif
422 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
423
8127d661
BH		 424 return 0;
425
0f5c0845
SS		 426fail5:
427 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
428fail4:
429 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 430fail3:
431 efx_mcdi_fini(efx);
432fail2:
433 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
434fail1:
435 kfree(nic_data);
436 efx->nic_data = NULL;
437 return rc;
438}
439
440static int efx_ef10_free_vis(struct efx_nic *efx)
441{
aa09a3da 442 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 443 size_t outlen;
444 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
445 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 446
447 /* -EALREADY means nothing to free, so ignore */
448 if (rc == -EALREADY)
449 rc = 0;
1e0b8120
EC		 450 if (rc)
451 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
452 rc);
8127d661
BH		 453 return rc;
454}
455
183233be
BH		 456#ifdef EFX_USE_PIO
457
458static void efx_ef10_free_piobufs(struct efx_nic *efx)
459{
460 struct efx_ef10_nic_data *nic_data = efx->nic_data;
461 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
462 unsigned int i;
463 int rc;
464
465 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
466
467 for (i = 0; i < nic_data->n_piobufs; i++) {
468 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
469 nic_data->piobuf_handle[i]);
470 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
471 NULL, 0, NULL);
472 WARN_ON(rc);
473 }
474
475 nic_data->n_piobufs = 0;
476}
477
478static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
479{
480 struct efx_ef10_nic_data *nic_data = efx->nic_data;
481 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
482 unsigned int i;
483 size_t outlen;
484 int rc = 0;
485
486 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
487
488 for (i = 0; i < n; i++) {
489 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
490 outbuf, sizeof(outbuf), &outlen);
491 if (rc)
492 break;
493 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
494 rc = -EIO;
495 break;
496 }
497 nic_data->piobuf_handle[i] =
498 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
499 netif_dbg(efx, probe, efx->net_dev,
500 "allocated PIO buffer %u handle %x\n", i,
501 nic_data->piobuf_handle[i]);
502 }
503
504 nic_data->n_piobufs = i;
505 if (rc)
506 efx_ef10_free_piobufs(efx);
507 return rc;
508}
509
510static int efx_ef10_link_piobufs(struct efx_nic *efx)
511{
512 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 513 _MCDI_DECLARE_BUF(inbuf,
514 max(MC_CMD_LINK_PIOBUF_IN_LEN,
515 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 516 struct efx_channel *channel;
517 struct efx_tx_queue *tx_queue;
518 unsigned int offset, index;
519 int rc;
520
521 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
522 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
523
aa09a3da
JC		 524 memset(inbuf, 0, sizeof(inbuf));
525
183233be
BH		 526 /* Link a buffer to each VI in the write-combining mapping */
527 for (index = 0; index < nic_data->n_piobufs; ++index) {
528 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
529 nic_data->piobuf_handle[index]);
530 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
531 nic_data->pio_write_vi_base + index);
532 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
533 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
534 NULL, 0, NULL);
535 if (rc) {
536 netif_err(efx, drv, efx->net_dev,
537 "failed to link VI %u to PIO buffer %u (%d)\n",
538 nic_data->pio_write_vi_base + index, index,
539 rc);
540 goto fail;
541 }
542 netif_dbg(efx, probe, efx->net_dev,
543 "linked VI %u to PIO buffer %u\n",
544 nic_data->pio_write_vi_base + index, index);
545 }
546
547 /* Link a buffer to each TX queue */
548 efx_for_each_channel(channel, efx) {
549 efx_for_each_channel_tx_queue(tx_queue, channel) {
550 /* We assign the PIO buffers to queues in
551 * reverse order to allow for the following
552 * special case.
553 */
554 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
555 tx_queue->channel->channel - 1) *
556 efx_piobuf_size);
557 index = offset / ER_DZ_TX_PIOBUF_SIZE;
558 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
559
560 /* When the host page size is 4K, the first
561 * host page in the WC mapping may be within
562 * the same VI page as the last TX queue. We
563 * can only link one buffer to each VI.
564 */
565 if (tx_queue->queue == nic_data->pio_write_vi_base) {
566 BUG_ON(index != 0);
567 rc = 0;
568 } else {
569 MCDI_SET_DWORD(inbuf,
570 LINK_PIOBUF_IN_PIOBUF_HANDLE,
571 nic_data->piobuf_handle[index]);
572 MCDI_SET_DWORD(inbuf,
573 LINK_PIOBUF_IN_TXQ_INSTANCE,
574 tx_queue->queue);
575 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
576 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
577 NULL, 0, NULL);
578 }
579
580 if (rc) {
581 /* This is non-fatal; the TX path just
582 * won't use PIO for this queue
583 */
584 netif_err(efx, drv, efx->net_dev,
585 "failed to link VI %u to PIO buffer %u (%d)\n",
586 tx_queue->queue, index, rc);
587 tx_queue->piobuf = NULL;
588 } else {
589 tx_queue->piobuf =
590 nic_data->pio_write_base +
591 index * EFX_VI_PAGE_SIZE + offset;
592 tx_queue->piobuf_offset = offset;
593 netif_dbg(efx, probe, efx->net_dev,
594 "linked VI %u to PIO buffer %u offset %x addr %p\n",
595 tx_queue->queue, index,
596 tx_queue->piobuf_offset,
597 tx_queue->piobuf);
598 }
599 }
600 }
601
602 return 0;
603
604fail:
605 while (index--) {
606 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
607 nic_data->pio_write_vi_base + index);
608 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
609 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
610 NULL, 0, NULL);
611 }
612 return rc;
613}
614
615#else /* !EFX_USE_PIO */
616
617static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
618{
619 return n == 0 ? 0 : -ENOBUFS;
620}
621
622static int efx_ef10_link_piobufs(struct efx_nic *efx)
623{
624 return 0;
625}
626
627static void efx_ef10_free_piobufs(struct efx_nic *efx)
628{
629}
630
631#endif /* EFX_USE_PIO */
632
8127d661
BH		 633static void efx_ef10_remove(struct efx_nic *efx)
634{
635 struct efx_ef10_nic_data *nic_data = efx->nic_data;
636 int rc;
637
f1122a34
SS		 638#ifdef CONFIG_SFC_SRIOV
639 struct efx_ef10_nic_data *nic_data_pf;
640 struct pci_dev *pci_dev_pf;
641 struct efx_nic *efx_pf;
642 struct ef10_vf *vf;
643
644 if (efx->pci_dev->is_virtfn) {
645 pci_dev_pf = efx->pci_dev->physfn;
646 if (pci_dev_pf) {
647 efx_pf = pci_get_drvdata(pci_dev_pf);
648 nic_data_pf = efx_pf->nic_data;
649 vf = nic_data_pf->vf + nic_data->vf_index;
650 vf->efx = NULL;
651 } else
652 netif_info(efx, drv, efx->net_dev,
653 "Could not get the PF id from VF\n");
654 }
655#endif
656
9aecda95
BH		 657 efx_ptp_remove(efx);
658
8127d661
BH		 659 efx_mcdi_mon_remove(efx);
660
8127d661
BH		 661 efx_ef10_rx_free_indir_table(efx);
662
183233be
BH		 663 if (nic_data->wc_membase)
664 iounmap(nic_data->wc_membase);
665
8127d661
BH		 666 rc = efx_ef10_free_vis(efx);
667 WARN_ON(rc != 0);
668
183233be
BH		 669 if (!nic_data->must_restore_piobufs)
670 efx_ef10_free_piobufs(efx);
671
0f5c0845
SS		 672 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
673 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
674
8127d661
BH		 675 efx_mcdi_fini(efx);
676 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
677 kfree(nic_data);
678}
679
88a37de6
SS		 680static int efx_ef10_probe_pf(struct efx_nic *efx)
681{
682 return efx_ef10_probe(efx);
683}
684
7a186f47
DP		 685int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
686{
687 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
688
689 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
690 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
691 NULL, 0, NULL);
692}
693
694int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
695{
696 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
697
698 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
699 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
700 NULL, 0, NULL);
701}
702
703int efx_ef10_vport_add_mac(struct efx_nic *efx,
704 unsigned int port_id, u8 *mac)
705{
706 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
707
708 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
709 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
710
711 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
712 sizeof(inbuf), NULL, 0, NULL);
713}
714
715int efx_ef10_vport_del_mac(struct efx_nic *efx,
716 unsigned int port_id, u8 *mac)
717{
718 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
719
720 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
721 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
722
723 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
724 sizeof(inbuf), NULL, 0, NULL);
725}
726
88a37de6
SS		 727#ifdef CONFIG_SFC_SRIOV
728static int efx_ef10_probe_vf(struct efx_nic *efx)
729{
730 int rc;
6598dad2
DP		 731 struct pci_dev *pci_dev_pf;
732
733 /* If the parent PF has no VF data structure, it doesn't know about this
734 * VF so fail probe. The VF needs to be re-created. This can happen
735 * if the PF driver is unloaded while the VF is assigned to a guest.
736 */
737 pci_dev_pf = efx->pci_dev->physfn;
738 if (pci_dev_pf) {
739 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
740 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
741
742 if (!nic_data_pf->vf) {
743 netif_info(efx, drv, efx->net_dev,
744 "The VF cannot link to its parent PF; "
745 "please destroy and re-create the VF\n");
746 return -EBUSY;
747 }
748 }
88a37de6
SS		 749
750 rc = efx_ef10_probe(efx);
751 if (rc)
752 return rc;
753
754 rc = efx_ef10_get_vf_index(efx);
755 if (rc)
756 goto fail;
757
f1122a34
SS		 758 if (efx->pci_dev->is_virtfn) {
759 if (efx->pci_dev->physfn) {
760 struct efx_nic *efx_pf =
761 pci_get_drvdata(efx->pci_dev->physfn);
762 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
763 struct efx_ef10_nic_data *nic_data = efx->nic_data;
764
765 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 766 nic_data_p->vf[nic_data->vf_index].pci_dev =
767 efx->pci_dev;
f1122a34
SS		 768 } else
769 netif_info(efx, drv, efx->net_dev,
770 "Could not get the PF id from VF\n");
771 }
772
88a37de6
SS		 773 return 0;
774
775fail:
776 efx_ef10_remove(efx);
777 return rc;
778}
779#else
780static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
781{
782 return 0;
783}
784#endif
785
8127d661
BH		 786static int efx_ef10_alloc_vis(struct efx_nic *efx,
787 unsigned int min_vis, unsigned int max_vis)
788{
789 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
790 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
791 struct efx_ef10_nic_data *nic_data = efx->nic_data;
792 size_t outlen;
793 int rc;
794
795 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
796 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
797 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
798 outbuf, sizeof(outbuf), &outlen);
799 if (rc != 0)
800 return rc;
801
802 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
803 return -EIO;
804
805 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
806 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
807
808 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
809 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
810 return 0;
811}
812
183233be
BH		 813/* Note that the failure path of this function does not free
814 * resources, as this will be done by efx_ef10_remove().
815 */
8127d661
BH		 816static int efx_ef10_dimension_resources(struct efx_nic *efx)
817{
183233be
BH		 818 struct efx_ef10_nic_data *nic_data = efx->nic_data;
819 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 820 unsigned int min_vis = max(EFX_TXQ_TYPES,
821 efx_separate_tx_channels ? 2 : 1);
822 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 823 void __iomem *membase;
824 int rc;
825
b0fbdae1 826 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 827
183233be
BH		 828#ifdef EFX_USE_PIO
829 /* Try to allocate PIO buffers if wanted and if the full
830 * number of PIO buffers would be sufficient to allocate one
831 * copy-buffer per TX channel. Failure is non-fatal, as there
832 * are only a small number of PIO buffers shared between all
833 * functions of the controller.
834 */
835 if (efx_piobuf_size != 0 &&
836 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
837 efx->n_tx_channels) {
838 unsigned int n_piobufs =
839 DIV_ROUND_UP(efx->n_tx_channels,
840 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
841
842 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
843 if (rc)
844 netif_err(efx, probe, efx->net_dev,
845 "failed to allocate PIO buffers (%d)\n", rc);
846 else
847 netif_dbg(efx, probe, efx->net_dev,
848 "allocated %u PIO buffers\n", n_piobufs);
849 }
850#else
851 nic_data->n_piobufs = 0;
852#endif
853
854 /* PIO buffers should be mapped with write-combining enabled,
855 * and we want to make single UC and WC mappings rather than
856 * several of each (in fact that's the only option if host
857 * page size is >4K). So we may allocate some extra VIs just
858 * for writing PIO buffers through.
52ad762b 859 *
b0fbdae1 860 * The UC mapping contains (channel_vis - 1) complete VIs and the
52ad762b
DP		 861 * first half of the next VI. Then the WC mapping begins with
862 * the second half of this last VI.
183233be 863 */
b0fbdae1 864 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
183233be
BH		 865 ER_DZ_TX_PIOBUF);
866 if (nic_data->n_piobufs) {
52ad762b
DP		 867 /* pio_write_vi_base rounds down to give the number of complete
868 * VIs inside the UC mapping.
869 */
183233be
BH		 870 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
871 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
872 nic_data->n_piobufs) *
873 EFX_VI_PAGE_SIZE) -
874 uc_mem_map_size);
875 max_vis = pio_write_vi_base + nic_data->n_piobufs;
876 } else {
877 pio_write_vi_base = 0;
878 wc_mem_map_size = 0;
b0fbdae1 879 max_vis = channel_vis;
183233be
BH		 880 }
881
882 /* In case the last attached driver failed to free VIs, do it now */
883 rc = efx_ef10_free_vis(efx);
884 if (rc != 0)
885 return rc;
886
887 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
888 if (rc != 0)
889 return rc;
890
b0fbdae1
SS		 891 if (nic_data->n_allocated_vis < channel_vis) {
892 netif_info(efx, drv, efx->net_dev,
893 "Could not allocate enough VIs to satisfy RSS"
894 " requirements. Performance may not be optimal.\n");
895 /* We didn't get the VIs to populate our channels.
896 * We could keep what we got but then we'd have more
897 * interrupts than we need.
898 * Instead calculate new max_channels and restart
899 */
900 efx->max_channels = nic_data->n_allocated_vis;
901 efx->max_tx_channels =
902 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
903
904 efx_ef10_free_vis(efx);
905 return -EAGAIN;
906 }
907
183233be
BH		 908 /* If we didn't get enough VIs to map all the PIO buffers, free the
909 * PIO buffers
910 */
911 if (nic_data->n_piobufs &&
912 nic_data->n_allocated_vis <
913 pio_write_vi_base + nic_data->n_piobufs) {
914 netif_dbg(efx, probe, efx->net_dev,
915 "%u VIs are not sufficient to map %u PIO buffers\n",
916 nic_data->n_allocated_vis, nic_data->n_piobufs);
917 efx_ef10_free_piobufs(efx);
918 }
919
920 /* Shrink the original UC mapping of the memory BAR */
921 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
922 if (!membase) {
923 netif_err(efx, probe, efx->net_dev,
924 "could not shrink memory BAR to %x\n",
925 uc_mem_map_size);
926 return -ENOMEM;
927 }
928 iounmap(efx->membase);
929 efx->membase = membase;
930
931 /* Set up the WC mapping if needed */
932 if (wc_mem_map_size) {
933 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
934 uc_mem_map_size,
935 wc_mem_map_size);
936 if (!nic_data->wc_membase) {
937 netif_err(efx, probe, efx->net_dev,
938 "could not allocate WC mapping of size %x\n",
939 wc_mem_map_size);
940 return -ENOMEM;
941 }
942 nic_data->pio_write_vi_base = pio_write_vi_base;
943 nic_data->pio_write_base =
944 nic_data->wc_membase +
945 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
946 uc_mem_map_size);
947
948 rc = efx_ef10_link_piobufs(efx);
949 if (rc)
950 efx_ef10_free_piobufs(efx);
951 }
952
953 netif_dbg(efx, probe, efx->net_dev,
954 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
955 &efx->membase_phys, efx->membase, uc_mem_map_size,
956 nic_data->wc_membase, wc_mem_map_size);
957
958 return 0;
8127d661
BH		 959}
960
961static int efx_ef10_init_nic(struct efx_nic *efx)
962{
963 struct efx_ef10_nic_data *nic_data = efx->nic_data;
964 int rc;
965
a915ccc9
BH		 966 if (nic_data->must_check_datapath_caps) {
967 rc = efx_ef10_init_datapath_caps(efx);
968 if (rc)
969 return rc;
970 nic_data->must_check_datapath_caps = false;
971 }
972
8127d661
BH		 973 if (nic_data->must_realloc_vis) {
974 /* We cannot let the number of VIs change now */
975 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
976 nic_data->n_allocated_vis);
977 if (rc)
978 return rc;
979 nic_data->must_realloc_vis = false;
980 }
981
183233be
BH		 982 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
983 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
984 if (rc == 0) {
985 rc = efx_ef10_link_piobufs(efx);
986 if (rc)
987 efx_ef10_free_piobufs(efx);
988 }
989
990 /* Log an error on failure, but this is non-fatal */
991 if (rc)
992 netif_err(efx, drv, efx->net_dev,
993 "failed to restore PIO buffers (%d)\n", rc);
994 nic_data->must_restore_piobufs = false;
995 }
996
267c0157
JC		 997 /* don't fail init if RSS setup doesn't work */
998 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
999
8127d661
BH		 1000 return 0;
1001}
1002
3e336261
JC		 1003static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1004{
1005 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1006#ifdef CONFIG_SFC_SRIOV
1007 unsigned int i;
1008#endif
3e336261
JC		 1009
1010 /* All our allocations have been reset */
1011 nic_data->must_realloc_vis = true;
1012 nic_data->must_restore_filters = true;
1013 nic_data->must_restore_piobufs = true;
1014 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1015
1016 /* Driver-created vswitches and vports must be re-created */
1017 nic_data->must_probe_vswitching = true;
1018 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1019#ifdef CONFIG_SFC_SRIOV
1020 if (nic_data->vf)
1021 for (i = 0; i < efx->vf_count; i++)
1022 nic_data->vf[i].vport_id = 0;
1023#endif
3e336261
JC		 1024}
1025
087e9025
JC		 1026static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1027{
1028 if (reason == RESET_TYPE_MC_FAILURE)
1029 return RESET_TYPE_DATAPATH;
1030
1031 return efx_mcdi_map_reset_reason(reason);
1032}
1033
8127d661
BH		 1034static int efx_ef10_map_reset_flags(u32 *flags)
1035{
1036 enum {
1037 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1038 ETH_RESET_SHARED_SHIFT),
1039 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1040 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1041 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1042 ETH_RESET_SHARED_SHIFT)
1043 };
1044
1045 /* We assume for now that our PCI function is permitted to
1046 * reset everything.
1047 */
1048
1049 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1050 *flags &= ~EF10_RESET_MC;
1051 return RESET_TYPE_WORLD;
1052 }
1053
1054 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1055 *flags &= ~EF10_RESET_PORT;
1056 return RESET_TYPE_ALL;
1057 }
1058
1059 /* no invisible reset implemented */
1060
1061 return -EINVAL;
1062}
1063
3e336261
JC		 1064static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1065{
1066 int rc = efx_mcdi_reset(efx, reset_type);
1067
27324820
DP		 1068 /* Unprivileged functions return -EPERM, but need to return success
1069 * here so that the datapath is brought back up.
1070 */
1071 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1072 rc = 0;
1073
3e336261
JC		 1074 /* If it was a port reset, trigger reallocation of MC resources.
1075 * Note that on an MC reset nothing needs to be done now because we'll
1076 * detect the MC reset later and handle it then.
e283546c
EC		 1077 * For an FLR, we never get an MC reset event, but the MC has reset all
1078 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1079 */
e283546c
EC		 1080 if ((reset_type == RESET_TYPE_ALL ||
1081 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1082 efx_ef10_reset_mc_allocations(efx);
1083 return rc;
1084}
1085
8127d661
BH		 1086#define EF10_DMA_STAT(ext_name, mcdi_name) \
1087 [EF10_STAT_ ## ext_name] = \
1088 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1089#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1090 [EF10_STAT_ ## int_name] = \
1091 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1092#define EF10_OTHER_STAT(ext_name) \
1093 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1094#define GENERIC_SW_STAT(ext_name) \
1095 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1096
1097static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1098 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1099 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1100 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1101 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1102 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1103 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1104 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1105 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1106 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1107 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1108 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1109 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1110 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1111 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1112 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1113 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1114 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1115 EF10_OTHER_STAT(port_rx_good_bytes),
1116 EF10_OTHER_STAT(port_rx_bad_bytes),
1117 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1118 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1119 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1120 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1121 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1122 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1123 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1124 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1125 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1126 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1127 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1128 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1129 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1130 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1131 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1132 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1133 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1134 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1135 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1136 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1137 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1138 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1139 GENERIC_SW_STAT(rx_nodesc_trunc),
1140 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1141 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1142 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1143 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1144 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1145 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1146 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1147 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1148 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1149 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1150 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1151 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1152 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1153 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1154 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1155 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1156 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1157 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1158 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1159 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1160 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1161 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1162 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1163 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1164 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1165 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1166 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1167 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1168 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1169 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1170 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1171};
1172
e80ca013
DP		 1173#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1174 (1ULL << EF10_STAT_port_tx_packets) | \
1175 (1ULL << EF10_STAT_port_tx_pause) | \
1176 (1ULL << EF10_STAT_port_tx_unicast) | \
1177 (1ULL << EF10_STAT_port_tx_multicast) | \
1178 (1ULL << EF10_STAT_port_tx_broadcast) | \
1179 (1ULL << EF10_STAT_port_rx_bytes) | \
1180 (1ULL << \
1181 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1182 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1183 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1184 (1ULL << EF10_STAT_port_rx_packets) | \
1185 (1ULL << EF10_STAT_port_rx_good) | \
1186 (1ULL << EF10_STAT_port_rx_bad) | \
1187 (1ULL << EF10_STAT_port_rx_pause) | \
1188 (1ULL << EF10_STAT_port_rx_control) | \
1189 (1ULL << EF10_STAT_port_rx_unicast) | \
1190 (1ULL << EF10_STAT_port_rx_multicast) | \
1191 (1ULL << EF10_STAT_port_rx_broadcast) | \
1192 (1ULL << EF10_STAT_port_rx_lt64) | \
1193 (1ULL << EF10_STAT_port_rx_64) | \
1194 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1195 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1196 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1197 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1198 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1199 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1200 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1201 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1202 (1ULL << EF10_STAT_port_rx_overflow) | \
1203 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1204 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1205 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661
BH		 1206
1207/* These statistics are only provided by the 10G MAC. For a 10G/40G
1208 * switchable port we do not expose these because they might not
1209 * include all the packets they should.
1210 */
e80ca013
DP		 1211#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1212 (1ULL << EF10_STAT_port_tx_lt64) | \
1213 (1ULL << EF10_STAT_port_tx_64) | \
1214 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1215 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1216 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1217 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1218 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1219 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1220
1221/* These statistics are only provided by the 40G MAC. For a 10G/40G
1222 * switchable port we do expose these because the errors will otherwise
1223 * be silent.
1224 */
e80ca013
DP		 1225#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1226 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1227
568d7a00
EC		 1228/* These statistics are only provided if the firmware supports the
1229 * capability PM_AND_RXDP_COUNTERS.
1230 */
1231#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1232 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1233 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1234 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1235 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1236 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1237 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1238 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1239 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1240 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1241 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1242 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1243 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1244
4bae913b 1245static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1246{
4bae913b 1247 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1248 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1249 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1250
3c36a2ad
DP		 1251 if (!(efx->mcdi->fn_flags &
1252 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1253 return 0;
1254
8127d661 1255 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 1256 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 1257 else
4bae913b 1258 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 1259
1260 if (nic_data->datapath_caps &
1261 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1262 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1263
4bae913b
EC		 1264 return raw_mask;
1265}
1266
1267static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1268{
d94619cd 1269 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1270 u64 raw_mask[2];
1271
1272 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1273
d94619cd
DP		 1274 /* Only show vadaptor stats when EVB capability is present */
1275 if (nic_data->datapath_caps &
1276 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1277 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1278 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1279 } else {
1280 raw_mask[1] = 0;
1281 }
4bae913b
EC		 1282
1283#if BITS_PER_LONG == 64
3c36a2ad
DP		 1284 mask[0] = raw_mask[0];
1285 mask[1] = raw_mask[1];
4bae913b 1286#else
3c36a2ad
DP		 1287 mask[0] = raw_mask[0] & 0xffffffff;
1288 mask[1] = raw_mask[0] >> 32;
1289 mask[2] = raw_mask[1] & 0xffffffff;
1290 mask[3] = raw_mask[1] >> 32;
4bae913b 1291#endif
8127d661
BH		 1292}
1293
1294static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1295{
4bae913b
EC		 1296 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1297
1298 efx_ef10_get_stat_mask(efx, mask);
8127d661 1299 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1300 mask, names);
8127d661
BH		 1301}
1302
d7788196
DP		 1303static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1304 struct rtnl_link_stats64 *core_stats)
1305{
1306 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1307 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1308 u64 *stats = nic_data->stats;
1309 size_t stats_count = 0, index;
1310
1311 efx_ef10_get_stat_mask(efx, mask);
1312
1313 if (full_stats) {
1314 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1315 if (efx_ef10_stat_desc[index].name) {
1316 *full_stats++ = stats[index];
1317 ++stats_count;
1318 }
1319 }
1320 }
1321
fbe4307e
BK		 1322 if (!core_stats)
1323 return stats_count;
1324
1325 if (nic_data->datapath_caps &
1326 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1327 /* Use vadaptor stats. */
0fc95fca
DP		 1328 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1329 stats[EF10_STAT_rx_multicast] +
1330 stats[EF10_STAT_rx_broadcast];
1331 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1332 stats[EF10_STAT_tx_multicast] +
1333 stats[EF10_STAT_tx_broadcast];
1334 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1335 stats[EF10_STAT_rx_multicast_bytes] +
1336 stats[EF10_STAT_rx_broadcast_bytes];
1337 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1338 stats[EF10_STAT_tx_multicast_bytes] +
1339 stats[EF10_STAT_tx_broadcast_bytes];
1340 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1341 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1342 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1343 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1344 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1345 core_stats->rx_errors = core_stats->rx_crc_errors;
1346 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1347 } else {
1348 /* Use port stats. */
1349 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1350 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1351 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1352 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1353 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1354 stats[GENERIC_STAT_rx_nodesc_trunc] +
1355 stats[GENERIC_STAT_rx_noskb_drops];
1356 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1357 core_stats->rx_length_errors =
1358 stats[EF10_STAT_port_rx_gtjumbo] +
1359 stats[EF10_STAT_port_rx_length_error];
1360 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1361 core_stats->rx_frame_errors =
1362 stats[EF10_STAT_port_rx_align_error];
1363 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1364 core_stats->rx_errors = (core_stats->rx_length_errors +
1365 core_stats->rx_crc_errors +
1366 core_stats->rx_frame_errors);
d7788196
DP		 1367 }
1368
1369 return stats_count;
1370}
1371
1372static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1373{
1374 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1375 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1376 __le64 generation_start, generation_end;
1377 u64 *stats = nic_data->stats;
1378 __le64 *dma_stats;
1379
4bae913b
EC		 1380 efx_ef10_get_stat_mask(efx, mask);
1381
8127d661
BH		 1382 dma_stats = efx->stats_buffer.addr;
1383 nic_data = efx->nic_data;
1384
1385 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1386 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1387 return 0;
1388 rmb();
4bae913b 1389 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1390 stats, efx->stats_buffer.addr, false);
d546a893 1391 rmb();
8127d661
BH		 1392 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1393 if (generation_end != generation_start)
1394 return -EAGAIN;
1395
1396 /* Update derived statistics */
e80ca013
DP		 1397 efx_nic_fix_nodesc_drop_stat(efx,
1398 &stats[EF10_STAT_port_rx_nodesc_drops]);
1399 stats[EF10_STAT_port_rx_good_bytes] =
1400 stats[EF10_STAT_port_rx_bytes] -
1401 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1402 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1403 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1404 efx_update_sw_stats(efx, stats);
8127d661
BH		 1405 return 0;
1406}
1407
1408
d7788196
DP		 1409static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1410 struct rtnl_link_stats64 *core_stats)
8127d661 1411{
8127d661
BH		 1412 int retry;
1413
1414 /* If we're unlucky enough to read statistics during the DMA, wait
1415 * up to 10ms for it to finish (typically takes <500us)
1416 */
1417 for (retry = 0; retry < 100; ++retry) {
d7788196 1418 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1419 break;
1420 udelay(100);
1421 }
1422
d7788196
DP		 1423 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1424}
8127d661 1425
d7788196
DP		 1426static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1427{
1428 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1429 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1430 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1431 __le64 generation_start, generation_end;
1432 u64 *stats = nic_data->stats;
1433 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1434 struct efx_buffer stats_buf;
1435 __le64 *dma_stats;
1436 int rc;
1437
f00bf230
DP		 1438 spin_unlock_bh(&efx->stats_lock);
1439
1440 if (in_interrupt()) {
1441 /* If in atomic context, cannot update stats. Just update the
1442 * software stats and return so the caller can continue.
1443 */
1444 spin_lock_bh(&efx->stats_lock);
1445 efx_update_sw_stats(efx, stats);
1446 return 0;
1447 }
1448
d7788196
DP		 1449 efx_ef10_get_stat_mask(efx, mask);
1450
1451 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1452 if (rc) {
1453 spin_lock_bh(&efx->stats_lock);
d7788196 1454 return rc;
f00bf230 1455 }
d7788196
DP		 1456
1457 dma_stats = stats_buf.addr;
1458 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1459
1460 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1461 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1462 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1463 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1464 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1465
6dd4859b
DP		 1466 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1467 NULL, 0, NULL);
d7788196 1468 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1469 if (rc) {
1470 /* Expect ENOENT if DMA queues have not been set up */
1471 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1472 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1473 sizeof(inbuf), NULL, 0, rc);
d7788196 1474 goto out;
6dd4859b 1475 }
d7788196
DP		 1476
1477 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1478 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1479 WARN_ON_ONCE(1);
d7788196 1480 goto out;
0fc95fca 1481 }
d7788196
DP		 1482 rmb();
1483 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1484 stats, stats_buf.addr, false);
1485 rmb();
1486 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1487 if (generation_end != generation_start) {
1488 rc = -EAGAIN;
1489 goto out;
8127d661
BH		 1490 }
1491
d7788196
DP		 1492 efx_update_sw_stats(efx, stats);
1493out:
1494 efx_nic_free_buffer(efx, &stats_buf);
1495 return rc;
1496}
1497
1498static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1499 struct rtnl_link_stats64 *core_stats)
1500{
1501 if (efx_ef10_try_update_nic_stats_vf(efx))
1502 return 0;
1503
1504 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1505}
1506
1507static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1508{
1509 struct efx_nic *efx = channel->efx;
1510 unsigned int mode, value;
1511 efx_dword_t timer_cmd;
1512
1513 if (channel->irq_moderation) {
1514 mode = 3;
1515 value = channel->irq_moderation - 1;
1516 } else {
1517 mode = 0;
1518 value = 0;
1519 }
1520
1521 if (EFX_EF10_WORKAROUND_35388(efx)) {
1522 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1523 EFE_DD_EVQ_IND_TIMER_FLAGS,
1524 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1525 ERF_DD_EVQ_IND_TIMER_VAL, value);
1526 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1527 channel->channel);
1528 } else {
1529 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1530 ERF_DZ_TC_TIMER_VAL, value);
1531 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1532 channel->channel);
1533 }
1534}
1535
02246a7f
SS		 1536static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1537 struct ethtool_wolinfo *wol) {}
1538
1539static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1540{
1541 return -EOPNOTSUPP;
1542}
1543
8127d661
BH		 1544static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1545{
1546 wol->supported = 0;
1547 wol->wolopts = 0;
1548 memset(&wol->sopass, 0, sizeof(wol->sopass));
1549}
1550
1551static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1552{
1553 if (type != 0)
1554 return -EINVAL;
1555 return 0;
1556}
1557
1558static void efx_ef10_mcdi_request(struct efx_nic *efx,
1559 const efx_dword_t *hdr, size_t hdr_len,
1560 const efx_dword_t *sdu, size_t sdu_len)
1561{
1562 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1563 u8 *pdu = nic_data->mcdi_buf.addr;
1564
1565 memcpy(pdu, hdr, hdr_len);
1566 memcpy(pdu + hdr_len, sdu, sdu_len);
1567 wmb();
1568
1569 /* The hardware provides 'low' and 'high' (doorbell) registers
1570 * for passing the 64-bit address of an MCDI request to
1571 * firmware. However the dwords are swapped by firmware. The
1572 * least significant bits of the doorbell are then 0 for all
1573 * MCDI requests due to alignment.
1574 */
1575 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1576 ER_DZ_MC_DB_LWRD);
1577 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1578 ER_DZ_MC_DB_HWRD);
1579}
1580
1581static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1582{
1583 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1584 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1585
1586 rmb();
1587 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1588}
1589
1590static void
1591efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1592 size_t offset, size_t outlen)
1593{
1594 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1595 const u8 *pdu = nic_data->mcdi_buf.addr;
1596
1597 memcpy(outbuf, pdu + offset, outlen);
1598}
1599
c577e59e
DP		 1600static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1601{
1602 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1603
1604 /* All our allocations have been reset */
1605 efx_ef10_reset_mc_allocations(efx);
1606
1607 /* The datapath firmware might have been changed */
1608 nic_data->must_check_datapath_caps = true;
1609
1610 /* MAC statistics have been cleared on the NIC; clear the local
1611 * statistic that we update with efx_update_diff_stat().
1612 */
1613 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1614}
1615
8127d661
BH		 1616static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1617{
1618 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1619 int rc;
1620
1621 rc = efx_ef10_get_warm_boot_count(efx);
1622 if (rc < 0) {
1623 /* The firmware is presumably in the process of
1624 * rebooting. However, we are supposed to report each
1625 * reboot just once, so we must only do that once we
1626 * can read and store the updated warm boot count.
1627 */
1628 return 0;
1629 }
1630
1631 if (rc == nic_data->warm_boot_count)
1632 return 0;
1633
1634 nic_data->warm_boot_count = rc;
c577e59e 1635 efx_ef10_mcdi_reboot_detected(efx);
869070c5 1636
8127d661
BH		 1637 return -EIO;
1638}
1639
1640/* Handle an MSI interrupt
1641 *
1642 * Handle an MSI hardware interrupt. This routine schedules event
1643 * queue processing. No interrupt acknowledgement cycle is necessary.
1644 * Also, we never need to check that the interrupt is for us, since
1645 * MSI interrupts cannot be shared.
1646 */
1647static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1648{
1649 struct efx_msi_context *context = dev_id;
1650 struct efx_nic *efx = context->efx;
1651
1652 netif_vdbg(efx, intr, efx->net_dev,
1653 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1654
1655 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1656 /* Note test interrupts */
1657 if (context->index == efx->irq_level)
1658 efx->last_irq_cpu = raw_smp_processor_id();
1659
1660 /* Schedule processing of the channel */
1661 efx_schedule_channel_irq(efx->channel[context->index]);
1662 }
1663
1664 return IRQ_HANDLED;
1665}
1666
1667static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1668{
1669 struct efx_nic *efx = dev_id;
1670 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1671 struct efx_channel *channel;
1672 efx_dword_t reg;
1673 u32 queues;
1674
1675 /* Read the ISR which also ACKs the interrupts */
1676 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1677 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1678
1679 if (queues == 0)
1680 return IRQ_NONE;
1681
1682 if (likely(soft_enabled)) {
1683 /* Note test interrupts */
1684 if (queues & (1U << efx->irq_level))
1685 efx->last_irq_cpu = raw_smp_processor_id();
1686
1687 efx_for_each_channel(channel, efx) {
1688 if (queues & 1)
1689 efx_schedule_channel_irq(channel);
1690 queues >>= 1;
1691 }
1692 }
1693
1694 netif_vdbg(efx, intr, efx->net_dev,
1695 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1696 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1697
1698 return IRQ_HANDLED;
1699}
1700
1701static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1702{
1703 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1704
1705 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1706
1707 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1708 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1709 inbuf, sizeof(inbuf), NULL, 0, NULL);
1710}
1711
1712static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1713{
1714 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1715 (tx_queue->ptr_mask + 1) *
1716 sizeof(efx_qword_t),
1717 GFP_KERNEL);
1718}
1719
1720/* This writes to the TX_DESC_WPTR and also pushes data */
1721static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1722 const efx_qword_t *txd)
1723{
1724 unsigned int write_ptr;
1725 efx_oword_t reg;
1726
1727 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1728 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1729 reg.qword[0] = *txd;
1730 efx_writeo_page(tx_queue->efx, &reg,
1731 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1732}
1733
1734static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1735{
1736 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1737 EFX_BUF_SIZE));
8127d661
BH		 1738 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1739 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1740 struct efx_channel *channel = tx_queue->channel;
1741 struct efx_nic *efx = tx_queue->efx;
45b2449e 1742 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1743 size_t inlen;
8127d661
BH		 1744 dma_addr_t dma_addr;
1745 efx_qword_t *txd;
1746 int rc;
1747 int i;
aa09a3da 1748 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661
BH		 1749
1750 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1751 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1752 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1753 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1754 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1755 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1756 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1757 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 1758 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 1759
1760 dma_addr = tx_queue->txd.buf.dma_addr;
1761
1762 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1763 tx_queue->queue, entries, (u64)dma_addr);
1764
1765 for (i = 0; i < entries; ++i) {
1766 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1767 dma_addr += EFX_BUF_SIZE;
1768 }
1769
1770 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1771
1772 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
aa09a3da 1773 NULL, 0, NULL);
8127d661
BH		 1774 if (rc)
1775 goto fail;
1776
1777 /* A previous user of this TX queue might have set us up the
1778 * bomb by writing a descriptor to the TX push collector but
1779 * not the doorbell. (Each collector belongs to a port, not a
1780 * queue or function, so cannot easily be reset.) We must
1781 * attempt to push a no-op descriptor in its place.
1782 */
1783 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1784 tx_queue->insert_count = 1;
1785 txd = efx_tx_desc(tx_queue, 0);
1786 EFX_POPULATE_QWORD_4(*txd,
1787 ESF_DZ_TX_DESC_IS_OPT, true,
1788 ESF_DZ_TX_OPTION_TYPE,
1789 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1790 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1791 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1792 tx_queue->write_count = 1;
93171b14
BK		 1793
1794 if (nic_data->datapath_caps &
1795 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
1796 tx_queue->tso_version = 1;
1797 }
1798
8127d661
BH		 1799 wmb();
1800 efx_ef10_push_tx_desc(tx_queue, txd);
1801
1802 return;
1803
1804fail:
48ce5634
BH		 1805 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1806 tx_queue->queue);
8127d661
BH		 1807}
1808
1809static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1810{
1811 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 1812 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 1813 struct efx_nic *efx = tx_queue->efx;
1814 size_t outlen;
1815 int rc;
1816
1817 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1818 tx_queue->queue);
1819
1e0b8120 1820 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1821 outbuf, sizeof(outbuf), &outlen);
1822
1823 if (rc && rc != -EALREADY)
1824 goto fail;
1825
1826 return;
1827
1828fail:
1e0b8120
EC		 1829 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1830 outbuf, outlen, rc);
8127d661
BH		 1831}
1832
1833static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1834{
1835 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1836}
1837
1838/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1839static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1840{
1841 unsigned int write_ptr;
1842 efx_dword_t reg;
1843
1844 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1845 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1846 efx_writed_page(tx_queue->efx, &reg,
1847 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1848}
1849
1850static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1851{
1852 unsigned int old_write_count = tx_queue->write_count;
1853 struct efx_tx_buffer *buffer;
1854 unsigned int write_ptr;
1855 efx_qword_t *txd;
1856
b2663a4f
MH		 1857 tx_queue->xmit_more_available = false;
1858 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
1859 return;
8127d661
BH		 1860
1861 do {
1862 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1863 buffer = &tx_queue->buffer[write_ptr];
1864 txd = efx_tx_desc(tx_queue, write_ptr);
1865 ++tx_queue->write_count;
1866
1867 /* Create TX descriptor ring entry */
1868 if (buffer->flags & EFX_TX_BUF_OPTION) {
1869 *txd = buffer->option;
1870 } else {
1871 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1872 EFX_POPULATE_QWORD_3(
1873 *txd,
1874 ESF_DZ_TX_KER_CONT,
1875 buffer->flags & EFX_TX_BUF_CONT,
1876 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1877 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1878 }
1879 } while (tx_queue->write_count != tx_queue->insert_count);
1880
1881 wmb(); /* Ensure descriptors are written before they are fetched */
1882
1883 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1884 txd = efx_tx_desc(tx_queue,
1885 old_write_count & tx_queue->ptr_mask);
1886 efx_ef10_push_tx_desc(tx_queue, txd);
1887 ++tx_queue->pushes;
1888 } else {
1889 efx_ef10_notify_tx_desc(tx_queue);
1890 }
1891}
1892
267c0157
JC		 1893static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1894 bool exclusive, unsigned *context_size)
8127d661
BH		 1895{
1896 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1897 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 1898 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 1899 size_t outlen;
1900 int rc;
267c0157
JC		 1901 u32 alloc_type = exclusive ?
1902 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1903 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1904 unsigned rss_spread = exclusive ?
1905 efx->rss_spread :
1906 min(rounddown_pow_of_two(efx->rss_spread),
1907 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1908
1909 if (!exclusive && rss_spread == 1) {
1910 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1911 if (context_size)
1912 *context_size = 1;
1913 return 0;
1914 }
8127d661
BH		 1915
1916 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 1917 nic_data->vport_id);
267c0157
JC		 1918 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1919 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 1920
1921 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1922 outbuf, sizeof(outbuf), &outlen);
1923 if (rc != 0)
1924 return rc;
1925
1926 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1927 return -EIO;
1928
1929 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1930
267c0157
JC		 1931 if (context_size)
1932 *context_size = rss_spread;
1933
8127d661
BH		 1934 return 0;
1935}
1936
1937static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1938{
1939 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1940 int rc;
1941
1942 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1943 context);
1944
1945 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1946 NULL, 0, NULL);
1947 WARN_ON(rc != 0);
1948}
1949
267c0157
JC		 1950static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1951 const u32 *rx_indir_table)
8127d661
BH		 1952{
1953 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1954 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1955 int i, rc;
1956
1957 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1958 context);
1959 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1960 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1961
1962 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1963 MCDI_PTR(tablebuf,
1964 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 1965 (u8) rx_indir_table[i];
8127d661
BH		 1966
1967 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1968 sizeof(tablebuf), NULL, 0, NULL);
1969 if (rc != 0)
1970 return rc;
1971
1972 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1973 context);
1974 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1975 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1976 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1977 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1978 efx->rx_hash_key[i];
1979
1980 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1981 sizeof(keybuf), NULL, 0, NULL);
1982}
1983
1984static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1985{
1986 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1987
1988 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1989 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1990 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1991}
1992
267c0157
JC		 1993static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1994 unsigned *context_size)
8127d661 1995{
267c0157 1996 u32 new_rx_rss_context;
8127d661 1997 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 1998 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1999 false, context_size);
2000
2001 if (rc != 0)
2002 return rc;
8127d661 2003
267c0157
JC		 2004 nic_data->rx_rss_context = new_rx_rss_context;
2005 nic_data->rx_rss_context_exclusive = false;
2006 efx_set_default_rx_indir_table(efx);
2007 return 0;
2008}
8127d661 2009
267c0157
JC		 2010static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2011 const u32 *rx_indir_table)
2012{
2013 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2014 int rc;
2015 u32 new_rx_rss_context;
2016
2017 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2018 !nic_data->rx_rss_context_exclusive) {
2019 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2020 true, NULL);
2021 if (rc == -EOPNOTSUPP)
2022 return rc;
2023 else if (rc != 0)
2024 goto fail1;
2025 } else {
2026 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2027 }
2028
267c0157
JC		 2029 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2030 rx_indir_table);
8127d661 2031 if (rc != 0)
267c0157 2032 goto fail2;
8127d661 2033
267c0157
JC		 2034 if (nic_data->rx_rss_context != new_rx_rss_context)
2035 efx_ef10_rx_free_indir_table(efx);
2036 nic_data->rx_rss_context = new_rx_rss_context;
2037 nic_data->rx_rss_context_exclusive = true;
2038 if (rx_indir_table != efx->rx_indir_table)
2039 memcpy(efx->rx_indir_table, rx_indir_table,
2040 sizeof(efx->rx_indir_table));
2041 return 0;
8127d661 2042
267c0157
JC		 2043fail2:
2044 if (new_rx_rss_context != nic_data->rx_rss_context)
2045 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2046fail1:
8127d661 2047 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2048 return rc;
2049}
2050
2051static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2052 const u32 *rx_indir_table)
2053{
2054 int rc;
2055
2056 if (efx->rss_spread == 1)
2057 return 0;
2058
2059 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2060
2061 if (rc == -ENOBUFS && !user) {
2062 unsigned context_size;
2063 bool mismatch = false;
2064 size_t i;
2065
2066 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2067 i++)
2068 mismatch = rx_indir_table[i] !=
2069 ethtool_rxfh_indir_default(i, efx->rss_spread);
2070
2071 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2072 if (rc == 0) {
2073 if (context_size != efx->rss_spread)
2074 netif_warn(efx, probe, efx->net_dev,
2075 "Could not allocate an exclusive RSS"
2076 " context; allocated a shared one of"
2077 " different size."
2078 " Wanted %u, got %u.\n",
2079 efx->rss_spread, context_size);
2080 else if (mismatch)
2081 netif_warn(efx, probe, efx->net_dev,
2082 "Could not allocate an exclusive RSS"
2083 " context; allocated a shared one but"
2084 " could not apply custom"
2085 " indirection.\n");
2086 else
2087 netif_info(efx, probe, efx->net_dev,
2088 "Could not allocate an exclusive RSS"
2089 " context; allocated a shared one.\n");
2090 }
2091 }
2092 return rc;
2093}
2094
2095static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2096 const u32 *rx_indir_table
2097 __attribute__ ((unused)))
2098{
2099 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2100
2101 if (user)
2102 return -EOPNOTSUPP;
2103 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2104 return 0;
2105 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2106}
2107
2108static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2109{
2110 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2111 (rx_queue->ptr_mask + 1) *
2112 sizeof(efx_qword_t),
2113 GFP_KERNEL);
2114}
2115
2116static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2117{
2118 MCDI_DECLARE_BUF(inbuf,
2119 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2120 EFX_BUF_SIZE));
8127d661
BH		 2121 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2122 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2123 struct efx_nic *efx = rx_queue->efx;
45b2449e 2124 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2125 size_t inlen;
8127d661
BH		 2126 dma_addr_t dma_addr;
2127 int rc;
2128 int i;
aa09a3da 2129 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2130
2131 rx_queue->scatter_n = 0;
2132 rx_queue->scatter_len = 0;
2133
2134 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2135 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2136 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2137 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2138 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2139 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2140 INIT_RXQ_IN_FLAG_PREFIX, 1,
2141 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2142 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2143 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2144
2145 dma_addr = rx_queue->rxd.buf.dma_addr;
2146
2147 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2148 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2149
2150 for (i = 0; i < entries; ++i) {
2151 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2152 dma_addr += EFX_BUF_SIZE;
2153 }
2154
2155 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2156
2157 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2158 NULL, 0, NULL);
48ce5634
BH		 2159 if (rc)
2160 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2161 efx_rx_queue_index(rx_queue));
8127d661
BH		 2162}
2163
2164static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2165{
2166 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2167 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2168 struct efx_nic *efx = rx_queue->efx;
2169 size_t outlen;
2170 int rc;
2171
2172 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2173 efx_rx_queue_index(rx_queue));
2174
1e0b8120 2175 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2176 outbuf, sizeof(outbuf), &outlen);
2177
2178 if (rc && rc != -EALREADY)
2179 goto fail;
2180
2181 return;
2182
2183fail:
1e0b8120
EC		 2184 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2185 outbuf, outlen, rc);
8127d661
BH		 2186}
2187
2188static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2189{
2190 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2191}
2192
2193/* This creates an entry in the RX descriptor queue */
2194static inline void
2195efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2196{
2197 struct efx_rx_buffer *rx_buf;
2198 efx_qword_t *rxd;
2199
2200 rxd = efx_rx_desc(rx_queue, index);
2201 rx_buf = efx_rx_buffer(rx_queue, index);
2202 EFX_POPULATE_QWORD_2(*rxd,
2203 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2204 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2205}
2206
2207static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2208{
2209 struct efx_nic *efx = rx_queue->efx;
2210 unsigned int write_count;
2211 efx_dword_t reg;
2212
2213 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2214 write_count = rx_queue->added_count & ~7;
2215 if (rx_queue->notified_count == write_count)
2216 return;
2217
2218 do
2219 efx_ef10_build_rx_desc(
2220 rx_queue,
2221 rx_queue->notified_count & rx_queue->ptr_mask);
2222 while (++rx_queue->notified_count != write_count);
2223
2224 wmb();
2225 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2226 write_count & rx_queue->ptr_mask);
2227 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2228 efx_rx_queue_index(rx_queue));
2229}
2230
2231static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2232
2233static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2234{
2235 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2236 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2237 efx_qword_t event;
2238
2239 EFX_POPULATE_QWORD_2(event,
2240 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2241 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2242
2243 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2244
2245 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2246 * already swapped the data to little-endian order.
2247 */
2248 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2249 sizeof(efx_qword_t));
2250
2251 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2252 inbuf, sizeof(inbuf), 0,
2253 efx_ef10_rx_defer_refill_complete, 0);
2254}
2255
2256static void
2257efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2258 int rc, efx_dword_t *outbuf,
2259 size_t outlen_actual)
2260{
2261 /* nothing to do */
2262}
2263
2264static int efx_ef10_ev_probe(struct efx_channel *channel)
2265{
2266 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2267 (channel->eventq_mask + 1) *
2268 sizeof(efx_qword_t),
2269 GFP_KERNEL);
2270}
2271
46e612b0
DP		 2272static void efx_ef10_ev_fini(struct efx_channel *channel)
2273{
2274 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2275 MCDI_DECLARE_BUF_ERR(outbuf);
2276 struct efx_nic *efx = channel->efx;
2277 size_t outlen;
2278 int rc;
2279
2280 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2281
2282 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2283 outbuf, sizeof(outbuf), &outlen);
2284
2285 if (rc && rc != -EALREADY)
2286 goto fail;
2287
2288 return;
2289
2290fail:
2291 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2292 outbuf, outlen, rc);
2293}
2294
8127d661
BH		 2295static int efx_ef10_ev_init(struct efx_channel *channel)
2296{
2297 MCDI_DECLARE_BUF(inbuf,
2298 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2299 EFX_BUF_SIZE));
2300 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2301 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2302 struct efx_nic *efx = channel->efx;
2303 struct efx_ef10_nic_data *nic_data;
2304 bool supports_rx_merge;
2305 size_t inlen, outlen;
46e612b0 2306 unsigned int enabled, implemented;
8127d661
BH		 2307 dma_addr_t dma_addr;
2308 int rc;
2309 int i;
2310
2311 nic_data = efx->nic_data;
2312 supports_rx_merge =
2313 !!(nic_data->datapath_caps &
2314 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2315
2316 /* Fill event queue with all ones (i.e. empty events) */
2317 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2318
2319 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2320 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2321 /* INIT_EVQ expects index in vector table, not absolute */
2322 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2323 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2324 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2325 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2326 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2327 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2328 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2329 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2330 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2331 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2332 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2333 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2334 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2335
2336 dma_addr = channel->eventq.buf.dma_addr;
2337 for (i = 0; i < entries; ++i) {
2338 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2339 dma_addr += EFX_BUF_SIZE;
2340 }
2341
2342 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2343
2344 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2345 outbuf, sizeof(outbuf), &outlen);
8127d661 2346 /* IRQ return is ignored */
46e612b0
DP		 2347 if (channel->channel || rc)
2348 return rc;
8127d661 2349
46e612b0
DP		 2350 /* Successfully created event queue on channel 0 */
2351 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed
EC		 2352 if (rc == -ENOSYS) {
2353 /* GET_WORKAROUNDS was implemented before the bug26807
2354 * workaround, thus the latter must be unavailable in this fw
2355 */
2356 nic_data->workaround_26807 = false;
2357 rc = 0;
2358 } else if (rc) {
8127d661 2359 goto fail;
832dc9ed
EC		 2360 } else {
2361 nic_data->workaround_26807 =
2362 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2363
2364 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2365 !nic_data->workaround_26807) {
5a55a72a
DP		 2366 unsigned int flags;
2367
34ccfe6f
DP		 2368 rc = efx_mcdi_set_workaround(efx,
2369 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 2370 true, &flags);
2371
2372 if (!rc) {
2373 if (flags &
2374 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2375 netif_info(efx, drv, efx->net_dev,
2376 "other functions on NIC have been reset\n");
2377 /* MC's boot count has incremented */
2378 ++nic_data->warm_boot_count;
2379 }
832dc9ed 2380 nic_data->workaround_26807 = true;
5a55a72a 2381 } else if (rc == -EPERM) {
832dc9ed 2382 rc = 0;
5a55a72a 2383 }
832dc9ed 2384 }
46e612b0
DP		 2385 }
2386
2387 if (!rc)
2388 return 0;
8127d661
BH		 2389
2390fail:
46e612b0
DP		 2391 efx_ef10_ev_fini(channel);
2392 return rc;
8127d661
BH		 2393}
2394
2395static void efx_ef10_ev_remove(struct efx_channel *channel)
2396{
2397 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2398}
2399
2400static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2401 unsigned int rx_queue_label)
2402{
2403 struct efx_nic *efx = rx_queue->efx;
2404
2405 netif_info(efx, hw, efx->net_dev,
2406 "rx event arrived on queue %d labeled as queue %u\n",
2407 efx_rx_queue_index(rx_queue), rx_queue_label);
2408
2409 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2410}
2411
2412static void
2413efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2414 unsigned int actual, unsigned int expected)
2415{
2416 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2417 struct efx_nic *efx = rx_queue->efx;
2418
2419 netif_info(efx, hw, efx->net_dev,
2420 "dropped %d events (index=%d expected=%d)\n",
2421 dropped, actual, expected);
2422
2423 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2424}
2425
2426/* partially received RX was aborted. clean up. */
2427static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2428{
2429 unsigned int rx_desc_ptr;
2430
8127d661
BH		 2431 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2432 "scattered RX aborted (dropping %u buffers)\n",
2433 rx_queue->scatter_n);
2434
2435 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2436
2437 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2438 0, EFX_RX_PKT_DISCARD);
2439
2440 rx_queue->removed_count += rx_queue->scatter_n;
2441 rx_queue->scatter_n = 0;
2442 rx_queue->scatter_len = 0;
2443 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2444}
2445
2446static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2447 const efx_qword_t *event)
2448{
2449 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2450 unsigned int n_descs, n_packets, i;
2451 struct efx_nic *efx = channel->efx;
2452 struct efx_rx_queue *rx_queue;
2453 bool rx_cont;
2454 u16 flags = 0;
2455
2456 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2457 return 0;
2458
2459 /* Basic packet information */
2460 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2461 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2462 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2463 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2464 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2465
48ce5634
BH		 2466 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2467 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2468 EFX_QWORD_FMT "\n",
2469 EFX_QWORD_VAL(*event));
8127d661
BH		 2470
2471 rx_queue = efx_channel_get_rx_queue(channel);
2472
2473 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2474 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2475
2476 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2477 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2478
2479 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 2480 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2481
8127d661
BH		 2482 /* detect rx abort */
2483 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2484 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2485 netdev_WARN(efx->net_dev,
2486 "invalid RX abort: scatter_n=%u event="
2487 EFX_QWORD_FMT "\n",
2488 rx_queue->scatter_n,
2489 EFX_QWORD_VAL(*event));
8127d661
BH		 2490 efx_ef10_handle_rx_abort(rx_queue);
2491 return 0;
2492 }
2493
92a04168
BH		 2494 /* Check that RX completion merging is valid, i.e.
2495 * the current firmware supports it and this is a
2496 * non-scattered packet.
2497 */
2498 if (!(nic_data->datapath_caps &
2499 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2500 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2501 efx_ef10_handle_rx_bad_lbits(
2502 rx_queue, next_ptr_lbits,
2503 (rx_queue->removed_count +
2504 rx_queue->scatter_n + 1) &
2505 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2506 return 0;
2507 }
2508
2509 /* Merged completion for multiple non-scattered packets */
2510 rx_queue->scatter_n = 1;
2511 rx_queue->scatter_len = 0;
2512 n_packets = n_descs;
2513 ++channel->n_rx_merge_events;
2514 channel->n_rx_merge_packets += n_packets;
2515 flags |= EFX_RX_PKT_PREFIX_LEN;
2516 } else {
2517 ++rx_queue->scatter_n;
2518 rx_queue->scatter_len += rx_bytes;
2519 if (rx_cont)
2520 return 0;
2521 n_packets = 1;
2522 }
2523
2524 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2525 flags |= EFX_RX_PKT_DISCARD;
2526
2527 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2528 channel->n_rx_ip_hdr_chksum_err += n_packets;
2529 } else if (unlikely(EFX_QWORD_FIELD(*event,
2530 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2531 channel->n_rx_tcp_udp_chksum_err += n_packets;
2532 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2533 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2534 flags |= EFX_RX_PKT_CSUMMED;
2535 }
2536
2537 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2538 flags |= EFX_RX_PKT_TCP;
2539
2540 channel->irq_mod_score += 2 * n_packets;
2541
2542 /* Handle received packet(s) */
2543 for (i = 0; i < n_packets; i++) {
2544 efx_rx_packet(rx_queue,
2545 rx_queue->removed_count & rx_queue->ptr_mask,
2546 rx_queue->scatter_n, rx_queue->scatter_len,
2547 flags);
2548 rx_queue->removed_count += rx_queue->scatter_n;
2549 }
2550
2551 rx_queue->scatter_n = 0;
2552 rx_queue->scatter_len = 0;
2553
2554 return n_packets;
2555}
2556
2557static int
2558efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2559{
2560 struct efx_nic *efx = channel->efx;
2561 struct efx_tx_queue *tx_queue;
2562 unsigned int tx_ev_desc_ptr;
2563 unsigned int tx_ev_q_label;
2564 int tx_descs = 0;
2565
2566 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2567 return 0;
2568
2569 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2570 return 0;
2571
2572 /* Transmit completion */
2573 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2574 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2575 tx_queue = efx_channel_get_tx_queue(channel,
2576 tx_ev_q_label % EFX_TXQ_TYPES);
2577 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2578 tx_queue->ptr_mask);
2579 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2580
2581 return tx_descs;
2582}
2583
2584static void
2585efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2586{
2587 struct efx_nic *efx = channel->efx;
2588 int subcode;
2589
2590 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2591
2592 switch (subcode) {
2593 case ESE_DZ_DRV_TIMER_EV:
2594 case ESE_DZ_DRV_WAKE_UP_EV:
2595 break;
2596 case ESE_DZ_DRV_START_UP_EV:
2597 /* event queue init complete. ok. */
2598 break;
2599 default:
2600 netif_err(efx, hw, efx->net_dev,
2601 "channel %d unknown driver event type %d"
2602 " (data " EFX_QWORD_FMT ")\n",
2603 channel->channel, subcode,
2604 EFX_QWORD_VAL(*event));
2605
2606 }
2607}
2608
2609static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2610 efx_qword_t *event)
2611{
2612 struct efx_nic *efx = channel->efx;
2613 u32 subcode;
2614
2615 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2616
2617 switch (subcode) {
2618 case EFX_EF10_TEST:
2619 channel->event_test_cpu = raw_smp_processor_id();
2620 break;
2621 case EFX_EF10_REFILL:
2622 /* The queue must be empty, so we won't receive any rx
2623 * events, so efx_process_channel() won't refill the
2624 * queue. Refill it here
2625 */
cce28794 2626 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 2627 break;
2628 default:
2629 netif_err(efx, hw, efx->net_dev,
2630 "channel %d unknown driver event type %u"
2631 " (data " EFX_QWORD_FMT ")\n",
2632 channel->channel, (unsigned) subcode,
2633 EFX_QWORD_VAL(*event));
2634 }
2635}
2636
2637static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2638{
2639 struct efx_nic *efx = channel->efx;
2640 efx_qword_t event, *p_event;
2641 unsigned int read_ptr;
2642 int ev_code;
2643 int tx_descs = 0;
2644 int spent = 0;
2645
75363a46
EB		 2646 if (quota <= 0)
2647 return spent;
2648
8127d661
BH		 2649 read_ptr = channel->eventq_read_ptr;
2650
2651 for (;;) {
2652 p_event = efx_event(channel, read_ptr);
2653 event = *p_event;
2654
2655 if (!efx_event_present(&event))
2656 break;
2657
2658 EFX_SET_QWORD(*p_event);
2659
2660 ++read_ptr;
2661
2662 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2663
2664 netif_vdbg(efx, drv, efx->net_dev,
2665 "processing event on %d " EFX_QWORD_FMT "\n",
2666 channel->channel, EFX_QWORD_VAL(event));
2667
2668 switch (ev_code) {
2669 case ESE_DZ_EV_CODE_MCDI_EV:
2670 efx_mcdi_process_event(channel, &event);
2671 break;
2672 case ESE_DZ_EV_CODE_RX_EV:
2673 spent += efx_ef10_handle_rx_event(channel, &event);
2674 if (spent >= quota) {
2675 /* XXX can we split a merged event to
2676 * avoid going over-quota?
2677 */
2678 spent = quota;
2679 goto out;
2680 }
2681 break;
2682 case ESE_DZ_EV_CODE_TX_EV:
2683 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2684 if (tx_descs > efx->txq_entries) {
2685 spent = quota;
2686 goto out;
2687 } else if (++spent == quota) {
2688 goto out;
2689 }
2690 break;
2691 case ESE_DZ_EV_CODE_DRIVER_EV:
2692 efx_ef10_handle_driver_event(channel, &event);
2693 if (++spent == quota)
2694 goto out;
2695 break;
2696 case EFX_EF10_DRVGEN_EV:
2697 efx_ef10_handle_driver_generated_event(channel, &event);
2698 break;
2699 default:
2700 netif_err(efx, hw, efx->net_dev,
2701 "channel %d unknown event type %d"
2702 " (data " EFX_QWORD_FMT ")\n",
2703 channel->channel, ev_code,
2704 EFX_QWORD_VAL(event));
2705 }
2706 }
2707
2708out:
2709 channel->eventq_read_ptr = read_ptr;
2710 return spent;
2711}
2712
2713static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2714{
2715 struct efx_nic *efx = channel->efx;
2716 efx_dword_t rptr;
2717
2718 if (EFX_EF10_WORKAROUND_35388(efx)) {
2719 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2720 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2721 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2722 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2723
2724 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2725 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2726 ERF_DD_EVQ_IND_RPTR,
2727 (channel->eventq_read_ptr &
2728 channel->eventq_mask) >>
2729 ERF_DD_EVQ_IND_RPTR_WIDTH);
2730 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2731 channel->channel);
2732 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2733 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2734 ERF_DD_EVQ_IND_RPTR,
2735 channel->eventq_read_ptr &
2736 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2737 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2738 channel->channel);
2739 } else {
2740 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2741 channel->eventq_read_ptr &
2742 channel->eventq_mask);
2743 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2744 }
2745}
2746
2747static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2748{
2749 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2750 struct efx_nic *efx = channel->efx;
2751 efx_qword_t event;
2752 int rc;
2753
2754 EFX_POPULATE_QWORD_2(event,
2755 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2756 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2757
2758 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2759
2760 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2761 * already swapped the data to little-endian order.
2762 */
2763 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2764 sizeof(efx_qword_t));
2765
2766 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2767 NULL, 0, NULL);
2768 if (rc != 0)
2769 goto fail;
2770
2771 return;
2772
2773fail:
2774 WARN_ON(true);
2775 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2776}
2777
2778void efx_ef10_handle_drain_event(struct efx_nic *efx)
2779{
2780 if (atomic_dec_and_test(&efx->active_queues))
2781 wake_up(&efx->flush_wq);
2782
2783 WARN_ON(atomic_read(&efx->active_queues) < 0);
2784}
2785
2786static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2787{
2788 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2789 struct efx_channel *channel;
2790 struct efx_tx_queue *tx_queue;
2791 struct efx_rx_queue *rx_queue;
2792 int pending;
2793
2794 /* If the MC has just rebooted, the TX/RX queues will have already been
2795 * torn down, but efx->active_queues needs to be set to zero.
2796 */
2797 if (nic_data->must_realloc_vis) {
2798 atomic_set(&efx->active_queues, 0);
2799 return 0;
2800 }
2801
2802 /* Do not attempt to write to the NIC during EEH recovery */
2803 if (efx->state != STATE_RECOVERY) {
2804 efx_for_each_channel(channel, efx) {
2805 efx_for_each_channel_rx_queue(rx_queue, channel)
2806 efx_ef10_rx_fini(rx_queue);
2807 efx_for_each_channel_tx_queue(tx_queue, channel)
2808 efx_ef10_tx_fini(tx_queue);
2809 }
2810
2811 wait_event_timeout(efx->flush_wq,
2812 atomic_read(&efx->active_queues) == 0,
2813 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2814 pending = atomic_read(&efx->active_queues);
2815 if (pending) {
2816 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2817 pending);
2818 return -ETIMEDOUT;
2819 }
2820 }
2821
2822 return 0;
2823}
2824
e283546c
EC		 2825static void efx_ef10_prepare_flr(struct efx_nic *efx)
2826{
2827 atomic_set(&efx->active_queues, 0);
2828}
2829
8127d661
BH		 2830static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2831 const struct efx_filter_spec *right)
2832{
2833 if ((left->match_flags ^ right->match_flags) |
2834 ((left->flags ^ right->flags) &
2835 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2836 return false;
2837
2838 return memcmp(&left->outer_vid, &right->outer_vid,
2839 sizeof(struct efx_filter_spec) -
2840 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2841}
2842
2843static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2844{
2845 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2846 return jhash2((const u32 *)&spec->outer_vid,
2847 (sizeof(struct efx_filter_spec) -
2848 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2849 0);
2850 /* XXX should we randomise the initval? */
2851}
2852
2853/* Decide whether a filter should be exclusive or else should allow
2854 * delivery to additional recipients. Currently we decide that
2855 * filters for specific local unicast MAC and IP addresses are
2856 * exclusive.
2857 */
2858static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2859{
2860 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2861 !is_multicast_ether_addr(spec->loc_mac))
2862 return true;
2863
2864 if ((spec->match_flags &
2865 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2866 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2867 if (spec->ether_type == htons(ETH_P_IP) &&
2868 !ipv4_is_multicast(spec->loc_host[0]))
2869 return true;
2870 if (spec->ether_type == htons(ETH_P_IPV6) &&
2871 ((const u8 *)spec->loc_host)[0] != 0xff)
2872 return true;
2873 }
2874
2875 return false;
2876}
2877
2878static struct efx_filter_spec *
2879efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2880 unsigned int filter_idx)
2881{
2882 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2883 ~EFX_EF10_FILTER_FLAGS);
2884}
2885
2886static unsigned int
2887efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2888 unsigned int filter_idx)
2889{
2890 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2891}
2892
2893static void
2894efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2895 unsigned int filter_idx,
2896 const struct efx_filter_spec *spec,
2897 unsigned int flags)
2898{
2899 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2900}
2901
2902static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2903 const struct efx_filter_spec *spec,
2904 efx_dword_t *inbuf, u64 handle,
2905 bool replacing)
2906{
2907 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2908
2909 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2910
2911 if (replacing) {
2912 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2913 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2914 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2915 } else {
2916 u32 match_fields = 0;
2917
2918 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2919 efx_ef10_filter_is_exclusive(spec) ?
2920 MC_CMD_FILTER_OP_IN_OP_INSERT :
2921 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2922
2923 /* Convert match flags and values. Unlike almost
2924 * everything else in MCDI, these fields are in
2925 * network byte order.
2926 */
2927 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2928 match_fields |=
2929 is_multicast_ether_addr(spec->loc_mac) ?
2930 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2931 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2932#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2933 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2934 match_fields |= \
2935 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2936 mcdi_field ## _LBN; \
2937 BUILD_BUG_ON( \
2938 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2939 sizeof(spec->gen_field)); \
2940 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2941 &spec->gen_field, sizeof(spec->gen_field)); \
2942 }
2943 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2944 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2945 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2946 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2947 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2948 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2949 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2950 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2951 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2952 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2953#undef COPY_FIELD
2954 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2955 match_fields);
2956 }
2957
45b2449e 2958 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2959 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2960 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2961 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2962 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 2963 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 2964 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2965 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 2966 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2967 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2968 0 : spec->dmaq_id);
8127d661
BH		 2969 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2970 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2971 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2972 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2973 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2974 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2975 spec->rss_context !=
2976 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2977 spec->rss_context : nic_data->rx_rss_context);
2978}
2979
2980static int efx_ef10_filter_push(struct efx_nic *efx,
2981 const struct efx_filter_spec *spec,
2982 u64 *handle, bool replacing)
2983{
2984 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2985 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2986 int rc;
2987
2988 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2989 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2990 outbuf, sizeof(outbuf), NULL);
2991 if (rc == 0)
2992 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 2993 if (rc == -ENOSPC)
2994 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 2995 return rc;
2996}
2997
2998static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2999 enum efx_filter_match_flags match_flags)
3000{
3001 unsigned int match_pri;
3002
3003 for (match_pri = 0;
3004 match_pri < table->rx_match_count;
3005 match_pri++)
3006 if (table->rx_match_flags[match_pri] == match_flags)
3007 return match_pri;
3008
3009 return -EPROTONOSUPPORT;
3010}
3011
3012static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3013 struct efx_filter_spec *spec,
3014 bool replace_equal)
3015{
3016 struct efx_ef10_filter_table *table = efx->filter_state;
3017 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3018 struct efx_filter_spec *saved_spec;
3019 unsigned int match_pri, hash;
3020 unsigned int priv_flags;
3021 bool replacing = false;
3022 int ins_index = -1;
3023 DEFINE_WAIT(wait);
3024 bool is_mc_recip;
3025 s32 rc;
3026
3027 /* For now, only support RX filters */
3028 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3029 EFX_FILTER_FLAG_RX)
3030 return -EINVAL;
3031
3032 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
3033 if (rc < 0)
3034 return rc;
3035 match_pri = rc;
3036
3037 hash = efx_ef10_filter_hash(spec);
3038 is_mc_recip = efx_filter_is_mc_recipient(spec);
3039 if (is_mc_recip)
3040 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3041
3042 /* Find any existing filters with the same match tuple or
3043 * else a free slot to insert at. If any of them are busy,
3044 * we have to wait and retry.
3045 */
3046 for (;;) {
3047 unsigned int depth = 1;
3048 unsigned int i;
3049
3050 spin_lock_bh(&efx->filter_lock);
3051
3052 for (;;) {
3053 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3054 saved_spec = efx_ef10_filter_entry_spec(table, i);
3055
3056 if (!saved_spec) {
3057 if (ins_index < 0)
3058 ins_index = i;
3059 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3060 if (table->entry[i].spec &
3061 EFX_EF10_FILTER_FLAG_BUSY)
3062 break;
3063 if (spec->priority < saved_spec->priority &&
7665d1ab 3064 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3065 rc = -EPERM;
3066 goto out_unlock;
3067 }
3068 if (!is_mc_recip) {
3069 /* This is the only one */
3070 if (spec->priority ==
3071 saved_spec->priority &&
3072 !replace_equal) {
3073 rc = -EEXIST;
3074 goto out_unlock;
3075 }
3076 ins_index = i;
3077 goto found;
3078 } else if (spec->priority >
3079 saved_spec->priority ||
3080 (spec->priority ==
3081 saved_spec->priority &&
3082 replace_equal)) {
3083 if (ins_index < 0)
3084 ins_index = i;
3085 else
3086 __set_bit(depth, mc_rem_map);
3087 }
3088 }
3089
3090 /* Once we reach the maximum search depth, use
3091 * the first suitable slot or return -EBUSY if
3092 * there was none
3093 */
3094 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3095 if (ins_index < 0) {
3096 rc = -EBUSY;
3097 goto out_unlock;
3098 }
3099 goto found;
3100 }
3101
3102 ++depth;
3103 }
3104
3105 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3106 spin_unlock_bh(&efx->filter_lock);
3107 schedule();
3108 }
3109
3110found:
3111 /* Create a software table entry if necessary, and mark it
3112 * busy. We might yet fail to insert, but any attempt to
3113 * insert a conflicting filter while we're waiting for the
3114 * firmware must find the busy entry.
3115 */
3116 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3117 if (saved_spec) {
7665d1ab
BH		 3118 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3119 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3120 /* Just make sure it won't be removed */
7665d1ab
BH		 3121 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3122 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3123 table->entry[ins_index].spec &=
b59e6ef8 3124 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3125 rc = ins_index;
3126 goto out_unlock;
3127 }
3128 replacing = true;
3129 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3130 } else {
3131 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3132 if (!saved_spec) {
3133 rc = -ENOMEM;
3134 goto out_unlock;
3135 }
3136 *saved_spec = *spec;
3137 priv_flags = 0;
3138 }
3139 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3140 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3141
3142 /* Mark lower-priority multicast recipients busy prior to removal */
3143 if (is_mc_recip) {
3144 unsigned int depth, i;
3145
3146 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3147 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3148 if (test_bit(depth, mc_rem_map))
3149 table->entry[i].spec |=
3150 EFX_EF10_FILTER_FLAG_BUSY;
3151 }
3152 }
3153
3154 spin_unlock_bh(&efx->filter_lock);
3155
3156 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3157 replacing);
3158
3159 /* Finalise the software table entry */
3160 spin_lock_bh(&efx->filter_lock);
3161 if (rc == 0) {
3162 if (replacing) {
3163 /* Update the fields that may differ */
7665d1ab
BH		 3164 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3165 saved_spec->flags |=
3166 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3167 saved_spec->priority = spec->priority;
7665d1ab 3168 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 3169 saved_spec->flags |= spec->flags;
3170 saved_spec->rss_context = spec->rss_context;
3171 saved_spec->dmaq_id = spec->dmaq_id;
3172 }
3173 } else if (!replacing) {
3174 kfree(saved_spec);
3175 saved_spec = NULL;
3176 }
3177 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3178
3179 /* Remove and finalise entries for lower-priority multicast
3180 * recipients
3181 */
3182 if (is_mc_recip) {
3183 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3184 unsigned int depth, i;
3185
3186 memset(inbuf, 0, sizeof(inbuf));
3187
3188 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3189 if (!test_bit(depth, mc_rem_map))
3190 continue;
3191
3192 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3193 saved_spec = efx_ef10_filter_entry_spec(table, i);
3194 priv_flags = efx_ef10_filter_entry_flags(table, i);
3195
3196 if (rc == 0) {
3197 spin_unlock_bh(&efx->filter_lock);
3198 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3199 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3200 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3201 table->entry[i].handle);
3202 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3203 inbuf, sizeof(inbuf),
3204 NULL, 0, NULL);
3205 spin_lock_bh(&efx->filter_lock);
3206 }
3207
3208 if (rc == 0) {
3209 kfree(saved_spec);
3210 saved_spec = NULL;
3211 priv_flags = 0;
3212 } else {
3213 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3214 }
3215 efx_ef10_filter_set_entry(table, i, saved_spec,
3216 priv_flags);
3217 }
3218 }
3219
3220 /* If successful, return the inserted filter ID */
3221 if (rc == 0)
3222 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3223
3224 wake_up_all(&table->waitq);
3225out_unlock:
3226 spin_unlock_bh(&efx->filter_lock);
3227 finish_wait(&table->waitq, &wait);
3228 return rc;
3229}
3230
9fd8095d 3231static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 3232{
3233 /* no need to do anything here on EF10 */
3234}
3235
3236/* Remove a filter.
b59e6ef8
BH		 3237 * If !by_index, remove by ID
3238 * If by_index, remove by index
8127d661
BH		 3239 * Filter ID may come from userland and must be range-checked.
3240 */
3241static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 3242 unsigned int priority_mask,
b59e6ef8 3243 u32 filter_id, bool by_index)
8127d661
BH		 3244{
3245 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3246 struct efx_ef10_filter_table *table = efx->filter_state;
3247 MCDI_DECLARE_BUF(inbuf,
3248 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3249 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3250 struct efx_filter_spec *spec;
3251 DEFINE_WAIT(wait);
3252 int rc;
3253
3254 /* Find the software table entry and mark it busy. Don't
3255 * remove it yet; any attempt to update while we're waiting
3256 * for the firmware must find the busy entry.
3257 */
3258 for (;;) {
3259 spin_lock_bh(&efx->filter_lock);
3260 if (!(table->entry[filter_idx].spec &
3261 EFX_EF10_FILTER_FLAG_BUSY))
3262 break;
3263 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3264 spin_unlock_bh(&efx->filter_lock);
3265 schedule();
3266 }
7665d1ab 3267
8127d661 3268 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 3269 if (!spec ||
b59e6ef8 3270 (!by_index &&
8127d661
BH		 3271 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3272 filter_id / HUNT_FILTER_TBL_ROWS)) {
3273 rc = -ENOENT;
3274 goto out_unlock;
3275 }
7665d1ab
BH		 3276
3277 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 3278 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 3279 /* Just remove flags */
3280 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 3281 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 3282 rc = 0;
3283 goto out_unlock;
3284 }
3285
fbd79120 3286 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 3287 rc = -ENOENT;
3288 goto out_unlock;
3289 }
3290
8127d661
BH		 3291 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3292 spin_unlock_bh(&efx->filter_lock);
3293
7665d1ab 3294 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 3295 /* Reset to an automatic filter */
8127d661
BH		 3296
3297 struct efx_filter_spec new_spec = *spec;
3298
7665d1ab 3299 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 3300 new_spec.flags = (EFX_FILTER_FLAG_RX |
7665d1ab 3301 EFX_FILTER_FLAG_RX_RSS);
8127d661
BH		 3302 new_spec.dmaq_id = 0;
3303 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3304 rc = efx_ef10_filter_push(efx, &new_spec,
3305 &table->entry[filter_idx].handle,
3306 true);
3307
3308 spin_lock_bh(&efx->filter_lock);
3309 if (rc == 0)
3310 *spec = new_spec;
3311 } else {
3312 /* Really remove the filter */
3313
3314 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3315 efx_ef10_filter_is_exclusive(spec) ?
3316 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3317 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3318 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3319 table->entry[filter_idx].handle);
3320 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3321 inbuf, sizeof(inbuf), NULL, 0, NULL);
3322
3323 spin_lock_bh(&efx->filter_lock);
3324 if (rc == 0) {
3325 kfree(spec);
3326 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3327 }
3328 }
7665d1ab 3329
8127d661
BH		 3330 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3331 wake_up_all(&table->waitq);
3332out_unlock:
3333 spin_unlock_bh(&efx->filter_lock);
3334 finish_wait(&table->waitq, &wait);
3335 return rc;
3336}
3337
3338static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3339 enum efx_filter_priority priority,
3340 u32 filter_id)
3341{
fbd79120
BH		 3342 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3343 filter_id, false);
8127d661
BH		 3344}
3345
12fb0da4
EC		 3346static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3347{
3348 return filter_id % HUNT_FILTER_TBL_ROWS;
3349}
3350
3351static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3352 enum efx_filter_priority priority,
3353 u32 filter_id)
3354{
3355 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3356 filter_id, true);
3357}
3358
8127d661
BH		 3359static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3360 enum efx_filter_priority priority,
3361 u32 filter_id, struct efx_filter_spec *spec)
3362{
3363 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3364 struct efx_ef10_filter_table *table = efx->filter_state;
3365 const struct efx_filter_spec *saved_spec;
3366 int rc;
3367
3368 spin_lock_bh(&efx->filter_lock);
3369 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3370 if (saved_spec && saved_spec->priority == priority &&
3371 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3372 filter_id / HUNT_FILTER_TBL_ROWS) {
3373 *spec = *saved_spec;
3374 rc = 0;
3375 } else {
3376 rc = -ENOENT;
3377 }
3378 spin_unlock_bh(&efx->filter_lock);
3379 return rc;
3380}
3381
fbd79120 3382static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 3383 enum efx_filter_priority priority)
3384{
fbd79120
BH		 3385 unsigned int priority_mask;
3386 unsigned int i;
3387 int rc;
3388
3389 priority_mask = (((1U << (priority + 1)) - 1) &
3390 ~(1U << EFX_FILTER_PRI_AUTO));
3391
3392 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3393 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3394 i, true);
3395 if (rc && rc != -ENOENT)
3396 return rc;
3397 }
3398
3399 return 0;
8127d661
BH		 3400}
3401
3402static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3403 enum efx_filter_priority priority)
3404{
3405 struct efx_ef10_filter_table *table = efx->filter_state;
3406 unsigned int filter_idx;
3407 s32 count = 0;
3408
3409 spin_lock_bh(&efx->filter_lock);
3410 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3411 if (table->entry[filter_idx].spec &&
3412 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3413 priority)
3414 ++count;
3415 }
3416 spin_unlock_bh(&efx->filter_lock);
3417 return count;
3418}
3419
3420static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3421{
3422 struct efx_ef10_filter_table *table = efx->filter_state;
3423
3424 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3425}
3426
3427static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3428 enum efx_filter_priority priority,
3429 u32 *buf, u32 size)
3430{
3431 struct efx_ef10_filter_table *table = efx->filter_state;
3432 struct efx_filter_spec *spec;
3433 unsigned int filter_idx;
3434 s32 count = 0;
3435
3436 spin_lock_bh(&efx->filter_lock);
3437 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3438 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3439 if (spec && spec->priority == priority) {
3440 if (count == size) {
3441 count = -EMSGSIZE;
3442 break;
3443 }
3444 buf[count++] = (efx_ef10_filter_rx_match_pri(
3445 table, spec->match_flags) *
3446 HUNT_FILTER_TBL_ROWS +
3447 filter_idx);
3448 }
3449 }
3450 spin_unlock_bh(&efx->filter_lock);
3451 return count;
3452}
3453
3454#ifdef CONFIG_RFS_ACCEL
3455
3456static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3457
3458static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3459 struct efx_filter_spec *spec)
3460{
3461 struct efx_ef10_filter_table *table = efx->filter_state;
3462 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3463 struct efx_filter_spec *saved_spec;
3464 unsigned int hash, i, depth = 1;
3465 bool replacing = false;
3466 int ins_index = -1;
3467 u64 cookie;
3468 s32 rc;
3469
3470 /* Must be an RX filter without RSS and not for a multicast
3471 * destination address (RFS only works for connected sockets).
3472 * These restrictions allow us to pass only a tiny amount of
3473 * data through to the completion function.
3474 */
3475 EFX_WARN_ON_PARANOID(spec->flags !=
3476 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3477 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3478 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3479
3480 hash = efx_ef10_filter_hash(spec);
3481
3482 spin_lock_bh(&efx->filter_lock);
3483
3484 /* Find any existing filter with the same match tuple or else
3485 * a free slot to insert at. If an existing filter is busy,
3486 * we have to give up.
3487 */
3488 for (;;) {
3489 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3490 saved_spec = efx_ef10_filter_entry_spec(table, i);
3491
3492 if (!saved_spec) {
3493 if (ins_index < 0)
3494 ins_index = i;
3495 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3496 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3497 rc = -EBUSY;
3498 goto fail_unlock;
3499 }
8127d661
BH		 3500 if (spec->priority < saved_spec->priority) {
3501 rc = -EPERM;
3502 goto fail_unlock;
3503 }
3504 ins_index = i;
3505 break;
3506 }
3507
3508 /* Once we reach the maximum search depth, use the
3509 * first suitable slot or return -EBUSY if there was
3510 * none
3511 */
3512 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3513 if (ins_index < 0) {
3514 rc = -EBUSY;
3515 goto fail_unlock;
3516 }
3517 break;
3518 }
3519
3520 ++depth;
3521 }
3522
3523 /* Create a software table entry if necessary, and mark it
3524 * busy. We might yet fail to insert, but any attempt to
3525 * insert a conflicting filter while we're waiting for the
3526 * firmware must find the busy entry.
3527 */
3528 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3529 if (saved_spec) {
3530 replacing = true;
3531 } else {
3532 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3533 if (!saved_spec) {
3534 rc = -ENOMEM;
3535 goto fail_unlock;
3536 }
3537 *saved_spec = *spec;
3538 }
3539 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3540 EFX_EF10_FILTER_FLAG_BUSY);
3541
3542 spin_unlock_bh(&efx->filter_lock);
3543
3544 /* Pack up the variables needed on completion */
3545 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3546
3547 efx_ef10_filter_push_prep(efx, spec, inbuf,
3548 table->entry[ins_index].handle, replacing);
3549 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3550 MC_CMD_FILTER_OP_OUT_LEN,
3551 efx_ef10_filter_rfs_insert_complete, cookie);
3552
3553 return ins_index;
3554
3555fail_unlock:
3556 spin_unlock_bh(&efx->filter_lock);
3557 return rc;
3558}
3559
3560static void
3561efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3562 int rc, efx_dword_t *outbuf,
3563 size_t outlen_actual)
3564{
3565 struct efx_ef10_filter_table *table = efx->filter_state;
3566 unsigned int ins_index, dmaq_id;
3567 struct efx_filter_spec *spec;
3568 bool replacing;
3569
3570 /* Unpack the cookie */
3571 replacing = cookie >> 31;
3572 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3573 dmaq_id = cookie & 0xffff;
3574
3575 spin_lock_bh(&efx->filter_lock);
3576 spec = efx_ef10_filter_entry_spec(table, ins_index);
3577 if (rc == 0) {
3578 table->entry[ins_index].handle =
3579 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3580 if (replacing)
3581 spec->dmaq_id = dmaq_id;
3582 } else if (!replacing) {
3583 kfree(spec);
3584 spec = NULL;
3585 }
3586 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3587 spin_unlock_bh(&efx->filter_lock);
3588
3589 wake_up_all(&table->waitq);
3590}
3591
3592static void
3593efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3594 unsigned long filter_idx,
3595 int rc, efx_dword_t *outbuf,
3596 size_t outlen_actual);
3597
3598static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3599 unsigned int filter_idx)
3600{
3601 struct efx_ef10_filter_table *table = efx->filter_state;
3602 struct efx_filter_spec *spec =
3603 efx_ef10_filter_entry_spec(table, filter_idx);
3604 MCDI_DECLARE_BUF(inbuf,
3605 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3606 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3607
3608 if (!spec ||
3609 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3610 spec->priority != EFX_FILTER_PRI_HINT ||
3611 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3612 flow_id, filter_idx))
3613 return false;
3614
3615 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3616 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3617 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3618 table->entry[filter_idx].handle);
3619 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3620 efx_ef10_filter_rfs_expire_complete, filter_idx))
3621 return false;
3622
3623 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3624 return true;
3625}
3626
3627static void
3628efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3629 unsigned long filter_idx,
3630 int rc, efx_dword_t *outbuf,
3631 size_t outlen_actual)
3632{
3633 struct efx_ef10_filter_table *table = efx->filter_state;
3634 struct efx_filter_spec *spec =
3635 efx_ef10_filter_entry_spec(table, filter_idx);
3636
3637 spin_lock_bh(&efx->filter_lock);
3638 if (rc == 0) {
3639 kfree(spec);
3640 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3641 }
3642 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3643 wake_up_all(&table->waitq);
3644 spin_unlock_bh(&efx->filter_lock);
3645}
3646
3647#endif /* CONFIG_RFS_ACCEL */
3648
3649static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3650{
3651 int match_flags = 0;
3652
3653#define MAP_FLAG(gen_flag, mcdi_field) { \
3654 u32 old_mcdi_flags = mcdi_flags; \
3655 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3656 mcdi_field ## _LBN); \
3657 if (mcdi_flags != old_mcdi_flags) \
3658 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3659 }
3660 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3661 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3662 MAP_FLAG(REM_HOST, SRC_IP);
3663 MAP_FLAG(LOC_HOST, DST_IP);
3664 MAP_FLAG(REM_MAC, SRC_MAC);
3665 MAP_FLAG(REM_PORT, SRC_PORT);
3666 MAP_FLAG(LOC_MAC, DST_MAC);
3667 MAP_FLAG(LOC_PORT, DST_PORT);
3668 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3669 MAP_FLAG(INNER_VID, INNER_VLAN);
3670 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3671 MAP_FLAG(IP_PROTO, IP_PROTO);
3672#undef MAP_FLAG
3673
3674 /* Did we map them all? */
3675 if (mcdi_flags)
3676 return -EINVAL;
3677
3678 return match_flags;
3679}
3680
3681static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3682{
3683 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3684 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3685 unsigned int pd_match_pri, pd_match_count;
3686 struct efx_ef10_filter_table *table;
3687 size_t outlen;
3688 int rc;
3689
3690 table = kzalloc(sizeof(*table), GFP_KERNEL);
3691 if (!table)
3692 return -ENOMEM;
3693
3694 /* Find out which RX filter types are supported, and their priorities */
3695 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3696 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3697 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3698 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3699 &outlen);
3700 if (rc)
3701 goto fail;
3702 pd_match_count = MCDI_VAR_ARRAY_LEN(
3703 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3704 table->rx_match_count = 0;
3705
3706 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3707 u32 mcdi_flags =
3708 MCDI_ARRAY_DWORD(
3709 outbuf,
3710 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3711 pd_match_pri);
3712 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3713 if (rc < 0) {
3714 netif_dbg(efx, probe, efx->net_dev,
3715 "%s: fw flags %#x pri %u not supported in driver\n",
3716 __func__, mcdi_flags, pd_match_pri);
3717 } else {
3718 netif_dbg(efx, probe, efx->net_dev,
3719 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3720 __func__, mcdi_flags, pd_match_pri,
3721 rc, table->rx_match_count);
3722 table->rx_match_flags[table->rx_match_count++] = rc;
3723 }
3724 }
3725
3726 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3727 if (!table->entry) {
3728 rc = -ENOMEM;
3729 goto fail;
3730 }
3731
12fb0da4
EC		 3732 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3733 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3734 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3735
8127d661
BH		 3736 efx->filter_state = table;
3737 init_waitqueue_head(&table->waitq);
3738 return 0;
3739
3740fail:
3741 kfree(table);
3742 return rc;
3743}
3744
0d322413
EC		 3745/* Caller must hold efx->filter_sem for read if race against
3746 * efx_ef10_filter_table_remove() is possible
3747 */
8127d661
BH		 3748static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3749{
3750 struct efx_ef10_filter_table *table = efx->filter_state;
3751 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3752 struct efx_filter_spec *spec;
3753 unsigned int filter_idx;
3754 bool failed = false;
3755 int rc;
3756
0d322413
EC		 3757 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3758
8127d661
BH		 3759 if (!nic_data->must_restore_filters)
3760 return;
3761
0d322413
EC		 3762 if (!table)
3763 return;
3764
8127d661
BH		 3765 spin_lock_bh(&efx->filter_lock);
3766
3767 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3768 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3769 if (!spec)
3770 continue;
3771
3772 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3773 spin_unlock_bh(&efx->filter_lock);
3774
3775 rc = efx_ef10_filter_push(efx, spec,
3776 &table->entry[filter_idx].handle,
3777 false);
3778 if (rc)
3779 failed = true;
3780
3781 spin_lock_bh(&efx->filter_lock);
3782 if (rc) {
3783 kfree(spec);
3784 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3785 } else {
3786 table->entry[filter_idx].spec &=
3787 ~EFX_EF10_FILTER_FLAG_BUSY;
3788 }
3789 }
3790
3791 spin_unlock_bh(&efx->filter_lock);
3792
3793 if (failed)
3794 netif_err(efx, hw, efx->net_dev,
3795 "unable to restore all filters\n");
3796 else
3797 nic_data->must_restore_filters = false;
3798}
3799
0d322413 3800/* Caller must hold efx->filter_sem for write */
8127d661
BH		 3801static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3802{
3803 struct efx_ef10_filter_table *table = efx->filter_state;
3804 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3805 struct efx_filter_spec *spec;
3806 unsigned int filter_idx;
3807 int rc;
3808
0d322413
EC		 3809 efx->filter_state = NULL;
3810 if (!table)
3811 return;
3812
8127d661
BH		 3813 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3814 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3815 if (!spec)
3816 continue;
3817
3818 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3819 efx_ef10_filter_is_exclusive(spec) ?
3820 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3821 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3822 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3823 table->entry[filter_idx].handle);
3824 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3825 NULL, 0, NULL);
48ce5634
BH		 3826 if (rc)
3827 netdev_WARN(efx->net_dev,
3828 "filter_idx=%#x handle=%#llx\n",
3829 filter_idx,
3830 table->entry[filter_idx].handle);
8127d661
BH		 3831 kfree(spec);
3832 }
3833
3834 vfree(table->entry);
3835 kfree(table);
3836}
3837
12fb0da4
EC		 3838#define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3839 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3840 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3841 WARN_ON(!table->entry[filter_idx].spec); \
3842 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \
3843 }
822b96f8 3844static void efx_ef10_filter_mark_old(struct efx_nic *efx)
8127d661
BH		 3845{
3846 struct efx_ef10_filter_table *table = efx->filter_state;
822b96f8 3847 unsigned int filter_idx, i;
8127d661 3848
0d322413
EC		 3849 if (!table)
3850 return;
3851
8127d661
BH		 3852 /* Mark old filters that may need to be removed */
3853 spin_lock_bh(&efx->filter_lock);
12fb0da4
EC		 3854 for (i = 0; i < table->dev_uc_count; i++)
3855 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3856 for (i = 0; i < table->dev_mc_count; i++)
3857 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3858 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3859 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3860 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
8127d661 3861 spin_unlock_bh(&efx->filter_lock);
822b96f8 3862}
12fb0da4 3863#undef EFX_EF10_FILTER_DO_MARK_OLD
822b96f8
DP		 3864
3865static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3866{
3867 struct efx_ef10_filter_table *table = efx->filter_state;
3868 struct net_device *net_dev = efx->net_dev;
3869 struct netdev_hw_addr *uc;
12fb0da4 3870 int addr_count;
822b96f8 3871 unsigned int i;
8127d661 3872
12fb0da4
EC		 3873 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3874 addr_count = netdev_uc_count(net_dev);
3875 if (net_dev->flags & IFF_PROMISC)
822b96f8 3876 *promisc = true;
12fb0da4 3877 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 3878 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3879 i = 1;
3880 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4
EC		 3881 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3882 *promisc = true;
3883 break;
3884 }
822b96f8 3885 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
12fb0da4 3886 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
822b96f8
DP		 3887 i++;
3888 }
3889}
3890
3891static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3892{
3893 struct efx_ef10_filter_table *table = efx->filter_state;
3894 struct net_device *net_dev = efx->net_dev;
3895 struct netdev_hw_addr *mc;
ab8b1f7c 3896 unsigned int i, addr_count;
822b96f8 3897
12fb0da4
EC		 3898 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3899 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
ab8b1f7c 3900 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
822b96f8 3901 *promisc = true;
ab8b1f7c 3902
12fb0da4
EC		 3903 addr_count = netdev_mc_count(net_dev);
3904 i = 0;
ab8b1f7c 3905 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4
EC		 3906 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3907 *promisc = true;
3908 break;
3909 }
ab8b1f7c 3910 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
12fb0da4 3911 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
ab8b1f7c 3912 i++;
8127d661 3913 }
12fb0da4
EC		 3914
3915 table->dev_mc_count = i;
822b96f8 3916}
8127d661 3917
12fb0da4
EC		 3918static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3919 bool multicast, bool rollback)
822b96f8
DP		 3920{
3921 struct efx_ef10_filter_table *table = efx->filter_state;
3922 struct efx_ef10_dev_addr *addr_list;
3923 struct efx_filter_spec spec;
12fb0da4
EC		 3924 u8 baddr[ETH_ALEN];
3925 unsigned int i, j;
3926 int addr_count;
822b96f8
DP		 3927 int rc;
3928
3929 if (multicast) {
3930 addr_list = table->dev_mc_list;
12fb0da4 3931 addr_count = table->dev_mc_count;
822b96f8
DP		 3932 } else {
3933 addr_list = table->dev_uc_list;
12fb0da4 3934 addr_count = table->dev_uc_count;
8127d661
BH		 3935 }
3936
822b96f8 3937 /* Insert/renew filters */
12fb0da4 3938 for (i = 0; i < addr_count; i++) {
b6f568e2
JC		 3939 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3940 EFX_FILTER_FLAG_RX_RSS,
3941 0);
3942 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
822b96f8 3943 addr_list[i].addr);
b6f568e2
JC		 3944 rc = efx_ef10_filter_insert(efx, &spec, true);
3945 if (rc < 0) {
12fb0da4
EC		 3946 if (rollback) {
3947 netif_info(efx, drv, efx->net_dev,
3948 "efx_ef10_filter_insert failed rc=%d\n",
3949 rc);
3950 /* Fall back to promiscuous */
3951 for (j = 0; j < i; j++) {
3952 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3953 continue;
3954 efx_ef10_filter_remove_unsafe(
3955 efx, EFX_FILTER_PRI_AUTO,
3956 addr_list[j].id);
3957 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3958 }
3959 return rc;
3960 } else {
3961 /* mark as not inserted, and carry on */
3962 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 3963 }
8127d661 3964 }
12fb0da4 3965 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 3966 }
822b96f8 3967
12fb0da4
EC		 3968 if (multicast && rollback) {
3969 /* Also need an Ethernet broadcast filter */
7665d1ab
BH		 3970 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3971 EFX_FILTER_FLAG_RX_RSS,
8127d661 3972 0);
12fb0da4
EC		 3973 eth_broadcast_addr(baddr);
3974 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
8127d661 3975 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 3976 if (rc < 0) {
822b96f8 3977 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 3978 "Broadcast filter insert failed rc=%d\n", rc);
3979 /* Fall back to promiscuous */
3980 for (j = 0; j < i; j++) {
3981 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3982 continue;
3983 efx_ef10_filter_remove_unsafe(
3984 efx, EFX_FILTER_PRI_AUTO,
3985 addr_list[j].id);
3986 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3987 }
3988 return rc;
3989 } else {
3990 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3991 }
8127d661 3992 }
12fb0da4
EC		 3993
3994 return 0;
3995}
3996
3997static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
3998 bool rollback)
3999{
4000 struct efx_ef10_filter_table *table = efx->filter_state;
4001 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4002 struct efx_filter_spec spec;
4003 u8 baddr[ETH_ALEN];
4004 int rc;
4005
4006 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4007 EFX_FILTER_FLAG_RX_RSS,
4008 0);
4009
4010 if (multicast)
4011 efx_filter_set_mc_def(&spec);
4012 else
4013 efx_filter_set_uc_def(&spec);
4014
4015 rc = efx_ef10_filter_insert(efx, &spec, true);
4016 if (rc < 0) {
4017 netif_warn(efx, drv, efx->net_dev,
4018 "%scast mismatch filter insert failed rc=%d\n",
4019 multicast ? "Multi" : "Uni", rc);
4020 } else if (multicast) {
4021 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4022 if (!nic_data->workaround_26807) {
4023 /* Also need an Ethernet broadcast filter */
4024 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4025 EFX_FILTER_FLAG_RX_RSS,
4026 0);
4027 eth_broadcast_addr(baddr);
4028 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
4029 baddr);
4030 rc = efx_ef10_filter_insert(efx, &spec, true);
4031 if (rc < 0) {
4032 netif_warn(efx, drv, efx->net_dev,
4033 "Broadcast filter insert failed rc=%d\n",
4034 rc);
4035 if (rollback) {
4036 /* Roll back the mc_def filter */
4037 efx_ef10_filter_remove_unsafe(
4038 efx, EFX_FILTER_PRI_AUTO,
4039 table->mcdef_id);
4040 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
4041 return rc;
4042 }
4043 } else {
4044 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4045 }
4046 }
4047 rc = 0;
4048 } else {
4049 table->ucdef_id = rc;
4050 rc = 0;
4051 }
4052 return rc;
822b96f8
DP		 4053}
4054
4055/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4056 * flag or removes these filters, we don't need to hold the filter_lock while
4057 * scanning for these filters.
4058 */
4059static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4060{
4061 struct efx_ef10_filter_table *table = efx->filter_state;
4062 bool remove_failed = false;
4063 int i;
8127d661 4064
8127d661
BH		 4065 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4066 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 4067 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
7665d1ab 4068 if (efx_ef10_filter_remove_internal(
fbd79120
BH		 4069 efx, 1U << EFX_FILTER_PRI_AUTO,
4070 i, true) < 0)
8127d661
BH		 4071 remove_failed = true;
4072 }
4073 }
4074 WARN_ON(remove_failed);
4075}
4076
7a186f47
DP		 4077static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4078{
4079 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4080 u8 mac_old[ETH_ALEN];
4081 int rc, rc2;
4082
4083 /* Only reconfigure a PF-created vport */
4084 if (is_zero_ether_addr(nic_data->vport_mac))
4085 return 0;
4086
4087 efx_device_detach_sync(efx);
4088 efx_net_stop(efx->net_dev);
4089 down_write(&efx->filter_sem);
4090 efx_ef10_filter_table_remove(efx);
4091 up_write(&efx->filter_sem);
4092
4093 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4094 if (rc)
4095 goto restore_filters;
4096
4097 ether_addr_copy(mac_old, nic_data->vport_mac);
4098 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4099 nic_data->vport_mac);
4100 if (rc)
4101 goto restore_vadaptor;
4102
4103 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4104 efx->net_dev->dev_addr);
4105 if (!rc) {
4106 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4107 } else {
4108 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4109 if (rc2) {
4110 /* Failed to add original MAC, so clear vport_mac */
4111 eth_zero_addr(nic_data->vport_mac);
4112 goto reset_nic;
4113 }
4114 }
4115
4116restore_vadaptor:
4117 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4118 if (rc2)
4119 goto reset_nic;
4120restore_filters:
4121 down_write(&efx->filter_sem);
4122 rc2 = efx_ef10_filter_table_probe(efx);
4123 up_write(&efx->filter_sem);
4124 if (rc2)
4125 goto reset_nic;
4126
4127 rc2 = efx_net_open(efx->net_dev);
4128 if (rc2)
4129 goto reset_nic;
4130
4131 netif_device_attach(efx->net_dev);
4132
4133 return rc;
4134
4135reset_nic:
4136 netif_err(efx, drv, efx->net_dev,
4137 "Failed to restore when changing MAC address - scheduling reset\n");
4138 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4139
4140 return rc ? rc : rc2;
4141}
4142
822b96f8
DP		 4143/* Caller must hold efx->filter_sem for read if race against
4144 * efx_ef10_filter_table_remove() is possible
4145 */
4146static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4147{
4148 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 4149 struct efx_ef10_nic_data *nic_data = efx->nic_data;
822b96f8
DP		 4150 struct net_device *net_dev = efx->net_dev;
4151 bool uc_promisc = false, mc_promisc = false;
4152
4153 if (!efx_dev_registered(efx))
4154 return;
4155
4156 if (!table)
4157 return;
4158
4159 efx_ef10_filter_mark_old(efx);
4160
4161 /* Copy/convert the address lists; add the primary station
4162 * address and broadcast address
4163 */
4164 netif_addr_lock_bh(net_dev);
4165 efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4166 efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4167 netif_addr_unlock_bh(net_dev);
4168
12fb0da4
EC		 4169 /* Insert/renew unicast filters */
4170 if (uc_promisc) {
4171 efx_ef10_filter_insert_def(efx, false, false);
4172 efx_ef10_filter_insert_addr_list(efx, false, false);
4173 } else {
4174 /* If any of the filters failed to insert, fall back to
4175 * promiscuous mode - add in the uc_def filter. But keep
4176 * our individual unicast filters.
4177 */
4178 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4179 efx_ef10_filter_insert_def(efx, false, false);
4180 }
ab8b1f7c 4181
12fb0da4 4182 /* Insert/renew multicast filters */
ab8b1f7c
DP		 4183 /* If changing promiscuous state with cascaded multicast filters, remove
4184 * old filters first, so that packets are dropped rather than duplicated
4185 */
4186 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4187 efx_ef10_filter_remove_old(efx);
12fb0da4
EC		 4188 if (mc_promisc) {
4189 if (nic_data->workaround_26807) {
4190 /* If we failed to insert promiscuous filters, rollback
4191 * and fall back to individual multicast filters
4192 */
4193 if (efx_ef10_filter_insert_def(efx, true, true)) {
4194 /* Changing promisc state, so remove old filters */
4195 efx_ef10_filter_remove_old(efx);
4196 efx_ef10_filter_insert_addr_list(efx, true, false);
4197 }
4198 } else {
4199 /* If we failed to insert promiscuous filters, don't
4200 * rollback. Regardless, also insert the mc_list
4201 */
4202 efx_ef10_filter_insert_def(efx, true, false);
4203 efx_ef10_filter_insert_addr_list(efx, true, false);
4204 }
4205 } else {
4206 /* If any filters failed to insert, rollback and fall back to
4207 * promiscuous mode - mc_def filter and maybe broadcast. If
4208 * that fails, roll back again and insert as many of our
4209 * individual multicast filters as we can.
4210 */
4211 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4212 /* Changing promisc state, so remove old filters */
4213 if (nic_data->workaround_26807)
4214 efx_ef10_filter_remove_old(efx);
4215 if (efx_ef10_filter_insert_def(efx, true, true))
4216 efx_ef10_filter_insert_addr_list(efx, true, false);
4217 }
4218 }
822b96f8
DP		 4219
4220 efx_ef10_filter_remove_old(efx);
ab8b1f7c 4221 efx->mc_promisc = mc_promisc;
822b96f8
DP		 4222}
4223
910c8789
SS		 4224static int efx_ef10_set_mac_address(struct efx_nic *efx)
4225{
4226 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4227 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4228 bool was_enabled = efx->port_enabled;
4229 int rc;
4230
4231 efx_device_detach_sync(efx);
4232 efx_net_stop(efx->net_dev);
4233 down_write(&efx->filter_sem);
4234 efx_ef10_filter_table_remove(efx);
4235
4236 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4237 efx->net_dev->dev_addr);
4238 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4239 nic_data->vport_id);
535a6177
DP		 4240 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4241 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 4242
4243 efx_ef10_filter_table_probe(efx);
4244 up_write(&efx->filter_sem);
4245 if (was_enabled)
4246 efx_net_open(efx->net_dev);
4247 netif_device_attach(efx->net_dev);
4248
9e9f665a
DP		 4249#ifdef CONFIG_SFC_SRIOV
4250 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 4251 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4252
9e9f665a
DP		 4253 if (rc == -EPERM) {
4254 struct efx_nic *efx_pf;
910c8789 4255
9e9f665a
DP		 4256 /* Switch to PF and change MAC address on vport */
4257 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 4258
9e9f665a
DP		 4259 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4260 nic_data->vf_index,
4261 efx->net_dev->dev_addr);
4262 } else if (!rc) {
910c8789
SS		 4263 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4264 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4265 unsigned int i;
4266
9e9f665a
DP		 4267 /* MAC address successfully changed by VF (with MAC
4268 * spoofing) so update the parent PF if possible.
4269 */
910c8789
SS		 4270 for (i = 0; i < efx_pf->vf_count; ++i) {
4271 struct ef10_vf *vf = nic_data->vf + i;
4272
4273 if (vf->efx == efx) {
4274 ether_addr_copy(vf->mac,
4275 efx->net_dev->dev_addr);
4276 return 0;
4277 }
4278 }
4279 }
9e9f665a 4280 } else
910c8789 4281#endif
9e9f665a
DP		 4282 if (rc == -EPERM) {
4283 netif_err(efx, drv, efx->net_dev,
4284 "Cannot change MAC address; use sfboot to enable"
4285 " mac-spoofing on this interface\n");
7a186f47
DP		 4286 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4287 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4288 * fall-back to the method of changing the MAC address on the
4289 * vport. This only applies to PFs because such versions of
4290 * MCFW do not support VFs.
4291 */
4292 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 4293 } else {
4294 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4295 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 4296 }
4297
910c8789
SS		 4298 return rc;
4299}
4300
8127d661
BH		 4301static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4302{
4303 efx_ef10_filter_sync_rx_mode(efx);
4304
4305 return efx_mcdi_set_mac(efx);
4306}
4307
862f894c
SS		 4308static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4309{
4310 efx_ef10_filter_sync_rx_mode(efx);
4311
4312 return 0;
4313}
4314
74cd60a4
JC		 4315static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4316{
4317 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4318
4319 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4320 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4321 NULL, 0, NULL);
4322}
4323
4324/* MC BISTs follow a different poll mechanism to phy BISTs.
4325 * The BIST is done in the poll handler on the MC, and the MCDI command
4326 * will block until the BIST is done.
4327 */
4328static int efx_ef10_poll_bist(struct efx_nic *efx)
4329{
4330 int rc;
4331 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4332 size_t outlen;
4333 u32 result;
4334
4335 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4336 outbuf, sizeof(outbuf), &outlen);
4337 if (rc != 0)
4338 return rc;
4339
4340 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4341 return -EIO;
4342
4343 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4344 switch (result) {
4345 case MC_CMD_POLL_BIST_PASSED:
4346 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4347 return 0;
4348 case MC_CMD_POLL_BIST_TIMEOUT:
4349 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4350 return -EIO;
4351 case MC_CMD_POLL_BIST_FAILED:
4352 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4353 return -EIO;
4354 default:
4355 netif_err(efx, hw, efx->net_dev,
4356 "BIST returned unknown result %u", result);
4357 return -EIO;
4358 }
4359}
4360
4361static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4362{
4363 int rc;
4364
4365 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4366
4367 rc = efx_ef10_start_bist(efx, bist_type);
4368 if (rc != 0)
4369 return rc;
4370
4371 return efx_ef10_poll_bist(efx);
4372}
4373
4374static int
4375efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4376{
4377 int rc, rc2;
4378
4379 efx_reset_down(efx, RESET_TYPE_WORLD);
4380
4381 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4382 NULL, 0, NULL, 0, NULL);
4383 if (rc != 0)
4384 goto out;
4385
4386 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4387 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4388
4389 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4390
4391out:
27324820
DP		 4392 if (rc == -EPERM)
4393 rc = 0;
74cd60a4
JC		 4394 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4395 return rc ? rc : rc2;
4396}
4397
8127d661
BH		 4398#ifdef CONFIG_SFC_MTD
4399
4400struct efx_ef10_nvram_type_info {
4401 u16 type, type_mask;
4402 u8 port;
4403 const char *name;
4404};
4405
4406static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4407 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4408 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4409 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4410 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4411 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4412 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4413 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4414 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4415 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 4416 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 4417 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4418};
4419
4420static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4421 struct efx_mcdi_mtd_partition *part,
4422 unsigned int type)
4423{
4424 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4425 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4426 const struct efx_ef10_nvram_type_info *info;
4427 size_t size, erase_size, outlen;
4428 bool protected;
4429 int rc;
4430
4431 for (info = efx_ef10_nvram_types; ; info++) {
4432 if (info ==
4433 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4434 return -ENODEV;
4435 if ((type & ~info->type_mask) == info->type)
4436 break;
4437 }
4438 if (info->port != efx_port_num(efx))
4439 return -ENODEV;
4440
4441 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4442 if (rc)
4443 return rc;
4444 if (protected)
4445 return -ENODEV; /* hide it */
4446
4447 part->nvram_type = type;
4448
4449 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4450 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4451 outbuf, sizeof(outbuf), &outlen);
4452 if (rc)
4453 return rc;
4454 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4455 return -EIO;
4456 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4457 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4458 part->fw_subtype = MCDI_DWORD(outbuf,
4459 NVRAM_METADATA_OUT_SUBTYPE);
4460
4461 part->common.dev_type_name = "EF10 NVRAM manager";
4462 part->common.type_name = info->name;
4463
4464 part->common.mtd.type = MTD_NORFLASH;
4465 part->common.mtd.flags = MTD_CAP_NORFLASH;
4466 part->common.mtd.size = size;
4467 part->common.mtd.erasesize = erase_size;
4468
4469 return 0;
4470}
4471
4472static int efx_ef10_mtd_probe(struct efx_nic *efx)
4473{
4474 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4475 struct efx_mcdi_mtd_partition *parts;
4476 size_t outlen, n_parts_total, i, n_parts;
4477 unsigned int type;
4478 int rc;
4479
4480 ASSERT_RTNL();
4481
4482 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4483 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4484 outbuf, sizeof(outbuf), &outlen);
4485 if (rc)
4486 return rc;
4487 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4488 return -EIO;
4489
4490 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4491 if (n_parts_total >
4492 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4493 return -EIO;
4494
4495 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4496 if (!parts)
4497 return -ENOMEM;
4498
4499 n_parts = 0;
4500 for (i = 0; i < n_parts_total; i++) {
4501 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4502 i);
4503 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4504 if (rc == 0)
4505 n_parts++;
4506 else if (rc != -ENODEV)
4507 goto fail;
4508 }
4509
4510 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4511fail:
4512 if (rc)
4513 kfree(parts);
4514 return rc;
4515}
4516
4517#endif /* CONFIG_SFC_MTD */
4518
4519static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4520{
4521 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4522}
4523
02246a7f
SS		 4524static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4525 u32 host_time) {}
4526
bd9a265d
JC		 4527static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4528 bool temp)
4529{
4530 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4531 int rc;
4532
4533 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4534 channel->sync_events_state == SYNC_EVENTS_VALID ||
4535 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4536 return 0;
4537 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4538
4539 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4540 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4541 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4542 channel->channel);
4543
4544 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4545 inbuf, sizeof(inbuf), NULL, 0, NULL);
4546
4547 if (rc != 0)
4548 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4549 SYNC_EVENTS_DISABLED;
4550
4551 return rc;
4552}
4553
4554static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4555 bool temp)
4556{
4557 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4558 int rc;
4559
4560 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4561 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4562 return 0;
4563 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4564 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4565 return 0;
4566 }
4567 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4568 SYNC_EVENTS_DISABLED;
4569
4570 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4571 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4572 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4573 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4574 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4575 channel->channel);
4576
4577 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4578 inbuf, sizeof(inbuf), NULL, 0, NULL);
4579
4580 return rc;
4581}
4582
4583static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4584 bool temp)
4585{
4586 int (*set)(struct efx_channel *channel, bool temp);
4587 struct efx_channel *channel;
4588
4589 set = en ?
4590 efx_ef10_rx_enable_timestamping :
4591 efx_ef10_rx_disable_timestamping;
4592
4593 efx_for_each_channel(channel, efx) {
4594 int rc = set(channel, temp);
4595 if (en && rc != 0) {
4596 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4597 return rc;
4598 }
4599 }
4600
4601 return 0;
4602}
4603
02246a7f
SS		 4604static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4605 struct hwtstamp_config *init)
4606{
4607 return -EOPNOTSUPP;
4608}
4609
bd9a265d
JC		 4610static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4611 struct hwtstamp_config *init)
4612{
4613 int rc;
4614
4615 switch (init->rx_filter) {
4616 case HWTSTAMP_FILTER_NONE:
4617 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4618 /* if TX timestamping is still requested then leave PTP on */
4619 return efx_ptp_change_mode(efx,
4620 init->tx_type != HWTSTAMP_TX_OFF, 0);
4621 case HWTSTAMP_FILTER_ALL:
4622 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4623 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4624 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4625 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4626 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4627 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4628 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4629 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4630 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4631 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4632 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4633 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4634 init->rx_filter = HWTSTAMP_FILTER_ALL;
4635 rc = efx_ptp_change_mode(efx, true, 0);
4636 if (!rc)
4637 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4638 if (rc)
4639 efx_ptp_change_mode(efx, false, 0);
4640 return rc;
4641 default:
4642 return -ERANGE;
4643 }
4644}
4645
02246a7f 4646const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 4647 .is_vf = true,
02246a7f
SS		 4648 .mem_bar = EFX_MEM_VF_BAR,
4649 .mem_map_size = efx_ef10_mem_map_size,
4650 .probe = efx_ef10_probe_vf,
4651 .remove = efx_ef10_remove,
4652 .dimension_resources = efx_ef10_dimension_resources,
4653 .init = efx_ef10_init_nic,
4654 .fini = efx_port_dummy_op_void,
087e9025 4655 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 4656 .map_reset_flags = efx_ef10_map_reset_flags,
4657 .reset = efx_ef10_reset,
4658 .probe_port = efx_mcdi_port_probe,
4659 .remove_port = efx_mcdi_port_remove,
4660 .fini_dmaq = efx_ef10_fini_dmaq,
4661 .prepare_flr = efx_ef10_prepare_flr,
4662 .finish_flr = efx_port_dummy_op_void,
4663 .describe_stats = efx_ef10_describe_stats,
d7788196 4664 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 4665 .start_stats = efx_port_dummy_op_void,
4666 .pull_stats = efx_port_dummy_op_void,
4667 .stop_stats = efx_port_dummy_op_void,
4668 .set_id_led = efx_mcdi_set_id_led,
4669 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 4670 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 4671 .check_mac_fault = efx_mcdi_mac_check_fault,
4672 .reconfigure_port = efx_mcdi_port_reconfigure,
4673 .get_wol = efx_ef10_get_wol_vf,
4674 .set_wol = efx_ef10_set_wol_vf,
4675 .resume_wol = efx_port_dummy_op_void,
4676 .mcdi_request = efx_ef10_mcdi_request,
4677 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4678 .mcdi_read_response = efx_ef10_mcdi_read_response,
4679 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 4680 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 4681 .irq_enable_master = efx_port_dummy_op_void,
4682 .irq_test_generate = efx_ef10_irq_test_generate,
4683 .irq_disable_non_ev = efx_port_dummy_op_void,
4684 .irq_handle_msi = efx_ef10_msi_interrupt,
4685 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4686 .tx_probe = efx_ef10_tx_probe,
4687 .tx_init = efx_ef10_tx_init,
4688 .tx_remove = efx_ef10_tx_remove,
4689 .tx_write = efx_ef10_tx_write,
267c0157 4690 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 4691 .rx_probe = efx_ef10_rx_probe,
4692 .rx_init = efx_ef10_rx_init,
4693 .rx_remove = efx_ef10_rx_remove,
4694 .rx_write = efx_ef10_rx_write,
4695 .rx_defer_refill = efx_ef10_rx_defer_refill,
4696 .ev_probe = efx_ef10_ev_probe,
4697 .ev_init = efx_ef10_ev_init,
4698 .ev_fini = efx_ef10_ev_fini,
4699 .ev_remove = efx_ef10_ev_remove,
4700 .ev_process = efx_ef10_ev_process,
4701 .ev_read_ack = efx_ef10_ev_read_ack,
4702 .ev_test_generate = efx_ef10_ev_test_generate,
4703 .filter_table_probe = efx_ef10_filter_table_probe,
4704 .filter_table_restore = efx_ef10_filter_table_restore,
4705 .filter_table_remove = efx_ef10_filter_table_remove,
4706 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4707 .filter_insert = efx_ef10_filter_insert,
4708 .filter_remove_safe = efx_ef10_filter_remove_safe,
4709 .filter_get_safe = efx_ef10_filter_get_safe,
4710 .filter_clear_rx = efx_ef10_filter_clear_rx,
4711 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4712 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4713 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4714#ifdef CONFIG_RFS_ACCEL
4715 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4716 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4717#endif
4718#ifdef CONFIG_SFC_MTD
4719 .mtd_probe = efx_port_dummy_op_int,
4720#endif
4721 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4722 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4723#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 4724 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4725 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4726 .vswitching_remove = efx_ef10_vswitching_remove_vf,
1d051e00 4727 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
02246a7f 4728#endif
0d5e0fbb 4729 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 4730 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 4731
02246a7f
SS		 4732 .revision = EFX_REV_HUNT_A0,
4733 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4734 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4735 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4736 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4737 .can_rx_scatter = true,
4738 .always_rx_scatter = true,
4739 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4740 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4741 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4742 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4743 .mcdi_max_ver = 2,
4744 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4745 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4746 1 << HWTSTAMP_FILTER_ALL,
4747};
4748
8127d661 4749const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 4750 .is_vf = false,
02246a7f 4751 .mem_bar = EFX_MEM_BAR,
8127d661 4752 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 4753 .probe = efx_ef10_probe_pf,
8127d661
BH		 4754 .remove = efx_ef10_remove,
4755 .dimension_resources = efx_ef10_dimension_resources,
4756 .init = efx_ef10_init_nic,
4757 .fini = efx_port_dummy_op_void,
087e9025 4758 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 4759 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 4760 .reset = efx_ef10_reset,
8127d661
BH		 4761 .probe_port = efx_mcdi_port_probe,
4762 .remove_port = efx_mcdi_port_remove,
4763 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 4764 .prepare_flr = efx_ef10_prepare_flr,
4765 .finish_flr = efx_port_dummy_op_void,
8127d661 4766 .describe_stats = efx_ef10_describe_stats,
d7788196 4767 .update_stats = efx_ef10_update_stats_pf,
8127d661 4768 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 4769 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 4770 .stop_stats = efx_mcdi_mac_stop_stats,
4771 .set_id_led = efx_mcdi_set_id_led,
4772 .push_irq_moderation = efx_ef10_push_irq_moderation,
4773 .reconfigure_mac = efx_ef10_mac_reconfigure,
4774 .check_mac_fault = efx_mcdi_mac_check_fault,
4775 .reconfigure_port = efx_mcdi_port_reconfigure,
4776 .get_wol = efx_ef10_get_wol,
4777 .set_wol = efx_ef10_set_wol,
4778 .resume_wol = efx_port_dummy_op_void,
74cd60a4 4779 .test_chip = efx_ef10_test_chip,
8127d661
BH		 4780 .test_nvram = efx_mcdi_nvram_test_all,
4781 .mcdi_request = efx_ef10_mcdi_request,
4782 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4783 .mcdi_read_response = efx_ef10_mcdi_read_response,
4784 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 4785 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 4786 .irq_enable_master = efx_port_dummy_op_void,
4787 .irq_test_generate = efx_ef10_irq_test_generate,
4788 .irq_disable_non_ev = efx_port_dummy_op_void,
4789 .irq_handle_msi = efx_ef10_msi_interrupt,
4790 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4791 .tx_probe = efx_ef10_tx_probe,
4792 .tx_init = efx_ef10_tx_init,
4793 .tx_remove = efx_ef10_tx_remove,
4794 .tx_write = efx_ef10_tx_write,
267c0157 4795 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 4796 .rx_probe = efx_ef10_rx_probe,
4797 .rx_init = efx_ef10_rx_init,
4798 .rx_remove = efx_ef10_rx_remove,
4799 .rx_write = efx_ef10_rx_write,
4800 .rx_defer_refill = efx_ef10_rx_defer_refill,
4801 .ev_probe = efx_ef10_ev_probe,
4802 .ev_init = efx_ef10_ev_init,
4803 .ev_fini = efx_ef10_ev_fini,
4804 .ev_remove = efx_ef10_ev_remove,
4805 .ev_process = efx_ef10_ev_process,
4806 .ev_read_ack = efx_ef10_ev_read_ack,
4807 .ev_test_generate = efx_ef10_ev_test_generate,
4808 .filter_table_probe = efx_ef10_filter_table_probe,
4809 .filter_table_restore = efx_ef10_filter_table_restore,
4810 .filter_table_remove = efx_ef10_filter_table_remove,
4811 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4812 .filter_insert = efx_ef10_filter_insert,
4813 .filter_remove_safe = efx_ef10_filter_remove_safe,
4814 .filter_get_safe = efx_ef10_filter_get_safe,
4815 .filter_clear_rx = efx_ef10_filter_clear_rx,
4816 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4817 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4818 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4819#ifdef CONFIG_RFS_ACCEL
4820 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4821 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4822#endif
4823#ifdef CONFIG_SFC_MTD
4824 .mtd_probe = efx_ef10_mtd_probe,
4825 .mtd_rename = efx_mcdi_mtd_rename,
4826 .mtd_read = efx_mcdi_mtd_read,
4827 .mtd_erase = efx_mcdi_mtd_erase,
4828 .mtd_write = efx_mcdi_mtd_write,
4829 .mtd_sync = efx_mcdi_mtd_sync,
4830#endif
4831 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 4832 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4833 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
7fa8d547 4834#ifdef CONFIG_SFC_SRIOV
834e23dd 4835 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 4836 .sriov_init = efx_ef10_sriov_init,
4837 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 4838 .sriov_wanted = efx_ef10_sriov_wanted,
4839 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 4840 .sriov_flr = efx_ef10_sriov_flr,
4841 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4842 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4843 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4844 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 4845 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 4846 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4847 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4848 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 4849#endif
0d5e0fbb 4850 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 4851 .set_mac_address = efx_ef10_set_mac_address,
8127d661
BH		 4852
4853 .revision = EFX_REV_HUNT_A0,
4854 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4855 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4856 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 4857 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 4858 .can_rx_scatter = true,
4859 .always_rx_scatter = true,
4860 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4861 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4862 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4863 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4864 .mcdi_max_ver = 2,
4865 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 4866 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4867 1 << HWTSTAMP_FILTER_ALL,
8127d661 4868};
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