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jme: do vlan cleanup
[mirror_ubuntu-artful-kernel.git] / drivers / net / jme.c
CommitLineData
95252236
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
e47dfcd8 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
95252236
GFT		 7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
49d70c48
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
95252236
GFT		 27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/crc32.h>
35#include <linux/delay.h>
36#include <linux/spinlock.h>
37#include <linux/in.h>
38#include <linux/ip.h>
39#include <linux/ipv6.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/if_vlan.h>
5a0e3ad6 43#include <linux/slab.h>
b7c6bfb7 44#include <net/ip6_checksum.h>
95252236
GFT		 45#include "jme.h"
46
47static int force_pseudohp = -1;
48static int no_pseudohp = -1;
49static int no_extplug = -1;
50module_param(force_pseudohp, int, 0);
51MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53module_param(no_pseudohp, int, 0);
54MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55module_param(no_extplug, int, 0);
56MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
58
59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
61{
62 struct jme_adapter *jme = netdev_priv(netdev);
63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
64
65read_again:
66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
69
70 wmb();
71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72 udelay(20);
73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
75 break;
76 }
77
78 if (i == 0) {
49d70c48 79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
95252236
GFT		 80 return 0;
81 }
82
83 if (again--)
84 goto read_again;
85
86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
87}
88
89static void
90jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
92{
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
99
100 wmb();
101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 break;
105 }
106
107 if (i == 0)
49d70c48 108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
95252236
GFT		 109}
110
111static inline void
112jme_reset_phy_processor(struct jme_adapter *jme)
113{
114 u32 val;
115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120
121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126
127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
95252236
GFT		 134}
135
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
b6bc7650 138 const u32 *mask, u32 crc, int fnr)
95252236
GFT		 139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
162
854a2e7c
GFT		 163static inline void
164jme_mac_rxclk_off(struct jme_adapter *jme)
165{
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168}
169
170static inline void
171jme_mac_rxclk_on(struct jme_adapter *jme)
172{
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175}
176
177static inline void
178jme_mac_txclk_off(struct jme_adapter *jme)
179{
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
182}
183
184static inline void
185jme_mac_txclk_on(struct jme_adapter *jme)
186{
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190 else
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
193}
194
195static inline void
196jme_reset_ghc_speed(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_reset_250A2_workaround(struct jme_adapter *jme)
204{
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206 GPREG1_RSSPATCH);
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208}
209
210static inline void
211jme_assert_ghc_reset(struct jme_adapter *jme)
212{
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215}
216
217static inline void
218jme_clear_ghc_reset(struct jme_adapter *jme)
219{
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
222}
223
95252236
GFT		 224static inline void
225jme_reset_mac_processor(struct jme_adapter *jme)
226{
b6bc7650 227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
95252236
GFT		 228 u32 crc = 0xCDCDCDCD;
229 u32 gpreg0;
230 int i;
231
854a2e7c
GFT		 232 jme_reset_ghc_speed(jme);
233 jme_reset_250A2_workaround(jme);
234
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
237 udelay(1);
238 jme_assert_ghc_reset(jme);
239 udelay(1);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
242 udelay(1);
243 jme_clear_ghc_reset(jme);
244 udelay(1);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
247 udelay(1);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
95252236
GFT		 250
251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253 jwrite32(jme, JME_RXQDC, 0x00000000);
254 jwrite32(jme, JME_RXNDA, 0x00000000);
255 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257 jwrite32(jme, JME_TXQDC, 0x00000000);
258 jwrite32(jme, JME_TXNDA, 0x00000000);
259
260 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
262 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
263 jme_setup_wakeup_frame(jme, mask, crc, i);
264 if (jme->fpgaver)
265 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266 else
267 gpreg0 = GPREG0_DEFAULT;
268 jwrite32(jme, JME_GPREG0, gpreg0);
95252236
GFT		 269}
270
271static inline void
272jme_clear_pm(struct jme_adapter *jme)
273{
bc057e03 274 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
95252236
GFT		 275}
276
277static int
278jme_reload_eeprom(struct jme_adapter *jme)
279{
280 u32 val;
281 int i;
282
283 val = jread32(jme, JME_SMBCSR);
284
285 if (val & SMBCSR_EEPROMD) {
286 val |= SMBCSR_CNACK;
287 jwrite32(jme, JME_SMBCSR, val);
288 val |= SMBCSR_RELOAD;
289 jwrite32(jme, JME_SMBCSR, val);
290 mdelay(12);
291
292 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
293 mdelay(1);
294 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
295 break;
296 }
297
298 if (i == 0) {
49d70c48 299 pr_err("eeprom reload timeout\n");
95252236
GFT		 300 return -EIO;
301 }
302 }
303
304 return 0;
305}
306
307static void
308jme_load_macaddr(struct net_device *netdev)
309{
310 struct jme_adapter *jme = netdev_priv(netdev);
311 unsigned char macaddr[6];
312 u32 val;
313
314 spin_lock_bh(&jme->macaddr_lock);
315 val = jread32(jme, JME_RXUMA_LO);
316 macaddr[0] = (val >> 0) & 0xFF;
317 macaddr[1] = (val >> 8) & 0xFF;
318 macaddr[2] = (val >> 16) & 0xFF;
319 macaddr[3] = (val >> 24) & 0xFF;
320 val = jread32(jme, JME_RXUMA_HI);
321 macaddr[4] = (val >> 0) & 0xFF;
322 macaddr[5] = (val >> 8) & 0xFF;
323 memcpy(netdev->dev_addr, macaddr, 6);
324 spin_unlock_bh(&jme->macaddr_lock);
325}
326
327static inline void
328jme_set_rx_pcc(struct jme_adapter *jme, int p)
329{
330 switch (p) {
331 case PCC_OFF:
332 jwrite32(jme, JME_PCCRX0,
333 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
334 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
335 break;
336 case PCC_P1:
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340 break;
341 case PCC_P2:
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345 break;
346 case PCC_P3:
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350 break;
351 default:
352 break;
353 }
354 wmb();
355
356 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
f8502ce4 357 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
95252236
GFT		 358}
359
360static void
361jme_start_irq(struct jme_adapter *jme)
362{
363 register struct dynpcc_info *dpi = &(jme->dpi);
364
365 jme_set_rx_pcc(jme, PCC_P1);
366 dpi->cur = PCC_P1;
367 dpi->attempt = PCC_P1;
368 dpi->cnt = 0;
369
370 jwrite32(jme, JME_PCCTX,
371 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
372 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
373 PCCTXQ0_EN
374 );
375
376 /*
377 * Enable Interrupts
378 */
379 jwrite32(jme, JME_IENS, INTR_ENABLE);
380}
381
382static inline void
383jme_stop_irq(struct jme_adapter *jme)
384{
385 /*
386 * Disable Interrupts
387 */
388 jwrite32f(jme, JME_IENC, INTR_ENABLE);
389}
390
95252236
GFT		 391static u32
392jme_linkstat_from_phy(struct jme_adapter *jme)
393{
394 u32 phylink, bmsr;
395
396 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
397 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
398 if (bmsr & BMSR_ANCOMP)
399 phylink |= PHY_LINK_AUTONEG_COMPLETE;
400
401 return phylink;
402}
403
404static inline void
51754572 405jme_set_phyfifo_5level(struct jme_adapter *jme)
95252236
GFT		 406{
407 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
408}
409
410static inline void
51754572 411jme_set_phyfifo_8level(struct jme_adapter *jme)
95252236
GFT		 412{
413 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
414}
415
416static int
417jme_check_link(struct net_device *netdev, int testonly)
418{
419 struct jme_adapter *jme = netdev_priv(netdev);
854a2e7c 420 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
95252236
GFT		 421 char linkmsg[64];
422 int rc = 0;
423
424 linkmsg[0] = '\0';
425
426 if (jme->fpgaver)
427 phylink = jme_linkstat_from_phy(jme);
428 else
429 phylink = jread32(jme, JME_PHY_LINK);
430
431 if (phylink & PHY_LINK_UP) {
432 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
433 /*
434 * If we did not enable AN
435 * Speed/Duplex Info should be obtained from SMI
436 */
437 phylink = PHY_LINK_UP;
438
439 bmcr = jme_mdio_read(jme->dev,
440 jme->mii_if.phy_id,
441 MII_BMCR);
442
443 phylink |= ((bmcr & BMCR_SPEED1000) &&
444 (bmcr & BMCR_SPEED100) == 0) ?
445 PHY_LINK_SPEED_1000M :
446 (bmcr & BMCR_SPEED100) ?
447 PHY_LINK_SPEED_100M :
448 PHY_LINK_SPEED_10M;
449
450 phylink |= (bmcr & BMCR_FULLDPLX) ?
451 PHY_LINK_DUPLEX : 0;
452
453 strcat(linkmsg, "Forced: ");
454 } else {
455 /*
456 * Keep polling for speed/duplex resolve complete
457 */
458 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
459 --cnt) {
460
461 udelay(1);
462
463 if (jme->fpgaver)
464 phylink = jme_linkstat_from_phy(jme);
465 else
466 phylink = jread32(jme, JME_PHY_LINK);
467 }
468 if (!cnt)
49d70c48 469 pr_err("Waiting speed resolve timeout\n");
95252236
GFT		 470
471 strcat(linkmsg, "ANed: ");
472 }
473
474 if (jme->phylink == phylink) {
475 rc = 1;
476 goto out;
477 }
478 if (testonly)
479 goto out;
480
481 jme->phylink = phylink;
482
854a2e7c
GFT		 483 /*
484 * The speed/duplex setting of jme->reg_ghc already cleared
485 * by jme_reset_mac_processor()
486 */
95252236
GFT		 487 switch (phylink & PHY_LINK_SPEED_MASK) {
488 case PHY_LINK_SPEED_10M:
854a2e7c 489 jme->reg_ghc |= GHC_SPEED_10M;
95252236 490 strcat(linkmsg, "10 Mbps, ");
95252236
GFT		 491 break;
492 case PHY_LINK_SPEED_100M:
854a2e7c 493 jme->reg_ghc |= GHC_SPEED_100M;
95252236 494 strcat(linkmsg, "100 Mbps, ");
95252236
GFT		 495 break;
496 case PHY_LINK_SPEED_1000M:
854a2e7c 497 jme->reg_ghc |= GHC_SPEED_1000M;
95252236 498 strcat(linkmsg, "1000 Mbps, ");
95252236
GFT		 499 break;
500 default:
501 break;
502 }
95252236
GFT		 503
504 if (phylink & PHY_LINK_DUPLEX) {
505 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
3903c023 506 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
854a2e7c 507 jme->reg_ghc |= GHC_DPX;
95252236
GFT		 508 } else {
509 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
510 TXMCS_BACKOFF |
511 TXMCS_CARRIERSENSE |
512 TXMCS_COLLISION);
3903c023 513 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
95252236 514 }
a821ebe5 515
854a2e7c
GFT		 516 jwrite32(jme, JME_GHC, jme->reg_ghc);
517
a821ebe5 518 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
854a2e7c
GFT		 519 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
520 GPREG1_RSSPATCH);
a821ebe5 521 if (!(phylink & PHY_LINK_DUPLEX))
854a2e7c 522 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
a821ebe5
GFT		 523 switch (phylink & PHY_LINK_SPEED_MASK) {
524 case PHY_LINK_SPEED_10M:
51754572 525 jme_set_phyfifo_8level(jme);
854a2e7c 526 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
a821ebe5
GFT		 527 break;
528 case PHY_LINK_SPEED_100M:
51754572 529 jme_set_phyfifo_5level(jme);
854a2e7c 530 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
a821ebe5
GFT		 531 break;
532 case PHY_LINK_SPEED_1000M:
51754572 533 jme_set_phyfifo_8level(jme);
a821ebe5
GFT		 534 break;
535 default:
536 break;
537 }
538 }
854a2e7c 539 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
95252236 540
4f40bf46 541 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
542 "Full-Duplex, " :
543 "Half-Duplex, ");
544 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
545 "MDI-X" :
546 "MDI");
49d70c48 547 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
95252236
GFT		 548 netif_carrier_on(netdev);
549 } else {
550 if (testonly)
551 goto out;
552
49d70c48 553 netif_info(jme, link, jme->dev, "Link is down\n");
95252236
GFT		 554 jme->phylink = 0;
555 netif_carrier_off(netdev);
556 }
557
558out:
559 return rc;
560}
561
562static int
563jme_setup_tx_resources(struct jme_adapter *jme)
564{
565 struct jme_ring *txring = &(jme->txring[0]);
566
567 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
568 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
569 &(txring->dmaalloc),
570 GFP_ATOMIC);
571
47bd10d1
GFT		 572 if (!txring->alloc)
573 goto err_set_null;
95252236
GFT		 574
575 /*
576 * 16 Bytes align
577 */
578 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
579 RING_DESC_ALIGN);
580 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
581 txring->next_to_use = 0;
582 atomic_set(&txring->next_to_clean, 0);
583 atomic_set(&txring->nr_free, jme->tx_ring_size);
584
47bd10d1
GFT		 585 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
586 jme->tx_ring_size, GFP_ATOMIC);
587 if (unlikely(!(txring->bufinf)))
588 goto err_free_txring;
589
95252236
GFT		 590 /*
591 * Initialize Transmit Descriptors
592 */
593 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
594 memset(txring->bufinf, 0,
595 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
596
597 return 0;
47bd10d1
GFT		 598
599err_free_txring:
600 dma_free_coherent(&(jme->pdev->dev),
601 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
602 txring->alloc,
603 txring->dmaalloc);
604
605err_set_null:
606 txring->desc = NULL;
607 txring->dmaalloc = 0;
608 txring->dma = 0;
609 txring->bufinf = NULL;
610
611 return -ENOMEM;
95252236
GFT		 612}
613
614static void
615jme_free_tx_resources(struct jme_adapter *jme)
616{
617 int i;
618 struct jme_ring *txring = &(jme->txring[0]);
eacf69a1 619 struct jme_buffer_info *txbi;
95252236
GFT		 620
621 if (txring->alloc) {
47bd10d1
GFT		 622 if (txring->bufinf) {
623 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
624 txbi = txring->bufinf + i;
625 if (txbi->skb) {
626 dev_kfree_skb(txbi->skb);
627 txbi->skb = NULL;
628 }
629 txbi->mapping = 0;
630 txbi->len = 0;
631 txbi->nr_desc = 0;
632 txbi->start_xmit = 0;
95252236 633 }
47bd10d1 634 kfree(txring->bufinf);
95252236
GFT		 635 }
636
637 dma_free_coherent(&(jme->pdev->dev),
638 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
639 txring->alloc,
640 txring->dmaalloc);
641
642 txring->alloc = NULL;
643 txring->desc = NULL;
644 txring->dmaalloc = 0;
645 txring->dma = 0;
47bd10d1 646 txring->bufinf = NULL;
95252236
GFT		 647 }
648 txring->next_to_use = 0;
649 atomic_set(&txring->next_to_clean, 0);
650 atomic_set(&txring->nr_free, 0);
95252236
GFT		 651}
652
653static inline void
654jme_enable_tx_engine(struct jme_adapter *jme)
655{
656 /*
657 * Select Queue 0
658 */
659 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
660 wmb();
661
662 /*
663 * Setup TX Queue 0 DMA Bass Address
664 */
665 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
666 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
667 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
668
669 /*
670 * Setup TX Descptor Count
671 */
672 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
673
674 /*
675 * Enable TX Engine
676 */
677 wmb();
854a2e7c 678 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
95252236
GFT		 679 TXCS_SELECT_QUEUE0 |
680 TXCS_ENABLE);
681
854a2e7c
GFT		 682 /*
683 * Start clock for TX MAC Processor
684 */
685 jme_mac_txclk_on(jme);
95252236
GFT		 686}
687
688static inline void
689jme_restart_tx_engine(struct jme_adapter *jme)
690{
691 /*
692 * Restart TX Engine
693 */
694 jwrite32(jme, JME_TXCS, jme->reg_txcs |
695 TXCS_SELECT_QUEUE0 |
696 TXCS_ENABLE);
697}
698
699static inline void
700jme_disable_tx_engine(struct jme_adapter *jme)
701{
702 int i;
703 u32 val;
704
705 /*
706 * Disable TX Engine
707 */
708 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
709 wmb();
710
711 val = jread32(jme, JME_TXCS);
712 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
713 mdelay(1);
714 val = jread32(jme, JME_TXCS);
715 rmb();
716 }
717
718 if (!i)
49d70c48 719 pr_err("Disable TX engine timeout\n");
854a2e7c
GFT		 720
721 /*
722 * Stop clock for TX MAC Processor
723 */
724 jme_mac_txclk_off(jme);
95252236
GFT		 725}
726
727static void
728jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
729{
eacf69a1 730 struct jme_ring *rxring = &(jme->rxring[0]);
95252236
GFT		 731 register struct rxdesc *rxdesc = rxring->desc;
732 struct jme_buffer_info *rxbi = rxring->bufinf;
733 rxdesc += i;
734 rxbi += i;
735
736 rxdesc->dw[0] = 0;
737 rxdesc->dw[1] = 0;
738 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
739 rxdesc->desc1.bufaddrl = cpu_to_le32(
740 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
741 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
742 if (jme->dev->features & NETIF_F_HIGHDMA)
743 rxdesc->desc1.flags = RXFLAG_64BIT;
744 wmb();
745 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
746}
747
748static int
749jme_make_new_rx_buf(struct jme_adapter *jme, int i)
750{
751 struct jme_ring *rxring = &(jme->rxring[0]);
752 struct jme_buffer_info *rxbi = rxring->bufinf + i;
753 struct sk_buff *skb;
754
755 skb = netdev_alloc_skb(jme->dev,
756 jme->dev->mtu + RX_EXTRA_LEN);
757 if (unlikely(!skb))
758 return -ENOMEM;
759
760 rxbi->skb = skb;
761 rxbi->len = skb_tailroom(skb);
762 rxbi->mapping = pci_map_page(jme->pdev,
763 virt_to_page(skb->data),
764 offset_in_page(skb->data),
765 rxbi->len,
766 PCI_DMA_FROMDEVICE);
767
768 return 0;
769}
770
771static void
772jme_free_rx_buf(struct jme_adapter *jme, int i)
773{
774 struct jme_ring *rxring = &(jme->rxring[0]);
775 struct jme_buffer_info *rxbi = rxring->bufinf;
776 rxbi += i;
777
778 if (rxbi->skb) {
779 pci_unmap_page(jme->pdev,
780 rxbi->mapping,
781 rxbi->len,
782 PCI_DMA_FROMDEVICE);
783 dev_kfree_skb(rxbi->skb);
784 rxbi->skb = NULL;
785 rxbi->mapping = 0;
786 rxbi->len = 0;
787 }
788}
789
790static void
791jme_free_rx_resources(struct jme_adapter *jme)
792{
793 int i;
794 struct jme_ring *rxring = &(jme->rxring[0]);
795
796 if (rxring->alloc) {
47bd10d1
GFT		 797 if (rxring->bufinf) {
798 for (i = 0 ; i < jme->rx_ring_size ; ++i)
799 jme_free_rx_buf(jme, i);
800 kfree(rxring->bufinf);
801 }
95252236
GFT		 802
803 dma_free_coherent(&(jme->pdev->dev),
804 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
805 rxring->alloc,
806 rxring->dmaalloc);
807 rxring->alloc = NULL;
808 rxring->desc = NULL;
809 rxring->dmaalloc = 0;
810 rxring->dma = 0;
47bd10d1 811 rxring->bufinf = NULL;
95252236
GFT		 812 }
813 rxring->next_to_use = 0;
814 atomic_set(&rxring->next_to_clean, 0);
815}
816
817static int
818jme_setup_rx_resources(struct jme_adapter *jme)
819{
820 int i;
821 struct jme_ring *rxring = &(jme->rxring[0]);
822
823 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
824 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
825 &(rxring->dmaalloc),
826 GFP_ATOMIC);
47bd10d1
GFT		 827 if (!rxring->alloc)
828 goto err_set_null;
95252236
GFT		 829
830 /*
831 * 16 Bytes align
832 */
833 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
834 RING_DESC_ALIGN);
835 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
836 rxring->next_to_use = 0;
837 atomic_set(&rxring->next_to_clean, 0);
838
47bd10d1
GFT		 839 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
840 jme->rx_ring_size, GFP_ATOMIC);
841 if (unlikely(!(rxring->bufinf)))
842 goto err_free_rxring;
843
95252236
GFT		 844 /*
845 * Initiallize Receive Descriptors
846 */
47bd10d1
GFT		 847 memset(rxring->bufinf, 0,
848 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
95252236
GFT		 849 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
850 if (unlikely(jme_make_new_rx_buf(jme, i))) {
851 jme_free_rx_resources(jme);
852 return -ENOMEM;
853 }
854
855 jme_set_clean_rxdesc(jme, i);
856 }
857
858 return 0;
47bd10d1
GFT		 859
860err_free_rxring:
861 dma_free_coherent(&(jme->pdev->dev),
862 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
863 rxring->alloc,
864 rxring->dmaalloc);
865err_set_null:
866 rxring->desc = NULL;
867 rxring->dmaalloc = 0;
868 rxring->dma = 0;
869 rxring->bufinf = NULL;
870
871 return -ENOMEM;
95252236
GFT		 872}
873
874static inline void
875jme_enable_rx_engine(struct jme_adapter *jme)
876{
877 /*
878 * Select Queue 0
879 */
880 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
881 RXCS_QUEUESEL_Q0);
882 wmb();
883
884 /*
885 * Setup RX DMA Bass Address
886 */
eacf69a1 887 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
95252236 888 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
eacf69a1 889 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
95252236
GFT		 890
891 /*
892 * Setup RX Descriptor Count
893 */
894 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
895
896 /*
897 * Setup Unicast Filter
898 */
8b53abae 899 jme_set_unicastaddr(jme->dev);
95252236
GFT		 900 jme_set_multi(jme->dev);
901
902 /*
903 * Enable RX Engine
904 */
905 wmb();
854a2e7c 906 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
95252236
GFT		 907 RXCS_QUEUESEL_Q0 |
908 RXCS_ENABLE |
909 RXCS_QST);
854a2e7c
GFT		 910
911 /*
912 * Start clock for RX MAC Processor
913 */
914 jme_mac_rxclk_on(jme);
95252236
GFT		 915}
916
917static inline void
918jme_restart_rx_engine(struct jme_adapter *jme)
919{
920 /*
921 * Start RX Engine
922 */
923 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
924 RXCS_QUEUESEL_Q0 |
925 RXCS_ENABLE |
926 RXCS_QST);
927}
928
929static inline void
930jme_disable_rx_engine(struct jme_adapter *jme)
931{
932 int i;
933 u32 val;
934
935 /*
936 * Disable RX Engine
937 */
938 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
939 wmb();
940
941 val = jread32(jme, JME_RXCS);
942 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
943 mdelay(1);
944 val = jread32(jme, JME_RXCS);
945 rmb();
946 }
947
948 if (!i)
49d70c48 949 pr_err("Disable RX engine timeout\n");
95252236 950
854a2e7c
GFT		 951 /*
952 * Stop clock for RX MAC Processor
953 */
954 jme_mac_rxclk_off(jme);
95252236
GFT		 955}
956
c00cd826
GFT		 957static u16
958jme_udpsum(struct sk_buff *skb)
959{
960 u16 csum = 0xFFFFu;
961
962 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
963 return csum;
964 if (skb->protocol != htons(ETH_P_IP))
965 return csum;
966 skb_set_network_header(skb, ETH_HLEN);
967 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
968 (skb->len < (ETH_HLEN +
969 (ip_hdr(skb)->ihl << 2) +
970 sizeof(struct udphdr)))) {
971 skb_reset_network_header(skb);
972 return csum;
973 }
974 skb_set_transport_header(skb,
975 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
976 csum = udp_hdr(skb)->check;
977 skb_reset_transport_header(skb);
978 skb_reset_network_header(skb);
979
980 return csum;
981}
982
95252236 983static int
c00cd826 984jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
95252236
GFT		 985{
986 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
987 return false;
988
ce7d70af
GFT		 989 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
990 == RXWBFLAG_TCPON)) {
991 if (flags & RXWBFLAG_IPV4)
f8502ce4 992 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
ce7d70af 993 return false;
95252236
GFT		 994 }
995
ce7d70af 996 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
c00cd826 997 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
ce7d70af 998 if (flags & RXWBFLAG_IPV4)
49d70c48 999 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
ce7d70af 1000 return false;
95252236
GFT		 1001 }
1002
ce7d70af
GFT		 1003 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1004 == RXWBFLAG_IPV4)) {
49d70c48 1005 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
ce7d70af 1006 return false;
95252236
GFT		 1007 }
1008
1009 return true;
95252236
GFT		 1010}
1011
1012static void
1013jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1014{
1015 struct jme_ring *rxring = &(jme->rxring[0]);
1016 struct rxdesc *rxdesc = rxring->desc;
1017 struct jme_buffer_info *rxbi = rxring->bufinf;
1018 struct sk_buff *skb;
1019 int framesize;
1020
1021 rxdesc += idx;
1022 rxbi += idx;
1023
1024 skb = rxbi->skb;
1025 pci_dma_sync_single_for_cpu(jme->pdev,
1026 rxbi->mapping,
1027 rxbi->len,
1028 PCI_DMA_FROMDEVICE);
1029
1030 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1031 pci_dma_sync_single_for_device(jme->pdev,
1032 rxbi->mapping,
1033 rxbi->len,
1034 PCI_DMA_FROMDEVICE);
1035
1036 ++(NET_STAT(jme).rx_dropped);
1037 } else {
1038 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1039 - RX_PREPAD_SIZE;
1040
1041 skb_reserve(skb, RX_PREPAD_SIZE);
1042 skb_put(skb, framesize);
1043 skb->protocol = eth_type_trans(skb, jme->dev);
1044
c00cd826 1045 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
95252236
GFT		 1046 skb->ip_summed = CHECKSUM_UNNECESSARY;
1047 else
bc8acf2c 1048 skb_checksum_none_assert(skb);
95252236 1049
31c221c4 1050 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
5043f505
JP		 1051 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1052
1053 __vlan_hwaccel_put_tag(skb, vid);
1054 NET_STAT(jme).rx_bytes += 4;
95252236 1055 }
5043f505 1056 jme->jme_rx(skb);
95252236 1057
31c221c4
HH		 1058 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1059 cpu_to_le16(RXWBFLAG_DEST_MUL))
95252236
GFT		 1060 ++(NET_STAT(jme).multicast);
1061
95252236
GFT		 1062 NET_STAT(jme).rx_bytes += framesize;
1063 ++(NET_STAT(jme).rx_packets);
1064 }
1065
1066 jme_set_clean_rxdesc(jme, idx);
1067
1068}
1069
1070static int
1071jme_process_receive(struct jme_adapter *jme, int limit)
1072{
1073 struct jme_ring *rxring = &(jme->rxring[0]);
1074 struct rxdesc *rxdesc = rxring->desc;
1075 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1076
1077 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1078 goto out_inc;
1079
1080 if (unlikely(atomic_read(&jme->link_changing) != 1))
1081 goto out_inc;
1082
1083 if (unlikely(!netif_carrier_ok(jme->dev)))
1084 goto out_inc;
1085
1086 i = atomic_read(&rxring->next_to_clean);
858b9ced 1087 while (limit > 0) {
95252236
GFT		 1088 rxdesc = rxring->desc;
1089 rxdesc += i;
1090
31c221c4 1091 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
95252236
GFT		 1092 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1093 goto out;
858b9ced 1094 --limit;
95252236 1095
ea192aa8 1096 rmb();
95252236
GFT		 1097 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1098
1099 if (unlikely(desccnt > 1 ||
1100 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1101
1102 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1103 ++(NET_STAT(jme).rx_crc_errors);
1104 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1105 ++(NET_STAT(jme).rx_fifo_errors);
1106 else
1107 ++(NET_STAT(jme).rx_errors);
1108
1109 if (desccnt > 1)
1110 limit -= desccnt - 1;
1111
1112 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1113 jme_set_clean_rxdesc(jme, j);
1114 j = (j + 1) & (mask);
1115 }
1116
1117 } else {
1118 jme_alloc_and_feed_skb(jme, i);
1119 }
1120
1121 i = (i + desccnt) & (mask);
1122 }
1123
1124out:
1125 atomic_set(&rxring->next_to_clean, i);
1126
1127out_inc:
1128 atomic_inc(&jme->rx_cleaning);
1129
1130 return limit > 0 ? limit : 0;
1131
1132}
1133
1134static void
1135jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1136{
1137 if (likely(atmp == dpi->cur)) {
1138 dpi->cnt = 0;
1139 return;
1140 }
1141
1142 if (dpi->attempt == atmp) {
1143 ++(dpi->cnt);
1144 } else {
1145 dpi->attempt = atmp;
1146 dpi->cnt = 0;
1147 }
1148
1149}
1150
1151static void
1152jme_dynamic_pcc(struct jme_adapter *jme)
1153{
1154 register struct dynpcc_info *dpi = &(jme->dpi);
1155
1156 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1157 jme_attempt_pcc(dpi, PCC_P3);
8e95a202
JP		 1158 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1159 dpi->intr_cnt > PCC_INTR_THRESHOLD)
95252236
GFT		 1160 jme_attempt_pcc(dpi, PCC_P2);
1161 else
1162 jme_attempt_pcc(dpi, PCC_P1);
1163
1164 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1165 if (dpi->attempt < dpi->cur)
1166 tasklet_schedule(&jme->rxclean_task);
1167 jme_set_rx_pcc(jme, dpi->attempt);
1168 dpi->cur = dpi->attempt;
1169 dpi->cnt = 0;
1170 }
1171}
1172
1173static void
1174jme_start_pcc_timer(struct jme_adapter *jme)
1175{
1176 struct dynpcc_info *dpi = &(jme->dpi);
1177 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1178 dpi->last_pkts = NET_STAT(jme).rx_packets;
1179 dpi->intr_cnt = 0;
1180 jwrite32(jme, JME_TMCSR,
1181 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1182}
1183
1184static inline void
1185jme_stop_pcc_timer(struct jme_adapter *jme)
1186{
1187 jwrite32(jme, JME_TMCSR, 0);
1188}
1189
1190static void
1191jme_shutdown_nic(struct jme_adapter *jme)
1192{
1193 u32 phylink;
1194
1195 phylink = jme_linkstat_from_phy(jme);
1196
1197 if (!(phylink & PHY_LINK_UP)) {
1198 /*
1199 * Disable all interrupt before issue timer
1200 */
1201 jme_stop_irq(jme);
1202 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1203 }
1204}
1205
1206static void
1207jme_pcc_tasklet(unsigned long arg)
1208{
1209 struct jme_adapter *jme = (struct jme_adapter *)arg;
1210 struct net_device *netdev = jme->dev;
1211
1212 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1213 jme_shutdown_nic(jme);
1214 return;
1215 }
1216
1217 if (unlikely(!netif_carrier_ok(netdev) ||
1218 (atomic_read(&jme->link_changing) != 1)
1219 )) {
1220 jme_stop_pcc_timer(jme);
1221 return;
1222 }
1223
1224 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1225 jme_dynamic_pcc(jme);
1226
1227 jme_start_pcc_timer(jme);
1228}
1229
1230static inline void
1231jme_polling_mode(struct jme_adapter *jme)
1232{
1233 jme_set_rx_pcc(jme, PCC_OFF);
1234}
1235
1236static inline void
1237jme_interrupt_mode(struct jme_adapter *jme)
1238{
1239 jme_set_rx_pcc(jme, PCC_P1);
1240}
1241
1242static inline int
1243jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1244{
1245 u32 apmc;
1246 apmc = jread32(jme, JME_APMC);
1247 return apmc & JME_APMC_PSEUDO_HP_EN;
1248}
1249
1250static void
1251jme_start_shutdown_timer(struct jme_adapter *jme)
1252{
1253 u32 apmc;
1254
1255 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1256 apmc &= ~JME_APMC_EPIEN_CTRL;
1257 if (!no_extplug) {
1258 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1259 wmb();
1260 }
1261 jwrite32f(jme, JME_APMC, apmc);
1262
1263 jwrite32f(jme, JME_TIMER2, 0);
1264 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1265 jwrite32(jme, JME_TMCSR,
1266 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1267}
1268
1269static void
1270jme_stop_shutdown_timer(struct jme_adapter *jme)
1271{
1272 u32 apmc;
1273
1274 jwrite32f(jme, JME_TMCSR, 0);
1275 jwrite32f(jme, JME_TIMER2, 0);
1276 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1277
1278 apmc = jread32(jme, JME_APMC);
1279 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1280 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1281 wmb();
1282 jwrite32f(jme, JME_APMC, apmc);
1283}
1284
1285static void
1286jme_link_change_tasklet(unsigned long arg)
1287{
1288 struct jme_adapter *jme = (struct jme_adapter *)arg;
1289 struct net_device *netdev = jme->dev;
1290 int rc;
1291
1292 while (!atomic_dec_and_test(&jme->link_changing)) {
1293 atomic_inc(&jme->link_changing);
49d70c48 1294 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
95252236 1295 while (atomic_read(&jme->link_changing) != 1)
49d70c48 1296 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
95252236
GFT		 1297 }
1298
1299 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1300 goto out;
1301
1302 jme->old_mtu = netdev->mtu;
1303 netif_stop_queue(netdev);
1304 if (jme_pseudo_hotplug_enabled(jme))
1305 jme_stop_shutdown_timer(jme);
1306
1307 jme_stop_pcc_timer(jme);
1308 tasklet_disable(&jme->txclean_task);
1309 tasklet_disable(&jme->rxclean_task);
1310 tasklet_disable(&jme->rxempty_task);
1311
1312 if (netif_carrier_ok(netdev)) {
95252236
GFT		 1313 jme_disable_rx_engine(jme);
1314 jme_disable_tx_engine(jme);
1315 jme_reset_mac_processor(jme);
1316 jme_free_rx_resources(jme);
1317 jme_free_tx_resources(jme);
1318
1319 if (test_bit(JME_FLAG_POLL, &jme->flags))
1320 jme_polling_mode(jme);
1321
1322 netif_carrier_off(netdev);
1323 }
1324
1325 jme_check_link(netdev, 0);
1326 if (netif_carrier_ok(netdev)) {
1327 rc = jme_setup_rx_resources(jme);
1328 if (rc) {
49d70c48 1329 pr_err("Allocating resources for RX error, Device STOPPED!\n");
95252236
GFT		 1330 goto out_enable_tasklet;
1331 }
1332
1333 rc = jme_setup_tx_resources(jme);
1334 if (rc) {
49d70c48 1335 pr_err("Allocating resources for TX error, Device STOPPED!\n");
95252236
GFT		 1336 goto err_out_free_rx_resources;
1337 }
1338
1339 jme_enable_rx_engine(jme);
1340 jme_enable_tx_engine(jme);
1341
1342 netif_start_queue(netdev);
1343
1344 if (test_bit(JME_FLAG_POLL, &jme->flags))
1345 jme_interrupt_mode(jme);
1346
1347 jme_start_pcc_timer(jme);
1348 } else if (jme_pseudo_hotplug_enabled(jme)) {
1349 jme_start_shutdown_timer(jme);
1350 }
1351
1352 goto out_enable_tasklet;
1353
1354err_out_free_rx_resources:
1355 jme_free_rx_resources(jme);
1356out_enable_tasklet:
1357 tasklet_enable(&jme->txclean_task);
1358 tasklet_hi_enable(&jme->rxclean_task);
1359 tasklet_hi_enable(&jme->rxempty_task);
1360out:
1361 atomic_inc(&jme->link_changing);
1362}
1363
1364static void
1365jme_rx_clean_tasklet(unsigned long arg)
1366{
1367 struct jme_adapter *jme = (struct jme_adapter *)arg;
1368 struct dynpcc_info *dpi = &(jme->dpi);
1369
1370 jme_process_receive(jme, jme->rx_ring_size);
1371 ++(dpi->intr_cnt);
1372
1373}
1374
1375static int
1376jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1377{
1378 struct jme_adapter *jme = jme_napi_priv(holder);
95252236
GFT		 1379 int rest;
1380
1381 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1382
1383 while (atomic_read(&jme->rx_empty) > 0) {
1384 atomic_dec(&jme->rx_empty);
1385 ++(NET_STAT(jme).rx_dropped);
1386 jme_restart_rx_engine(jme);
1387 }
1388 atomic_inc(&jme->rx_empty);
1389
1390 if (rest) {
1391 JME_RX_COMPLETE(netdev, holder);
1392 jme_interrupt_mode(jme);
1393 }
1394
1395 JME_NAPI_WEIGHT_SET(budget, rest);
1396 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1397}
1398
1399static void
1400jme_rx_empty_tasklet(unsigned long arg)
1401{
1402 struct jme_adapter *jme = (struct jme_adapter *)arg;
1403
1404 if (unlikely(atomic_read(&jme->link_changing) != 1))
1405 return;
1406
1407 if (unlikely(!netif_carrier_ok(jme->dev)))
1408 return;
1409
f8502ce4 1410 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
95252236
GFT		 1411
1412 jme_rx_clean_tasklet(arg);
1413
1414 while (atomic_read(&jme->rx_empty) > 0) {
1415 atomic_dec(&jme->rx_empty);
1416 ++(NET_STAT(jme).rx_dropped);
1417 jme_restart_rx_engine(jme);
1418 }
1419 atomic_inc(&jme->rx_empty);
1420}
1421
1422static void
1423jme_wake_queue_if_stopped(struct jme_adapter *jme)
1424{
eacf69a1 1425 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1426
1427 smp_wmb();
1428 if (unlikely(netif_queue_stopped(jme->dev) &&
1429 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
49d70c48 1430 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
95252236
GFT		 1431 netif_wake_queue(jme->dev);
1432 }
1433
1434}
1435
1436static void
1437jme_tx_clean_tasklet(unsigned long arg)
1438{
1439 struct jme_adapter *jme = (struct jme_adapter *)arg;
1440 struct jme_ring *txring = &(jme->txring[0]);
1441 struct txdesc *txdesc = txring->desc;
1442 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1443 int i, j, cnt = 0, max, err, mask;
1444
49d70c48 1445 tx_dbg(jme, "Into txclean\n");
95252236
GFT		 1446
1447 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1448 goto out;
1449
1450 if (unlikely(atomic_read(&jme->link_changing) != 1))
1451 goto out;
1452
1453 if (unlikely(!netif_carrier_ok(jme->dev)))
1454 goto out;
1455
1456 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1457 mask = jme->tx_ring_mask;
1458
1459 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1460
1461 ctxbi = txbi + i;
1462
1463 if (likely(ctxbi->skb &&
1464 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1465
1466 tx_dbg(jme, "txclean: %d+%d@%lu\n",
49d70c48 1467 i, ctxbi->nr_desc, jiffies);
95252236
GFT		 1468
1469 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1470
1471 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1472 ttxbi = txbi + ((i + j) & (mask));
1473 txdesc[(i + j) & (mask)].dw[0] = 0;
1474
1475 pci_unmap_page(jme->pdev,
1476 ttxbi->mapping,
1477 ttxbi->len,
1478 PCI_DMA_TODEVICE);
1479
1480 ttxbi->mapping = 0;
1481 ttxbi->len = 0;
1482 }
1483
1484 dev_kfree_skb(ctxbi->skb);
1485
1486 cnt += ctxbi->nr_desc;
1487
1488 if (unlikely(err)) {
1489 ++(NET_STAT(jme).tx_carrier_errors);
1490 } else {
1491 ++(NET_STAT(jme).tx_packets);
1492 NET_STAT(jme).tx_bytes += ctxbi->len;
1493 }
1494
1495 ctxbi->skb = NULL;
1496 ctxbi->len = 0;
1497 ctxbi->start_xmit = 0;
1498
1499 } else {
1500 break;
1501 }
1502
1503 i = (i + ctxbi->nr_desc) & mask;
1504
1505 ctxbi->nr_desc = 0;
1506 }
1507
49d70c48 1508 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
95252236
GFT		 1509 atomic_set(&txring->next_to_clean, i);
1510 atomic_add(cnt, &txring->nr_free);
1511
1512 jme_wake_queue_if_stopped(jme);
1513
1514out:
1515 atomic_inc(&jme->tx_cleaning);
1516}
1517
1518static void
1519jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1520{
1521 /*
1522 * Disable interrupt
1523 */
1524 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1525
1526 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1527 /*
1528 * Link change event is critical
1529 * all other events are ignored
1530 */
1531 jwrite32(jme, JME_IEVE, intrstat);
1532 tasklet_schedule(&jme->linkch_task);
1533 goto out_reenable;
1534 }
1535
1536 if (intrstat & INTR_TMINTR) {
1537 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1538 tasklet_schedule(&jme->pcc_task);
1539 }
1540
1541 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1542 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1543 tasklet_schedule(&jme->txclean_task);
1544 }
1545
1546 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1547 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1548 INTR_PCCRX0 |
1549 INTR_RX0EMP)) |
1550 INTR_RX0);
1551 }
1552
1553 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1554 if (intrstat & INTR_RX0EMP)
1555 atomic_inc(&jme->rx_empty);
1556
1557 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1558 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1559 jme_polling_mode(jme);
1560 JME_RX_SCHEDULE(jme);
1561 }
1562 }
1563 } else {
1564 if (intrstat & INTR_RX0EMP) {
1565 atomic_inc(&jme->rx_empty);
1566 tasklet_hi_schedule(&jme->rxempty_task);
1567 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1568 tasklet_hi_schedule(&jme->rxclean_task);
1569 }
1570 }
1571
1572out_reenable:
1573 /*
1574 * Re-enable interrupt
1575 */
1576 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1577}
1578
1579static irqreturn_t
1580jme_intr(int irq, void *dev_id)
1581{
1582 struct net_device *netdev = dev_id;
1583 struct jme_adapter *jme = netdev_priv(netdev);
1584 u32 intrstat;
1585
1586 intrstat = jread32(jme, JME_IEVE);
1587
1588 /*
1589 * Check if it's really an interrupt for us
1590 */
576b5223 1591 if (unlikely((intrstat & INTR_ENABLE) == 0))
95252236
GFT		 1592 return IRQ_NONE;
1593
1594 /*
1595 * Check if the device still exist
1596 */
1597 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1598 return IRQ_NONE;
1599
1600 jme_intr_msi(jme, intrstat);
1601
1602 return IRQ_HANDLED;
1603}
1604
1605static irqreturn_t
1606jme_msi(int irq, void *dev_id)
1607{
1608 struct net_device *netdev = dev_id;
1609 struct jme_adapter *jme = netdev_priv(netdev);
1610 u32 intrstat;
1611
d1dfa1d1 1612 intrstat = jread32(jme, JME_IEVE);
95252236
GFT		 1613
1614 jme_intr_msi(jme, intrstat);
1615
1616 return IRQ_HANDLED;
1617}
1618
1619static void
1620jme_reset_link(struct jme_adapter *jme)
1621{
1622 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1623}
1624
1625static void
1626jme_restart_an(struct jme_adapter *jme)
1627{
1628 u32 bmcr;
1629
1630 spin_lock_bh(&jme->phy_lock);
1631 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1632 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1633 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1634 spin_unlock_bh(&jme->phy_lock);
1635}
1636
1637static int
1638jme_request_irq(struct jme_adapter *jme)
1639{
1640 int rc;
1641 struct net_device *netdev = jme->dev;
1642 irq_handler_t handler = jme_intr;
1643 int irq_flags = IRQF_SHARED;
1644
1645 if (!pci_enable_msi(jme->pdev)) {
1646 set_bit(JME_FLAG_MSI, &jme->flags);
1647 handler = jme_msi;
1648 irq_flags = 0;
1649 }
1650
1651 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1652 netdev);
1653 if (rc) {
49d70c48
JP		 1654 netdev_err(netdev,
1655 "Unable to request %s interrupt (return: %d)\n",
1656 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1657 rc);
95252236
GFT		 1658
1659 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1660 pci_disable_msi(jme->pdev);
1661 clear_bit(JME_FLAG_MSI, &jme->flags);
1662 }
1663 } else {
1664 netdev->irq = jme->pdev->irq;
1665 }
1666
1667 return rc;
1668}
1669
1670static void
1671jme_free_irq(struct jme_adapter *jme)
1672{
1673 free_irq(jme->pdev->irq, jme->dev);
1674 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1675 pci_disable_msi(jme->pdev);
1676 clear_bit(JME_FLAG_MSI, &jme->flags);
1677 jme->dev->irq = jme->pdev->irq;
1678 }
1679}
1680
4872b11f
GFT		 1681static inline void
1682jme_new_phy_on(struct jme_adapter *jme)
1683{
1684 u32 reg;
1685
1686 reg = jread32(jme, JME_PHY_PWR);
1687 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1688 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1689 jwrite32(jme, JME_PHY_PWR, reg);
1690
1691 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1692 reg &= ~PE1_GPREG0_PBG;
1693 reg |= PE1_GPREG0_ENBG;
1694 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1695}
1696
1697static inline void
1698jme_new_phy_off(struct jme_adapter *jme)
1699{
1700 u32 reg;
1701
1702 reg = jread32(jme, JME_PHY_PWR);
1703 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1704 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1705 jwrite32(jme, JME_PHY_PWR, reg);
1706
1707 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1708 reg &= ~PE1_GPREG0_PBG;
1709 reg |= PE1_GPREG0_PDD3COLD;
1710 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1711}
1712
c8a8684d
GFT		 1713static inline void
1714jme_phy_on(struct jme_adapter *jme)
1715{
1716 u32 bmcr;
1717
1718 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1719 bmcr &= ~BMCR_PDOWN;
1720 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
4872b11f
GFT		 1721
1722 if (new_phy_power_ctrl(jme->chip_main_rev))
1723 jme_new_phy_on(jme);
1724}
1725
1726static inline void
1727jme_phy_off(struct jme_adapter *jme)
1728{
1729 u32 bmcr;
1730
1731 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1732 bmcr |= BMCR_PDOWN;
1733 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1734
1735 if (new_phy_power_ctrl(jme->chip_main_rev))
1736 jme_new_phy_off(jme);
c8a8684d
GFT		 1737}
1738
95252236
GFT		 1739static int
1740jme_open(struct net_device *netdev)
1741{
1742 struct jme_adapter *jme = netdev_priv(netdev);
1743 int rc;
1744
1745 jme_clear_pm(jme);
1746 JME_NAPI_ENABLE(jme);
1747
38ed0c21 1748 tasklet_enable(&jme->linkch_task);
95252236
GFT		 1749 tasklet_enable(&jme->txclean_task);
1750 tasklet_hi_enable(&jme->rxclean_task);
1751 tasklet_hi_enable(&jme->rxempty_task);
1752
1753 rc = jme_request_irq(jme);
1754 if (rc)
1755 goto err_out;
1756
95252236
GFT		 1757 jme_start_irq(jme);
1758
4872b11f
GFT		 1759 jme_phy_on(jme);
1760 if (test_bit(JME_FLAG_SSET, &jme->flags))
95252236 1761 jme_set_settings(netdev, &jme->old_ecmd);
4872b11f 1762 else
95252236
GFT		 1763 jme_reset_phy_processor(jme);
1764
1765 jme_reset_link(jme);
1766
1767 return 0;
1768
1769err_out:
1770 netif_stop_queue(netdev);
1771 netif_carrier_off(netdev);
1772 return rc;
1773}
1774
1775static void
1776jme_set_100m_half(struct jme_adapter *jme)
1777{
1778 u32 bmcr, tmp;
1779
1c557819 1780 jme_phy_on(jme);
95252236
GFT		 1781 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1782 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1783 BMCR_SPEED1000 | BMCR_FULLDPLX);
1784 tmp |= BMCR_SPEED100;
1785
1786 if (bmcr != tmp)
1787 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1788
1789 if (jme->fpgaver)
1790 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1791 else
1792 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1793}
1794
1795#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1796static void
1797jme_wait_link(struct jme_adapter *jme)
1798{
1799 u32 phylink, to = JME_WAIT_LINK_TIME;
1800
1801 mdelay(1000);
1802 phylink = jme_linkstat_from_phy(jme);
1803 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1804 mdelay(10);
1805 phylink = jme_linkstat_from_phy(jme);
1806 }
1807}
1808
1c557819
GFT		 1809static void
1810jme_powersave_phy(struct jme_adapter *jme)
1811{
1812 if (jme->reg_pmcs) {
1813 jme_set_100m_half(jme);
1c557819
GFT		 1814 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1815 jme_wait_link(jme);
bc057e03 1816 jme_clear_pm(jme);
1c557819
GFT		 1817 } else {
1818 jme_phy_off(jme);
1819 }
1820}
1821
95252236
GFT		 1822static int
1823jme_close(struct net_device *netdev)
1824{
1825 struct jme_adapter *jme = netdev_priv(netdev);
1826
1827 netif_stop_queue(netdev);
1828 netif_carrier_off(netdev);
1829
1830 jme_stop_irq(jme);
95252236
GFT		 1831 jme_free_irq(jme);
1832
1833 JME_NAPI_DISABLE(jme);
1834
38ed0c21
GFT		 1835 tasklet_disable(&jme->linkch_task);
1836 tasklet_disable(&jme->txclean_task);
1837 tasklet_disable(&jme->rxclean_task);
1838 tasklet_disable(&jme->rxempty_task);
95252236 1839
95252236
GFT		 1840 jme_disable_rx_engine(jme);
1841 jme_disable_tx_engine(jme);
1842 jme_reset_mac_processor(jme);
1843 jme_free_rx_resources(jme);
1844 jme_free_tx_resources(jme);
1845 jme->phylink = 0;
1846 jme_phy_off(jme);
1847
1848 return 0;
1849}
1850
1851static int
1852jme_alloc_txdesc(struct jme_adapter *jme,
1853 struct sk_buff *skb)
1854{
eacf69a1 1855 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1856 int idx, nr_alloc, mask = jme->tx_ring_mask;
1857
1858 idx = txring->next_to_use;
1859 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1860
1861 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1862 return -1;
1863
1864 atomic_sub(nr_alloc, &txring->nr_free);
1865
1866 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1867
1868 return idx;
1869}
1870
1871static void
1872jme_fill_tx_map(struct pci_dev *pdev,
1873 struct txdesc *txdesc,
1874 struct jme_buffer_info *txbi,
1875 struct page *page,
1876 u32 page_offset,
1877 u32 len,
1878 u8 hidma)
1879{
1880 dma_addr_t dmaaddr;
1881
1882 dmaaddr = pci_map_page(pdev,
1883 page,
1884 page_offset,
1885 len,
1886 PCI_DMA_TODEVICE);
1887
1888 pci_dma_sync_single_for_device(pdev,
1889 dmaaddr,
1890 len,
1891 PCI_DMA_TODEVICE);
1892
1893 txdesc->dw[0] = 0;
1894 txdesc->dw[1] = 0;
1895 txdesc->desc2.flags = TXFLAG_OWN;
1896 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1897 txdesc->desc2.datalen = cpu_to_le16(len);
1898 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1899 txdesc->desc2.bufaddrl = cpu_to_le32(
1900 (__u64)dmaaddr & 0xFFFFFFFFUL);
1901
1902 txbi->mapping = dmaaddr;
1903 txbi->len = len;
1904}
1905
1906static void
1907jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1908{
eacf69a1 1909 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1910 struct txdesc *txdesc = txring->desc, *ctxdesc;
1911 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1912 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1913 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1914 int mask = jme->tx_ring_mask;
1915 struct skb_frag_struct *frag;
1916 u32 len;
1917
1918 for (i = 0 ; i < nr_frags ; ++i) {
1919 frag = &skb_shinfo(skb)->frags[i];
1920 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1921 ctxbi = txbi + ((idx + i + 2) & (mask));
1922
1923 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1924 frag->page_offset, frag->size, hidma);
1925 }
1926
1927 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1928 ctxdesc = txdesc + ((idx + 1) & (mask));
1929 ctxbi = txbi + ((idx + 1) & (mask));
1930 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1931 offset_in_page(skb->data), len, hidma);
1932
1933}
1934
1935static int
1936jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1937{
1938 if (unlikely(skb_shinfo(skb)->gso_size &&
1939 skb_header_cloned(skb) &&
1940 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1941 dev_kfree_skb(skb);
1942 return -1;
1943 }
1944
1945 return 0;
1946}
1947
1948static int
31c221c4 1949jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
95252236 1950{
31c221c4 1951 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
95252236
GFT		 1952 if (*mss) {
1953 *flags |= TXFLAG_LSEN;
1954
1955 if (skb->protocol == htons(ETH_P_IP)) {
1956 struct iphdr *iph = ip_hdr(skb);
1957
1958 iph->check = 0;
1959 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1960 iph->daddr, 0,
1961 IPPROTO_TCP,
1962 0);
1963 } else {
1964 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1965
1966 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1967 &ip6h->daddr, 0,
1968 IPPROTO_TCP,
1969 0);
1970 }
1971
1972 return 0;
1973 }
1974
1975 return 1;
1976}
1977
1978static void
1979jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1980{
1981 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1982 u8 ip_proto;
1983
1984 switch (skb->protocol) {
1985 case htons(ETH_P_IP):
1986 ip_proto = ip_hdr(skb)->protocol;
1987 break;
1988 case htons(ETH_P_IPV6):
1989 ip_proto = ipv6_hdr(skb)->nexthdr;
1990 break;
1991 default:
1992 ip_proto = 0;
1993 break;
1994 }
1995
1996 switch (ip_proto) {
1997 case IPPROTO_TCP:
1998 *flags |= TXFLAG_TCPCS;
1999 break;
2000 case IPPROTO_UDP:
2001 *flags |= TXFLAG_UDPCS;
2002 break;
2003 default:
49d70c48 2004 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
95252236
GFT		 2005 break;
2006 }
2007 }
2008}
2009
2010static inline void
31c221c4 2011jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
95252236
GFT		 2012{
2013 if (vlan_tx_tag_present(skb)) {
2014 *flags |= TXFLAG_TAGON;
31c221c4 2015 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
95252236
GFT		 2016 }
2017}
2018
2019static int
7f7fd2da 2020jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
95252236 2021{
eacf69a1 2022 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 2023 struct txdesc *txdesc;
2024 struct jme_buffer_info *txbi;
2025 u8 flags;
2026
2027 txdesc = (struct txdesc *)txring->desc + idx;
2028 txbi = txring->bufinf + idx;
2029
2030 txdesc->dw[0] = 0;
2031 txdesc->dw[1] = 0;
2032 txdesc->dw[2] = 0;
2033 txdesc->dw[3] = 0;
2034 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2035 /*
2036 * Set OWN bit at final.
2037 * When kernel transmit faster than NIC.
2038 * And NIC trying to send this descriptor before we tell
2039 * it to start sending this TX queue.
2040 * Other fields are already filled correctly.
2041 */
2042 wmb();
2043 flags = TXFLAG_OWN | TXFLAG_INT;
2044 /*
2045 * Set checksum flags while not tso
2046 */
2047 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2048 jme_tx_csum(jme, skb, &flags);
2049 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
7f7fd2da 2050 jme_map_tx_skb(jme, skb, idx);
95252236
GFT		 2051 txdesc->desc1.flags = flags;
2052 /*
2053 * Set tx buffer info after telling NIC to send
2054 * For better tx_clean timing
2055 */
2056 wmb();
2057 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2058 txbi->skb = skb;
2059 txbi->len = skb->len;
2060 txbi->start_xmit = jiffies;
2061 if (!txbi->start_xmit)
2062 txbi->start_xmit = (0UL-1);
2063
2064 return 0;
2065}
2066
2067static void
2068jme_stop_queue_if_full(struct jme_adapter *jme)
2069{
eacf69a1 2070 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 2071 struct jme_buffer_info *txbi = txring->bufinf;
2072 int idx = atomic_read(&txring->next_to_clean);
2073
2074 txbi += idx;
2075
2076 smp_wmb();
2077 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2078 netif_stop_queue(jme->dev);
49d70c48 2079 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
95252236
GFT		 2080 smp_wmb();
2081 if (atomic_read(&txring->nr_free)
2082 >= (jme->tx_wake_threshold)) {
2083 netif_wake_queue(jme->dev);
49d70c48 2084 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
95252236
GFT		 2085 }
2086 }
2087
2088 if (unlikely(txbi->start_xmit &&
2089 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2090 txbi->skb)) {
2091 netif_stop_queue(jme->dev);
49d70c48
JP		 2092 netif_info(jme, tx_queued, jme->dev,
2093 "TX Queue Stopped %d@%lu\n", idx, jiffies);
95252236
GFT		 2094 }
2095}
2096
2097/*
2098 * This function is already protected by netif_tx_lock()
2099 */
2100
61357325 2101static netdev_tx_t
95252236
GFT		 2102jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2103{
2104 struct jme_adapter *jme = netdev_priv(netdev);
2105 int idx;
2106
2107 if (unlikely(jme_expand_header(jme, skb))) {
2108 ++(NET_STAT(jme).tx_dropped);
2109 return NETDEV_TX_OK;
2110 }
2111
2112 idx = jme_alloc_txdesc(jme, skb);
2113
2114 if (unlikely(idx < 0)) {
2115 netif_stop_queue(netdev);
49d70c48
JP		 2116 netif_err(jme, tx_err, jme->dev,
2117 "BUG! Tx ring full when queue awake!\n");
95252236
GFT		 2118
2119 return NETDEV_TX_BUSY;
2120 }
2121
7f7fd2da 2122 jme_fill_tx_desc(jme, skb, idx);
95252236
GFT		 2123
2124 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2125 TXCS_SELECT_QUEUE0 |
2126 TXCS_QUEUE0S |
2127 TXCS_ENABLE);
95252236 2128
49d70c48
JP		 2129 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2130 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
95252236
GFT		 2131 jme_stop_queue_if_full(jme);
2132
2133 return NETDEV_TX_OK;
2134}
2135
8b53abae
GFT		 2136static void
2137jme_set_unicastaddr(struct net_device *netdev)
2138{
2139 struct jme_adapter *jme = netdev_priv(netdev);
2140 u32 val;
2141
2142 val = (netdev->dev_addr[3] & 0xff) << 24 |
2143 (netdev->dev_addr[2] & 0xff) << 16 |
2144 (netdev->dev_addr[1] & 0xff) << 8 |
2145 (netdev->dev_addr[0] & 0xff);
2146 jwrite32(jme, JME_RXUMA_LO, val);
2147 val = (netdev->dev_addr[5] & 0xff) << 8 |
2148 (netdev->dev_addr[4] & 0xff);
2149 jwrite32(jme, JME_RXUMA_HI, val);
2150}
2151
95252236
GFT		 2152static int
2153jme_set_macaddr(struct net_device *netdev, void *p)
2154{
2155 struct jme_adapter *jme = netdev_priv(netdev);
2156 struct sockaddr *addr = p;
95252236
GFT		 2157
2158 if (netif_running(netdev))
2159 return -EBUSY;
2160
2161 spin_lock_bh(&jme->macaddr_lock);
2162 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
8b53abae 2163 jme_set_unicastaddr(netdev);
95252236
GFT		 2164 spin_unlock_bh(&jme->macaddr_lock);
2165
2166 return 0;
2167}
2168
2169static void
2170jme_set_multi(struct net_device *netdev)
2171{
2172 struct jme_adapter *jme = netdev_priv(netdev);
2173 u32 mc_hash[2] = {};
95252236
GFT		 2174
2175 spin_lock_bh(&jme->rxmcs_lock);
2176
2177 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2178
2179 if (netdev->flags & IFF_PROMISC) {
2180 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2181 } else if (netdev->flags & IFF_ALLMULTI) {
2182 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2183 } else if (netdev->flags & IFF_MULTICAST) {
22bedad3 2184 struct netdev_hw_addr *ha;
95252236
GFT		 2185 int bit_nr;
2186
2187 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
22bedad3
JP		 2188 netdev_for_each_mc_addr(ha, netdev) {
2189 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
95252236
GFT		 2190 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2191 }
2192
2193 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2194 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2195 }
2196
2197 wmb();
2198 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2199
2200 spin_unlock_bh(&jme->rxmcs_lock);
2201}
2202
2203static int
2204jme_change_mtu(struct net_device *netdev, int new_mtu)
2205{
2206 struct jme_adapter *jme = netdev_priv(netdev);
2207
2208 if (new_mtu == jme->old_mtu)
2209 return 0;
2210
2211 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2212 ((new_mtu) < IPV6_MIN_MTU))
2213 return -EINVAL;
2214
2215 if (new_mtu > 4000) {
2216 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2217 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2218 jme_restart_rx_engine(jme);
2219 } else {
2220 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2221 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2222 jme_restart_rx_engine(jme);
2223 }
2224
95252236 2225 netdev->mtu = new_mtu;
d7b57654
MM		 2226 netdev_update_features(netdev);
2227
95252236
GFT		 2228 jme_reset_link(jme);
2229
2230 return 0;
2231}
2232
2233static void
2234jme_tx_timeout(struct net_device *netdev)
2235{
2236 struct jme_adapter *jme = netdev_priv(netdev);
2237
2238 jme->phylink = 0;
2239 jme_reset_phy_processor(jme);
2240 if (test_bit(JME_FLAG_SSET, &jme->flags))
2241 jme_set_settings(netdev, &jme->old_ecmd);
2242
2243 /*
2244 * Force to Reset the link again
2245 */
2246 jme_reset_link(jme);
2247}
2248
bf5e5360
GFT		 2249static inline void jme_pause_rx(struct jme_adapter *jme)
2250{
2251 atomic_dec(&jme->link_changing);
2252
2253 jme_set_rx_pcc(jme, PCC_OFF);
2254 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2255 JME_NAPI_DISABLE(jme);
2256 } else {
2257 tasklet_disable(&jme->rxclean_task);
2258 tasklet_disable(&jme->rxempty_task);
2259 }
2260}
2261
2262static inline void jme_resume_rx(struct jme_adapter *jme)
2263{
2264 struct dynpcc_info *dpi = &(jme->dpi);
2265
2266 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2267 JME_NAPI_ENABLE(jme);
2268 } else {
2269 tasklet_hi_enable(&jme->rxclean_task);
2270 tasklet_hi_enable(&jme->rxempty_task);
2271 }
2272 dpi->cur = PCC_P1;
2273 dpi->attempt = PCC_P1;
2274 dpi->cnt = 0;
2275 jme_set_rx_pcc(jme, PCC_P1);
2276
2277 atomic_inc(&jme->link_changing);
2278}
2279
95252236
GFT		 2280static void
2281jme_get_drvinfo(struct net_device *netdev,
2282 struct ethtool_drvinfo *info)
2283{
2284 struct jme_adapter *jme = netdev_priv(netdev);
2285
2286 strcpy(info->driver, DRV_NAME);
2287 strcpy(info->version, DRV_VERSION);
2288 strcpy(info->bus_info, pci_name(jme->pdev));
2289}
2290
2291static int
2292jme_get_regs_len(struct net_device *netdev)
2293{
2294 return JME_REG_LEN;
2295}
2296
2297static void
2298mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2299{
2300 int i;
2301
2302 for (i = 0 ; i < len ; i += 4)
2303 p[i >> 2] = jread32(jme, reg + i);
2304}
2305
2306static void
2307mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2308{
2309 int i;
2310 u16 *p16 = (u16 *)p;
2311
2312 for (i = 0 ; i < reg_nr ; ++i)
2313 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2314}
2315
2316static void
2317jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2318{
2319 struct jme_adapter *jme = netdev_priv(netdev);
2320 u32 *p32 = (u32 *)p;
2321
2322 memset(p, 0xFF, JME_REG_LEN);
2323
2324 regs->version = 1;
2325 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2326
2327 p32 += 0x100 >> 2;
2328 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2329
2330 p32 += 0x100 >> 2;
2331 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2332
2333 p32 += 0x100 >> 2;
2334 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2335
2336 p32 += 0x100 >> 2;
2337 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2338}
2339
2340static int
2341jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2342{
2343 struct jme_adapter *jme = netdev_priv(netdev);
2344
2345 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2346 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2347
2348 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2349 ecmd->use_adaptive_rx_coalesce = false;
2350 ecmd->rx_coalesce_usecs = 0;
2351 ecmd->rx_max_coalesced_frames = 0;
2352 return 0;
2353 }
2354
2355 ecmd->use_adaptive_rx_coalesce = true;
2356
2357 switch (jme->dpi.cur) {
2358 case PCC_P1:
2359 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2360 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2361 break;
2362 case PCC_P2:
2363 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2364 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2365 break;
2366 case PCC_P3:
2367 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2368 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2369 break;
2370 default:
2371 break;
2372 }
2373
2374 return 0;
2375}
2376
2377static int
2378jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2379{
2380 struct jme_adapter *jme = netdev_priv(netdev);
2381 struct dynpcc_info *dpi = &(jme->dpi);
2382
2383 if (netif_running(netdev))
2384 return -EBUSY;
2385
8e95a202
JP		 2386 if (ecmd->use_adaptive_rx_coalesce &&
2387 test_bit(JME_FLAG_POLL, &jme->flags)) {
95252236
GFT		 2388 clear_bit(JME_FLAG_POLL, &jme->flags);
2389 jme->jme_rx = netif_rx;
95252236
GFT		 2390 dpi->cur = PCC_P1;
2391 dpi->attempt = PCC_P1;
2392 dpi->cnt = 0;
2393 jme_set_rx_pcc(jme, PCC_P1);
2394 jme_interrupt_mode(jme);
8e95a202
JP		 2395 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2396 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
95252236
GFT		 2397 set_bit(JME_FLAG_POLL, &jme->flags);
2398 jme->jme_rx = netif_receive_skb;
95252236
GFT		 2399 jme_interrupt_mode(jme);
2400 }
2401
2402 return 0;
2403}
2404
2405static void
2406jme_get_pauseparam(struct net_device *netdev,
2407 struct ethtool_pauseparam *ecmd)
2408{
2409 struct jme_adapter *jme = netdev_priv(netdev);
2410 u32 val;
2411
2412 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2413 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2414
2415 spin_lock_bh(&jme->phy_lock);
2416 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2417 spin_unlock_bh(&jme->phy_lock);
2418
2419 ecmd->autoneg =
2420 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2421}
2422
2423static int
2424jme_set_pauseparam(struct net_device *netdev,
2425 struct ethtool_pauseparam *ecmd)
2426{
2427 struct jme_adapter *jme = netdev_priv(netdev);
2428 u32 val;
2429
2430 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2431 (ecmd->tx_pause != 0)) {
2432
2433 if (ecmd->tx_pause)
2434 jme->reg_txpfc |= TXPFC_PF_EN;
2435 else
2436 jme->reg_txpfc &= ~TXPFC_PF_EN;
2437
2438 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2439 }
2440
2441 spin_lock_bh(&jme->rxmcs_lock);
2442 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2443 (ecmd->rx_pause != 0)) {
2444
2445 if (ecmd->rx_pause)
2446 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2447 else
2448 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2449
2450 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2451 }
2452 spin_unlock_bh(&jme->rxmcs_lock);
2453
2454 spin_lock_bh(&jme->phy_lock);
2455 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2456 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2457 (ecmd->autoneg != 0)) {
2458
2459 if (ecmd->autoneg)
2460 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2461 else
2462 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2463
2464 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2465 MII_ADVERTISE, val);
2466 }
2467 spin_unlock_bh(&jme->phy_lock);
2468
2469 return 0;
2470}
2471
2472static void
2473jme_get_wol(struct net_device *netdev,
2474 struct ethtool_wolinfo *wol)
2475{
2476 struct jme_adapter *jme = netdev_priv(netdev);
2477
2478 wol->supported = WAKE_MAGIC | WAKE_PHY;
2479
2480 wol->wolopts = 0;
2481
2482 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2483 wol->wolopts |= WAKE_PHY;
2484
2485 if (jme->reg_pmcs & PMCS_MFEN)
2486 wol->wolopts |= WAKE_MAGIC;
2487
2488}
2489
2490static int
2491jme_set_wol(struct net_device *netdev,
2492 struct ethtool_wolinfo *wol)
2493{
2494 struct jme_adapter *jme = netdev_priv(netdev);
2495
2496 if (wol->wolopts & (WAKE_MAGICSECURE |
2497 WAKE_UCAST |
2498 WAKE_MCAST |
2499 WAKE_BCAST |
2500 WAKE_ARP))
2501 return -EOPNOTSUPP;
2502
2503 jme->reg_pmcs = 0;
2504
2505 if (wol->wolopts & WAKE_PHY)
2506 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2507
2508 if (wol->wolopts & WAKE_MAGIC)
2509 jme->reg_pmcs |= PMCS_MFEN;
2510
2511 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
bc057e03 2512 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
f4e5bd4f 2513
95252236
GFT		 2514 return 0;
2515}
2516
2517static int
2518jme_get_settings(struct net_device *netdev,
2519 struct ethtool_cmd *ecmd)
2520{
2521 struct jme_adapter *jme = netdev_priv(netdev);
2522 int rc;
2523
2524 spin_lock_bh(&jme->phy_lock);
2525 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2526 spin_unlock_bh(&jme->phy_lock);
2527 return rc;
2528}
2529
2530static int
2531jme_set_settings(struct net_device *netdev,
2532 struct ethtool_cmd *ecmd)
2533{
2534 struct jme_adapter *jme = netdev_priv(netdev);
2535 int rc, fdc = 0;
2536
25db0338
DD		 2537 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2538 && ecmd->autoneg != AUTONEG_ENABLE)
95252236
GFT		 2539 return -EINVAL;
2540
3ee94018
GFT		 2541 /*
2542 * Check If user changed duplex only while force_media.
2543 * Hardware would not generate link change interrupt.
2544 */
95252236
GFT		 2545 if (jme->mii_if.force_media &&
2546 ecmd->autoneg != AUTONEG_ENABLE &&
2547 (jme->mii_if.full_duplex != ecmd->duplex))
2548 fdc = 1;
2549
2550 spin_lock_bh(&jme->phy_lock);
2551 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2552 spin_unlock_bh(&jme->phy_lock);
2553
95252236 2554 if (!rc) {
3ee94018
GFT		 2555 if (fdc)
2556 jme_reset_link(jme);
95252236 2557 jme->old_ecmd = *ecmd;
334fbbb7
GFT		 2558 set_bit(JME_FLAG_SSET, &jme->flags);
2559 }
2560
2561 return rc;
2562}
2563
2564static int
2565jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2566{
2567 int rc;
2568 struct jme_adapter *jme = netdev_priv(netdev);
2569 struct mii_ioctl_data *mii_data = if_mii(rq);
2570 unsigned int duplex_chg;
2571
2572 if (cmd == SIOCSMIIREG) {
2573 u16 val = mii_data->val_in;
2574 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2575 (val & BMCR_SPEED1000))
2576 return -EINVAL;
2577 }
2578
2579 spin_lock_bh(&jme->phy_lock);
2580 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2581 spin_unlock_bh(&jme->phy_lock);
2582
2583 if (!rc && (cmd == SIOCSMIIREG)) {
2584 if (duplex_chg)
2585 jme_reset_link(jme);
2586 jme_get_settings(netdev, &jme->old_ecmd);
2587 set_bit(JME_FLAG_SSET, &jme->flags);
95252236
GFT		 2588 }
2589
2590 return rc;
2591}
2592
2593static u32
2594jme_get_link(struct net_device *netdev)
2595{
2596 struct jme_adapter *jme = netdev_priv(netdev);
2597 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2598}
2599
2600static u32
2601jme_get_msglevel(struct net_device *netdev)
2602{
2603 struct jme_adapter *jme = netdev_priv(netdev);
2604 return jme->msg_enable;
2605}
2606
2607static void
2608jme_set_msglevel(struct net_device *netdev, u32 value)
2609{
2610 struct jme_adapter *jme = netdev_priv(netdev);
2611 jme->msg_enable = value;
2612}
2613
2614static u32
d7b57654 2615jme_fix_features(struct net_device *netdev, u32 features)
95252236 2616{
d7b57654
MM		 2617 if (netdev->mtu > 1900)
2618 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2619 return features;
95252236
GFT		 2620}
2621
2622static int
d7b57654 2623jme_set_features(struct net_device *netdev, u32 features)
95252236
GFT		 2624{
2625 struct jme_adapter *jme = netdev_priv(netdev);
2626
2627 spin_lock_bh(&jme->rxmcs_lock);
d7b57654 2628 if (features & NETIF_F_RXCSUM)
95252236
GFT		 2629 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2630 else
2631 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2632 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2633 spin_unlock_bh(&jme->rxmcs_lock);
2634
2635 return 0;
2636}
2637
95252236
GFT		 2638static int
2639jme_nway_reset(struct net_device *netdev)
2640{
2641 struct jme_adapter *jme = netdev_priv(netdev);
2642 jme_restart_an(jme);
2643 return 0;
2644}
2645
2646static u8
2647jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2648{
2649 u32 val;
2650 int to;
2651
2652 val = jread32(jme, JME_SMBCSR);
2653 to = JME_SMB_BUSY_TIMEOUT;
2654 while ((val & SMBCSR_BUSY) && --to) {
2655 msleep(1);
2656 val = jread32(jme, JME_SMBCSR);
2657 }
2658 if (!to) {
49d70c48 2659 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
95252236
GFT		 2660 return 0xFF;
2661 }
2662
2663 jwrite32(jme, JME_SMBINTF,
2664 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2665 SMBINTF_HWRWN_READ |
2666 SMBINTF_HWCMD);
2667
2668 val = jread32(jme, JME_SMBINTF);
2669 to = JME_SMB_BUSY_TIMEOUT;
2670 while ((val & SMBINTF_HWCMD) && --to) {
2671 msleep(1);
2672 val = jread32(jme, JME_SMBINTF);
2673 }
2674 if (!to) {
49d70c48 2675 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
95252236
GFT		 2676 return 0xFF;
2677 }
2678
2679 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2680}
2681
2682static void
2683jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2684{
2685 u32 val;
2686 int to;
2687
2688 val = jread32(jme, JME_SMBCSR);
2689 to = JME_SMB_BUSY_TIMEOUT;
2690 while ((val & SMBCSR_BUSY) && --to) {
2691 msleep(1);
2692 val = jread32(jme, JME_SMBCSR);
2693 }
2694 if (!to) {
49d70c48 2695 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
95252236
GFT		 2696 return;
2697 }
2698
2699 jwrite32(jme, JME_SMBINTF,
2700 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2701 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2702 SMBINTF_HWRWN_WRITE |
2703 SMBINTF_HWCMD);
2704
2705 val = jread32(jme, JME_SMBINTF);
2706 to = JME_SMB_BUSY_TIMEOUT;
2707 while ((val & SMBINTF_HWCMD) && --to) {
2708 msleep(1);
2709 val = jread32(jme, JME_SMBINTF);
2710 }
2711 if (!to) {
49d70c48 2712 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
95252236
GFT		 2713 return;
2714 }
2715
2716 mdelay(2);
2717}
2718
2719static int
2720jme_get_eeprom_len(struct net_device *netdev)
2721{
2722 struct jme_adapter *jme = netdev_priv(netdev);
2723 u32 val;
2724 val = jread32(jme, JME_SMBCSR);
2725 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2726}
2727
2728static int
2729jme_get_eeprom(struct net_device *netdev,
2730 struct ethtool_eeprom *eeprom, u8 *data)
2731{
2732 struct jme_adapter *jme = netdev_priv(netdev);
2733 int i, offset = eeprom->offset, len = eeprom->len;
2734
2735 /*
2736 * ethtool will check the boundary for us
2737 */
2738 eeprom->magic = JME_EEPROM_MAGIC;
2739 for (i = 0 ; i < len ; ++i)
2740 data[i] = jme_smb_read(jme, i + offset);
2741
2742 return 0;
2743}
2744
2745static int
2746jme_set_eeprom(struct net_device *netdev,
2747 struct ethtool_eeprom *eeprom, u8 *data)
2748{
2749 struct jme_adapter *jme = netdev_priv(netdev);
2750 int i, offset = eeprom->offset, len = eeprom->len;
2751
2752 if (eeprom->magic != JME_EEPROM_MAGIC)
2753 return -EINVAL;
2754
2755 /*
2756 * ethtool will check the boundary for us
2757 */
2758 for (i = 0 ; i < len ; ++i)
2759 jme_smb_write(jme, i + offset, data[i]);
2760
2761 return 0;
2762}
2763
2764static const struct ethtool_ops jme_ethtool_ops = {
2765 .get_drvinfo = jme_get_drvinfo,
2766 .get_regs_len = jme_get_regs_len,
2767 .get_regs = jme_get_regs,
2768 .get_coalesce = jme_get_coalesce,
2769 .set_coalesce = jme_set_coalesce,
2770 .get_pauseparam = jme_get_pauseparam,
2771 .set_pauseparam = jme_set_pauseparam,
2772 .get_wol = jme_get_wol,
2773 .set_wol = jme_set_wol,
2774 .get_settings = jme_get_settings,
2775 .set_settings = jme_set_settings,
2776 .get_link = jme_get_link,
2777 .get_msglevel = jme_get_msglevel,
2778 .set_msglevel = jme_set_msglevel,
95252236
GFT		 2779 .nway_reset = jme_nway_reset,
2780 .get_eeprom_len = jme_get_eeprom_len,
2781 .get_eeprom = jme_get_eeprom,
2782 .set_eeprom = jme_set_eeprom,
2783};
2784
2785static int
2786jme_pci_dma64(struct pci_dev *pdev)
2787{
814c01dc 2788 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
e930438c
YH		 2789 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2790 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
814c01dc
GFT		 2791 return 1;
2792
2793 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
e930438c
YH		 2794 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2795 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
814c01dc
GFT		 2796 return 1;
2797
284901a9
YH		 2798 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2799 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
95252236
GFT		 2800 return 0;
2801
2802 return -1;
2803}
2804
2805static inline void
2806jme_phy_init(struct jme_adapter *jme)
2807{
2808 u16 reg26;
2809
2810 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2811 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2812}
2813
2814static inline void
2815jme_check_hw_ver(struct jme_adapter *jme)
2816{
2817 u32 chipmode;
2818
2819 chipmode = jread32(jme, JME_CHIPMODE);
2820
2821 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2822 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
19d96017
GFT		 2823 jme->chip_main_rev = jme->chiprev & 0xF;
2824 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
95252236
GFT		 2825}
2826
e48714ba
SH		 2827static const struct net_device_ops jme_netdev_ops = {
2828 .ndo_open = jme_open,
2829 .ndo_stop = jme_close,
2830 .ndo_validate_addr = eth_validate_addr,
334fbbb7 2831 .ndo_do_ioctl = jme_ioctl,
e48714ba
SH		 2832 .ndo_start_xmit = jme_start_xmit,
2833 .ndo_set_mac_address = jme_set_macaddr,
2834 .ndo_set_multicast_list = jme_set_multi,
2835 .ndo_change_mtu = jme_change_mtu,
2836 .ndo_tx_timeout = jme_tx_timeout,
d7b57654
MM		 2837 .ndo_fix_features = jme_fix_features,
2838 .ndo_set_features = jme_set_features,
e48714ba
SH		 2839};
2840
95252236
GFT		 2841static int __devinit
2842jme_init_one(struct pci_dev *pdev,
2843 const struct pci_device_id *ent)
2844{
2845 int rc = 0, using_dac, i;
2846 struct net_device *netdev;
2847 struct jme_adapter *jme;
2848 u16 bmcr, bmsr;
2849 u32 apmc;
2850
2851 /*
2852 * set up PCI device basics
2853 */
2854 rc = pci_enable_device(pdev);
2855 if (rc) {
49d70c48 2856 pr_err("Cannot enable PCI device\n");
95252236
GFT		 2857 goto err_out;
2858 }
2859
2860 using_dac = jme_pci_dma64(pdev);
2861 if (using_dac < 0) {
49d70c48 2862 pr_err("Cannot set PCI DMA Mask\n");
95252236
GFT		 2863 rc = -EIO;
2864 goto err_out_disable_pdev;
2865 }
2866
2867 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
49d70c48 2868 pr_err("No PCI resource region found\n");
95252236
GFT		 2869 rc = -ENOMEM;
2870 goto err_out_disable_pdev;
2871 }
2872
2873 rc = pci_request_regions(pdev, DRV_NAME);
2874 if (rc) {
49d70c48 2875 pr_err("Cannot obtain PCI resource region\n");
95252236
GFT		 2876 goto err_out_disable_pdev;
2877 }
2878
2879 pci_set_master(pdev);
2880
2881 /*
2882 * alloc and init net device
2883 */
2884 netdev = alloc_etherdev(sizeof(*jme));
2885 if (!netdev) {
49d70c48 2886 pr_err("Cannot allocate netdev structure\n");
95252236
GFT		 2887 rc = -ENOMEM;
2888 goto err_out_release_regions;
2889 }
e48714ba 2890 netdev->netdev_ops = &jme_netdev_ops;
95252236 2891 netdev->ethtool_ops = &jme_ethtool_ops;
95252236 2892 netdev->watchdog_timeo = TX_TIMEOUT;
d7b57654
MM		 2893 netdev->hw_features = NETIF_F_IP_CSUM |
2894 NETIF_F_IPV6_CSUM |
2895 NETIF_F_SG |
2896 NETIF_F_TSO |
2897 NETIF_F_TSO6 |
2898 NETIF_F_RXCSUM;
79032644
MM		 2899 netdev->features = NETIF_F_IP_CSUM |
2900 NETIF_F_IPV6_CSUM |
95252236
GFT		 2901 NETIF_F_SG |
2902 NETIF_F_TSO |
2903 NETIF_F_TSO6 |
2904 NETIF_F_HW_VLAN_TX |
2905 NETIF_F_HW_VLAN_RX;
2906 if (using_dac)
2907 netdev->features |= NETIF_F_HIGHDMA;
2908
2909 SET_NETDEV_DEV(netdev, &pdev->dev);
2910 pci_set_drvdata(pdev, netdev);
2911
2912 /*
2913 * init adapter info
2914 */
2915 jme = netdev_priv(netdev);
2916 jme->pdev = pdev;
2917 jme->dev = netdev;
2918 jme->jme_rx = netif_rx;
95252236
GFT		 2919 jme->old_mtu = netdev->mtu = 1500;
2920 jme->phylink = 0;
2921 jme->tx_ring_size = 1 << 10;
2922 jme->tx_ring_mask = jme->tx_ring_size - 1;
2923 jme->tx_wake_threshold = 1 << 9;
2924 jme->rx_ring_size = 1 << 9;
2925 jme->rx_ring_mask = jme->rx_ring_size - 1;
2926 jme->msg_enable = JME_DEF_MSG_ENABLE;
2927 jme->regs = ioremap(pci_resource_start(pdev, 0),
2928 pci_resource_len(pdev, 0));
2929 if (!(jme->regs)) {
49d70c48 2930 pr_err("Mapping PCI resource region error\n");
95252236
GFT		 2931 rc = -ENOMEM;
2932 goto err_out_free_netdev;
2933 }
95252236
GFT		 2934
2935 if (no_pseudohp) {
2936 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2937 jwrite32(jme, JME_APMC, apmc);
2938 } else if (force_pseudohp) {
2939 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2940 jwrite32(jme, JME_APMC, apmc);
2941 }
2942
2943 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2944
2945 spin_lock_init(&jme->phy_lock);
2946 spin_lock_init(&jme->macaddr_lock);
2947 spin_lock_init(&jme->rxmcs_lock);
2948
2949 atomic_set(&jme->link_changing, 1);
2950 atomic_set(&jme->rx_cleaning, 1);
2951 atomic_set(&jme->tx_cleaning, 1);
2952 atomic_set(&jme->rx_empty, 1);
2953
2954 tasklet_init(&jme->pcc_task,
164165da 2955 jme_pcc_tasklet,
95252236
GFT		 2956 (unsigned long) jme);
2957 tasklet_init(&jme->linkch_task,
164165da 2958 jme_link_change_tasklet,
95252236
GFT		 2959 (unsigned long) jme);
2960 tasklet_init(&jme->txclean_task,
164165da 2961 jme_tx_clean_tasklet,
95252236
GFT		 2962 (unsigned long) jme);
2963 tasklet_init(&jme->rxclean_task,
164165da 2964 jme_rx_clean_tasklet,
95252236
GFT		 2965 (unsigned long) jme);
2966 tasklet_init(&jme->rxempty_task,
164165da 2967 jme_rx_empty_tasklet,
95252236 2968 (unsigned long) jme);
38ed0c21 2969 tasklet_disable_nosync(&jme->linkch_task);
95252236
GFT		 2970 tasklet_disable_nosync(&jme->txclean_task);
2971 tasklet_disable_nosync(&jme->rxclean_task);
2972 tasklet_disable_nosync(&jme->rxempty_task);
2973 jme->dpi.cur = PCC_P1;
2974
2975 jme->reg_ghc = 0;
2976 jme->reg_rxcs = RXCS_DEFAULT;
2977 jme->reg_rxmcs = RXMCS_DEFAULT;
2978 jme->reg_txpfc = 0;
2979 jme->reg_pmcs = PMCS_MFEN;
854a2e7c 2980 jme->reg_gpreg1 = GPREG1_DEFAULT;
d7b57654
MM		 2981
2982 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
2983 netdev->features |= NETIF_F_RXCSUM;
95252236
GFT		 2984
2985 /*
2986 * Get Max Read Req Size from PCI Config Space
2987 */
2988 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2989 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2990 switch (jme->mrrs) {
2991 case MRRS_128B:
2992 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2993 break;
2994 case MRRS_256B:
2995 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2996 break;
2997 default:
2998 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2999 break;
ee289b64 3000 }
95252236
GFT		 3001
3002 /*
3003 * Must check before reset_mac_processor
3004 */
3005 jme_check_hw_ver(jme);
3006 jme->mii_if.dev = netdev;
3007 if (jme->fpgaver) {
3008 jme->mii_if.phy_id = 0;
3009 for (i = 1 ; i < 32 ; ++i) {
3010 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3011 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3012 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3013 jme->mii_if.phy_id = i;
3014 break;
3015 }
3016 }
3017
3018 if (!jme->mii_if.phy_id) {
3019 rc = -EIO;
49d70c48
JP		 3020 pr_err("Can not find phy_id\n");
3021 goto err_out_unmap;
95252236
GFT		 3022 }
3023
3024 jme->reg_ghc |= GHC_LINK_POLL;
3025 } else {
3026 jme->mii_if.phy_id = 1;
3027 }
3028 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3029 jme->mii_if.supports_gmii = true;
3030 else
3031 jme->mii_if.supports_gmii = false;
334fbbb7
GFT		 3032 jme->mii_if.phy_id_mask = 0x1F;
3033 jme->mii_if.reg_num_mask = 0x1F;
95252236
GFT		 3034 jme->mii_if.mdio_read = jme_mdio_read;
3035 jme->mii_if.mdio_write = jme_mdio_write;
3036
3037 jme_clear_pm(jme);
bc057e03
GFT		 3038 pci_set_power_state(jme->pdev, PCI_D0);
3039 device_set_wakeup_enable(&pdev->dev, true);
3040
51754572 3041 jme_set_phyfifo_5level(jme);
ff938e43 3042 jme->pcirev = pdev->revision;
95252236
GFT		 3043 if (!jme->fpgaver)
3044 jme_phy_init(jme);
3045 jme_phy_off(jme);
3046
3047 /*
3048 * Reset MAC processor and reload EEPROM for MAC Address
3049 */
3050 jme_reset_mac_processor(jme);
3051 rc = jme_reload_eeprom(jme);
3052 if (rc) {
49d70c48 3053 pr_err("Reload eeprom for reading MAC Address error\n");
d1dfa1d1 3054 goto err_out_unmap;
95252236
GFT		 3055 }
3056 jme_load_macaddr(netdev);
3057
3058 /*
3059 * Tell stack that we are not ready to work until open()
3060 */
3061 netif_carrier_off(netdev);
95252236 3062
95252236
GFT		 3063 rc = register_netdev(netdev);
3064 if (rc) {
49d70c48 3065 pr_err("Cannot register net device\n");
d1dfa1d1 3066 goto err_out_unmap;
95252236
GFT		 3067 }
3068
19d96017 3069 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
f8502ce4
JP		 3070 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3071 "JMC250 Gigabit Ethernet" :
3072 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3073 "JMC260 Fast Ethernet" : "Unknown",
3074 (jme->fpgaver != 0) ? " (FPGA)" : "",
3075 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
19d96017 3076 jme->pcirev, netdev->dev_addr);
95252236
GFT		 3077
3078 return 0;
3079
95252236
GFT		 3080err_out_unmap:
3081 iounmap(jme->regs);
3082err_out_free_netdev:
3083 pci_set_drvdata(pdev, NULL);
3084 free_netdev(netdev);
3085err_out_release_regions:
3086 pci_release_regions(pdev);
3087err_out_disable_pdev:
3088 pci_disable_device(pdev);
3089err_out:
3090 return rc;
3091}
3092
3093static void __devexit
3094jme_remove_one(struct pci_dev *pdev)
3095{
3096 struct net_device *netdev = pci_get_drvdata(pdev);
3097 struct jme_adapter *jme = netdev_priv(netdev);
3098
3099 unregister_netdev(netdev);
95252236
GFT		 3100 iounmap(jme->regs);
3101 pci_set_drvdata(pdev, NULL);
3102 free_netdev(netdev);
3103 pci_release_regions(pdev);
3104 pci_disable_device(pdev);
3105
3106}
3107
1c557819
GFT		 3108static void
3109jme_shutdown(struct pci_dev *pdev)
3110{
3111 struct net_device *netdev = pci_get_drvdata(pdev);
3112 struct jme_adapter *jme = netdev_priv(netdev);
3113
3114 jme_powersave_phy(jme);
3115 pci_pme_active(pdev, true);
3116}
3117
aab6fb82 3118#ifdef CONFIG_PM_SLEEP
bc057e03
GFT		 3119static int
3120jme_suspend(struct device *dev)
95252236 3121{
f4e5bd4f 3122 struct pci_dev *pdev = to_pci_dev(dev);
95252236
GFT		 3123 struct net_device *netdev = pci_get_drvdata(pdev);
3124 struct jme_adapter *jme = netdev_priv(netdev);
3125
3126 atomic_dec(&jme->link_changing);
3127
3128 netif_device_detach(netdev);
3129 netif_stop_queue(netdev);
3130 jme_stop_irq(jme);
3131
3132 tasklet_disable(&jme->txclean_task);
3133 tasklet_disable(&jme->rxclean_task);
3134 tasklet_disable(&jme->rxempty_task);
3135
95252236
GFT		 3136 if (netif_carrier_ok(netdev)) {
3137 if (test_bit(JME_FLAG_POLL, &jme->flags))
3138 jme_polling_mode(jme);
3139
3140 jme_stop_pcc_timer(jme);
95252236
GFT		 3141 jme_disable_rx_engine(jme);
3142 jme_disable_tx_engine(jme);
3143 jme_reset_mac_processor(jme);
3144 jme_free_rx_resources(jme);
3145 jme_free_tx_resources(jme);
3146 netif_carrier_off(netdev);
3147 jme->phylink = 0;
3148 }
3149
3150 tasklet_enable(&jme->txclean_task);
3151 tasklet_hi_enable(&jme->rxclean_task);
3152 tasklet_hi_enable(&jme->rxempty_task);
3153
1c557819 3154 jme_powersave_phy(jme);
95252236
GFT		 3155
3156 return 0;
3157}
3158
bc057e03
GFT		 3159static int
3160jme_resume(struct device *dev)
95252236 3161{
f4e5bd4f 3162 struct pci_dev *pdev = to_pci_dev(dev);
95252236
GFT		 3163 struct net_device *netdev = pci_get_drvdata(pdev);
3164 struct jme_adapter *jme = netdev_priv(netdev);
3165
bc057e03 3166 jme_clear_pm(jme);
4872b11f
GFT		 3167 jme_phy_on(jme);
3168 if (test_bit(JME_FLAG_SSET, &jme->flags))
95252236 3169 jme_set_settings(netdev, &jme->old_ecmd);
4872b11f 3170 else
95252236
GFT		 3171 jme_reset_phy_processor(jme);
3172
95252236
GFT		 3173 jme_start_irq(jme);
3174 netif_device_attach(netdev);
3175
3176 atomic_inc(&jme->link_changing);
3177
3178 jme_reset_link(jme);
3179
3180 return 0;
3181}
f4e5bd4f
RW		 3182
3183static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3184#define JME_PM_OPS (&jme_pm_ops)
3185
3186#else
3187
3188#define JME_PM_OPS NULL
724f8805 3189#endif
95252236 3190
a3aa1884 3191static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
95252236
GFT		 3192 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3193 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3194 { }
3195};
3196
3197static struct pci_driver jme_driver = {
3198 .name = DRV_NAME,
3199 .id_table = jme_pci_tbl,
3200 .probe = jme_init_one,
3201 .remove = __devexit_p(jme_remove_one),
1c557819 3202 .shutdown = jme_shutdown,
f4e5bd4f 3203 .driver.pm = JME_PM_OPS,
95252236
GFT		 3204};
3205
3206static int __init
3207jme_init_module(void)
3208{
49d70c48 3209 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
95252236
GFT		 3210 return pci_register_driver(&jme_driver);
3211}
3212
3213static void __exit
3214jme_cleanup_module(void)
3215{
3216 pci_unregister_driver(&jme_driver);
3217}
3218
3219module_init(jme_init_module);
3220module_exit(jme_cleanup_module);
3221
3222MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3223MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3224MODULE_LICENSE("GPL");
3225MODULE_VERSION(DRV_VERSION);
3226MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3227
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