]>
Commit | Line | Data |
---|---|---|
3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
cb8011ad | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
cb8011ad | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | * | |
29 | * | |
30 | * Source file for NIC routines to access the Phantom hardware | |
31 | * | |
32 | */ | |
33 | ||
34 | #include "netxen_nic.h" | |
35 | #include "netxen_nic_hw.h" | |
3176ff3e | 36 | #define DEFINE_GLOBAL_RECV_CRB |
3d396eb1 AK |
37 | #include "netxen_nic_phan_reg.h" |
38 | ||
3176ff3e | 39 | |
c9bdd4b5 ACM |
40 | #include <net/ip.h> |
41 | ||
3176ff3e MT |
42 | struct netxen_recv_crb recv_crb_registers[] = { |
43 | /* | |
44 | * Instance 0. | |
45 | */ | |
46 | { | |
47 | /* rcv_desc_crb: */ | |
48 | { | |
49 | { | |
50 | /* crb_rcv_producer_offset: */ | |
51 | NETXEN_NIC_REG(0x100), | |
52 | /* crb_rcv_consumer_offset: */ | |
53 | NETXEN_NIC_REG(0x104), | |
54 | /* crb_gloablrcv_ring: */ | |
55 | NETXEN_NIC_REG(0x108), | |
56 | /* crb_rcv_ring_size */ | |
57 | NETXEN_NIC_REG(0x10c), | |
58 | ||
59 | }, | |
60 | /* Jumbo frames */ | |
61 | { | |
62 | /* crb_rcv_producer_offset: */ | |
63 | NETXEN_NIC_REG(0x110), | |
64 | /* crb_rcv_consumer_offset: */ | |
65 | NETXEN_NIC_REG(0x114), | |
66 | /* crb_gloablrcv_ring: */ | |
67 | NETXEN_NIC_REG(0x118), | |
68 | /* crb_rcv_ring_size */ | |
69 | NETXEN_NIC_REG(0x11c), | |
70 | }, | |
71 | /* LRO */ | |
72 | { | |
73 | /* crb_rcv_producer_offset: */ | |
74 | NETXEN_NIC_REG(0x120), | |
75 | /* crb_rcv_consumer_offset: */ | |
76 | NETXEN_NIC_REG(0x124), | |
77 | /* crb_gloablrcv_ring: */ | |
78 | NETXEN_NIC_REG(0x128), | |
79 | /* crb_rcv_ring_size */ | |
80 | NETXEN_NIC_REG(0x12c), | |
81 | } | |
82 | }, | |
83 | /* crb_rcvstatus_ring: */ | |
84 | NETXEN_NIC_REG(0x130), | |
85 | /* crb_rcv_status_producer: */ | |
86 | NETXEN_NIC_REG(0x134), | |
87 | /* crb_rcv_status_consumer: */ | |
88 | NETXEN_NIC_REG(0x138), | |
89 | /* crb_rcvpeg_state: */ | |
90 | NETXEN_NIC_REG(0x13c), | |
91 | /* crb_status_ring_size */ | |
92 | NETXEN_NIC_REG(0x140), | |
93 | ||
94 | }, | |
95 | /* | |
96 | * Instance 1, | |
97 | */ | |
98 | { | |
99 | /* rcv_desc_crb: */ | |
100 | { | |
101 | { | |
102 | /* crb_rcv_producer_offset: */ | |
103 | NETXEN_NIC_REG(0x144), | |
104 | /* crb_rcv_consumer_offset: */ | |
105 | NETXEN_NIC_REG(0x148), | |
106 | /* crb_globalrcv_ring: */ | |
107 | NETXEN_NIC_REG(0x14c), | |
108 | /* crb_rcv_ring_size */ | |
109 | NETXEN_NIC_REG(0x150), | |
110 | ||
111 | }, | |
112 | /* Jumbo frames */ | |
113 | { | |
114 | /* crb_rcv_producer_offset: */ | |
115 | NETXEN_NIC_REG(0x154), | |
116 | /* crb_rcv_consumer_offset: */ | |
117 | NETXEN_NIC_REG(0x158), | |
118 | /* crb_globalrcv_ring: */ | |
119 | NETXEN_NIC_REG(0x15c), | |
120 | /* crb_rcv_ring_size */ | |
121 | NETXEN_NIC_REG(0x160), | |
122 | }, | |
123 | /* LRO */ | |
124 | { | |
125 | /* crb_rcv_producer_offset: */ | |
126 | NETXEN_NIC_REG(0x164), | |
127 | /* crb_rcv_consumer_offset: */ | |
128 | NETXEN_NIC_REG(0x168), | |
129 | /* crb_globalrcv_ring: */ | |
130 | NETXEN_NIC_REG(0x16c), | |
131 | /* crb_rcv_ring_size */ | |
132 | NETXEN_NIC_REG(0x170), | |
133 | } | |
134 | ||
135 | }, | |
136 | /* crb_rcvstatus_ring: */ | |
137 | NETXEN_NIC_REG(0x174), | |
138 | /* crb_rcv_status_producer: */ | |
139 | NETXEN_NIC_REG(0x178), | |
140 | /* crb_rcv_status_consumer: */ | |
141 | NETXEN_NIC_REG(0x17c), | |
142 | /* crb_rcvpeg_state: */ | |
143 | NETXEN_NIC_REG(0x180), | |
144 | /* crb_status_ring_size */ | |
145 | NETXEN_NIC_REG(0x184), | |
146 | ||
147 | }, | |
148 | }; | |
149 | ||
150 | u64 ctx_addr_sig_regs[][3] = { | |
151 | {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)}, | |
152 | {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)}, | |
153 | {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)}, | |
154 | {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)} | |
155 | }; | |
156 | ||
157 | ||
3d396eb1 AK |
158 | /* PCI Windowing for DDR regions. */ |
159 | ||
160 | #define ADDR_IN_RANGE(addr, low, high) \ | |
161 | (((addr) <= (high)) && ((addr) >= (low))) | |
162 | ||
163 | #define NETXEN_FLASH_BASE (BOOTLD_START) | |
164 | #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE) | |
ed25ffa1 | 165 | #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE |
cb8011ad | 166 | #define NETXEN_MIN_MTU 64 |
3d396eb1 AK |
167 | #define NETXEN_ETH_FCS_SIZE 4 |
168 | #define NETXEN_ENET_HEADER_SIZE 14 | |
cb8011ad | 169 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
3d396eb1 AK |
170 | #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4) |
171 | #define NETXEN_NIU_HDRSIZE (0x1 << 6) | |
172 | #define NETXEN_NIU_TLRSIZE (0x1 << 5) | |
173 | ||
cb8011ad AK |
174 | #define lower32(x) ((u32)((x) & 0xffffffff)) |
175 | #define upper32(x) \ | |
176 | ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff)) | |
177 | ||
178 | #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL | |
179 | #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL | |
180 | #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL | |
181 | #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL | |
182 | ||
183 | #define NETXEN_NIC_WINDOW_MARGIN 0x100000 | |
184 | ||
185 | unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter, | |
3d396eb1 AK |
186 | unsigned long long addr); |
187 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
188 | ||
189 | int netxen_nic_set_mac(struct net_device *netdev, void *p) | |
190 | { | |
3176ff3e | 191 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 AK |
192 | struct sockaddr *addr = p; |
193 | ||
194 | if (netif_running(netdev)) | |
195 | return -EBUSY; | |
196 | ||
197 | if (!is_valid_ether_addr(addr->sa_data)) | |
198 | return -EADDRNOTAVAIL; | |
199 | ||
200 | DPRINTK(INFO, "valid ether addr\n"); | |
201 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
202 | ||
80922fbc | 203 | if (adapter->macaddr_set) |
3176ff3e | 204 | adapter->macaddr_set(adapter, addr->sa_data); |
3d396eb1 AK |
205 | |
206 | return 0; | |
207 | } | |
208 | ||
209 | /* | |
210 | * netxen_nic_set_multi - Multicast | |
211 | */ | |
212 | void netxen_nic_set_multi(struct net_device *netdev) | |
213 | { | |
3176ff3e | 214 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 | 215 | struct dev_mc_list *mc_ptr; |
a608ab9c | 216 | __u32 netxen_mac_addr_cntl_data = 0; |
3d396eb1 AK |
217 | |
218 | mc_ptr = netdev->mc_list; | |
219 | if (netdev->flags & IFF_PROMISC) { | |
80922fbc AK |
220 | if (adapter->set_promisc) |
221 | adapter->set_promisc(adapter, | |
80922fbc | 222 | NETXEN_NIU_PROMISC_MODE); |
3d396eb1 | 223 | } else { |
80922fbc | 224 | if (adapter->unset_promisc && |
cb8011ad AK |
225 | adapter->ahw.boardcfg.board_type |
226 | != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) | |
80922fbc | 227 | adapter->unset_promisc(adapter, |
80922fbc | 228 | NETXEN_NIU_NON_PROMISC_MODE); |
3d396eb1 AK |
229 | } |
230 | if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { | |
231 | netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03); | |
232 | netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00); | |
233 | netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00); | |
234 | netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00); | |
235 | netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00); | |
236 | netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data); | |
237 | netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data); | |
238 | netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data); | |
239 | netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data); | |
240 | } else { | |
241 | netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00); | |
242 | netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00); | |
243 | netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01); | |
244 | netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02); | |
245 | netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03); | |
246 | } | |
247 | writel(netxen_mac_addr_cntl_data, | |
248 | NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG)); | |
249 | if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { | |
250 | writel(netxen_mac_addr_cntl_data, | |
251 | NETXEN_CRB_NORMALIZE(adapter, | |
252 | NETXEN_MULTICAST_ADDR_HI_0)); | |
253 | } else { | |
254 | writel(netxen_mac_addr_cntl_data, | |
255 | NETXEN_CRB_NORMALIZE(adapter, | |
256 | NETXEN_MULTICAST_ADDR_HI_1)); | |
257 | } | |
258 | netxen_mac_addr_cntl_data = 0; | |
259 | writel(netxen_mac_addr_cntl_data, | |
260 | NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR)); | |
261 | } | |
262 | ||
263 | /* | |
264 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit | |
265 | * @returns 0 on success, negative on failure | |
266 | */ | |
267 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) | |
268 | { | |
3176ff3e | 269 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 AK |
270 | int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE; |
271 | ||
272 | if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) { | |
273 | printk(KERN_ERR "%s: %s %d is not supported.\n", | |
274 | netxen_nic_driver_name, netdev->name, mtu); | |
275 | return -EINVAL; | |
276 | } | |
277 | ||
80922fbc | 278 | if (adapter->set_mtu) |
3176ff3e | 279 | adapter->set_mtu(adapter, mtu); |
3d396eb1 AK |
280 | netdev->mtu = mtu; |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
285 | /* | |
286 | * check if the firmware has been downloaded and ready to run and | |
287 | * setup the address for the descriptors in the adapter | |
288 | */ | |
289 | int netxen_nic_hw_resources(struct netxen_adapter *adapter) | |
290 | { | |
291 | struct netxen_hardware_context *hw = &adapter->ahw; | |
3d396eb1 AK |
292 | u32 state = 0; |
293 | void *addr; | |
294 | int loops = 0, err = 0; | |
295 | int ctx, ring; | |
296 | u32 card_cmdring = 0; | |
3d396eb1 AK |
297 | struct netxen_recv_context *recv_ctx; |
298 | struct netxen_rcv_desc_ctx *rcv_desc; | |
3d396eb1 | 299 | |
80922fbc | 300 | DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE, |
cb8011ad | 301 | PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE)); |
80922fbc | 302 | DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM, |
cb8011ad | 303 | pci_base_offset(adapter, NETXEN_CRB_CAM)); |
80922fbc | 304 | DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE, |
cb8011ad | 305 | pci_base_offset(adapter, NETXEN_CAM_RAM_BASE)); |
3d396eb1 AK |
306 | |
307 | /* Window 1 call */ | |
308 | card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING)); | |
309 | ||
310 | DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n", | |
311 | card_cmdring); | |
312 | ||
313 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
314 | DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n"); | |
315 | loops = 0; | |
316 | state = 0; | |
317 | /* Window 1 call */ | |
318 | state = readl(NETXEN_CRB_NORMALIZE(adapter, | |
319 | recv_crb_registers[ctx]. | |
320 | crb_rcvpeg_state)); | |
321 | while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) { | |
322 | udelay(100); | |
323 | /* Window 1 call */ | |
324 | state = readl(NETXEN_CRB_NORMALIZE(adapter, | |
325 | recv_crb_registers | |
326 | [ctx]. | |
327 | crb_rcvpeg_state)); | |
328 | loops++; | |
329 | } | |
330 | if (loops >= 20) { | |
331 | printk(KERN_ERR "Rcv Peg initialization not complete:" | |
332 | "%x.\n", state); | |
333 | err = -EIO; | |
334 | return err; | |
335 | } | |
336 | } | |
337 | DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n"); | |
338 | ||
cb8011ad | 339 | addr = netxen_alloc(adapter->ahw.pdev, |
ed25ffa1 AK |
340 | sizeof(struct netxen_ring_ctx) + |
341 | sizeof(uint32_t), | |
342 | (dma_addr_t *) & adapter->ctx_desc_phys_addr, | |
343 | &adapter->ctx_desc_pdev); | |
cb8011ad | 344 | |
3176ff3e | 345 | printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n", |
b8d095d7 | 346 | (unsigned long long) adapter->ctx_desc_phys_addr); |
3d396eb1 AK |
347 | if (addr == NULL) { |
348 | DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); | |
ed25ffa1 AK |
349 | err = -ENOMEM; |
350 | return err; | |
cb8011ad | 351 | } |
ed25ffa1 AK |
352 | memset(addr, 0, sizeof(struct netxen_ring_ctx)); |
353 | adapter->ctx_desc = (struct netxen_ring_ctx *)addr; | |
a608ab9c AV |
354 | adapter->ctx_desc->cmd_consumer_offset = |
355 | cpu_to_le64(adapter->ctx_desc_phys_addr + | |
356 | sizeof(struct netxen_ring_ctx)); | |
ed25ffa1 AK |
357 | adapter->cmd_consumer = (uint32_t *) (((char *)addr) + |
358 | sizeof(struct netxen_ring_ctx)); | |
359 | ||
9de06610 AK |
360 | addr = netxen_alloc(adapter->ahw.pdev, |
361 | sizeof(struct cmd_desc_type0) * | |
362 | adapter->max_tx_desc_count, | |
363 | (dma_addr_t *) & hw->cmd_desc_phys_addr, | |
364 | &adapter->ahw.cmd_desc_pdev); | |
3176ff3e | 365 | printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n", |
b8d095d7 | 366 | (unsigned long long) hw->cmd_desc_phys_addr); |
cb8011ad | 367 | |
ed25ffa1 AK |
368 | if (addr == NULL) { |
369 | DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); | |
370 | netxen_free_hw_resources(adapter); | |
cb8011ad | 371 | return -ENOMEM; |
3d396eb1 AK |
372 | } |
373 | ||
a608ab9c AV |
374 | adapter->ctx_desc->cmd_ring_addr = |
375 | cpu_to_le64(hw->cmd_desc_phys_addr); | |
376 | adapter->ctx_desc->cmd_ring_size = | |
377 | cpu_to_le32(adapter->max_tx_desc_count); | |
3d396eb1 AK |
378 | |
379 | hw->cmd_desc_head = (struct cmd_desc_type0 *)addr; | |
380 | ||
381 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
382 | recv_ctx = &adapter->recv_ctx[ctx]; | |
383 | ||
384 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
385 | rcv_desc = &recv_ctx->rcv_desc[ring]; | |
cb8011ad AK |
386 | addr = netxen_alloc(adapter->ahw.pdev, |
387 | RCV_DESC_RINGSIZE, | |
388 | &rcv_desc->phys_addr, | |
389 | &rcv_desc->phys_pdev); | |
3d396eb1 AK |
390 | if (addr == NULL) { |
391 | DPRINTK(ERR, "bad return from " | |
392 | "pci_alloc_consistent\n"); | |
393 | netxen_free_hw_resources(adapter); | |
394 | err = -ENOMEM; | |
395 | return err; | |
396 | } | |
397 | rcv_desc->desc_head = (struct rcv_desc *)addr; | |
a608ab9c AV |
398 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr = |
399 | cpu_to_le64(rcv_desc->phys_addr); | |
ed25ffa1 | 400 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size = |
a608ab9c | 401 | cpu_to_le32(rcv_desc->max_rx_desc_count); |
3d396eb1 AK |
402 | } |
403 | ||
71bd7877 AK |
404 | addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE, |
405 | &recv_ctx->rcv_status_desc_phys_addr, | |
cb8011ad | 406 | &recv_ctx->rcv_status_desc_pdev); |
3d396eb1 AK |
407 | if (addr == NULL) { |
408 | DPRINTK(ERR, "bad return from" | |
409 | " pci_alloc_consistent\n"); | |
410 | netxen_free_hw_resources(adapter); | |
411 | err = -ENOMEM; | |
412 | return err; | |
413 | } | |
414 | recv_ctx->rcv_status_desc_head = (struct status_desc *)addr; | |
a608ab9c AV |
415 | adapter->ctx_desc->sts_ring_addr = |
416 | cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); | |
417 | adapter->ctx_desc->sts_ring_size = | |
418 | cpu_to_le32(adapter->max_rx_desc_count); | |
3d396eb1 | 419 | |
3d396eb1 AK |
420 | } |
421 | /* Window = 1 */ | |
ed25ffa1 AK |
422 | |
423 | writel(lower32(adapter->ctx_desc_phys_addr), | |
424 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO)); | |
425 | writel(upper32(adapter->ctx_desc_phys_addr), | |
426 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI)); | |
427 | writel(NETXEN_CTX_SIGNATURE, | |
428 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG)); | |
3d396eb1 AK |
429 | return err; |
430 | } | |
431 | ||
432 | void netxen_free_hw_resources(struct netxen_adapter *adapter) | |
433 | { | |
434 | struct netxen_recv_context *recv_ctx; | |
435 | struct netxen_rcv_desc_ctx *rcv_desc; | |
436 | int ctx, ring; | |
437 | ||
ed25ffa1 AK |
438 | if (adapter->ctx_desc != NULL) { |
439 | pci_free_consistent(adapter->ctx_desc_pdev, | |
440 | sizeof(struct netxen_ring_ctx) + | |
441 | sizeof(uint32_t), | |
442 | adapter->ctx_desc, | |
443 | adapter->ctx_desc_phys_addr); | |
444 | adapter->ctx_desc = NULL; | |
445 | } | |
446 | ||
3d396eb1 | 447 | if (adapter->ahw.cmd_desc_head != NULL) { |
cb8011ad | 448 | pci_free_consistent(adapter->ahw.cmd_desc_pdev, |
3d396eb1 AK |
449 | sizeof(struct cmd_desc_type0) * |
450 | adapter->max_tx_desc_count, | |
451 | adapter->ahw.cmd_desc_head, | |
452 | adapter->ahw.cmd_desc_phys_addr); | |
453 | adapter->ahw.cmd_desc_head = NULL; | |
454 | } | |
ed25ffa1 AK |
455 | /* Special handling: there are 2 ports on this board */ |
456 | if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) { | |
457 | adapter->ahw.max_ports = 2; | |
cb8011ad | 458 | } |
3d396eb1 AK |
459 | |
460 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
461 | recv_ctx = &adapter->recv_ctx[ctx]; | |
462 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
463 | rcv_desc = &recv_ctx->rcv_desc[ring]; | |
464 | ||
465 | if (rcv_desc->desc_head != NULL) { | |
cb8011ad | 466 | pci_free_consistent(rcv_desc->phys_pdev, |
3d396eb1 AK |
467 | RCV_DESC_RINGSIZE, |
468 | rcv_desc->desc_head, | |
469 | rcv_desc->phys_addr); | |
470 | rcv_desc->desc_head = NULL; | |
471 | } | |
472 | } | |
473 | ||
474 | if (recv_ctx->rcv_status_desc_head != NULL) { | |
cb8011ad | 475 | pci_free_consistent(recv_ctx->rcv_status_desc_pdev, |
3d396eb1 AK |
476 | STATUS_DESC_RINGSIZE, |
477 | recv_ctx->rcv_status_desc_head, | |
478 | recv_ctx-> | |
479 | rcv_status_desc_phys_addr); | |
480 | recv_ctx->rcv_status_desc_head = NULL; | |
481 | } | |
482 | } | |
483 | } | |
484 | ||
485 | void netxen_tso_check(struct netxen_adapter *adapter, | |
486 | struct cmd_desc_type0 *desc, struct sk_buff *skb) | |
487 | { | |
488 | if (desc->mss) { | |
c9bdd4b5 | 489 | desc->total_hdr_length = (sizeof(struct ethhdr) + |
ab6a5bb6 | 490 | ip_hdrlen(skb) + tcp_hdrlen(skb)); |
ed25ffa1 | 491 | netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO); |
c75e86b4 | 492 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 493 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) { |
ed25ffa1 | 494 | netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT); |
eddc9ec5 | 495 | } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
ed25ffa1 | 496 | netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT); |
3d396eb1 AK |
497 | } else { |
498 | return; | |
499 | } | |
500 | } | |
ea2ae17d | 501 | desc->tcp_hdr_offset = skb_transport_offset(skb); |
bbe735e4 | 502 | desc->ip_hdr_offset = skb_network_offset(skb); |
3d396eb1 AK |
503 | } |
504 | ||
505 | int netxen_is_flash_supported(struct netxen_adapter *adapter) | |
506 | { | |
507 | const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 }; | |
508 | int addr, val01, val02, i, j; | |
509 | ||
510 | /* if the flash size less than 4Mb, make huge war cry and die */ | |
511 | for (j = 1; j < 4; j++) { | |
cb8011ad | 512 | addr = j * NETXEN_NIC_WINDOW_MARGIN; |
3d396eb1 AK |
513 | for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) { |
514 | if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0 | |
515 | && netxen_rom_fast_read(adapter, (addr + locs[i]), | |
516 | &val02) == 0) { | |
517 | if (val01 == val02) | |
518 | return -1; | |
519 | } else | |
520 | return -1; | |
521 | } | |
522 | } | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, | |
528 | int size, u32 * buf) | |
529 | { | |
530 | int i, addr; | |
531 | u32 *ptr32; | |
532 | ||
533 | addr = base; | |
534 | ptr32 = buf; | |
535 | for (i = 0; i < size / sizeof(u32); i++) { | |
536 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) | |
537 | return -1; | |
9b410117 | 538 | *ptr32 = cpu_to_le32(*ptr32); |
3d396eb1 AK |
539 | ptr32++; |
540 | addr += sizeof(u32); | |
541 | } | |
542 | if ((char *)buf + size > (char *)ptr32) { | |
543 | u32 local; | |
544 | ||
545 | if (netxen_rom_fast_read(adapter, addr, &local) == -1) | |
546 | return -1; | |
9b410117 | 547 | local = cpu_to_le32(local); |
3d396eb1 AK |
548 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
549 | } | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]) | |
555 | { | |
556 | u32 *pmac = (u32 *) & mac[0]; | |
557 | ||
558 | if (netxen_get_flash_block(adapter, | |
559 | USER_START + | |
560 | offsetof(struct netxen_new_user_info, | |
561 | mac_addr), | |
562 | FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) { | |
563 | return -1; | |
564 | } | |
565 | if (*mac == ~0ULL) { | |
566 | if (netxen_get_flash_block(adapter, | |
567 | USER_START_OLD + | |
568 | offsetof(struct netxen_user_old_info, | |
569 | mac_addr), | |
570 | FLASH_NUM_PORTS * sizeof(u64), | |
571 | pmac) == -1) | |
572 | return -1; | |
573 | if (*mac == ~0ULL) | |
574 | return -1; | |
575 | } | |
576 | return 0; | |
577 | } | |
578 | ||
579 | /* | |
580 | * Changes the CRB window to the specified window. | |
581 | */ | |
582 | void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw) | |
583 | { | |
584 | void __iomem *offset; | |
585 | u32 tmp; | |
586 | int count = 0; | |
587 | ||
588 | if (adapter->curr_window == wndw) | |
589 | return; | |
3176ff3e MT |
590 | switch(adapter->portnum) { |
591 | case 0: | |
592 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
593 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW)); | |
594 | break; | |
595 | case 1: | |
596 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
597 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1)); | |
598 | break; | |
599 | case 2: | |
600 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
601 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2)); | |
602 | break; | |
603 | case 3: | |
604 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
605 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3)); | |
606 | break; | |
607 | default: | |
608 | printk(KERN_INFO "Changing the window for PCI function" | |
609 | "%d\n", adapter->portnum); | |
610 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
611 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW)); | |
612 | break; | |
613 | } | |
3d396eb1 AK |
614 | /* |
615 | * Move the CRB window. | |
616 | * We need to write to the "direct access" region of PCI | |
617 | * to avoid a race condition where the window register has | |
618 | * not been successfully written across CRB before the target | |
619 | * register address is received by PCI. The direct region bypasses | |
620 | * the CRB bus. | |
621 | */ | |
3d396eb1 AK |
622 | |
623 | if (wndw & 0x1) | |
624 | wndw = NETXEN_WINDOW_ONE; | |
625 | ||
626 | writel(wndw, offset); | |
627 | ||
628 | /* MUST make sure window is set before we forge on... */ | |
629 | while ((tmp = readl(offset)) != wndw) { | |
630 | printk(KERN_WARNING "%s: %s WARNING: CRB window value not " | |
631 | "registered properly: 0x%08x.\n", | |
632 | netxen_nic_driver_name, __FUNCTION__, tmp); | |
633 | mdelay(1); | |
634 | if (count >= 10) | |
635 | break; | |
636 | count++; | |
637 | } | |
638 | ||
639 | adapter->curr_window = wndw; | |
640 | } | |
641 | ||
642 | void netxen_load_firmware(struct netxen_adapter *adapter) | |
643 | { | |
644 | int i; | |
e0e20a1a LCMT |
645 | u32 data, size = 0; |
646 | u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE; | |
3d396eb1 AK |
647 | u64 off; |
648 | void __iomem *addr; | |
649 | ||
650 | size = NETXEN_FIRMWARE_LEN; | |
651 | writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); | |
652 | ||
653 | for (i = 0; i < size; i++) { | |
654 | if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) { | |
655 | DPRINTK(ERR, | |
656 | "Error in netxen_rom_fast_read(). Will skip" | |
657 | "loading flash image\n"); | |
658 | return; | |
659 | } | |
cb8011ad AK |
660 | off = netxen_nic_pci_set_window(adapter, memaddr); |
661 | addr = pci_base_offset(adapter, off); | |
3d396eb1 AK |
662 | writel(data, addr); |
663 | flashaddr += 4; | |
664 | memaddr += 4; | |
665 | } | |
666 | udelay(100); | |
667 | /* make sure Casper is powered on */ | |
668 | writel(0x3fff, | |
669 | NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL)); | |
670 | writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); | |
671 | ||
672 | udelay(100); | |
673 | } | |
674 | ||
675 | int | |
676 | netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
677 | int len) | |
678 | { | |
679 | void __iomem *addr; | |
680 | ||
681 | if (ADDR_IN_WINDOW1(off)) { | |
682 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
683 | } else { /* Window 0 */ | |
cb8011ad | 684 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
685 | netxen_nic_pci_change_crbwindow(adapter, 0); |
686 | } | |
687 | ||
688 | DPRINTK(INFO, "writing to base %lx offset %llx addr %p" | |
689 | " data %llx len %d\n", | |
cb8011ad | 690 | pci_base(adapter, off), off, addr, |
3d396eb1 | 691 | *(unsigned long long *)data, len); |
cb8011ad AK |
692 | if (!addr) { |
693 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
694 | return 1; | |
695 | } | |
696 | ||
3d396eb1 AK |
697 | switch (len) { |
698 | case 1: | |
699 | writeb(*(u8 *) data, addr); | |
700 | break; | |
701 | case 2: | |
702 | writew(*(u16 *) data, addr); | |
703 | break; | |
704 | case 4: | |
705 | writel(*(u32 *) data, addr); | |
706 | break; | |
707 | case 8: | |
708 | writeq(*(u64 *) data, addr); | |
709 | break; | |
710 | default: | |
711 | DPRINTK(INFO, | |
712 | "writing data %lx to offset %llx, num words=%d\n", | |
713 | *(unsigned long *)data, off, (len >> 3)); | |
714 | ||
715 | netxen_nic_hw_block_write64((u64 __iomem *) data, addr, | |
716 | (len >> 3)); | |
717 | break; | |
718 | } | |
719 | if (!ADDR_IN_WINDOW1(off)) | |
720 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | int | |
726 | netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
727 | int len) | |
728 | { | |
729 | void __iomem *addr; | |
730 | ||
731 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ | |
732 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
733 | } else { /* Window 0 */ | |
cb8011ad | 734 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
735 | netxen_nic_pci_change_crbwindow(adapter, 0); |
736 | } | |
737 | ||
738 | DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", | |
cb8011ad AK |
739 | pci_base(adapter, off), off, addr); |
740 | if (!addr) { | |
741 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
742 | return 1; | |
743 | } | |
3d396eb1 AK |
744 | switch (len) { |
745 | case 1: | |
746 | *(u8 *) data = readb(addr); | |
747 | break; | |
748 | case 2: | |
749 | *(u16 *) data = readw(addr); | |
750 | break; | |
751 | case 4: | |
752 | *(u32 *) data = readl(addr); | |
753 | break; | |
754 | case 8: | |
755 | *(u64 *) data = readq(addr); | |
756 | break; | |
757 | default: | |
758 | netxen_nic_hw_block_read64((u64 __iomem *) data, addr, | |
759 | (len >> 3)); | |
760 | break; | |
761 | } | |
762 | DPRINTK(INFO, "read %lx\n", *(unsigned long *)data); | |
763 | ||
764 | if (!ADDR_IN_WINDOW1(off)) | |
765 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
770 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) | |
771 | { /* Only for window 1 */ | |
772 | void __iomem *addr; | |
773 | ||
774 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
775 | DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n", | |
80922fbc | 776 | pci_base(adapter, off), off, addr, val); |
3d396eb1 AK |
777 | writel(val, addr); |
778 | ||
779 | } | |
780 | ||
781 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off) | |
782 | { /* Only for window 1 */ | |
783 | void __iomem *addr; | |
784 | int val; | |
785 | ||
786 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
787 | DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", | |
80922fbc | 788 | pci_base(adapter, off), off, addr); |
3d396eb1 AK |
789 | val = readl(addr); |
790 | writel(val, addr); | |
791 | ||
792 | return val; | |
793 | } | |
794 | ||
795 | /* Change the window to 0, write and change back to window 1. */ | |
796 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value) | |
797 | { | |
798 | void __iomem *addr; | |
799 | ||
800 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
71bd7877 | 801 | addr = pci_base_offset(adapter, index); |
3d396eb1 AK |
802 | writel(value, addr); |
803 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
804 | } | |
805 | ||
806 | /* Change the window to 0, read and change back to window 1. */ | |
807 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value) | |
808 | { | |
809 | void __iomem *addr; | |
810 | ||
71bd7877 | 811 | addr = pci_base_offset(adapter, index); |
3d396eb1 AK |
812 | |
813 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
814 | *value = readl(addr); | |
815 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
816 | } | |
817 | ||
818 | int netxen_pci_set_window_warning_count = 0; | |
819 | ||
820 | unsigned long | |
cb8011ad AK |
821 | netxen_nic_pci_set_window(struct netxen_adapter *adapter, |
822 | unsigned long long addr) | |
3d396eb1 AK |
823 | { |
824 | static int ddr_mn_window = -1; | |
825 | static int qdr_sn_window = -1; | |
826 | int window; | |
827 | ||
828 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | |
829 | /* DDR network side */ | |
830 | addr -= NETXEN_ADDR_DDR_NET; | |
831 | window = (addr >> 25) & 0x3ff; | |
832 | if (ddr_mn_window != window) { | |
833 | ddr_mn_window = window; | |
cb8011ad AK |
834 | writel(window, PCI_OFFSET_SECOND_RANGE(adapter, |
835 | NETXEN_PCIX_PH_REG | |
836 | (PCIX_MN_WINDOW))); | |
3d396eb1 | 837 | /* MUST make sure window is set before we forge on... */ |
cb8011ad AK |
838 | readl(PCI_OFFSET_SECOND_RANGE(adapter, |
839 | NETXEN_PCIX_PH_REG | |
840 | (PCIX_MN_WINDOW))); | |
3d396eb1 | 841 | } |
cb8011ad | 842 | addr -= (window * NETXEN_WINDOW_ONE); |
3d396eb1 AK |
843 | addr += NETXEN_PCI_DDR_NET; |
844 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { | |
845 | addr -= NETXEN_ADDR_OCM0; | |
846 | addr += NETXEN_PCI_OCM0; | |
847 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
848 | addr -= NETXEN_ADDR_OCM1; | |
849 | addr += NETXEN_PCI_OCM1; | |
850 | } else | |
851 | if (ADDR_IN_RANGE | |
852 | (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) { | |
853 | /* QDR network side */ | |
854 | addr -= NETXEN_ADDR_QDR_NET; | |
855 | window = (addr >> 22) & 0x3f; | |
856 | if (qdr_sn_window != window) { | |
857 | qdr_sn_window = window; | |
cb8011ad AK |
858 | writel((window << 22), |
859 | PCI_OFFSET_SECOND_RANGE(adapter, | |
860 | NETXEN_PCIX_PH_REG | |
861 | (PCIX_SN_WINDOW))); | |
3d396eb1 | 862 | /* MUST make sure window is set before we forge on... */ |
cb8011ad AK |
863 | readl(PCI_OFFSET_SECOND_RANGE(adapter, |
864 | NETXEN_PCIX_PH_REG | |
865 | (PCIX_SN_WINDOW))); | |
3d396eb1 AK |
866 | } |
867 | addr -= (window * 0x400000); | |
868 | addr += NETXEN_PCI_QDR_NET; | |
869 | } else { | |
870 | /* | |
871 | * peg gdb frequently accesses memory that doesn't exist, | |
872 | * this limits the chit chat so debugging isn't slowed down. | |
873 | */ | |
874 | if ((netxen_pci_set_window_warning_count++ < 8) | |
875 | || (netxen_pci_set_window_warning_count % 64 == 0)) | |
876 | printk("%s: Warning:netxen_nic_pci_set_window()" | |
877 | " Unknown address range!\n", | |
878 | netxen_nic_driver_name); | |
879 | ||
880 | } | |
881 | return addr; | |
882 | } | |
883 | ||
884 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) | |
885 | { | |
886 | int rv = 0; | |
887 | int addr = BRDCFG_START; | |
888 | struct netxen_board_info *boardinfo; | |
889 | int index; | |
890 | u32 *ptr32; | |
891 | ||
892 | boardinfo = &adapter->ahw.boardcfg; | |
893 | ptr32 = (u32 *) boardinfo; | |
894 | ||
895 | for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32); | |
896 | index++) { | |
897 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { | |
898 | return -EIO; | |
899 | } | |
900 | ptr32++; | |
901 | addr += sizeof(u32); | |
902 | } | |
903 | if (boardinfo->magic != NETXEN_BDINFO_MAGIC) { | |
904 | printk("%s: ERROR reading %s board config." | |
905 | " Read %x, expected %x\n", netxen_nic_driver_name, | |
906 | netxen_nic_driver_name, | |
907 | boardinfo->magic, NETXEN_BDINFO_MAGIC); | |
908 | rv = -1; | |
909 | } | |
910 | if (boardinfo->header_version != NETXEN_BDINFO_VERSION) { | |
911 | printk("%s: Unknown board config version." | |
912 | " Read %x, expected %x\n", netxen_nic_driver_name, | |
913 | boardinfo->header_version, NETXEN_BDINFO_VERSION); | |
914 | rv = -1; | |
915 | } | |
916 | ||
917 | DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type); | |
918 | switch ((netxen_brdtype_t) boardinfo->board_type) { | |
919 | case NETXEN_BRDTYPE_P2_SB35_4G: | |
920 | adapter->ahw.board_type = NETXEN_NIC_GBE; | |
921 | break; | |
922 | case NETXEN_BRDTYPE_P2_SB31_10G: | |
923 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: | |
924 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: | |
925 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: | |
926 | adapter->ahw.board_type = NETXEN_NIC_XGBE; | |
927 | break; | |
928 | case NETXEN_BRDTYPE_P1_BD: | |
929 | case NETXEN_BRDTYPE_P1_SB: | |
930 | case NETXEN_BRDTYPE_P1_SMAX: | |
931 | case NETXEN_BRDTYPE_P1_SOCK: | |
932 | adapter->ahw.board_type = NETXEN_NIC_GBE; | |
933 | break; | |
934 | default: | |
935 | printk("%s: Unknown(%x)\n", netxen_nic_driver_name, | |
936 | boardinfo->board_type); | |
937 | break; | |
938 | } | |
939 | ||
940 | return rv; | |
941 | } | |
942 | ||
943 | /* NIU access sections */ | |
944 | ||
3176ff3e | 945 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 946 | { |
3d396eb1 | 947 | netxen_nic_write_w0(adapter, |
3176ff3e | 948 | NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->portnum), |
3d396eb1 AK |
949 | new_mtu); |
950 | return 0; | |
951 | } | |
952 | ||
3176ff3e | 953 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 954 | { |
3d396eb1 | 955 | new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE; |
3176ff3e | 956 | if (adapter->portnum == 0) |
8b902aea | 957 | netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu); |
3176ff3e | 958 | else if (adapter->portnum == 1) |
8b902aea | 959 | netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu); |
3d396eb1 AK |
960 | return 0; |
961 | } | |
962 | ||
963 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter) | |
964 | { | |
3176ff3e | 965 | netxen_niu_gbe_init_port(adapter, adapter->portnum); |
3d396eb1 AK |
966 | } |
967 | ||
968 | void | |
969 | netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off, | |
970 | int data) | |
971 | { | |
972 | void __iomem *addr; | |
973 | ||
974 | if (ADDR_IN_WINDOW1(off)) { | |
975 | writel(data, NETXEN_CRB_NORMALIZE(adapter, off)); | |
976 | } else { | |
977 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
71bd7877 | 978 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
979 | writel(data, addr); |
980 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
981 | } | |
982 | } | |
983 | ||
3176ff3e | 984 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
3d396eb1 | 985 | { |
a608ab9c AV |
986 | __u32 status; |
987 | __u32 autoneg; | |
988 | __u32 mode; | |
3d396eb1 AK |
989 | |
990 | netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode); | |
991 | if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */ | |
80922fbc AK |
992 | if (adapter->phy_read |
993 | && adapter-> | |
3176ff3e | 994 | phy_read(adapter, adapter->portnum, |
3d396eb1 AK |
995 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, |
996 | &status) == 0) { | |
997 | if (netxen_get_phy_link(status)) { | |
998 | switch (netxen_get_phy_speed(status)) { | |
999 | case 0: | |
3176ff3e | 1000 | adapter->link_speed = SPEED_10; |
3d396eb1 AK |
1001 | break; |
1002 | case 1: | |
3176ff3e | 1003 | adapter->link_speed = SPEED_100; |
3d396eb1 AK |
1004 | break; |
1005 | case 2: | |
3176ff3e | 1006 | adapter->link_speed = SPEED_1000; |
3d396eb1 AK |
1007 | break; |
1008 | default: | |
3176ff3e | 1009 | adapter->link_speed = -1; |
3d396eb1 AK |
1010 | break; |
1011 | } | |
1012 | switch (netxen_get_phy_duplex(status)) { | |
1013 | case 0: | |
3176ff3e | 1014 | adapter->link_duplex = DUPLEX_HALF; |
3d396eb1 AK |
1015 | break; |
1016 | case 1: | |
3176ff3e | 1017 | adapter->link_duplex = DUPLEX_FULL; |
3d396eb1 AK |
1018 | break; |
1019 | default: | |
3176ff3e | 1020 | adapter->link_duplex = -1; |
3d396eb1 AK |
1021 | break; |
1022 | } | |
80922fbc AK |
1023 | if (adapter->phy_read |
1024 | && adapter-> | |
3176ff3e | 1025 | phy_read(adapter, adapter->portnum, |
3d396eb1 | 1026 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, |
ed25ffa1 | 1027 | &autoneg) != 0) |
3176ff3e | 1028 | adapter->link_autoneg = autoneg; |
3d396eb1 AK |
1029 | } else |
1030 | goto link_down; | |
1031 | } else { | |
1032 | link_down: | |
3176ff3e MT |
1033 | adapter->link_speed = -1; |
1034 | adapter->link_duplex = -1; | |
3d396eb1 AK |
1035 | } |
1036 | } | |
1037 | } | |
1038 | ||
1039 | void netxen_nic_flash_print(struct netxen_adapter *adapter) | |
1040 | { | |
1041 | int valid = 1; | |
1042 | u32 fw_major = 0; | |
1043 | u32 fw_minor = 0; | |
1044 | u32 fw_build = 0; | |
cb8011ad AK |
1045 | char brd_name[NETXEN_MAX_SHORT_NAME]; |
1046 | struct netxen_new_user_info user_info; | |
1047 | int i, addr = USER_START; | |
1048 | u32 *ptr32; | |
3d396eb1 AK |
1049 | |
1050 | struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); | |
1051 | if (board_info->magic != NETXEN_BDINFO_MAGIC) { | |
1052 | printk | |
1053 | ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n", | |
1054 | board_info->magic, NETXEN_BDINFO_MAGIC); | |
1055 | valid = 0; | |
1056 | } | |
1057 | if (board_info->header_version != NETXEN_BDINFO_VERSION) { | |
1058 | printk("NetXen Unknown board config version." | |
1059 | " Read %x, expected %x\n", | |
1060 | board_info->header_version, NETXEN_BDINFO_VERSION); | |
1061 | valid = 0; | |
1062 | } | |
1063 | if (valid) { | |
cb8011ad AK |
1064 | ptr32 = (u32 *) & user_info; |
1065 | for (i = 0; | |
1066 | i < sizeof(struct netxen_new_user_info) / sizeof(u32); | |
1067 | i++) { | |
1068 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { | |
1069 | printk("%s: ERROR reading %s board userarea.\n", | |
1070 | netxen_nic_driver_name, | |
1071 | netxen_nic_driver_name); | |
1072 | return; | |
1073 | } | |
e0e20a1a | 1074 | *ptr32 = le32_to_cpu(*ptr32); |
cb8011ad AK |
1075 | ptr32++; |
1076 | addr += sizeof(u32); | |
1077 | } | |
1078 | get_brd_name_by_type(board_info->board_type, brd_name); | |
1079 | ||
1080 | printk("NetXen %s Board S/N %s Chip id 0x%x\n", | |
1081 | brd_name, user_info.serial_num, board_info->chip_id); | |
1082 | ||
3d396eb1 AK |
1083 | printk("NetXen %s Board #%d, Chip id 0x%x\n", |
1084 | board_info->board_type == 0x0b ? "XGB" : "GBE", | |
1085 | board_info->board_num, board_info->chip_id); | |
1086 | fw_major = readl(NETXEN_CRB_NORMALIZE(adapter, | |
1087 | NETXEN_FW_VERSION_MAJOR)); | |
1088 | fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter, | |
1089 | NETXEN_FW_VERSION_MINOR)); | |
1090 | fw_build = | |
1091 | readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB)); | |
1092 | ||
1093 | printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor, | |
1094 | fw_build); | |
1095 | } | |
1096 | if (fw_major != _NETXEN_NIC_LINUX_MAJOR) { | |
1097 | printk(KERN_ERR "The mismatch in driver version and firmware " | |
1098 | "version major number\n" | |
1099 | "Driver version major number = %d \t" | |
1100 | "Firmware version major number = %d \n", | |
1101 | _NETXEN_NIC_LINUX_MAJOR, fw_major); | |
1102 | adapter->driver_mismatch = 1; | |
1103 | } | |
90f8b1d2 AK |
1104 | if (fw_minor != _NETXEN_NIC_LINUX_MINOR && |
1105 | fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) { | |
3d396eb1 AK |
1106 | printk(KERN_ERR "The mismatch in driver version and firmware " |
1107 | "version minor number\n" | |
1108 | "Driver version minor number = %d \t" | |
1109 | "Firmware version minor number = %d \n", | |
1110 | _NETXEN_NIC_LINUX_MINOR, fw_minor); | |
1111 | adapter->driver_mismatch = 1; | |
1112 | } | |
1113 | if (adapter->driver_mismatch) | |
1114 | printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n", | |
1115 | fw_major, fw_minor); | |
1116 | } | |
1117 |