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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | ||
99f252b0 | 27 | #include <asm/system.h> |
1da177e4 LT |
28 | #include <asm/io.h> |
29 | #include <asm/irq.h> | |
30 | ||
f7ccf420 SH |
31 | #ifdef CONFIG_R8169_NAPI |
32 | #define NAPI_SUFFIX "-NAPI" | |
33 | #else | |
34 | #define NAPI_SUFFIX "" | |
35 | #endif | |
36 | ||
37 | #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX | |
1da177e4 LT |
38 | #define MODULENAME "r8169" |
39 | #define PFX MODULENAME ": " | |
40 | ||
41 | #ifdef RTL8169_DEBUG | |
42 | #define assert(expr) \ | |
5b0384f4 FR |
43 | if (!(expr)) { \ |
44 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
45 | #expr,__FILE__,__FUNCTION__,__LINE__); \ | |
46 | } | |
06fa7358 JP |
47 | #define dprintk(fmt, args...) \ |
48 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
49 | #else |
50 | #define assert(expr) do {} while (0) | |
51 | #define dprintk(fmt, args...) do {} while (0) | |
52 | #endif /* RTL8169_DEBUG */ | |
53 | ||
b57b7e5a | 54 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 55 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 56 | |
1da177e4 LT |
57 | #define TX_BUFFS_AVAIL(tp) \ |
58 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
59 | ||
60 | #ifdef CONFIG_R8169_NAPI | |
61 | #define rtl8169_rx_skb netif_receive_skb | |
0b50f81d | 62 | #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb |
1da177e4 LT |
63 | #define rtl8169_rx_quota(count, quota) min(count, quota) |
64 | #else | |
65 | #define rtl8169_rx_skb netif_rx | |
0b50f81d | 66 | #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx |
1da177e4 LT |
67 | #define rtl8169_rx_quota(count, quota) count |
68 | #endif | |
69 | ||
1da177e4 | 70 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
f71e1309 | 71 | static const int max_interrupt_work = 20; |
1da177e4 LT |
72 | |
73 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
74 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 75 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
76 | |
77 | /* MAC address length */ | |
78 | #define MAC_ADDR_LEN 6 | |
79 | ||
80 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ | |
81 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
82 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
07d3f51f | 83 | #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
1da177e4 LT |
84 | #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ |
85 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ | |
86 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
87 | ||
88 | #define R8169_REGS_SIZE 256 | |
89 | #define R8169_NAPI_WEIGHT 64 | |
90 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
91 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
92 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
93 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
94 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
95 | ||
96 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
97 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
98 | ||
99 | /* write/read MMIO register */ | |
100 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
101 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
102 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
103 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
104 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
105 | #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) | |
106 | ||
107 | enum mac_version { | |
ba6eb6ee FR |
108 | RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
109 | RTL_GIGA_MAC_VER_02 = 0x02, // 8169S | |
110 | RTL_GIGA_MAC_VER_03 = 0x03, // 8110S | |
111 | RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB | |
112 | RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd | |
6dccd16b | 113 | RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
2dd99530 | 114 | RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
e3cf0cc0 FR |
115 | RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
116 | RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb | |
117 | RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? | |
118 | RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? | |
119 | RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec | |
120 | RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf | |
121 | RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP | |
122 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C | |
123 | RTL_GIGA_MAC_VER_20 = 0x14 // 8168C | |
1da177e4 LT |
124 | }; |
125 | ||
1da177e4 LT |
126 | #define _R(NAME,MAC,MASK) \ |
127 | { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } | |
128 | ||
3c6bee1d | 129 | static const struct { |
1da177e4 LT |
130 | const char *name; |
131 | u8 mac_version; | |
132 | u32 RxConfigMask; /* Clears the bits supported by this chip */ | |
133 | } rtl_chip_info[] = { | |
ba6eb6ee FR |
134 | _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
135 | _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S | |
136 | _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S | |
137 | _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB | |
138 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd | |
6dccd16b | 139 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
bcf0bf90 FR |
140 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
141 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E | |
142 | _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 | |
143 | _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 | |
e3cf0cc0 FR |
144 | _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
145 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E | |
146 | _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E | |
147 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E | |
148 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E | |
149 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E | |
1da177e4 LT |
150 | }; |
151 | #undef _R | |
152 | ||
bcf0bf90 FR |
153 | enum cfg_version { |
154 | RTL_CFG_0 = 0x00, | |
155 | RTL_CFG_1, | |
156 | RTL_CFG_2 | |
157 | }; | |
158 | ||
07ce4064 FR |
159 | static void rtl_hw_start_8169(struct net_device *); |
160 | static void rtl_hw_start_8168(struct net_device *); | |
161 | static void rtl_hw_start_8101(struct net_device *); | |
162 | ||
1da177e4 | 163 | static struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 164 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 165 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 166 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 167 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
168 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
169 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
bc1660b5 | 170 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
171 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
172 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
173 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
174 | { 0x0001, 0x8168, |
175 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
176 | {0,}, |
177 | }; | |
178 | ||
179 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
180 | ||
181 | static int rx_copybreak = 200; | |
182 | static int use_dac; | |
b57b7e5a SH |
183 | static struct { |
184 | u32 msg_enable; | |
185 | } debug = { -1 }; | |
1da177e4 | 186 | |
07d3f51f FR |
187 | enum rtl_registers { |
188 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 189 | MAC4 = 4, |
07d3f51f FR |
190 | MAR0 = 8, /* Multicast filter. */ |
191 | CounterAddrLow = 0x10, | |
192 | CounterAddrHigh = 0x14, | |
193 | TxDescStartAddrLow = 0x20, | |
194 | TxDescStartAddrHigh = 0x24, | |
195 | TxHDescStartAddrLow = 0x28, | |
196 | TxHDescStartAddrHigh = 0x2c, | |
197 | FLASH = 0x30, | |
198 | ERSR = 0x36, | |
199 | ChipCmd = 0x37, | |
200 | TxPoll = 0x38, | |
201 | IntrMask = 0x3c, | |
202 | IntrStatus = 0x3e, | |
203 | TxConfig = 0x40, | |
204 | RxConfig = 0x44, | |
205 | RxMissed = 0x4c, | |
206 | Cfg9346 = 0x50, | |
207 | Config0 = 0x51, | |
208 | Config1 = 0x52, | |
209 | Config2 = 0x53, | |
210 | Config3 = 0x54, | |
211 | Config4 = 0x55, | |
212 | Config5 = 0x56, | |
213 | MultiIntr = 0x5c, | |
214 | PHYAR = 0x60, | |
215 | TBICSR = 0x64, | |
216 | TBI_ANAR = 0x68, | |
217 | TBI_LPAR = 0x6a, | |
218 | PHYstatus = 0x6c, | |
219 | RxMaxSize = 0xda, | |
220 | CPlusCmd = 0xe0, | |
221 | IntrMitigate = 0xe2, | |
222 | RxDescAddrLow = 0xe4, | |
223 | RxDescAddrHigh = 0xe8, | |
224 | EarlyTxThres = 0xec, | |
225 | FuncEvent = 0xf0, | |
226 | FuncEventMask = 0xf4, | |
227 | FuncPresetState = 0xf8, | |
228 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
229 | }; |
230 | ||
07d3f51f | 231 | enum rtl_register_content { |
1da177e4 | 232 | /* InterruptStatusBits */ |
07d3f51f FR |
233 | SYSErr = 0x8000, |
234 | PCSTimeout = 0x4000, | |
235 | SWInt = 0x0100, | |
236 | TxDescUnavail = 0x0080, | |
237 | RxFIFOOver = 0x0040, | |
238 | LinkChg = 0x0020, | |
239 | RxOverflow = 0x0010, | |
240 | TxErr = 0x0008, | |
241 | TxOK = 0x0004, | |
242 | RxErr = 0x0002, | |
243 | RxOK = 0x0001, | |
1da177e4 LT |
244 | |
245 | /* RxStatusDesc */ | |
9dccf611 FR |
246 | RxFOVF = (1 << 23), |
247 | RxRWT = (1 << 22), | |
248 | RxRES = (1 << 21), | |
249 | RxRUNT = (1 << 20), | |
250 | RxCRC = (1 << 19), | |
1da177e4 LT |
251 | |
252 | /* ChipCmdBits */ | |
07d3f51f FR |
253 | CmdReset = 0x10, |
254 | CmdRxEnb = 0x08, | |
255 | CmdTxEnb = 0x04, | |
256 | RxBufEmpty = 0x01, | |
1da177e4 | 257 | |
275391a4 FR |
258 | /* TXPoll register p.5 */ |
259 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
260 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
261 | FSWInt = 0x01, /* Forced software interrupt */ | |
262 | ||
1da177e4 | 263 | /* Cfg9346Bits */ |
07d3f51f FR |
264 | Cfg9346_Lock = 0x00, |
265 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
266 | |
267 | /* rx_mode_bits */ | |
07d3f51f FR |
268 | AcceptErr = 0x20, |
269 | AcceptRunt = 0x10, | |
270 | AcceptBroadcast = 0x08, | |
271 | AcceptMulticast = 0x04, | |
272 | AcceptMyPhys = 0x02, | |
273 | AcceptAllPhys = 0x01, | |
1da177e4 LT |
274 | |
275 | /* RxConfigBits */ | |
07d3f51f FR |
276 | RxCfgFIFOShift = 13, |
277 | RxCfgDMAShift = 8, | |
1da177e4 LT |
278 | |
279 | /* TxConfigBits */ | |
280 | TxInterFrameGapShift = 24, | |
281 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
282 | ||
5d06a99f | 283 | /* Config1 register p.24 */ |
fbac58fc | 284 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
5d06a99f FR |
285 | PMEnable = (1 << 0), /* Power Management Enable */ |
286 | ||
6dccd16b FR |
287 | /* Config2 register p. 25 */ |
288 | PCI_Clock_66MHz = 0x01, | |
289 | PCI_Clock_33MHz = 0x00, | |
290 | ||
61a4dcc2 FR |
291 | /* Config3 register p.25 */ |
292 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
293 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
294 | ||
5d06a99f | 295 | /* Config5 register p.27 */ |
61a4dcc2 FR |
296 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
297 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
298 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
299 | LanWake = (1 << 1), /* LanWake enable/disable */ | |
5d06a99f FR |
300 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
301 | ||
1da177e4 LT |
302 | /* TBICSR p.28 */ |
303 | TBIReset = 0x80000000, | |
304 | TBILoopback = 0x40000000, | |
305 | TBINwEnable = 0x20000000, | |
306 | TBINwRestart = 0x10000000, | |
307 | TBILinkOk = 0x02000000, | |
308 | TBINwComplete = 0x01000000, | |
309 | ||
310 | /* CPlusCmd p.31 */ | |
0e485150 | 311 | PktCntrDisable = (1 << 7), // 8168 |
1da177e4 LT |
312 | RxVlan = (1 << 6), |
313 | RxChkSum = (1 << 5), | |
314 | PCIDAC = (1 << 4), | |
315 | PCIMulRW = (1 << 3), | |
0e485150 FR |
316 | INTT_0 = 0x0000, // 8168 |
317 | INTT_1 = 0x0001, // 8168 | |
318 | INTT_2 = 0x0002, // 8168 | |
319 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
320 | |
321 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
322 | TBI_Enable = 0x80, |
323 | TxFlowCtrl = 0x40, | |
324 | RxFlowCtrl = 0x20, | |
325 | _1000bpsF = 0x10, | |
326 | _100bps = 0x08, | |
327 | _10bps = 0x04, | |
328 | LinkStatus = 0x02, | |
329 | FullDup = 0x01, | |
1da177e4 | 330 | |
1da177e4 | 331 | /* _TBICSRBit */ |
07d3f51f | 332 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
333 | |
334 | /* DumpCounterCommand */ | |
07d3f51f | 335 | CounterDump = 0x8, |
1da177e4 LT |
336 | }; |
337 | ||
07d3f51f | 338 | enum desc_status_bit { |
1da177e4 LT |
339 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
340 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
341 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
342 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
343 | ||
344 | /* Tx private */ | |
345 | LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ | |
346 | MSSShift = 16, /* MSS value position */ | |
347 | MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ | |
348 | IPCS = (1 << 18), /* Calculate IP checksum */ | |
349 | UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ | |
350 | TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ | |
351 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
352 | ||
353 | /* Rx private */ | |
354 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
355 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
356 | ||
357 | #define RxProtoUDP (PID1) | |
358 | #define RxProtoTCP (PID0) | |
359 | #define RxProtoIP (PID1 | PID0) | |
360 | #define RxProtoMask RxProtoIP | |
361 | ||
362 | IPFail = (1 << 16), /* IP checksum failed */ | |
363 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
364 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
365 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
366 | }; | |
367 | ||
368 | #define RsvdMask 0x3fffc000 | |
369 | ||
370 | struct TxDesc { | |
6cccd6e7 REB |
371 | __le32 opts1; |
372 | __le32 opts2; | |
373 | __le64 addr; | |
1da177e4 LT |
374 | }; |
375 | ||
376 | struct RxDesc { | |
6cccd6e7 REB |
377 | __le32 opts1; |
378 | __le32 opts2; | |
379 | __le64 addr; | |
1da177e4 LT |
380 | }; |
381 | ||
382 | struct ring_info { | |
383 | struct sk_buff *skb; | |
384 | u32 len; | |
385 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
386 | }; | |
387 | ||
f23e7fda FR |
388 | enum features { |
389 | RTL_FEATURE_WOL = (1 << 0), | |
fbac58fc | 390 | RTL_FEATURE_MSI = (1 << 1), |
f23e7fda FR |
391 | }; |
392 | ||
1da177e4 LT |
393 | struct rtl8169_private { |
394 | void __iomem *mmio_addr; /* memory map physical address */ | |
395 | struct pci_dev *pci_dev; /* Index of PCI device */ | |
c4028958 | 396 | struct net_device *dev; |
7fab06c0 | 397 | #ifdef CONFIG_R8169_NAPI |
bea3348e | 398 | struct napi_struct napi; |
7fab06c0 | 399 | #endif |
1da177e4 | 400 | spinlock_t lock; /* spin lock flag */ |
b57b7e5a | 401 | u32 msg_enable; |
1da177e4 LT |
402 | int chipset; |
403 | int mac_version; | |
1da177e4 LT |
404 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
405 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
406 | u32 dirty_rx; | |
407 | u32 dirty_tx; | |
408 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
409 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
410 | dma_addr_t TxPhyAddr; | |
411 | dma_addr_t RxPhyAddr; | |
412 | struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ | |
413 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ | |
bcf0bf90 | 414 | unsigned align; |
1da177e4 LT |
415 | unsigned rx_buf_sz; |
416 | struct timer_list timer; | |
417 | u16 cp_cmd; | |
0e485150 FR |
418 | u16 intr_event; |
419 | u16 napi_event; | |
1da177e4 LT |
420 | u16 intr_mask; |
421 | int phy_auto_nego_reg; | |
422 | int phy_1000_ctrl_reg; | |
423 | #ifdef CONFIG_R8169_VLAN | |
424 | struct vlan_group *vlgrp; | |
425 | #endif | |
426 | int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); | |
427 | void (*get_settings)(struct net_device *, struct ethtool_cmd *); | |
428 | void (*phy_reset_enable)(void __iomem *); | |
07ce4064 | 429 | void (*hw_start)(struct net_device *); |
1da177e4 LT |
430 | unsigned int (*phy_reset_pending)(void __iomem *); |
431 | unsigned int (*link_ok)(void __iomem *); | |
c4028958 | 432 | struct delayed_work task; |
f23e7fda | 433 | unsigned features; |
1da177e4 LT |
434 | }; |
435 | ||
979b6c13 | 436 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 437 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 438 | module_param(rx_copybreak, int, 0); |
1b7efd58 | 439 | MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
1da177e4 LT |
440 | module_param(use_dac, int, 0); |
441 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); | |
b57b7e5a SH |
442 | module_param_named(debug, debug.msg_enable, int, 0); |
443 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
444 | MODULE_LICENSE("GPL"); |
445 | MODULE_VERSION(RTL8169_VERSION); | |
446 | ||
447 | static int rtl8169_open(struct net_device *dev); | |
448 | static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
7d12e780 | 449 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
1da177e4 | 450 | static int rtl8169_init_ring(struct net_device *dev); |
07ce4064 | 451 | static void rtl_hw_start(struct net_device *dev); |
1da177e4 | 452 | static int rtl8169_close(struct net_device *dev); |
07ce4064 | 453 | static void rtl_set_rx_mode(struct net_device *dev); |
1da177e4 | 454 | static void rtl8169_tx_timeout(struct net_device *dev); |
4dcb7d33 | 455 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
1da177e4 | 456 | static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
bea3348e | 457 | void __iomem *, u32 budget); |
4dcb7d33 | 458 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
1da177e4 | 459 | static void rtl8169_down(struct net_device *dev); |
99f252b0 | 460 | static void rtl8169_rx_clear(struct rtl8169_private *tp); |
1da177e4 LT |
461 | |
462 | #ifdef CONFIG_R8169_NAPI | |
bea3348e | 463 | static int rtl8169_poll(struct napi_struct *napi, int budget); |
1da177e4 LT |
464 | #endif |
465 | ||
1da177e4 | 466 | static const unsigned int rtl8169_rx_config = |
5b0384f4 | 467 | (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
1da177e4 | 468 | |
07d3f51f | 469 | static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
1da177e4 LT |
470 | { |
471 | int i; | |
472 | ||
07d3f51f | 473 | RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value); |
1da177e4 | 474 | |
2371408c | 475 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
476 | /* |
477 | * Check if the RTL8169 has completed writing to the specified | |
478 | * MII register. | |
479 | */ | |
5b0384f4 | 480 | if (!(RTL_R32(PHYAR) & 0x80000000)) |
1da177e4 | 481 | break; |
2371408c | 482 | udelay(25); |
1da177e4 LT |
483 | } |
484 | } | |
485 | ||
07d3f51f | 486 | static int mdio_read(void __iomem *ioaddr, int reg_addr) |
1da177e4 LT |
487 | { |
488 | int i, value = -1; | |
489 | ||
07d3f51f | 490 | RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16); |
1da177e4 | 491 | |
2371408c | 492 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
493 | /* |
494 | * Check if the RTL8169 has completed retrieving data from | |
495 | * the specified MII register. | |
496 | */ | |
1da177e4 LT |
497 | if (RTL_R32(PHYAR) & 0x80000000) { |
498 | value = (int) (RTL_R32(PHYAR) & 0xFFFF); | |
499 | break; | |
500 | } | |
2371408c | 501 | udelay(25); |
1da177e4 LT |
502 | } |
503 | return value; | |
504 | } | |
505 | ||
506 | static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) | |
507 | { | |
508 | RTL_W16(IntrMask, 0x0000); | |
509 | ||
510 | RTL_W16(IntrStatus, 0xffff); | |
511 | } | |
512 | ||
513 | static void rtl8169_asic_down(void __iomem *ioaddr) | |
514 | { | |
515 | RTL_W8(ChipCmd, 0x00); | |
516 | rtl8169_irq_mask_and_ack(ioaddr); | |
517 | RTL_R16(CPlusCmd); | |
518 | } | |
519 | ||
520 | static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) | |
521 | { | |
522 | return RTL_R32(TBICSR) & TBIReset; | |
523 | } | |
524 | ||
525 | static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) | |
526 | { | |
64e4bfb4 | 527 | return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
528 | } |
529 | ||
530 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
531 | { | |
532 | return RTL_R32(TBICSR) & TBILinkOk; | |
533 | } | |
534 | ||
535 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
536 | { | |
537 | return RTL_R8(PHYstatus) & LinkStatus; | |
538 | } | |
539 | ||
540 | static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) | |
541 | { | |
542 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); | |
543 | } | |
544 | ||
545 | static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) | |
546 | { | |
547 | unsigned int val; | |
548 | ||
9e0db8ef FR |
549 | val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
550 | mdio_write(ioaddr, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
551 | } |
552 | ||
553 | static void rtl8169_check_link_status(struct net_device *dev, | |
07d3f51f FR |
554 | struct rtl8169_private *tp, |
555 | void __iomem *ioaddr) | |
1da177e4 LT |
556 | { |
557 | unsigned long flags; | |
558 | ||
559 | spin_lock_irqsave(&tp->lock, flags); | |
560 | if (tp->link_ok(ioaddr)) { | |
561 | netif_carrier_on(dev); | |
b57b7e5a SH |
562 | if (netif_msg_ifup(tp)) |
563 | printk(KERN_INFO PFX "%s: link up\n", dev->name); | |
564 | } else { | |
565 | if (netif_msg_ifdown(tp)) | |
566 | printk(KERN_INFO PFX "%s: link down\n", dev->name); | |
1da177e4 | 567 | netif_carrier_off(dev); |
b57b7e5a | 568 | } |
1da177e4 LT |
569 | spin_unlock_irqrestore(&tp->lock, flags); |
570 | } | |
571 | ||
61a4dcc2 FR |
572 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
573 | { | |
574 | struct rtl8169_private *tp = netdev_priv(dev); | |
575 | void __iomem *ioaddr = tp->mmio_addr; | |
576 | u8 options; | |
577 | ||
578 | wol->wolopts = 0; | |
579 | ||
580 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) | |
581 | wol->supported = WAKE_ANY; | |
582 | ||
583 | spin_lock_irq(&tp->lock); | |
584 | ||
585 | options = RTL_R8(Config1); | |
586 | if (!(options & PMEnable)) | |
587 | goto out_unlock; | |
588 | ||
589 | options = RTL_R8(Config3); | |
590 | if (options & LinkUp) | |
591 | wol->wolopts |= WAKE_PHY; | |
592 | if (options & MagicPacket) | |
593 | wol->wolopts |= WAKE_MAGIC; | |
594 | ||
595 | options = RTL_R8(Config5); | |
596 | if (options & UWF) | |
597 | wol->wolopts |= WAKE_UCAST; | |
598 | if (options & BWF) | |
5b0384f4 | 599 | wol->wolopts |= WAKE_BCAST; |
61a4dcc2 | 600 | if (options & MWF) |
5b0384f4 | 601 | wol->wolopts |= WAKE_MCAST; |
61a4dcc2 FR |
602 | |
603 | out_unlock: | |
604 | spin_unlock_irq(&tp->lock); | |
605 | } | |
606 | ||
607 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
608 | { | |
609 | struct rtl8169_private *tp = netdev_priv(dev); | |
610 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 611 | unsigned int i; |
61a4dcc2 FR |
612 | static struct { |
613 | u32 opt; | |
614 | u16 reg; | |
615 | u8 mask; | |
616 | } cfg[] = { | |
617 | { WAKE_ANY, Config1, PMEnable }, | |
618 | { WAKE_PHY, Config3, LinkUp }, | |
619 | { WAKE_MAGIC, Config3, MagicPacket }, | |
620 | { WAKE_UCAST, Config5, UWF }, | |
621 | { WAKE_BCAST, Config5, BWF }, | |
622 | { WAKE_MCAST, Config5, MWF }, | |
623 | { WAKE_ANY, Config5, LanWake } | |
624 | }; | |
625 | ||
626 | spin_lock_irq(&tp->lock); | |
627 | ||
628 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
629 | ||
630 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
631 | u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; | |
632 | if (wol->wolopts & cfg[i].opt) | |
633 | options |= cfg[i].mask; | |
634 | RTL_W8(cfg[i].reg, options); | |
635 | } | |
636 | ||
637 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
638 | ||
f23e7fda FR |
639 | if (wol->wolopts) |
640 | tp->features |= RTL_FEATURE_WOL; | |
641 | else | |
642 | tp->features &= ~RTL_FEATURE_WOL; | |
61a4dcc2 FR |
643 | |
644 | spin_unlock_irq(&tp->lock); | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
1da177e4 LT |
649 | static void rtl8169_get_drvinfo(struct net_device *dev, |
650 | struct ethtool_drvinfo *info) | |
651 | { | |
652 | struct rtl8169_private *tp = netdev_priv(dev); | |
653 | ||
654 | strcpy(info->driver, MODULENAME); | |
655 | strcpy(info->version, RTL8169_VERSION); | |
656 | strcpy(info->bus_info, pci_name(tp->pci_dev)); | |
657 | } | |
658 | ||
659 | static int rtl8169_get_regs_len(struct net_device *dev) | |
660 | { | |
661 | return R8169_REGS_SIZE; | |
662 | } | |
663 | ||
664 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
665 | u8 autoneg, u16 speed, u8 duplex) | |
666 | { | |
667 | struct rtl8169_private *tp = netdev_priv(dev); | |
668 | void __iomem *ioaddr = tp->mmio_addr; | |
669 | int ret = 0; | |
670 | u32 reg; | |
671 | ||
672 | reg = RTL_R32(TBICSR); | |
673 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
674 | (duplex == DUPLEX_FULL)) { | |
675 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
676 | } else if (autoneg == AUTONEG_ENABLE) | |
677 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
678 | else { | |
b57b7e5a SH |
679 | if (netif_msg_link(tp)) { |
680 | printk(KERN_WARNING "%s: " | |
681 | "incorrect speed setting refused in TBI mode\n", | |
682 | dev->name); | |
683 | } | |
1da177e4 LT |
684 | ret = -EOPNOTSUPP; |
685 | } | |
686 | ||
687 | return ret; | |
688 | } | |
689 | ||
690 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
691 | u8 autoneg, u16 speed, u8 duplex) | |
692 | { | |
693 | struct rtl8169_private *tp = netdev_priv(dev); | |
694 | void __iomem *ioaddr = tp->mmio_addr; | |
695 | int auto_nego, giga_ctrl; | |
696 | ||
64e4bfb4 FR |
697 | auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
698 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
699 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
700 | giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); | |
701 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
1da177e4 LT |
702 | |
703 | if (autoneg == AUTONEG_ENABLE) { | |
64e4bfb4 FR |
704 | auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
705 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
706 | giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
1da177e4 LT |
707 | } else { |
708 | if (speed == SPEED_10) | |
64e4bfb4 | 709 | auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
1da177e4 | 710 | else if (speed == SPEED_100) |
64e4bfb4 | 711 | auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
1da177e4 | 712 | else if (speed == SPEED_1000) |
64e4bfb4 | 713 | giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
1da177e4 LT |
714 | |
715 | if (duplex == DUPLEX_HALF) | |
64e4bfb4 | 716 | auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); |
726ecdcf AG |
717 | |
718 | if (duplex == DUPLEX_FULL) | |
64e4bfb4 | 719 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); |
bcf0bf90 FR |
720 | |
721 | /* This tweak comes straight from Realtek's driver. */ | |
722 | if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && | |
e3cf0cc0 FR |
723 | ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
724 | (tp->mac_version == RTL_GIGA_MAC_VER_16))) { | |
64e4bfb4 | 725 | auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; |
bcf0bf90 FR |
726 | } |
727 | } | |
728 | ||
729 | /* The 8100e/8101e do Fast Ethernet only. */ | |
730 | if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || | |
731 | (tp->mac_version == RTL_GIGA_MAC_VER_14) || | |
e3cf0cc0 FR |
732 | (tp->mac_version == RTL_GIGA_MAC_VER_15) || |
733 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
64e4bfb4 | 734 | if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && |
bcf0bf90 FR |
735 | netif_msg_link(tp)) { |
736 | printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", | |
737 | dev->name); | |
738 | } | |
64e4bfb4 | 739 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
1da177e4 LT |
740 | } |
741 | ||
623a1593 FR |
742 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
743 | ||
e3cf0cc0 FR |
744 | if ((tp->mac_version == RTL_GIGA_MAC_VER_12) || |
745 | (tp->mac_version == RTL_GIGA_MAC_VER_17)) { | |
2584fbc3 RS |
746 | /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */ |
747 | mdio_write(ioaddr, 0x1f, 0x0000); | |
748 | mdio_write(ioaddr, 0x0e, 0x0000); | |
749 | } | |
750 | ||
1da177e4 LT |
751 | tp->phy_auto_nego_reg = auto_nego; |
752 | tp->phy_1000_ctrl_reg = giga_ctrl; | |
753 | ||
64e4bfb4 FR |
754 | mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
755 | mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); | |
756 | mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); | |
1da177e4 LT |
757 | return 0; |
758 | } | |
759 | ||
760 | static int rtl8169_set_speed(struct net_device *dev, | |
761 | u8 autoneg, u16 speed, u8 duplex) | |
762 | { | |
763 | struct rtl8169_private *tp = netdev_priv(dev); | |
764 | int ret; | |
765 | ||
766 | ret = tp->set_speed(dev, autoneg, speed, duplex); | |
767 | ||
64e4bfb4 | 768 | if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
769 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
770 | ||
771 | return ret; | |
772 | } | |
773 | ||
774 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
775 | { | |
776 | struct rtl8169_private *tp = netdev_priv(dev); | |
777 | unsigned long flags; | |
778 | int ret; | |
779 | ||
780 | spin_lock_irqsave(&tp->lock, flags); | |
781 | ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); | |
782 | spin_unlock_irqrestore(&tp->lock, flags); | |
5b0384f4 | 783 | |
1da177e4 LT |
784 | return ret; |
785 | } | |
786 | ||
787 | static u32 rtl8169_get_rx_csum(struct net_device *dev) | |
788 | { | |
789 | struct rtl8169_private *tp = netdev_priv(dev); | |
790 | ||
791 | return tp->cp_cmd & RxChkSum; | |
792 | } | |
793 | ||
794 | static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) | |
795 | { | |
796 | struct rtl8169_private *tp = netdev_priv(dev); | |
797 | void __iomem *ioaddr = tp->mmio_addr; | |
798 | unsigned long flags; | |
799 | ||
800 | spin_lock_irqsave(&tp->lock, flags); | |
801 | ||
802 | if (data) | |
803 | tp->cp_cmd |= RxChkSum; | |
804 | else | |
805 | tp->cp_cmd &= ~RxChkSum; | |
806 | ||
807 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
808 | RTL_R16(CPlusCmd); | |
809 | ||
810 | spin_unlock_irqrestore(&tp->lock, flags); | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
815 | #ifdef CONFIG_R8169_VLAN | |
816 | ||
817 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, | |
818 | struct sk_buff *skb) | |
819 | { | |
820 | return (tp->vlgrp && vlan_tx_tag_present(skb)) ? | |
821 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; | |
822 | } | |
823 | ||
824 | static void rtl8169_vlan_rx_register(struct net_device *dev, | |
825 | struct vlan_group *grp) | |
826 | { | |
827 | struct rtl8169_private *tp = netdev_priv(dev); | |
828 | void __iomem *ioaddr = tp->mmio_addr; | |
829 | unsigned long flags; | |
830 | ||
831 | spin_lock_irqsave(&tp->lock, flags); | |
832 | tp->vlgrp = grp; | |
833 | if (tp->vlgrp) | |
834 | tp->cp_cmd |= RxVlan; | |
835 | else | |
836 | tp->cp_cmd &= ~RxVlan; | |
837 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
838 | RTL_R16(CPlusCmd); | |
839 | spin_unlock_irqrestore(&tp->lock, flags); | |
840 | } | |
841 | ||
1da177e4 LT |
842 | static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
843 | struct sk_buff *skb) | |
844 | { | |
845 | u32 opts2 = le32_to_cpu(desc->opts2); | |
846 | int ret; | |
847 | ||
848 | if (tp->vlgrp && (opts2 & RxVlanTag)) { | |
07d3f51f | 849 | rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff)); |
1da177e4 LT |
850 | ret = 0; |
851 | } else | |
852 | ret = -1; | |
853 | desc->opts2 = 0; | |
854 | return ret; | |
855 | } | |
856 | ||
857 | #else /* !CONFIG_R8169_VLAN */ | |
858 | ||
859 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, | |
860 | struct sk_buff *skb) | |
861 | { | |
862 | return 0; | |
863 | } | |
864 | ||
865 | static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, | |
866 | struct sk_buff *skb) | |
867 | { | |
868 | return -1; | |
869 | } | |
870 | ||
871 | #endif | |
872 | ||
873 | static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) | |
874 | { | |
875 | struct rtl8169_private *tp = netdev_priv(dev); | |
876 | void __iomem *ioaddr = tp->mmio_addr; | |
877 | u32 status; | |
878 | ||
879 | cmd->supported = | |
880 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
881 | cmd->port = PORT_FIBRE; | |
882 | cmd->transceiver = XCVR_INTERNAL; | |
883 | ||
884 | status = RTL_R32(TBICSR); | |
885 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
886 | cmd->autoneg = !!(status & TBINwEnable); | |
887 | ||
888 | cmd->speed = SPEED_1000; | |
889 | cmd->duplex = DUPLEX_FULL; /* Always set */ | |
890 | } | |
891 | ||
892 | static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) | |
893 | { | |
894 | struct rtl8169_private *tp = netdev_priv(dev); | |
895 | void __iomem *ioaddr = tp->mmio_addr; | |
896 | u8 status; | |
897 | ||
898 | cmd->supported = SUPPORTED_10baseT_Half | | |
899 | SUPPORTED_10baseT_Full | | |
900 | SUPPORTED_100baseT_Half | | |
901 | SUPPORTED_100baseT_Full | | |
902 | SUPPORTED_1000baseT_Full | | |
903 | SUPPORTED_Autoneg | | |
5b0384f4 | 904 | SUPPORTED_TP; |
1da177e4 LT |
905 | |
906 | cmd->autoneg = 1; | |
907 | cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg; | |
908 | ||
64e4bfb4 | 909 | if (tp->phy_auto_nego_reg & ADVERTISE_10HALF) |
1da177e4 | 910 | cmd->advertising |= ADVERTISED_10baseT_Half; |
64e4bfb4 | 911 | if (tp->phy_auto_nego_reg & ADVERTISE_10FULL) |
1da177e4 | 912 | cmd->advertising |= ADVERTISED_10baseT_Full; |
64e4bfb4 | 913 | if (tp->phy_auto_nego_reg & ADVERTISE_100HALF) |
1da177e4 | 914 | cmd->advertising |= ADVERTISED_100baseT_Half; |
64e4bfb4 | 915 | if (tp->phy_auto_nego_reg & ADVERTISE_100FULL) |
1da177e4 | 916 | cmd->advertising |= ADVERTISED_100baseT_Full; |
64e4bfb4 | 917 | if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL) |
1da177e4 LT |
918 | cmd->advertising |= ADVERTISED_1000baseT_Full; |
919 | ||
920 | status = RTL_R8(PHYstatus); | |
921 | ||
922 | if (status & _1000bpsF) | |
923 | cmd->speed = SPEED_1000; | |
924 | else if (status & _100bps) | |
925 | cmd->speed = SPEED_100; | |
926 | else if (status & _10bps) | |
927 | cmd->speed = SPEED_10; | |
928 | ||
623a1593 FR |
929 | if (status & TxFlowCtrl) |
930 | cmd->advertising |= ADVERTISED_Asym_Pause; | |
931 | if (status & RxFlowCtrl) | |
932 | cmd->advertising |= ADVERTISED_Pause; | |
933 | ||
1da177e4 LT |
934 | cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ? |
935 | DUPLEX_FULL : DUPLEX_HALF; | |
936 | } | |
937 | ||
938 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
939 | { | |
940 | struct rtl8169_private *tp = netdev_priv(dev); | |
941 | unsigned long flags; | |
942 | ||
943 | spin_lock_irqsave(&tp->lock, flags); | |
944 | ||
945 | tp->get_settings(dev, cmd); | |
946 | ||
947 | spin_unlock_irqrestore(&tp->lock, flags); | |
948 | return 0; | |
949 | } | |
950 | ||
951 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
952 | void *p) | |
953 | { | |
5b0384f4 FR |
954 | struct rtl8169_private *tp = netdev_priv(dev); |
955 | unsigned long flags; | |
1da177e4 | 956 | |
5b0384f4 FR |
957 | if (regs->len > R8169_REGS_SIZE) |
958 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 959 | |
5b0384f4 FR |
960 | spin_lock_irqsave(&tp->lock, flags); |
961 | memcpy_fromio(p, tp->mmio_addr, regs->len); | |
962 | spin_unlock_irqrestore(&tp->lock, flags); | |
1da177e4 LT |
963 | } |
964 | ||
b57b7e5a SH |
965 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
966 | { | |
967 | struct rtl8169_private *tp = netdev_priv(dev); | |
968 | ||
969 | return tp->msg_enable; | |
970 | } | |
971 | ||
972 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
973 | { | |
974 | struct rtl8169_private *tp = netdev_priv(dev); | |
975 | ||
976 | tp->msg_enable = value; | |
977 | } | |
978 | ||
d4a3a0fc SH |
979 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
980 | "tx_packets", | |
981 | "rx_packets", | |
982 | "tx_errors", | |
983 | "rx_errors", | |
984 | "rx_missed", | |
985 | "align_errors", | |
986 | "tx_single_collisions", | |
987 | "tx_multi_collisions", | |
988 | "unicast", | |
989 | "broadcast", | |
990 | "multicast", | |
991 | "tx_aborted", | |
992 | "tx_underrun", | |
993 | }; | |
994 | ||
995 | struct rtl8169_counters { | |
b1eab701 AV |
996 | __le64 tx_packets; |
997 | __le64 rx_packets; | |
998 | __le64 tx_errors; | |
999 | __le32 rx_errors; | |
1000 | __le16 rx_missed; | |
1001 | __le16 align_errors; | |
1002 | __le32 tx_one_collision; | |
1003 | __le32 tx_multi_collision; | |
1004 | __le64 rx_unicast; | |
1005 | __le64 rx_broadcast; | |
1006 | __le32 rx_multicast; | |
1007 | __le16 tx_aborted; | |
1008 | __le16 tx_underun; | |
d4a3a0fc SH |
1009 | }; |
1010 | ||
b9f2c044 | 1011 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1012 | { |
b9f2c044 JG |
1013 | switch (sset) { |
1014 | case ETH_SS_STATS: | |
1015 | return ARRAY_SIZE(rtl8169_gstrings); | |
1016 | default: | |
1017 | return -EOPNOTSUPP; | |
1018 | } | |
d4a3a0fc SH |
1019 | } |
1020 | ||
1021 | static void rtl8169_get_ethtool_stats(struct net_device *dev, | |
1022 | struct ethtool_stats *stats, u64 *data) | |
1023 | { | |
1024 | struct rtl8169_private *tp = netdev_priv(dev); | |
1025 | void __iomem *ioaddr = tp->mmio_addr; | |
1026 | struct rtl8169_counters *counters; | |
1027 | dma_addr_t paddr; | |
1028 | u32 cmd; | |
1029 | ||
1030 | ASSERT_RTNL(); | |
1031 | ||
1032 | counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); | |
1033 | if (!counters) | |
1034 | return; | |
1035 | ||
1036 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
1037 | cmd = (u64)paddr & DMA_32BIT_MASK; | |
1038 | RTL_W32(CounterAddrLow, cmd); | |
1039 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1040 | ||
1041 | while (RTL_R32(CounterAddrLow) & CounterDump) { | |
1042 | if (msleep_interruptible(1)) | |
1043 | break; | |
1044 | } | |
1045 | ||
1046 | RTL_W32(CounterAddrLow, 0); | |
1047 | RTL_W32(CounterAddrHigh, 0); | |
1048 | ||
5b0384f4 | 1049 | data[0] = le64_to_cpu(counters->tx_packets); |
d4a3a0fc SH |
1050 | data[1] = le64_to_cpu(counters->rx_packets); |
1051 | data[2] = le64_to_cpu(counters->tx_errors); | |
1052 | data[3] = le32_to_cpu(counters->rx_errors); | |
1053 | data[4] = le16_to_cpu(counters->rx_missed); | |
1054 | data[5] = le16_to_cpu(counters->align_errors); | |
1055 | data[6] = le32_to_cpu(counters->tx_one_collision); | |
1056 | data[7] = le32_to_cpu(counters->tx_multi_collision); | |
1057 | data[8] = le64_to_cpu(counters->rx_unicast); | |
1058 | data[9] = le64_to_cpu(counters->rx_broadcast); | |
1059 | data[10] = le32_to_cpu(counters->rx_multicast); | |
1060 | data[11] = le16_to_cpu(counters->tx_aborted); | |
1061 | data[12] = le16_to_cpu(counters->tx_underun); | |
1062 | ||
1063 | pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); | |
1064 | } | |
1065 | ||
1066 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
1067 | { | |
1068 | switch(stringset) { | |
1069 | case ETH_SS_STATS: | |
1070 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1071 | break; | |
1072 | } | |
1073 | } | |
1074 | ||
7282d491 | 1075 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1076 | .get_drvinfo = rtl8169_get_drvinfo, |
1077 | .get_regs_len = rtl8169_get_regs_len, | |
1078 | .get_link = ethtool_op_get_link, | |
1079 | .get_settings = rtl8169_get_settings, | |
1080 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1081 | .get_msglevel = rtl8169_get_msglevel, |
1082 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 LT |
1083 | .get_rx_csum = rtl8169_get_rx_csum, |
1084 | .set_rx_csum = rtl8169_set_rx_csum, | |
1da177e4 | 1085 | .set_tx_csum = ethtool_op_set_tx_csum, |
1da177e4 | 1086 | .set_sg = ethtool_op_set_sg, |
1da177e4 LT |
1087 | .set_tso = ethtool_op_set_tso, |
1088 | .get_regs = rtl8169_get_regs, | |
61a4dcc2 FR |
1089 | .get_wol = rtl8169_get_wol, |
1090 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1091 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1092 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1093 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
1da177e4 LT |
1094 | }; |
1095 | ||
07d3f51f FR |
1096 | static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, |
1097 | int bitnum, int bitval) | |
1da177e4 LT |
1098 | { |
1099 | int val; | |
1100 | ||
1101 | val = mdio_read(ioaddr, reg); | |
1102 | val = (bitval == 1) ? | |
1103 | val | (bitval << bitnum) : val & ~(0x0001 << bitnum); | |
5b0384f4 | 1104 | mdio_write(ioaddr, reg, val & 0xffff); |
1da177e4 LT |
1105 | } |
1106 | ||
07d3f51f FR |
1107 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
1108 | void __iomem *ioaddr) | |
1da177e4 | 1109 | { |
0e485150 FR |
1110 | /* |
1111 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1112 | * but they can be identified more specifically through the test below | |
1113 | * if needed: | |
1114 | * | |
1115 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1116 | * |
1117 | * Same thing for the 8101Eb and the 8101Ec: | |
1118 | * | |
1119 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1120 | */ |
1da177e4 LT |
1121 | const struct { |
1122 | u32 mask; | |
e3cf0cc0 | 1123 | u32 val; |
1da177e4 LT |
1124 | int mac_version; |
1125 | } mac_info[] = { | |
e3cf0cc0 FR |
1126 | /* 8168B family. */ |
1127 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, | |
1128 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, | |
1129 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
1130 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 }, | |
1131 | ||
1132 | /* 8168B family. */ | |
1133 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1134 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1135 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1136 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1137 | ||
1138 | /* 8101 family. */ | |
1139 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, | |
1140 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, | |
1141 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, | |
1142 | /* FIXME: where did these entries come from ? -- FR */ | |
1143 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1144 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1145 | ||
1146 | /* 8110 family. */ | |
1147 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1148 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1149 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1150 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1151 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
1152 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
1153 | ||
1154 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ | |
1da177e4 LT |
1155 | }, *p = mac_info; |
1156 | u32 reg; | |
1157 | ||
e3cf0cc0 FR |
1158 | reg = RTL_R32(TxConfig); |
1159 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
1160 | p++; |
1161 | tp->mac_version = p->mac_version; | |
e3cf0cc0 FR |
1162 | |
1163 | if (p->mask == 0x00000000) { | |
1164 | struct pci_dev *pdev = tp->pci_dev; | |
1165 | ||
1166 | dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg); | |
1167 | } | |
1da177e4 LT |
1168 | } |
1169 | ||
1170 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
1171 | { | |
bcf0bf90 | 1172 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
1173 | } |
1174 | ||
867763c1 FR |
1175 | struct phy_reg { |
1176 | u16 reg; | |
1177 | u16 val; | |
1178 | }; | |
1179 | ||
1180 | static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) | |
1181 | { | |
1182 | while (len-- > 0) { | |
1183 | mdio_write(ioaddr, regs->reg, regs->val); | |
1184 | regs++; | |
1185 | } | |
1186 | } | |
1187 | ||
5615d9f1 | 1188 | static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
1da177e4 | 1189 | { |
1da177e4 LT |
1190 | struct { |
1191 | u16 regs[5]; /* Beware of bit-sign propagation */ | |
1192 | } phy_magic[5] = { { | |
1193 | { 0x0000, //w 4 15 12 0 | |
1194 | 0x00a1, //w 3 15 0 00a1 | |
1195 | 0x0008, //w 2 15 0 0008 | |
1196 | 0x1020, //w 1 15 0 1020 | |
1197 | 0x1000 } },{ //w 0 15 0 1000 | |
1198 | { 0x7000, //w 4 15 12 7 | |
1199 | 0xff41, //w 3 15 0 ff41 | |
1200 | 0xde60, //w 2 15 0 de60 | |
1201 | 0x0140, //w 1 15 0 0140 | |
1202 | 0x0077 } },{ //w 0 15 0 0077 | |
1203 | { 0xa000, //w 4 15 12 a | |
1204 | 0xdf01, //w 3 15 0 df01 | |
1205 | 0xdf20, //w 2 15 0 df20 | |
1206 | 0xff95, //w 1 15 0 ff95 | |
1207 | 0xfa00 } },{ //w 0 15 0 fa00 | |
1208 | { 0xb000, //w 4 15 12 b | |
1209 | 0xff41, //w 3 15 0 ff41 | |
1210 | 0xde20, //w 2 15 0 de20 | |
1211 | 0x0140, //w 1 15 0 0140 | |
1212 | 0x00bb } },{ //w 0 15 0 00bb | |
1213 | { 0xf000, //w 4 15 12 f | |
1214 | 0xdf01, //w 3 15 0 df01 | |
1215 | 0xdf20, //w 2 15 0 df20 | |
1216 | 0xff95, //w 1 15 0 ff95 | |
1217 | 0xbf00 } //w 0 15 0 bf00 | |
1218 | } | |
1219 | }, *p = phy_magic; | |
07d3f51f | 1220 | unsigned int i; |
1da177e4 | 1221 | |
a441d7b6 FR |
1222 | mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 |
1223 | mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 | |
1224 | mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 | |
1da177e4 LT |
1225 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
1226 | ||
1227 | for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { | |
1228 | int val, pos = 4; | |
1229 | ||
1230 | val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); | |
1231 | mdio_write(ioaddr, pos, val); | |
1232 | while (--pos >= 0) | |
1233 | mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); | |
1234 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 | |
1235 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 | |
1236 | } | |
a441d7b6 | 1237 | mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 |
1da177e4 LT |
1238 | } |
1239 | ||
5615d9f1 FR |
1240 | static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
1241 | { | |
a441d7b6 FR |
1242 | struct phy_reg phy_reg_init[] = { |
1243 | { 0x1f, 0x0002 }, | |
1244 | { 0x01, 0x90d0 }, | |
1245 | { 0x1f, 0x0000 } | |
1246 | }; | |
1247 | ||
1248 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
5615d9f1 | 1249 | } |
7da97ec9 FR |
1250 | static void rtl8168b_hw_phy_config(void __iomem *ioaddr) |
1251 | { | |
1252 | struct phy_reg phy_reg_init[] = { | |
1253 | { 0x1f, 0x0000 }, | |
1254 | { 0x10, 0xf41b }, | |
1255 | { 0x1f, 0x0000 } | |
1256 | }; | |
1257 | ||
1258 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1259 | } | |
5615d9f1 | 1260 | |
867763c1 FR |
1261 | static void rtl8168cp_hw_phy_config(void __iomem *ioaddr) |
1262 | { | |
1263 | struct phy_reg phy_reg_init[] = { | |
1264 | { 0x1f, 0x0000 }, | |
1265 | { 0x1d, 0x0f00 }, | |
1266 | { 0x1f, 0x0002 }, | |
1267 | { 0x0c, 0x1ec8 }, | |
1268 | { 0x1f, 0x0000 } | |
1269 | }; | |
1270 | ||
1271 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1272 | } | |
1273 | ||
1274 | static void rtl8168c_hw_phy_config(void __iomem *ioaddr) | |
1275 | { | |
1276 | struct phy_reg phy_reg_init[] = { | |
a3f80671 FR |
1277 | { 0x1f, 0x0001 }, |
1278 | { 0x12, 0x2300 }, | |
867763c1 FR |
1279 | { 0x1f, 0x0002 }, |
1280 | { 0x00, 0x88d4 }, | |
1281 | { 0x01, 0x82b1 }, | |
1282 | { 0x03, 0x7002 }, | |
1283 | { 0x08, 0x9e30 }, | |
1284 | { 0x09, 0x01f0 }, | |
1285 | { 0x0a, 0x5500 }, | |
1286 | { 0x0c, 0x00c8 }, | |
1287 | { 0x1f, 0x0003 }, | |
1288 | { 0x12, 0xc096 }, | |
1289 | { 0x16, 0x000a }, | |
1290 | { 0x1f, 0x0000 } | |
1291 | }; | |
1292 | ||
1293 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1294 | } | |
1295 | ||
7da97ec9 FR |
1296 | static void rtl8168cx_hw_phy_config(void __iomem *ioaddr) |
1297 | { | |
1298 | struct phy_reg phy_reg_init[] = { | |
1299 | { 0x1f, 0x0000 }, | |
1300 | { 0x12, 0x2300 }, | |
1301 | { 0x1f, 0x0003 }, | |
1302 | { 0x16, 0x0f0a }, | |
1303 | { 0x1f, 0x0000 }, | |
1304 | { 0x1f, 0x0002 }, | |
1305 | { 0x0c, 0x7eb8 }, | |
1306 | { 0x1f, 0x0000 } | |
1307 | }; | |
1308 | ||
1309 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1310 | } | |
1311 | ||
5615d9f1 FR |
1312 | static void rtl_hw_phy_config(struct net_device *dev) |
1313 | { | |
1314 | struct rtl8169_private *tp = netdev_priv(dev); | |
1315 | void __iomem *ioaddr = tp->mmio_addr; | |
1316 | ||
1317 | rtl8169_print_mac_version(tp); | |
1318 | ||
1319 | switch (tp->mac_version) { | |
1320 | case RTL_GIGA_MAC_VER_01: | |
1321 | break; | |
1322 | case RTL_GIGA_MAC_VER_02: | |
1323 | case RTL_GIGA_MAC_VER_03: | |
1324 | rtl8169s_hw_phy_config(ioaddr); | |
1325 | break; | |
1326 | case RTL_GIGA_MAC_VER_04: | |
1327 | rtl8169sb_hw_phy_config(ioaddr); | |
1328 | break; | |
7da97ec9 FR |
1329 | case RTL_GIGA_MAC_VER_11: |
1330 | case RTL_GIGA_MAC_VER_12: | |
1331 | case RTL_GIGA_MAC_VER_17: | |
1332 | rtl8168b_hw_phy_config(ioaddr); | |
1333 | break; | |
867763c1 FR |
1334 | case RTL_GIGA_MAC_VER_18: |
1335 | rtl8168cp_hw_phy_config(ioaddr); | |
1336 | break; | |
1337 | case RTL_GIGA_MAC_VER_19: | |
1338 | rtl8168c_hw_phy_config(ioaddr); | |
1339 | break; | |
7da97ec9 FR |
1340 | case RTL_GIGA_MAC_VER_20: |
1341 | rtl8168cx_hw_phy_config(ioaddr); | |
1342 | break; | |
5615d9f1 FR |
1343 | default: |
1344 | break; | |
1345 | } | |
1346 | } | |
1347 | ||
1da177e4 LT |
1348 | static void rtl8169_phy_timer(unsigned long __opaque) |
1349 | { | |
1350 | struct net_device *dev = (struct net_device *)__opaque; | |
1351 | struct rtl8169_private *tp = netdev_priv(dev); | |
1352 | struct timer_list *timer = &tp->timer; | |
1353 | void __iomem *ioaddr = tp->mmio_addr; | |
1354 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
1355 | ||
bcf0bf90 | 1356 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 1357 | |
64e4bfb4 | 1358 | if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
1359 | return; |
1360 | ||
1361 | spin_lock_irq(&tp->lock); | |
1362 | ||
1363 | if (tp->phy_reset_pending(ioaddr)) { | |
5b0384f4 | 1364 | /* |
1da177e4 LT |
1365 | * A busy loop could burn quite a few cycles on nowadays CPU. |
1366 | * Let's delay the execution of the timer for a few ticks. | |
1367 | */ | |
1368 | timeout = HZ/10; | |
1369 | goto out_mod_timer; | |
1370 | } | |
1371 | ||
1372 | if (tp->link_ok(ioaddr)) | |
1373 | goto out_unlock; | |
1374 | ||
b57b7e5a SH |
1375 | if (netif_msg_link(tp)) |
1376 | printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); | |
1da177e4 LT |
1377 | |
1378 | tp->phy_reset_enable(ioaddr); | |
1379 | ||
1380 | out_mod_timer: | |
1381 | mod_timer(timer, jiffies + timeout); | |
1382 | out_unlock: | |
1383 | spin_unlock_irq(&tp->lock); | |
1384 | } | |
1385 | ||
1386 | static inline void rtl8169_delete_timer(struct net_device *dev) | |
1387 | { | |
1388 | struct rtl8169_private *tp = netdev_priv(dev); | |
1389 | struct timer_list *timer = &tp->timer; | |
1390 | ||
e179bb7b | 1391 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
1392 | return; |
1393 | ||
1394 | del_timer_sync(timer); | |
1395 | } | |
1396 | ||
1397 | static inline void rtl8169_request_timer(struct net_device *dev) | |
1398 | { | |
1399 | struct rtl8169_private *tp = netdev_priv(dev); | |
1400 | struct timer_list *timer = &tp->timer; | |
1401 | ||
e179bb7b | 1402 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
1403 | return; |
1404 | ||
2efa53f3 | 1405 | mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
1da177e4 LT |
1406 | } |
1407 | ||
1408 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1409 | /* | |
1410 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1411 | * without having to re-enable interrupts. It's not called while | |
1412 | * the interrupt routine is executing. | |
1413 | */ | |
1414 | static void rtl8169_netpoll(struct net_device *dev) | |
1415 | { | |
1416 | struct rtl8169_private *tp = netdev_priv(dev); | |
1417 | struct pci_dev *pdev = tp->pci_dev; | |
1418 | ||
1419 | disable_irq(pdev->irq); | |
7d12e780 | 1420 | rtl8169_interrupt(pdev->irq, dev); |
1da177e4 LT |
1421 | enable_irq(pdev->irq); |
1422 | } | |
1423 | #endif | |
1424 | ||
1425 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, | |
1426 | void __iomem *ioaddr) | |
1427 | { | |
1428 | iounmap(ioaddr); | |
1429 | pci_release_regions(pdev); | |
1430 | pci_disable_device(pdev); | |
1431 | free_netdev(dev); | |
1432 | } | |
1433 | ||
bf793295 FR |
1434 | static void rtl8169_phy_reset(struct net_device *dev, |
1435 | struct rtl8169_private *tp) | |
1436 | { | |
1437 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 1438 | unsigned int i; |
bf793295 FR |
1439 | |
1440 | tp->phy_reset_enable(ioaddr); | |
1441 | for (i = 0; i < 100; i++) { | |
1442 | if (!tp->phy_reset_pending(ioaddr)) | |
1443 | return; | |
1444 | msleep(1); | |
1445 | } | |
1446 | if (netif_msg_link(tp)) | |
1447 | printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); | |
1448 | } | |
1449 | ||
4ff96fa6 FR |
1450 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
1451 | { | |
1452 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 1453 | |
5615d9f1 | 1454 | rtl_hw_phy_config(dev); |
4ff96fa6 FR |
1455 | |
1456 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
1457 | RTL_W8(0x82, 0x01); | |
1458 | ||
6dccd16b FR |
1459 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
1460 | ||
1461 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
1462 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 1463 | |
bcf0bf90 | 1464 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
1465 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
1466 | RTL_W8(0x82, 0x01); | |
1467 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
1468 | mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 | |
1469 | } | |
1470 | ||
bf793295 FR |
1471 | rtl8169_phy_reset(dev, tp); |
1472 | ||
901dda2b FR |
1473 | /* |
1474 | * rtl8169_set_speed_xmii takes good care of the Fast Ethernet | |
1475 | * only 8101. Don't panic. | |
1476 | */ | |
1477 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); | |
4ff96fa6 FR |
1478 | |
1479 | if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) | |
1480 | printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); | |
1481 | } | |
1482 | ||
773d2021 FR |
1483 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
1484 | { | |
1485 | void __iomem *ioaddr = tp->mmio_addr; | |
1486 | u32 high; | |
1487 | u32 low; | |
1488 | ||
1489 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
1490 | high = addr[4] | (addr[5] << 8); | |
1491 | ||
1492 | spin_lock_irq(&tp->lock); | |
1493 | ||
1494 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
1495 | RTL_W32(MAC0, low); | |
1496 | RTL_W32(MAC4, high); | |
1497 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
1498 | ||
1499 | spin_unlock_irq(&tp->lock); | |
1500 | } | |
1501 | ||
1502 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
1503 | { | |
1504 | struct rtl8169_private *tp = netdev_priv(dev); | |
1505 | struct sockaddr *addr = p; | |
1506 | ||
1507 | if (!is_valid_ether_addr(addr->sa_data)) | |
1508 | return -EADDRNOTAVAIL; | |
1509 | ||
1510 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
1511 | ||
1512 | rtl_rar_set(tp, dev->dev_addr); | |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
5f787a1a FR |
1517 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1518 | { | |
1519 | struct rtl8169_private *tp = netdev_priv(dev); | |
1520 | struct mii_ioctl_data *data = if_mii(ifr); | |
1521 | ||
1522 | if (!netif_running(dev)) | |
1523 | return -ENODEV; | |
1524 | ||
1525 | switch (cmd) { | |
1526 | case SIOCGMIIPHY: | |
1527 | data->phy_id = 32; /* Internal PHY */ | |
1528 | return 0; | |
1529 | ||
1530 | case SIOCGMIIREG: | |
1531 | data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); | |
1532 | return 0; | |
1533 | ||
1534 | case SIOCSMIIREG: | |
1535 | if (!capable(CAP_NET_ADMIN)) | |
1536 | return -EPERM; | |
1537 | mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); | |
1538 | return 0; | |
1539 | } | |
1540 | return -EOPNOTSUPP; | |
1541 | } | |
1542 | ||
0e485150 FR |
1543 | static const struct rtl_cfg_info { |
1544 | void (*hw_start)(struct net_device *); | |
1545 | unsigned int region; | |
1546 | unsigned int align; | |
1547 | u16 intr_event; | |
1548 | u16 napi_event; | |
fbac58fc | 1549 | unsigned msi; |
0e485150 FR |
1550 | } rtl_cfg_infos [] = { |
1551 | [RTL_CFG_0] = { | |
1552 | .hw_start = rtl_hw_start_8169, | |
1553 | .region = 1, | |
e9f63f30 | 1554 | .align = 0, |
0e485150 FR |
1555 | .intr_event = SYSErr | LinkChg | RxOverflow | |
1556 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc FR |
1557 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
1558 | .msi = 0 | |
0e485150 FR |
1559 | }, |
1560 | [RTL_CFG_1] = { | |
1561 | .hw_start = rtl_hw_start_8168, | |
1562 | .region = 2, | |
1563 | .align = 8, | |
1564 | .intr_event = SYSErr | LinkChg | RxOverflow | | |
1565 | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc FR |
1566 | .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
1567 | .msi = RTL_FEATURE_MSI | |
0e485150 FR |
1568 | }, |
1569 | [RTL_CFG_2] = { | |
1570 | .hw_start = rtl_hw_start_8101, | |
1571 | .region = 2, | |
1572 | .align = 8, | |
1573 | .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | | |
1574 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc FR |
1575 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
1576 | .msi = RTL_FEATURE_MSI | |
0e485150 FR |
1577 | } |
1578 | }; | |
1579 | ||
fbac58fc FR |
1580 | /* Cfg9346_Unlock assumed. */ |
1581 | static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, | |
1582 | const struct rtl_cfg_info *cfg) | |
1583 | { | |
1584 | unsigned msi = 0; | |
1585 | u8 cfg2; | |
1586 | ||
1587 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
1588 | if (cfg->msi) { | |
1589 | if (pci_enable_msi(pdev)) { | |
1590 | dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); | |
1591 | } else { | |
1592 | cfg2 |= MSIEnable; | |
1593 | msi = RTL_FEATURE_MSI; | |
1594 | } | |
1595 | } | |
1596 | RTL_W8(Config2, cfg2); | |
1597 | return msi; | |
1598 | } | |
1599 | ||
1600 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) | |
1601 | { | |
1602 | if (tp->features & RTL_FEATURE_MSI) { | |
1603 | pci_disable_msi(pdev); | |
1604 | tp->features &= ~RTL_FEATURE_MSI; | |
1605 | } | |
1606 | } | |
1607 | ||
1da177e4 | 1608 | static int __devinit |
4ff96fa6 | 1609 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 1610 | { |
0e485150 FR |
1611 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
1612 | const unsigned int region = cfg->region; | |
1da177e4 | 1613 | struct rtl8169_private *tp; |
4ff96fa6 FR |
1614 | struct net_device *dev; |
1615 | void __iomem *ioaddr; | |
07d3f51f FR |
1616 | unsigned int i; |
1617 | int rc; | |
1da177e4 | 1618 | |
4ff96fa6 FR |
1619 | if (netif_msg_drv(&debug)) { |
1620 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
1621 | MODULENAME, RTL8169_VERSION); | |
1622 | } | |
1da177e4 | 1623 | |
1da177e4 | 1624 | dev = alloc_etherdev(sizeof (*tp)); |
4ff96fa6 | 1625 | if (!dev) { |
b57b7e5a | 1626 | if (netif_msg_drv(&debug)) |
9b91cf9d | 1627 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
4ff96fa6 FR |
1628 | rc = -ENOMEM; |
1629 | goto out; | |
1da177e4 LT |
1630 | } |
1631 | ||
1da177e4 LT |
1632 | SET_NETDEV_DEV(dev, &pdev->dev); |
1633 | tp = netdev_priv(dev); | |
c4028958 | 1634 | tp->dev = dev; |
b57b7e5a | 1635 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
1da177e4 LT |
1636 | |
1637 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ | |
1638 | rc = pci_enable_device(pdev); | |
b57b7e5a | 1639 | if (rc < 0) { |
2e8a538d | 1640 | if (netif_msg_probe(tp)) |
9b91cf9d | 1641 | dev_err(&pdev->dev, "enable failure\n"); |
4ff96fa6 | 1642 | goto err_out_free_dev_1; |
1da177e4 LT |
1643 | } |
1644 | ||
1645 | rc = pci_set_mwi(pdev); | |
1646 | if (rc < 0) | |
4ff96fa6 | 1647 | goto err_out_disable_2; |
1da177e4 | 1648 | |
1da177e4 | 1649 | /* make sure PCI base addr 1 is MMIO */ |
bcf0bf90 | 1650 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
4ff96fa6 | 1651 | if (netif_msg_probe(tp)) { |
9b91cf9d | 1652 | dev_err(&pdev->dev, |
bcf0bf90 FR |
1653 | "region #%d not an MMIO resource, aborting\n", |
1654 | region); | |
4ff96fa6 | 1655 | } |
1da177e4 | 1656 | rc = -ENODEV; |
4ff96fa6 | 1657 | goto err_out_mwi_3; |
1da177e4 | 1658 | } |
4ff96fa6 | 1659 | |
1da177e4 | 1660 | /* check for weird/broken PCI region reporting */ |
bcf0bf90 | 1661 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
4ff96fa6 | 1662 | if (netif_msg_probe(tp)) { |
9b91cf9d | 1663 | dev_err(&pdev->dev, |
4ff96fa6 FR |
1664 | "Invalid PCI region size(s), aborting\n"); |
1665 | } | |
1da177e4 | 1666 | rc = -ENODEV; |
4ff96fa6 | 1667 | goto err_out_mwi_3; |
1da177e4 LT |
1668 | } |
1669 | ||
1670 | rc = pci_request_regions(pdev, MODULENAME); | |
b57b7e5a | 1671 | if (rc < 0) { |
2e8a538d | 1672 | if (netif_msg_probe(tp)) |
9b91cf9d | 1673 | dev_err(&pdev->dev, "could not request regions.\n"); |
4ff96fa6 | 1674 | goto err_out_mwi_3; |
1da177e4 LT |
1675 | } |
1676 | ||
1677 | tp->cp_cmd = PCIMulRW | RxChkSum; | |
1678 | ||
1679 | if ((sizeof(dma_addr_t) > 4) && | |
1680 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) { | |
1681 | tp->cp_cmd |= PCIDAC; | |
1682 | dev->features |= NETIF_F_HIGHDMA; | |
1683 | } else { | |
1684 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1685 | if (rc < 0) { | |
4ff96fa6 | 1686 | if (netif_msg_probe(tp)) { |
9b91cf9d | 1687 | dev_err(&pdev->dev, |
4ff96fa6 FR |
1688 | "DMA configuration failed.\n"); |
1689 | } | |
1690 | goto err_out_free_res_4; | |
1da177e4 LT |
1691 | } |
1692 | } | |
1693 | ||
1694 | pci_set_master(pdev); | |
1695 | ||
1696 | /* ioremap MMIO region */ | |
bcf0bf90 | 1697 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
4ff96fa6 | 1698 | if (!ioaddr) { |
b57b7e5a | 1699 | if (netif_msg_probe(tp)) |
9b91cf9d | 1700 | dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
1da177e4 | 1701 | rc = -EIO; |
4ff96fa6 | 1702 | goto err_out_free_res_4; |
1da177e4 LT |
1703 | } |
1704 | ||
1705 | /* Unneeded ? Don't mess with Mrs. Murphy. */ | |
1706 | rtl8169_irq_mask_and_ack(ioaddr); | |
1707 | ||
1708 | /* Soft reset the chip. */ | |
1709 | RTL_W8(ChipCmd, CmdReset); | |
1710 | ||
1711 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 1712 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
1713 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
1714 | break; | |
b518fa8e | 1715 | msleep_interruptible(1); |
1da177e4 LT |
1716 | } |
1717 | ||
1718 | /* Identify chip attached to board */ | |
1719 | rtl8169_get_mac_version(tp, ioaddr); | |
1da177e4 LT |
1720 | |
1721 | rtl8169_print_mac_version(tp); | |
1da177e4 LT |
1722 | |
1723 | for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) { | |
1724 | if (tp->mac_version == rtl_chip_info[i].mac_version) | |
1725 | break; | |
1726 | } | |
1727 | if (i < 0) { | |
1728 | /* Unknown chip: assume array element #0, original RTL-8169 */ | |
b57b7e5a | 1729 | if (netif_msg_probe(tp)) { |
2e8a538d | 1730 | dev_printk(KERN_DEBUG, &pdev->dev, |
4ff96fa6 FR |
1731 | "unknown chip version, assuming %s\n", |
1732 | rtl_chip_info[0].name); | |
b57b7e5a | 1733 | } |
1da177e4 LT |
1734 | i++; |
1735 | } | |
1736 | tp->chipset = i; | |
1737 | ||
5d06a99f FR |
1738 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1739 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
1740 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
fbac58fc | 1741 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
5d06a99f FR |
1742 | RTL_W8(Cfg9346, Cfg9346_Lock); |
1743 | ||
1da177e4 LT |
1744 | if (RTL_R8(PHYstatus) & TBI_Enable) { |
1745 | tp->set_speed = rtl8169_set_speed_tbi; | |
1746 | tp->get_settings = rtl8169_gset_tbi; | |
1747 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
1748 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
1749 | tp->link_ok = rtl8169_tbi_link_ok; | |
1750 | ||
64e4bfb4 | 1751 | tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
1da177e4 LT |
1752 | } else { |
1753 | tp->set_speed = rtl8169_set_speed_xmii; | |
1754 | tp->get_settings = rtl8169_gset_xmii; | |
1755 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
1756 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
1757 | tp->link_ok = rtl8169_xmii_link_ok; | |
5f787a1a FR |
1758 | |
1759 | dev->do_ioctl = rtl8169_ioctl; | |
1da177e4 LT |
1760 | } |
1761 | ||
1762 | /* Get MAC address. FIXME: read EEPROM */ | |
1763 | for (i = 0; i < MAC_ADDR_LEN; i++) | |
1764 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6d6525b7 | 1765 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
1766 | |
1767 | dev->open = rtl8169_open; | |
1768 | dev->hard_start_xmit = rtl8169_start_xmit; | |
1769 | dev->get_stats = rtl8169_get_stats; | |
1770 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); | |
1771 | dev->stop = rtl8169_close; | |
1772 | dev->tx_timeout = rtl8169_tx_timeout; | |
07ce4064 | 1773 | dev->set_multicast_list = rtl_set_rx_mode; |
1da177e4 LT |
1774 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
1775 | dev->irq = pdev->irq; | |
1776 | dev->base_addr = (unsigned long) ioaddr; | |
1777 | dev->change_mtu = rtl8169_change_mtu; | |
773d2021 | 1778 | dev->set_mac_address = rtl_set_mac_address; |
1da177e4 LT |
1779 | |
1780 | #ifdef CONFIG_R8169_NAPI | |
bea3348e | 1781 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
1da177e4 LT |
1782 | #endif |
1783 | ||
1784 | #ifdef CONFIG_R8169_VLAN | |
1785 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
1786 | dev->vlan_rx_register = rtl8169_vlan_rx_register; | |
1da177e4 LT |
1787 | #endif |
1788 | ||
1789 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1790 | dev->poll_controller = rtl8169_netpoll; | |
1791 | #endif | |
1792 | ||
1793 | tp->intr_mask = 0xffff; | |
1794 | tp->pci_dev = pdev; | |
1795 | tp->mmio_addr = ioaddr; | |
0e485150 FR |
1796 | tp->align = cfg->align; |
1797 | tp->hw_start = cfg->hw_start; | |
1798 | tp->intr_event = cfg->intr_event; | |
1799 | tp->napi_event = cfg->napi_event; | |
1da177e4 | 1800 | |
2efa53f3 FR |
1801 | init_timer(&tp->timer); |
1802 | tp->timer.data = (unsigned long) dev; | |
1803 | tp->timer.function = rtl8169_phy_timer; | |
1804 | ||
1da177e4 LT |
1805 | spin_lock_init(&tp->lock); |
1806 | ||
1807 | rc = register_netdev(dev); | |
4ff96fa6 | 1808 | if (rc < 0) |
fbac58fc | 1809 | goto err_out_msi_5; |
1da177e4 LT |
1810 | |
1811 | pci_set_drvdata(pdev, dev); | |
1812 | ||
b57b7e5a | 1813 | if (netif_msg_probe(tp)) { |
96b9709c FR |
1814 | u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff; |
1815 | ||
b57b7e5a SH |
1816 | printk(KERN_INFO "%s: %s at 0x%lx, " |
1817 | "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " | |
96b9709c | 1818 | "XID %08x IRQ %d\n", |
b57b7e5a | 1819 | dev->name, |
bcf0bf90 | 1820 | rtl_chip_info[tp->chipset].name, |
b57b7e5a SH |
1821 | dev->base_addr, |
1822 | dev->dev_addr[0], dev->dev_addr[1], | |
1823 | dev->dev_addr[2], dev->dev_addr[3], | |
96b9709c | 1824 | dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
b57b7e5a | 1825 | } |
1da177e4 | 1826 | |
4ff96fa6 | 1827 | rtl8169_init_phy(dev, tp); |
1da177e4 | 1828 | |
4ff96fa6 FR |
1829 | out: |
1830 | return rc; | |
1da177e4 | 1831 | |
fbac58fc FR |
1832 | err_out_msi_5: |
1833 | rtl_disable_msi(pdev, tp); | |
4ff96fa6 FR |
1834 | iounmap(ioaddr); |
1835 | err_out_free_res_4: | |
1836 | pci_release_regions(pdev); | |
1837 | err_out_mwi_3: | |
1838 | pci_clear_mwi(pdev); | |
1839 | err_out_disable_2: | |
1840 | pci_disable_device(pdev); | |
1841 | err_out_free_dev_1: | |
1842 | free_netdev(dev); | |
1843 | goto out; | |
1da177e4 LT |
1844 | } |
1845 | ||
07d3f51f | 1846 | static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
1847 | { |
1848 | struct net_device *dev = pci_get_drvdata(pdev); | |
1849 | struct rtl8169_private *tp = netdev_priv(dev); | |
1850 | ||
eb2a021c FR |
1851 | flush_scheduled_work(); |
1852 | ||
1da177e4 | 1853 | unregister_netdev(dev); |
fbac58fc | 1854 | rtl_disable_msi(pdev, tp); |
1da177e4 LT |
1855 | rtl8169_release_board(pdev, dev, tp->mmio_addr); |
1856 | pci_set_drvdata(pdev, NULL); | |
1857 | } | |
1858 | ||
1da177e4 LT |
1859 | static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
1860 | struct net_device *dev) | |
1861 | { | |
1862 | unsigned int mtu = dev->mtu; | |
1863 | ||
1864 | tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; | |
1865 | } | |
1866 | ||
1867 | static int rtl8169_open(struct net_device *dev) | |
1868 | { | |
1869 | struct rtl8169_private *tp = netdev_priv(dev); | |
1870 | struct pci_dev *pdev = tp->pci_dev; | |
99f252b0 | 1871 | int retval = -ENOMEM; |
1da177e4 | 1872 | |
1da177e4 | 1873 | |
99f252b0 | 1874 | rtl8169_set_rxbufsize(tp, dev); |
1da177e4 LT |
1875 | |
1876 | /* | |
1877 | * Rx and Tx desscriptors needs 256 bytes alignment. | |
1878 | * pci_alloc_consistent provides more. | |
1879 | */ | |
1880 | tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, | |
1881 | &tp->TxPhyAddr); | |
1882 | if (!tp->TxDescArray) | |
99f252b0 | 1883 | goto out; |
1da177e4 LT |
1884 | |
1885 | tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, | |
1886 | &tp->RxPhyAddr); | |
1887 | if (!tp->RxDescArray) | |
99f252b0 | 1888 | goto err_free_tx_0; |
1da177e4 LT |
1889 | |
1890 | retval = rtl8169_init_ring(dev); | |
1891 | if (retval < 0) | |
99f252b0 | 1892 | goto err_free_rx_1; |
1da177e4 | 1893 | |
c4028958 | 1894 | INIT_DELAYED_WORK(&tp->task, NULL); |
1da177e4 | 1895 | |
99f252b0 FR |
1896 | smp_mb(); |
1897 | ||
fbac58fc FR |
1898 | retval = request_irq(dev->irq, rtl8169_interrupt, |
1899 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, | |
99f252b0 FR |
1900 | dev->name, dev); |
1901 | if (retval < 0) | |
1902 | goto err_release_ring_2; | |
1903 | ||
bea3348e SH |
1904 | #ifdef CONFIG_R8169_NAPI |
1905 | napi_enable(&tp->napi); | |
1906 | #endif | |
1907 | ||
07ce4064 | 1908 | rtl_hw_start(dev); |
1da177e4 LT |
1909 | |
1910 | rtl8169_request_timer(dev); | |
1911 | ||
1912 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
1913 | out: | |
1914 | return retval; | |
1915 | ||
99f252b0 FR |
1916 | err_release_ring_2: |
1917 | rtl8169_rx_clear(tp); | |
1918 | err_free_rx_1: | |
1da177e4 LT |
1919 | pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
1920 | tp->RxPhyAddr); | |
99f252b0 | 1921 | err_free_tx_0: |
1da177e4 LT |
1922 | pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
1923 | tp->TxPhyAddr); | |
1da177e4 LT |
1924 | goto out; |
1925 | } | |
1926 | ||
1927 | static void rtl8169_hw_reset(void __iomem *ioaddr) | |
1928 | { | |
1929 | /* Disable interrupts */ | |
1930 | rtl8169_irq_mask_and_ack(ioaddr); | |
1931 | ||
1932 | /* Reset the chipset */ | |
1933 | RTL_W8(ChipCmd, CmdReset); | |
1934 | ||
1935 | /* PCI commit */ | |
1936 | RTL_R8(ChipCmd); | |
1937 | } | |
1938 | ||
7f796d83 | 1939 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
1940 | { |
1941 | void __iomem *ioaddr = tp->mmio_addr; | |
1942 | u32 cfg = rtl8169_rx_config; | |
1943 | ||
1944 | cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
1945 | RTL_W32(RxConfig, cfg); | |
1946 | ||
1947 | /* Set DMA burst size and Interframe Gap Time */ | |
1948 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
1949 | (InterFrameGap << TxInterFrameGapShift)); | |
1950 | } | |
1951 | ||
07ce4064 | 1952 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
1953 | { |
1954 | struct rtl8169_private *tp = netdev_priv(dev); | |
1955 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 1956 | unsigned int i; |
1da177e4 LT |
1957 | |
1958 | /* Soft reset the chip. */ | |
1959 | RTL_W8(ChipCmd, CmdReset); | |
1960 | ||
1961 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 1962 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
1963 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
1964 | break; | |
b518fa8e | 1965 | msleep_interruptible(1); |
1da177e4 LT |
1966 | } |
1967 | ||
07ce4064 FR |
1968 | tp->hw_start(dev); |
1969 | ||
07ce4064 FR |
1970 | netif_start_queue(dev); |
1971 | } | |
1972 | ||
1973 | ||
7f796d83 FR |
1974 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
1975 | void __iomem *ioaddr) | |
1976 | { | |
1977 | /* | |
1978 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
1979 | * register to be written before TxDescAddrLow to work. | |
1980 | * Switching from MMIO to I/O access fixes the issue as well. | |
1981 | */ | |
1982 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
1983 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK); | |
1984 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); | |
1985 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK); | |
1986 | } | |
1987 | ||
1988 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
1989 | { | |
1990 | u16 cmd; | |
1991 | ||
1992 | cmd = RTL_R16(CPlusCmd); | |
1993 | RTL_W16(CPlusCmd, cmd); | |
1994 | return cmd; | |
1995 | } | |
1996 | ||
1997 | static void rtl_set_rx_max_size(void __iomem *ioaddr) | |
1998 | { | |
1999 | /* Low hurts. Let's disable the filtering. */ | |
2000 | RTL_W16(RxMaxSize, 16383); | |
2001 | } | |
2002 | ||
6dccd16b FR |
2003 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
2004 | { | |
2005 | struct { | |
2006 | u32 mac_version; | |
2007 | u32 clk; | |
2008 | u32 val; | |
2009 | } cfg2_info [] = { | |
2010 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
2011 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
2012 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
2013 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
2014 | }, *p = cfg2_info; | |
2015 | unsigned int i; | |
2016 | u32 clk; | |
2017 | ||
2018 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
2019 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) { | |
2020 | if ((p->mac_version == mac_version) && (p->clk == clk)) { | |
2021 | RTL_W32(0x7c, p->val); | |
2022 | break; | |
2023 | } | |
2024 | } | |
2025 | } | |
2026 | ||
07ce4064 FR |
2027 | static void rtl_hw_start_8169(struct net_device *dev) |
2028 | { | |
2029 | struct rtl8169_private *tp = netdev_priv(dev); | |
2030 | void __iomem *ioaddr = tp->mmio_addr; | |
2031 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 2032 | |
9cb427b6 FR |
2033 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
2034 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
2035 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
2036 | } | |
2037 | ||
1da177e4 | 2038 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
9cb427b6 FR |
2039 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
2040 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
2041 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
2042 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
2043 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2044 | ||
1da177e4 LT |
2045 | RTL_W8(EarlyTxThres, EarlyTxThld); |
2046 | ||
7f796d83 | 2047 | rtl_set_rx_max_size(ioaddr); |
1da177e4 | 2048 | |
c946b304 FR |
2049 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
2050 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
2051 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
2052 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
2053 | rtl_set_rx_tx_config_registers(tp); | |
1da177e4 | 2054 | |
7f796d83 | 2055 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 2056 | |
bcf0bf90 FR |
2057 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
2058 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
06fa7358 | 2059 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 2060 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 2061 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
2062 | } |
2063 | ||
bcf0bf90 FR |
2064 | RTL_W16(CPlusCmd, tp->cp_cmd); |
2065 | ||
6dccd16b FR |
2066 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
2067 | ||
1da177e4 LT |
2068 | /* |
2069 | * Undocumented corner. Supposedly: | |
2070 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
2071 | */ | |
2072 | RTL_W16(IntrMitigate, 0x0000); | |
2073 | ||
7f796d83 | 2074 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 2075 | |
c946b304 FR |
2076 | if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
2077 | (tp->mac_version != RTL_GIGA_MAC_VER_02) && | |
2078 | (tp->mac_version != RTL_GIGA_MAC_VER_03) && | |
2079 | (tp->mac_version != RTL_GIGA_MAC_VER_04)) { | |
2080 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2081 | rtl_set_rx_tx_config_registers(tp); | |
2082 | } | |
2083 | ||
1da177e4 | 2084 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
2085 | |
2086 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
2087 | RTL_R8(IntrMask); | |
1da177e4 LT |
2088 | |
2089 | RTL_W32(RxMissed, 0); | |
2090 | ||
07ce4064 | 2091 | rtl_set_rx_mode(dev); |
1da177e4 LT |
2092 | |
2093 | /* no early-rx interrupts */ | |
2094 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
6dccd16b FR |
2095 | |
2096 | /* Enable all known interrupts by setting the interrupt mask. */ | |
0e485150 | 2097 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 2098 | } |
1da177e4 | 2099 | |
07ce4064 FR |
2100 | static void rtl_hw_start_8168(struct net_device *dev) |
2101 | { | |
2dd99530 FR |
2102 | struct rtl8169_private *tp = netdev_priv(dev); |
2103 | void __iomem *ioaddr = tp->mmio_addr; | |
0e485150 FR |
2104 | struct pci_dev *pdev = tp->pci_dev; |
2105 | u8 ctl; | |
2dd99530 FR |
2106 | |
2107 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
2108 | ||
2109 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2110 | ||
2111 | rtl_set_rx_max_size(ioaddr); | |
2112 | ||
0e485150 FR |
2113 | rtl_set_rx_tx_config_registers(tp); |
2114 | ||
2115 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; | |
2dd99530 FR |
2116 | |
2117 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2118 | ||
0e485150 FR |
2119 | /* Tx performance tweak. */ |
2120 | pci_read_config_byte(pdev, 0x69, &ctl); | |
2121 | ctl = (ctl & ~0x70) | 0x50; | |
2122 | pci_write_config_byte(pdev, 0x69, ctl); | |
2dd99530 | 2123 | |
0e485150 | 2124 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 2125 | |
0e485150 FR |
2126 | /* Work around for RxFIFO overflow. */ |
2127 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { | |
2128 | tp->intr_event |= RxFIFOOver | PCSTimeout; | |
2129 | tp->intr_event &= ~RxOverflow; | |
2130 | } | |
2131 | ||
2132 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 FR |
2133 | |
2134 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
2135 | ||
2136 | RTL_R8(IntrMask); | |
2137 | ||
2138 | RTL_W32(RxMissed, 0); | |
2139 | ||
2140 | rtl_set_rx_mode(dev); | |
2141 | ||
0e485150 FR |
2142 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
2143 | ||
2dd99530 | 2144 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
6dccd16b | 2145 | |
0e485150 | 2146 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 2147 | } |
1da177e4 | 2148 | |
07ce4064 FR |
2149 | static void rtl_hw_start_8101(struct net_device *dev) |
2150 | { | |
cdf1a608 FR |
2151 | struct rtl8169_private *tp = netdev_priv(dev); |
2152 | void __iomem *ioaddr = tp->mmio_addr; | |
2153 | struct pci_dev *pdev = tp->pci_dev; | |
2154 | ||
e3cf0cc0 FR |
2155 | if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
2156 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
cdf1a608 FR |
2157 | pci_write_config_word(pdev, 0x68, 0x00); |
2158 | pci_write_config_word(pdev, 0x69, 0x08); | |
2159 | } | |
2160 | ||
2161 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
2162 | ||
2163 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2164 | ||
2165 | rtl_set_rx_max_size(ioaddr); | |
2166 | ||
2167 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; | |
2168 | ||
2169 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2170 | ||
2171 | RTL_W16(IntrMitigate, 0x0000); | |
2172 | ||
2173 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2174 | ||
2175 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2176 | rtl_set_rx_tx_config_registers(tp); | |
2177 | ||
2178 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
2179 | ||
2180 | RTL_R8(IntrMask); | |
2181 | ||
2182 | RTL_W32(RxMissed, 0); | |
2183 | ||
2184 | rtl_set_rx_mode(dev); | |
2185 | ||
0e485150 FR |
2186 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
2187 | ||
cdf1a608 | 2188 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
6dccd16b | 2189 | |
0e485150 | 2190 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
2191 | } |
2192 | ||
2193 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
2194 | { | |
2195 | struct rtl8169_private *tp = netdev_priv(dev); | |
2196 | int ret = 0; | |
2197 | ||
2198 | if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) | |
2199 | return -EINVAL; | |
2200 | ||
2201 | dev->mtu = new_mtu; | |
2202 | ||
2203 | if (!netif_running(dev)) | |
2204 | goto out; | |
2205 | ||
2206 | rtl8169_down(dev); | |
2207 | ||
2208 | rtl8169_set_rxbufsize(tp, dev); | |
2209 | ||
2210 | ret = rtl8169_init_ring(dev); | |
2211 | if (ret < 0) | |
2212 | goto out; | |
2213 | ||
bea3348e SH |
2214 | #ifdef CONFIG_R8169_NAPI |
2215 | napi_enable(&tp->napi); | |
2216 | #endif | |
1da177e4 | 2217 | |
07ce4064 | 2218 | rtl_hw_start(dev); |
1da177e4 LT |
2219 | |
2220 | rtl8169_request_timer(dev); | |
2221 | ||
2222 | out: | |
2223 | return ret; | |
2224 | } | |
2225 | ||
2226 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
2227 | { | |
2228 | desc->addr = 0x0badbadbadbadbadull; | |
2229 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); | |
2230 | } | |
2231 | ||
2232 | static void rtl8169_free_rx_skb(struct rtl8169_private *tp, | |
2233 | struct sk_buff **sk_buff, struct RxDesc *desc) | |
2234 | { | |
2235 | struct pci_dev *pdev = tp->pci_dev; | |
2236 | ||
2237 | pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, | |
2238 | PCI_DMA_FROMDEVICE); | |
2239 | dev_kfree_skb(*sk_buff); | |
2240 | *sk_buff = NULL; | |
2241 | rtl8169_make_unusable_by_asic(desc); | |
2242 | } | |
2243 | ||
2244 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
2245 | { | |
2246 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
2247 | ||
2248 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
2249 | } | |
2250 | ||
2251 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
2252 | u32 rx_buf_sz) | |
2253 | { | |
2254 | desc->addr = cpu_to_le64(mapping); | |
2255 | wmb(); | |
2256 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
2257 | } | |
2258 | ||
15d31758 SH |
2259 | static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
2260 | struct net_device *dev, | |
2261 | struct RxDesc *desc, int rx_buf_sz, | |
2262 | unsigned int align) | |
1da177e4 LT |
2263 | { |
2264 | struct sk_buff *skb; | |
2265 | dma_addr_t mapping; | |
e9f63f30 | 2266 | unsigned int pad; |
1da177e4 | 2267 | |
e9f63f30 FR |
2268 | pad = align ? align : NET_IP_ALIGN; |
2269 | ||
2270 | skb = netdev_alloc_skb(dev, rx_buf_sz + pad); | |
1da177e4 LT |
2271 | if (!skb) |
2272 | goto err_out; | |
2273 | ||
e9f63f30 | 2274 | skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
1da177e4 | 2275 | |
689be439 | 2276 | mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
1da177e4 LT |
2277 | PCI_DMA_FROMDEVICE); |
2278 | ||
2279 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
1da177e4 | 2280 | out: |
15d31758 | 2281 | return skb; |
1da177e4 LT |
2282 | |
2283 | err_out: | |
1da177e4 LT |
2284 | rtl8169_make_unusable_by_asic(desc); |
2285 | goto out; | |
2286 | } | |
2287 | ||
2288 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
2289 | { | |
07d3f51f | 2290 | unsigned int i; |
1da177e4 LT |
2291 | |
2292 | for (i = 0; i < NUM_RX_DESC; i++) { | |
2293 | if (tp->Rx_skbuff[i]) { | |
2294 | rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, | |
2295 | tp->RxDescArray + i); | |
2296 | } | |
2297 | } | |
2298 | } | |
2299 | ||
2300 | static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, | |
2301 | u32 start, u32 end) | |
2302 | { | |
2303 | u32 cur; | |
5b0384f4 | 2304 | |
4ae47c2d | 2305 | for (cur = start; end - cur != 0; cur++) { |
15d31758 SH |
2306 | struct sk_buff *skb; |
2307 | unsigned int i = cur % NUM_RX_DESC; | |
1da177e4 | 2308 | |
4ae47c2d FR |
2309 | WARN_ON((s32)(end - cur) < 0); |
2310 | ||
1da177e4 LT |
2311 | if (tp->Rx_skbuff[i]) |
2312 | continue; | |
bcf0bf90 | 2313 | |
15d31758 SH |
2314 | skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
2315 | tp->RxDescArray + i, | |
2316 | tp->rx_buf_sz, tp->align); | |
2317 | if (!skb) | |
1da177e4 | 2318 | break; |
15d31758 SH |
2319 | |
2320 | tp->Rx_skbuff[i] = skb; | |
1da177e4 LT |
2321 | } |
2322 | return cur - start; | |
2323 | } | |
2324 | ||
2325 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) | |
2326 | { | |
2327 | desc->opts1 |= cpu_to_le32(RingEnd); | |
2328 | } | |
2329 | ||
2330 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) | |
2331 | { | |
2332 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
2333 | } | |
2334 | ||
2335 | static int rtl8169_init_ring(struct net_device *dev) | |
2336 | { | |
2337 | struct rtl8169_private *tp = netdev_priv(dev); | |
2338 | ||
2339 | rtl8169_init_ring_indexes(tp); | |
2340 | ||
2341 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
2342 | memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); | |
2343 | ||
2344 | if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) | |
2345 | goto err_out; | |
2346 | ||
2347 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); | |
2348 | ||
2349 | return 0; | |
2350 | ||
2351 | err_out: | |
2352 | rtl8169_rx_clear(tp); | |
2353 | return -ENOMEM; | |
2354 | } | |
2355 | ||
2356 | static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, | |
2357 | struct TxDesc *desc) | |
2358 | { | |
2359 | unsigned int len = tx_skb->len; | |
2360 | ||
2361 | pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); | |
2362 | desc->opts1 = 0x00; | |
2363 | desc->opts2 = 0x00; | |
2364 | desc->addr = 0x00; | |
2365 | tx_skb->len = 0; | |
2366 | } | |
2367 | ||
2368 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
2369 | { | |
2370 | unsigned int i; | |
2371 | ||
2372 | for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { | |
2373 | unsigned int entry = i % NUM_TX_DESC; | |
2374 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
2375 | unsigned int len = tx_skb->len; | |
2376 | ||
2377 | if (len) { | |
2378 | struct sk_buff *skb = tx_skb->skb; | |
2379 | ||
2380 | rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, | |
2381 | tp->TxDescArray + entry); | |
2382 | if (skb) { | |
2383 | dev_kfree_skb(skb); | |
2384 | tx_skb->skb = NULL; | |
2385 | } | |
cebf8cc7 | 2386 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
2387 | } |
2388 | } | |
2389 | tp->cur_tx = tp->dirty_tx = 0; | |
2390 | } | |
2391 | ||
c4028958 | 2392 | static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
1da177e4 LT |
2393 | { |
2394 | struct rtl8169_private *tp = netdev_priv(dev); | |
2395 | ||
c4028958 | 2396 | PREPARE_DELAYED_WORK(&tp->task, task); |
1da177e4 LT |
2397 | schedule_delayed_work(&tp->task, 4); |
2398 | } | |
2399 | ||
2400 | static void rtl8169_wait_for_quiescence(struct net_device *dev) | |
2401 | { | |
2402 | struct rtl8169_private *tp = netdev_priv(dev); | |
2403 | void __iomem *ioaddr = tp->mmio_addr; | |
2404 | ||
2405 | synchronize_irq(dev->irq); | |
2406 | ||
2407 | /* Wait for any pending NAPI task to complete */ | |
bea3348e SH |
2408 | #ifdef CONFIG_R8169_NAPI |
2409 | napi_disable(&tp->napi); | |
2410 | #endif | |
1da177e4 LT |
2411 | |
2412 | rtl8169_irq_mask_and_ack(ioaddr); | |
2413 | ||
bea3348e SH |
2414 | #ifdef CONFIG_R8169_NAPI |
2415 | napi_enable(&tp->napi); | |
2416 | #endif | |
1da177e4 LT |
2417 | } |
2418 | ||
c4028958 | 2419 | static void rtl8169_reinit_task(struct work_struct *work) |
1da177e4 | 2420 | { |
c4028958 DH |
2421 | struct rtl8169_private *tp = |
2422 | container_of(work, struct rtl8169_private, task.work); | |
2423 | struct net_device *dev = tp->dev; | |
1da177e4 LT |
2424 | int ret; |
2425 | ||
eb2a021c FR |
2426 | rtnl_lock(); |
2427 | ||
2428 | if (!netif_running(dev)) | |
2429 | goto out_unlock; | |
2430 | ||
2431 | rtl8169_wait_for_quiescence(dev); | |
2432 | rtl8169_close(dev); | |
1da177e4 LT |
2433 | |
2434 | ret = rtl8169_open(dev); | |
2435 | if (unlikely(ret < 0)) { | |
07d3f51f | 2436 | if (net_ratelimit() && netif_msg_drv(tp)) { |
53edbecd | 2437 | printk(KERN_ERR PFX "%s: reinit failure (status = %d)." |
07d3f51f | 2438 | " Rescheduling.\n", dev->name, ret); |
1da177e4 LT |
2439 | } |
2440 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
2441 | } | |
eb2a021c FR |
2442 | |
2443 | out_unlock: | |
2444 | rtnl_unlock(); | |
1da177e4 LT |
2445 | } |
2446 | ||
c4028958 | 2447 | static void rtl8169_reset_task(struct work_struct *work) |
1da177e4 | 2448 | { |
c4028958 DH |
2449 | struct rtl8169_private *tp = |
2450 | container_of(work, struct rtl8169_private, task.work); | |
2451 | struct net_device *dev = tp->dev; | |
1da177e4 | 2452 | |
eb2a021c FR |
2453 | rtnl_lock(); |
2454 | ||
1da177e4 | 2455 | if (!netif_running(dev)) |
eb2a021c | 2456 | goto out_unlock; |
1da177e4 LT |
2457 | |
2458 | rtl8169_wait_for_quiescence(dev); | |
2459 | ||
bea3348e | 2460 | rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
1da177e4 LT |
2461 | rtl8169_tx_clear(tp); |
2462 | ||
2463 | if (tp->dirty_rx == tp->cur_rx) { | |
2464 | rtl8169_init_ring_indexes(tp); | |
07ce4064 | 2465 | rtl_hw_start(dev); |
1da177e4 | 2466 | netif_wake_queue(dev); |
cebf8cc7 | 2467 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
1da177e4 | 2468 | } else { |
07d3f51f | 2469 | if (net_ratelimit() && netif_msg_intr(tp)) { |
53edbecd | 2470 | printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", |
07d3f51f | 2471 | dev->name); |
1da177e4 LT |
2472 | } |
2473 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
2474 | } | |
eb2a021c FR |
2475 | |
2476 | out_unlock: | |
2477 | rtnl_unlock(); | |
1da177e4 LT |
2478 | } |
2479 | ||
2480 | static void rtl8169_tx_timeout(struct net_device *dev) | |
2481 | { | |
2482 | struct rtl8169_private *tp = netdev_priv(dev); | |
2483 | ||
2484 | rtl8169_hw_reset(tp->mmio_addr); | |
2485 | ||
2486 | /* Let's wait a bit while any (async) irq lands on */ | |
2487 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
2488 | } | |
2489 | ||
2490 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
2491 | u32 opts1) | |
2492 | { | |
2493 | struct skb_shared_info *info = skb_shinfo(skb); | |
2494 | unsigned int cur_frag, entry; | |
a6343afb | 2495 | struct TxDesc * uninitialized_var(txd); |
1da177e4 LT |
2496 | |
2497 | entry = tp->cur_tx; | |
2498 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
2499 | skb_frag_t *frag = info->frags + cur_frag; | |
2500 | dma_addr_t mapping; | |
2501 | u32 status, len; | |
2502 | void *addr; | |
2503 | ||
2504 | entry = (entry + 1) % NUM_TX_DESC; | |
2505 | ||
2506 | txd = tp->TxDescArray + entry; | |
2507 | len = frag->size; | |
2508 | addr = ((void *) page_address(frag->page)) + frag->page_offset; | |
2509 | mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); | |
2510 | ||
2511 | /* anti gcc 2.95.3 bugware (sic) */ | |
2512 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
2513 | ||
2514 | txd->opts1 = cpu_to_le32(status); | |
2515 | txd->addr = cpu_to_le64(mapping); | |
2516 | ||
2517 | tp->tx_skb[entry].len = len; | |
2518 | } | |
2519 | ||
2520 | if (cur_frag) { | |
2521 | tp->tx_skb[entry].skb = skb; | |
2522 | txd->opts1 |= cpu_to_le32(LastFrag); | |
2523 | } | |
2524 | ||
2525 | return cur_frag; | |
2526 | } | |
2527 | ||
2528 | static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) | |
2529 | { | |
2530 | if (dev->features & NETIF_F_TSO) { | |
7967168c | 2531 | u32 mss = skb_shinfo(skb)->gso_size; |
1da177e4 LT |
2532 | |
2533 | if (mss) | |
2534 | return LargeSend | ((mss & MSSMask) << MSSShift); | |
2535 | } | |
84fa7933 | 2536 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 2537 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
2538 | |
2539 | if (ip->protocol == IPPROTO_TCP) | |
2540 | return IPCS | TCPCS; | |
2541 | else if (ip->protocol == IPPROTO_UDP) | |
2542 | return IPCS | UDPCS; | |
2543 | WARN_ON(1); /* we need a WARN() */ | |
2544 | } | |
2545 | return 0; | |
2546 | } | |
2547 | ||
2548 | static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
2549 | { | |
2550 | struct rtl8169_private *tp = netdev_priv(dev); | |
2551 | unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; | |
2552 | struct TxDesc *txd = tp->TxDescArray + entry; | |
2553 | void __iomem *ioaddr = tp->mmio_addr; | |
2554 | dma_addr_t mapping; | |
2555 | u32 status, len; | |
2556 | u32 opts1; | |
188f4af0 | 2557 | int ret = NETDEV_TX_OK; |
5b0384f4 | 2558 | |
1da177e4 | 2559 | if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
b57b7e5a SH |
2560 | if (netif_msg_drv(tp)) { |
2561 | printk(KERN_ERR | |
2562 | "%s: BUG! Tx Ring full when queue awake!\n", | |
2563 | dev->name); | |
2564 | } | |
1da177e4 LT |
2565 | goto err_stop; |
2566 | } | |
2567 | ||
2568 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
2569 | goto err_stop; | |
2570 | ||
2571 | opts1 = DescOwn | rtl8169_tso_csum(skb, dev); | |
2572 | ||
2573 | frags = rtl8169_xmit_frags(tp, skb, opts1); | |
2574 | if (frags) { | |
2575 | len = skb_headlen(skb); | |
2576 | opts1 |= FirstFrag; | |
2577 | } else { | |
2578 | len = skb->len; | |
2579 | ||
2580 | if (unlikely(len < ETH_ZLEN)) { | |
5b057c6b | 2581 | if (skb_padto(skb, ETH_ZLEN)) |
1da177e4 LT |
2582 | goto err_update_stats; |
2583 | len = ETH_ZLEN; | |
2584 | } | |
2585 | ||
2586 | opts1 |= FirstFrag | LastFrag; | |
2587 | tp->tx_skb[entry].skb = skb; | |
2588 | } | |
2589 | ||
2590 | mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); | |
2591 | ||
2592 | tp->tx_skb[entry].len = len; | |
2593 | txd->addr = cpu_to_le64(mapping); | |
2594 | txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); | |
2595 | ||
2596 | wmb(); | |
2597 | ||
2598 | /* anti gcc 2.95.3 bugware (sic) */ | |
2599 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
2600 | txd->opts1 = cpu_to_le32(status); | |
2601 | ||
2602 | dev->trans_start = jiffies; | |
2603 | ||
2604 | tp->cur_tx += frags + 1; | |
2605 | ||
2606 | smp_wmb(); | |
2607 | ||
275391a4 | 2608 | RTL_W8(TxPoll, NPQ); /* set polling bit */ |
1da177e4 LT |
2609 | |
2610 | if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { | |
2611 | netif_stop_queue(dev); | |
2612 | smp_rmb(); | |
2613 | if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) | |
2614 | netif_wake_queue(dev); | |
2615 | } | |
2616 | ||
2617 | out: | |
2618 | return ret; | |
2619 | ||
2620 | err_stop: | |
2621 | netif_stop_queue(dev); | |
188f4af0 | 2622 | ret = NETDEV_TX_BUSY; |
1da177e4 | 2623 | err_update_stats: |
cebf8cc7 | 2624 | dev->stats.tx_dropped++; |
1da177e4 LT |
2625 | goto out; |
2626 | } | |
2627 | ||
2628 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
2629 | { | |
2630 | struct rtl8169_private *tp = netdev_priv(dev); | |
2631 | struct pci_dev *pdev = tp->pci_dev; | |
2632 | void __iomem *ioaddr = tp->mmio_addr; | |
2633 | u16 pci_status, pci_cmd; | |
2634 | ||
2635 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
2636 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
2637 | ||
b57b7e5a SH |
2638 | if (netif_msg_intr(tp)) { |
2639 | printk(KERN_ERR | |
2640 | "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", | |
2641 | dev->name, pci_cmd, pci_status); | |
2642 | } | |
1da177e4 LT |
2643 | |
2644 | /* | |
2645 | * The recovery sequence below admits a very elaborated explanation: | |
2646 | * - it seems to work; | |
d03902b8 FR |
2647 | * - I did not see what else could be done; |
2648 | * - it makes iop3xx happy. | |
1da177e4 LT |
2649 | * |
2650 | * Feel free to adjust to your needs. | |
2651 | */ | |
a27993f3 | 2652 | if (pdev->broken_parity_status) |
d03902b8 FR |
2653 | pci_cmd &= ~PCI_COMMAND_PARITY; |
2654 | else | |
2655 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
2656 | ||
2657 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
2658 | |
2659 | pci_write_config_word(pdev, PCI_STATUS, | |
2660 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
2661 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
2662 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
2663 | ||
2664 | /* The infamous DAC f*ckup only happens at boot time */ | |
2665 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
b57b7e5a SH |
2666 | if (netif_msg_intr(tp)) |
2667 | printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); | |
1da177e4 LT |
2668 | tp->cp_cmd &= ~PCIDAC; |
2669 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2670 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
2671 | } |
2672 | ||
2673 | rtl8169_hw_reset(ioaddr); | |
d03902b8 FR |
2674 | |
2675 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
1da177e4 LT |
2676 | } |
2677 | ||
07d3f51f FR |
2678 | static void rtl8169_tx_interrupt(struct net_device *dev, |
2679 | struct rtl8169_private *tp, | |
2680 | void __iomem *ioaddr) | |
1da177e4 LT |
2681 | { |
2682 | unsigned int dirty_tx, tx_left; | |
2683 | ||
1da177e4 LT |
2684 | dirty_tx = tp->dirty_tx; |
2685 | smp_rmb(); | |
2686 | tx_left = tp->cur_tx - dirty_tx; | |
2687 | ||
2688 | while (tx_left > 0) { | |
2689 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
2690 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
2691 | u32 len = tx_skb->len; | |
2692 | u32 status; | |
2693 | ||
2694 | rmb(); | |
2695 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
2696 | if (status & DescOwn) | |
2697 | break; | |
2698 | ||
cebf8cc7 FR |
2699 | dev->stats.tx_bytes += len; |
2700 | dev->stats.tx_packets++; | |
1da177e4 LT |
2701 | |
2702 | rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); | |
2703 | ||
2704 | if (status & LastFrag) { | |
2705 | dev_kfree_skb_irq(tx_skb->skb); | |
2706 | tx_skb->skb = NULL; | |
2707 | } | |
2708 | dirty_tx++; | |
2709 | tx_left--; | |
2710 | } | |
2711 | ||
2712 | if (tp->dirty_tx != dirty_tx) { | |
2713 | tp->dirty_tx = dirty_tx; | |
2714 | smp_wmb(); | |
2715 | if (netif_queue_stopped(dev) && | |
2716 | (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { | |
2717 | netif_wake_queue(dev); | |
2718 | } | |
d78ae2dc FR |
2719 | /* |
2720 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
2721 | * too close. Let's kick an extra TxPoll request when a burst | |
2722 | * of start_xmit activity is detected (if it is not detected, | |
2723 | * it is slow enough). -- FR | |
2724 | */ | |
2725 | smp_rmb(); | |
2726 | if (tp->cur_tx != dirty_tx) | |
2727 | RTL_W8(TxPoll, NPQ); | |
1da177e4 LT |
2728 | } |
2729 | } | |
2730 | ||
126fa4b9 FR |
2731 | static inline int rtl8169_fragmented_frame(u32 status) |
2732 | { | |
2733 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
2734 | } | |
2735 | ||
1da177e4 LT |
2736 | static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
2737 | { | |
2738 | u32 opts1 = le32_to_cpu(desc->opts1); | |
2739 | u32 status = opts1 & RxProtoMask; | |
2740 | ||
2741 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
2742 | ((status == RxProtoUDP) && !(opts1 & UDPFail)) || | |
2743 | ((status == RxProtoIP) && !(opts1 & IPFail))) | |
2744 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2745 | else | |
2746 | skb->ip_summed = CHECKSUM_NONE; | |
2747 | } | |
2748 | ||
07d3f51f FR |
2749 | static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
2750 | struct rtl8169_private *tp, int pkt_size, | |
2751 | dma_addr_t addr) | |
1da177e4 | 2752 | { |
b449655f SH |
2753 | struct sk_buff *skb; |
2754 | bool done = false; | |
1da177e4 | 2755 | |
b449655f SH |
2756 | if (pkt_size >= rx_copybreak) |
2757 | goto out; | |
1da177e4 | 2758 | |
07d3f51f | 2759 | skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
b449655f SH |
2760 | if (!skb) |
2761 | goto out; | |
2762 | ||
07d3f51f FR |
2763 | pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
2764 | PCI_DMA_FROMDEVICE); | |
86402234 | 2765 | skb_reserve(skb, NET_IP_ALIGN); |
b449655f SH |
2766 | skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
2767 | *sk_buff = skb; | |
2768 | done = true; | |
2769 | out: | |
2770 | return done; | |
1da177e4 LT |
2771 | } |
2772 | ||
07d3f51f FR |
2773 | static int rtl8169_rx_interrupt(struct net_device *dev, |
2774 | struct rtl8169_private *tp, | |
bea3348e | 2775 | void __iomem *ioaddr, u32 budget) |
1da177e4 LT |
2776 | { |
2777 | unsigned int cur_rx, rx_left; | |
2778 | unsigned int delta, count; | |
2779 | ||
1da177e4 LT |
2780 | cur_rx = tp->cur_rx; |
2781 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
bea3348e | 2782 | rx_left = rtl8169_rx_quota(rx_left, budget); |
1da177e4 | 2783 | |
4dcb7d33 | 2784 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 2785 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 2786 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
2787 | u32 status; |
2788 | ||
2789 | rmb(); | |
126fa4b9 | 2790 | status = le32_to_cpu(desc->opts1); |
1da177e4 LT |
2791 | |
2792 | if (status & DescOwn) | |
2793 | break; | |
4dcb7d33 | 2794 | if (unlikely(status & RxRES)) { |
b57b7e5a SH |
2795 | if (netif_msg_rx_err(tp)) { |
2796 | printk(KERN_INFO | |
2797 | "%s: Rx ERROR. status = %08x\n", | |
2798 | dev->name, status); | |
2799 | } | |
cebf8cc7 | 2800 | dev->stats.rx_errors++; |
1da177e4 | 2801 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 2802 | dev->stats.rx_length_errors++; |
1da177e4 | 2803 | if (status & RxCRC) |
cebf8cc7 | 2804 | dev->stats.rx_crc_errors++; |
9dccf611 FR |
2805 | if (status & RxFOVF) { |
2806 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
cebf8cc7 | 2807 | dev->stats.rx_fifo_errors++; |
9dccf611 | 2808 | } |
126fa4b9 | 2809 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
1da177e4 | 2810 | } else { |
1da177e4 | 2811 | struct sk_buff *skb = tp->Rx_skbuff[entry]; |
b449655f | 2812 | dma_addr_t addr = le64_to_cpu(desc->addr); |
1da177e4 | 2813 | int pkt_size = (status & 0x00001FFF) - 4; |
b449655f | 2814 | struct pci_dev *pdev = tp->pci_dev; |
1da177e4 | 2815 | |
126fa4b9 FR |
2816 | /* |
2817 | * The driver does not support incoming fragmented | |
2818 | * frames. They are seen as a symptom of over-mtu | |
2819 | * sized frames. | |
2820 | */ | |
2821 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
2822 | dev->stats.rx_dropped++; |
2823 | dev->stats.rx_length_errors++; | |
126fa4b9 | 2824 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
4dcb7d33 | 2825 | continue; |
126fa4b9 FR |
2826 | } |
2827 | ||
1da177e4 | 2828 | rtl8169_rx_csum(skb, desc); |
bcf0bf90 | 2829 | |
07d3f51f | 2830 | if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { |
b449655f SH |
2831 | pci_dma_sync_single_for_device(pdev, addr, |
2832 | pkt_size, PCI_DMA_FROMDEVICE); | |
2833 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); | |
2834 | } else { | |
2835 | pci_unmap_single(pdev, addr, pkt_size, | |
2836 | PCI_DMA_FROMDEVICE); | |
1da177e4 LT |
2837 | tp->Rx_skbuff[entry] = NULL; |
2838 | } | |
2839 | ||
1da177e4 LT |
2840 | skb_put(skb, pkt_size); |
2841 | skb->protocol = eth_type_trans(skb, dev); | |
2842 | ||
2843 | if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) | |
2844 | rtl8169_rx_skb(skb); | |
2845 | ||
2846 | dev->last_rx = jiffies; | |
cebf8cc7 FR |
2847 | dev->stats.rx_bytes += pkt_size; |
2848 | dev->stats.rx_packets++; | |
1da177e4 | 2849 | } |
6dccd16b FR |
2850 | |
2851 | /* Work around for AMD plateform. */ | |
2852 | if ((desc->opts2 & 0xfffe000) && | |
2853 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { | |
2854 | desc->opts2 = 0; | |
2855 | cur_rx++; | |
2856 | } | |
1da177e4 LT |
2857 | } |
2858 | ||
2859 | count = cur_rx - tp->cur_rx; | |
2860 | tp->cur_rx = cur_rx; | |
2861 | ||
2862 | delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); | |
b57b7e5a | 2863 | if (!delta && count && netif_msg_intr(tp)) |
1da177e4 LT |
2864 | printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
2865 | tp->dirty_rx += delta; | |
2866 | ||
2867 | /* | |
2868 | * FIXME: until there is periodic timer to try and refill the ring, | |
2869 | * a temporary shortage may definitely kill the Rx process. | |
2870 | * - disable the asic to try and avoid an overflow and kick it again | |
2871 | * after refill ? | |
2872 | * - how do others driver handle this condition (Uh oh...). | |
2873 | */ | |
b57b7e5a | 2874 | if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
1da177e4 LT |
2875 | printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
2876 | ||
2877 | return count; | |
2878 | } | |
2879 | ||
07d3f51f | 2880 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 2881 | { |
07d3f51f | 2882 | struct net_device *dev = dev_instance; |
1da177e4 LT |
2883 | struct rtl8169_private *tp = netdev_priv(dev); |
2884 | int boguscnt = max_interrupt_work; | |
2885 | void __iomem *ioaddr = tp->mmio_addr; | |
2886 | int status; | |
2887 | int handled = 0; | |
2888 | ||
2889 | do { | |
2890 | status = RTL_R16(IntrStatus); | |
2891 | ||
2892 | /* hotplug/major error/no more work/shared irq */ | |
2893 | if ((status == 0xFFFF) || !status) | |
2894 | break; | |
2895 | ||
2896 | handled = 1; | |
2897 | ||
2898 | if (unlikely(!netif_running(dev))) { | |
2899 | rtl8169_asic_down(ioaddr); | |
2900 | goto out; | |
2901 | } | |
2902 | ||
2903 | status &= tp->intr_mask; | |
2904 | RTL_W16(IntrStatus, | |
2905 | (status & RxFIFOOver) ? (status | RxOverflow) : status); | |
2906 | ||
0e485150 FR |
2907 | if (!(status & tp->intr_event)) |
2908 | break; | |
2909 | ||
2910 | /* Work around for rx fifo overflow */ | |
2911 | if (unlikely(status & RxFIFOOver) && | |
2912 | (tp->mac_version == RTL_GIGA_MAC_VER_11)) { | |
2913 | netif_stop_queue(dev); | |
2914 | rtl8169_tx_timeout(dev); | |
1da177e4 | 2915 | break; |
0e485150 | 2916 | } |
1da177e4 LT |
2917 | |
2918 | if (unlikely(status & SYSErr)) { | |
2919 | rtl8169_pcierr_interrupt(dev); | |
2920 | break; | |
2921 | } | |
2922 | ||
2923 | if (status & LinkChg) | |
2924 | rtl8169_check_link_status(dev, tp, ioaddr); | |
2925 | ||
2926 | #ifdef CONFIG_R8169_NAPI | |
313b0305 FR |
2927 | if (status & tp->napi_event) { |
2928 | RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); | |
2929 | tp->intr_mask = ~tp->napi_event; | |
2930 | ||
bea3348e SH |
2931 | if (likely(netif_rx_schedule_prep(dev, &tp->napi))) |
2932 | __netif_rx_schedule(dev, &tp->napi); | |
313b0305 FR |
2933 | else if (netif_msg_intr(tp)) { |
2934 | printk(KERN_INFO "%s: interrupt %04x in poll\n", | |
2935 | dev->name, status); | |
2936 | } | |
1da177e4 LT |
2937 | } |
2938 | break; | |
2939 | #else | |
2940 | /* Rx interrupt */ | |
07d3f51f | 2941 | if (status & (RxOK | RxOverflow | RxFIFOOver)) |
bea3348e | 2942 | rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0); |
07d3f51f | 2943 | |
1da177e4 LT |
2944 | /* Tx interrupt */ |
2945 | if (status & (TxOK | TxErr)) | |
2946 | rtl8169_tx_interrupt(dev, tp, ioaddr); | |
2947 | #endif | |
2948 | ||
2949 | boguscnt--; | |
2950 | } while (boguscnt > 0); | |
2951 | ||
2952 | if (boguscnt <= 0) { | |
7c8b2eb4 | 2953 | if (netif_msg_intr(tp) && net_ratelimit() ) { |
b57b7e5a SH |
2954 | printk(KERN_WARNING |
2955 | "%s: Too much work at interrupt!\n", dev->name); | |
2956 | } | |
1da177e4 LT |
2957 | /* Clear all interrupt sources. */ |
2958 | RTL_W16(IntrStatus, 0xffff); | |
2959 | } | |
2960 | out: | |
2961 | return IRQ_RETVAL(handled); | |
2962 | } | |
2963 | ||
2964 | #ifdef CONFIG_R8169_NAPI | |
bea3348e | 2965 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2966 | { |
bea3348e SH |
2967 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
2968 | struct net_device *dev = tp->dev; | |
1da177e4 | 2969 | void __iomem *ioaddr = tp->mmio_addr; |
bea3348e | 2970 | int work_done; |
1da177e4 | 2971 | |
bea3348e | 2972 | work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
1da177e4 LT |
2973 | rtl8169_tx_interrupt(dev, tp, ioaddr); |
2974 | ||
bea3348e SH |
2975 | if (work_done < budget) { |
2976 | netif_rx_complete(dev, napi); | |
1da177e4 LT |
2977 | tp->intr_mask = 0xffff; |
2978 | /* | |
2979 | * 20040426: the barrier is not strictly required but the | |
2980 | * behavior of the irq handler could be less predictable | |
2981 | * without it. Btw, the lack of flush for the posted pci | |
2982 | * write is safe - FR | |
2983 | */ | |
2984 | smp_wmb(); | |
0e485150 | 2985 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
2986 | } |
2987 | ||
bea3348e | 2988 | return work_done; |
1da177e4 LT |
2989 | } |
2990 | #endif | |
2991 | ||
2992 | static void rtl8169_down(struct net_device *dev) | |
2993 | { | |
2994 | struct rtl8169_private *tp = netdev_priv(dev); | |
2995 | void __iomem *ioaddr = tp->mmio_addr; | |
733b736c | 2996 | unsigned int intrmask; |
1da177e4 LT |
2997 | |
2998 | rtl8169_delete_timer(dev); | |
2999 | ||
3000 | netif_stop_queue(dev); | |
3001 | ||
93dd79e8 SH |
3002 | #ifdef CONFIG_R8169_NAPI |
3003 | napi_disable(&tp->napi); | |
3004 | #endif | |
3005 | ||
1da177e4 LT |
3006 | core_down: |
3007 | spin_lock_irq(&tp->lock); | |
3008 | ||
3009 | rtl8169_asic_down(ioaddr); | |
3010 | ||
3011 | /* Update the error counts. */ | |
cebf8cc7 | 3012 | dev->stats.rx_missed_errors += RTL_R32(RxMissed); |
1da177e4 LT |
3013 | RTL_W32(RxMissed, 0); |
3014 | ||
3015 | spin_unlock_irq(&tp->lock); | |
3016 | ||
3017 | synchronize_irq(dev->irq); | |
3018 | ||
1da177e4 | 3019 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
fbd568a3 | 3020 | synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
1da177e4 LT |
3021 | |
3022 | /* | |
3023 | * And now for the 50k$ question: are IRQ disabled or not ? | |
3024 | * | |
3025 | * Two paths lead here: | |
3026 | * 1) dev->close | |
3027 | * -> netif_running() is available to sync the current code and the | |
3028 | * IRQ handler. See rtl8169_interrupt for details. | |
3029 | * 2) dev->change_mtu | |
3030 | * -> rtl8169_poll can not be issued again and re-enable the | |
3031 | * interruptions. Let's simply issue the IRQ down sequence again. | |
733b736c AP |
3032 | * |
3033 | * No loop if hotpluged or major error (0xffff). | |
1da177e4 | 3034 | */ |
733b736c AP |
3035 | intrmask = RTL_R16(IntrMask); |
3036 | if (intrmask && (intrmask != 0xffff)) | |
1da177e4 LT |
3037 | goto core_down; |
3038 | ||
3039 | rtl8169_tx_clear(tp); | |
3040 | ||
3041 | rtl8169_rx_clear(tp); | |
3042 | } | |
3043 | ||
3044 | static int rtl8169_close(struct net_device *dev) | |
3045 | { | |
3046 | struct rtl8169_private *tp = netdev_priv(dev); | |
3047 | struct pci_dev *pdev = tp->pci_dev; | |
3048 | ||
3049 | rtl8169_down(dev); | |
3050 | ||
3051 | free_irq(dev->irq, dev); | |
3052 | ||
1da177e4 LT |
3053 | pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
3054 | tp->RxPhyAddr); | |
3055 | pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
3056 | tp->TxPhyAddr); | |
3057 | tp->TxDescArray = NULL; | |
3058 | tp->RxDescArray = NULL; | |
3059 | ||
3060 | return 0; | |
3061 | } | |
3062 | ||
07ce4064 | 3063 | static void rtl_set_rx_mode(struct net_device *dev) |
1da177e4 LT |
3064 | { |
3065 | struct rtl8169_private *tp = netdev_priv(dev); | |
3066 | void __iomem *ioaddr = tp->mmio_addr; | |
3067 | unsigned long flags; | |
3068 | u32 mc_filter[2]; /* Multicast hash filter */ | |
07d3f51f | 3069 | int rx_mode; |
1da177e4 LT |
3070 | u32 tmp = 0; |
3071 | ||
3072 | if (dev->flags & IFF_PROMISC) { | |
3073 | /* Unconditionally log net taps. */ | |
b57b7e5a SH |
3074 | if (netif_msg_link(tp)) { |
3075 | printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", | |
3076 | dev->name); | |
3077 | } | |
1da177e4 LT |
3078 | rx_mode = |
3079 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
3080 | AcceptAllPhys; | |
3081 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
3082 | } else if ((dev->mc_count > multicast_filter_limit) | |
3083 | || (dev->flags & IFF_ALLMULTI)) { | |
3084 | /* Too many to filter perfectly -- accept all multicasts. */ | |
3085 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
3086 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
3087 | } else { | |
3088 | struct dev_mc_list *mclist; | |
07d3f51f FR |
3089 | unsigned int i; |
3090 | ||
1da177e4 LT |
3091 | rx_mode = AcceptBroadcast | AcceptMyPhys; |
3092 | mc_filter[1] = mc_filter[0] = 0; | |
3093 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
3094 | i++, mclist = mclist->next) { | |
3095 | int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; | |
3096 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
3097 | rx_mode |= AcceptMulticast; | |
3098 | } | |
3099 | } | |
3100 | ||
3101 | spin_lock_irqsave(&tp->lock, flags); | |
3102 | ||
3103 | tmp = rtl8169_rx_config | rx_mode | | |
3104 | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
3105 | ||
bcf0bf90 FR |
3106 | if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
3107 | (tp->mac_version == RTL_GIGA_MAC_VER_12) || | |
3108 | (tp->mac_version == RTL_GIGA_MAC_VER_13) || | |
3109 | (tp->mac_version == RTL_GIGA_MAC_VER_14) || | |
e3cf0cc0 FR |
3110 | (tp->mac_version == RTL_GIGA_MAC_VER_15) || |
3111 | (tp->mac_version == RTL_GIGA_MAC_VER_16) || | |
3112 | (tp->mac_version == RTL_GIGA_MAC_VER_17)) { | |
bcf0bf90 FR |
3113 | mc_filter[0] = 0xffffffff; |
3114 | mc_filter[1] = 0xffffffff; | |
3115 | } | |
3116 | ||
1da177e4 LT |
3117 | RTL_W32(MAR0 + 0, mc_filter[0]); |
3118 | RTL_W32(MAR0 + 4, mc_filter[1]); | |
3119 | ||
57a9f236 FR |
3120 | RTL_W32(RxConfig, tmp); |
3121 | ||
1da177e4 LT |
3122 | spin_unlock_irqrestore(&tp->lock, flags); |
3123 | } | |
3124 | ||
3125 | /** | |
3126 | * rtl8169_get_stats - Get rtl8169 read/write statistics | |
3127 | * @dev: The Ethernet Device to get statistics for | |
3128 | * | |
3129 | * Get TX/RX statistics for rtl8169 | |
3130 | */ | |
3131 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) | |
3132 | { | |
3133 | struct rtl8169_private *tp = netdev_priv(dev); | |
3134 | void __iomem *ioaddr = tp->mmio_addr; | |
3135 | unsigned long flags; | |
3136 | ||
3137 | if (netif_running(dev)) { | |
3138 | spin_lock_irqsave(&tp->lock, flags); | |
cebf8cc7 | 3139 | dev->stats.rx_missed_errors += RTL_R32(RxMissed); |
1da177e4 LT |
3140 | RTL_W32(RxMissed, 0); |
3141 | spin_unlock_irqrestore(&tp->lock, flags); | |
3142 | } | |
5b0384f4 | 3143 | |
cebf8cc7 | 3144 | return &dev->stats; |
1da177e4 LT |
3145 | } |
3146 | ||
5d06a99f FR |
3147 | #ifdef CONFIG_PM |
3148 | ||
3149 | static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state) | |
3150 | { | |
3151 | struct net_device *dev = pci_get_drvdata(pdev); | |
3152 | struct rtl8169_private *tp = netdev_priv(dev); | |
3153 | void __iomem *ioaddr = tp->mmio_addr; | |
3154 | ||
3155 | if (!netif_running(dev)) | |
1371fa6d | 3156 | goto out_pci_suspend; |
5d06a99f FR |
3157 | |
3158 | netif_device_detach(dev); | |
3159 | netif_stop_queue(dev); | |
3160 | ||
3161 | spin_lock_irq(&tp->lock); | |
3162 | ||
3163 | rtl8169_asic_down(ioaddr); | |
3164 | ||
cebf8cc7 | 3165 | dev->stats.rx_missed_errors += RTL_R32(RxMissed); |
5d06a99f FR |
3166 | RTL_W32(RxMissed, 0); |
3167 | ||
3168 | spin_unlock_irq(&tp->lock); | |
3169 | ||
1371fa6d | 3170 | out_pci_suspend: |
5d06a99f | 3171 | pci_save_state(pdev); |
f23e7fda FR |
3172 | pci_enable_wake(pdev, pci_choose_state(pdev, state), |
3173 | (tp->features & RTL_FEATURE_WOL) ? 1 : 0); | |
5d06a99f | 3174 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
1371fa6d | 3175 | |
5d06a99f FR |
3176 | return 0; |
3177 | } | |
3178 | ||
3179 | static int rtl8169_resume(struct pci_dev *pdev) | |
3180 | { | |
3181 | struct net_device *dev = pci_get_drvdata(pdev); | |
3182 | ||
1371fa6d FR |
3183 | pci_set_power_state(pdev, PCI_D0); |
3184 | pci_restore_state(pdev); | |
3185 | pci_enable_wake(pdev, PCI_D0, 0); | |
3186 | ||
5d06a99f FR |
3187 | if (!netif_running(dev)) |
3188 | goto out; | |
3189 | ||
3190 | netif_device_attach(dev); | |
3191 | ||
5d06a99f FR |
3192 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
3193 | out: | |
3194 | return 0; | |
3195 | } | |
3196 | ||
3197 | #endif /* CONFIG_PM */ | |
3198 | ||
1da177e4 LT |
3199 | static struct pci_driver rtl8169_pci_driver = { |
3200 | .name = MODULENAME, | |
3201 | .id_table = rtl8169_pci_tbl, | |
3202 | .probe = rtl8169_init_one, | |
3203 | .remove = __devexit_p(rtl8169_remove_one), | |
3204 | #ifdef CONFIG_PM | |
3205 | .suspend = rtl8169_suspend, | |
3206 | .resume = rtl8169_resume, | |
3207 | #endif | |
3208 | }; | |
3209 | ||
07d3f51f | 3210 | static int __init rtl8169_init_module(void) |
1da177e4 | 3211 | { |
29917620 | 3212 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
3213 | } |
3214 | ||
07d3f51f | 3215 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
3216 | { |
3217 | pci_unregister_driver(&rtl8169_pci_driver); | |
3218 | } | |
3219 | ||
3220 | module_init(rtl8169_init_module); | |
3221 | module_exit(rtl8169_cleanup_module); |