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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
8ceee660 | 24 | #include "net_driver.h" |
8ceee660 BH |
25 | #include "efx.h" |
26 | #include "mdio_10g.h" | |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
41 | const char *efx_loopback_mode_names[] = { | |
42 | [LOOPBACK_NONE] = "NONE", | |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
47 | [LOOPBACK_XAUI] = "XAUI", | |
e58f69f4 BH |
48 | [LOOPBACK_GMII] = "GMII", |
49 | [LOOPBACK_SGMII] = "SGMII", | |
50 | [LOOPBACK_XGBR] = "XGBR", | |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
58 | [LOOPBACK_PCS] = "PCS", | |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", | |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", | |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
65 | [LOOPBACK_GMII_WS] = "GMII_WS", | |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", | |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", | |
c459302d BH |
69 | }; |
70 | ||
71 | /* Interrupt mode names (see INT_MODE())) */ | |
72 | const unsigned int efx_interrupt_mode_max = EFX_INT_MODE_MAX; | |
73 | const char *efx_interrupt_mode_names[] = { | |
74 | [EFX_INT_MODE_MSIX] = "MSI-X", | |
75 | [EFX_INT_MODE_MSI] = "MSI", | |
76 | [EFX_INT_MODE_LEGACY] = "legacy", | |
77 | }; | |
78 | ||
79 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; | |
80 | const char *efx_reset_type_names[] = { | |
81 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
82 | [RESET_TYPE_ALL] = "ALL", | |
83 | [RESET_TYPE_WORLD] = "WORLD", | |
84 | [RESET_TYPE_DISABLE] = "DISABLE", | |
85 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
86 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
87 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
88 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
89 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
90 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 91 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
92 | }; |
93 | ||
8ceee660 BH |
94 | #define EFX_MAX_MTU (9 * 1024) |
95 | ||
1ab00629 SH |
96 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
97 | * queued onto this work queue. This is not a per-nic work queue, because | |
98 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
99 | */ | |
100 | static struct workqueue_struct *reset_workqueue; | |
101 | ||
8ceee660 BH |
102 | /************************************************************************** |
103 | * | |
104 | * Configurable values | |
105 | * | |
106 | *************************************************************************/ | |
107 | ||
8ceee660 BH |
108 | /* |
109 | * Use separate channels for TX and RX events | |
110 | * | |
28b581ab NT |
111 | * Set this to 1 to use separate channels for TX and RX. It allows us |
112 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 113 | * |
28b581ab | 114 | * This is only used in MSI-X interrupt mode |
8ceee660 | 115 | */ |
28b581ab NT |
116 | static unsigned int separate_tx_channels; |
117 | module_param(separate_tx_channels, uint, 0644); | |
118 | MODULE_PARM_DESC(separate_tx_channels, | |
119 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
120 | |
121 | /* This is the weight assigned to each of the (per-channel) virtual | |
122 | * NAPI devices. | |
123 | */ | |
124 | static int napi_weight = 64; | |
125 | ||
126 | /* This is the time (in jiffies) between invocations of the hardware | |
127 | * monitor, which checks for known hardware bugs and resets the | |
128 | * hardware and driver as necessary. | |
129 | */ | |
130 | unsigned int efx_monitor_interval = 1 * HZ; | |
131 | ||
8ceee660 BH |
132 | /* This controls whether or not the driver will initialise devices |
133 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
134 | * such devices will be initialised with a random locally-generated | |
135 | * MAC address. This allows for loading the sfc_mtd driver to | |
136 | * reprogram the flash, even if the flash contents (including the MAC | |
137 | * address) have previously been erased. | |
138 | */ | |
139 | static unsigned int allow_bad_hwaddr; | |
140 | ||
141 | /* Initial interrupt moderation settings. They can be modified after | |
142 | * module load with ethtool. | |
143 | * | |
144 | * The default for RX should strike a balance between increasing the | |
145 | * round-trip latency and reducing overhead. | |
146 | */ | |
147 | static unsigned int rx_irq_mod_usec = 60; | |
148 | ||
149 | /* Initial interrupt moderation settings. They can be modified after | |
150 | * module load with ethtool. | |
151 | * | |
152 | * This default is chosen to ensure that a 10G link does not go idle | |
153 | * while a TX queue is stopped after it has become full. A queue is | |
154 | * restarted when it drops below half full. The time this takes (assuming | |
155 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
156 | * 512 / 3 * 1.2 = 205 usec. | |
157 | */ | |
158 | static unsigned int tx_irq_mod_usec = 150; | |
159 | ||
160 | /* This is the first interrupt mode to try out of: | |
161 | * 0 => MSI-X | |
162 | * 1 => MSI | |
163 | * 2 => legacy | |
164 | */ | |
165 | static unsigned int interrupt_mode; | |
166 | ||
167 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
168 | * i.e. the number of CPUs among which we may distribute simultaneous | |
169 | * interrupt handling. | |
170 | * | |
171 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
172 | * The default (0) means to assign an interrupt to each package (level II cache) | |
173 | */ | |
174 | static unsigned int rss_cpus; | |
175 | module_param(rss_cpus, uint, 0444); | |
176 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
177 | ||
84ae48fe BH |
178 | static int phy_flash_cfg; |
179 | module_param(phy_flash_cfg, int, 0644); | |
180 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
181 | ||
6fb70fd1 BH |
182 | static unsigned irq_adapt_low_thresh = 10000; |
183 | module_param(irq_adapt_low_thresh, uint, 0644); | |
184 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
185 | "Threshold score for reducing IRQ moderation"); | |
186 | ||
187 | static unsigned irq_adapt_high_thresh = 20000; | |
188 | module_param(irq_adapt_high_thresh, uint, 0644); | |
189 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
190 | "Threshold score for increasing IRQ moderation"); | |
191 | ||
8ceee660 BH |
192 | /************************************************************************** |
193 | * | |
194 | * Utility functions and prototypes | |
195 | * | |
196 | *************************************************************************/ | |
197 | static void efx_remove_channel(struct efx_channel *channel); | |
198 | static void efx_remove_port(struct efx_nic *efx); | |
199 | static void efx_fini_napi(struct efx_nic *efx); | |
200 | static void efx_fini_channels(struct efx_nic *efx); | |
201 | ||
202 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
203 | do { \ | |
332c1ce9 BH |
204 | if ((efx->state == STATE_RUNNING) || \ |
205 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
206 | ASSERT_RTNL(); \ |
207 | } while (0) | |
208 | ||
209 | /************************************************************************** | |
210 | * | |
211 | * Event queue processing | |
212 | * | |
213 | *************************************************************************/ | |
214 | ||
215 | /* Process channel's event queue | |
216 | * | |
217 | * This function is responsible for processing the event queue of a | |
218 | * single channel. The caller must guarantee that this function will | |
219 | * never be concurrently called more than once on the same channel, | |
220 | * though different channels may be being processed concurrently. | |
221 | */ | |
fa236e18 | 222 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 223 | { |
42cbe2d7 | 224 | struct efx_nic *efx = channel->efx; |
fa236e18 | 225 | int spent; |
8ceee660 | 226 | |
42cbe2d7 | 227 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 228 | !channel->enabled)) |
42cbe2d7 | 229 | return 0; |
8ceee660 | 230 | |
fa236e18 BH |
231 | spent = efx_nic_process_eventq(channel, budget); |
232 | if (spent == 0) | |
42cbe2d7 | 233 | return 0; |
8ceee660 BH |
234 | |
235 | /* Deliver last RX packet. */ | |
236 | if (channel->rx_pkt) { | |
237 | __efx_rx_packet(channel, channel->rx_pkt, | |
238 | channel->rx_pkt_csummed); | |
239 | channel->rx_pkt = NULL; | |
240 | } | |
241 | ||
8ceee660 BH |
242 | efx_rx_strategy(channel); |
243 | ||
42cbe2d7 | 244 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 245 | |
fa236e18 | 246 | return spent; |
8ceee660 BH |
247 | } |
248 | ||
249 | /* Mark channel as finished processing | |
250 | * | |
251 | * Note that since we will not receive further interrupts for this | |
252 | * channel before we finish processing and call the eventq_read_ack() | |
253 | * method, there is no need to use the interrupt hold-off timers. | |
254 | */ | |
255 | static inline void efx_channel_processed(struct efx_channel *channel) | |
256 | { | |
5b9e207c BH |
257 | /* The interrupt handler for this channel may set work_pending |
258 | * as soon as we acknowledge the events we've seen. Make sure | |
259 | * it's cleared before then. */ | |
dc8cfa55 | 260 | channel->work_pending = false; |
5b9e207c BH |
261 | smp_wmb(); |
262 | ||
152b6a62 | 263 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
264 | } |
265 | ||
266 | /* NAPI poll handler | |
267 | * | |
268 | * NAPI guarantees serialisation of polls of the same device, which | |
269 | * provides the guarantee required by efx_process_channel(). | |
270 | */ | |
271 | static int efx_poll(struct napi_struct *napi, int budget) | |
272 | { | |
273 | struct efx_channel *channel = | |
274 | container_of(napi, struct efx_channel, napi_str); | |
fa236e18 | 275 | int spent; |
8ceee660 BH |
276 | |
277 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
278 | channel->channel, raw_smp_processor_id()); | |
279 | ||
fa236e18 | 280 | spent = efx_process_channel(channel, budget); |
8ceee660 | 281 | |
fa236e18 | 282 | if (spent < budget) { |
6fb70fd1 BH |
283 | struct efx_nic *efx = channel->efx; |
284 | ||
a4900ac9 | 285 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
286 | efx->irq_rx_adaptive && |
287 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
288 | if (unlikely(channel->irq_mod_score < |
289 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
290 | if (channel->irq_moderation > 1) { |
291 | channel->irq_moderation -= 1; | |
ef2b90ee | 292 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 293 | } |
6fb70fd1 BH |
294 | } else if (unlikely(channel->irq_mod_score > |
295 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
296 | if (channel->irq_moderation < |
297 | efx->irq_rx_moderation) { | |
298 | channel->irq_moderation += 1; | |
ef2b90ee | 299 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 300 | } |
6fb70fd1 | 301 | } |
6fb70fd1 BH |
302 | channel->irq_count = 0; |
303 | channel->irq_mod_score = 0; | |
304 | } | |
305 | ||
8ceee660 | 306 | /* There is no race here; although napi_disable() will |
288379f0 | 307 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
308 | * since efx_channel_processed() will have no effect if |
309 | * interrupts have already been disabled. | |
310 | */ | |
288379f0 | 311 | napi_complete(napi); |
8ceee660 BH |
312 | efx_channel_processed(channel); |
313 | } | |
314 | ||
fa236e18 | 315 | return spent; |
8ceee660 BH |
316 | } |
317 | ||
318 | /* Process the eventq of the specified channel immediately on this CPU | |
319 | * | |
320 | * Disable hardware generated interrupts, wait for any existing | |
321 | * processing to finish, then directly poll (and ack ) the eventq. | |
322 | * Finally reenable NAPI and interrupts. | |
323 | * | |
324 | * Since we are touching interrupts the caller should hold the suspend lock | |
325 | */ | |
326 | void efx_process_channel_now(struct efx_channel *channel) | |
327 | { | |
328 | struct efx_nic *efx = channel->efx; | |
329 | ||
8ceee660 BH |
330 | BUG_ON(!channel->enabled); |
331 | ||
332 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 333 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
334 | if (efx->legacy_irq) |
335 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 336 | if (channel->irq) |
8ceee660 BH |
337 | synchronize_irq(channel->irq); |
338 | ||
339 | /* Wait for any NAPI processing to complete */ | |
340 | napi_disable(&channel->napi_str); | |
341 | ||
342 | /* Poll the channel */ | |
3ffeabdd | 343 | efx_process_channel(channel, EFX_EVQ_SIZE); |
8ceee660 BH |
344 | |
345 | /* Ack the eventq. This may cause an interrupt to be generated | |
346 | * when they are reenabled */ | |
347 | efx_channel_processed(channel); | |
348 | ||
349 | napi_enable(&channel->napi_str); | |
152b6a62 | 350 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
351 | } |
352 | ||
353 | /* Create event queue | |
354 | * Event queue memory allocations are done only once. If the channel | |
355 | * is reset, the memory buffer will be reused; this guards against | |
356 | * errors during channel reset and also simplifies interrupt handling. | |
357 | */ | |
358 | static int efx_probe_eventq(struct efx_channel *channel) | |
359 | { | |
360 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
361 | ||
152b6a62 | 362 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
363 | } |
364 | ||
365 | /* Prepare channel's event queue */ | |
bc3c90a2 | 366 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
367 | { |
368 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
369 | ||
370 | channel->eventq_read_ptr = 0; | |
371 | ||
152b6a62 | 372 | efx_nic_init_eventq(channel); |
8ceee660 BH |
373 | } |
374 | ||
375 | static void efx_fini_eventq(struct efx_channel *channel) | |
376 | { | |
377 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
378 | ||
152b6a62 | 379 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
380 | } |
381 | ||
382 | static void efx_remove_eventq(struct efx_channel *channel) | |
383 | { | |
384 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
385 | ||
152b6a62 | 386 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
387 | } |
388 | ||
389 | /************************************************************************** | |
390 | * | |
391 | * Channel handling | |
392 | * | |
393 | *************************************************************************/ | |
394 | ||
8ceee660 BH |
395 | static int efx_probe_channel(struct efx_channel *channel) |
396 | { | |
397 | struct efx_tx_queue *tx_queue; | |
398 | struct efx_rx_queue *rx_queue; | |
399 | int rc; | |
400 | ||
401 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
402 | ||
403 | rc = efx_probe_eventq(channel); | |
404 | if (rc) | |
405 | goto fail1; | |
406 | ||
407 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
408 | rc = efx_probe_tx_queue(tx_queue); | |
409 | if (rc) | |
410 | goto fail2; | |
411 | } | |
412 | ||
413 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
414 | rc = efx_probe_rx_queue(rx_queue); | |
415 | if (rc) | |
416 | goto fail3; | |
417 | } | |
418 | ||
419 | channel->n_rx_frm_trunc = 0; | |
420 | ||
421 | return 0; | |
422 | ||
423 | fail3: | |
424 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
425 | efx_remove_rx_queue(rx_queue); | |
426 | fail2: | |
427 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
428 | efx_remove_tx_queue(tx_queue); | |
429 | fail1: | |
430 | return rc; | |
431 | } | |
432 | ||
433 | ||
56536e9c BH |
434 | static void efx_set_channel_names(struct efx_nic *efx) |
435 | { | |
436 | struct efx_channel *channel; | |
437 | const char *type = ""; | |
438 | int number; | |
439 | ||
440 | efx_for_each_channel(channel, efx) { | |
441 | number = channel->channel; | |
a4900ac9 BH |
442 | if (efx->n_channels > efx->n_rx_channels) { |
443 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
444 | type = "-rx"; |
445 | } else { | |
446 | type = "-tx"; | |
a4900ac9 | 447 | number -= efx->n_rx_channels; |
56536e9c BH |
448 | } |
449 | } | |
450 | snprintf(channel->name, sizeof(channel->name), | |
451 | "%s%s-%d", efx->name, type, number); | |
452 | } | |
453 | } | |
454 | ||
8ceee660 BH |
455 | /* Channels are shutdown and reinitialised whilst the NIC is running |
456 | * to propagate configuration changes (mtu, checksum offload), or | |
457 | * to clear hardware error conditions | |
458 | */ | |
bc3c90a2 | 459 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
460 | { |
461 | struct efx_tx_queue *tx_queue; | |
462 | struct efx_rx_queue *rx_queue; | |
463 | struct efx_channel *channel; | |
8ceee660 | 464 | |
f7f13b0b BH |
465 | /* Calculate the rx buffer allocation parameters required to |
466 | * support the current MTU, including padding for header | |
467 | * alignment and overruns. | |
468 | */ | |
469 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
470 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
471 | efx->type->rx_buffer_padding); | |
472 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
473 | |
474 | /* Initialise the channels */ | |
475 | efx_for_each_channel(channel, efx) { | |
476 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
477 | ||
bc3c90a2 | 478 | efx_init_eventq(channel); |
8ceee660 | 479 | |
bc3c90a2 BH |
480 | efx_for_each_channel_tx_queue(tx_queue, channel) |
481 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
482 | |
483 | /* The rx buffer allocation strategy is MTU dependent */ | |
484 | efx_rx_strategy(channel); | |
485 | ||
bc3c90a2 BH |
486 | efx_for_each_channel_rx_queue(rx_queue, channel) |
487 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
488 | |
489 | WARN_ON(channel->rx_pkt != NULL); | |
490 | efx_rx_strategy(channel); | |
491 | } | |
8ceee660 BH |
492 | } |
493 | ||
494 | /* This enables event queue processing and packet transmission. | |
495 | * | |
496 | * Note that this function is not allowed to fail, since that would | |
497 | * introduce too much complexity into the suspend/resume path. | |
498 | */ | |
499 | static void efx_start_channel(struct efx_channel *channel) | |
500 | { | |
501 | struct efx_rx_queue *rx_queue; | |
502 | ||
503 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
504 | ||
5b9e207c BH |
505 | /* The interrupt handler for this channel may set work_pending |
506 | * as soon as we enable it. Make sure it's cleared before | |
507 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
508 | channel->work_pending = false; |
509 | channel->enabled = true; | |
5b9e207c | 510 | smp_wmb(); |
8ceee660 | 511 | |
90d683af | 512 | /* Fill the queues before enabling NAPI */ |
8ceee660 BH |
513 | efx_for_each_channel_rx_queue(rx_queue, channel) |
514 | efx_fast_push_rx_descriptors(rx_queue); | |
90d683af SH |
515 | |
516 | napi_enable(&channel->napi_str); | |
8ceee660 BH |
517 | } |
518 | ||
519 | /* This disables event queue processing and packet transmission. | |
520 | * This function does not guarantee that all queue processing | |
521 | * (e.g. RX refill) is complete. | |
522 | */ | |
523 | static void efx_stop_channel(struct efx_channel *channel) | |
524 | { | |
8ceee660 BH |
525 | if (!channel->enabled) |
526 | return; | |
527 | ||
528 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
529 | ||
dc8cfa55 | 530 | channel->enabled = false; |
8ceee660 | 531 | napi_disable(&channel->napi_str); |
8ceee660 BH |
532 | } |
533 | ||
534 | static void efx_fini_channels(struct efx_nic *efx) | |
535 | { | |
536 | struct efx_channel *channel; | |
537 | struct efx_tx_queue *tx_queue; | |
538 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 539 | int rc; |
8ceee660 BH |
540 | |
541 | EFX_ASSERT_RESET_SERIALISED(efx); | |
542 | BUG_ON(efx->port_enabled); | |
543 | ||
152b6a62 | 544 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
545 | if (rc && EFX_WORKAROUND_7803(efx)) { |
546 | /* Schedule a reset to recover from the flush failure. The | |
547 | * descriptor caches reference memory we're about to free, | |
548 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
549 | * the MACs because of the pending reset. */ | |
550 | EFX_ERR(efx, "Resetting to recover from flush failure\n"); | |
551 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
552 | } else if (rc) { | |
6bc5d3a9 | 553 | EFX_ERR(efx, "failed to flush queues\n"); |
fd371e32 | 554 | } else { |
6bc5d3a9 | 555 | EFX_LOG(efx, "successfully flushed all queues\n"); |
fd371e32 | 556 | } |
6bc5d3a9 | 557 | |
8ceee660 BH |
558 | efx_for_each_channel(channel, efx) { |
559 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
560 | ||
561 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
562 | efx_fini_rx_queue(rx_queue); | |
563 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
564 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
565 | efx_fini_eventq(channel); |
566 | } | |
567 | } | |
568 | ||
569 | static void efx_remove_channel(struct efx_channel *channel) | |
570 | { | |
571 | struct efx_tx_queue *tx_queue; | |
572 | struct efx_rx_queue *rx_queue; | |
573 | ||
574 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
575 | ||
576 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
577 | efx_remove_rx_queue(rx_queue); | |
578 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
579 | efx_remove_tx_queue(tx_queue); | |
580 | efx_remove_eventq(channel); | |
8ceee660 BH |
581 | } |
582 | ||
90d683af | 583 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 584 | { |
90d683af | 585 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
586 | } |
587 | ||
588 | /************************************************************************** | |
589 | * | |
590 | * Port handling | |
591 | * | |
592 | **************************************************************************/ | |
593 | ||
594 | /* This ensures that the kernel is kept informed (via | |
595 | * netif_carrier_on/off) of the link status, and also maintains the | |
596 | * link status's stop on the port's TX queue. | |
597 | */ | |
fdaa9aed | 598 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 599 | { |
eb50c0d6 BH |
600 | struct efx_link_state *link_state = &efx->link_state; |
601 | ||
8ceee660 BH |
602 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
603 | * that no events are triggered between unregister_netdev() and the | |
604 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
605 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
606 | if (!netif_running(efx->net_dev)) | |
607 | return; | |
608 | ||
8c8661e4 BH |
609 | if (efx->port_inhibited) { |
610 | netif_carrier_off(efx->net_dev); | |
611 | return; | |
612 | } | |
613 | ||
eb50c0d6 | 614 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
615 | efx->n_link_state_changes++; |
616 | ||
eb50c0d6 | 617 | if (link_state->up) |
8ceee660 BH |
618 | netif_carrier_on(efx->net_dev); |
619 | else | |
620 | netif_carrier_off(efx->net_dev); | |
621 | } | |
622 | ||
623 | /* Status message for kernel log */ | |
eb50c0d6 | 624 | if (link_state->up) { |
f31a45d2 | 625 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
eb50c0d6 | 626 | link_state->speed, link_state->fd ? "full" : "half", |
8ceee660 BH |
627 | efx->net_dev->mtu, |
628 | (efx->promiscuous ? " [PROMISC]" : "")); | |
629 | } else { | |
630 | EFX_INFO(efx, "link down\n"); | |
631 | } | |
632 | ||
633 | } | |
634 | ||
d3245b28 BH |
635 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
636 | { | |
637 | efx->link_advertising = advertising; | |
638 | if (advertising) { | |
639 | if (advertising & ADVERTISED_Pause) | |
640 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
641 | else | |
642 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
643 | if (advertising & ADVERTISED_Asym_Pause) | |
644 | efx->wanted_fc ^= EFX_FC_TX; | |
645 | } | |
646 | } | |
647 | ||
648 | void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc) | |
649 | { | |
650 | efx->wanted_fc = wanted_fc; | |
651 | if (efx->link_advertising) { | |
652 | if (wanted_fc & EFX_FC_RX) | |
653 | efx->link_advertising |= (ADVERTISED_Pause | | |
654 | ADVERTISED_Asym_Pause); | |
655 | else | |
656 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
657 | ADVERTISED_Asym_Pause); | |
658 | if (wanted_fc & EFX_FC_TX) | |
659 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
660 | } | |
661 | } | |
662 | ||
115122af BH |
663 | static void efx_fini_port(struct efx_nic *efx); |
664 | ||
d3245b28 BH |
665 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
666 | * the MAC appropriately. All other PHY configuration changes are pushed | |
667 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
668 | * through efx_monitor(). | |
669 | * | |
670 | * Callers must hold the mac_lock | |
671 | */ | |
672 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 673 | { |
d3245b28 BH |
674 | enum efx_phy_mode phy_mode; |
675 | int rc; | |
8ceee660 | 676 | |
d3245b28 | 677 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 678 | |
a816f75a BH |
679 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
680 | if (efx_dev_registered(efx)) { | |
681 | netif_addr_lock_bh(efx->net_dev); | |
682 | netif_addr_unlock_bh(efx->net_dev); | |
683 | } | |
684 | ||
d3245b28 BH |
685 | /* Disable PHY transmit in mac level loopbacks */ |
686 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
687 | if (LOOPBACK_INTERNAL(efx)) |
688 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
689 | else | |
690 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 691 | |
d3245b28 | 692 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 693 | |
d3245b28 BH |
694 | if (rc) |
695 | efx->phy_mode = phy_mode; | |
177dfcd8 | 696 | |
d3245b28 | 697 | return rc; |
8ceee660 BH |
698 | } |
699 | ||
700 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
701 | * disabled. */ | |
d3245b28 | 702 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 703 | { |
d3245b28 BH |
704 | int rc; |
705 | ||
8ceee660 BH |
706 | EFX_ASSERT_RESET_SERIALISED(efx); |
707 | ||
708 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 709 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 710 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
711 | |
712 | return rc; | |
8ceee660 BH |
713 | } |
714 | ||
8be4f3e6 BH |
715 | /* Asynchronous work item for changing MAC promiscuity and multicast |
716 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
717 | * MAC directly. */ | |
766ca0fa BH |
718 | static void efx_mac_work(struct work_struct *data) |
719 | { | |
720 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
721 | ||
722 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 723 | if (efx->port_enabled) { |
ef2b90ee | 724 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
725 | efx->mac_op->reconfigure(efx); |
726 | } | |
766ca0fa BH |
727 | mutex_unlock(&efx->mac_lock); |
728 | } | |
729 | ||
8ceee660 BH |
730 | static int efx_probe_port(struct efx_nic *efx) |
731 | { | |
732 | int rc; | |
733 | ||
734 | EFX_LOG(efx, "create port\n"); | |
735 | ||
ff3b00a0 SH |
736 | if (phy_flash_cfg) |
737 | efx->phy_mode = PHY_MODE_SPECIAL; | |
738 | ||
ef2b90ee BH |
739 | /* Connect up MAC/PHY operations table */ |
740 | rc = efx->type->probe_port(efx); | |
8ceee660 BH |
741 | if (rc) |
742 | goto err; | |
743 | ||
744 | /* Sanity check MAC address */ | |
745 | if (is_valid_ether_addr(efx->mac_address)) { | |
746 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
747 | } else { | |
e174961c JB |
748 | EFX_ERR(efx, "invalid MAC address %pM\n", |
749 | efx->mac_address); | |
8ceee660 BH |
750 | if (!allow_bad_hwaddr) { |
751 | rc = -EINVAL; | |
752 | goto err; | |
753 | } | |
754 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
755 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
756 | efx->net_dev->dev_addr); | |
8ceee660 BH |
757 | } |
758 | ||
759 | return 0; | |
760 | ||
761 | err: | |
762 | efx_remove_port(efx); | |
763 | return rc; | |
764 | } | |
765 | ||
766 | static int efx_init_port(struct efx_nic *efx) | |
767 | { | |
768 | int rc; | |
769 | ||
770 | EFX_LOG(efx, "init port\n"); | |
771 | ||
1dfc5cea BH |
772 | mutex_lock(&efx->mac_lock); |
773 | ||
177dfcd8 | 774 | rc = efx->phy_op->init(efx); |
8ceee660 | 775 | if (rc) |
1dfc5cea | 776 | goto fail1; |
8ceee660 | 777 | |
dc8cfa55 | 778 | efx->port_initialized = true; |
1dfc5cea | 779 | |
d3245b28 BH |
780 | /* Reconfigure the MAC before creating dma queues (required for |
781 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
782 | efx->mac_op->reconfigure(efx); | |
783 | ||
784 | /* Ensure the PHY advertises the correct flow control settings */ | |
785 | rc = efx->phy_op->reconfigure(efx); | |
786 | if (rc) | |
787 | goto fail2; | |
788 | ||
1dfc5cea | 789 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 790 | return 0; |
177dfcd8 | 791 | |
1dfc5cea | 792 | fail2: |
177dfcd8 | 793 | efx->phy_op->fini(efx); |
1dfc5cea BH |
794 | fail1: |
795 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 796 | return rc; |
8ceee660 BH |
797 | } |
798 | ||
8ceee660 BH |
799 | static void efx_start_port(struct efx_nic *efx) |
800 | { | |
801 | EFX_LOG(efx, "start port\n"); | |
802 | BUG_ON(efx->port_enabled); | |
803 | ||
804 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 805 | efx->port_enabled = true; |
8be4f3e6 BH |
806 | |
807 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
808 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 809 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
810 | efx->mac_op->reconfigure(efx); |
811 | ||
8ceee660 BH |
812 | mutex_unlock(&efx->mac_lock); |
813 | } | |
814 | ||
fdaa9aed | 815 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
816 | static void efx_stop_port(struct efx_nic *efx) |
817 | { | |
818 | EFX_LOG(efx, "stop port\n"); | |
819 | ||
820 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 821 | efx->port_enabled = false; |
8ceee660 BH |
822 | mutex_unlock(&efx->mac_lock); |
823 | ||
824 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 825 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
826 | netif_addr_lock_bh(efx->net_dev); |
827 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
828 | } |
829 | } | |
830 | ||
831 | static void efx_fini_port(struct efx_nic *efx) | |
832 | { | |
833 | EFX_LOG(efx, "shut down port\n"); | |
834 | ||
835 | if (!efx->port_initialized) | |
836 | return; | |
837 | ||
177dfcd8 | 838 | efx->phy_op->fini(efx); |
dc8cfa55 | 839 | efx->port_initialized = false; |
8ceee660 | 840 | |
eb50c0d6 | 841 | efx->link_state.up = false; |
8ceee660 BH |
842 | efx_link_status_changed(efx); |
843 | } | |
844 | ||
845 | static void efx_remove_port(struct efx_nic *efx) | |
846 | { | |
847 | EFX_LOG(efx, "destroying port\n"); | |
848 | ||
ef2b90ee | 849 | efx->type->remove_port(efx); |
8ceee660 BH |
850 | } |
851 | ||
852 | /************************************************************************** | |
853 | * | |
854 | * NIC handling | |
855 | * | |
856 | **************************************************************************/ | |
857 | ||
858 | /* This configures the PCI device to enable I/O and DMA. */ | |
859 | static int efx_init_io(struct efx_nic *efx) | |
860 | { | |
861 | struct pci_dev *pci_dev = efx->pci_dev; | |
862 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
863 | int rc; | |
864 | ||
865 | EFX_LOG(efx, "initialising I/O\n"); | |
866 | ||
867 | rc = pci_enable_device(pci_dev); | |
868 | if (rc) { | |
869 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
870 | goto fail1; | |
871 | } | |
872 | ||
873 | pci_set_master(pci_dev); | |
874 | ||
875 | /* Set the PCI DMA mask. Try all possibilities from our | |
876 | * genuine mask down to 32 bits, because some architectures | |
877 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
878 | * masks event though they reject 46 bit masks. | |
879 | */ | |
880 | while (dma_mask > 0x7fffffffUL) { | |
881 | if (pci_dma_supported(pci_dev, dma_mask) && | |
882 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
883 | break; | |
884 | dma_mask >>= 1; | |
885 | } | |
886 | if (rc) { | |
887 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
888 | goto fail2; | |
889 | } | |
890 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
891 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
892 | if (rc) { | |
893 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
894 | * fail with a mask that pci_set_dma_mask() accepted, | |
895 | * but just in case... | |
896 | */ | |
897 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
898 | goto fail2; | |
899 | } | |
900 | ||
dc803df8 BH |
901 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
902 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 BH |
903 | if (rc) { |
904 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
905 | rc = -EIO; | |
906 | goto fail3; | |
907 | } | |
908 | efx->membase = ioremap_nocache(efx->membase_phys, | |
909 | efx->type->mem_map_size); | |
910 | if (!efx->membase) { | |
dc803df8 | 911 | EFX_ERR(efx, "could not map memory BAR at %llx+%x\n", |
086ea356 | 912 | (unsigned long long)efx->membase_phys, |
8ceee660 BH |
913 | efx->type->mem_map_size); |
914 | rc = -ENOMEM; | |
915 | goto fail4; | |
916 | } | |
dc803df8 BH |
917 | EFX_LOG(efx, "memory BAR at %llx+%x (virtual %p)\n", |
918 | (unsigned long long)efx->membase_phys, | |
086ea356 | 919 | efx->type->mem_map_size, efx->membase); |
8ceee660 BH |
920 | |
921 | return 0; | |
922 | ||
923 | fail4: | |
dc803df8 | 924 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 925 | fail3: |
2c118e0f | 926 | efx->membase_phys = 0; |
8ceee660 BH |
927 | fail2: |
928 | pci_disable_device(efx->pci_dev); | |
929 | fail1: | |
930 | return rc; | |
931 | } | |
932 | ||
933 | static void efx_fini_io(struct efx_nic *efx) | |
934 | { | |
935 | EFX_LOG(efx, "shutting down I/O\n"); | |
936 | ||
937 | if (efx->membase) { | |
938 | iounmap(efx->membase); | |
939 | efx->membase = NULL; | |
940 | } | |
941 | ||
942 | if (efx->membase_phys) { | |
dc803df8 | 943 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 944 | efx->membase_phys = 0; |
8ceee660 BH |
945 | } |
946 | ||
947 | pci_disable_device(efx->pci_dev); | |
948 | } | |
949 | ||
a4900ac9 BH |
950 | /* Get number of channels wanted. Each channel will have its own IRQ, |
951 | * 1 RX queue and/or 2 TX queues. */ | |
952 | static int efx_wanted_channels(void) | |
46123d04 | 953 | { |
2f8975fb | 954 | cpumask_var_t core_mask; |
46123d04 BH |
955 | int count; |
956 | int cpu; | |
957 | ||
79f55997 | 958 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 959 | printk(KERN_WARNING |
3977d033 | 960 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
961 | return 1; |
962 | } | |
963 | ||
46123d04 BH |
964 | count = 0; |
965 | for_each_online_cpu(cpu) { | |
2f8975fb | 966 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 967 | ++count; |
2f8975fb | 968 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 969 | topology_core_cpumask(cpu)); |
46123d04 BH |
970 | } |
971 | } | |
972 | ||
2f8975fb | 973 | free_cpumask_var(core_mask); |
46123d04 BH |
974 | return count; |
975 | } | |
976 | ||
977 | /* Probe the number and type of interrupts we are able to obtain, and | |
978 | * the resulting numbers of channels and RX queues. | |
979 | */ | |
8ceee660 BH |
980 | static void efx_probe_interrupts(struct efx_nic *efx) |
981 | { | |
46123d04 BH |
982 | int max_channels = |
983 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
984 | int rc, i; |
985 | ||
986 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 987 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 988 | int n_channels; |
aa6ef27e | 989 | |
a4900ac9 BH |
990 | n_channels = efx_wanted_channels(); |
991 | if (separate_tx_channels) | |
992 | n_channels *= 2; | |
993 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 994 | |
a4900ac9 | 995 | for (i = 0; i < n_channels; i++) |
8ceee660 | 996 | xentries[i].entry = i; |
a4900ac9 | 997 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 998 | if (rc > 0) { |
28b581ab | 999 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
a4900ac9 | 1000 | " available (%d < %d).\n", rc, n_channels); |
28b581ab | 1001 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); |
a4900ac9 BH |
1002 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1003 | n_channels = rc; | |
8ceee660 | 1004 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1005 | n_channels); |
8ceee660 BH |
1006 | } |
1007 | ||
1008 | if (rc == 0) { | |
a4900ac9 BH |
1009 | efx->n_channels = n_channels; |
1010 | if (separate_tx_channels) { | |
1011 | efx->n_tx_channels = | |
1012 | max(efx->n_channels / 2, 1U); | |
1013 | efx->n_rx_channels = | |
1014 | max(efx->n_channels - | |
1015 | efx->n_tx_channels, 1U); | |
1016 | } else { | |
1017 | efx->n_tx_channels = efx->n_channels; | |
1018 | efx->n_rx_channels = efx->n_channels; | |
1019 | } | |
1020 | for (i = 0; i < n_channels; i++) | |
8ceee660 | 1021 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
1022 | } else { |
1023 | /* Fall back to single channel MSI */ | |
1024 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
1025 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | /* Try single interrupt MSI */ | |
1030 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1031 | efx->n_channels = 1; |
a4900ac9 BH |
1032 | efx->n_rx_channels = 1; |
1033 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1034 | rc = pci_enable_msi(efx->pci_dev); |
1035 | if (rc == 0) { | |
1036 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
1037 | } else { |
1038 | EFX_ERR(efx, "could not enable MSI\n"); | |
1039 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /* Assume legacy interrupts */ | |
1044 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1045 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1046 | efx->n_rx_channels = 1; |
1047 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1048 | efx->legacy_irq = efx->pci_dev->irq; |
1049 | } | |
1050 | } | |
1051 | ||
1052 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1053 | { | |
1054 | struct efx_channel *channel; | |
1055 | ||
1056 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1057 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1058 | channel->irq = 0; |
1059 | pci_disable_msi(efx->pci_dev); | |
1060 | pci_disable_msix(efx->pci_dev); | |
1061 | ||
1062 | /* Remove legacy interrupt */ | |
1063 | efx->legacy_irq = 0; | |
1064 | } | |
1065 | ||
8831da7b | 1066 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1067 | { |
a4900ac9 | 1068 | struct efx_channel *channel; |
8ceee660 BH |
1069 | struct efx_tx_queue *tx_queue; |
1070 | struct efx_rx_queue *rx_queue; | |
a4900ac9 BH |
1071 | unsigned tx_channel_offset = |
1072 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; | |
8ceee660 | 1073 | |
a4900ac9 BH |
1074 | efx_for_each_channel(channel, efx) { |
1075 | if (channel->channel - tx_channel_offset < efx->n_tx_channels) { | |
1076 | channel->tx_queue = &efx->tx_queue[ | |
1077 | (channel->channel - tx_channel_offset) * | |
1078 | EFX_TXQ_TYPES]; | |
1079 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1080 | tx_queue->channel = channel; | |
1081 | } | |
60ac1065 | 1082 | } |
8ceee660 | 1083 | |
a4900ac9 | 1084 | efx_for_each_rx_queue(rx_queue, efx) |
8831da7b | 1085 | rx_queue->channel = &efx->channel[rx_queue->queue]; |
8ceee660 BH |
1086 | } |
1087 | ||
1088 | static int efx_probe_nic(struct efx_nic *efx) | |
1089 | { | |
1090 | int rc; | |
1091 | ||
1092 | EFX_LOG(efx, "creating NIC\n"); | |
1093 | ||
1094 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1095 | rc = efx->type->probe(efx); |
8ceee660 BH |
1096 | if (rc) |
1097 | return rc; | |
1098 | ||
a4900ac9 | 1099 | /* Determine the number of channels and queues by trying to hook |
8ceee660 BH |
1100 | * in MSI-X interrupts. */ |
1101 | efx_probe_interrupts(efx); | |
1102 | ||
8831da7b | 1103 | efx_set_channels(efx); |
a4900ac9 | 1104 | efx->net_dev->real_num_tx_queues = efx->n_tx_channels; |
8ceee660 BH |
1105 | |
1106 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1107 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1108 | |
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | static void efx_remove_nic(struct efx_nic *efx) | |
1113 | { | |
1114 | EFX_LOG(efx, "destroying NIC\n"); | |
1115 | ||
1116 | efx_remove_interrupts(efx); | |
ef2b90ee | 1117 | efx->type->remove(efx); |
8ceee660 BH |
1118 | } |
1119 | ||
1120 | /************************************************************************** | |
1121 | * | |
1122 | * NIC startup/shutdown | |
1123 | * | |
1124 | *************************************************************************/ | |
1125 | ||
1126 | static int efx_probe_all(struct efx_nic *efx) | |
1127 | { | |
1128 | struct efx_channel *channel; | |
1129 | int rc; | |
1130 | ||
1131 | /* Create NIC */ | |
1132 | rc = efx_probe_nic(efx); | |
1133 | if (rc) { | |
1134 | EFX_ERR(efx, "failed to create NIC\n"); | |
1135 | goto fail1; | |
1136 | } | |
1137 | ||
1138 | /* Create port */ | |
1139 | rc = efx_probe_port(efx); | |
1140 | if (rc) { | |
1141 | EFX_ERR(efx, "failed to create port\n"); | |
1142 | goto fail2; | |
1143 | } | |
1144 | ||
1145 | /* Create channels */ | |
1146 | efx_for_each_channel(channel, efx) { | |
1147 | rc = efx_probe_channel(channel); | |
1148 | if (rc) { | |
1149 | EFX_ERR(efx, "failed to create channel %d\n", | |
1150 | channel->channel); | |
1151 | goto fail3; | |
1152 | } | |
1153 | } | |
56536e9c | 1154 | efx_set_channel_names(efx); |
8ceee660 BH |
1155 | |
1156 | return 0; | |
1157 | ||
1158 | fail3: | |
1159 | efx_for_each_channel(channel, efx) | |
1160 | efx_remove_channel(channel); | |
1161 | efx_remove_port(efx); | |
1162 | fail2: | |
1163 | efx_remove_nic(efx); | |
1164 | fail1: | |
1165 | return rc; | |
1166 | } | |
1167 | ||
1168 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1169 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1170 | * and ensures that the port is scheduled to be reconfigured. | |
1171 | * This function is safe to call multiple times when the NIC is in any | |
1172 | * state. */ | |
1173 | static void efx_start_all(struct efx_nic *efx) | |
1174 | { | |
1175 | struct efx_channel *channel; | |
1176 | ||
1177 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1178 | ||
1179 | /* Check that it is appropriate to restart the interface. All | |
1180 | * of these flags are safe to read under just the rtnl lock */ | |
1181 | if (efx->port_enabled) | |
1182 | return; | |
1183 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1184 | return; | |
55668611 | 1185 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1186 | return; |
1187 | ||
1188 | /* Mark the port as enabled so port reconfigurations can start, then | |
1189 | * restart the transmit interface early so the watchdog timer stops */ | |
1190 | efx_start_port(efx); | |
8ceee660 | 1191 | |
a4900ac9 BH |
1192 | efx_for_each_channel(channel, efx) { |
1193 | if (efx_dev_registered(efx)) | |
1194 | efx_wake_queue(channel); | |
8ceee660 | 1195 | efx_start_channel(channel); |
a4900ac9 | 1196 | } |
8ceee660 | 1197 | |
152b6a62 | 1198 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1199 | |
8880f4ec BH |
1200 | /* Switch to event based MCDI completions after enabling interrupts. |
1201 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1202 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1203 | * reset_pending [modified from an atomic context], we instead guarantee | |
1204 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1205 | efx_mcdi_mode_event(efx); | |
1206 | if (efx->reset_pending != RESET_TYPE_NONE) | |
1207 | efx_mcdi_mode_poll(efx); | |
1208 | ||
78c1f0a0 SH |
1209 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1210 | * event driven), we have to poll the PHY because after an event queue | |
1211 | * flush, we could have a missed a link state change */ | |
1212 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1213 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1214 | efx_monitor_interval); | |
78c1f0a0 SH |
1215 | } else { |
1216 | mutex_lock(&efx->mac_lock); | |
1217 | if (efx->phy_op->poll(efx)) | |
1218 | efx_link_status_changed(efx); | |
1219 | mutex_unlock(&efx->mac_lock); | |
1220 | } | |
55edc6e6 | 1221 | |
ef2b90ee | 1222 | efx->type->start_stats(efx); |
8ceee660 BH |
1223 | } |
1224 | ||
1225 | /* Flush all delayed work. Should only be called when no more delayed work | |
1226 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1227 | * since we're holding the rtnl_lock at this point. */ | |
1228 | static void efx_flush_all(struct efx_nic *efx) | |
1229 | { | |
8ceee660 BH |
1230 | /* Make sure the hardware monitor is stopped */ |
1231 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1232 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1233 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1234 | } |
1235 | ||
1236 | /* Quiesce hardware and software without bringing the link down. | |
1237 | * Safe to call multiple times, when the nic and interface is in any | |
1238 | * state. The caller is guaranteed to subsequently be in a position | |
1239 | * to modify any hardware and software state they see fit without | |
1240 | * taking locks. */ | |
1241 | static void efx_stop_all(struct efx_nic *efx) | |
1242 | { | |
1243 | struct efx_channel *channel; | |
1244 | ||
1245 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1246 | ||
1247 | /* port_enabled can be read safely under the rtnl lock */ | |
1248 | if (!efx->port_enabled) | |
1249 | return; | |
1250 | ||
ef2b90ee | 1251 | efx->type->stop_stats(efx); |
55edc6e6 | 1252 | |
8880f4ec BH |
1253 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1254 | efx_mcdi_mode_poll(efx); | |
1255 | ||
8ceee660 | 1256 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1257 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
1258 | if (efx->legacy_irq) |
1259 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1260 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1261 | if (channel->irq) |
1262 | synchronize_irq(channel->irq); | |
b3475645 | 1263 | } |
8ceee660 BH |
1264 | |
1265 | /* Stop all NAPI processing and synchronous rx refills */ | |
1266 | efx_for_each_channel(channel, efx) | |
1267 | efx_stop_channel(channel); | |
1268 | ||
1269 | /* Stop all asynchronous port reconfigurations. Since all | |
1270 | * event processing has already been stopped, there is no | |
1271 | * window to loose phy events */ | |
1272 | efx_stop_port(efx); | |
1273 | ||
fdaa9aed | 1274 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1275 | efx_flush_all(efx); |
1276 | ||
8ceee660 BH |
1277 | /* Stop the kernel transmit interface late, so the watchdog |
1278 | * timer isn't ticking over the flush */ | |
55668611 | 1279 | if (efx_dev_registered(efx)) { |
a4900ac9 BH |
1280 | struct efx_channel *channel; |
1281 | efx_for_each_channel(channel, efx) | |
1282 | efx_stop_queue(channel); | |
8ceee660 BH |
1283 | netif_tx_lock_bh(efx->net_dev); |
1284 | netif_tx_unlock_bh(efx->net_dev); | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | static void efx_remove_all(struct efx_nic *efx) | |
1289 | { | |
1290 | struct efx_channel *channel; | |
1291 | ||
1292 | efx_for_each_channel(channel, efx) | |
1293 | efx_remove_channel(channel); | |
1294 | efx_remove_port(efx); | |
1295 | efx_remove_nic(efx); | |
1296 | } | |
1297 | ||
8ceee660 BH |
1298 | /************************************************************************** |
1299 | * | |
1300 | * Interrupt moderation | |
1301 | * | |
1302 | **************************************************************************/ | |
1303 | ||
0d86ebd8 BH |
1304 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1305 | { | |
1306 | if (usecs <= 0) | |
1307 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1308 | if (usecs < resolution) | |
1309 | return 1; /* never round down to 0 */ | |
1310 | return usecs / resolution; | |
1311 | } | |
1312 | ||
8ceee660 | 1313 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1314 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1315 | bool rx_adaptive) | |
8ceee660 BH |
1316 | { |
1317 | struct efx_tx_queue *tx_queue; | |
1318 | struct efx_rx_queue *rx_queue; | |
152b6a62 BH |
1319 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1320 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1321 | |
1322 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1323 | ||
1324 | efx_for_each_tx_queue(tx_queue, efx) | |
0d86ebd8 | 1325 | tx_queue->channel->irq_moderation = tx_ticks; |
8ceee660 | 1326 | |
6fb70fd1 | 1327 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1328 | efx->irq_rx_moderation = rx_ticks; |
8ceee660 | 1329 | efx_for_each_rx_queue(rx_queue, efx) |
0d86ebd8 | 1330 | rx_queue->channel->irq_moderation = rx_ticks; |
8ceee660 BH |
1331 | } |
1332 | ||
1333 | /************************************************************************** | |
1334 | * | |
1335 | * Hardware monitor | |
1336 | * | |
1337 | **************************************************************************/ | |
1338 | ||
1339 | /* Run periodically off the general workqueue. Serialised against | |
1340 | * efx_reconfigure_port via the mac_lock */ | |
1341 | static void efx_monitor(struct work_struct *data) | |
1342 | { | |
1343 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1344 | monitor_work.work); | |
8ceee660 BH |
1345 | |
1346 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1347 | raw_smp_processor_id()); | |
ef2b90ee | 1348 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1349 | |
8ceee660 BH |
1350 | /* If the mac_lock is already held then it is likely a port |
1351 | * reconfiguration is already in place, which will likely do | |
1352 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1353 | if (!mutex_trylock(&efx->mac_lock)) |
1354 | goto out_requeue; | |
1355 | if (!efx->port_enabled) | |
1356 | goto out_unlock; | |
ef2b90ee | 1357 | efx->type->monitor(efx); |
8ceee660 | 1358 | |
766ca0fa | 1359 | out_unlock: |
8ceee660 | 1360 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1361 | out_requeue: |
8ceee660 BH |
1362 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1363 | efx_monitor_interval); | |
1364 | } | |
1365 | ||
1366 | /************************************************************************** | |
1367 | * | |
1368 | * ioctls | |
1369 | * | |
1370 | *************************************************************************/ | |
1371 | ||
1372 | /* Net device ioctl | |
1373 | * Context: process, rtnl_lock() held. | |
1374 | */ | |
1375 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1376 | { | |
767e468c | 1377 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1378 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1379 | |
1380 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1381 | ||
68e7f45e BH |
1382 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1383 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1384 | (data->phy_id & 0xfc00) == 0x0400) | |
1385 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1386 | ||
1387 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1388 | } |
1389 | ||
1390 | /************************************************************************** | |
1391 | * | |
1392 | * NAPI interface | |
1393 | * | |
1394 | **************************************************************************/ | |
1395 | ||
1396 | static int efx_init_napi(struct efx_nic *efx) | |
1397 | { | |
1398 | struct efx_channel *channel; | |
8ceee660 BH |
1399 | |
1400 | efx_for_each_channel(channel, efx) { | |
1401 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1402 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1403 | efx_poll, napi_weight); | |
8ceee660 BH |
1404 | } |
1405 | return 0; | |
8ceee660 BH |
1406 | } |
1407 | ||
1408 | static void efx_fini_napi(struct efx_nic *efx) | |
1409 | { | |
1410 | struct efx_channel *channel; | |
1411 | ||
1412 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1413 | if (channel->napi_dev) |
1414 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1415 | channel->napi_dev = NULL; |
1416 | } | |
1417 | } | |
1418 | ||
1419 | /************************************************************************** | |
1420 | * | |
1421 | * Kernel netpoll interface | |
1422 | * | |
1423 | *************************************************************************/ | |
1424 | ||
1425 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1426 | ||
1427 | /* Although in the common case interrupts will be disabled, this is not | |
1428 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1429 | * so no locking is required. | |
1430 | */ | |
1431 | static void efx_netpoll(struct net_device *net_dev) | |
1432 | { | |
767e468c | 1433 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1434 | struct efx_channel *channel; |
1435 | ||
64ee3120 | 1436 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1437 | efx_schedule_channel(channel); |
1438 | } | |
1439 | ||
1440 | #endif | |
1441 | ||
1442 | /************************************************************************** | |
1443 | * | |
1444 | * Kernel net device interface | |
1445 | * | |
1446 | *************************************************************************/ | |
1447 | ||
1448 | /* Context: process, rtnl_lock() held. */ | |
1449 | static int efx_net_open(struct net_device *net_dev) | |
1450 | { | |
767e468c | 1451 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1452 | EFX_ASSERT_RESET_SERIALISED(efx); |
1453 | ||
1454 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1455 | raw_smp_processor_id()); | |
1456 | ||
f4bd954e BH |
1457 | if (efx->state == STATE_DISABLED) |
1458 | return -EIO; | |
f8b87c17 BH |
1459 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1460 | return -EBUSY; | |
8880f4ec BH |
1461 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1462 | return -EIO; | |
f8b87c17 | 1463 | |
78c1f0a0 SH |
1464 | /* Notify the kernel of the link state polled during driver load, |
1465 | * before the monitor starts running */ | |
1466 | efx_link_status_changed(efx); | |
1467 | ||
8ceee660 BH |
1468 | efx_start_all(efx); |
1469 | return 0; | |
1470 | } | |
1471 | ||
1472 | /* Context: process, rtnl_lock() held. | |
1473 | * Note that the kernel will ignore our return code; this method | |
1474 | * should really be a void. | |
1475 | */ | |
1476 | static int efx_net_stop(struct net_device *net_dev) | |
1477 | { | |
767e468c | 1478 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1479 | |
1480 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1481 | raw_smp_processor_id()); | |
1482 | ||
f4bd954e BH |
1483 | if (efx->state != STATE_DISABLED) { |
1484 | /* Stop the device and flush all the channels */ | |
1485 | efx_stop_all(efx); | |
1486 | efx_fini_channels(efx); | |
1487 | efx_init_channels(efx); | |
1488 | } | |
8ceee660 BH |
1489 | |
1490 | return 0; | |
1491 | } | |
1492 | ||
5b9e207c | 1493 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1494 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1495 | { | |
767e468c | 1496 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1497 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1498 | struct net_device_stats *stats = &net_dev->stats; | |
1499 | ||
55edc6e6 | 1500 | spin_lock_bh(&efx->stats_lock); |
ef2b90ee | 1501 | efx->type->update_stats(efx); |
55edc6e6 | 1502 | spin_unlock_bh(&efx->stats_lock); |
8ceee660 BH |
1503 | |
1504 | stats->rx_packets = mac_stats->rx_packets; | |
1505 | stats->tx_packets = mac_stats->tx_packets; | |
1506 | stats->rx_bytes = mac_stats->rx_bytes; | |
1507 | stats->tx_bytes = mac_stats->tx_bytes; | |
1508 | stats->multicast = mac_stats->rx_multicast; | |
1509 | stats->collisions = mac_stats->tx_collision; | |
1510 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1511 | mac_stats->rx_length_error); | |
1512 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1513 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1514 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1515 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1516 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1517 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1518 | ||
1519 | stats->rx_errors = (stats->rx_length_errors + | |
1520 | stats->rx_over_errors + | |
1521 | stats->rx_crc_errors + | |
1522 | stats->rx_frame_errors + | |
1523 | stats->rx_fifo_errors + | |
1524 | stats->rx_missed_errors + | |
1525 | mac_stats->rx_symbol_error); | |
1526 | stats->tx_errors = (stats->tx_window_errors + | |
1527 | mac_stats->tx_bad); | |
1528 | ||
1529 | return stats; | |
1530 | } | |
1531 | ||
1532 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1533 | static void efx_watchdog(struct net_device *net_dev) | |
1534 | { | |
767e468c | 1535 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1536 | |
a4900ac9 BH |
1537 | EFX_ERR(efx, "TX stuck with port_enabled=%d: resetting channels\n", |
1538 | efx->port_enabled); | |
8ceee660 | 1539 | |
739bb23d | 1540 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1541 | } |
1542 | ||
1543 | ||
1544 | /* Context: process, rtnl_lock() held. */ | |
1545 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1546 | { | |
767e468c | 1547 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1548 | int rc = 0; |
1549 | ||
1550 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1551 | ||
1552 | if (new_mtu > EFX_MAX_MTU) | |
1553 | return -EINVAL; | |
1554 | ||
1555 | efx_stop_all(efx); | |
1556 | ||
1557 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1558 | ||
1559 | efx_fini_channels(efx); | |
d3245b28 BH |
1560 | |
1561 | mutex_lock(&efx->mac_lock); | |
1562 | /* Reconfigure the MAC before enabling the dma queues so that | |
1563 | * the RX buffers don't overflow */ | |
8ceee660 | 1564 | net_dev->mtu = new_mtu; |
d3245b28 BH |
1565 | efx->mac_op->reconfigure(efx); |
1566 | mutex_unlock(&efx->mac_lock); | |
1567 | ||
bc3c90a2 | 1568 | efx_init_channels(efx); |
8ceee660 BH |
1569 | |
1570 | efx_start_all(efx); | |
1571 | return rc; | |
8ceee660 BH |
1572 | } |
1573 | ||
1574 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1575 | { | |
767e468c | 1576 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1577 | struct sockaddr *addr = data; |
1578 | char *new_addr = addr->sa_data; | |
1579 | ||
1580 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1581 | ||
1582 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1583 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1584 | new_addr); | |
8ceee660 BH |
1585 | return -EINVAL; |
1586 | } | |
1587 | ||
1588 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1589 | ||
1590 | /* Reconfigure the MAC */ | |
d3245b28 BH |
1591 | mutex_lock(&efx->mac_lock); |
1592 | efx->mac_op->reconfigure(efx); | |
1593 | mutex_unlock(&efx->mac_lock); | |
8ceee660 BH |
1594 | |
1595 | return 0; | |
1596 | } | |
1597 | ||
a816f75a | 1598 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1599 | static void efx_set_multicast_list(struct net_device *net_dev) |
1600 | { | |
767e468c | 1601 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1602 | struct netdev_hw_addr *ha; |
8ceee660 | 1603 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1604 | u32 crc; |
1605 | int bit; | |
8ceee660 | 1606 | |
8be4f3e6 | 1607 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1608 | |
1609 | /* Build multicast hash table */ | |
8be4f3e6 | 1610 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1611 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1612 | } else { | |
1613 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1614 | netdev_for_each_mc_addr(ha, net_dev) { |
1615 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1616 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1617 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1618 | } |
8ceee660 | 1619 | |
8be4f3e6 BH |
1620 | /* Broadcast packets go through the multicast hash filter. |
1621 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1622 | * so we always add bit 0xff to the mask. | |
1623 | */ | |
1624 | set_bit_le(0xff, mc_hash->byte); | |
1625 | } | |
a816f75a | 1626 | |
8be4f3e6 BH |
1627 | if (efx->port_enabled) |
1628 | queue_work(efx->workqueue, &efx->mac_work); | |
1629 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1630 | } |
1631 | ||
c3ecb9f3 SH |
1632 | static const struct net_device_ops efx_netdev_ops = { |
1633 | .ndo_open = efx_net_open, | |
1634 | .ndo_stop = efx_net_stop, | |
1635 | .ndo_get_stats = efx_net_stats, | |
1636 | .ndo_tx_timeout = efx_watchdog, | |
1637 | .ndo_start_xmit = efx_hard_start_xmit, | |
1638 | .ndo_validate_addr = eth_validate_addr, | |
1639 | .ndo_do_ioctl = efx_ioctl, | |
1640 | .ndo_change_mtu = efx_change_mtu, | |
1641 | .ndo_set_mac_address = efx_set_mac_address, | |
1642 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1643 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1644 | .ndo_poll_controller = efx_netpoll, | |
1645 | #endif | |
1646 | }; | |
1647 | ||
7dde596e BH |
1648 | static void efx_update_name(struct efx_nic *efx) |
1649 | { | |
1650 | strcpy(efx->name, efx->net_dev->name); | |
1651 | efx_mtd_rename(efx); | |
1652 | efx_set_channel_names(efx); | |
1653 | } | |
1654 | ||
8ceee660 BH |
1655 | static int efx_netdev_event(struct notifier_block *this, |
1656 | unsigned long event, void *ptr) | |
1657 | { | |
d3208b5e | 1658 | struct net_device *net_dev = ptr; |
8ceee660 | 1659 | |
7dde596e BH |
1660 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1661 | event == NETDEV_CHANGENAME) | |
1662 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1663 | |
1664 | return NOTIFY_DONE; | |
1665 | } | |
1666 | ||
1667 | static struct notifier_block efx_netdev_notifier = { | |
1668 | .notifier_call = efx_netdev_event, | |
1669 | }; | |
1670 | ||
06d5e193 BH |
1671 | static ssize_t |
1672 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1673 | { | |
1674 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1675 | return sprintf(buf, "%d\n", efx->phy_type); | |
1676 | } | |
1677 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1678 | ||
8ceee660 BH |
1679 | static int efx_register_netdev(struct efx_nic *efx) |
1680 | { | |
1681 | struct net_device *net_dev = efx->net_dev; | |
1682 | int rc; | |
1683 | ||
1684 | net_dev->watchdog_timeo = 5 * HZ; | |
1685 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1686 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1687 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1688 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1689 | ||
8ceee660 | 1690 | /* Clear MAC statistics */ |
177dfcd8 | 1691 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1692 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1693 | ||
7dde596e | 1694 | rtnl_lock(); |
aed0628d BH |
1695 | |
1696 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1697 | if (rc < 0) | |
1698 | goto fail_locked; | |
7dde596e | 1699 | efx_update_name(efx); |
aed0628d BH |
1700 | |
1701 | rc = register_netdevice(net_dev); | |
1702 | if (rc) | |
1703 | goto fail_locked; | |
1704 | ||
1705 | /* Always start with carrier off; PHY events will detect the link */ | |
1706 | netif_carrier_off(efx->net_dev); | |
1707 | ||
7dde596e | 1708 | rtnl_unlock(); |
8ceee660 | 1709 | |
06d5e193 BH |
1710 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1711 | if (rc) { | |
1712 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1713 | goto fail_registered; | |
1714 | } | |
1715 | ||
8ceee660 | 1716 | return 0; |
06d5e193 | 1717 | |
aed0628d BH |
1718 | fail_locked: |
1719 | rtnl_unlock(); | |
1720 | EFX_ERR(efx, "could not register net dev\n"); | |
1721 | return rc; | |
1722 | ||
06d5e193 BH |
1723 | fail_registered: |
1724 | unregister_netdev(net_dev); | |
1725 | return rc; | |
8ceee660 BH |
1726 | } |
1727 | ||
1728 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1729 | { | |
1730 | struct efx_tx_queue *tx_queue; | |
1731 | ||
1732 | if (!efx->net_dev) | |
1733 | return; | |
1734 | ||
767e468c | 1735 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1736 | |
1737 | /* Free up any skbs still remaining. This has to happen before | |
1738 | * we try to unregister the netdev as running their destructors | |
1739 | * may be needed to get the device ref. count to 0. */ | |
1740 | efx_for_each_tx_queue(tx_queue, efx) | |
1741 | efx_release_tx_buffers(tx_queue); | |
1742 | ||
55668611 | 1743 | if (efx_dev_registered(efx)) { |
8ceee660 | 1744 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1745 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1746 | unregister_netdev(efx->net_dev); |
1747 | } | |
1748 | } | |
1749 | ||
1750 | /************************************************************************** | |
1751 | * | |
1752 | * Device reset and suspend | |
1753 | * | |
1754 | **************************************************************************/ | |
1755 | ||
2467ca46 BH |
1756 | /* Tears down the entire software state and most of the hardware state |
1757 | * before reset. */ | |
d3245b28 | 1758 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1759 | { |
8ceee660 BH |
1760 | EFX_ASSERT_RESET_SERIALISED(efx); |
1761 | ||
2467ca46 BH |
1762 | efx_stop_all(efx); |
1763 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1764 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1765 | |
8ceee660 | 1766 | efx_fini_channels(efx); |
4b988280 SH |
1767 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1768 | efx->phy_op->fini(efx); | |
ef2b90ee | 1769 | efx->type->fini(efx); |
8ceee660 BH |
1770 | } |
1771 | ||
2467ca46 BH |
1772 | /* This function will always ensure that the locks acquired in |
1773 | * efx_reset_down() are released. A failure return code indicates | |
1774 | * that we were unable to reinitialise the hardware, and the | |
1775 | * driver should be disabled. If ok is false, then the rx and tx | |
1776 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 1777 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
1778 | { |
1779 | int rc; | |
1780 | ||
2467ca46 | 1781 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1782 | |
ef2b90ee | 1783 | rc = efx->type->init(efx); |
8ceee660 | 1784 | if (rc) { |
2467ca46 | 1785 | EFX_ERR(efx, "failed to initialise NIC\n"); |
eb9f6744 | 1786 | goto fail; |
8ceee660 BH |
1787 | } |
1788 | ||
eb9f6744 BH |
1789 | if (!ok) |
1790 | goto fail; | |
1791 | ||
4b988280 | 1792 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
1793 | rc = efx->phy_op->init(efx); |
1794 | if (rc) | |
1795 | goto fail; | |
1796 | if (efx->phy_op->reconfigure(efx)) | |
1797 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
4b988280 SH |
1798 | } |
1799 | ||
eb9f6744 | 1800 | efx->mac_op->reconfigure(efx); |
8ceee660 | 1801 | |
eb9f6744 BH |
1802 | efx_init_channels(efx); |
1803 | ||
1804 | mutex_unlock(&efx->spi_lock); | |
1805 | mutex_unlock(&efx->mac_lock); | |
1806 | ||
1807 | efx_start_all(efx); | |
1808 | ||
1809 | return 0; | |
1810 | ||
1811 | fail: | |
1812 | efx->port_initialized = false; | |
2467ca46 | 1813 | |
f4150724 | 1814 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1815 | mutex_unlock(&efx->mac_lock); |
1816 | ||
8ceee660 BH |
1817 | return rc; |
1818 | } | |
1819 | ||
eb9f6744 BH |
1820 | /* Reset the NIC using the specified method. Note that the reset may |
1821 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 1822 | * |
eb9f6744 | 1823 | * Caller must hold the rtnl_lock. |
8ceee660 | 1824 | */ |
eb9f6744 | 1825 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1826 | { |
eb9f6744 BH |
1827 | int rc, rc2; |
1828 | bool disabled; | |
8ceee660 | 1829 | |
c459302d | 1830 | EFX_INFO(efx, "resetting (%s)\n", RESET_TYPE(method)); |
8ceee660 | 1831 | |
d3245b28 | 1832 | efx_reset_down(efx, method); |
8ceee660 | 1833 | |
ef2b90ee | 1834 | rc = efx->type->reset(efx, method); |
8ceee660 BH |
1835 | if (rc) { |
1836 | EFX_ERR(efx, "failed to reset hardware\n"); | |
eb9f6744 | 1837 | goto out; |
8ceee660 BH |
1838 | } |
1839 | ||
1840 | /* Allow resets to be rescheduled. */ | |
1841 | efx->reset_pending = RESET_TYPE_NONE; | |
1842 | ||
1843 | /* Reinitialise bus-mastering, which may have been turned off before | |
1844 | * the reset was scheduled. This is still appropriate, even in the | |
1845 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1846 | * can respond to requests. */ | |
1847 | pci_set_master(efx->pci_dev); | |
1848 | ||
eb9f6744 | 1849 | out: |
8ceee660 | 1850 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
1851 | disabled = rc || method == RESET_TYPE_DISABLE; |
1852 | rc2 = efx_reset_up(efx, method, !disabled); | |
1853 | if (rc2) { | |
1854 | disabled = true; | |
1855 | if (!rc) | |
1856 | rc = rc2; | |
8ceee660 BH |
1857 | } |
1858 | ||
eb9f6744 | 1859 | if (disabled) { |
f49a4589 | 1860 | dev_close(efx->net_dev); |
f4bd954e BH |
1861 | EFX_ERR(efx, "has been disabled\n"); |
1862 | efx->state = STATE_DISABLED; | |
f4bd954e BH |
1863 | } else { |
1864 | EFX_LOG(efx, "reset complete\n"); | |
1865 | } | |
8ceee660 BH |
1866 | return rc; |
1867 | } | |
1868 | ||
1869 | /* The worker thread exists so that code that cannot sleep can | |
1870 | * schedule a reset for later. | |
1871 | */ | |
1872 | static void efx_reset_work(struct work_struct *data) | |
1873 | { | |
eb9f6744 | 1874 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
8ceee660 | 1875 | |
319ba649 SH |
1876 | if (efx->reset_pending == RESET_TYPE_NONE) |
1877 | return; | |
1878 | ||
eb9f6744 BH |
1879 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
1880 | * flag set so that efx_pci_probe_main will be retried */ | |
1881 | if (efx->state != STATE_RUNNING) { | |
1882 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1883 | return; | |
1884 | } | |
1885 | ||
1886 | rtnl_lock(); | |
f49a4589 | 1887 | (void)efx_reset(efx, efx->reset_pending); |
eb9f6744 | 1888 | rtnl_unlock(); |
8ceee660 BH |
1889 | } |
1890 | ||
1891 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1892 | { | |
1893 | enum reset_type method; | |
1894 | ||
1895 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1896 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1897 | return; | |
1898 | } | |
1899 | ||
1900 | switch (type) { | |
1901 | case RESET_TYPE_INVISIBLE: | |
1902 | case RESET_TYPE_ALL: | |
1903 | case RESET_TYPE_WORLD: | |
1904 | case RESET_TYPE_DISABLE: | |
1905 | method = type; | |
1906 | break; | |
1907 | case RESET_TYPE_RX_RECOVERY: | |
1908 | case RESET_TYPE_RX_DESC_FETCH: | |
1909 | case RESET_TYPE_TX_DESC_FETCH: | |
1910 | case RESET_TYPE_TX_SKIP: | |
1911 | method = RESET_TYPE_INVISIBLE; | |
1912 | break; | |
8880f4ec | 1913 | case RESET_TYPE_MC_FAILURE: |
8ceee660 BH |
1914 | default: |
1915 | method = RESET_TYPE_ALL; | |
1916 | break; | |
1917 | } | |
1918 | ||
1919 | if (method != type) | |
c459302d BH |
1920 | EFX_LOG(efx, "scheduling %s reset for %s\n", |
1921 | RESET_TYPE(method), RESET_TYPE(type)); | |
8ceee660 | 1922 | else |
c459302d | 1923 | EFX_LOG(efx, "scheduling %s reset\n", RESET_TYPE(method)); |
8ceee660 BH |
1924 | |
1925 | efx->reset_pending = method; | |
1926 | ||
8880f4ec BH |
1927 | /* efx_process_channel() will no longer read events once a |
1928 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
1929 | efx_mcdi_mode_poll(efx); | |
1930 | ||
1ab00629 | 1931 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1932 | } |
1933 | ||
1934 | /************************************************************************** | |
1935 | * | |
1936 | * List of NICs we support | |
1937 | * | |
1938 | **************************************************************************/ | |
1939 | ||
1940 | /* PCI device ID table */ | |
a3aa1884 | 1941 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
8ceee660 | 1942 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), |
daeda630 | 1943 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
8ceee660 | 1944 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), |
daeda630 | 1945 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
8880f4ec BH |
1946 | {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID), |
1947 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
1948 | {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID), | |
1949 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
8ceee660 BH |
1950 | {0} /* end of list */ |
1951 | }; | |
1952 | ||
1953 | /************************************************************************** | |
1954 | * | |
3759433d | 1955 | * Dummy PHY/MAC operations |
8ceee660 | 1956 | * |
01aad7b6 | 1957 | * Can be used for some unimplemented operations |
8ceee660 BH |
1958 | * Needed so all function pointers are valid and do not have to be tested |
1959 | * before use | |
1960 | * | |
1961 | **************************************************************************/ | |
1962 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1963 | { | |
1964 | return 0; | |
1965 | } | |
1966 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
398468ed BH |
1967 | void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1968 | { | |
1969 | } | |
fdaa9aed SH |
1970 | bool efx_port_dummy_op_poll(struct efx_nic *efx) |
1971 | { | |
1972 | return false; | |
1973 | } | |
8ceee660 BH |
1974 | |
1975 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1976 | .init = efx_port_dummy_op_int, | |
d3245b28 | 1977 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 1978 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 1979 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
1980 | }; |
1981 | ||
8ceee660 BH |
1982 | /************************************************************************** |
1983 | * | |
1984 | * Data housekeeping | |
1985 | * | |
1986 | **************************************************************************/ | |
1987 | ||
1988 | /* This zeroes out and then fills in the invariants in a struct | |
1989 | * efx_nic (including all sub-structures). | |
1990 | */ | |
1991 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1992 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1993 | { | |
1994 | struct efx_channel *channel; | |
1995 | struct efx_tx_queue *tx_queue; | |
1996 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1997 | int i; |
8ceee660 BH |
1998 | |
1999 | /* Initialise common structures */ | |
2000 | memset(efx, 0, sizeof(*efx)); | |
2001 | spin_lock_init(&efx->biu_lock); | |
ab867461 | 2002 | mutex_init(&efx->mdio_lock); |
f4150724 | 2003 | mutex_init(&efx->spi_lock); |
76884835 BH |
2004 | #ifdef CONFIG_SFC_MTD |
2005 | INIT_LIST_HEAD(&efx->mtd_list); | |
2006 | #endif | |
8ceee660 BH |
2007 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2008 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2009 | efx->pci_dev = pci_dev; | |
2010 | efx->state = STATE_INIT; | |
2011 | efx->reset_pending = RESET_TYPE_NONE; | |
2012 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
2013 | |
2014 | efx->net_dev = net_dev; | |
dc8cfa55 | 2015 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
2016 | spin_lock_init(&efx->stats_lock); |
2017 | mutex_init(&efx->mac_lock); | |
b895d73e | 2018 | efx->mac_op = type->default_mac_ops; |
8ceee660 | 2019 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 2020 | efx->mdio.dev = net_dev; |
766ca0fa | 2021 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2022 | |
2023 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
2024 | channel = &efx->channel[i]; | |
2025 | channel->efx = efx; | |
2026 | channel->channel = i; | |
dc8cfa55 | 2027 | channel->work_pending = false; |
a4900ac9 BH |
2028 | spin_lock_init(&channel->tx_stop_lock); |
2029 | atomic_set(&channel->tx_stop_count, 1); | |
8ceee660 | 2030 | } |
a4900ac9 | 2031 | for (i = 0; i < EFX_MAX_TX_QUEUES; i++) { |
8ceee660 BH |
2032 | tx_queue = &efx->tx_queue[i]; |
2033 | tx_queue->efx = efx; | |
2034 | tx_queue->queue = i; | |
2035 | tx_queue->buffer = NULL; | |
2036 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 2037 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
2038 | } |
2039 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
2040 | rx_queue = &efx->rx_queue[i]; | |
2041 | rx_queue->efx = efx; | |
2042 | rx_queue->queue = i; | |
2043 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
2044 | rx_queue->buffer = NULL; | |
90d683af SH |
2045 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
2046 | (unsigned long)rx_queue); | |
8ceee660 BH |
2047 | } |
2048 | ||
2049 | efx->type = type; | |
2050 | ||
8ceee660 | 2051 | /* As close as we can get to guaranteeing that we don't overflow */ |
3ffeabdd BH |
2052 | BUILD_BUG_ON(EFX_EVQ_SIZE < EFX_TXQ_SIZE + EFX_RXQ_SIZE); |
2053 | ||
8ceee660 BH |
2054 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2055 | ||
2056 | /* Higher numbered interrupt modes are less capable! */ | |
2057 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2058 | interrupt_mode); | |
2059 | ||
6977dc63 BH |
2060 | /* Would be good to use the net_dev name, but we're too early */ |
2061 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2062 | pci_name(pci_dev)); | |
2063 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
2064 | if (!efx->workqueue) |
2065 | return -ENOMEM; | |
8d9853d9 | 2066 | |
8ceee660 | 2067 | return 0; |
8ceee660 BH |
2068 | } |
2069 | ||
2070 | static void efx_fini_struct(struct efx_nic *efx) | |
2071 | { | |
2072 | if (efx->workqueue) { | |
2073 | destroy_workqueue(efx->workqueue); | |
2074 | efx->workqueue = NULL; | |
2075 | } | |
2076 | } | |
2077 | ||
2078 | /************************************************************************** | |
2079 | * | |
2080 | * PCI interface | |
2081 | * | |
2082 | **************************************************************************/ | |
2083 | ||
2084 | /* Main body of final NIC shutdown code | |
2085 | * This is called only at module unload (or hotplug removal). | |
2086 | */ | |
2087 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2088 | { | |
152b6a62 | 2089 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2090 | efx_fini_channels(efx); |
2091 | efx_fini_port(efx); | |
ef2b90ee | 2092 | efx->type->fini(efx); |
8ceee660 BH |
2093 | efx_fini_napi(efx); |
2094 | efx_remove_all(efx); | |
2095 | } | |
2096 | ||
2097 | /* Final NIC shutdown | |
2098 | * This is called only at module unload (or hotplug removal). | |
2099 | */ | |
2100 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2101 | { | |
2102 | struct efx_nic *efx; | |
2103 | ||
2104 | efx = pci_get_drvdata(pci_dev); | |
2105 | if (!efx) | |
2106 | return; | |
2107 | ||
2108 | /* Mark the NIC as fini, then stop the interface */ | |
2109 | rtnl_lock(); | |
2110 | efx->state = STATE_FINI; | |
2111 | dev_close(efx->net_dev); | |
2112 | ||
2113 | /* Allow any queued efx_resets() to complete */ | |
2114 | rtnl_unlock(); | |
2115 | ||
8ceee660 BH |
2116 | efx_unregister_netdev(efx); |
2117 | ||
7dde596e BH |
2118 | efx_mtd_remove(efx); |
2119 | ||
8ceee660 BH |
2120 | /* Wait for any scheduled resets to complete. No more will be |
2121 | * scheduled from this point because efx_stop_all() has been | |
2122 | * called, we are no longer registered with driverlink, and | |
2123 | * the net_device's have been removed. */ | |
1ab00629 | 2124 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2125 | |
2126 | efx_pci_remove_main(efx); | |
2127 | ||
8ceee660 BH |
2128 | efx_fini_io(efx); |
2129 | EFX_LOG(efx, "shutdown successful\n"); | |
2130 | ||
2131 | pci_set_drvdata(pci_dev, NULL); | |
2132 | efx_fini_struct(efx); | |
2133 | free_netdev(efx->net_dev); | |
2134 | }; | |
2135 | ||
2136 | /* Main body of NIC initialisation | |
2137 | * This is called at module load (or hotplug insertion, theoretically). | |
2138 | */ | |
2139 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2140 | { | |
2141 | int rc; | |
2142 | ||
2143 | /* Do start-of-day initialisation */ | |
2144 | rc = efx_probe_all(efx); | |
2145 | if (rc) | |
2146 | goto fail1; | |
2147 | ||
2148 | rc = efx_init_napi(efx); | |
2149 | if (rc) | |
2150 | goto fail2; | |
2151 | ||
ef2b90ee | 2152 | rc = efx->type->init(efx); |
8ceee660 BH |
2153 | if (rc) { |
2154 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
278c0621 | 2155 | goto fail3; |
8ceee660 BH |
2156 | } |
2157 | ||
2158 | rc = efx_init_port(efx); | |
2159 | if (rc) { | |
2160 | EFX_ERR(efx, "failed to initialise port\n"); | |
278c0621 | 2161 | goto fail4; |
8ceee660 BH |
2162 | } |
2163 | ||
bc3c90a2 | 2164 | efx_init_channels(efx); |
8ceee660 | 2165 | |
152b6a62 | 2166 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2167 | if (rc) |
278c0621 | 2168 | goto fail5; |
8ceee660 BH |
2169 | |
2170 | return 0; | |
2171 | ||
278c0621 | 2172 | fail5: |
bc3c90a2 | 2173 | efx_fini_channels(efx); |
8ceee660 | 2174 | efx_fini_port(efx); |
8ceee660 | 2175 | fail4: |
ef2b90ee | 2176 | efx->type->fini(efx); |
8ceee660 BH |
2177 | fail3: |
2178 | efx_fini_napi(efx); | |
2179 | fail2: | |
2180 | efx_remove_all(efx); | |
2181 | fail1: | |
2182 | return rc; | |
2183 | } | |
2184 | ||
2185 | /* NIC initialisation | |
2186 | * | |
2187 | * This is called at module load (or hotplug insertion, | |
2188 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2189 | * sets up and registers the network devices with the kernel and hooks | |
2190 | * the interrupt service routine. It does not prepare the device for | |
2191 | * transmission; this is left to the first time one of the network | |
2192 | * interfaces is brought up (i.e. efx_net_open). | |
2193 | */ | |
2194 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2195 | const struct pci_device_id *entry) | |
2196 | { | |
2197 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2198 | struct net_device *net_dev; | |
2199 | struct efx_nic *efx; | |
2200 | int i, rc; | |
2201 | ||
2202 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
a4900ac9 | 2203 | net_dev = alloc_etherdev_mq(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES); |
8ceee660 BH |
2204 | if (!net_dev) |
2205 | return -ENOMEM; | |
c383b537 | 2206 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 BH |
2207 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2208 | NETIF_F_GRO); | |
738a8f4b BH |
2209 | if (type->offload_features & NETIF_F_V6_CSUM) |
2210 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2211 | /* Mask for features that also apply to VLAN devices */ |
2212 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2213 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2214 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2215 | pci_set_drvdata(pci_dev, efx); |
2216 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2217 | if (rc) | |
2218 | goto fail1; | |
2219 | ||
2220 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2221 | ||
2222 | /* Set up basic I/O (BAR mappings etc) */ | |
2223 | rc = efx_init_io(efx); | |
2224 | if (rc) | |
2225 | goto fail2; | |
2226 | ||
2227 | /* No serialisation is required with the reset path because | |
2228 | * we're in STATE_INIT. */ | |
2229 | for (i = 0; i < 5; i++) { | |
2230 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2231 | |
2232 | /* Serialise against efx_reset(). No more resets will be | |
2233 | * scheduled since efx_stop_all() has been called, and we | |
2234 | * have not and never have been registered with either | |
2235 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2236 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2237 | |
fa402b2e SH |
2238 | if (rc == 0) { |
2239 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2240 | /* If there was a scheduled reset during | |
2241 | * probe, the NIC is probably hosed anyway */ | |
2242 | efx_pci_remove_main(efx); | |
2243 | rc = -EIO; | |
2244 | } else { | |
2245 | break; | |
2246 | } | |
2247 | } | |
2248 | ||
8ceee660 BH |
2249 | /* Retry if a recoverably reset event has been scheduled */ |
2250 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2251 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2252 | goto fail3; | |
2253 | ||
2254 | efx->reset_pending = RESET_TYPE_NONE; | |
2255 | } | |
2256 | ||
2257 | if (rc) { | |
2258 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2259 | goto fail4; | |
2260 | } | |
2261 | ||
55edc6e6 BH |
2262 | /* Switch to the running state before we expose the device to the OS, |
2263 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2264 | efx->state = STATE_RUNNING; |
7dde596e | 2265 | |
8ceee660 BH |
2266 | rc = efx_register_netdev(efx); |
2267 | if (rc) | |
2268 | goto fail5; | |
2269 | ||
2270 | EFX_LOG(efx, "initialisation successful\n"); | |
a5211bb5 BH |
2271 | |
2272 | rtnl_lock(); | |
2273 | efx_mtd_probe(efx); /* allowed to fail */ | |
2274 | rtnl_unlock(); | |
8ceee660 BH |
2275 | return 0; |
2276 | ||
2277 | fail5: | |
2278 | efx_pci_remove_main(efx); | |
2279 | fail4: | |
2280 | fail3: | |
2281 | efx_fini_io(efx); | |
2282 | fail2: | |
2283 | efx_fini_struct(efx); | |
2284 | fail1: | |
5e2a911c | 2285 | WARN_ON(rc > 0); |
8ceee660 BH |
2286 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); |
2287 | free_netdev(net_dev); | |
2288 | return rc; | |
2289 | } | |
2290 | ||
89c758fa BH |
2291 | static int efx_pm_freeze(struct device *dev) |
2292 | { | |
2293 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2294 | ||
2295 | efx->state = STATE_FINI; | |
2296 | ||
2297 | netif_device_detach(efx->net_dev); | |
2298 | ||
2299 | efx_stop_all(efx); | |
2300 | efx_fini_channels(efx); | |
2301 | ||
2302 | return 0; | |
2303 | } | |
2304 | ||
2305 | static int efx_pm_thaw(struct device *dev) | |
2306 | { | |
2307 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2308 | ||
2309 | efx->state = STATE_INIT; | |
2310 | ||
2311 | efx_init_channels(efx); | |
2312 | ||
2313 | mutex_lock(&efx->mac_lock); | |
2314 | efx->phy_op->reconfigure(efx); | |
2315 | mutex_unlock(&efx->mac_lock); | |
2316 | ||
2317 | efx_start_all(efx); | |
2318 | ||
2319 | netif_device_attach(efx->net_dev); | |
2320 | ||
2321 | efx->state = STATE_RUNNING; | |
2322 | ||
2323 | efx->type->resume_wol(efx); | |
2324 | ||
319ba649 SH |
2325 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2326 | queue_work(reset_workqueue, &efx->reset_work); | |
2327 | ||
89c758fa BH |
2328 | return 0; |
2329 | } | |
2330 | ||
2331 | static int efx_pm_poweroff(struct device *dev) | |
2332 | { | |
2333 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2334 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2335 | ||
2336 | efx->type->fini(efx); | |
2337 | ||
2338 | efx->reset_pending = RESET_TYPE_NONE; | |
2339 | ||
2340 | pci_save_state(pci_dev); | |
2341 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2342 | } | |
2343 | ||
2344 | /* Used for both resume and restore */ | |
2345 | static int efx_pm_resume(struct device *dev) | |
2346 | { | |
2347 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2348 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2349 | int rc; | |
2350 | ||
2351 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2352 | if (rc) | |
2353 | return rc; | |
2354 | pci_restore_state(pci_dev); | |
2355 | rc = pci_enable_device(pci_dev); | |
2356 | if (rc) | |
2357 | return rc; | |
2358 | pci_set_master(efx->pci_dev); | |
2359 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2360 | if (rc) | |
2361 | return rc; | |
2362 | rc = efx->type->init(efx); | |
2363 | if (rc) | |
2364 | return rc; | |
2365 | efx_pm_thaw(dev); | |
2366 | return 0; | |
2367 | } | |
2368 | ||
2369 | static int efx_pm_suspend(struct device *dev) | |
2370 | { | |
2371 | int rc; | |
2372 | ||
2373 | efx_pm_freeze(dev); | |
2374 | rc = efx_pm_poweroff(dev); | |
2375 | if (rc) | |
2376 | efx_pm_resume(dev); | |
2377 | return rc; | |
2378 | } | |
2379 | ||
2380 | static struct dev_pm_ops efx_pm_ops = { | |
2381 | .suspend = efx_pm_suspend, | |
2382 | .resume = efx_pm_resume, | |
2383 | .freeze = efx_pm_freeze, | |
2384 | .thaw = efx_pm_thaw, | |
2385 | .poweroff = efx_pm_poweroff, | |
2386 | .restore = efx_pm_resume, | |
2387 | }; | |
2388 | ||
8ceee660 BH |
2389 | static struct pci_driver efx_pci_driver = { |
2390 | .name = EFX_DRIVER_NAME, | |
2391 | .id_table = efx_pci_table, | |
2392 | .probe = efx_pci_probe, | |
2393 | .remove = efx_pci_remove, | |
89c758fa | 2394 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2395 | }; |
2396 | ||
2397 | /************************************************************************** | |
2398 | * | |
2399 | * Kernel module interface | |
2400 | * | |
2401 | *************************************************************************/ | |
2402 | ||
2403 | module_param(interrupt_mode, uint, 0444); | |
2404 | MODULE_PARM_DESC(interrupt_mode, | |
2405 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2406 | ||
2407 | static int __init efx_init_module(void) | |
2408 | { | |
2409 | int rc; | |
2410 | ||
2411 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2412 | ||
2413 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2414 | if (rc) | |
2415 | goto err_notifier; | |
2416 | ||
1ab00629 SH |
2417 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2418 | if (!reset_workqueue) { | |
2419 | rc = -ENOMEM; | |
2420 | goto err_reset; | |
2421 | } | |
8ceee660 BH |
2422 | |
2423 | rc = pci_register_driver(&efx_pci_driver); | |
2424 | if (rc < 0) | |
2425 | goto err_pci; | |
2426 | ||
2427 | return 0; | |
2428 | ||
2429 | err_pci: | |
1ab00629 SH |
2430 | destroy_workqueue(reset_workqueue); |
2431 | err_reset: | |
8ceee660 BH |
2432 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2433 | err_notifier: | |
2434 | return rc; | |
2435 | } | |
2436 | ||
2437 | static void __exit efx_exit_module(void) | |
2438 | { | |
2439 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2440 | ||
2441 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2442 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2443 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2444 | ||
2445 | } | |
2446 | ||
2447 | module_init(efx_init_module); | |
2448 | module_exit(efx_exit_module); | |
2449 | ||
906bb26c BH |
2450 | MODULE_AUTHOR("Solarflare Communications and " |
2451 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2452 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2453 | MODULE_LICENSE("GPL"); | |
2454 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |