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Merge tag 'linux-kselftest-4.13-rc6-fixes' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-artful-kernel.git] / drivers / net / usb / smsc75xx.c
CommitLineData
d0cad871
SG
1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2010 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
9cb00073 16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
d0cad871
SG
17 *
18 *****************************************************************************/
19
20#include <linux/module.h>
21#include <linux/kmod.h>
d0cad871
SG
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/usb.h>
899a391b
SG
27#include <linux/bitrev.h>
28#include <linux/crc16.h>
d0cad871
SG
29#include <linux/crc32.h>
30#include <linux/usb/usbnet.h>
5a0e3ad6 31#include <linux/slab.h>
c489565b 32#include <linux/of_net.h>
d0cad871
SG
33#include "smsc75xx.h"
34
35#define SMSC_CHIPNAME "smsc75xx"
36#define SMSC_DRIVER_VERSION "1.0.0"
37#define HS_USB_PKT_SIZE (512)
38#define FS_USB_PKT_SIZE (64)
39#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
40#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
41#define DEFAULT_BULK_IN_DELAY (0x00002000)
42#define MAX_SINGLE_PACKET_SIZE (9000)
43#define LAN75XX_EEPROM_MAGIC (0x7500)
44#define EEPROM_MAC_OFFSET (0x01)
45#define DEFAULT_TX_CSUM_ENABLE (true)
46#define DEFAULT_RX_CSUM_ENABLE (true)
d0cad871
SG
47#define SMSC75XX_INTERNAL_PHY_ID (1)
48#define SMSC75XX_TX_OVERHEAD (8)
49#define MAX_RX_FIFO_SIZE (20 * 1024)
50#define MAX_TX_FIFO_SIZE (12 * 1024)
51#define USB_VENDOR_ID_SMSC (0x0424)
52#define USB_PRODUCT_ID_LAN7500 (0x7500)
53#define USB_PRODUCT_ID_LAN7505 (0x7505)
ea1649de 54#define RXW_PADDING 2
f329ccdc 55#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
899a391b 56 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
d0cad871 57
b4cdea9c
SG
58#define SUSPEND_SUSPEND0 (0x01)
59#define SUSPEND_SUSPEND1 (0x02)
60#define SUSPEND_SUSPEND2 (0x04)
61#define SUSPEND_SUSPEND3 (0x08)
b4cdea9c
SG
62#define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
63 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
64
d0cad871
SG
65struct smsc75xx_priv {
66 struct usbnet *dev;
67 u32 rfe_ctl;
6c636503 68 u32 wolopts;
d0cad871 69 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
d0cad871
SG
70 struct mutex dataport_mutex;
71 spinlock_t rfe_ctl_lock;
72 struct work_struct set_multicast;
b4cdea9c 73 u8 suspend_flags;
d0cad871
SG
74};
75
76struct usb_context {
77 struct usb_ctrlrequest req;
78 struct usbnet *dev;
79};
80
eb939922 81static bool turbo_mode = true;
d0cad871
SG
82module_param(turbo_mode, bool, 0644);
83MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
84
47bbea41
ML
85static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
86 u32 *data, int in_pm)
d0cad871 87{
2b2e41e3 88 u32 buf;
d0cad871 89 int ret;
47bbea41 90 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
d0cad871
SG
91
92 BUG_ON(!dev);
93
47bbea41
ML
94 if (!in_pm)
95 fn = usbnet_read_cmd;
96 else
97 fn = usbnet_read_cmd_nopm;
98
99 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
100 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
101 0, index, &buf, 4);
58ef6a3f 102 if (unlikely(ret < 0)) {
1e1d7412
JP
103 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
104 index, ret);
58ef6a3f
DC
105 return ret;
106 }
d0cad871 107
2b2e41e3
ML
108 le32_to_cpus(&buf);
109 *data = buf;
d0cad871
SG
110
111 return ret;
112}
113
47bbea41
ML
114static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
115 u32 data, int in_pm)
d0cad871 116{
2b2e41e3 117 u32 buf;
d0cad871 118 int ret;
47bbea41 119 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
d0cad871
SG
120
121 BUG_ON(!dev);
122
47bbea41
ML
123 if (!in_pm)
124 fn = usbnet_write_cmd;
125 else
126 fn = usbnet_write_cmd_nopm;
127
2b2e41e3
ML
128 buf = data;
129 cpu_to_le32s(&buf);
d0cad871 130
47bbea41
ML
131 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
132 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
133 0, index, &buf, 4);
d0cad871 134 if (unlikely(ret < 0))
1e1d7412
JP
135 netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
136 index, ret);
d0cad871 137
d0cad871
SG
138 return ret;
139}
140
47bbea41
ML
141static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
142 u32 *data)
143{
144 return __smsc75xx_read_reg(dev, index, data, 1);
145}
146
147static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
148 u32 data)
149{
150 return __smsc75xx_write_reg(dev, index, data, 1);
151}
152
153static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
154 u32 *data)
155{
156 return __smsc75xx_read_reg(dev, index, data, 0);
157}
158
159static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
160 u32 data)
161{
162 return __smsc75xx_write_reg(dev, index, data, 0);
163}
164
d0cad871
SG
165/* Loop until the read is completed with timeout
166 * called with phy_mutex held */
f329ccdc
SG
167static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
168 int in_pm)
d0cad871
SG
169{
170 unsigned long start_time = jiffies;
171 u32 val;
172 int ret;
173
174 do {
f329ccdc 175 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
e3c678e6
SG
176 if (ret < 0) {
177 netdev_warn(dev->net, "Error reading MII_ACCESS\n");
178 return ret;
179 }
d0cad871
SG
180
181 if (!(val & MII_ACCESS_BUSY))
182 return 0;
183 } while (!time_after(jiffies, start_time + HZ));
184
185 return -EIO;
186}
187
f329ccdc
SG
188static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
189 int in_pm)
d0cad871
SG
190{
191 struct usbnet *dev = netdev_priv(netdev);
192 u32 val, addr;
193 int ret;
194
195 mutex_lock(&dev->phy_mutex);
196
197 /* confirm MII not busy */
f329ccdc 198 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
199 if (ret < 0) {
200 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
201 goto done;
202 }
d0cad871
SG
203
204 /* set the address, index & direction (read from PHY) */
205 phy_id &= dev->mii.phy_id_mask;
206 idx &= dev->mii.reg_num_mask;
207 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
208 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 209 | MII_ACCESS_READ | MII_ACCESS_BUSY;
f329ccdc 210 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
211 if (ret < 0) {
212 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
213 goto done;
214 }
d0cad871 215
f329ccdc 216 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
217 if (ret < 0) {
218 netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
219 goto done;
220 }
d0cad871 221
f329ccdc 222 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
e3c678e6
SG
223 if (ret < 0) {
224 netdev_warn(dev->net, "Error reading MII_DATA\n");
225 goto done;
226 }
d0cad871
SG
227
228 ret = (u16)(val & 0xFFFF);
229
230done:
231 mutex_unlock(&dev->phy_mutex);
232 return ret;
233}
234
f329ccdc
SG
235static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
236 int idx, int regval, int in_pm)
d0cad871
SG
237{
238 struct usbnet *dev = netdev_priv(netdev);
239 u32 val, addr;
240 int ret;
241
242 mutex_lock(&dev->phy_mutex);
243
244 /* confirm MII not busy */
f329ccdc 245 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
246 if (ret < 0) {
247 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
248 goto done;
249 }
d0cad871
SG
250
251 val = regval;
f329ccdc 252 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
e3c678e6
SG
253 if (ret < 0) {
254 netdev_warn(dev->net, "Error writing MII_DATA\n");
255 goto done;
256 }
d0cad871
SG
257
258 /* set the address, index & direction (write to PHY) */
259 phy_id &= dev->mii.phy_id_mask;
260 idx &= dev->mii.reg_num_mask;
261 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
262 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 263 | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
f329ccdc 264 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
265 if (ret < 0) {
266 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
267 goto done;
268 }
d0cad871 269
f329ccdc 270 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
271 if (ret < 0) {
272 netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
273 goto done;
274 }
d0cad871
SG
275
276done:
277 mutex_unlock(&dev->phy_mutex);
278}
279
f329ccdc
SG
280static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
281 int idx)
282{
283 return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
284}
285
286static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
287 int idx, int regval)
288{
289 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
290}
291
292static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
293{
294 return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
295}
296
297static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
298 int regval)
299{
300 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
301}
302
d0cad871
SG
303static int smsc75xx_wait_eeprom(struct usbnet *dev)
304{
305 unsigned long start_time = jiffies;
306 u32 val;
307 int ret;
308
309 do {
310 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
311 if (ret < 0) {
312 netdev_warn(dev->net, "Error reading E2P_CMD\n");
313 return ret;
314 }
d0cad871
SG
315
316 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
317 break;
318 udelay(40);
319 } while (!time_after(jiffies, start_time + HZ));
320
321 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
1e1d7412 322 netdev_warn(dev->net, "EEPROM read operation timeout\n");
d0cad871
SG
323 return -EIO;
324 }
325
326 return 0;
327}
328
329static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
330{
331 unsigned long start_time = jiffies;
332 u32 val;
333 int ret;
334
335 do {
336 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
337 if (ret < 0) {
338 netdev_warn(dev->net, "Error reading E2P_CMD\n");
339 return ret;
340 }
d0cad871
SG
341
342 if (!(val & E2P_CMD_BUSY))
343 return 0;
344
345 udelay(40);
346 } while (!time_after(jiffies, start_time + HZ));
347
1e1d7412 348 netdev_warn(dev->net, "EEPROM is busy\n");
d0cad871
SG
349 return -EIO;
350}
351
352static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
353 u8 *data)
354{
355 u32 val;
356 int i, ret;
357
358 BUG_ON(!dev);
359 BUG_ON(!data);
360
361 ret = smsc75xx_eeprom_confirm_not_busy(dev);
362 if (ret)
363 return ret;
364
365 for (i = 0; i < length; i++) {
366 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
367 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
368 if (ret < 0) {
369 netdev_warn(dev->net, "Error writing E2P_CMD\n");
370 return ret;
371 }
d0cad871
SG
372
373 ret = smsc75xx_wait_eeprom(dev);
374 if (ret < 0)
375 return ret;
376
377 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
e3c678e6
SG
378 if (ret < 0) {
379 netdev_warn(dev->net, "Error reading E2P_DATA\n");
380 return ret;
381 }
d0cad871
SG
382
383 data[i] = val & 0xFF;
384 offset++;
385 }
386
387 return 0;
388}
389
390static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
391 u8 *data)
392{
393 u32 val;
394 int i, ret;
395
396 BUG_ON(!dev);
397 BUG_ON(!data);
398
399 ret = smsc75xx_eeprom_confirm_not_busy(dev);
400 if (ret)
401 return ret;
402
403 /* Issue write/erase enable command */
404 val = E2P_CMD_BUSY | E2P_CMD_EWEN;
405 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
406 if (ret < 0) {
407 netdev_warn(dev->net, "Error writing E2P_CMD\n");
408 return ret;
409 }
d0cad871
SG
410
411 ret = smsc75xx_wait_eeprom(dev);
412 if (ret < 0)
413 return ret;
414
415 for (i = 0; i < length; i++) {
416
417 /* Fill data register */
418 val = data[i];
419 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
e3c678e6
SG
420 if (ret < 0) {
421 netdev_warn(dev->net, "Error writing E2P_DATA\n");
422 return ret;
423 }
d0cad871
SG
424
425 /* Send "write" command */
426 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
427 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
428 if (ret < 0) {
429 netdev_warn(dev->net, "Error writing E2P_CMD\n");
430 return ret;
431 }
d0cad871
SG
432
433 ret = smsc75xx_wait_eeprom(dev);
434 if (ret < 0)
435 return ret;
436
437 offset++;
438 }
439
440 return 0;
441}
442
443static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
444{
445 int i, ret;
446
447 for (i = 0; i < 100; i++) {
448 u32 dp_sel;
449 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
450 if (ret < 0) {
451 netdev_warn(dev->net, "Error reading DP_SEL\n");
452 return ret;
453 }
d0cad871
SG
454
455 if (dp_sel & DP_SEL_DPRDY)
456 return 0;
457
458 udelay(40);
459 }
460
1e1d7412 461 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
d0cad871
SG
462
463 return -EIO;
464}
465
466static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
467 u32 length, u32 *buf)
468{
469 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
470 u32 dp_sel;
471 int i, ret;
472
473 mutex_lock(&pdata->dataport_mutex);
474
475 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
476 if (ret < 0) {
477 netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
478 goto done;
479 }
d0cad871
SG
480
481 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
482 if (ret < 0) {
483 netdev_warn(dev->net, "Error reading DP_SEL\n");
484 goto done;
485 }
d0cad871
SG
486
487 dp_sel &= ~DP_SEL_RSEL;
488 dp_sel |= ram_select;
489 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
e3c678e6
SG
490 if (ret < 0) {
491 netdev_warn(dev->net, "Error writing DP_SEL\n");
492 goto done;
493 }
d0cad871
SG
494
495 for (i = 0; i < length; i++) {
496 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
e3c678e6
SG
497 if (ret < 0) {
498 netdev_warn(dev->net, "Error writing DP_ADDR\n");
499 goto done;
500 }
d0cad871
SG
501
502 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
e3c678e6
SG
503 if (ret < 0) {
504 netdev_warn(dev->net, "Error writing DP_DATA\n");
505 goto done;
506 }
d0cad871
SG
507
508 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
e3c678e6
SG
509 if (ret < 0) {
510 netdev_warn(dev->net, "Error writing DP_CMD\n");
511 goto done;
512 }
d0cad871
SG
513
514 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
515 if (ret < 0) {
516 netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
517 goto done;
518 }
d0cad871
SG
519 }
520
521done:
522 mutex_unlock(&pdata->dataport_mutex);
523 return ret;
524}
525
526/* returns hash bit number for given MAC address */
527static u32 smsc75xx_hash(char addr[ETH_ALEN])
528{
529 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
530}
531
532static void smsc75xx_deferred_multicast_write(struct work_struct *param)
533{
534 struct smsc75xx_priv *pdata =
535 container_of(param, struct smsc75xx_priv, set_multicast);
536 struct usbnet *dev = pdata->dev;
537 int ret;
538
1e1d7412
JP
539 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
540 pdata->rfe_ctl);
d0cad871
SG
541
542 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
543 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
544
545 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
546 if (ret < 0)
547 netdev_warn(dev->net, "Error writing RFE_CRL\n");
d0cad871
SG
548}
549
550static void smsc75xx_set_multicast(struct net_device *netdev)
551{
552 struct usbnet *dev = netdev_priv(netdev);
553 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
554 unsigned long flags;
555 int i;
556
557 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
558
559 pdata->rfe_ctl &=
560 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
561 pdata->rfe_ctl |= RFE_CTL_AB;
562
563 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
564 pdata->multicast_hash_table[i] = 0;
565
566 if (dev->net->flags & IFF_PROMISC) {
1e1d7412 567 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
d0cad871
SG
568 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
569 } else if (dev->net->flags & IFF_ALLMULTI) {
1e1d7412 570 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
d0cad871
SG
571 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
572 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 573 struct netdev_hw_addr *ha;
d0cad871 574
1e1d7412 575 netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
d0cad871
SG
576
577 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
578
22bedad3
JP
579 netdev_for_each_mc_addr(ha, netdev) {
580 u32 bitnum = smsc75xx_hash(ha->addr);
d0cad871
SG
581 pdata->multicast_hash_table[bitnum / 32] |=
582 (1 << (bitnum % 32));
583 }
584 } else {
1e1d7412 585 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
d0cad871
SG
586 pdata->rfe_ctl |= RFE_CTL_DPF;
587 }
588
589 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
590
591 /* defer register writes to a sleepable context */
592 schedule_work(&pdata->set_multicast);
593}
594
595static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
596 u16 lcladv, u16 rmtadv)
597{
598 u32 flow = 0, fct_flow = 0;
599 int ret;
600
601 if (duplex == DUPLEX_FULL) {
602 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
603
604 if (cap & FLOW_CTRL_TX) {
605 flow = (FLOW_TX_FCEN | 0xFFFF);
606 /* set fct_flow thresholds to 20% and 80% */
607 fct_flow = (8 << 8) | 32;
608 }
609
610 if (cap & FLOW_CTRL_RX)
611 flow |= FLOW_RX_FCEN;
612
1e1d7412
JP
613 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
614 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
615 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
d0cad871 616 } else {
1e1d7412 617 netif_dbg(dev, link, dev->net, "half duplex\n");
d0cad871
SG
618 }
619
620 ret = smsc75xx_write_reg(dev, FLOW, flow);
e3c678e6
SG
621 if (ret < 0) {
622 netdev_warn(dev->net, "Error writing FLOW\n");
623 return ret;
624 }
d0cad871
SG
625
626 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
e3c678e6
SG
627 if (ret < 0) {
628 netdev_warn(dev->net, "Error writing FCT_FLOW\n");
629 return ret;
630 }
d0cad871
SG
631
632 return 0;
633}
634
635static int smsc75xx_link_reset(struct usbnet *dev)
636{
637 struct mii_if_info *mii = &dev->mii;
8ae6daca 638 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
d0cad871
SG
639 u16 lcladv, rmtadv;
640 int ret;
641
4f94a929 642 /* write to clear phy interrupt status */
7749622d
SG
643 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
644 PHY_INT_SRC_CLEAR_ALL);
d0cad871
SG
645
646 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
647 if (ret < 0) {
648 netdev_warn(dev->net, "Error writing INT_STS\n");
649 return ret;
650 }
d0cad871
SG
651
652 mii_check_media(mii, 1, 1);
653 mii_ethtool_gset(&dev->mii, &ecmd);
654 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
655 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
656
1e1d7412
JP
657 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
658 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
d0cad871
SG
659
660 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
661}
662
663static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
664{
665 u32 intdata;
666
667 if (urb->actual_length != 4) {
1e1d7412
JP
668 netdev_warn(dev->net, "unexpected urb length %d\n",
669 urb->actual_length);
d0cad871
SG
670 return;
671 }
672
673 memcpy(&intdata, urb->transfer_buffer, 4);
674 le32_to_cpus(&intdata);
675
1e1d7412 676 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
d0cad871
SG
677
678 if (intdata & INT_ENP_PHY_INT)
679 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
680 else
1e1d7412
JP
681 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
682 intdata);
d0cad871
SG
683}
684
d0cad871
SG
685static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
686{
687 return MAX_EEPROM_SIZE;
688}
689
690static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
691 struct ethtool_eeprom *ee, u8 *data)
692{
693 struct usbnet *dev = netdev_priv(netdev);
694
695 ee->magic = LAN75XX_EEPROM_MAGIC;
696
697 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
698}
699
700static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
701 struct ethtool_eeprom *ee, u8 *data)
702{
703 struct usbnet *dev = netdev_priv(netdev);
704
705 if (ee->magic != LAN75XX_EEPROM_MAGIC) {
1e1d7412
JP
706 netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
707 ee->magic);
d0cad871
SG
708 return -EINVAL;
709 }
710
711 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
712}
713
6c636503
SG
714static void smsc75xx_ethtool_get_wol(struct net_device *net,
715 struct ethtool_wolinfo *wolinfo)
716{
717 struct usbnet *dev = netdev_priv(net);
718 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
719
720 wolinfo->supported = SUPPORTED_WAKE;
721 wolinfo->wolopts = pdata->wolopts;
722}
723
724static int smsc75xx_ethtool_set_wol(struct net_device *net,
725 struct ethtool_wolinfo *wolinfo)
726{
727 struct usbnet *dev = netdev_priv(net);
728 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
351f33d9 729 int ret;
6c636503
SG
730
731 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
351f33d9
SG
732
733 ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
e3c678e6
SG
734 if (ret < 0)
735 netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
351f33d9 736
e3c678e6 737 return ret;
6c636503
SG
738}
739
d0cad871
SG
740static const struct ethtool_ops smsc75xx_ethtool_ops = {
741 .get_link = usbnet_get_link,
742 .nway_reset = usbnet_nway_reset,
743 .get_drvinfo = usbnet_get_drvinfo,
744 .get_msglevel = usbnet_get_msglevel,
745 .set_msglevel = usbnet_set_msglevel,
d0cad871
SG
746 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
747 .get_eeprom = smsc75xx_ethtool_get_eeprom,
748 .set_eeprom = smsc75xx_ethtool_set_eeprom,
6c636503
SG
749 .get_wol = smsc75xx_ethtool_get_wol,
750 .set_wol = smsc75xx_ethtool_set_wol,
a44017a5
PR
751 .get_link_ksettings = usbnet_get_link_ksettings,
752 .set_link_ksettings = usbnet_set_link_ksettings,
d0cad871
SG
753};
754
755static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
756{
757 struct usbnet *dev = netdev_priv(netdev);
758
759 if (!netif_running(netdev))
760 return -EINVAL;
761
762 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
763}
764
765static void smsc75xx_init_mac_address(struct usbnet *dev)
766{
c489565b
AB
767 const u8 *mac_addr;
768
769 /* maybe the boot loader passed the MAC address in devicetree */
770 mac_addr = of_get_mac_address(dev->udev->dev.of_node);
771 if (mac_addr) {
772 memcpy(dev->net->dev_addr, mac_addr, ETH_ALEN);
773 return;
774 }
775
d0cad871
SG
776 /* try reading mac address from EEPROM */
777 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
778 dev->net->dev_addr) == 0) {
779 if (is_valid_ether_addr(dev->net->dev_addr)) {
780 /* eeprom values are valid so use them */
781 netif_dbg(dev, ifup, dev->net,
1e1d7412 782 "MAC address read from EEPROM\n");
d0cad871
SG
783 return;
784 }
785 }
786
c489565b 787 /* no useful static MAC address found. generate a random one */
f2cedb63 788 eth_hw_addr_random(dev->net);
1e1d7412 789 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
d0cad871
SG
790}
791
792static int smsc75xx_set_mac_address(struct usbnet *dev)
793{
794 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
795 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
796 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
797
798 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
e3c678e6
SG
799 if (ret < 0) {
800 netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
801 return ret;
802 }
d0cad871
SG
803
804 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
e3c678e6
SG
805 if (ret < 0) {
806 netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
807 return ret;
808 }
d0cad871
SG
809
810 addr_hi |= ADDR_FILTX_FB_VALID;
811 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
e3c678e6
SG
812 if (ret < 0) {
813 netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
814 return ret;
815 }
d0cad871
SG
816
817 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
e3c678e6
SG
818 if (ret < 0)
819 netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
d0cad871 820
e3c678e6 821 return ret;
d0cad871
SG
822}
823
824static int smsc75xx_phy_initialize(struct usbnet *dev)
825{
b140504a 826 int bmcr, ret, timeout = 0;
d0cad871
SG
827
828 /* Initialize MII structure */
829 dev->mii.dev = dev->net;
830 dev->mii.mdio_read = smsc75xx_mdio_read;
831 dev->mii.mdio_write = smsc75xx_mdio_write;
832 dev->mii.phy_id_mask = 0x1f;
833 dev->mii.reg_num_mask = 0x1f;
c0b92e4d 834 dev->mii.supports_gmii = 1;
d0cad871
SG
835 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
836
837 /* reset phy and wait for reset to complete */
838 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
839
840 do {
841 msleep(10);
842 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
e3c678e6
SG
843 if (bmcr < 0) {
844 netdev_warn(dev->net, "Error reading MII_BMCR\n");
845 return bmcr;
846 }
d0cad871 847 timeout++;
8a1d59d7 848 } while ((bmcr & BMCR_RESET) && (timeout < 100));
d0cad871
SG
849
850 if (timeout >= 100) {
1e1d7412 851 netdev_warn(dev->net, "timeout on PHY Reset\n");
d0cad871
SG
852 return -EIO;
853 }
854
855 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
856 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
857 ADVERTISE_PAUSE_ASYM);
c0b92e4d
SG
858 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
859 ADVERTISE_1000FULL);
d0cad871 860
b140504a
SG
861 /* read and write to clear phy interrupt status */
862 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
e3c678e6
SG
863 if (ret < 0) {
864 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
865 return ret;
866 }
867
b140504a 868 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
d0cad871
SG
869
870 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
871 PHY_INT_MASK_DEFAULT);
872 mii_nway_restart(&dev->mii);
873
1e1d7412 874 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
d0cad871
SG
875 return 0;
876}
877
878static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
879{
880 int ret = 0;
881 u32 buf;
882 bool rxenabled;
883
884 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
885 if (ret < 0) {
886 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
887 return ret;
888 }
d0cad871
SG
889
890 rxenabled = ((buf & MAC_RX_RXEN) != 0);
891
892 if (rxenabled) {
893 buf &= ~MAC_RX_RXEN;
894 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
895 if (ret < 0) {
896 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
897 return ret;
898 }
d0cad871
SG
899 }
900
901 /* add 4 to size for FCS */
902 buf &= ~MAC_RX_MAX_SIZE;
903 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
904
905 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
906 if (ret < 0) {
907 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
908 return ret;
909 }
d0cad871
SG
910
911 if (rxenabled) {
912 buf |= MAC_RX_RXEN;
913 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
914 if (ret < 0) {
915 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
916 return ret;
917 }
d0cad871
SG
918 }
919
920 return 0;
921}
922
923static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
924{
925 struct usbnet *dev = netdev_priv(netdev);
4c51e536
SG
926 int ret;
927
4c51e536 928 ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
e3c678e6
SG
929 if (ret < 0) {
930 netdev_warn(dev->net, "Failed to set mac rx frame length\n");
931 return ret;
932 }
d0cad871
SG
933
934 return usbnet_change_mtu(netdev, new_mtu);
935}
936
78e47fe4 937/* Enable or disable Rx checksum offload engine */
c8f44aff
MM
938static int smsc75xx_set_features(struct net_device *netdev,
939 netdev_features_t features)
78e47fe4
MM
940{
941 struct usbnet *dev = netdev_priv(netdev);
942 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
943 unsigned long flags;
944 int ret;
945
946 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
947
948 if (features & NETIF_F_RXCSUM)
949 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
950 else
951 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
952
953 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
954 /* it's racing here! */
955
956 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
957 if (ret < 0)
958 netdev_warn(dev->net, "Error writing RFE_CTL\n");
78e47fe4 959
e3c678e6 960 return ret;
78e47fe4
MM
961}
962
47bbea41 963static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
8762cec8
SG
964{
965 int timeout = 0;
966
967 do {
968 u32 buf;
47bbea41
ML
969 int ret;
970
971 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
972
e3c678e6
SG
973 if (ret < 0) {
974 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
975 return ret;
976 }
8762cec8
SG
977
978 if (buf & PMT_CTL_DEV_RDY)
979 return 0;
980
981 msleep(10);
982 timeout++;
983 } while (timeout < 100);
984
1e1d7412 985 netdev_warn(dev->net, "timeout waiting for device ready\n");
8762cec8
SG
986 return -EIO;
987}
988
d0cad871
SG
989static int smsc75xx_reset(struct usbnet *dev)
990{
991 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
992 u32 buf;
993 int ret = 0, timeout;
994
1e1d7412 995 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
d0cad871 996
47bbea41 997 ret = smsc75xx_wait_ready(dev, 0);
e3c678e6
SG
998 if (ret < 0) {
999 netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
1000 return ret;
1001 }
8762cec8 1002
d0cad871 1003 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1004 if (ret < 0) {
1005 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1006 return ret;
1007 }
d0cad871
SG
1008
1009 buf |= HW_CFG_LRST;
1010
1011 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1012 if (ret < 0) {
1013 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1014 return ret;
1015 }
d0cad871
SG
1016
1017 timeout = 0;
1018 do {
1019 msleep(10);
1020 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1021 if (ret < 0) {
1022 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1023 return ret;
1024 }
d0cad871
SG
1025 timeout++;
1026 } while ((buf & HW_CFG_LRST) && (timeout < 100));
1027
1028 if (timeout >= 100) {
1e1d7412 1029 netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
d0cad871
SG
1030 return -EIO;
1031 }
1032
1e1d7412 1033 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
d0cad871
SG
1034
1035 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1036 if (ret < 0) {
1037 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1038 return ret;
1039 }
d0cad871
SG
1040
1041 buf |= PMT_CTL_PHY_RST;
1042
1043 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
e3c678e6
SG
1044 if (ret < 0) {
1045 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1046 return ret;
1047 }
d0cad871
SG
1048
1049 timeout = 0;
1050 do {
1051 msleep(10);
1052 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1053 if (ret < 0) {
1054 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1055 return ret;
1056 }
d0cad871
SG
1057 timeout++;
1058 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
1059
1060 if (timeout >= 100) {
1e1d7412 1061 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
d0cad871
SG
1062 return -EIO;
1063 }
1064
1e1d7412 1065 netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
d0cad871 1066
d0cad871 1067 ret = smsc75xx_set_mac_address(dev);
e3c678e6
SG
1068 if (ret < 0) {
1069 netdev_warn(dev->net, "Failed to set mac address\n");
1070 return ret;
1071 }
d0cad871 1072
1e1d7412
JP
1073 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
1074 dev->net->dev_addr);
d0cad871
SG
1075
1076 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1077 if (ret < 0) {
1078 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1079 return ret;
1080 }
d0cad871 1081
1e1d7412
JP
1082 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
1083 buf);
d0cad871
SG
1084
1085 buf |= HW_CFG_BIR;
1086
1087 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1088 if (ret < 0) {
1089 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1090 return ret;
1091 }
d0cad871
SG
1092
1093 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1094 if (ret < 0) {
1095 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1096 return ret;
1097 }
d0cad871 1098
1e1d7412
JP
1099 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
1100 buf);
d0cad871
SG
1101
1102 if (!turbo_mode) {
1103 buf = 0;
1104 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
1105 } else if (dev->udev->speed == USB_SPEED_HIGH) {
1106 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
1107 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
1108 } else {
1109 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
1110 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
1111 }
1112
1e1d7412
JP
1113 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
1114 (ulong)dev->rx_urb_size);
d0cad871
SG
1115
1116 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
e3c678e6
SG
1117 if (ret < 0) {
1118 netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
1119 return ret;
1120 }
d0cad871
SG
1121
1122 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
e3c678e6
SG
1123 if (ret < 0) {
1124 netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
1125 return ret;
1126 }
d0cad871
SG
1127
1128 netif_dbg(dev, ifup, dev->net,
1e1d7412 1129 "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
d0cad871
SG
1130
1131 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
e3c678e6
SG
1132 if (ret < 0) {
1133 netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
1134 return ret;
1135 }
d0cad871
SG
1136
1137 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
e3c678e6
SG
1138 if (ret < 0) {
1139 netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
1140 return ret;
1141 }
d0cad871
SG
1142
1143 netif_dbg(dev, ifup, dev->net,
1e1d7412 1144 "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
d0cad871
SG
1145
1146 if (turbo_mode) {
1147 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1148 if (ret < 0) {
1149 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1150 return ret;
1151 }
d0cad871 1152
1e1d7412 1153 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1154
1155 buf |= (HW_CFG_MEF | HW_CFG_BCE);
1156
1157 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1158 if (ret < 0) {
1159 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1160 return ret;
1161 }
d0cad871
SG
1162
1163 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1164 if (ret < 0) {
1165 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1166 return ret;
1167 }
d0cad871 1168
1e1d7412 1169 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1170 }
1171
1172 /* set FIFO sizes */
1173 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
1174 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
e3c678e6
SG
1175 if (ret < 0) {
1176 netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
1177 return ret;
1178 }
d0cad871 1179
1e1d7412 1180 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1181
1182 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
1183 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
e3c678e6
SG
1184 if (ret < 0) {
1185 netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
1186 return ret;
1187 }
d0cad871 1188
1e1d7412 1189 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1190
1191 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
1192 if (ret < 0) {
1193 netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
1194 return ret;
1195 }
d0cad871
SG
1196
1197 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
e3c678e6
SG
1198 if (ret < 0) {
1199 netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
1200 return ret;
1201 }
d0cad871 1202
1e1d7412 1203 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
d0cad871 1204
97138a1c 1205 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
e3c678e6
SG
1206 if (ret < 0) {
1207 netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
1208 return ret;
1209 }
d0cad871 1210
97138a1c
SG
1211 /* only set default GPIO/LED settings if no EEPROM is detected */
1212 if (!(buf & E2P_CMD_LOADED)) {
1213 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
e3c678e6
SG
1214 if (ret < 0) {
1215 netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
1216 return ret;
1217 }
d0cad871 1218
97138a1c
SG
1219 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
1220 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
1221
1222 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
e3c678e6
SG
1223 if (ret < 0) {
1224 netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
1225 return ret;
1226 }
97138a1c 1227 }
d0cad871
SG
1228
1229 ret = smsc75xx_write_reg(dev, FLOW, 0);
e3c678e6
SG
1230 if (ret < 0) {
1231 netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
1232 return ret;
1233 }
d0cad871
SG
1234
1235 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
e3c678e6
SG
1236 if (ret < 0) {
1237 netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
1238 return ret;
1239 }
d0cad871
SG
1240
1241 /* Don't need rfe_ctl_lock during initialisation */
1242 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1243 if (ret < 0) {
1244 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1245 return ret;
1246 }
d0cad871
SG
1247
1248 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
1249
1250 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
1251 if (ret < 0) {
1252 netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
1253 return ret;
1254 }
d0cad871
SG
1255
1256 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1257 if (ret < 0) {
1258 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1259 return ret;
1260 }
d0cad871 1261
1e1d7412
JP
1262 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
1263 pdata->rfe_ctl);
d0cad871
SG
1264
1265 /* Enable or disable checksum offload engines */
78e47fe4 1266 smsc75xx_set_features(dev->net, dev->net->features);
d0cad871
SG
1267
1268 smsc75xx_set_multicast(dev->net);
1269
1270 ret = smsc75xx_phy_initialize(dev);
e3c678e6
SG
1271 if (ret < 0) {
1272 netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
1273 return ret;
1274 }
d0cad871
SG
1275
1276 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
e3c678e6
SG
1277 if (ret < 0) {
1278 netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
1279 return ret;
1280 }
d0cad871
SG
1281
1282 /* enable PHY interrupts */
1283 buf |= INT_ENP_PHY_INT;
1284
1285 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
e3c678e6
SG
1286 if (ret < 0) {
1287 netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
1288 return ret;
1289 }
d0cad871 1290
2f3a081e
SG
1291 /* allow mac to detect speed and duplex from phy */
1292 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
e3c678e6
SG
1293 if (ret < 0) {
1294 netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
1295 return ret;
1296 }
2f3a081e
SG
1297
1298 buf |= (MAC_CR_ADD | MAC_CR_ASD);
1299 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
e3c678e6
SG
1300 if (ret < 0) {
1301 netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
1302 return ret;
1303 }
2f3a081e 1304
d0cad871 1305 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
e3c678e6
SG
1306 if (ret < 0) {
1307 netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
1308 return ret;
1309 }
d0cad871
SG
1310
1311 buf |= MAC_TX_TXEN;
1312
1313 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
e3c678e6
SG
1314 if (ret < 0) {
1315 netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
1316 return ret;
1317 }
d0cad871 1318
1e1d7412 1319 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
d0cad871
SG
1320
1321 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
e3c678e6
SG
1322 if (ret < 0) {
1323 netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
1324 return ret;
1325 }
d0cad871
SG
1326
1327 buf |= FCT_TX_CTL_EN;
1328
1329 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
e3c678e6
SG
1330 if (ret < 0) {
1331 netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
1332 return ret;
1333 }
d0cad871 1334
1e1d7412 1335 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
d0cad871 1336
4c51e536 1337 ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
e3c678e6
SG
1338 if (ret < 0) {
1339 netdev_warn(dev->net, "Failed to set max rx frame length\n");
1340 return ret;
1341 }
d0cad871
SG
1342
1343 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
1344 if (ret < 0) {
1345 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
1346 return ret;
1347 }
d0cad871
SG
1348
1349 buf |= MAC_RX_RXEN;
1350
1351 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
1352 if (ret < 0) {
1353 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
1354 return ret;
1355 }
d0cad871 1356
1e1d7412 1357 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
d0cad871
SG
1358
1359 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
e3c678e6
SG
1360 if (ret < 0) {
1361 netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
1362 return ret;
1363 }
d0cad871
SG
1364
1365 buf |= FCT_RX_CTL_EN;
1366
1367 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
e3c678e6
SG
1368 if (ret < 0) {
1369 netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
1370 return ret;
1371 }
d0cad871 1372
1e1d7412 1373 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
d0cad871 1374
1e1d7412 1375 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
d0cad871
SG
1376 return 0;
1377}
1378
1379static const struct net_device_ops smsc75xx_netdev_ops = {
1380 .ndo_open = usbnet_open,
1381 .ndo_stop = usbnet_stop,
1382 .ndo_start_xmit = usbnet_start_xmit,
1383 .ndo_tx_timeout = usbnet_tx_timeout,
c8b5d129 1384 .ndo_get_stats64 = usbnet_get_stats64,
d0cad871
SG
1385 .ndo_change_mtu = smsc75xx_change_mtu,
1386 .ndo_set_mac_address = eth_mac_addr,
1387 .ndo_validate_addr = eth_validate_addr,
1388 .ndo_do_ioctl = smsc75xx_ioctl,
afc4b13d 1389 .ndo_set_rx_mode = smsc75xx_set_multicast,
78e47fe4 1390 .ndo_set_features = smsc75xx_set_features,
d0cad871
SG
1391};
1392
1393static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
1394{
1395 struct smsc75xx_priv *pdata = NULL;
1396 int ret;
1397
1398 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1399
1400 ret = usbnet_get_endpoints(dev, intf);
e3c678e6
SG
1401 if (ret < 0) {
1402 netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
1403 return ret;
1404 }
d0cad871
SG
1405
1406 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
38673c82 1407 GFP_KERNEL);
d0cad871
SG
1408
1409 pdata = (struct smsc75xx_priv *)(dev->data[0]);
38673c82 1410 if (!pdata)
d0cad871 1411 return -ENOMEM;
d0cad871
SG
1412
1413 pdata->dev = dev;
1414
1415 spin_lock_init(&pdata->rfe_ctl_lock);
1416 mutex_init(&pdata->dataport_mutex);
1417
1418 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
1419
20f01703 1420 if (DEFAULT_TX_CSUM_ENABLE)
78e47fe4 1421 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
20f01703 1422
78e47fe4
MM
1423 if (DEFAULT_RX_CSUM_ENABLE)
1424 dev->net->features |= NETIF_F_RXCSUM;
d0cad871 1425
78e47fe4 1426 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
20f01703 1427 NETIF_F_RXCSUM;
d0cad871 1428
481705a1
SG
1429 ret = smsc75xx_wait_ready(dev, 0);
1430 if (ret < 0) {
1431 netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
1432 return ret;
1433 }
1434
1435 smsc75xx_init_mac_address(dev);
1436
d0cad871
SG
1437 /* Init all registers */
1438 ret = smsc75xx_reset(dev);
e3c678e6
SG
1439 if (ret < 0) {
1440 netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
1441 return ret;
1442 }
d0cad871
SG
1443
1444 dev->net->netdev_ops = &smsc75xx_netdev_ops;
1445 dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
1446 dev->net->flags |= IFF_MULTICAST;
1447 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
a99ff7d0 1448 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
f77f0aee 1449 dev->net->max_mtu = MAX_SINGLE_PACKET_SIZE;
d0cad871
SG
1450 return 0;
1451}
1452
1453static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1454{
1455 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1456 if (pdata) {
1e1d7412 1457 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
d0cad871
SG
1458 kfree(pdata);
1459 pdata = NULL;
1460 dev->data[0] = 0;
1461 }
1462}
1463
899a391b
SG
1464static u16 smsc_crc(const u8 *buffer, size_t len)
1465{
1466 return bitrev16(crc16(0xFFFF, buffer, len));
1467}
1468
1469static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
1470 u32 wuf_mask1)
1471{
1472 int cfg_base = WUF_CFGX + filter * 4;
1473 int mask_base = WUF_MASKX + filter * 16;
1474 int ret;
1475
1476 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
e3c678e6
SG
1477 if (ret < 0) {
1478 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1479 return ret;
1480 }
899a391b
SG
1481
1482 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
e3c678e6
SG
1483 if (ret < 0) {
1484 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1485 return ret;
1486 }
899a391b
SG
1487
1488 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
e3c678e6
SG
1489 if (ret < 0) {
1490 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1491 return ret;
1492 }
899a391b
SG
1493
1494 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
e3c678e6
SG
1495 if (ret < 0) {
1496 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1497 return ret;
1498 }
899a391b
SG
1499
1500 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
e3c678e6
SG
1501 if (ret < 0) {
1502 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1503 return ret;
1504 }
899a391b
SG
1505
1506 return 0;
1507}
1508
9deb2757
SG
1509static int smsc75xx_enter_suspend0(struct usbnet *dev)
1510{
b4cdea9c 1511 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1512 u32 val;
1513 int ret;
1514
1515 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1516 if (ret < 0) {
1517 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1518 return ret;
1519 }
9deb2757
SG
1520
1521 val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
1522 val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
1523
1524 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1525 if (ret < 0) {
1526 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1527 return ret;
1528 }
9deb2757 1529
351f33d9 1530 pdata->suspend_flags |= SUSPEND_SUSPEND0;
b4cdea9c 1531
9deb2757
SG
1532 return 0;
1533}
1534
f329ccdc
SG
1535static int smsc75xx_enter_suspend1(struct usbnet *dev)
1536{
b4cdea9c 1537 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc
SG
1538 u32 val;
1539 int ret;
1540
1541 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1542 if (ret < 0) {
1543 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1544 return ret;
1545 }
f329ccdc
SG
1546
1547 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1548 val |= PMT_CTL_SUS_MODE_1;
1549
1550 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1551 if (ret < 0) {
1552 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1553 return ret;
1554 }
f329ccdc
SG
1555
1556 /* clear wol status, enable energy detection */
1557 val &= ~PMT_CTL_WUPS;
1558 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1559
1560 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1561 if (ret < 0) {
1562 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1563 return ret;
1564 }
f329ccdc 1565
351f33d9 1566 pdata->suspend_flags |= SUSPEND_SUSPEND1;
b4cdea9c 1567
f329ccdc
SG
1568 return 0;
1569}
1570
9deb2757
SG
1571static int smsc75xx_enter_suspend2(struct usbnet *dev)
1572{
b4cdea9c 1573 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1574 u32 val;
1575 int ret;
1576
1577 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1578 if (ret < 0) {
1579 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1580 return ret;
1581 }
9deb2757
SG
1582
1583 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1584 val |= PMT_CTL_SUS_MODE_2;
1585
1586 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1587 if (ret < 0) {
1588 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1589 return ret;
1590 }
9deb2757 1591
b4cdea9c
SG
1592 pdata->suspend_flags |= SUSPEND_SUSPEND2;
1593
1594 return 0;
1595}
1596
1597static int smsc75xx_enter_suspend3(struct usbnet *dev)
1598{
1599 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1600 u32 val;
1601 int ret;
1602
1603 ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
e3c678e6
SG
1604 if (ret < 0) {
1605 netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
1606 return ret;
1607 }
b4cdea9c
SG
1608
1609 if (val & FCT_RX_CTL_RXUSED) {
1610 netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
1611 return -EBUSY;
1612 }
1613
1614 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1615 if (ret < 0) {
1616 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1617 return ret;
1618 }
b4cdea9c
SG
1619
1620 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1621 val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
1622
1623 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1624 if (ret < 0) {
1625 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1626 return ret;
1627 }
b4cdea9c
SG
1628
1629 /* clear wol status */
1630 val &= ~PMT_CTL_WUPS;
1631 val |= PMT_CTL_WUPS_WOL;
1632
1633 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1634 if (ret < 0) {
1635 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1636 return ret;
1637 }
b4cdea9c 1638
351f33d9 1639 pdata->suspend_flags |= SUSPEND_SUSPEND3;
b4cdea9c 1640
9deb2757
SG
1641 return 0;
1642}
1643
f329ccdc
SG
1644static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
1645{
1646 struct mii_if_info *mii = &dev->mii;
1647 int ret;
1648
1649 netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
1650
1651 /* read to clear */
1652 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
e3c678e6
SG
1653 if (ret < 0) {
1654 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
1655 return ret;
1656 }
f329ccdc
SG
1657
1658 /* enable interrupt source */
1659 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
e3c678e6
SG
1660 if (ret < 0) {
1661 netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
1662 return ret;
1663 }
f329ccdc
SG
1664
1665 ret |= mask;
1666
1667 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1668
1669 return 0;
1670}
1671
1672static int smsc75xx_link_ok_nopm(struct usbnet *dev)
1673{
1674 struct mii_if_info *mii = &dev->mii;
1675 int ret;
1676
1677 /* first, a dummy read, needed to latch some MII phys */
1678 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1679 if (ret < 0) {
1680 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1681 return ret;
1682 }
f329ccdc
SG
1683
1684 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1685 if (ret < 0) {
1686 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1687 return ret;
1688 }
f329ccdc
SG
1689
1690 return !!(ret & BMSR_LSTATUS);
1691}
1692
b4cdea9c
SG
1693static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
1694{
1695 int ret;
1696
1697 if (!netif_running(dev->net)) {
1698 /* interface is ifconfig down so fully power down hw */
1699 netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
1700 return smsc75xx_enter_suspend2(dev);
1701 }
1702
1703 if (!link_up) {
1704 /* link is down so enter EDPD mode */
1705 netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
1706
1707 /* enable PHY wakeup events for if cable is attached */
1708 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1709 PHY_INT_MASK_ANEG_COMP);
e3c678e6
SG
1710 if (ret < 0) {
1711 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1712 return ret;
1713 }
b4cdea9c
SG
1714
1715 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1716 return smsc75xx_enter_suspend1(dev);
1717 }
1718
1719 /* enable PHY wakeup events so we remote wakeup if cable is pulled */
1720 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1721 PHY_INT_MASK_LINK_DOWN);
e3c678e6
SG
1722 if (ret < 0) {
1723 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1724 return ret;
1725 }
b4cdea9c
SG
1726
1727 netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
1728 return smsc75xx_enter_suspend3(dev);
1729}
1730
16c79a04
SG
1731static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
1732{
1733 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1734 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc 1735 u32 val, link_up;
16c79a04 1736 int ret;
16c79a04 1737
16c79a04 1738 ret = usbnet_suspend(intf, message);
e3c678e6
SG
1739 if (ret < 0) {
1740 netdev_warn(dev->net, "usbnet_suspend error\n");
1741 return ret;
1742 }
16c79a04 1743
b4cdea9c
SG
1744 if (pdata->suspend_flags) {
1745 netdev_warn(dev->net, "error during last resume\n");
1746 pdata->suspend_flags = 0;
1747 }
1748
f329ccdc
SG
1749 /* determine if link is up using only _nopm functions */
1750 link_up = smsc75xx_link_ok_nopm(dev);
1751
b4cdea9c
SG
1752 if (message.event == PM_EVENT_AUTO_SUSPEND) {
1753 ret = smsc75xx_autosuspend(dev, link_up);
1754 goto done;
1755 }
1756
1757 /* if we get this far we're not autosuspending */
f329ccdc
SG
1758 /* if no wol options set, or if link is down and we're not waking on
1759 * PHY activity, enter lowest power SUSPEND2 mode
1760 */
1761 if (!(pdata->wolopts & SUPPORTED_WAKE) ||
1762 !(link_up || (pdata->wolopts & WAKE_PHY))) {
1e1d7412 1763 netdev_info(dev->net, "entering SUSPEND2 mode\n");
6c636503
SG
1764
1765 /* disable energy detect (link up) & wake up events */
47bbea41 1766 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1767 if (ret < 0) {
1768 netdev_warn(dev->net, "Error reading WUCSR\n");
1769 goto done;
1770 }
6c636503
SG
1771
1772 val &= ~(WUCSR_MPEN | WUCSR_WUEN);
1773
47bbea41 1774 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1775 if (ret < 0) {
1776 netdev_warn(dev->net, "Error writing WUCSR\n");
1777 goto done;
1778 }
6c636503 1779
47bbea41 1780 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1781 if (ret < 0) {
1782 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1783 goto done;
1784 }
6c636503
SG
1785
1786 val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
1787
47bbea41 1788 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1789 if (ret < 0) {
1790 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1791 goto done;
1792 }
6c636503 1793
eacdd6c2
SG
1794 ret = smsc75xx_enter_suspend2(dev);
1795 goto done;
6c636503
SG
1796 }
1797
f329ccdc
SG
1798 if (pdata->wolopts & WAKE_PHY) {
1799 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1800 (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
e3c678e6
SG
1801 if (ret < 0) {
1802 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1803 goto done;
1804 }
f329ccdc
SG
1805
1806 /* if link is down then configure EDPD and enter SUSPEND1,
1807 * otherwise enter SUSPEND0 below
1808 */
1809 if (!link_up) {
1810 struct mii_if_info *mii = &dev->mii;
1811 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1812
1813 /* enable energy detect power-down mode */
1814 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1815 PHY_MODE_CTRL_STS);
e3c678e6
SG
1816 if (ret < 0) {
1817 netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
1818 goto done;
1819 }
f329ccdc
SG
1820
1821 ret |= MODE_CTRL_STS_EDPWRDOWN;
1822
1823 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
1824 PHY_MODE_CTRL_STS, ret);
1825
1826 /* enter SUSPEND1 mode */
eacdd6c2
SG
1827 ret = smsc75xx_enter_suspend1(dev);
1828 goto done;
f329ccdc
SG
1829 }
1830 }
1831
899a391b
SG
1832 if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
1833 int i, filter = 0;
1834
1835 /* disable all filters */
1836 for (i = 0; i < WUF_NUM; i++) {
47bbea41 1837 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
e3c678e6
SG
1838 if (ret < 0) {
1839 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1840 goto done;
1841 }
899a391b
SG
1842 }
1843
1844 if (pdata->wolopts & WAKE_MCAST) {
1845 const u8 mcast[] = {0x01, 0x00, 0x5E};
1e1d7412 1846 netdev_info(dev->net, "enabling multicast detection\n");
899a391b
SG
1847
1848 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
1849 | smsc_crc(mcast, 3);
1850 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
e3c678e6
SG
1851 if (ret < 0) {
1852 netdev_warn(dev->net, "Error writing wakeup filter\n");
1853 goto done;
1854 }
899a391b
SG
1855 }
1856
1857 if (pdata->wolopts & WAKE_ARP) {
1858 const u8 arp[] = {0x08, 0x06};
1e1d7412 1859 netdev_info(dev->net, "enabling ARP detection\n");
899a391b
SG
1860
1861 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
1862 | smsc_crc(arp, 2);
1863 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
e3c678e6
SG
1864 if (ret < 0) {
1865 netdev_warn(dev->net, "Error writing wakeup filter\n");
1866 goto done;
1867 }
899a391b
SG
1868 }
1869
1870 /* clear any pending pattern match packet status */
47bbea41 1871 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1872 if (ret < 0) {
1873 netdev_warn(dev->net, "Error reading WUCSR\n");
1874 goto done;
1875 }
899a391b
SG
1876
1877 val |= WUCSR_WUFR;
1878
47bbea41 1879 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1880 if (ret < 0) {
1881 netdev_warn(dev->net, "Error writing WUCSR\n");
1882 goto done;
1883 }
899a391b 1884
1e1d7412 1885 netdev_info(dev->net, "enabling packet match detection\n");
47bbea41 1886 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1887 if (ret < 0) {
1888 netdev_warn(dev->net, "Error reading WUCSR\n");
1889 goto done;
1890 }
899a391b
SG
1891
1892 val |= WUCSR_WUEN;
1893
47bbea41 1894 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1895 if (ret < 0) {
1896 netdev_warn(dev->net, "Error writing WUCSR\n");
1897 goto done;
1898 }
899a391b 1899 } else {
1e1d7412 1900 netdev_info(dev->net, "disabling packet match detection\n");
47bbea41 1901 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1902 if (ret < 0) {
1903 netdev_warn(dev->net, "Error reading WUCSR\n");
1904 goto done;
1905 }
6c636503 1906
899a391b 1907 val &= ~WUCSR_WUEN;
16c79a04 1908
47bbea41 1909 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1910 if (ret < 0) {
1911 netdev_warn(dev->net, "Error writing WUCSR\n");
1912 goto done;
1913 }
6c636503
SG
1914 }
1915
899a391b 1916 /* disable magic, bcast & unicast wakeup sources */
47bbea41 1917 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1918 if (ret < 0) {
1919 netdev_warn(dev->net, "Error reading WUCSR\n");
1920 goto done;
1921 }
6c636503 1922
899a391b
SG
1923 val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
1924
47bbea41 1925 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1926 if (ret < 0) {
1927 netdev_warn(dev->net, "Error writing WUCSR\n");
1928 goto done;
1929 }
899a391b 1930
f329ccdc
SG
1931 if (pdata->wolopts & WAKE_PHY) {
1932 netdev_info(dev->net, "enabling PHY wakeup\n");
1933
1934 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1935 if (ret < 0) {
1936 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1937 goto done;
1938 }
f329ccdc
SG
1939
1940 /* clear wol status, enable energy detection */
1941 val &= ~PMT_CTL_WUPS;
1942 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1943
1944 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1945 if (ret < 0) {
1946 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1947 goto done;
1948 }
f329ccdc
SG
1949 }
1950
6c636503 1951 if (pdata->wolopts & WAKE_MAGIC) {
1e1d7412 1952 netdev_info(dev->net, "enabling magic packet wakeup\n");
47bbea41 1953 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1954 if (ret < 0) {
1955 netdev_warn(dev->net, "Error reading WUCSR\n");
1956 goto done;
1957 }
899a391b
SG
1958
1959 /* clear any pending magic packet status */
1960 val |= WUCSR_MPR | WUCSR_MPEN;
1961
47bbea41 1962 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1963 if (ret < 0) {
1964 netdev_warn(dev->net, "Error writing WUCSR\n");
1965 goto done;
1966 }
6c636503
SG
1967 }
1968
899a391b 1969 if (pdata->wolopts & WAKE_BCAST) {
1e1d7412 1970 netdev_info(dev->net, "enabling broadcast detection\n");
47bbea41 1971 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1972 if (ret < 0) {
1973 netdev_warn(dev->net, "Error reading WUCSR\n");
1974 goto done;
1975 }
6c636503 1976
899a391b 1977 val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
16c79a04 1978
47bbea41 1979 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1980 if (ret < 0) {
1981 netdev_warn(dev->net, "Error writing WUCSR\n");
1982 goto done;
1983 }
899a391b 1984 }
6c636503 1985
899a391b 1986 if (pdata->wolopts & WAKE_UCAST) {
1e1d7412 1987 netdev_info(dev->net, "enabling unicast detection\n");
47bbea41 1988 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1989 if (ret < 0) {
1990 netdev_warn(dev->net, "Error reading WUCSR\n");
1991 goto done;
1992 }
899a391b
SG
1993
1994 val |= WUCSR_WUFR | WUCSR_PFDA_EN;
6c636503 1995
47bbea41 1996 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1997 if (ret < 0) {
1998 netdev_warn(dev->net, "Error writing WUCSR\n");
1999 goto done;
2000 }
899a391b
SG
2001 }
2002
2003 /* enable receiver to enable frame reception */
47bbea41 2004 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
e3c678e6
SG
2005 if (ret < 0) {
2006 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
2007 goto done;
2008 }
6c636503
SG
2009
2010 val |= MAC_RX_RXEN;
2011
47bbea41 2012 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
e3c678e6
SG
2013 if (ret < 0) {
2014 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
2015 goto done;
2016 }
6c636503
SG
2017
2018 /* some wol options are enabled, so enter SUSPEND0 */
1e1d7412 2019 netdev_info(dev->net, "entering SUSPEND0 mode\n");
eacdd6c2
SG
2020 ret = smsc75xx_enter_suspend0(dev);
2021
2022done:
5410a473
ML
2023 /*
2024 * TODO: resume() might need to handle the suspend failure
2025 * in system sleep
2026 */
2027 if (ret && PMSG_IS_AUTO(message))
eacdd6c2
SG
2028 usbnet_resume(intf);
2029 return ret;
16c79a04
SG
2030}
2031
2032static int smsc75xx_resume(struct usb_interface *intf)
2033{
2034 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 2035 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
b4cdea9c 2036 u8 suspend_flags = pdata->suspend_flags;
16c79a04
SG
2037 int ret;
2038 u32 val;
2039
b4cdea9c 2040 netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
16c79a04 2041
b4cdea9c
SG
2042 /* do this first to ensure it's cleared even in error case */
2043 pdata->suspend_flags = 0;
2044
b4cdea9c 2045 if (suspend_flags & SUSPEND_ALLMODES) {
899a391b 2046 /* Disable wakeup sources */
47bbea41 2047 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
2048 if (ret < 0) {
2049 netdev_warn(dev->net, "Error reading WUCSR\n");
2050 return ret;
2051 }
16c79a04 2052
899a391b
SG
2053 val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
2054 | WUCSR_BCST_EN);
16c79a04 2055
47bbea41 2056 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
2057 if (ret < 0) {
2058 netdev_warn(dev->net, "Error writing WUCSR\n");
2059 return ret;
2060 }
6c636503
SG
2061
2062 /* clear wake-up status */
47bbea41 2063 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2064 if (ret < 0) {
2065 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2066 return ret;
2067 }
6c636503
SG
2068
2069 val &= ~PMT_CTL_WOL_EN;
2070 val |= PMT_CTL_WUPS;
2071
47bbea41 2072 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2073 if (ret < 0) {
2074 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2075 return ret;
2076 }
b4cdea9c
SG
2077 }
2078
2079 if (suspend_flags & SUSPEND_SUSPEND2) {
1e1d7412 2080 netdev_info(dev->net, "resuming from SUSPEND2\n");
6c636503 2081
47bbea41 2082 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2083 if (ret < 0) {
2084 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2085 return ret;
2086 }
6c636503
SG
2087
2088 val |= PMT_CTL_PHY_PWRUP;
2089
47bbea41 2090 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2091 if (ret < 0) {
2092 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2093 return ret;
2094 }
6c636503 2095 }
16c79a04 2096
47bbea41 2097 ret = smsc75xx_wait_ready(dev, 1);
e3c678e6
SG
2098 if (ret < 0) {
2099 netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
2100 return ret;
2101 }
16c79a04
SG
2102
2103 return usbnet_resume(intf);
2104}
2105
78e47fe4
MM
2106static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
2107 u32 rx_cmd_a, u32 rx_cmd_b)
d0cad871 2108{
78e47fe4
MM
2109 if (!(dev->net->features & NETIF_F_RXCSUM) ||
2110 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
d0cad871
SG
2111 skb->ip_summed = CHECKSUM_NONE;
2112 } else {
2113 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
2114 skb->ip_summed = CHECKSUM_COMPLETE;
2115 }
2116}
2117
2118static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
2119{
eb85569f
EG
2120 /* This check is no longer done by usbnet */
2121 if (skb->len < dev->net->hard_header_len)
2122 return 0;
2123
d0cad871
SG
2124 while (skb->len > 0) {
2125 u32 rx_cmd_a, rx_cmd_b, align_count, size;
2126 struct sk_buff *ax_skb;
2127 unsigned char *packet;
2128
2129 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
2130 le32_to_cpus(&rx_cmd_a);
2131 skb_pull(skb, 4);
2132
2133 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
2134 le32_to_cpus(&rx_cmd_b);
ea1649de 2135 skb_pull(skb, 4 + RXW_PADDING);
d0cad871
SG
2136
2137 packet = skb->data;
2138
2139 /* get the packet length */
ea1649de
NE
2140 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
2141 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
d0cad871
SG
2142
2143 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
2144 netif_dbg(dev, rx_err, dev->net,
1e1d7412 2145 "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
d0cad871
SG
2146 dev->net->stats.rx_errors++;
2147 dev->net->stats.rx_dropped++;
2148
2149 if (rx_cmd_a & RX_CMD_A_FCS)
2150 dev->net->stats.rx_crc_errors++;
2151 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
2152 dev->net->stats.rx_frame_errors++;
2153 } else {
4c51e536
SG
2154 /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
2155 if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
d0cad871 2156 netif_dbg(dev, rx_err, dev->net,
1e1d7412
JP
2157 "size err rx_cmd_a=0x%08x\n",
2158 rx_cmd_a);
d0cad871
SG
2159 return 0;
2160 }
2161
2162 /* last frame in this batch */
2163 if (skb->len == size) {
78e47fe4
MM
2164 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
2165 rx_cmd_b);
d0cad871
SG
2166
2167 skb_trim(skb, skb->len - 4); /* remove fcs */
2168 skb->truesize = size + sizeof(struct sk_buff);
2169
2170 return 1;
2171 }
2172
2173 ax_skb = skb_clone(skb, GFP_ATOMIC);
2174 if (unlikely(!ax_skb)) {
1e1d7412 2175 netdev_warn(dev->net, "Error allocating skb\n");
d0cad871
SG
2176 return 0;
2177 }
2178
2179 ax_skb->len = size;
2180 ax_skb->data = packet;
2181 skb_set_tail_pointer(ax_skb, size);
2182
78e47fe4
MM
2183 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
2184 rx_cmd_b);
d0cad871
SG
2185
2186 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
2187 ax_skb->truesize = size + sizeof(struct sk_buff);
2188
2189 usbnet_skb_return(dev, ax_skb);
2190 }
2191
2192 skb_pull(skb, size);
2193
2194 /* padding bytes before the next frame starts */
2195 if (skb->len)
2196 skb_pull(skb, align_count);
2197 }
2198
d0cad871
SG
2199 return 1;
2200}
2201
2202static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
2203 struct sk_buff *skb, gfp_t flags)
2204{
2205 u32 tx_cmd_a, tx_cmd_b;
2206
b7c6d267 2207 if (skb_cow_head(skb, SMSC75XX_TX_OVERHEAD)) {
d0cad871 2208 dev_kfree_skb_any(skb);
b7c6d267 2209 return NULL;
d0cad871
SG
2210 }
2211
2212 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
2213
2214 if (skb->ip_summed == CHECKSUM_PARTIAL)
2215 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
2216
2217 if (skb_is_gso(skb)) {
2218 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
2219 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
2220
2221 tx_cmd_a |= TX_CMD_A_LSO;
2222 } else {
2223 tx_cmd_b = 0;
2224 }
2225
2226 skb_push(skb, 4);
2227 cpu_to_le32s(&tx_cmd_b);
2228 memcpy(skb->data, &tx_cmd_b, 4);
2229
2230 skb_push(skb, 4);
2231 cpu_to_le32s(&tx_cmd_a);
2232 memcpy(skb->data, &tx_cmd_a, 4);
2233
2234 return skb;
2235}
2236
b4cdea9c
SG
2237static int smsc75xx_manage_power(struct usbnet *dev, int on)
2238{
2239 dev->intf->needs_remote_wakeup = on;
2240 return 0;
2241}
2242
d0cad871
SG
2243static const struct driver_info smsc75xx_info = {
2244 .description = "smsc75xx USB 2.0 Gigabit Ethernet",
2245 .bind = smsc75xx_bind,
2246 .unbind = smsc75xx_unbind,
2247 .link_reset = smsc75xx_link_reset,
2248 .reset = smsc75xx_reset,
2249 .rx_fixup = smsc75xx_rx_fixup,
2250 .tx_fixup = smsc75xx_tx_fixup,
2251 .status = smsc75xx_status,
b4cdea9c 2252 .manage_power = smsc75xx_manage_power,
7bdd305e 2253 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
d0cad871
SG
2254};
2255
2256static const struct usb_device_id products[] = {
2257 {
2258 /* SMSC7500 USB Gigabit Ethernet Device */
2259 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
2260 .driver_info = (unsigned long) &smsc75xx_info,
2261 },
2262 {
2263 /* SMSC7500 USB Gigabit Ethernet Device */
2264 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
2265 .driver_info = (unsigned long) &smsc75xx_info,
2266 },
2267 { }, /* END */
2268};
2269MODULE_DEVICE_TABLE(usb, products);
2270
2271static struct usb_driver smsc75xx_driver = {
2272 .name = SMSC_CHIPNAME,
2273 .id_table = products,
2274 .probe = usbnet_probe,
16c79a04
SG
2275 .suspend = smsc75xx_suspend,
2276 .resume = smsc75xx_resume,
2277 .reset_resume = smsc75xx_resume,
d0cad871 2278 .disconnect = usbnet_disconnect,
e1f12eb6 2279 .disable_hub_initiated_lpm = 1,
b4cdea9c 2280 .supports_autosuspend = 1,
d0cad871
SG
2281};
2282
d632eb1b 2283module_usb_driver(smsc75xx_driver);
d0cad871
SG
2284
2285MODULE_AUTHOR("Nancy Lin");
90b24cfb 2286MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
d0cad871
SG
2287MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
2288MODULE_LICENSE("GPL");