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vmxnet3: add receive data ring support
[mirror_ubuntu-artful-kernel.git] / drivers / net / vmxnet3 / vmxnet3_defs.h
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
190af10f 4 * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved.
d1a890fa
SB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
190af10f 23 * Maintained by: pv-drivers@vmware.com
d1a890fa
SB		 24 *
25 */
26
27#ifndef _VMXNET3_DEFS_H_
28#define _VMXNET3_DEFS_H_
29
30#include "upt1_defs.h"
31
32/* all registers are 32 bit wide */
33/* BAR 1 */
34enum {
35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
39 VMXNET3_REG_CMD = 0x20, /* Command */
40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */
42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
43 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */
44};
45
46/* BAR 0 */
47enum {
48 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
49 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
50 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
51 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
52};
53
54#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
55#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
56
57#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
58#define VMXNET3_REG_ALIGN_MASK 0x7
59
60/* I/O Mapped access to registers */
61#define VMXNET3_IO_TYPE_PT 0
62#define VMXNET3_IO_TYPE_VD 1
63#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
64#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
65#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
66
67enum {
68 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
69 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
70 VMXNET3_CMD_QUIESCE_DEV,
71 VMXNET3_CMD_RESET_DEV,
72 VMXNET3_CMD_UPDATE_RX_MODE,
73 VMXNET3_CMD_UPDATE_MAC_FILTERS,
74 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
75 VMXNET3_CMD_UPDATE_RSSIDT,
76 VMXNET3_CMD_UPDATE_IML,
77 VMXNET3_CMD_UPDATE_PMCFG,
78 VMXNET3_CMD_UPDATE_FEATURE,
190af10f 79 VMXNET3_CMD_RESERVED1,
d1a890fa 80 VMXNET3_CMD_LOAD_PLUGIN,
190af10f 81 VMXNET3_CMD_RESERVED2,
f35c7480 82 VMXNET3_CMD_RESERVED3,
d1a890fa
SB		 83
84 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
85 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
86 VMXNET3_CMD_GET_STATS,
87 VMXNET3_CMD_GET_LINK,
88 VMXNET3_CMD_GET_PERM_MAC_LO,
89 VMXNET3_CMD_GET_PERM_MAC_HI,
90 VMXNET3_CMD_GET_DID_LO,
91 VMXNET3_CMD_GET_DID_HI,
92 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
190af10f
SK		 93 VMXNET3_CMD_GET_CONF_INTR,
94 VMXNET3_CMD_GET_RESERVED1,
3c8b3efc 95 VMXNET3_CMD_GET_TXDATA_DESC_SIZE
d1a890fa
SB		 96};
97
115924b6
SB		 98/*
99 * Little Endian layout of bitfields -
100 * Byte 0 : 7.....len.....0
101 * Byte 1 : rsvd gen 13.len.8
102 * Byte 2 : 5.msscof.0 ext1 dtype
103 * Byte 3 : 13...msscof...6
104 *
105 * Big Endian layout of bitfields -
106 * Byte 0: 13...msscof...6
107 * Byte 1 : 5.msscof.0 ext1 dtype
108 * Byte 2 : rsvd gen 13.len.8
109 * Byte 3 : 7.....len.....0
110 *
111 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
112 * the bit fields correctly. And cpu_to_le32 will convert bitfields
113 * bit fields written by big endian driver to format required by device.
114 */
d1a890fa 115
115924b6
SB		 116struct Vmxnet3_TxDesc {
117 __le64 addr;
118
119#ifdef __BIG_ENDIAN_BITFIELD
120 u32 msscof:14; /* MSS, checksum offset, flags */
121 u32 ext1:1;
122 u32 dtype:1; /* descriptor type */
123 u32 rsvd:1;
124 u32 gen:1; /* generation bit */
125 u32 len:14;
126#else
127 u32 len:14;
128 u32 gen:1; /* generation bit */
129 u32 rsvd:1;
130 u32 dtype:1; /* descriptor type */
131 u32 ext1:1;
132 u32 msscof:14; /* MSS, checksum offset, flags */
133#endif /* __BIG_ENDIAN_BITFIELD */
134
135#ifdef __BIG_ENDIAN_BITFIELD
136 u32 tci:16; /* Tag to Insert */
137 u32 ti:1; /* VLAN Tag Insertion */
138 u32 ext2:1;
139 u32 cq:1; /* completion request */
140 u32 eop:1; /* End Of Packet */
141 u32 om:2; /* offload mode */
142 u32 hlen:10; /* header len */
143#else
144 u32 hlen:10; /* header len */
145 u32 om:2; /* offload mode */
146 u32 eop:1; /* End Of Packet */
147 u32 cq:1; /* completion request */
148 u32 ext2:1;
149 u32 ti:1; /* VLAN Tag Insertion */
150 u32 tci:16; /* Tag to Insert */
151#endif /* __BIG_ENDIAN_BITFIELD */
d1a890fa
SB		 152};
153
154/* TxDesc.OM values */
155#define VMXNET3_OM_NONE 0
156#define VMXNET3_OM_CSUM 2
157#define VMXNET3_OM_TSO 3
158
159/* fields in TxDesc we access w/o using bit fields */
160#define VMXNET3_TXD_EOP_SHIFT 12
161#define VMXNET3_TXD_CQ_SHIFT 13
162#define VMXNET3_TXD_GEN_SHIFT 14
115924b6
SB		 163#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
164#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
d1a890fa
SB		 165
166#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
167#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
168#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
169
170#define VMXNET3_HDR_COPY_SIZE 128
171
172
173struct Vmxnet3_TxDataDesc {
174 u8 data[VMXNET3_HDR_COPY_SIZE];
175};
176
50a5ce3e
SK		 177typedef u8 Vmxnet3_RxDataDesc;
178
115924b6
SB		 179#define VMXNET3_TCD_GEN_SHIFT 31
180#define VMXNET3_TCD_GEN_SIZE 1
181#define VMXNET3_TCD_TXIDX_SHIFT 0
182#define VMXNET3_TCD_TXIDX_SIZE 12
183#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
d1a890fa
SB		 184
185struct Vmxnet3_TxCompDesc {
186 u32 txdIdx:12; /* Index of the EOP TxDesc */
187 u32 ext1:20;
188
115924b6
SB		 189 __le32 ext2;
190 __le32 ext3;
d1a890fa
SB		 191
192 u32 rsvd:24;
193 u32 type:7; /* completion type */
194 u32 gen:1; /* generation bit */
195};
196
d1a890fa 197struct Vmxnet3_RxDesc {
115924b6 198 __le64 addr;
d1a890fa 199
115924b6
SB		 200#ifdef __BIG_ENDIAN_BITFIELD
201 u32 gen:1; /* Generation bit */
202 u32 rsvd:15;
203 u32 dtype:1; /* Descriptor type */
204 u32 btype:1; /* Buffer Type */
205 u32 len:14;
206#else
d1a890fa
SB		 207 u32 len:14;
208 u32 btype:1; /* Buffer Type */
209 u32 dtype:1; /* Descriptor type */
210 u32 rsvd:15;
211 u32 gen:1; /* Generation bit */
115924b6 212#endif
d1a890fa
SB		 213 u32 ext1;
214};
215
216/* values of RXD.BTYPE */
217#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
218#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
219
220/* fields in RxDesc we access w/o using bit fields */
221#define VMXNET3_RXD_BTYPE_SHIFT 14
222#define VMXNET3_RXD_GEN_SHIFT 31
223
d1a890fa 224struct Vmxnet3_RxCompDesc {
115924b6
SB		 225#ifdef __BIG_ENDIAN_BITFIELD
226 u32 ext2:1;
227 u32 cnc:1; /* Checksum Not Calculated */
228 u32 rssType:4; /* RSS hash type used */
229 u32 rqID:10; /* rx queue/ring ID */
230 u32 sop:1; /* Start of Packet */
231 u32 eop:1; /* End of Packet */
232 u32 ext1:2;
233 u32 rxdIdx:12; /* Index of the RxDesc */
234#else
d1a890fa
SB		 235 u32 rxdIdx:12; /* Index of the RxDesc */
236 u32 ext1:2;
237 u32 eop:1; /* End of Packet */
238 u32 sop:1; /* Start of Packet */
239 u32 rqID:10; /* rx queue/ring ID */
240 u32 rssType:4; /* RSS hash type used */
241 u32 cnc:1; /* Checksum Not Calculated */
242 u32 ext2:1;
115924b6 243#endif /* __BIG_ENDIAN_BITFIELD */
d1a890fa 244
115924b6 245 __le32 rssHash; /* RSS hash value */
d1a890fa 246
115924b6
SB		 247#ifdef __BIG_ENDIAN_BITFIELD
248 u32 tci:16; /* Tag stripped */
249 u32 ts:1; /* Tag is stripped */
250 u32 err:1; /* Error */
251 u32 len:14; /* data length */
252#else
d1a890fa
SB		 253 u32 len:14; /* data length */
254 u32 err:1; /* Error */
255 u32 ts:1; /* Tag is stripped */
256 u32 tci:16; /* Tag stripped */
115924b6
SB		 257#endif /* __BIG_ENDIAN_BITFIELD */
258
d1a890fa 259
115924b6
SB		 260#ifdef __BIG_ENDIAN_BITFIELD
261 u32 gen:1; /* generation bit */
262 u32 type:7; /* completion type */
263 u32 fcs:1; /* Frame CRC correct */
264 u32 frg:1; /* IP Fragment */
265 u32 v4:1; /* IPv4 */
266 u32 v6:1; /* IPv6 */
267 u32 ipc:1; /* IP Checksum Correct */
268 u32 tcp:1; /* TCP packet */
269 u32 udp:1; /* UDP packet */
270 u32 tuc:1; /* TCP/UDP Checksum Correct */
271 u32 csum:16;
272#else
d1a890fa
SB		 273 u32 csum:16;
274 u32 tuc:1; /* TCP/UDP Checksum Correct */
275 u32 udp:1; /* UDP packet */
276 u32 tcp:1; /* TCP packet */
277 u32 ipc:1; /* IP Checksum Correct */
278 u32 v6:1; /* IPv6 */
279 u32 v4:1; /* IPv4 */
280 u32 frg:1; /* IP Fragment */
281 u32 fcs:1; /* Frame CRC correct */
282 u32 type:7; /* completion type */
283 u32 gen:1; /* generation bit */
115924b6 284#endif /* __BIG_ENDIAN_BITFIELD */
d1a890fa
SB		 285};
286
45dac1d6
SB		 287struct Vmxnet3_RxCompDescExt {
288 __le32 dword1;
289 u8 segCnt; /* Number of aggregated packets */
290 u8 dupAckCnt; /* Number of duplicate Acks */
291 __le16 tsDelta; /* TCP timestamp difference */
292 __le32 dword2;
293#ifdef __BIG_ENDIAN_BITFIELD
294 u32 gen:1; /* generation bit */
295 u32 type:7; /* completion type */
296 u32 fcs:1; /* Frame CRC correct */
297 u32 frg:1; /* IP Fragment */
298 u32 v4:1; /* IPv4 */
299 u32 v6:1; /* IPv6 */
300 u32 ipc:1; /* IP Checksum Correct */
301 u32 tcp:1; /* TCP packet */
302 u32 udp:1; /* UDP packet */
303 u32 tuc:1; /* TCP/UDP Checksum Correct */
304 u32 mss:16;
305#else
306 u32 mss:16;
307 u32 tuc:1; /* TCP/UDP Checksum Correct */
308 u32 udp:1; /* UDP packet */
309 u32 tcp:1; /* TCP packet */
310 u32 ipc:1; /* IP Checksum Correct */
311 u32 v6:1; /* IPv6 */
312 u32 v4:1; /* IPv4 */
313 u32 frg:1; /* IP Fragment */
314 u32 fcs:1; /* Frame CRC correct */
315 u32 type:7; /* completion type */
316 u32 gen:1; /* generation bit */
317#endif /* __BIG_ENDIAN_BITFIELD */
318};
319
320
d1a890fa
SB		 321/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
322#define VMXNET3_RCD_TUC_SHIFT 16
323#define VMXNET3_RCD_IPC_SHIFT 19
324
325/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
326#define VMXNET3_RCD_TYPE_SHIFT 56
327#define VMXNET3_RCD_GEN_SHIFT 63
328
329/* csum OK for TCP/UDP pkts over IP */
330#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
331 1 << VMXNET3_RCD_IPC_SHIFT)
115924b6
SB		 332#define VMXNET3_TXD_GEN_SIZE 1
333#define VMXNET3_TXD_EOP_SIZE 1
d1a890fa
SB		 334
335/* value of RxCompDesc.rssType */
336enum {
337 VMXNET3_RCD_RSS_TYPE_NONE = 0,
338 VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
339 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
340 VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
341 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
342};
343
344
345/* a union for accessing all cmd/completion descriptors */
346union Vmxnet3_GenericDesc {
115924b6
SB		 347 __le64 qword[2];
348 __le32 dword[4];
349 __le16 word[8];
d1a890fa
SB		 350 struct Vmxnet3_TxDesc txd;
351 struct Vmxnet3_RxDesc rxd;
352 struct Vmxnet3_TxCompDesc tcd;
353 struct Vmxnet3_RxCompDesc rcd;
45dac1d6 354 struct Vmxnet3_RxCompDescExt rcdExt;
d1a890fa
SB		 355};
356
357#define VMXNET3_INIT_GEN 1
358
359/* Max size of a single tx buffer */
360#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
361
362/* # of tx desc needed for a tx buffer size */
363#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
364 VMXNET3_MAX_TX_BUF_SIZE)
365
366/* max # of tx descs for a non-tso pkt */
367#define VMXNET3_MAX_TXD_PER_PKT 16
368
369/* Max size of a single rx buffer */
370#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
371/* Minimum size of a type 0 buffer */
372#define VMXNET3_MIN_T0_BUF_SIZE 128
373#define VMXNET3_MAX_CSUM_OFFSET 1024
374
375/* Ring base address alignment */
376#define VMXNET3_RING_BA_ALIGN 512
377#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
378
379/* Ring size must be a multiple of 32 */
380#define VMXNET3_RING_SIZE_ALIGN 32
381#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
382
3c8b3efc
SK		 383/* Tx Data Ring buffer size must be a multiple of 64 */
384#define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
385#define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
386
50a5ce3e
SK		 387/* Rx Data Ring buffer size must be a multiple of 64 */
388#define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
389#define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
390
d1a890fa
SB		 391/* Max ring size */
392#define VMXNET3_TX_RING_MAX_SIZE 4096
393#define VMXNET3_TC_RING_MAX_SIZE 4096
394#define VMXNET3_RX_RING_MAX_SIZE 4096
14112ca5 395#define VMXNET3_RX_RING2_MAX_SIZE 4096
d1a890fa
SB		 396#define VMXNET3_RC_RING_MAX_SIZE 8192
397
3c8b3efc
SK		 398#define VMXNET3_TXDATA_DESC_MIN_SIZE 128
399#define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
400
50a5ce3e
SK		 401#define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
402
d1a890fa
SB		 403/* a list of reasons for queue stop */
404
405enum {
406 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
407 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
408 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
409 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
410 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
411 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
412 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
413 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
414};
415
416/* completion descriptor types */
417#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
418#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
45dac1d6 419#define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
d1a890fa
SB		 420
421enum {
422 VMXNET3_GOS_BITS_UNK = 0, /* unknown */
423 VMXNET3_GOS_BITS_32 = 1,
424 VMXNET3_GOS_BITS_64 = 2,
425};
426
427#define VMXNET3_GOS_TYPE_LINUX 1
428
429
430struct Vmxnet3_GOSInfo {
115924b6
SB		 431#ifdef __BIG_ENDIAN_BITFIELD
432 u32 gosMisc:10; /* other info about gos */
433 u32 gosVer:16; /* gos version */
434 u32 gosType:4; /* which guest */
435 u32 gosBits:2; /* 32-bit or 64-bit? */
436#else
437 u32 gosBits:2; /* 32-bit or 64-bit? */
438 u32 gosType:4; /* which guest */
439 u32 gosVer:16; /* gos version */
440 u32 gosMisc:10; /* other info about gos */
441#endif /* __BIG_ENDIAN_BITFIELD */
d1a890fa
SB		 442};
443
d1a890fa 444struct Vmxnet3_DriverInfo {
115924b6 445 __le32 version;
d1a890fa 446 struct Vmxnet3_GOSInfo gos;
115924b6
SB		 447 __le32 vmxnet3RevSpt;
448 __le32 uptVerSpt;
d1a890fa
SB		 449};
450
451
dd83829e 452#define VMXNET3_REV1_MAGIC 3133079265u
d1a890fa
SB		 453
454/*
455 * QueueDescPA must be 128 bytes aligned. It points to an array of
456 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
457 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
458 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
459 */
460#define VMXNET3_QUEUE_DESC_ALIGN 128
461
462
463struct Vmxnet3_MiscConf {
464 struct Vmxnet3_DriverInfo driverInfo;
115924b6
SB		 465 __le64 uptFeatures;
466 __le64 ddPA; /* driver data PA */
467 __le64 queueDescPA; /* queue descriptor table PA */
468 __le32 ddLen; /* driver data len */
469 __le32 queueDescLen; /* queue desc. table len in bytes */
470 __le32 mtu;
471 __le16 maxNumRxSG;
d1a890fa
SB		 472 u8 numTxQueues;
473 u8 numRxQueues;
115924b6 474 __le32 reserved[4];
d1a890fa
SB		 475};
476
477
478struct Vmxnet3_TxQueueConf {
115924b6
SB		 479 __le64 txRingBasePA;
480 __le64 dataRingBasePA;
481 __le64 compRingBasePA;
482 __le64 ddPA; /* driver data */
483 __le64 reserved;
484 __le32 txRingSize; /* # of tx desc */
485 __le32 dataRingSize; /* # of data desc */
486 __le32 compRingSize; /* # of comp desc */
487 __le32 ddLen; /* size of driver data */
d1a890fa 488 u8 intrIdx;
3c8b3efc
SK		 489 u8 _pad1[1];
490 __le16 txDataRingDescSize;
491 u8 _pad2[4];
d1a890fa
SB		 492};
493
494
495struct Vmxnet3_RxQueueConf {
115924b6
SB		 496 __le64 rxRingBasePA[2];
497 __le64 compRingBasePA;
498 __le64 ddPA; /* driver data */
50a5ce3e 499 __le64 rxDataRingBasePA;
115924b6
SB		 500 __le32 rxRingSize[2]; /* # of rx desc */
501 __le32 compRingSize; /* # of rx comp desc */
502 __le32 ddLen; /* size of driver data */
d1a890fa 503 u8 intrIdx;
50a5ce3e
SK		 504 u8 _pad1[1];
505 __le16 rxDataRingDescSize; /* size of rx data ring buffer */
506 u8 _pad2[4];
d1a890fa
SB		 507};
508
509
510enum vmxnet3_intr_mask_mode {
511 VMXNET3_IMM_AUTO = 0,
512 VMXNET3_IMM_ACTIVE = 1,
513 VMXNET3_IMM_LAZY = 2
514};
515
516enum vmxnet3_intr_type {
517 VMXNET3_IT_AUTO = 0,
518 VMXNET3_IT_INTX = 1,
519 VMXNET3_IT_MSI = 2,
520 VMXNET3_IT_MSIX = 3
521};
522
523#define VMXNET3_MAX_TX_QUEUES 8
524#define VMXNET3_MAX_RX_QUEUES 16
525/* addition 1 for events */
526#define VMXNET3_MAX_INTRS 25
527
6929fe8a
RZ		 528/* value of intrCtrl */
529#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
530
d1a890fa
SB		 531
532struct Vmxnet3_IntrConf {
533 bool autoMask;
534 u8 numIntrs; /* # of interrupts */
535 u8 eventIntrIdx;
536 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for
537 * each intr */
6929fe8a
RZ		 538 __le32 intrCtrl;
539 __le32 reserved[2];
d1a890fa
SB		 540};
541
542/* one bit per VLAN ID, the size is in the units of u32 */
543#define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8))
544
545
546struct Vmxnet3_QueueStatus {
547 bool stopped;
548 u8 _pad[3];
115924b6 549 __le32 error;
d1a890fa
SB		 550};
551
552
553struct Vmxnet3_TxQueueCtrl {
115924b6
SB		 554 __le32 txNumDeferred;
555 __le32 txThreshold;
556 __le64 reserved;
d1a890fa
SB		 557};
558
559
560struct Vmxnet3_RxQueueCtrl {
561 bool updateRxProd;
562 u8 _pad[7];
115924b6 563 __le64 reserved;
d1a890fa
SB		 564};
565
566enum {
567 VMXNET3_RXM_UCAST = 0x01, /* unicast only */
568 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
569 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
570 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
571 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
572};
573
574struct Vmxnet3_RxFilterConf {
115924b6
SB		 575 __le32 rxMode; /* VMXNET3_RXM_xxx */
576 __le16 mfTableLen; /* size of the multicast filter table */
577 __le16 _pad1;
578 __le64 mfTablePA; /* PA of the multicast filters table */
579 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
d1a890fa
SB		 580};
581
582
583#define VMXNET3_PM_MAX_FILTERS 6
584#define VMXNET3_PM_MAX_PATTERN_SIZE 128
585#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
586
3843e515
HH		 587#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
588#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
589 * filters */
d1a890fa
SB		 590
591
592struct Vmxnet3_PM_PktFilter {
593 u8 maskSize;
594 u8 patternSize;
595 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
596 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
597 u8 pad[6];
598};
599
600
601struct Vmxnet3_PMConf {
115924b6 602 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
d1a890fa
SB		 603 u8 numFilters;
604 u8 pad[5];
605 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
606};
607
608
609struct Vmxnet3_VariableLenConfDesc {
115924b6
SB		 610 __le32 confVer;
611 __le32 confLen;
612 __le64 confPA;
d1a890fa
SB		 613};
614
615
616struct Vmxnet3_TxQueueDesc {
617 struct Vmxnet3_TxQueueCtrl ctrl;
618 struct Vmxnet3_TxQueueConf conf;
619
620 /* Driver read after a GET command */
621 struct Vmxnet3_QueueStatus status;
622 struct UPT1_TxStats stats;
623 u8 _pad[88]; /* 128 aligned */
624};
625
626
627struct Vmxnet3_RxQueueDesc {
628 struct Vmxnet3_RxQueueCtrl ctrl;
629 struct Vmxnet3_RxQueueConf conf;
630 /* Driver read after a GET commad */
631 struct Vmxnet3_QueueStatus status;
632 struct UPT1_RxStats stats;
633 u8 __pad[88]; /* 128 aligned */
634};
635
f35c7480
SK		 636struct Vmxnet3_SetPolling {
637 u8 enablePolling;
638};
639
640/* If the command data <= 16 bytes, use the shared memory directly.
641 * otherwise, use variable length configuration descriptor.
642 */
643union Vmxnet3_CmdInfo {
644 struct Vmxnet3_VariableLenConfDesc varConf;
645 struct Vmxnet3_SetPolling setPolling;
646 __le64 data[2];
647};
d1a890fa
SB		 648
649struct Vmxnet3_DSDevRead {
650 /* read-only region for device, read by dev in response to a SET cmd */
651 struct Vmxnet3_MiscConf misc;
652 struct Vmxnet3_IntrConf intrConf;
653 struct Vmxnet3_RxFilterConf rxFilterConf;
654 struct Vmxnet3_VariableLenConfDesc rssConfDesc;
655 struct Vmxnet3_VariableLenConfDesc pmConfDesc;
656 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
657};
658
659/* All structures in DriverShared are padded to multiples of 8 bytes */
660struct Vmxnet3_DriverShared {
115924b6 661 __le32 magic;
d1a890fa 662 /* make devRead start at 64bit boundaries */
115924b6
SB		 663 __le32 pad;
664 struct Vmxnet3_DSDevRead devRead;
665 __le32 ecr;
f35c7480
SK		 666 __le32 reserved;
667 union {
668 __le32 reserved1[4];
669 union Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of
670 * executing the relevant
671 * command
672 */
673 } cu;
d1a890fa
SB		 674};
675
676
677#define VMXNET3_ECR_RQERR (1 << 0)
678#define VMXNET3_ECR_TQERR (1 << 1)
679#define VMXNET3_ECR_LINK (1 << 2)
680#define VMXNET3_ECR_DIC (1 << 3)
681#define VMXNET3_ECR_DEBUG (1 << 4)
682
683/* flip the gen bit of a ring */
684#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
685
686/* only use this if moving the idx won't affect the gen bit */
687#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
688 do {\
689 (idx)++;\
690 if (unlikely((idx) == (ring_size))) {\
691 (idx) = 0;\
692 } \
693 } while (0)
694
695#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
696 (vfTable[vid >> 5] |= (1 << (vid & 31)))
697#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
698 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
699
700#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
701 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
702
703#define VMXNET3_MAX_MTU 9000
704#define VMXNET3_MIN_MTU 60
705
706#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
707#define VMXNET3_LINK_DOWN 0
708
709#endif /* _VMXNET3_DEFS_H_ */
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