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bdcd8170 KV |
1 | /* |
2 | * Copyright (c) 2004-2010 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef TARGET_H | |
18 | #define TARGET_H | |
19 | ||
20 | #define AR6003_BOARD_DATA_SZ 1024 | |
21 | #define AR6003_BOARD_EXT_DATA_SZ 768 | |
22 | ||
d5720e59 | 23 | #define AR6004_BOARD_DATA_SZ 6144 |
31024d99 KF |
24 | #define AR6004_BOARD_EXT_DATA_SZ 0 |
25 | ||
bdcd8170 KV |
26 | #define RESET_CONTROL_ADDRESS 0x00000000 |
27 | #define RESET_CONTROL_COLD_RST 0x00000100 | |
28 | #define RESET_CONTROL_MBOX_RST 0x00000004 | |
29 | ||
30 | #define CPU_CLOCK_STANDARD_S 0 | |
31 | #define CPU_CLOCK_STANDARD 0x00000003 | |
32 | #define CPU_CLOCK_ADDRESS 0x00000020 | |
33 | ||
34 | #define CLOCK_CONTROL_ADDRESS 0x00000028 | |
35 | #define CLOCK_CONTROL_LF_CLK32_S 2 | |
36 | #define CLOCK_CONTROL_LF_CLK32 0x00000004 | |
37 | ||
38 | #define SYSTEM_SLEEP_ADDRESS 0x000000c4 | |
39 | #define SYSTEM_SLEEP_DISABLE_S 0 | |
40 | #define SYSTEM_SLEEP_DISABLE 0x00000001 | |
41 | ||
42 | #define LPO_CAL_ADDRESS 0x000000e0 | |
43 | #define LPO_CAL_ENABLE_S 20 | |
44 | #define LPO_CAL_ENABLE 0x00100000 | |
45 | ||
46 | #define GPIO_PIN10_ADDRESS 0x00000050 | |
47 | #define GPIO_PIN11_ADDRESS 0x00000054 | |
48 | #define GPIO_PIN12_ADDRESS 0x00000058 | |
49 | #define GPIO_PIN13_ADDRESS 0x0000005c | |
50 | ||
51 | #define HOST_INT_STATUS_ADDRESS 0x00000400 | |
52 | #define HOST_INT_STATUS_ERROR_S 7 | |
53 | #define HOST_INT_STATUS_ERROR 0x00000080 | |
54 | ||
55 | #define HOST_INT_STATUS_CPU_S 6 | |
56 | #define HOST_INT_STATUS_CPU 0x00000040 | |
57 | ||
58 | #define HOST_INT_STATUS_COUNTER_S 4 | |
59 | #define HOST_INT_STATUS_COUNTER 0x00000010 | |
60 | ||
61 | #define CPU_INT_STATUS_ADDRESS 0x00000401 | |
62 | ||
63 | #define ERROR_INT_STATUS_ADDRESS 0x00000402 | |
64 | #define ERROR_INT_STATUS_WAKEUP_S 2 | |
65 | #define ERROR_INT_STATUS_WAKEUP 0x00000004 | |
66 | ||
67 | #define ERROR_INT_STATUS_RX_UNDERFLOW_S 1 | |
68 | #define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002 | |
69 | ||
70 | #define ERROR_INT_STATUS_TX_OVERFLOW_S 0 | |
71 | #define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001 | |
72 | ||
73 | #define COUNTER_INT_STATUS_ADDRESS 0x00000403 | |
74 | #define COUNTER_INT_STATUS_COUNTER_S 0 | |
75 | #define COUNTER_INT_STATUS_COUNTER 0x000000ff | |
76 | ||
77 | #define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 | |
78 | ||
79 | #define INT_STATUS_ENABLE_ADDRESS 0x00000418 | |
80 | #define INT_STATUS_ENABLE_ERROR_S 7 | |
81 | #define INT_STATUS_ENABLE_ERROR 0x00000080 | |
82 | ||
83 | #define INT_STATUS_ENABLE_CPU_S 6 | |
84 | #define INT_STATUS_ENABLE_CPU 0x00000040 | |
85 | ||
86 | #define INT_STATUS_ENABLE_INT_S 5 | |
87 | #define INT_STATUS_ENABLE_INT 0x00000020 | |
88 | #define INT_STATUS_ENABLE_COUNTER_S 4 | |
89 | #define INT_STATUS_ENABLE_COUNTER 0x00000010 | |
90 | ||
91 | #define INT_STATUS_ENABLE_MBOX_DATA_S 0 | |
92 | #define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f | |
93 | ||
94 | #define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 | |
95 | #define CPU_INT_STATUS_ENABLE_BIT_S 0 | |
96 | #define CPU_INT_STATUS_ENABLE_BIT 0x000000ff | |
97 | ||
98 | #define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a | |
99 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S 1 | |
100 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002 | |
101 | ||
102 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0 | |
103 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001 | |
104 | ||
105 | #define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b | |
106 | #define COUNTER_INT_STATUS_ENABLE_BIT_S 0 | |
107 | #define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff | |
108 | ||
109 | #define COUNT_ADDRESS 0x00000420 | |
110 | ||
111 | #define COUNT_DEC_ADDRESS 0x00000440 | |
112 | ||
113 | #define WINDOW_DATA_ADDRESS 0x00000474 | |
114 | #define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 | |
115 | #define WINDOW_READ_ADDR_ADDRESS 0x0000047c | |
116 | #define CPU_DBG_SEL_ADDRESS 0x00000483 | |
117 | #define CPU_DBG_ADDRESS 0x00000484 | |
118 | ||
119 | #define LOCAL_SCRATCH_ADDRESS 0x000000c0 | |
120 | #define ATH6KL_OPTION_SLEEP_DISABLE 0x08 | |
121 | ||
122 | #define RTC_BASE_ADDRESS 0x00004000 | |
123 | #define GPIO_BASE_ADDRESS 0x00014000 | |
124 | #define MBOX_BASE_ADDRESS 0x00018000 | |
125 | #define ANALOG_INTF_BASE_ADDRESS 0x0001c000 | |
126 | ||
127 | /* real name of the register is unknown */ | |
128 | #define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284) | |
129 | ||
130 | #define SM(f, v) (((v) << f##_S) & f) | |
131 | #define MS(f, v) (((v) & f) >> f##_S) | |
132 | ||
133 | /* | |
134 | * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the | |
135 | * host_interest structure. | |
136 | * | |
137 | * Host Interest is shared between Host and Target in order to coordinate | |
138 | * between the two, and is intended to remain constant (with additions only | |
139 | * at the end). | |
140 | */ | |
31024d99 KF |
141 | #define ATH6KL_AR6003_HI_START_ADDR 0x00540600 |
142 | #define ATH6KL_AR6004_HI_START_ADDR 0x00400800 | |
bdcd8170 KV |
143 | |
144 | /* | |
145 | * These are items that the Host may need to access | |
146 | * via BMI or via the Diagnostic Window. The position | |
147 | * of items in this structure must remain constant. | |
148 | * across firmware revisions! | |
149 | * | |
150 | * Types for each item must be fixed size across target and host platforms. | |
151 | * The structure is used only to calculate offset for each register with | |
152 | * HI_ITEM() macro, no values are stored to it. | |
153 | * | |
154 | * More items may be added at the end. | |
155 | */ | |
156 | struct host_interest { | |
157 | /* | |
158 | * Pointer to application-defined area, if any. | |
159 | * Set by Target application during startup. | |
160 | */ | |
161 | u32 hi_app_host_interest; /* 0x00 */ | |
162 | ||
163 | /* Pointer to register dump area, valid after Target crash. */ | |
164 | u32 hi_failure_state; /* 0x04 */ | |
165 | ||
166 | /* Pointer to debug logging header */ | |
167 | u32 hi_dbglog_hdr; /* 0x08 */ | |
168 | ||
169 | u32 hi_unused1; /* 0x0c */ | |
170 | ||
171 | /* | |
172 | * General-purpose flag bits, similar to ATH6KL_OPTION_* flags. | |
173 | * Can be used by application rather than by OS. | |
174 | */ | |
175 | u32 hi_option_flag; /* 0x10 */ | |
176 | ||
177 | /* | |
178 | * Boolean that determines whether or not to | |
179 | * display messages on the serial port. | |
180 | */ | |
181 | u32 hi_serial_enable; /* 0x14 */ | |
182 | ||
183 | /* Start address of DataSet index, if any */ | |
184 | u32 hi_dset_list_head; /* 0x18 */ | |
185 | ||
186 | /* Override Target application start address */ | |
187 | u32 hi_app_start; /* 0x1c */ | |
188 | ||
189 | /* Clock and voltage tuning */ | |
190 | u32 hi_skip_clock_init; /* 0x20 */ | |
191 | u32 hi_core_clock_setting; /* 0x24 */ | |
192 | u32 hi_cpu_clock_setting; /* 0x28 */ | |
193 | u32 hi_system_sleep_setting; /* 0x2c */ | |
194 | u32 hi_xtal_control_setting; /* 0x30 */ | |
195 | u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ | |
196 | u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ | |
197 | u32 hi_ref_voltage_trim_setting; /* 0x3c */ | |
198 | u32 hi_clock_info; /* 0x40 */ | |
199 | ||
200 | /* | |
201 | * Flash configuration overrides, used only | |
202 | * when firmware is not executing from flash. | |
203 | * (When using flash, modify the global variables | |
204 | * with equivalent names.) | |
205 | */ | |
206 | u32 hi_bank0_addr_value; /* 0x44 */ | |
207 | u32 hi_bank0_read_value; /* 0x48 */ | |
208 | u32 hi_bank0_write_value; /* 0x4c */ | |
209 | u32 hi_bank0_config_value; /* 0x50 */ | |
210 | ||
211 | /* Pointer to Board Data */ | |
212 | u32 hi_board_data; /* 0x54 */ | |
213 | u32 hi_board_data_initialized; /* 0x58 */ | |
214 | ||
215 | u32 hi_dset_ram_index_tbl; /* 0x5c */ | |
216 | ||
217 | u32 hi_desired_baud_rate; /* 0x60 */ | |
218 | u32 hi_dbglog_config; /* 0x64 */ | |
219 | u32 hi_end_ram_reserve_sz; /* 0x68 */ | |
220 | u32 hi_mbox_io_block_sz; /* 0x6c */ | |
221 | ||
222 | u32 hi_num_bpatch_streams; /* 0x70 -- unused */ | |
223 | u32 hi_mbox_isr_yield_limit; /* 0x74 */ | |
224 | ||
225 | u32 hi_refclk_hz; /* 0x78 */ | |
226 | u32 hi_ext_clk_detected; /* 0x7c */ | |
227 | u32 hi_dbg_uart_txpin; /* 0x80 */ | |
228 | u32 hi_dbg_uart_rxpin; /* 0x84 */ | |
229 | u32 hi_hci_uart_baud; /* 0x88 */ | |
230 | u32 hi_hci_uart_pin_assignments; /* 0x8C */ | |
231 | /* | |
232 | * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts | |
233 | * pin | |
234 | */ | |
235 | u32 hi_hci_uart_baud_scale_val; /* 0x90 */ | |
236 | u32 hi_hci_uart_baud_step_val; /* 0x94 */ | |
237 | ||
238 | u32 hi_allocram_start; /* 0x98 */ | |
239 | u32 hi_allocram_sz; /* 0x9c */ | |
240 | u32 hi_hci_bridge_flags; /* 0xa0 */ | |
241 | u32 hi_hci_uart_support_pins; /* 0xa4 */ | |
242 | /* | |
243 | * NOTE: byte [0] = RESET pin (bit 7 is polarity), | |
244 | * bytes[1]..bytes[3] are for future use | |
245 | */ | |
246 | u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ | |
247 | /* | |
248 | * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high | |
249 | * [31:16]: wakeup timeout in ms | |
250 | */ | |
251 | ||
252 | /* Pointer to extended board data */ | |
253 | u32 hi_board_ext_data; /* 0xac */ | |
254 | u32 hi_board_ext_data_config; /* 0xb0 */ | |
255 | ||
256 | /* | |
257 | * Bit [0] : valid | |
258 | * Bit[31:16: size | |
259 | */ | |
260 | /* | |
261 | * hi_reset_flag is used to do some stuff when target reset. | |
262 | * such as restore app_start after warm reset or | |
263 | * preserve host Interest area, or preserve ROM data, literals etc. | |
264 | */ | |
265 | u32 hi_reset_flag; /* 0xb4 */ | |
266 | /* indicate hi_reset_flag is valid */ | |
267 | u32 hi_reset_flag_valid; /* 0xb8 */ | |
268 | u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ | |
269 | /* | |
270 | * 0xbc - [31:0]: idle timeout in ms | |
271 | */ | |
272 | /* ACS flags */ | |
273 | u32 hi_acs_flags; /* 0xc0 */ | |
274 | u32 hi_console_flags; /* 0xc4 */ | |
275 | u32 hi_nvram_state; /* 0xc8 */ | |
276 | u32 hi_option_flag2; /* 0xcc */ | |
277 | ||
278 | /* If non-zero, override values sent to Host in WMI_READY event. */ | |
279 | u32 hi_sw_version_override; /* 0xd0 */ | |
280 | u32 hi_abi_version_override; /* 0xd4 */ | |
281 | ||
282 | /* | |
283 | * Percentage of high priority RX traffic to total expected RX traffic - | |
284 | * applicable only to ar6004 | |
285 | */ | |
286 | u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ | |
287 | ||
288 | /* test applications flags */ | |
289 | u32 hi_test_apps_related ; /* 0xdc */ | |
290 | /* location of test script */ | |
291 | u32 hi_ota_testscript; /* 0xe0 */ | |
292 | /* location of CAL data */ | |
293 | u32 hi_cal_data; /* 0xe4 */ | |
294 | /* Number of packet log buffers */ | |
295 | u32 hi_pktlog_num_buffers; /* 0xe8 */ | |
296 | ||
297 | } __packed; | |
298 | ||
299 | #define HI_ITEM(item) offsetof(struct host_interest, item) | |
300 | ||
301 | #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 | |
302 | ||
303 | #define HI_OPTION_FW_MODE_IBSS 0x0 | |
304 | #define HI_OPTION_FW_MODE_BSS_STA 0x1 | |
305 | #define HI_OPTION_FW_MODE_AP 0x2 | |
306 | ||
6bbc7c35 JM |
307 | #define HI_OPTION_FW_SUBMODE_NONE 0x0 |
308 | #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 | |
309 | #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 | |
310 | #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 | |
311 | ||
bdcd8170 KV |
312 | #define HI_OPTION_NUM_DEV_SHIFT 0x9 |
313 | ||
314 | #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 | |
315 | ||
316 | /* Fw Mode/SubMode Mask | |
317 | |------------------------------------------------------------------------------| | |
318 | | SUB | SUB | SUB | SUB | | | | | |
319 | | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0| | |
320 | | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) | |
321 | |------------------------------------------------------------------------------| | |
322 | */ | |
7b85832d | 323 | #define HI_OPTION_FW_MODE_BITS 0x2 |
bdcd8170 | 324 | #define HI_OPTION_FW_MODE_SHIFT 0xC |
7b85832d VT |
325 | |
326 | #define HI_OPTION_FW_SUBMODE_BITS 0x2 | |
6bbc7c35 | 327 | #define HI_OPTION_FW_SUBMODE_SHIFT 0x14 |
bdcd8170 KV |
328 | |
329 | /* Convert a Target virtual address into a Target physical address */ | |
31024d99 KF |
330 | #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) |
331 | #define AR6004_VTOP(vaddr) (vaddr) | |
332 | ||
333 | #define TARG_VTOP(target_type, vaddr) \ | |
334 | (((target_type) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ | |
335 | (((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0)) | |
bdcd8170 | 336 | |
bdf5396b KV |
337 | #define ATH6KL_FWLOG_PAYLOAD_SIZE 1500 |
338 | ||
bc07ddb2 KV |
339 | struct ath6kl_dbglog_buf { |
340 | __le32 next; | |
341 | __le32 buffer_addr; | |
342 | __le32 bufsize; | |
343 | __le32 length; | |
344 | __le32 count; | |
345 | __le32 free; | |
346 | } __packed; | |
347 | ||
348 | struct ath6kl_dbglog_hdr { | |
349 | __le32 dbuf_addr; | |
350 | __le32 dropped; | |
351 | } __packed; | |
352 | ||
bdcd8170 | 353 | #endif |