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ath9k_htc: Fix probe failure if CONFIG_USB_DEBUG enabled
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
f078f209
LR		 19#include <asm/unaligned.h>
20
af03abec 21#include "hw.h"
d70357d5 22#include "hw-ops.h"
cfe8cba9 23#include "rc.h"
b622a720 24#include "ar9003_mac.h"
f078f209 25
cbe61d8a 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 27
7322fd19
LR		 28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
d70357d5
LR		 45/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
57static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58{
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62}
63
64773964
LR		 64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
66{
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
68}
69
991312d8
LR		 70static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
71{
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
73 return;
74
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
76}
77
e36b27af
LR		 78static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
79{
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
82 return;
83
84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
85}
86
f1dc5600
S		 87/********************/
88/* Helper Functions */
89/********************/
f078f209 90
dfdac8ac 91static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 92{
b002a4a9 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 94 struct ath_common *common = ath9k_hw_common(ah);
95 unsigned int clockrate;
cbe61d8a 96
2660b81a 97 if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 98 clockrate = ATH9K_CLOCK_RATE_CCK;
99 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
100 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
101 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
102 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 103 else
dfdac8ac
FF		 104 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
105
106 if (conf_is_ht40(conf))
107 clockrate *= 2;
108
109 common->clockrate = clockrate;
f1dc5600
S		 110}
111
cbe61d8a 112static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 113{
dfdac8ac 114 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 115
dfdac8ac 116 return usecs * common->clockrate;
f1dc5600 117}
f078f209 118
0caa7b14 119bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 120{
121 int i;
122
0caa7b14
S		 123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
04bd4638 131
c46917bb
LR		 132 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 135
f1dc5600 136 return false;
f078f209 137}
7322fd19 138EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 139
140u32 ath9k_hw_reverse_bits(u32 val, u32 n)
141{
142 u32 retval;
143 int i;
144
145 for (i = 0, retval = 0; i < n; i++) {
146 retval = (retval << 1) | (val & 1);
147 val >>= 1;
148 }
149 return retval;
150}
151
cbe61d8a 152bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 153 u16 flags, u16 *low,
154 u16 *high)
f078f209 155{
2660b81a 156 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 157
f1dc5600
S		 158 if (flags & CHANNEL_5GHZ) {
159 *low = pCap->low_5ghz_chan;
160 *high = pCap->high_5ghz_chan;
161 return true;
f078f209 162 }
f1dc5600
S		 163 if ((flags & CHANNEL_2GHZ)) {
164 *low = pCap->low_2ghz_chan;
165 *high = pCap->high_2ghz_chan;
166 return true;
167 }
168 return false;
f078f209
LR		 169}
170
cbe61d8a 171u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 172 u8 phy, int kbps,
f1dc5600
S		 173 u32 frameLen, u16 rateix,
174 bool shortPreamble)
f078f209 175{
f1dc5600 176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 177
f1dc5600
S		 178 if (kbps == 0)
179 return 0;
f078f209 180
545750d3 181 switch (phy) {
46d14a58 182 case WLAN_RC_PHY_CCK:
f1dc5600 183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 184 if (shortPreamble)
f1dc5600
S		 185 phyTime >>= 1;
186 numBits = frameLen << 3;
187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
188 break;
46d14a58 189 case WLAN_RC_PHY_OFDM:
2660b81a 190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 197 } else if (ah->curchan &&
198 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME_HALF +
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
205 } else {
206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
207 numBits = OFDM_PLCP_BITS + (frameLen << 3);
208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
210 + (numSymbols * OFDM_SYMBOL_TIME);
211 }
212 break;
213 default:
c46917bb 214 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 215 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 216 txTime = 0;
217 break;
218 }
f078f209 219
f1dc5600
S		 220 return txTime;
221}
7322fd19 222EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 223
cbe61d8a 224void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 225 struct ath9k_channel *chan,
226 struct chan_centers *centers)
f078f209 227{
f1dc5600 228 int8_t extoff;
f078f209 229
f1dc5600
S		 230 if (!IS_CHAN_HT40(chan)) {
231 centers->ctl_center = centers->ext_center =
232 centers->synth_center = chan->channel;
233 return;
f078f209 234 }
f078f209 235
f1dc5600
S		 236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
237 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
238 centers->synth_center =
239 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
240 extoff = 1;
241 } else {
242 centers->synth_center =
243 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
244 extoff = -1;
245 }
f078f209 246
f1dc5600
S		 247 centers->ctl_center =
248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 249 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 250 centers->ext_center =
6420014c 251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 252}
253
f1dc5600
S		 254/******************/
255/* Chip Revisions */
256/******************/
257
cbe61d8a 258static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 259{
f1dc5600 260 u32 val;
f078f209 261
f1dc5600 262 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 263
f1dc5600
S		 264 if (val == 0xFF) {
265 val = REG_READ(ah, AR_SREV);
d535a42a
S		 266 ah->hw_version.macVersion =
267 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 269 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 270 } else {
271 if (!AR_SREV_9100(ah))
d535a42a 272 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 273
d535a42a 274 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 275
d535a42a 276 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 277 ah->is_pciexpress = true;
f1dc5600 278 }
f078f209
LR		 279}
280
f1dc5600
S		 281/************************************/
282/* HW Attach, Detach, Init Routines */
283/************************************/
284
cbe61d8a 285static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 286{
feed029c 287 if (AR_SREV_9100(ah))
f1dc5600 288 return;
f078f209 289
7d0d0df0
S		 290 ENABLE_REGWRITE_BUFFER(ah);
291
f1dc5600
S		 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 301
f1dc5600 302 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
7d0d0df0
S		 303
304 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 305}
306
1f3f0618 307/* This should work for all families including legacy */
cbe61d8a 308static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 309{
c46917bb 310 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 311 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 312 u32 regHold[2];
313 u32 patternData[4] = { 0x55555555,
314 0xaaaaaaaa,
315 0x66666666,
316 0x99999999 };
1f3f0618 317 int i, j, loop_max;
f078f209 318
1f3f0618
SB		 319 if (!AR_SREV_9300_20_OR_LATER(ah)) {
320 loop_max = 2;
321 regAddr[1] = AR_PHY_BASE + (8 << 2);
322 } else
323 loop_max = 1;
324
325 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 326 u32 addr = regAddr[i];
327 u32 wrData, rdData;
f078f209 328
f1dc5600
S		 329 regHold[i] = REG_READ(ah, addr);
330 for (j = 0; j < 0x100; j++) {
331 wrData = (j << 16) | j;
332 REG_WRITE(ah, addr, wrData);
333 rdData = REG_READ(ah, addr);
334 if (rdData != wrData) {
c46917bb
LR		 335 ath_print(common, ATH_DBG_FATAL,
336 "address test failed "
337 "addr: 0x%08x - wr:0x%08x != "
338 "rd:0x%08x\n",
339 addr, wrData, rdData);
f1dc5600
S		 340 return false;
341 }
342 }
343 for (j = 0; j < 4; j++) {
344 wrData = patternData[j];
345 REG_WRITE(ah, addr, wrData);
346 rdData = REG_READ(ah, addr);
347 if (wrData != rdData) {
c46917bb
LR		 348 ath_print(common, ATH_DBG_FATAL,
349 "address test failed "
350 "addr: 0x%08x - wr:0x%08x != "
351 "rd:0x%08x\n",
352 addr, wrData, rdData);
f1dc5600
S		 353 return false;
354 }
f078f209 355 }
f1dc5600 356 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 357 }
f1dc5600 358 udelay(100);
cbe61d8a 359
f078f209
LR		 360 return true;
361}
362
b8b0f377 363static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 364{
365 int i;
f078f209 366
2660b81a
S		 367 ah->config.dma_beacon_response_time = 2;
368 ah->config.sw_beacon_response_time = 10;
369 ah->config.additional_swba_backoff = 0;
370 ah->config.ack_6mb = 0x0;
371 ah->config.cwm_ignore_extcca = 0;
372 ah->config.pcie_powersave_enable = 0;
2660b81a 373 ah->config.pcie_clock_req = 0;
2660b81a
S		 374 ah->config.pcie_waen = 0;
375 ah->config.analog_shiftreg = 1;
03c72518 376 ah->config.enable_ani = true;
f078f209 377
f1dc5600 378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 379 ah->config.spurchans[i][0] = AR_NO_SPUR;
380 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 381 }
382
5ffaf8a3
LR		 383 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
384 ah->config.ht_enable = 1;
385 else
386 ah->config.ht_enable = 0;
387
0ce024cb 388 ah->config.rx_intr_mitigation = true;
6a0ec30a 389 ah->config.pcieSerDesWrite = true;
6158425b
LR		 390
391 /*
392 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
393 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
394 * This means we use it for all AR5416 devices, and the few
395 * minor PCI AR9280 devices out there.
396 *
397 * Serialization is required because these devices do not handle
398 * well the case of two concurrent reads/writes due to the latency
399 * involved. During one read/write another read/write can be issued
400 * on another CPU while the previous read/write may still be working
401 * on our hardware, if we hit this case the hardware poops in a loop.
402 * We prevent this by serializing reads and writes.
403 *
404 * This issue is not present on PCI-Express devices or pre-AR5416
405 * devices (legacy, 802.11abg).
406 */
407 if (num_possible_cpus() > 1)
2d6a5e95 408 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 409}
410
50aca25b 411static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 412{
608b88cb
LR		 413 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
414
415 regulatory->country_code = CTRY_DEFAULT;
416 regulatory->power_limit = MAX_RATE_POWER;
417 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
418
d535a42a 419 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 420 ah->hw_version.subvendorid = 0;
f078f209
LR		 421
422 ah->ah_flags = 0;
f078f209
LR		 423 if (!AR_SREV_9100(ah))
424 ah->ah_flags = AH_USE_EEPROM;
425
2660b81a 426 ah->atim_window = 0;
16f2411f
FF		 427 ah->sta_id1_defaults =
428 AR_STA_ID1_CRPT_MIC_ENABLE |
429 AR_STA_ID1_MCAST_KSRCH;
2660b81a
S		 430 ah->beacon_interval = 100;
431 ah->enable_32kHz_clock = DONT_USE_32KHZ;
432 ah->slottime = (u32) -1;
2660b81a 433 ah->globaltxtimeout = (u32) -1;
cbdec975 434 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 435}
436
cbe61d8a 437static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 438{
1510718d 439 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 440 u32 sum;
441 int i;
442 u16 eeval;
49101676 443 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 444
445 sum = 0;
446 for (i = 0; i < 3; i++) {
49101676 447 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 448 sum += eeval;
1510718d
LR		 449 common->macaddr[2 * i] = eeval >> 8;
450 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 451 }
d8baa939 452 if (sum == 0 || sum == 0xffff * 3)
f078f209 453 return -EADDRNOTAVAIL;
f078f209
LR		 454
455 return 0;
456}
457
f637cfd6 458static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 459{
f1dc5600 460 int ecode;
f078f209 461
527d485f
S		 462 if (!AR_SREV_9271(ah)) {
463 if (!ath9k_hw_chip_test(ah))
464 return -ENODEV;
465 }
f078f209 466
ebd5a14a
LR		 467 if (!AR_SREV_9300_20_OR_LATER(ah)) {
468 ecode = ar9002_hw_rf_claim(ah);
469 if (ecode != 0)
470 return ecode;
471 }
f078f209 472
f637cfd6 473 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 474 if (ecode != 0)
475 return ecode;
7d01b221 476
c46917bb
LR		 477 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
478 "Eeprom VER: %d, REV: %d\n",
479 ah->eep_ops->get_eeprom_ver(ah),
480 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 481
8fe65368
LR		 482 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
483 if (ecode) {
484 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
485 "Failed allocating banks for "
486 "external radio\n");
487 return ecode;
574d6b12 488 }
f078f209 489
f1dc5600
S		 490 if (!AR_SREV_9100(ah)) {
491 ath9k_hw_ani_setup(ah);
f637cfd6 492 ath9k_hw_ani_init(ah);
f078f209
LR		 493 }
494
f078f209
LR		 495 return 0;
496}
497
8525f280 498static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 499{
8525f280
LR		 500 if (AR_SREV_9300_20_OR_LATER(ah))
501 ar9003_hw_attach_ops(ah);
502 else
503 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 504}
505
d70357d5
LR		 506/* Called for all hardware families */
507static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 508{
c46917bb 509 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 510 int r = 0;
aa4058ae 511
bab1f62e
LR		 512 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
513 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 514
515 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 516 ath_print(common, ATH_DBG_FATAL,
517 "Couldn't reset chip\n");
95fafca2 518 return -EIO;
aa4058ae
LR		 519 }
520
bab1f62e
LR		 521 ath9k_hw_init_defaults(ah);
522 ath9k_hw_init_config(ah);
523
8525f280 524 ath9k_hw_attach_ops(ah);
d70357d5 525
9ecdef4b 526 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 527 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 528 return -EIO;
aa4058ae
LR		 529 }
530
531 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
532 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 533 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
534 !ah->is_pciexpress)) {
aa4058ae
LR		 535 ah->config.serialize_regmode =
536 SER_REG_MODE_ON;
537 } else {
538 ah->config.serialize_regmode =
539 SER_REG_MODE_OFF;
540 }
541 }
542
c46917bb 543 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 544 ah->config.serialize_regmode);
545
f4709fdf
LR		 546 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
547 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
548 else
549 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
550
d70357d5 551 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 552 ath_print(common, ATH_DBG_FATAL,
553 "Mac Chip Rev 0x%02x.%x is not supported by "
554 "this driver\n", ah->hw_version.macVersion,
555 ah->hw_version.macRev);
95fafca2 556 return -EOPNOTSUPP;
aa4058ae
LR		 557 }
558
0df13da4 559 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 560 ah->is_pciexpress = false;
561
aa4058ae 562 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 563 ath9k_hw_init_cal_settings(ah);
564
565 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 566 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 567 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 568 if (!AR_SREV_9300_20_OR_LATER(ah))
569 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae
LR		 570
571 ath9k_hw_init_mode_regs(ah);
572
9a658d2b
LR		 573 /*
574 * Read back AR_WA into a permanent copy and set bits 14 and 17.
575 * We need to do this to avoid RMW of this register. We cannot
576 * read the reg when chip is asleep.
577 */
578 ah->WARegVal = REG_READ(ah, AR_WA);
579 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
580 AR_WA_ASPM_TIMER_BASED_DISABLE);
581
aa4058ae 582 if (ah->is_pciexpress)
93b1b37f 583 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 584 else
585 ath9k_hw_disablepcie(ah);
586
d8f492b7
LR		 587 if (!AR_SREV_9300_20_OR_LATER(ah))
588 ar9002_hw_cck_chan14_spread(ah);
193cd458 589
f637cfd6 590 r = ath9k_hw_post_init(ah);
aa4058ae 591 if (r)
95fafca2 592 return r;
aa4058ae
LR		 593
594 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 595 r = ath9k_hw_fill_cap_info(ah);
596 if (r)
597 return r;
598
4f3acf81
LR		 599 r = ath9k_hw_init_macaddr(ah);
600 if (r) {
c46917bb
LR		 601 ath_print(common, ATH_DBG_FATAL,
602 "Failed to initialize MAC address\n");
95fafca2 603 return r;
f078f209
LR		 604 }
605
d7e7d229 606 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 607 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 608 else
2660b81a 609 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 610
aea702b7 611 ah->bb_watchdog_timeout_ms = 25;
f078f209 612
211f5859
LR		 613 common->state = ATH_HW_INITIALIZED;
614
4f3acf81 615 return 0;
f078f209
LR		 616}
617
d70357d5 618int ath9k_hw_init(struct ath_hw *ah)
f078f209 619{
d70357d5
LR		 620 int ret;
621 struct ath_common *common = ath9k_hw_common(ah);
f078f209 622
d70357d5
LR		 623 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
624 switch (ah->hw_version.devid) {
625 case AR5416_DEVID_PCI:
626 case AR5416_DEVID_PCIE:
627 case AR5416_AR9100_DEVID:
628 case AR9160_DEVID_PCI:
629 case AR9280_DEVID_PCI:
630 case AR9280_DEVID_PCIE:
631 case AR9285_DEVID_PCIE:
db3cc53a
SB		 632 case AR9287_DEVID_PCI:
633 case AR9287_DEVID_PCIE:
d70357d5 634 case AR2427_DEVID_PCIE:
db3cc53a 635 case AR9300_DEVID_PCIE:
d70357d5
LR		 636 break;
637 default:
638 if (common->bus_ops->ath_bus_type == ATH_USB)
639 break;
640 ath_print(common, ATH_DBG_FATAL,
641 "Hardware device ID 0x%04x not supported\n",
642 ah->hw_version.devid);
643 return -EOPNOTSUPP;
644 }
f078f209 645
d70357d5
LR		 646 ret = __ath9k_hw_init(ah);
647 if (ret) {
648 ath_print(common, ATH_DBG_FATAL,
649 "Unable to initialize hardware; "
650 "initialization status: %d\n", ret);
651 return ret;
652 }
f078f209 653
d70357d5 654 return 0;
f078f209 655}
d70357d5 656EXPORT_SYMBOL(ath9k_hw_init);
f078f209 657
cbe61d8a 658static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 659{
7d0d0df0
S		 660 ENABLE_REGWRITE_BUFFER(ah);
661
f1dc5600
S		 662 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
663 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 664
f1dc5600
S		 665 REG_WRITE(ah, AR_QOS_NO_ACK,
666 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
667 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
668 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
669
670 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
671 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
672 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
673 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
674 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 675
676 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 677}
678
cbe61d8a 679static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 680 struct ath9k_channel *chan)
f078f209 681{
64773964 682 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 683
d03a66c1 684 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 685
c75724d1
LR		 686 /* Switch the core clock for ar9271 to 117Mhz */
687 if (AR_SREV_9271(ah)) {
25e2ab17
S		 688 udelay(500);
689 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 690 }
691
f1dc5600
S		 692 udelay(RTC_PLL_SETTLE_DELAY);
693
694 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 695}
696
cbe61d8a 697static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 698 enum nl80211_iftype opmode)
f078f209 699{
152d530d 700 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 701 AR_IMR_TXURN |
702 AR_IMR_RXERR |
703 AR_IMR_RXORN |
704 AR_IMR_BCNMISC;
f078f209 705
66860240
VT		 706 if (AR_SREV_9300_20_OR_LATER(ah)) {
707 imr_reg |= AR_IMR_RXOK_HP;
708 if (ah->config.rx_intr_mitigation)
709 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
710 else
711 imr_reg |= AR_IMR_RXOK_LP;
f078f209 712
66860240
VT		 713 } else {
714 if (ah->config.rx_intr_mitigation)
715 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
716 else
717 imr_reg |= AR_IMR_RXOK;
718 }
f078f209 719
66860240
VT		 720 if (ah->config.tx_intr_mitigation)
721 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
722 else
723 imr_reg |= AR_IMR_TXOK;
f078f209 724
d97809db 725 if (opmode == NL80211_IFTYPE_AP)
152d530d 726 imr_reg |= AR_IMR_MIB;
f078f209 727
7d0d0df0
S		 728 ENABLE_REGWRITE_BUFFER(ah);
729
152d530d 730 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 731 ah->imrs2_reg |= AR_IMR_S2_GTT;
732 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 733
f1dc5600
S		 734 if (!AR_SREV_9100(ah)) {
735 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
736 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
737 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
738 }
66860240 739
7d0d0df0 740 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 741
66860240
VT		 742 if (AR_SREV_9300_20_OR_LATER(ah)) {
743 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
744 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
745 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
746 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
747 }
f078f209
LR		 748}
749
0005baf4 750static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 751{
0005baf4
FF		 752 u32 val = ath9k_hw_mac_to_clks(ah, us);
753 val = min(val, (u32) 0xFFFF);
754 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 755}
756
0005baf4 757static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 758{
0005baf4
FF		 759 u32 val = ath9k_hw_mac_to_clks(ah, us);
760 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
761 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
762}
763
764static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
765{
766 u32 val = ath9k_hw_mac_to_clks(ah, us);
767 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
768 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 769}
f1dc5600 770
cbe61d8a 771static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 772{
f078f209 773 if (tu > 0xFFFF) {
c46917bb
LR		 774 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
775 "bad global tx timeout %u\n", tu);
2660b81a 776 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 777 return false;
778 } else {
779 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 780 ah->globaltxtimeout = tu;
f078f209
LR		 781 return true;
782 }
783}
784
0005baf4 785void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 786{
0005baf4
FF		 787 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
788 int acktimeout;
e239d859 789 int slottime;
0005baf4
FF		 790 int sifstime;
791
c46917bb
LR		 792 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
793 ah->misc_mode);
f078f209 794
2660b81a 795 if (ah->misc_mode != 0)
f1dc5600 796 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 797 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 798
799 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
800 sifstime = 16;
801 else
802 sifstime = 10;
803
e239d859
FF		 804 /* As defined by IEEE 802.11-2007 17.3.8.6 */
805 slottime = ah->slottime + 3 * ah->coverage_class;
806 acktimeout = slottime + sifstime;
42c4568a
FF		 807
808 /*
809 * Workaround for early ACK timeouts, add an offset to match the
810 * initval's 64us ack timeout value.
811 * This was initially only meant to work around an issue with delayed
812 * BA frames in some implementations, but it has been found to fix ACK
813 * timeout issues in other cases as well.
814 */
815 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
816 acktimeout += 64 - sifstime - ah->slottime;
817
e239d859 818 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 819 ath9k_hw_set_ack_timeout(ah, acktimeout);
820 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 821 if (ah->globaltxtimeout != (u32) -1)
822 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 823}
0005baf4 824EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 825
285f2dda 826void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 827{
211f5859
LR		 828 struct ath_common *common = ath9k_hw_common(ah);
829
736b3a27 830 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 831 goto free_hw;
832
9ecdef4b 833 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 834
835free_hw:
8fe65368 836 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 837}
285f2dda 838EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 839
f1dc5600
S		 840/*******/
841/* INI */
842/*******/
843
8fe65368 844u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 845{
846 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
847
848 if (IS_CHAN_B(chan))
849 ctl |= CTL_11B;
850 else if (IS_CHAN_G(chan))
851 ctl |= CTL_11G;
852 else
853 ctl |= CTL_11A;
854
855 return ctl;
856}
857
f1dc5600
S		 858/****************************************/
859/* Reset and Channel Switching Routines */
860/****************************************/
f1dc5600 861
cbe61d8a 862static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 863{
57b32227 864 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 865 u32 regval;
866
7d0d0df0
S		 867 ENABLE_REGWRITE_BUFFER(ah);
868
d7e7d229
LR		 869 /*
870 * set AHB_MODE not to do cacheline prefetches
871 */
57b32227
FF		 872 if (!AR_SREV_9300_20_OR_LATER(ah)) {
873 regval = REG_READ(ah, AR_AHB_MODE);
874 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
875 }
f1dc5600 876
d7e7d229
LR		 877 /*
878 * let mac dma reads be in 128 byte chunks
879 */
f1dc5600
S		 880 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
881 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
882
7d0d0df0 883 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 884
d7e7d229
LR		 885 /*
886 * Restore TX Trigger Level to its pre-reset value.
887 * The initial value depends on whether aggregation is enabled, and is
888 * adjusted whenever underruns are detected.
889 */
57b32227
FF		 890 if (!AR_SREV_9300_20_OR_LATER(ah))
891 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 892
7d0d0df0 893 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 894
d7e7d229
LR		 895 /*
896 * let mac dma writes be in 128 byte chunks
897 */
f1dc5600
S		 898 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
899 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
900
d7e7d229
LR		 901 /*
902 * Setup receive FIFO threshold to hold off TX activities
903 */
f1dc5600
S		 904 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
905
57b32227
FF		 906 if (AR_SREV_9300_20_OR_LATER(ah)) {
907 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
908 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
909
910 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
911 ah->caps.rx_status_len);
912 }
913
d7e7d229
LR		 914 /*
915 * reduce the number of usable entries in PCU TXBUF to avoid
916 * wrap around issues.
917 */
f1dc5600 918 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 919 /* For AR9285 the number of Fifos are reduced to half.
920 * So set the usable tx buf size also to half to
921 * avoid data/delimiter underruns
922 */
f1dc5600
S		 923 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
924 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 925 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 926 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
927 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
928 }
744d4025 929
7d0d0df0 930 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 931
744d4025
VT		 932 if (AR_SREV_9300_20_OR_LATER(ah))
933 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 934}
935
cbe61d8a 936static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 937{
938 u32 val;
939
940 val = REG_READ(ah, AR_STA_ID1);
941 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
942 switch (opmode) {
d97809db 943 case NL80211_IFTYPE_AP:
f1dc5600
S		 944 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
945 | AR_STA_ID1_KSRCH_MODE);
946 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 947 break;
d97809db 948 case NL80211_IFTYPE_ADHOC:
9cb5412b 949 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 950 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
951 | AR_STA_ID1_KSRCH_MODE);
952 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 953 break;
d97809db 954 case NL80211_IFTYPE_STATION:
f1dc5600 955 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 956 break;
5f841b41
RM		 957 default:
958 if (ah->is_monitoring)
959 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
960 break;
f1dc5600
S		 961 }
962}
963
8fe65368
LR		 964void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
965 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 966{
967 u32 coef_exp, coef_man;
968
969 for (coef_exp = 31; coef_exp > 0; coef_exp--)
970 if ((coef_scaled >> coef_exp) & 0x1)
971 break;
972
973 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
974
975 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
976
977 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
978 *coef_exponent = coef_exp - 16;
979}
980
cbe61d8a 981static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 982{
983 u32 rst_flags;
984 u32 tmpReg;
985
70768496
S		 986 if (AR_SREV_9100(ah)) {
987 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
988 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
989 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
990 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
991 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
992 }
993
7d0d0df0
S		 994 ENABLE_REGWRITE_BUFFER(ah);
995
9a658d2b
LR		 996 if (AR_SREV_9300_20_OR_LATER(ah)) {
997 REG_WRITE(ah, AR_WA, ah->WARegVal);
998 udelay(10);
999 }
1000
f1dc5600
S		 1001 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1002 AR_RTC_FORCE_WAKE_ON_INT);
1003
1004 if (AR_SREV_9100(ah)) {
1005 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1006 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1007 } else {
1008 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1009 if (tmpReg &
1010 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1011 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1012 u32 val;
f1dc5600 1013 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1014
1015 val = AR_RC_HOSTIF;
1016 if (!AR_SREV_9300_20_OR_LATER(ah))
1017 val |= AR_RC_AHB;
1018 REG_WRITE(ah, AR_RC, val);
1019
1020 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1021 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1022
1023 rst_flags = AR_RTC_RC_MAC_WARM;
1024 if (type == ATH9K_RESET_COLD)
1025 rst_flags |= AR_RTC_RC_MAC_COLD;
1026 }
1027
d03a66c1 1028 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1029
1030 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1031
f1dc5600
S		 1032 udelay(50);
1033
d03a66c1 1034 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1035 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1036 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1037 "RTC stuck in MAC reset\n");
f1dc5600
S		 1038 return false;
1039 }
1040
1041 if (!AR_SREV_9100(ah))
1042 REG_WRITE(ah, AR_RC, 0);
1043
f1dc5600
S		 1044 if (AR_SREV_9100(ah))
1045 udelay(50);
1046
1047 return true;
1048}
1049
cbe61d8a 1050static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1051{
7d0d0df0
S		 1052 ENABLE_REGWRITE_BUFFER(ah);
1053
9a658d2b
LR		 1054 if (AR_SREV_9300_20_OR_LATER(ah)) {
1055 REG_WRITE(ah, AR_WA, ah->WARegVal);
1056 udelay(10);
1057 }
1058
f1dc5600
S		 1059 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1060 AR_RTC_FORCE_WAKE_ON_INT);
1061
42d5bc3f 1062 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1063 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1064
d03a66c1 1065 REG_WRITE(ah, AR_RTC_RESET, 0);
ee031112 1066 udelay(2);
1c29ce67 1067
7d0d0df0 1068 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1069
84e2169b
SB		 1070 if (!AR_SREV_9300_20_OR_LATER(ah))
1071 udelay(2);
1072
1073 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1074 REG_WRITE(ah, AR_RC, 0);
1075
d03a66c1 1076 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1077
1078 if (!ath9k_hw_wait(ah,
1079 AR_RTC_STATUS,
1080 AR_RTC_STATUS_M,
0caa7b14
S		 1081 AR_RTC_STATUS_ON,
1082 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1083 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1084 "RTC not waking up\n");
f1dc5600 1085 return false;
f078f209
LR		 1086 }
1087
f1dc5600
S		 1088 ath9k_hw_read_revisions(ah);
1089
1090 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1091}
1092
cbe61d8a 1093static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1094{
9a658d2b
LR		 1095 if (AR_SREV_9300_20_OR_LATER(ah)) {
1096 REG_WRITE(ah, AR_WA, ah->WARegVal);
1097 udelay(10);
1098 }
1099
f1dc5600
S		 1100 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1101 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1102
1103 switch (type) {
1104 case ATH9K_RESET_POWER_ON:
1105 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1106 case ATH9K_RESET_WARM:
1107 case ATH9K_RESET_COLD:
1108 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1109 default:
1110 return false;
1111 }
f078f209
LR		 1112}
1113
cbe61d8a 1114static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1115 struct ath9k_channel *chan)
f078f209 1116{
42abfbee 1117 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1118 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1119 return false;
1120 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1121 return false;
f078f209 1122
9ecdef4b 1123 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1124 return false;
f078f209 1125
2660b81a 1126 ah->chip_fullsleep = false;
f1dc5600 1127 ath9k_hw_init_pll(ah, chan);
f1dc5600 1128 ath9k_hw_set_rfmode(ah, chan);
f078f209 1129
f1dc5600 1130 return true;
f078f209
LR		 1131}
1132
cbe61d8a 1133static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1134 struct ath9k_channel *chan)
f078f209 1135{
608b88cb 1136 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1137 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1138 struct ieee80211_channel *channel = chan->chan;
8fe65368 1139 u32 qnum;
0a3b7bac 1140 int r;
f078f209
LR		 1141
1142 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1143 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1144 ath_print(common, ATH_DBG_QUEUE,
1145 "Transmit frames pending on "
1146 "queue %d\n", qnum);
f078f209
LR		 1147 return false;
1148 }
1149 }
1150
8fe65368 1151 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1152 ath_print(common, ATH_DBG_FATAL,
1153 "Could not kill baseband RX\n");
f078f209
LR		 1154 return false;
1155 }
1156
8fe65368 1157 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1158
8fe65368 1159 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1160 if (r) {
1161 ath_print(common, ATH_DBG_FATAL,
1162 "Failed to set channel\n");
1163 return false;
f078f209 1164 }
dfdac8ac 1165 ath9k_hw_set_clockrate(ah);
f078f209 1166
8fbff4b8 1167 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1168 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1169 channel->max_antenna_gain * 2,
1170 channel->max_power * 2,
1171 min((u32) MAX_RATE_POWER,
608b88cb 1172 (u32) regulatory->power_limit));
f078f209 1173
8fe65368 1174 ath9k_hw_rfbus_done(ah);
f078f209 1175
f1dc5600
S		 1176 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1177 ath9k_hw_set_delta_slope(ah, chan);
1178
8fe65368 1179 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1180
f1dc5600
S		 1181 return true;
1182}
1183
c9c99e5e 1184bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1185{
c9c99e5e
FF		 1186 int count = 50;
1187 u32 reg;
1188
e17f83ea 1189 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1190 return true;
1191
1192 do {
1193 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1194
c9c99e5e
FF		 1195 if ((reg & 0x7E7FFFEF) == 0x00702400)
1196 continue;
1197
1198 switch (reg & 0x7E000B00) {
1199 case 0x1E000000:
1200 case 0x52000B00:
1201 case 0x18000B00:
1202 continue;
1203 default:
1204 return true;
1205 }
1206 } while (count-- > 0);
3b319aae 1207
c9c99e5e 1208 return false;
3b319aae 1209}
c9c99e5e 1210EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1211
cbe61d8a 1212int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 1213 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
f078f209 1214{
1510718d 1215 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1216 u32 saveLedState;
2660b81a 1217 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1218 u32 saveDefAntenna;
1219 u32 macStaId1;
46fe782c 1220 u64 tsf = 0;
8fe65368 1221 int i, r;
f078f209 1222
43c27613
LR		 1223 ah->txchainmask = common->tx_chainmask;
1224 ah->rxchainmask = common->rx_chainmask;
f078f209 1225
9b9cc61c
VT		 1226 if (!ah->chip_fullsleep) {
1227 ath9k_hw_abortpcurecv(ah);
9cc2f3e8 1228 if (!ath9k_hw_stopdmarecv(ah)) {
9b9cc61c
VT		 1229 ath_print(common, ATH_DBG_XMIT,
1230 "Failed to stop receive dma\n");
9cc2f3e8
FF		 1231 bChannelChange = false;
1232 }
9b9cc61c
VT		 1233 }
1234
9ecdef4b 1235 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1236 return -EIO;
f078f209 1237
d9891c78 1238 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1239 ath9k_hw_getnf(ah, curchan);
1240
20bd2a09
FF		 1241 ah->caldata = caldata;
1242 if (caldata &&
1243 (chan->channel != caldata->channel ||
1244 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1245 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1246 /* Operating channel changed, reset channel calibration data */
1247 memset(caldata, 0, sizeof(*caldata));
1248 ath9k_init_nfcal_hist_buffer(ah, chan);
1249 }
1250
f078f209 1251 if (bChannelChange &&
2660b81a
S		 1252 (ah->chip_fullsleep != true) &&
1253 (ah->curchan != NULL) &&
1254 (chan->channel != ah->curchan->channel) &&
f078f209 1255 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1256 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
58d7e0f3 1257 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
f078f209 1258
25c56eec 1259 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1260 ath9k_hw_loadnf(ah, ah->curchan);
00c86590 1261 ath9k_hw_start_nfcal(ah, true);
c2ba3342
RM		 1262 if (AR_SREV_9271(ah))
1263 ar9002_hw_load_ani_reg(ah, chan);
ae8d2858 1264 return 0;
f078f209
LR		 1265 }
1266 }
1267
1268 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1269 if (saveDefAntenna == 0)
1270 saveDefAntenna = 1;
1271
1272 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1273
46fe782c 1274 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1275 if (AR_SREV_9100(ah) ||
1276 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1277 tsf = ath9k_hw_gettsf64(ah);
1278
f078f209
LR		 1279 saveLedState = REG_READ(ah, AR_CFG_LED) &
1280 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1281 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1282
1283 ath9k_hw_mark_phy_inactive(ah);
1284
05020d23 1285 /* Only required on the first reset */
d7e7d229
LR		 1286 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1287 REG_WRITE(ah,
1288 AR9271_RESET_POWER_DOWN_CONTROL,
1289 AR9271_RADIO_RF_RST);
1290 udelay(50);
1291 }
1292
f078f209 1293 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1294 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1295 return -EINVAL;
f078f209
LR		 1296 }
1297
05020d23 1298 /* Only required on the first reset */
d7e7d229
LR		 1299 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1300 ah->htc_reset_init = false;
1301 REG_WRITE(ah,
1302 AR9271_RESET_POWER_DOWN_CONTROL,
1303 AR9271_GATE_MAC_CTL);
1304 udelay(50);
1305 }
1306
46fe782c 1307 /* Restore TSF */
f860d526 1308 if (tsf)
46fe782c
S		 1309 ath9k_hw_settsf64(ah, tsf);
1310
7a37081e 1311 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1312 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1313
e9141f71
S		 1314 if (!AR_SREV_9300_20_OR_LATER(ah))
1315 ar9002_hw_enable_async_fifo(ah);
1316
25c56eec 1317 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1318 if (r)
1319 return r;
f078f209 1320
f860d526
FF		 1321 /*
1322 * Some AR91xx SoC devices frequently fail to accept TSF writes
1323 * right after the chip reset. When that happens, write a new
1324 * value after the initvals have been applied, with an offset
1325 * based on measured time difference
1326 */
1327 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1328 tsf += 1500;
1329 ath9k_hw_settsf64(ah, tsf);
1330 }
1331
0ced0e17
JM		 1332 /* Setup MFP options for CCMP */
1333 if (AR_SREV_9280_20_OR_LATER(ah)) {
1334 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1335 * frames when constructing CCMP AAD. */
1336 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1337 0xc7ff);
1338 ah->sw_mgmt_crypto = false;
1339 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1340 /* Disable hardware crypto for management frames */
1341 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1342 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1343 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1344 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1345 ah->sw_mgmt_crypto = true;
1346 } else
1347 ah->sw_mgmt_crypto = true;
1348
f078f209
LR		 1349 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1350 ath9k_hw_set_delta_slope(ah, chan);
1351
8fe65368 1352 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1353 ah->eep_ops->set_board_values(ah, chan);
a7765828 1354
6819d57f
S		 1355 ath9k_hw_set_operating_mode(ah, ah->opmode);
1356
7d0d0df0
S		 1357 ENABLE_REGWRITE_BUFFER(ah);
1358
1510718d
LR		 1359 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1360 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1361 | macStaId1
1362 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1363 | (ah->config.
60b67f51 1364 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1365 | ah->sta_id1_defaults);
13b81559 1366 ath_hw_setbssidmask(common);
f078f209 1367 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1368 ath9k_hw_write_associd(ah);
f078f209 1369 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1370 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1371
7d0d0df0 1372 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1373
8fe65368 1374 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1375 if (r)
1376 return r;
f078f209 1377
dfdac8ac
FF		 1378 ath9k_hw_set_clockrate(ah);
1379
7d0d0df0
S		 1380 ENABLE_REGWRITE_BUFFER(ah);
1381
f078f209
LR		 1382 for (i = 0; i < AR_NUM_DCU; i++)
1383 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1384
7d0d0df0 1385 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1386
2660b81a
S		 1387 ah->intr_txqs = 0;
1388 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1389 ath9k_hw_resettxqueue(ah, i);
1390
2660b81a 1391 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1392 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1393 ath9k_hw_init_qos(ah);
1394
2660b81a 1395 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1396 ath9k_enable_rfkill(ah);
3b319aae 1397
0005baf4 1398 ath9k_hw_init_global_settings(ah);
f078f209 1399
6c94fdc9 1400 if (!AR_SREV_9300_20_OR_LATER(ah)) {
e9141f71 1401 ar9002_hw_update_async_fifo(ah);
6c94fdc9 1402 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1403 }
1404
f078f209
LR		 1405 REG_WRITE(ah, AR_STA_ID1,
1406 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1407
1408 ath9k_hw_set_dma(ah);
1409
1410 REG_WRITE(ah, AR_OBS, 8);
1411
0ce024cb 1412 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1413 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1414 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1415 }
1416
7f62a136
VT		 1417 if (ah->config.tx_intr_mitigation) {
1418 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1419 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1420 }
1421
f078f209
LR		 1422 ath9k_hw_init_bb(ah, chan);
1423
ae8d2858 1424 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1425 return -EIO;
f078f209 1426
7d0d0df0 1427 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1428
8fe65368 1429 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1430 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1431
7d0d0df0 1432 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1433
d7e7d229
LR		 1434 /*
1435 * For big endian systems turn on swapping for descriptors
1436 */
f078f209
LR		 1437 if (AR_SREV_9100(ah)) {
1438 u32 mask;
1439 mask = REG_READ(ah, AR_CFG);
1440 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1441 ath_print(common, ATH_DBG_RESET,
04bd4638 1442 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1443 } else {
1444 mask =
1445 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1446 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1447 ath_print(common, ATH_DBG_RESET,
04bd4638 1448 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1449 }
1450 } else {
cbba8cd1
S		 1451 if (common->bus_ops->ath_bus_type == ATH_USB) {
1452 /* Configure AR9271 target WLAN */
1453 if (AR_SREV_9271(ah))
1454 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1455 else
1456 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1457 }
f078f209 1458#ifdef __BIG_ENDIAN
d7e7d229
LR		 1459 else
1460 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1461#endif
1462 }
1463
766ec4a9 1464 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1465 ath9k_hw_btcoex_enable(ah);
1466
00c86590 1467 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1468 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1469
ae8d2858 1470 return 0;
f078f209 1471}
7322fd19 1472EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1473
f1dc5600
S		 1474/******************************/
1475/* Power Management (Chipset) */
1476/******************************/
1477
42d5bc3f
LR		 1478/*
1479 * Notify Power Mgt is disabled in self-generated frames.
1480 * If requested, force chip to sleep.
1481 */
cbe61d8a 1482static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1483{
f1dc5600
S		 1484 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1485 if (setChip) {
42d5bc3f
LR		 1486 /*
1487 * Clear the RTC force wake bit to allow the
1488 * mac to go to sleep.
1489 */
f1dc5600
S		 1490 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1491 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1492 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1493 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1494
42d5bc3f 1495 /* Shutdown chip. Active low */
14b3af38 1496 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1497 REG_CLR_BIT(ah, (AR_RTC_RESET),
1498 AR_RTC_RESET_EN);
f1dc5600 1499 }
9a658d2b
LR		 1500
1501 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1502 if (AR_SREV_9300_20_OR_LATER(ah))
1503 REG_WRITE(ah, AR_WA,
1504 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1505}
1506
bbd79af5
LR		 1507/*
1508 * Notify Power Management is enabled in self-generating
1509 * frames. If request, set power mode of chip to
1510 * auto/normal. Duration in units of 128us (1/8 TU).
1511 */
cbe61d8a 1512static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1513{
f1dc5600
S		 1514 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1515 if (setChip) {
2660b81a 1516 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1517
f1dc5600 1518 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1519 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1520 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1521 AR_RTC_FORCE_WAKE_ON_INT);
1522 } else {
bbd79af5
LR		 1523 /*
1524 * Clear the RTC force wake bit to allow the
1525 * mac to go to sleep.
1526 */
f1dc5600
S		 1527 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1528 AR_RTC_FORCE_WAKE_EN);
f078f209 1529 }
f078f209 1530 }
9a658d2b
LR		 1531
1532 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1533 if (AR_SREV_9300_20_OR_LATER(ah))
1534 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1535}
1536
cbe61d8a 1537static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1538{
f1dc5600
S		 1539 u32 val;
1540 int i;
f078f209 1541
9a658d2b
LR		 1542 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1543 if (AR_SREV_9300_20_OR_LATER(ah)) {
1544 REG_WRITE(ah, AR_WA, ah->WARegVal);
1545 udelay(10);
1546 }
1547
f1dc5600
S		 1548 if (setChip) {
1549 if ((REG_READ(ah, AR_RTC_STATUS) &
1550 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1551 if (ath9k_hw_set_reset_reg(ah,
1552 ATH9K_RESET_POWER_ON) != true) {
1553 return false;
1554 }
e041228f
LR		 1555 if (!AR_SREV_9300_20_OR_LATER(ah))
1556 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1557 }
1558 if (AR_SREV_9100(ah))
1559 REG_SET_BIT(ah, AR_RTC_RESET,
1560 AR_RTC_RESET_EN);
f078f209 1561
f1dc5600
S		 1562 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1563 AR_RTC_FORCE_WAKE_EN);
1564 udelay(50);
f078f209 1565
f1dc5600
S		 1566 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1567 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1568 if (val == AR_RTC_STATUS_ON)
1569 break;
1570 udelay(50);
1571 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1572 AR_RTC_FORCE_WAKE_EN);
f078f209 1573 }
f1dc5600 1574 if (i == 0) {
c46917bb
LR		 1575 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1576 "Failed to wakeup in %uus\n",
1577 POWER_UP_TIME / 20);
f1dc5600 1578 return false;
f078f209 1579 }
f078f209
LR		 1580 }
1581
f1dc5600 1582 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1583
f1dc5600 1584 return true;
f078f209
LR		 1585}
1586
9ecdef4b 1587bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1588{
c46917bb 1589 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1590 int status = true, setChip = true;
f1dc5600
S		 1591 static const char *modes[] = {
1592 "AWAKE",
1593 "FULL-SLEEP",
1594 "NETWORK SLEEP",
1595 "UNDEFINED"
1596 };
f1dc5600 1597
cbdec975
GJ		 1598 if (ah->power_mode == mode)
1599 return status;
1600
c46917bb
LR		 1601 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1602 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1603
1604 switch (mode) {
1605 case ATH9K_PM_AWAKE:
1606 status = ath9k_hw_set_power_awake(ah, setChip);
1607 break;
1608 case ATH9K_PM_FULL_SLEEP:
1609 ath9k_set_power_sleep(ah, setChip);
2660b81a 1610 ah->chip_fullsleep = true;
f1dc5600
S		 1611 break;
1612 case ATH9K_PM_NETWORK_SLEEP:
1613 ath9k_set_power_network_sleep(ah, setChip);
1614 break;
f078f209 1615 default:
c46917bb
LR		 1616 ath_print(common, ATH_DBG_FATAL,
1617 "Unknown power mode %u\n", mode);
f078f209
LR		 1618 return false;
1619 }
2660b81a 1620 ah->power_mode = mode;
f1dc5600
S		 1621
1622 return status;
f078f209 1623}
7322fd19 1624EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1625
f1dc5600
S		 1626/*******************/
1627/* Beacon Handling */
1628/*******************/
1629
cbe61d8a 1630void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1631{
f078f209
LR		 1632 int flags = 0;
1633
2660b81a 1634 ah->beacon_interval = beacon_period;
f078f209 1635
7d0d0df0
S		 1636 ENABLE_REGWRITE_BUFFER(ah);
1637
2660b81a 1638 switch (ah->opmode) {
d97809db 1639 case NL80211_IFTYPE_STATION:
f078f209
LR		 1640 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1641 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1642 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1643 flags |= AR_TBTT_TIMER_EN;
1644 break;
d97809db 1645 case NL80211_IFTYPE_ADHOC:
9cb5412b 1646 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1647 REG_SET_BIT(ah, AR_TXCFG,
1648 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1649 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1650 TU_TO_USEC(next_beacon +
2660b81a
S		 1651 (ah->atim_window ? ah->
1652 atim_window : 1)));
f078f209 1653 flags |= AR_NDP_TIMER_EN;
d97809db 1654 case NL80211_IFTYPE_AP:
f078f209
LR		 1655 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1656 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1657 TU_TO_USEC(next_beacon -
2660b81a 1658 ah->config.
60b67f51 1659 dma_beacon_response_time));
f078f209
LR		 1660 REG_WRITE(ah, AR_NEXT_SWBA,
1661 TU_TO_USEC(next_beacon -
2660b81a 1662 ah->config.
60b67f51 1663 sw_beacon_response_time));
f078f209
LR		 1664 flags |=
1665 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1666 break;
d97809db 1667 default:
5f841b41
RM		 1668 if (ah->is_monitoring) {
1669 REG_WRITE(ah, AR_NEXT_TBTT_TIMER,
1670 TU_TO_USEC(next_beacon));
1671 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1672 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1673 flags |= AR_TBTT_TIMER_EN;
1674 break;
1675 }
c46917bb
LR		 1676 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1677 "%s: unsupported opmode: %d\n",
1678 __func__, ah->opmode);
d97809db
CM		 1679 return;
1680 break;
f078f209
LR		 1681 }
1682
1683 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1684 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1685 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1686 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1687
7d0d0df0 1688 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1689
f078f209
LR		 1690 beacon_period &= ~ATH9K_BEACON_ENA;
1691 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1692 ath9k_hw_reset_tsf(ah);
1693 }
1694
1695 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1696}
7322fd19 1697EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1698
cbe61d8a 1699void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1700 const struct ath9k_beacon_state *bs)
f078f209
LR		 1701{
1702 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1703 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1704 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1705
7d0d0df0
S		 1706 ENABLE_REGWRITE_BUFFER(ah);
1707
f078f209
LR		 1708 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1709
1710 REG_WRITE(ah, AR_BEACON_PERIOD,
1711 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1712 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1713 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1714
7d0d0df0 1715 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1716
f078f209
LR		 1717 REG_RMW_FIELD(ah, AR_RSSI_THR,
1718 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1719
1720 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1721
1722 if (bs->bs_sleepduration > beaconintval)
1723 beaconintval = bs->bs_sleepduration;
1724
1725 dtimperiod = bs->bs_dtimperiod;
1726 if (bs->bs_sleepduration > dtimperiod)
1727 dtimperiod = bs->bs_sleepduration;
1728
1729 if (beaconintval == dtimperiod)
1730 nextTbtt = bs->bs_nextdtim;
1731 else
1732 nextTbtt = bs->bs_nexttbtt;
1733
c46917bb
LR		 1734 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1735 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1736 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1737 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1738
7d0d0df0
S		 1739 ENABLE_REGWRITE_BUFFER(ah);
1740
f1dc5600
S		 1741 REG_WRITE(ah, AR_NEXT_DTIM,
1742 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1743 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1744
f1dc5600
S		 1745 REG_WRITE(ah, AR_SLEEP1,
1746 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1747 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1748
f1dc5600
S		 1749 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1750 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1751 else
1752 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1753
f1dc5600
S		 1754 REG_WRITE(ah, AR_SLEEP2,
1755 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1756
f1dc5600
S		 1757 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1758 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1759
7d0d0df0 1760 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1761
f1dc5600
S		 1762 REG_SET_BIT(ah, AR_TIMER_MODE,
1763 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1764 AR_DTIM_TIMER_EN);
f078f209 1765
4af9cf4f
S		 1766 /* TSF Out of Range Threshold */
1767 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 1768}
7322fd19 1769EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 1770
f1dc5600
S		 1771/*******************/
1772/* HW Capabilities */
1773/*******************/
1774
a9a29ce6 1775int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 1776{
2660b81a 1777 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 1778 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1779 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 1780 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 1781
f1dc5600 1782 u16 capField = 0, eeval;
754dc536 1783 u8 ant_div_ctl1;
f078f209 1784
f74df6fb 1785 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 1786 regulatory->current_rd = eeval;
f078f209 1787
f74df6fb 1788 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
e17f83ea 1789 if (AR_SREV_9285_12_OR_LATER(ah))
fec0de11 1790 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 1791 regulatory->current_rd_ext = eeval;
f078f209 1792
f74df6fb 1793 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 1794
2660b81a 1795 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 1796 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 1797 if (regulatory->current_rd == 0x64 ||
1798 regulatory->current_rd == 0x65)
1799 regulatory->current_rd += 5;
1800 else if (regulatory->current_rd == 0x41)
1801 regulatory->current_rd = 0x43;
c46917bb
LR		 1802 ath_print(common, ATH_DBG_REGULATORY,
1803 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 1804 }
f078f209 1805
f74df6fb 1806 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 1807 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1808 ath_print(common, ATH_DBG_FATAL,
1809 "no band has been marked as supported in EEPROM.\n");
1810 return -EINVAL;
1811 }
1812
d4659912
FF		 1813 if (eeval & AR5416_OPFLAGS_11A)
1814 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 1815
d4659912
FF		 1816 if (eeval & AR5416_OPFLAGS_11G)
1817 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 1818
f74df6fb 1819 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 1820 /*
1821 * For AR9271 we will temporarilly uses the rx chainmax as read from
1822 * the EEPROM.
1823 */
8147f5de 1824 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 1825 !(eeval & AR5416_OPFLAGS_11A) &&
1826 !(AR_SREV_9271(ah)))
1827 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 1828 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1829 else
d7e7d229 1830 /* Use rx_chainmask from EEPROM. */
8147f5de 1831 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 1832
7a37081e 1833 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 1834
f1dc5600
S		 1835 pCap->low_2ghz_chan = 2312;
1836 pCap->high_2ghz_chan = 2732;
f078f209 1837
f1dc5600
S		 1838 pCap->low_5ghz_chan = 4920;
1839 pCap->high_5ghz_chan = 6100;
f078f209 1840
ce2220d1
BR		 1841 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1842
2660b81a 1843 if (ah->config.ht_enable)
f1dc5600
S		 1844 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1845 else
1846 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 1847
f1dc5600
S		 1848 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1849 pCap->total_queues =
1850 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1851 else
1852 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 1853
f1dc5600
S		 1854 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1855 pCap->keycache_size =
1856 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1857 else
1858 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 1859
f4709fdf
LR		 1860 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1861 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1862 else
1863 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 1864
5b5fa355
S		 1865 if (AR_SREV_9271(ah))
1866 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 1867 else if (AR_DEVID_7010(ah))
1868 pCap->num_gpio_pins = AR7010_NUM_GPIO;
e17f83ea 1869 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 1870 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 1871 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 1872 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1873 else
1874 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 1875
f1dc5600
S		 1876 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1877 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1878 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1879 } else {
1880 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 1881 }
1882
f1dc5600
S		 1883 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1884
e97275cb 1885#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 1886 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1887 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1888 ah->rfkill_gpio =
1889 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1890 ah->rfkill_polarity =
1891 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 1892
1893 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 1894 }
f1dc5600 1895#endif
d5d1154f 1896 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 1897 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1898 else
1899 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 1900
e7594072 1901 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 1902 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1903 else
1904 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 1905
608b88cb 1906 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 1907 pCap->reg_cap =
1908 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1909 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1910 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1911 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 1912 } else {
f1dc5600
S		 1913 pCap->reg_cap =
1914 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1915 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 1916 }
f078f209 1917
ebb90cfc
SB		 1918 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1919 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1920 AR_SREV_5416(ah))
1921 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 1922
1923 pCap->num_antcfg_5ghz =
f74df6fb 1924 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 1925 pCap->num_antcfg_2ghz =
f74df6fb 1926 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 1927
7a37081e 1928 if (AR_SREV_9280_20_OR_LATER(ah) &&
a36cfbca 1929 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 1930 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1931 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 1932
8c8f9ba7 1933 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 1934 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1935 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 1936 } else {
766ec4a9 1937 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 1938 }
22f25d0d 1939 } else {
766ec4a9 1940 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 1941 }
a9a29ce6 1942
ceb26445 1943 if (AR_SREV_9300_20_OR_LATER(ah)) {
e5553724
VT		 1944 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
1945 ATH9K_HW_CAP_FASTCLOCK;
ceb26445
VT		 1946 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1947 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1948 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 1949 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 1950 pCap->txs_len = sizeof(struct ar9003_txs);
4935250a
FF		 1951 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1952 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 1953 } else {
1954 pCap->tx_desc_len = sizeof(struct ath_desc);
6b42e8d0
FF		 1955 if (AR_SREV_9280_20(ah) &&
1956 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1957 AR5416_EEP_MINOR_VER_16) ||
1958 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1959 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 1960 }
1adf02ff 1961
6c84ce08
VT		 1962 if (AR_SREV_9300_20_OR_LATER(ah))
1963 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1964
a42acef0 1965 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 1966 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1967
754dc536
VT		 1968 if (AR_SREV_9285(ah))
1969 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1970 ant_div_ctl1 =
1971 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1972 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1973 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1974 }
1975
a9a29ce6 1976 return 0;
f078f209
LR		 1977}
1978
f1dc5600
S		 1979/****************************/
1980/* GPIO / RFKILL / Antennae */
1981/****************************/
f078f209 1982
cbe61d8a 1983static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 1984 u32 gpio, u32 type)
1985{
1986 int addr;
1987 u32 gpio_shift, tmp;
f078f209 1988
f1dc5600
S		 1989 if (gpio > 11)
1990 addr = AR_GPIO_OUTPUT_MUX3;
1991 else if (gpio > 5)
1992 addr = AR_GPIO_OUTPUT_MUX2;
1993 else
1994 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 1995
f1dc5600 1996 gpio_shift = (gpio % 6) * 5;
f078f209 1997
f1dc5600
S		 1998 if (AR_SREV_9280_20_OR_LATER(ah)
1999 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2000 REG_RMW(ah, addr, (type << gpio_shift),
2001 (0x1f << gpio_shift));
f078f209 2002 } else {
f1dc5600
S		 2003 tmp = REG_READ(ah, addr);
2004 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2005 tmp &= ~(0x1f << gpio_shift);
2006 tmp |= (type << gpio_shift);
2007 REG_WRITE(ah, addr, tmp);
f078f209 2008 }
f078f209
LR		 2009}
2010
cbe61d8a 2011void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2012{
f1dc5600 2013 u32 gpio_shift;
f078f209 2014
9680e8a3 2015 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2016
88c1f4f6
S		 2017 if (AR_DEVID_7010(ah)) {
2018 gpio_shift = gpio;
2019 REG_RMW(ah, AR7010_GPIO_OE,
2020 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2021 (AR7010_GPIO_OE_MASK << gpio_shift));
2022 return;
2023 }
f078f209 2024
88c1f4f6 2025 gpio_shift = gpio << 1;
f1dc5600
S		 2026 REG_RMW(ah,
2027 AR_GPIO_OE_OUT,
2028 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2029 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2030}
7322fd19 2031EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2032
cbe61d8a 2033u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2034{
cb33c412
SB		 2035#define MS_REG_READ(x, y) \
2036 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2037
2660b81a 2038 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2039 return 0xffffffff;
f078f209 2040
88c1f4f6
S		 2041 if (AR_DEVID_7010(ah)) {
2042 u32 val;
2043 val = REG_READ(ah, AR7010_GPIO_IN);
2044 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2045 } else if (AR_SREV_9300_20_OR_LATER(ah))
783dfca1
FF		 2046 return MS_REG_READ(AR9300, gpio) != 0;
2047 else if (AR_SREV_9271(ah))
5b5fa355 2048 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2049 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2050 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2051 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2052 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2053 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2054 return MS_REG_READ(AR928X, gpio) != 0;
2055 else
2056 return MS_REG_READ(AR, gpio) != 0;
f078f209 2057}
7322fd19 2058EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2059
cbe61d8a 2060void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2061 u32 ah_signal_type)
f078f209 2062{
f1dc5600 2063 u32 gpio_shift;
f078f209 2064
88c1f4f6
S		 2065 if (AR_DEVID_7010(ah)) {
2066 gpio_shift = gpio;
2067 REG_RMW(ah, AR7010_GPIO_OE,
2068 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2069 (AR7010_GPIO_OE_MASK << gpio_shift));
2070 return;
2071 }
f078f209 2072
88c1f4f6 2073 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2074 gpio_shift = 2 * gpio;
f1dc5600
S		 2075 REG_RMW(ah,
2076 AR_GPIO_OE_OUT,
2077 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2078 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2079}
7322fd19 2080EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2081
cbe61d8a 2082void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2083{
88c1f4f6
S		 2084 if (AR_DEVID_7010(ah)) {
2085 val = val ? 0 : 1;
2086 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2087 AR_GPIO_BIT(gpio));
2088 return;
2089 }
2090
5b5fa355
S		 2091 if (AR_SREV_9271(ah))
2092 val = ~val;
2093
f1dc5600
S		 2094 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2095 AR_GPIO_BIT(gpio));
f078f209 2096}
7322fd19 2097EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2098
cbe61d8a 2099u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2100{
f1dc5600 2101 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2102}
7322fd19 2103EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2104
cbe61d8a 2105void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2106{
f1dc5600 2107 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2108}
7322fd19 2109EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2110
f1dc5600
S		 2111/*********************/
2112/* General Operation */
2113/*********************/
2114
cbe61d8a 2115u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2116{
f1dc5600
S		 2117 u32 bits = REG_READ(ah, AR_RX_FILTER);
2118 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2119
f1dc5600
S		 2120 if (phybits & AR_PHY_ERR_RADAR)
2121 bits |= ATH9K_RX_FILTER_PHYRADAR;
2122 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2123 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2124
f1dc5600 2125 return bits;
f078f209 2126}
7322fd19 2127EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2128
cbe61d8a 2129void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2130{
f1dc5600 2131 u32 phybits;
f078f209 2132
7d0d0df0
S		 2133 ENABLE_REGWRITE_BUFFER(ah);
2134
7ea310be
S		 2135 REG_WRITE(ah, AR_RX_FILTER, bits);
2136
f1dc5600
S		 2137 phybits = 0;
2138 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2139 phybits |= AR_PHY_ERR_RADAR;
2140 if (bits & ATH9K_RX_FILTER_PHYERR)
2141 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2142 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2143
f1dc5600
S		 2144 if (phybits)
2145 REG_WRITE(ah, AR_RXCFG,
2146 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2147 else
2148 REG_WRITE(ah, AR_RXCFG,
2149 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2150
2151 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2152}
7322fd19 2153EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2154
cbe61d8a 2155bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2156{
63a75b91
SB		 2157 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2158 return false;
2159
2160 ath9k_hw_init_pll(ah, NULL);
2161 return true;
f1dc5600 2162}
7322fd19 2163EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2164
cbe61d8a 2165bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2166{
9ecdef4b 2167 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2168 return false;
f078f209 2169
63a75b91
SB		 2170 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2171 return false;
2172
2173 ath9k_hw_init_pll(ah, NULL);
2174 return true;
f078f209 2175}
7322fd19 2176EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2177
8fbff4b8 2178void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2179{
608b88cb 2180 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2181 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2182 struct ieee80211_channel *channel = chan->chan;
f078f209 2183
608b88cb 2184 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2185
8fbff4b8 2186 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2187 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2188 channel->max_antenna_gain * 2,
2189 channel->max_power * 2,
2190 min((u32) MAX_RATE_POWER,
608b88cb 2191 (u32) regulatory->power_limit));
6f255425 2192}
7322fd19 2193EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2194
cbe61d8a 2195void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2196{
2660b81a 2197 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2198}
7322fd19 2199EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2200
cbe61d8a 2201void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2202{
f1dc5600
S		 2203 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2204 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2205}
7322fd19 2206EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2207
f2b2143e 2208void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2209{
1510718d
LR		 2210 struct ath_common *common = ath9k_hw_common(ah);
2211
2212 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2213 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2214 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2215}
7322fd19 2216EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2217
1c0fc65e
BP		 2218#define ATH9K_MAX_TSF_READ 10
2219
cbe61d8a 2220u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2221{
1c0fc65e
BP		 2222 u32 tsf_lower, tsf_upper1, tsf_upper2;
2223 int i;
2224
2225 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2226 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2227 tsf_lower = REG_READ(ah, AR_TSF_L32);
2228 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2229 if (tsf_upper2 == tsf_upper1)
2230 break;
2231 tsf_upper1 = tsf_upper2;
2232 }
f078f209 2233
1c0fc65e 2234 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2235
1c0fc65e 2236 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2237}
7322fd19 2238EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2239
cbe61d8a 2240void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2241{
27abe060 2242 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2243 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2244}
7322fd19 2245EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2246
cbe61d8a 2247void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2248{
f9b604f6
GJ		 2249 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2250 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2251 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2252 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2253
f1dc5600
S		 2254 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2255}
7322fd19 2256EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2257
54e4cec6 2258void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2259{
f1dc5600 2260 if (setting)
2660b81a 2261 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2262 else
2660b81a 2263 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2264}
7322fd19 2265EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2266
25c56eec 2267void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2268{
25c56eec 2269 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2270 u32 macmode;
2271
25c56eec 2272 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2273 macmode = AR_2040_JOINED_RX_CLEAR;
2274 else
2275 macmode = 0;
f078f209 2276
f1dc5600 2277 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2278}
ff155a45
VT		 2279
2280/* HW Generic timers configuration */
2281
2282static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2283{
2284 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2285 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2286 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2287 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2288 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2289 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2290 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2291 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2292 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2293 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2294 AR_NDP2_TIMER_MODE, 0x0002},
2295 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2296 AR_NDP2_TIMER_MODE, 0x0004},
2297 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2298 AR_NDP2_TIMER_MODE, 0x0008},
2299 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2300 AR_NDP2_TIMER_MODE, 0x0010},
2301 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2302 AR_NDP2_TIMER_MODE, 0x0020},
2303 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2304 AR_NDP2_TIMER_MODE, 0x0040},
2305 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2306 AR_NDP2_TIMER_MODE, 0x0080}
2307};
2308
2309/* HW generic timer primitives */
2310
2311/* compute and clear index of rightmost 1 */
2312static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2313{
2314 u32 b;
2315
2316 b = *mask;
2317 b &= (0-b);
2318 *mask &= ~b;
2319 b *= debruijn32;
2320 b >>= 27;
2321
2322 return timer_table->gen_timer_index[b];
2323}
2324
1773912b 2325u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2326{
2327 return REG_READ(ah, AR_TSF_L32);
2328}
7322fd19 2329EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2330
2331struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2332 void (*trigger)(void *),
2333 void (*overflow)(void *),
2334 void *arg,
2335 u8 timer_index)
2336{
2337 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2338 struct ath_gen_timer *timer;
2339
2340 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2341
2342 if (timer == NULL) {
c46917bb
LR		 2343 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2344 "Failed to allocate memory"
2345 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2346 return NULL;
2347 }
2348
2349 /* allocate a hardware generic timer slot */
2350 timer_table->timers[timer_index] = timer;
2351 timer->index = timer_index;
2352 timer->trigger = trigger;
2353 timer->overflow = overflow;
2354 timer->arg = arg;
2355
2356 return timer;
2357}
7322fd19 2358EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2359
cd9bf689
LR		 2360void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2361 struct ath_gen_timer *timer,
2362 u32 timer_next,
2363 u32 timer_period)
ff155a45
VT		 2364{
2365 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2366 u32 tsf;
2367
2368 BUG_ON(!timer_period);
2369
2370 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2371
2372 tsf = ath9k_hw_gettsf32(ah);
2373
c46917bb
LR		 2374 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2375 "curent tsf %x period %x"
2376 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2377
2378 /*
2379 * Pull timer_next forward if the current TSF already passed it
2380 * because of software latency
2381 */
2382 if (timer_next < tsf)
2383 timer_next = tsf + timer_period;
2384
2385 /*
2386 * Program generic timer registers
2387 */
2388 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2389 timer_next);
2390 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2391 timer_period);
2392 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2393 gen_tmr_configuration[timer->index].mode_mask);
2394
2395 /* Enable both trigger and thresh interrupt masks */
2396 REG_SET_BIT(ah, AR_IMR_S5,
2397 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2398 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2399}
7322fd19 2400EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2401
cd9bf689 2402void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2403{
2404 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2405
2406 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2407 (timer->index >= ATH_MAX_GEN_TIMER)) {
2408 return;
2409 }
2410
2411 /* Clear generic timer enable bits. */
2412 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2413 gen_tmr_configuration[timer->index].mode_mask);
2414
2415 /* Disable both trigger and thresh interrupt masks */
2416 REG_CLR_BIT(ah, AR_IMR_S5,
2417 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2418 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2419
2420 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2421}
7322fd19 2422EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2423
2424void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2425{
2426 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2427
2428 /* free the hardware generic timer slot */
2429 timer_table->timers[timer->index] = NULL;
2430 kfree(timer);
2431}
7322fd19 2432EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2433
2434/*
2435 * Generic Timer Interrupts handling
2436 */
2437void ath_gen_timer_isr(struct ath_hw *ah)
2438{
2439 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2440 struct ath_gen_timer *timer;
c46917bb 2441 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2442 u32 trigger_mask, thresh_mask, index;
2443
2444 /* get hardware generic timer interrupt status */
2445 trigger_mask = ah->intr_gen_timer_trigger;
2446 thresh_mask = ah->intr_gen_timer_thresh;
2447 trigger_mask &= timer_table->timer_mask.val;
2448 thresh_mask &= timer_table->timer_mask.val;
2449
2450 trigger_mask &= ~thresh_mask;
2451
2452 while (thresh_mask) {
2453 index = rightmost_index(timer_table, &thresh_mask);
2454 timer = timer_table->timers[index];
2455 BUG_ON(!timer);
c46917bb
LR		 2456 ath_print(common, ATH_DBG_HWTIMER,
2457 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2458 timer->overflow(timer->arg);
2459 }
2460
2461 while (trigger_mask) {
2462 index = rightmost_index(timer_table, &trigger_mask);
2463 timer = timer_table->timers[index];
2464 BUG_ON(!timer);
c46917bb
LR		 2465 ath_print(common, ATH_DBG_HWTIMER,
2466 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2467 timer->trigger(timer->arg);
2468 }
2469}
7322fd19 2470EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2471
05020d23
S		 2472/********/
2473/* HTC */
2474/********/
2475
2476void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2477{
2478 ah->htc_reset_init = true;
2479}
2480EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2481
2da4f01a
LR		 2482static struct {
2483 u32 version;
2484 const char * name;
2485} ath_mac_bb_names[] = {
2486 /* Devices with external radios */
2487 { AR_SREV_VERSION_5416_PCI, "5416" },
2488 { AR_SREV_VERSION_5416_PCIE, "5418" },
2489 { AR_SREV_VERSION_9100, "9100" },
2490 { AR_SREV_VERSION_9160, "9160" },
2491 /* Single-chip solutions */
2492 { AR_SREV_VERSION_9280, "9280" },
2493 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2494 { AR_SREV_VERSION_9287, "9287" },
2495 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2496 { AR_SREV_VERSION_9300, "9300" },
2da4f01a
LR		 2497};
2498
2499/* For devices with external radios */
2500static struct {
2501 u16 version;
2502 const char * name;
2503} ath_rf_names[] = {
2504 { 0, "5133" },
2505 { AR_RAD5133_SREV_MAJOR, "5133" },
2506 { AR_RAD5122_SREV_MAJOR, "5122" },
2507 { AR_RAD2133_SREV_MAJOR, "2133" },
2508 { AR_RAD2122_SREV_MAJOR, "2122" }
2509};
2510
2511/*
2512 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2513 */
f934c4d9 2514static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2515{
2516 int i;
2517
2518 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2519 if (ath_mac_bb_names[i].version == mac_bb_version) {
2520 return ath_mac_bb_names[i].name;
2521 }
2522 }
2523
2524 return "????";
2525}
2da4f01a
LR		 2526
2527/*
2528 * Return the RF name. "????" is returned if the RF is unknown.
2529 * Used for devices with external radios.
2530 */
f934c4d9 2531static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2532{
2533 int i;
2534
2535 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2536 if (ath_rf_names[i].version == rf_version) {
2537 return ath_rf_names[i].name;
2538 }
2539 }
2540
2541 return "????";
2542}
f934c4d9
LR		 2543
2544void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2545{
2546 int used;
2547
2548 /* chipsets >= AR9280 are single-chip */
7a37081e 2549 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 2550 used = snprintf(hw_name, len,
2551 "Atheros AR%s Rev:%x",
2552 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2553 ah->hw_version.macRev);
2554 }
2555 else {
2556 used = snprintf(hw_name, len,
2557 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2558 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2559 ah->hw_version.macRev,
2560 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2561 AR_RADIO_SREV_MAJOR)),
2562 ah->hw_version.phyRev);
2563 }
2564
2565 hw_name[used] = '\0';
2566}
2567EXPORT_SYMBOL(ath9k_hw_name);
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