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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
5ca06ebe 22#include <linux/etherdevice.h>
61b559de 23#include <linux/gpio.h>
f078f209
LR		 24#include <asm/unaligned.h>
25
af03abec 26#include "hw.h"
d70357d5 27#include "hw-ops.h"
b622a720 28#include "ar9003_mac.h"
f4701b5a 29#include "ar9003_mci.h"
362cd03f 30#include "ar9003_phy.h"
462e58f2 31#include "ath9k.h"
f078f209 32
cbe61d8a 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 34
7322fd19
LR		 35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
dfdac8ac 40static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 41{
dfdac8ac 42 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 43 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 44 unsigned int clockrate;
cbe61d8a 45
087b6ff6
FF		 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
e4744ec7 49 else if (!chan) /* should really check for CCK instead */
dfdac8ac 50 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 51 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 55 else
dfdac8ac
FF		 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
beae416b
MN		 58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
e4744ec7 61 if (IS_CHAN_HALF_RATE(chan))
906c7205 62 clockrate /= 2;
e4744ec7 63 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 64 clockrate /= 4;
65 }
66
dfdac8ac 67 common->clockrate = clockrate;
f1dc5600
S		 68}
69
cbe61d8a 70static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 71{
dfdac8ac 72 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 73
dfdac8ac 74 return usecs * common->clockrate;
f1dc5600 75}
f078f209 76
0caa7b14 77bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 78{
79 int i;
80
0caa7b14
S		 81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
04bd4638 89
d2182b69 90 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 93
f1dc5600 94 return false;
f078f209 95}
7322fd19 96EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 97
7c5adc8d
FF		 98void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100{
1a5e6326 101 hw_delay /= 10;
7c5adc8d
FF		 102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109}
110
0166b4be 111void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 112 int column, unsigned int *writecnt)
113{
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123}
124
a57cb45a
OR		 125void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
126{
127 u32 *tmp_reg_list, *tmp_data;
128 int i;
129
130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
131 if (!tmp_reg_list) {
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
133 return;
134 }
135
136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
137 if (!tmp_data) {
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
139 goto error_tmp_data;
140 }
141
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
144
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
146
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
149
150 kfree(tmp_data);
151error_tmp_data:
152 kfree(tmp_reg_list);
153}
154
f078f209
LR		 155u32 ath9k_hw_reverse_bits(u32 val, u32 n)
156{
157 u32 retval;
158 int i;
159
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
162 val >>= 1;
163 }
164 return retval;
165}
166
cbe61d8a 167u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 168 u8 phy, int kbps,
f1dc5600
S		 169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
f078f209 171{
f1dc5600 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 173
f1dc5600
S		 174 if (kbps == 0)
175 return 0;
f078f209 176
545750d3 177 switch (phy) {
46d14a58 178 case WLAN_RC_PHY_CCK:
f1dc5600 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 180 if (shortPreamble)
f1dc5600
S		 181 phyTime >>= 1;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
184 break;
46d14a58 185 case WLAN_RC_PHY_OFDM:
2660b81a 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_QUARTER
191 + OFDM_PREAMBLE_TIME_QUARTER
192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
196 numBits = OFDM_PLCP_BITS + (frameLen << 3);
197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
198 txTime = OFDM_SIFS_TIME_HALF +
199 OFDM_PREAMBLE_TIME_HALF
200 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
201 } else {
202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
203 numBits = OFDM_PLCP_BITS + (frameLen << 3);
204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
206 + (numSymbols * OFDM_SYMBOL_TIME);
207 }
208 break;
209 default:
3800276a
JP		 210 ath_err(ath9k_hw_common(ah),
211 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 212 txTime = 0;
213 break;
214 }
f078f209 215
f1dc5600
S		 216 return txTime;
217}
7322fd19 218EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 219
cbe61d8a 220void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 221 struct ath9k_channel *chan,
222 struct chan_centers *centers)
f078f209 223{
f1dc5600 224 int8_t extoff;
f078f209 225
f1dc5600
S		 226 if (!IS_CHAN_HT40(chan)) {
227 centers->ctl_center = centers->ext_center =
228 centers->synth_center = chan->channel;
229 return;
f078f209 230 }
f078f209 231
8896934c 232 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 233 centers->synth_center =
234 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
235 extoff = 1;
236 } else {
237 centers->synth_center =
238 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
239 extoff = -1;
240 }
f078f209 241
f1dc5600
S		 242 centers->ctl_center =
243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 244 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 245 centers->ext_center =
6420014c 246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 247}
248
f1dc5600
S		 249/******************/
250/* Chip Revisions */
251/******************/
252
50cf1121 253static bool ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 254{
50cf1121 255 u32 srev;
f1dc5600 256 u32 val;
f078f209 257
09c74f7b
FF		 258 if (ah->get_mac_revision)
259 ah->hw_version.macRev = ah->get_mac_revision();
260
ecb1d385
VT		 261 switch (ah->hw_version.devid) {
262 case AR5416_AR9100_DEVID:
263 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 break;
3762561a
GJ		 265 case AR9300_DEVID_AR9330:
266 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
09c74f7b 267 if (!ah->get_mac_revision) {
3762561a
GJ		 268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
270 }
50cf1121 271 return true;
ecb1d385
VT		 272 case AR9300_DEVID_AR9340:
273 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
50cf1121 274 return true;
813831dc
GJ		 275 case AR9300_DEVID_QCA955X:
276 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
50cf1121 277 return true;
e6b1e46e
SM		 278 case AR9300_DEVID_AR953X:
279 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
50cf1121 280 return true;
2131fabb
MP		 281 case AR9300_DEVID_QCA956X:
282 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
50cf1121 283 return true;
ecb1d385
VT		 284 }
285
50cf1121
TS		 286 srev = REG_READ(ah, AR_SREV);
287
288 if (srev == -EIO) {
289 ath_err(ath9k_hw_common(ah),
290 "Failed to read SREV register");
291 return false;
292 }
293
294 val = srev & AR_SREV_ID;
f078f209 295
f1dc5600 296 if (val == 0xFF) {
50cf1121 297 val = srev;
d535a42a
S		 298 ah->hw_version.macVersion =
299 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
300 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 301
77fac465 302 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 303 ah->is_pciexpress = true;
304 else
305 ah->is_pciexpress = (val &
306 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 307 } else {
308 if (!AR_SREV_9100(ah))
d535a42a 309 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 310
d535a42a 311 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 312
d535a42a 313 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 314 ah->is_pciexpress = true;
f1dc5600 315 }
50cf1121
TS		 316
317 return true;
f078f209
LR		 318}
319
f1dc5600
S		 320/************************************/
321/* HW Attach, Detach, Init Routines */
322/************************************/
323
cbe61d8a 324static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 325{
040b74f7 326 if (!AR_SREV_5416(ah))
f1dc5600 327 return;
f078f209 328
f1dc5600
S		 329 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
336 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
337 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 338
f1dc5600 339 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 340}
341
1f3f0618 342/* This should work for all families including legacy */
cbe61d8a 343static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 344{
c46917bb 345 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 346 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 347 u32 regHold[2];
07b2fa5a
JP		 348 static const u32 patternData[4] = {
349 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
350 };
1f3f0618 351 int i, j, loop_max;
f078f209 352
1f3f0618
SB		 353 if (!AR_SREV_9300_20_OR_LATER(ah)) {
354 loop_max = 2;
355 regAddr[1] = AR_PHY_BASE + (8 << 2);
356 } else
357 loop_max = 1;
358
359 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 360 u32 addr = regAddr[i];
361 u32 wrData, rdData;
f078f209 362
f1dc5600
S		 363 regHold[i] = REG_READ(ah, addr);
364 for (j = 0; j < 0x100; j++) {
365 wrData = (j << 16) | j;
366 REG_WRITE(ah, addr, wrData);
367 rdData = REG_READ(ah, addr);
368 if (rdData != wrData) {
3800276a
JP		 369 ath_err(common,
370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 addr, wrData, rdData);
f1dc5600
S		 372 return false;
373 }
374 }
375 for (j = 0; j < 4; j++) {
376 wrData = patternData[j];
377 REG_WRITE(ah, addr, wrData);
378 rdData = REG_READ(ah, addr);
379 if (wrData != rdData) {
3800276a
JP		 380 ath_err(common,
381 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
382 addr, wrData, rdData);
f1dc5600
S		 383 return false;
384 }
f078f209 385 }
f1dc5600 386 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 387 }
f1dc5600 388 udelay(100);
cbe61d8a 389
f078f209
LR		 390 return true;
391}
392
b8b0f377 393static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 394{
f57cf939
SM		 395 struct ath_common *common = ath9k_hw_common(ah);
396
689e756f
FF		 397 ah->config.dma_beacon_response_time = 1;
398 ah->config.sw_beacon_response_time = 6;
621a5f7a 399 ah->config.cwm_ignore_extcca = false;
2660b81a 400 ah->config.analog_shiftreg = 1;
f078f209 401
0ce024cb 402 ah->config.rx_intr_mitigation = true;
6158425b 403
a64e1a45
SM		 404 if (AR_SREV_9300_20_OR_LATER(ah)) {
405 ah->config.rimt_last = 500;
406 ah->config.rimt_first = 2000;
407 } else {
408 ah->config.rimt_last = 250;
409 ah->config.rimt_first = 700;
410 }
411
656cd75c
SM		 412 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
413 ah->config.pll_pwrsave = 7;
414
6158425b
LR		 415 /*
416 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
417 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
418 * This means we use it for all AR5416 devices, and the few
419 * minor PCI AR9280 devices out there.
420 *
421 * Serialization is required because these devices do not handle
422 * well the case of two concurrent reads/writes due to the latency
423 * involved. During one read/write another read/write can be issued
424 * on another CPU while the previous read/write may still be working
425 * on our hardware, if we hit this case the hardware poops in a loop.
426 * We prevent this by serializing reads and writes.
427 *
428 * This issue is not present on PCI-Express devices or pre-AR5416
429 * devices (legacy, 802.11abg).
430 */
431 if (num_possible_cpus() > 1)
2d6a5e95 432 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 433
434 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
435 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
436 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
437 !ah->is_pciexpress)) {
438 ah->config.serialize_regmode = SER_REG_MODE_ON;
439 } else {
440 ah->config.serialize_regmode = SER_REG_MODE_OFF;
441 }
442 }
443
444 ath_dbg(common, RESET, "serialize_regmode is %d\n",
445 ah->config.serialize_regmode);
446
447 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
448 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
449 else
450 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 451}
452
50aca25b 453static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 454{
608b88cb
LR		 455 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
456
457 regulatory->country_code = CTRY_DEFAULT;
458 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 459
d535a42a 460 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 461 ah->hw_version.subvendorid = 0;
f078f209 462
f57cf939
SM		 463 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
464 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 465 if (AR_SREV_9100(ah))
466 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 467
11b0ac2e 468 ah->slottime = 9;
2660b81a 469 ah->globaltxtimeout = (u32) -1;
cbdec975 470 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 471 ah->htc_reset_init = true;
f57cf939 472
c09396eb 473 ah->tpc_enabled = false;
a9abe302 474
f57cf939
SM		 475 ah->ani_function = ATH9K_ANI_ALL;
476 if (!AR_SREV_9300_20_OR_LATER(ah))
477 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
478
479 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
480 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
481 else
482 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 483}
484
d323cb71 485static void ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 486{
1510718d 487 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 488 int i;
489 u16 eeval;
07b2fa5a 490 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209 491
0cefa974
MB		 492 /* MAC address may already be loaded via ath9k_platform_data */
493 if (is_valid_ether_addr(common->macaddr))
d323cb71 494 return;
0cefa974 495
f078f209 496 for (i = 0; i < 3; i++) {
49101676 497 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
1510718d
LR		 498 common->macaddr[2 * i] = eeval >> 8;
499 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 500 }
0cefa974
MB		 501
502 if (is_valid_ether_addr(common->macaddr))
d323cb71 503 return;
0cefa974
MB		 504
505 ath_err(common, "eeprom contains invalid mac address: %pM\n",
506 common->macaddr);
507
508 random_ether_addr(common->macaddr);
509 ath_err(common, "random mac address will be used: %pM\n",
510 common->macaddr);
f078f209 511
d323cb71 512 return;
f078f209
LR		 513}
514
f637cfd6 515static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 516{
6cae913d 517 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 518 int ecode;
f078f209 519
6cae913d 520 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 521 if (!ath9k_hw_chip_test(ah))
522 return -ENODEV;
523 }
f078f209 524
ebd5a14a
LR		 525 if (!AR_SREV_9300_20_OR_LATER(ah)) {
526 ecode = ar9002_hw_rf_claim(ah);
527 if (ecode != 0)
528 return ecode;
529 }
f078f209 530
f637cfd6 531 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 532 if (ecode != 0)
533 return ecode;
7d01b221 534
d2182b69 535 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 536 ah->eep_ops->get_eeprom_ver(ah),
537 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 538
e323300d 539 ath9k_hw_ani_init(ah);
f078f209 540
d3b371cb
SM		 541 /*
542 * EEPROM needs to be initialized before we do this.
543 * This is required for regulatory compliance.
544 */
0c7c2bb4 545 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 546 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
547 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 548 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
549 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 550 }
551 }
552
f078f209
LR		 553 return 0;
554}
555
c1b976d2 556static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 557{
c1b976d2
FF		 558 if (!AR_SREV_9300_20_OR_LATER(ah))
559 return ar9002_hw_attach_ops(ah);
560
561 ar9003_hw_attach_ops(ah);
562 return 0;
aa4058ae
LR		 563}
564
d70357d5
LR		 565/* Called for all hardware families */
566static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 567{
c46917bb 568 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 569 int r = 0;
aa4058ae 570
50cf1121
TS		 571 if (!ath9k_hw_read_revisions(ah)) {
572 ath_err(common, "Could not read hardware revisions");
573 return -EOPNOTSUPP;
574 }
ac45c12d 575
de82582b
SM		 576 switch (ah->hw_version.macVersion) {
577 case AR_SREV_VERSION_5416_PCI:
578 case AR_SREV_VERSION_5416_PCIE:
579 case AR_SREV_VERSION_9160:
580 case AR_SREV_VERSION_9100:
581 case AR_SREV_VERSION_9280:
582 case AR_SREV_VERSION_9285:
583 case AR_SREV_VERSION_9287:
584 case AR_SREV_VERSION_9271:
585 case AR_SREV_VERSION_9300:
586 case AR_SREV_VERSION_9330:
587 case AR_SREV_VERSION_9485:
588 case AR_SREV_VERSION_9340:
589 case AR_SREV_VERSION_9462:
590 case AR_SREV_VERSION_9550:
591 case AR_SREV_VERSION_9565:
e6b1e46e 592 case AR_SREV_VERSION_9531:
2131fabb 593 case AR_SREV_VERSION_9561:
de82582b
SM		 594 break;
595 default:
596 ath_err(common,
597 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
598 ah->hw_version.macVersion, ah->hw_version.macRev);
599 return -EOPNOTSUPP;
600 }
601
0a8d7cb0
SB		 602 /*
603 * Read back AR_WA into a permanent copy and set bits 14 and 17.
604 * We need to do this to avoid RMW of this register. We cannot
605 * read the reg when chip is asleep.
606 */
27251e00
SM		 607 if (AR_SREV_9300_20_OR_LATER(ah)) {
608 ah->WARegVal = REG_READ(ah, AR_WA);
609 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
610 AR_WA_ASPM_TIMER_BASED_DISABLE);
611 }
0a8d7cb0 612
aa4058ae 613 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 614 ath_err(common, "Couldn't reset chip\n");
95fafca2 615 return -EIO;
aa4058ae
LR		 616 }
617
a4a2954f
SM		 618 if (AR_SREV_9565(ah)) {
619 ah->WARegVal |= AR_WA_BIT22;
620 REG_WRITE(ah, AR_WA, ah->WARegVal);
621 }
622
bab1f62e
LR		 623 ath9k_hw_init_defaults(ah);
624 ath9k_hw_init_config(ah);
625
c1b976d2
FF		 626 r = ath9k_hw_attach_ops(ah);
627 if (r)
628 return r;
d70357d5 629
9ecdef4b 630 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 631 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 632 return -EIO;
aa4058ae
LR		 633 }
634
2c8e5937 635 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 636 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 637 ah->is_pciexpress = false;
638
aa4058ae 639 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 640 ath9k_hw_init_cal_settings(ah);
641
69ce674b 642 if (!ah->is_pciexpress)
aa4058ae
LR		 643 ath9k_hw_disablepcie(ah);
644
f637cfd6 645 r = ath9k_hw_post_init(ah);
aa4058ae 646 if (r)
95fafca2 647 return r;
aa4058ae
LR		 648
649 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 650 r = ath9k_hw_fill_cap_info(ah);
651 if (r)
652 return r;
653
d323cb71 654 ath9k_hw_init_macaddr(ah);
4598702d 655 ath9k_hw_init_hang_checks(ah);
f078f209 656
211f5859
LR		 657 common->state = ATH_HW_INITIALIZED;
658
4f3acf81 659 return 0;
f078f209
LR		 660}
661
d70357d5 662int ath9k_hw_init(struct ath_hw *ah)
f078f209 663{
d70357d5
LR		 664 int ret;
665 struct ath_common *common = ath9k_hw_common(ah);
f078f209 666
77fac465 667 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 668 switch (ah->hw_version.devid) {
669 case AR5416_DEVID_PCI:
670 case AR5416_DEVID_PCIE:
671 case AR5416_AR9100_DEVID:
672 case AR9160_DEVID_PCI:
673 case AR9280_DEVID_PCI:
674 case AR9280_DEVID_PCIE:
675 case AR9285_DEVID_PCIE:
db3cc53a
SB		 676 case AR9287_DEVID_PCI:
677 case AR9287_DEVID_PCIE:
d70357d5 678 case AR2427_DEVID_PCIE:
db3cc53a 679 case AR9300_DEVID_PCIE:
3050c914 680 case AR9300_DEVID_AR9485_PCIE:
999a7a88 681 case AR9300_DEVID_AR9330:
bca04689 682 case AR9300_DEVID_AR9340:
2b943a33 683 case AR9300_DEVID_QCA955X:
5a63ef0f 684 case AR9300_DEVID_AR9580:
423e38e8 685 case AR9300_DEVID_AR9462:
d4e5979c 686 case AR9485_DEVID_AR1111:
77fac465 687 case AR9300_DEVID_AR9565:
e6b1e46e 688 case AR9300_DEVID_AR953X:
2131fabb 689 case AR9300_DEVID_QCA956X:
d70357d5
LR		 690 break;
691 default:
692 if (common->bus_ops->ath_bus_type == ATH_USB)
693 break;
3800276a
JP		 694 ath_err(common, "Hardware device ID 0x%04x not supported\n",
695 ah->hw_version.devid);
d70357d5
LR		 696 return -EOPNOTSUPP;
697 }
f078f209 698
d70357d5
LR		 699 ret = __ath9k_hw_init(ah);
700 if (ret) {
3800276a
JP		 701 ath_err(common,
702 "Unable to initialize hardware; initialization status: %d\n",
703 ret);
d70357d5
LR		 704 return ret;
705 }
f078f209 706
c774d57f
LB		 707 ath_dynack_init(ah);
708
d70357d5 709 return 0;
f078f209 710}
d70357d5 711EXPORT_SYMBOL(ath9k_hw_init);
f078f209 712
cbe61d8a 713static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 714{
7d0d0df0
S		 715 ENABLE_REGWRITE_BUFFER(ah);
716
f1dc5600
S		 717 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
718 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 719
f1dc5600
S		 720 REG_WRITE(ah, AR_QOS_NO_ACK,
721 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
722 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
723 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
724
725 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
726 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
727 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
728 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
729 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 730
731 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 732}
733
b84628eb 734u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 735{
f18e3c6b
MSS		 736 struct ath_common *common = ath9k_hw_common(ah);
737 int i = 0;
738
ca7a4deb
FF		 739 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
740 udelay(100);
741 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 742
f18e3c6b
MSS		 743 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
744
ca7a4deb 745 udelay(100);
b1415819 746
f18e3c6b 747 if (WARN_ON_ONCE(i >= 100)) {
714ee339 748 ath_err(common, "PLL4 measurement not done\n");
f18e3c6b
MSS		 749 break;
750 }
751
752 i++;
753 }
754
ca7a4deb 755 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 756}
757EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
758
cbe61d8a 759static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 760 struct ath9k_channel *chan)
f078f209 761{
d09b17f7
VT		 762 u32 pll;
763
5fb9b1b9
FF		 764 pll = ath9k_hw_compute_pll_control(ah, chan);
765
a4a2954f 766 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 767 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
769 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
771 AR_CH0_DPLL2_KD, 0x40);
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 AR_CH0_DPLL2_KI, 0x4);
22983c30 774
3dfd7f60
VT		 775 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
776 AR_CH0_BB_DPLL1_REFDIV, 0x5);
777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
778 AR_CH0_BB_DPLL1_NINI, 0x58);
779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
780 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 781
782 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 783 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
784 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
785 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 786 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 787 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 788
3dfd7f60 789 /* program BB PLL phase_shift to 0x6 */
22983c30 790 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 791 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
792
793 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
794 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 795 udelay(1000);
a5415d62
GJ		 796 } else if (AR_SREV_9330(ah)) {
797 u32 ddr_dpll2, pll_control2, kd;
798
799 if (ah->is_clk_25mhz) {
800 ddr_dpll2 = 0x18e82f01;
801 pll_control2 = 0xe04a3d;
802 kd = 0x1d;
803 } else {
804 ddr_dpll2 = 0x19e82f01;
805 pll_control2 = 0x886666;
806 kd = 0x3d;
807 }
808
809 /* program DDR PLL ki and kd value */
810 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
811
812 /* program DDR PLL phase_shift */
813 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
814 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
815
5fb9b1b9
FF		 816 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
817 pll | AR_RTC_9300_PLL_BYPASS);
a5415d62
GJ		 818 udelay(1000);
819
820 /* program refdiv, nint, frac to RTC register */
821 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
822
823 /* program BB PLL kd and ki value */
824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
826
827 /* program BB PLL phase_shift */
828 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
829 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
ede6a5e7
MP		 830 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
831 AR_SREV_9561(ah)) {
0b488ac6
VT		 832 u32 regval, pll2_divint, pll2_divfrac, refdiv;
833
5fb9b1b9
FF		 834 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
835 pll | AR_RTC_9300_SOC_PLL_BYPASS);
0b488ac6
VT		 836 udelay(1000);
837
838 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
839 udelay(100);
840
841 if (ah->is_clk_25mhz) {
ede6a5e7 842 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 843 pll2_divint = 0x1c;
844 pll2_divfrac = 0xa3d2;
845 refdiv = 1;
846 } else {
847 pll2_divint = 0x54;
848 pll2_divfrac = 0x1eb85;
849 refdiv = 3;
850 }
0b488ac6 851 } else {
fc05a317
GJ		 852 if (AR_SREV_9340(ah)) {
853 pll2_divint = 88;
854 pll2_divfrac = 0;
855 refdiv = 5;
856 } else {
857 pll2_divint = 0x11;
ede6a5e7
MP		 858 pll2_divfrac = (AR_SREV_9531(ah) ||
859 AR_SREV_9561(ah)) ?
860 0x26665 : 0x26666;
fc05a317
GJ		 861 refdiv = 1;
862 }
0b488ac6
VT		 863 }
864
865 regval = REG_READ(ah, AR_PHY_PLL_MODE);
ede6a5e7 866 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 867 regval |= (0x1 << 22);
868 else
869 regval |= (0x1 << 16);
0b488ac6
VT		 870 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
871 udelay(100);
872
873 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
874 (pll2_divint << 18) | pll2_divfrac);
875 udelay(100);
876
877 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 878 if (AR_SREV_9340(ah))
2c323058
SM		 879 regval = (regval & 0x80071fff) |
880 (0x1 << 30) |
881 (0x1 << 13) |
882 (0x4 << 26) |
883 (0x18 << 19);
ede6a5e7 884 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 885 regval = (regval & 0x01c00fff) |
886 (0x1 << 31) |
887 (0x2 << 29) |
888 (0xa << 25) |
ede6a5e7
MP		 889 (0x1 << 19);
890
891 if (AR_SREV_9531(ah))
892 regval |= (0x6 << 12);
893 } else
2c323058
SM		 894 regval = (regval & 0x80071fff) |
895 (0x3 << 30) |
896 (0x1 << 13) |
897 (0x4 << 26) |
898 (0x60 << 19);
0b488ac6 899 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058 900
ede6a5e7 901 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 902 REG_WRITE(ah, AR_PHY_PLL_MODE,
903 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
904 else
905 REG_WRITE(ah, AR_PHY_PLL_MODE,
906 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
907
0b488ac6 908 udelay(1000);
22983c30 909 }
d09b17f7 910
8565f8bf
SM		 911 if (AR_SREV_9565(ah))
912 pll |= 0x40000;
d03a66c1 913 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 914
fc05a317
GJ		 915 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
916 AR_SREV_9550(ah))
3dfd7f60
VT		 917 udelay(1000);
918
c75724d1
LR		 919 /* Switch the core clock for ar9271 to 117Mhz */
920 if (AR_SREV_9271(ah)) {
25e2ab17
S		 921 udelay(500);
922 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 923 }
924
f1dc5600
S		 925 udelay(RTC_PLL_SETTLE_DELAY);
926
927 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 928}
929
cbe61d8a 930static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 931 enum nl80211_iftype opmode)
f078f209 932{
79d1d2b8 933 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 934 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 935 AR_IMR_TXURN |
936 AR_IMR_RXERR |
937 AR_IMR_RXORN |
938 AR_IMR_BCNMISC;
947810c8 939 u32 msi_cfg = 0;
f078f209 940
ede6a5e7
MP		 941 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
942 AR_SREV_9561(ah))
79d1d2b8
VT		 943 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
944
66860240
VT		 945 if (AR_SREV_9300_20_OR_LATER(ah)) {
946 imr_reg |= AR_IMR_RXOK_HP;
947810c8 947 if (ah->config.rx_intr_mitigation) {
66860240 948 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
947810c8
RH		 949 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;
950 } else {
66860240 951 imr_reg |= AR_IMR_RXOK_LP;
947810c8
RH		 952 msi_cfg |= AR_INTCFG_MSI_RXOK;
953 }
66860240 954 } else {
947810c8 955 if (ah->config.rx_intr_mitigation) {
66860240 956 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
947810c8
RH		 957 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;
958 } else {
66860240 959 imr_reg |= AR_IMR_RXOK;
947810c8
RH		 960 msi_cfg |= AR_INTCFG_MSI_RXOK;
961 }
66860240 962 }
f078f209 963
947810c8 964 if (ah->config.tx_intr_mitigation) {
66860240 965 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
947810c8
RH		 966 msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR;
967 } else {
66860240 968 imr_reg |= AR_IMR_TXOK;
947810c8
RH		 969 msi_cfg |= AR_INTCFG_MSI_TXOK;
970 }
f078f209 971
7d0d0df0
S		 972 ENABLE_REGWRITE_BUFFER(ah);
973
152d530d 974 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 975 ah->imrs2_reg |= AR_IMR_S2_GTT;
976 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 977
947810c8
RH		 978 if (ah->msi_enabled) {
979 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI);
980 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;
981 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;
982 REG_WRITE(ah, AR_INTCFG, msi_cfg);
983 ath_dbg(ath9k_hw_common(ah), ANY,
984 "value of AR_INTCFG=0x%X, msi_cfg=0x%X\n",
985 REG_READ(ah, AR_INTCFG), msi_cfg);
986 }
987
f1dc5600
S		 988 if (!AR_SREV_9100(ah)) {
989 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 990 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 991 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
992 }
66860240 993
7d0d0df0 994 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 995
66860240
VT		 996 if (AR_SREV_9300_20_OR_LATER(ah)) {
997 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
998 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
999 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
1000 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
1001 }
f078f209
LR		 1002}
1003
b6ba41bb
FF		 1004static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
1005{
1006 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
1007 val = min(val, (u32) 0xFFFF);
1008 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1009}
1010
8e15e094 1011void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 1012{
0005baf4
FF		 1013 u32 val = ath9k_hw_mac_to_clks(ah, us);
1014 val = min(val, (u32) 0xFFFF);
1015 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 1016}
1017
8e15e094 1018void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1019{
0005baf4
FF		 1020 u32 val = ath9k_hw_mac_to_clks(ah, us);
1021 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1022 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1023}
1024
8e15e094 1025void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
0005baf4
FF		 1026{
1027 u32 val = ath9k_hw_mac_to_clks(ah, us);
1028 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1029 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1030}
f1dc5600 1031
cbe61d8a 1032static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1033{
f078f209 1034 if (tu > 0xFFFF) {
d2182b69
JP		 1035 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1036 tu);
2660b81a 1037 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1038 return false;
1039 } else {
1040 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1041 ah->globaltxtimeout = tu;
f078f209
LR		 1042 return true;
1043 }
1044}
1045
0005baf4 1046void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1047{
b6ba41bb 1048 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 1049 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1050 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1051 int slottime;
0005baf4 1052 int sifstime;
b6ba41bb
FF		 1053 int rx_lat = 0, tx_lat = 0, eifs = 0;
1054 u32 reg;
0005baf4 1055
d2182b69 1056 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1057 ah->misc_mode);
f078f209 1058
b6ba41bb
FF		 1059 if (!chan)
1060 return;
1061
2660b81a 1062 if (ah->misc_mode != 0)
ca7a4deb 1063 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1064
81a91d57
RM		 1065 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1066 rx_lat = 41;
1067 else
1068 rx_lat = 37;
b6ba41bb
FF		 1069 tx_lat = 54;
1070
e88e4861
FF		 1071 if (IS_CHAN_5GHZ(chan))
1072 sifstime = 16;
1073 else
1074 sifstime = 10;
1075
b6ba41bb
FF		 1076 if (IS_CHAN_HALF_RATE(chan)) {
1077 eifs = 175;
1078 rx_lat *= 2;
1079 tx_lat *= 2;
1080 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1081 tx_lat += 11;
1082
92367fe7 1083 sifstime = 32;
e115b7ec 1084 ack_offset = 16;
b6ba41bb 1085 slottime = 13;
b6ba41bb
FF		 1086 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1087 eifs = 340;
81a91d57 1088 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1089 tx_lat *= 4;
1090 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1091 tx_lat += 22;
1092
92367fe7 1093 sifstime = 64;
e115b7ec 1094 ack_offset = 32;
b6ba41bb 1095 slottime = 21;
b6ba41bb 1096 } else {
a7be039d
RM		 1097 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1098 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1099 reg = AR_USEC_ASYNC_FIFO;
1100 } else {
1101 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1102 common->clockrate;
1103 reg = REG_READ(ah, AR_USEC);
1104 }
b6ba41bb
FF		 1105 rx_lat = MS(reg, AR_USEC_RX_LAT);
1106 tx_lat = MS(reg, AR_USEC_TX_LAT);
1107
1108 slottime = ah->slottime;
b6ba41bb 1109 }
0005baf4 1110
e239d859 1111 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1112 slottime += 3 * ah->coverage_class;
1113 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1114 ctstimeout = acktimeout;
42c4568a
FF		 1115
1116 /*
1117 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1118 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1119 * This was initially only meant to work around an issue with delayed
1120 * BA frames in some implementations, but it has been found to fix ACK
1121 * timeout issues in other cases as well.
1122 */
e4744ec7 1123 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1124 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1125 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1126 ctstimeout += 48 - sifstime - ah->slottime;
1127 }
1128
7aefa8aa
LB		 1129 if (ah->dynack.enabled) {
1130 acktimeout = ah->dynack.ackto;
1131 ctstimeout = acktimeout;
1132 slottime = (acktimeout - 3) / 2;
1133 } else {
1134 ah->dynack.ackto = acktimeout;
1135 }
1136
b6ba41bb
FF		 1137 ath9k_hw_set_sifs_time(ah, sifstime);
1138 ath9k_hw_setslottime(ah, slottime);
0005baf4 1139 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1140 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1141 if (ah->globaltxtimeout != (u32) -1)
1142 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1143
1144 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1145 REG_RMW(ah, AR_USEC,
1146 (common->clockrate - 1) |
1147 SM(rx_lat, AR_USEC_RX_LAT) |
1148 SM(tx_lat, AR_USEC_TX_LAT),
1149 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1150
f1dc5600 1151}
0005baf4 1152EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1153
285f2dda 1154void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1155{
211f5859
LR		 1156 struct ath_common *common = ath9k_hw_common(ah);
1157
736b3a27 1158 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1159 return;
211f5859 1160
9ecdef4b 1161 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1162}
285f2dda 1163EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1164
f1dc5600
S		 1165/*******/
1166/* INI */
1167/*******/
1168
8fe65368 1169u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1170{
1171 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1172
6b21fd20 1173 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1174 ctl |= CTL_11G;
1175 else
1176 ctl |= CTL_11A;
1177
1178 return ctl;
1179}
1180
f1dc5600
S		 1181/****************************************/
1182/* Reset and Channel Switching Routines */
1183/****************************************/
f1dc5600 1184
cbe61d8a 1185static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1186{
57b32227 1187 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1188 int txbuf_size;
f1dc5600 1189
7d0d0df0
S		 1190 ENABLE_REGWRITE_BUFFER(ah);
1191
d7e7d229
LR		 1192 /*
1193 * set AHB_MODE not to do cacheline prefetches
1194 */
ca7a4deb
FF		 1195 if (!AR_SREV_9300_20_OR_LATER(ah))
1196 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1197
d7e7d229
LR		 1198 /*
1199 * let mac dma reads be in 128 byte chunks
1200 */
ca7a4deb 1201 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1202
7d0d0df0 1203 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1204
d7e7d229
LR		 1205 /*
1206 * Restore TX Trigger Level to its pre-reset value.
1207 * The initial value depends on whether aggregation is enabled, and is
1208 * adjusted whenever underruns are detected.
1209 */
57b32227
FF		 1210 if (!AR_SREV_9300_20_OR_LATER(ah))
1211 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1212
7d0d0df0 1213 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1214
d7e7d229
LR		 1215 /*
1216 * let mac dma writes be in 128 byte chunks
1217 */
ca7a4deb 1218 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1219
d7e7d229
LR		 1220 /*
1221 * Setup receive FIFO threshold to hold off TX activities
1222 */
f1dc5600
S		 1223 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1224
57b32227
FF		 1225 if (AR_SREV_9300_20_OR_LATER(ah)) {
1226 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1227 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1228
1229 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1230 ah->caps.rx_status_len);
1231 }
1232
d7e7d229
LR		 1233 /*
1234 * reduce the number of usable entries in PCU TXBUF to avoid
1235 * wrap around issues.
1236 */
f1dc5600 1237 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1238 /* For AR9285 the number of Fifos are reduced to half.
1239 * So set the usable tx buf size also to half to
1240 * avoid data/delimiter underruns
1241 */
86c157b3
FF		 1242 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1243 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1244 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1245 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1246 } else {
1247 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1248 }
744d4025 1249
86c157b3
FF		 1250 if (!AR_SREV_9271(ah))
1251 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1252
7d0d0df0 1253 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1254
744d4025
VT		 1255 if (AR_SREV_9300_20_OR_LATER(ah))
1256 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1257}
1258
cbe61d8a 1259static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1260{
ca7a4deb
FF		 1261 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1262 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1263
7b37e0d4 1264 ENABLE_REG_RMW_BUFFER(ah);
f1dc5600 1265 switch (opmode) {
d97809db 1266 case NL80211_IFTYPE_ADHOC:
83322eb8
FF		 1267 if (!AR_SREV_9340_13(ah)) {
1268 set |= AR_STA_ID1_ADHOC;
1269 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1270 break;
1271 }
1272 /* fall through */
862a336c 1273 case NL80211_IFTYPE_OCB:
2664d666 1274 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1275 case NL80211_IFTYPE_AP:
1276 set |= AR_STA_ID1_STA_AP;
1277 /* fall through */
d97809db 1278 case NL80211_IFTYPE_STATION:
ca7a4deb 1279 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1280 break;
5f841b41 1281 default:
ca7a4deb
FF		 1282 if (!ah->is_monitoring)
1283 set = 0;
5f841b41 1284 break;
f1dc5600 1285 }
ca7a4deb 1286 REG_RMW(ah, AR_STA_ID1, set, mask);
7b37e0d4 1287 REG_RMW_BUFFER_FLUSH(ah);
f1dc5600
S		 1288}
1289
8fe65368
LR		 1290void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1291 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1292{
1293 u32 coef_exp, coef_man;
1294
1295 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1296 if ((coef_scaled >> coef_exp) & 0x1)
1297 break;
1298
1299 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1300
1301 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1302
1303 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1304 *coef_exponent = coef_exp - 16;
1305}
1306
d7df7a55
SM		 1307/* AR9330 WAR:
1308 * call external reset function to reset WMAC if:
1309 * - doing a cold reset
1310 * - we have pending frames in the TX queues.
1311 */
1312static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1313{
1314 int i, npend = 0;
1315
1316 for (i = 0; i < AR_NUM_QCU; i++) {
1317 npend = ath9k_hw_numtxpending(ah, i);
1318 if (npend)
1319 break;
1320 }
1321
1322 if (ah->external_reset &&
1323 (npend || type == ATH9K_RESET_COLD)) {
1324 int reset_err = 0;
1325
1326 ath_dbg(ath9k_hw_common(ah), RESET,
1327 "reset MAC via external reset\n");
1328
1329 reset_err = ah->external_reset();
1330 if (reset_err) {
1331 ath_err(ath9k_hw_common(ah),
1332 "External reset failed, err=%d\n",
1333 reset_err);
1334 return false;
1335 }
1336
1337 REG_WRITE(ah, AR_RTC_RESET, 1);
1338 }
1339
1340 return true;
1341}
1342
cbe61d8a 1343static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1344{
1345 u32 rst_flags;
1346 u32 tmpReg;
1347
70768496 1348 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1349 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1350 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1351 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1352 }
1353
7d0d0df0
S		 1354 ENABLE_REGWRITE_BUFFER(ah);
1355
9a658d2b
LR		 1356 if (AR_SREV_9300_20_OR_LATER(ah)) {
1357 REG_WRITE(ah, AR_WA, ah->WARegVal);
1358 udelay(10);
1359 }
1360
f1dc5600
S		 1361 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1362 AR_RTC_FORCE_WAKE_ON_INT);
1363
1364 if (AR_SREV_9100(ah)) {
1365 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1366 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1367 } else {
1368 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1369 if (AR_SREV_9340(ah))
1370 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1371 else
1372 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1373 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1374
1375 if (tmpReg) {
42d5bc3f 1376 u32 val;
f1dc5600 1377 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1378
1379 val = AR_RC_HOSTIF;
1380 if (!AR_SREV_9300_20_OR_LATER(ah))
1381 val |= AR_RC_AHB;
1382 REG_WRITE(ah, AR_RC, val);
1383
1384 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1385 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1386
1387 rst_flags = AR_RTC_RC_MAC_WARM;
1388 if (type == ATH9K_RESET_COLD)
1389 rst_flags |= AR_RTC_RC_MAC_COLD;
1390 }
1391
7d95847c 1392 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1393 if (!ath9k_hw_ar9330_reset_war(ah, type))
1394 return false;
7d95847c
GJ		 1395 }
1396
3863495b 1397 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1398 ar9003_mci_check_gpm_offset(ah);
3863495b 1399
466b0f02
MP		 1400 /* DMA HALT added to resolve ar9300 and ar9580 bus error during
1401 * RTC_RC reg read
1402 */
1403 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1404 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1405 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1406 20 * AH_WAIT_TIMEOUT);
1407 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1408 }
1409
d03a66c1 1410 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1411
1412 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1413
4dc78c43
SM		 1414 if (AR_SREV_9300_20_OR_LATER(ah))
1415 udelay(50);
1416 else if (AR_SREV_9100(ah))
3683a07b 1417 mdelay(10);
4dc78c43
SM		 1418 else
1419 udelay(100);
f1dc5600 1420
d03a66c1 1421 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1422 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1423 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1424 return false;
1425 }
1426
1427 if (!AR_SREV_9100(ah))
1428 REG_WRITE(ah, AR_RC, 0);
1429
f1dc5600
S		 1430 if (AR_SREV_9100(ah))
1431 udelay(50);
1432
1433 return true;
1434}
1435
cbe61d8a 1436static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1437{
7d0d0df0
S		 1438 ENABLE_REGWRITE_BUFFER(ah);
1439
9a658d2b
LR		 1440 if (AR_SREV_9300_20_OR_LATER(ah)) {
1441 REG_WRITE(ah, AR_WA, ah->WARegVal);
1442 udelay(10);
1443 }
1444
f1dc5600
S		 1445 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1446 AR_RTC_FORCE_WAKE_ON_INT);
1447
42d5bc3f 1448 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1449 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1450
d03a66c1 1451 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1452
7d0d0df0 1453 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1454
afe36533 1455 udelay(2);
84e2169b
SB		 1456
1457 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1458 REG_WRITE(ah, AR_RC, 0);
1459
d03a66c1 1460 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1461
1462 if (!ath9k_hw_wait(ah,
1463 AR_RTC_STATUS,
1464 AR_RTC_STATUS_M,
0caa7b14
S		 1465 AR_RTC_STATUS_ON,
1466 AH_WAIT_TIMEOUT)) {
d2182b69 1467 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1468 return false;
f078f209
LR		 1469 }
1470
f1dc5600
S		 1471 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1472}
1473
cbe61d8a 1474static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1475{
7a9233ff 1476 bool ret = false;
2577c6e8 1477
9a658d2b
LR		 1478 if (AR_SREV_9300_20_OR_LATER(ah)) {
1479 REG_WRITE(ah, AR_WA, ah->WARegVal);
1480 udelay(10);
1481 }
1482
f1dc5600
S		 1483 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1484 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1485
ceb26a60
FF		 1486 if (!ah->reset_power_on)
1487 type = ATH9K_RESET_POWER_ON;
1488
f1dc5600
S		 1489 switch (type) {
1490 case ATH9K_RESET_POWER_ON:
7a9233ff 1491 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1492 if (ret)
ceb26a60 1493 ah->reset_power_on = true;
7a9233ff 1494 break;
f1dc5600
S		 1495 case ATH9K_RESET_WARM:
1496 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1497 ret = ath9k_hw_set_reset(ah, type);
1498 break;
f1dc5600 1499 default:
7a9233ff 1500 break;
f1dc5600 1501 }
7a9233ff 1502
7a9233ff 1503 return ret;
f078f209
LR		 1504}
1505
cbe61d8a 1506static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1507 struct ath9k_channel *chan)
f078f209 1508{
9c083af8
FF		 1509 int reset_type = ATH9K_RESET_WARM;
1510
1511 if (AR_SREV_9280(ah)) {
1512 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1513 reset_type = ATH9K_RESET_POWER_ON;
1514 else
1515 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1516 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1517 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1518 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1519
1520 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1521 return false;
f078f209 1522
9ecdef4b 1523 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1524 return false;
f078f209 1525
2660b81a 1526 ah->chip_fullsleep = false;
bfc441a4
FF		 1527
1528 if (AR_SREV_9330(ah))
1529 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1530 ath9k_hw_init_pll(ah, chan);
f078f209 1531
f1dc5600 1532 return true;
f078f209
LR		 1533}
1534
cbe61d8a 1535static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1536 struct ath9k_channel *chan)
f078f209 1537{
c46917bb 1538 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1539 struct ath9k_hw_capabilities *pCap = &ah->caps;
1540 bool band_switch = false, mode_diff = false;
70e89a71 1541 u8 ini_reloaded = 0;
8fe65368 1542 u32 qnum;
0a3b7bac 1543 int r;
5f0c04ea 1544
b840cffe 1545 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1546 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1547 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1548 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1549 }
f078f209
LR		 1550
1551 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1552 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1553 ath_dbg(common, QUEUE,
226afe68 1554 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1555 return false;
1556 }
1557 }
1558
8fe65368 1559 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1560 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1561 return false;
1562 }
1563
b840cffe 1564 if (band_switch || mode_diff) {
5f0c04ea
RM		 1565 ath9k_hw_mark_phy_inactive(ah);
1566 udelay(5);
1567
5f35c0fa
SM		 1568 if (band_switch)
1569 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1570
1571 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1572 ath_err(common, "Failed to do fast channel change\n");
1573 return false;
1574 }
1575 }
1576
8fe65368 1577 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1578
8fe65368 1579 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1580 if (r) {
3800276a 1581 ath_err(common, "Failed to set channel\n");
0a3b7bac 1582 return false;
f078f209 1583 }
dfdac8ac 1584 ath9k_hw_set_clockrate(ah);
64ea57d0 1585 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1586
81c507a8 1587 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1588 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1589
70e89a71
SM		 1590 if (band_switch || ini_reloaded)
1591 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1592
70e89a71
SM		 1593 ath9k_hw_init_bb(ah, chan);
1594 ath9k_hw_rfbus_done(ah);
5f0c04ea 1595
70e89a71
SM		 1596 if (band_switch || ini_reloaded) {
1597 ah->ah_flags |= AH_FASTCC;
1598 ath9k_hw_init_cal(ah, chan);
a126ff51 1599 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1600 }
1601
f1dc5600
S		 1602 return true;
1603}
1604
691680b8
FF		 1605static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1606{
1607 u32 gpio_mask = ah->gpio_mask;
1608 int i;
1609
1610 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1611 if (!(gpio_mask & 1))
1612 continue;
1613
b2d70d49
MP		 1614 ath9k_hw_gpio_request_out(ah, i, NULL,
1615 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
691680b8 1616 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
db222190 1617 ath9k_hw_gpio_free(ah, i);
691680b8
FF		 1618 }
1619}
1620
1e516ca7
SM		 1621void ath9k_hw_check_nav(struct ath_hw *ah)
1622{
1623 struct ath_common *common = ath9k_hw_common(ah);
1624 u32 val;
1625
1626 val = REG_READ(ah, AR_NAV);
1627 if (val != 0xdeadbeef && val > 0x7fff) {
1628 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1629 REG_WRITE(ah, AR_NAV, 0);
1630 }
1631}
1632EXPORT_SYMBOL(ath9k_hw_check_nav);
1633
c9c99e5e 1634bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1635{
c9c99e5e 1636 int count = 50;
d31a36a6 1637 u32 reg, last_val;
c9c99e5e 1638
a34d0a0d
FF		 1639 /* Check if chip failed to wake up */
1640 if (REG_READ(ah, AR_CFG) == 0xdeadbeef)
1641 return false;
1642
01e18918
RM		 1643 if (AR_SREV_9300(ah))
1644 return !ath9k_hw_detect_mac_hang(ah);
1645
e17f83ea 1646 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1647 return true;
1648
d31a36a6 1649 last_val = REG_READ(ah, AR_OBS_BUS_1);
c9c99e5e
FF		 1650 do {
1651 reg = REG_READ(ah, AR_OBS_BUS_1);
d31a36a6
FF		 1652 if (reg != last_val)
1653 return true;
3b319aae 1654
105ff411 1655 udelay(1);
d31a36a6 1656 last_val = reg;
c9c99e5e
FF		 1657 if ((reg & 0x7E7FFFEF) == 0x00702400)
1658 continue;
1659
1660 switch (reg & 0x7E000B00) {
1661 case 0x1E000000:
1662 case 0x52000B00:
1663 case 0x18000B00:
1664 continue;
1665 default:
1666 return true;
1667 }
1668 } while (count-- > 0);
3b319aae 1669
c9c99e5e 1670 return false;
3b319aae 1671}
c9c99e5e 1672EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1673
15d2b585
SM		 1674static void ath9k_hw_init_mfp(struct ath_hw *ah)
1675{
1676 /* Setup MFP options for CCMP */
1677 if (AR_SREV_9280_20_OR_LATER(ah)) {
1678 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1679 * frames when constructing CCMP AAD. */
1680 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1681 0xc7ff);
60fc4962
CYY		 1682 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1683 ah->sw_mgmt_crypto_tx = true;
1684 else
1685 ah->sw_mgmt_crypto_tx = false;
e6510b11 1686 ah->sw_mgmt_crypto_rx = false;
15d2b585
SM		 1687 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1688 /* Disable hardware crypto for management frames */
1689 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1690 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1691 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1692 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
e6510b11
CYY		 1693 ah->sw_mgmt_crypto_tx = true;
1694 ah->sw_mgmt_crypto_rx = true;
15d2b585 1695 } else {
e6510b11
CYY		 1696 ah->sw_mgmt_crypto_tx = true;
1697 ah->sw_mgmt_crypto_rx = true;
15d2b585
SM		 1698 }
1699}
1700
1701static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1702 u32 macStaId1, u32 saveDefAntenna)
1703{
1704 struct ath_common *common = ath9k_hw_common(ah);
1705
1706 ENABLE_REGWRITE_BUFFER(ah);
1707
ecbbed32 1708 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1709 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1710 | ah->sta_id1_defaults,
1711 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1712 ath_hw_setbssidmask(common);
1713 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1714 ath9k_hw_write_associd(ah);
1715 REG_WRITE(ah, AR_ISR, ~0);
1716 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1717
1718 REGWRITE_BUFFER_FLUSH(ah);
1719
1720 ath9k_hw_set_operating_mode(ah, ah->opmode);
1721}
1722
1723static void ath9k_hw_init_queues(struct ath_hw *ah)
1724{
1725 int i;
1726
1727 ENABLE_REGWRITE_BUFFER(ah);
1728
1729 for (i = 0; i < AR_NUM_DCU; i++)
1730 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1731
1732 REGWRITE_BUFFER_FLUSH(ah);
1733
1734 ah->intr_txqs = 0;
1735 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1736 ath9k_hw_resettxqueue(ah, i);
1737}
1738
1739/*
1740 * For big endian systems turn on swapping for descriptors
1741 */
1742static void ath9k_hw_init_desc(struct ath_hw *ah)
1743{
1744 struct ath_common *common = ath9k_hw_common(ah);
1745
1746 if (AR_SREV_9100(ah)) {
1747 u32 mask;
1748 mask = REG_READ(ah, AR_CFG);
1749 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1750 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1751 mask);
1752 } else {
1753 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1754 REG_WRITE(ah, AR_CFG, mask);
1755 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1756 REG_READ(ah, AR_CFG));
1757 }
1758 } else {
1759 if (common->bus_ops->ath_bus_type == ATH_USB) {
1760 /* Configure AR9271 target WLAN */
1761 if (AR_SREV_9271(ah))
1762 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1763 else
1764 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1765 }
1766#ifdef __BIG_ENDIAN
1767 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
ede6a5e7
MP		 1768 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1769 AR_SREV_9561(ah))
15d2b585
SM		 1770 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1771 else
1772 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1773#endif
1774 }
1775}
1776
caed6579
SM		 1777/*
1778 * Fast channel change:
1779 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1780 */
1781static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1782{
1783 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1784 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1785 int ret;
1786
1787 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1788 goto fail;
1789
1790 if (ah->chip_fullsleep)
1791 goto fail;
1792
1793 if (!ah->curchan)
1794 goto fail;
1795
1796 if (chan->channel == ah->curchan->channel)
1797 goto fail;
1798
feb7bc99
FF		 1799 if ((ah->curchan->channelFlags | chan->channelFlags) &
1800 (CHANNEL_HALF | CHANNEL_QUARTER))
1801 goto fail;
1802
b840cffe 1803 /*
6b21fd20 1804 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1805 */
6b21fd20 1806 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1807 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1808 goto fail;
caed6579
SM		 1809
1810 if (!ath9k_hw_check_alive(ah))
1811 goto fail;
1812
1813 /*
1814 * For AR9462, make sure that calibration data for
1815 * re-using are present.
1816 */
8a90555f 1817 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1818 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1819 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1820 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1821 goto fail;
1822
1823 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1824 ah->curchan->channel, chan->channel);
1825
1826 ret = ath9k_hw_channel_change(ah, chan);
1827 if (!ret)
1828 goto fail;
1829
5955b2b0 1830 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1831 ar9003_mci_2g5g_switch(ah, false);
caed6579 1832
88033318
RM		 1833 ath9k_hw_loadnf(ah, ah->curchan);
1834 ath9k_hw_start_nfcal(ah, true);
1835
caed6579
SM		 1836 if (AR_SREV_9271(ah))
1837 ar9002_hw_load_ani_reg(ah, chan);
1838
1839 return 0;
1840fail:
1841 return -EINVAL;
1842}
1843
8d7e09dd
FF		 1844u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1845{
1846 struct timespec ts;
1847 s64 usec;
1848
1849 if (!cur) {
1850 getrawmonotonic(&ts);
1851 cur = &ts;
1852 }
1853
1854 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1855 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1856
1857 return (u32) usec;
1858}
1859EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1860
cbe61d8a 1861int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1862 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1863{
1510718d 1864 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1865 u32 saveLedState;
f078f209
LR		 1866 u32 saveDefAntenna;
1867 u32 macStaId1;
bec9a94b
BB		 1868 struct timespec tsf_ts;
1869 u32 tsf_offset;
46fe782c 1870 u64 tsf = 0;
15d2b585 1871 int r;
caed6579 1872 bool start_mci_reset = false;
63d32967
MSS		 1873 bool save_fullsleep = ah->chip_fullsleep;
1874
5955b2b0 1875 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1876 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1877 if (start_mci_reset)
1878 return 0;
63d32967
MSS		 1879 }
1880
9ecdef4b 1881 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1882 return -EIO;
f078f209 1883
caed6579
SM		 1884 if (ah->curchan && !ah->chip_fullsleep)
1885 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1886
20bd2a09 1887 ah->caldata = caldata;
fcb9a3de 1888 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1889 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1890 /* Operating channel changed, reset channel calibration data */
1891 memset(caldata, 0, sizeof(*caldata));
1892 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1893 } else if (caldata) {
4b9b42bf 1894 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1895 }
5bc225ac 1896 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1897
caed6579
SM		 1898 if (fastcc) {
1899 r = ath9k_hw_do_fastcc(ah, chan);
1900 if (!r)
1901 return r;
f078f209
LR		 1902 }
1903
5955b2b0 1904 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1905 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1906
f078f209
LR		 1907 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1908 if (saveDefAntenna == 0)
1909 saveDefAntenna = 1;
1910
1911 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1912
09d8e315 1913 /* Save TSF before chip reset, a cold reset clears it */
bec9a94b 1914 getrawmonotonic(&tsf_ts);
09d8e315 1915 tsf = ath9k_hw_gettsf64(ah);
46fe782c 1916
f078f209
LR		 1917 saveLedState = REG_READ(ah, AR_CFG_LED) &
1918 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1919 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1920
1921 ath9k_hw_mark_phy_inactive(ah);
1922
45ef6a0b
VT		 1923 ah->paprd_table_write_done = false;
1924
05020d23 1925 /* Only required on the first reset */
d7e7d229
LR		 1926 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1927 REG_WRITE(ah,
1928 AR9271_RESET_POWER_DOWN_CONTROL,
1929 AR9271_RADIO_RF_RST);
1930 udelay(50);
1931 }
1932
f078f209 1933 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1934 ath_err(common, "Chip reset failed\n");
ae8d2858 1935 return -EINVAL;
f078f209
LR		 1936 }
1937
05020d23 1938 /* Only required on the first reset */
d7e7d229
LR		 1939 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1940 ah->htc_reset_init = false;
1941 REG_WRITE(ah,
1942 AR9271_RESET_POWER_DOWN_CONTROL,
1943 AR9271_GATE_MAC_CTL);
1944 udelay(50);
1945 }
1946
46fe782c 1947 /* Restore TSF */
bec9a94b
BB		 1948 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1949 ath9k_hw_settsf64(ah, tsf + tsf_offset);
46fe782c 1950
7a37081e 1951 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1952 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1953
e9141f71
S		 1954 if (!AR_SREV_9300_20_OR_LATER(ah))
1955 ar9002_hw_enable_async_fifo(ah);
1956
25c56eec 1957 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1958 if (r)
1959 return r;
f078f209 1960
935d00cc
LB		 1961 ath9k_hw_set_rfmode(ah, chan);
1962
5955b2b0 1963 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1964 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1965
f860d526
FF		 1966 /*
1967 * Some AR91xx SoC devices frequently fail to accept TSF writes
1968 * right after the chip reset. When that happens, write a new
bec9a94b 1969 * value after the initvals have been applied.
f860d526
FF		 1970 */
1971 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
bec9a94b
BB		 1972 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
1973 ath9k_hw_settsf64(ah, tsf + tsf_offset);
f860d526
FF		 1974 }
1975
15d2b585 1976 ath9k_hw_init_mfp(ah);
0ced0e17 1977
81c507a8 1978 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1979 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1980 ah->eep_ops->set_board_values(ah, chan);
a7765828 1981
15d2b585 1982 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1983
8fe65368 1984 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1985 if (r)
1986 return r;
f078f209 1987
dfdac8ac
FF		 1988 ath9k_hw_set_clockrate(ah);
1989
15d2b585 1990 ath9k_hw_init_queues(ah);
2660b81a 1991 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1992 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1993 ath9k_hw_init_qos(ah);
1994
2660b81a 1995 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
b2d70d49 1996 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
3b319aae 1997
0005baf4 1998 ath9k_hw_init_global_settings(ah);
f078f209 1999
fe2b6afb
FF		 2000 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
2001 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2002 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2003 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2004 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2005 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2006 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 2007 }
2008
ca7a4deb 2009 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 2010
2011 ath9k_hw_set_dma(ah);
2012
ed6ebd8b
RM		 2013 if (!ath9k_hw_mci_is_enabled(ah))
2014 REG_WRITE(ah, AR_OBS, 8);
f078f209 2015
7b37e0d4 2016 ENABLE_REG_RMW_BUFFER(ah);
0ce024cb 2017 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 2018 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
2019 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 2020 }
2021
7f62a136
VT		 2022 if (ah->config.tx_intr_mitigation) {
2023 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2024 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2025 }
7b37e0d4 2026 REG_RMW_BUFFER_FLUSH(ah);
7f62a136 2027
f078f209
LR		 2028 ath9k_hw_init_bb(ah, chan);
2029
77a5a664 2030 if (caldata) {
4b9b42bf
SM		 2031 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2032 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 2033 }
ae8d2858 2034 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2035 return -EIO;
f078f209 2036
5955b2b0 2037 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 2038 return -EIO;
63d32967 2039
7d0d0df0 2040 ENABLE_REGWRITE_BUFFER(ah);
f078f209 2041
8fe65368 2042 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 2043 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2044
7d0d0df0 2045 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2046
f4c34af4
SM		 2047 ath9k_hw_gen_timer_start_tsf2(ah);
2048
15d2b585 2049 ath9k_hw_init_desc(ah);
f078f209 2050
dbccdd1d 2051 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2052 ath9k_hw_btcoex_enable(ah);
2053
5955b2b0 2054 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2055 ar9003_mci_check_bt(ah);
63d32967 2056
7b89fccf
FF		 2057 if (AR_SREV_9300_20_OR_LATER(ah)) {
2058 ath9k_hw_loadnf(ah, chan);
2059 ath9k_hw_start_nfcal(ah, true);
2060 }
1fe860ed 2061
a7abaf7d 2062 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 2063 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 2064
2065 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 2066 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 2067
691680b8
FF		 2068 ath9k_hw_apply_gpio_override(ah);
2069
7bdea96a 2070 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 2071 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2072
4307b0fe
LB		 2073 if (ah->hw->conf.radar_enabled) {
2074 /* set HW specific DFS configuration */
7a0a260a 2075 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
4307b0fe
LB		 2076 ath9k_hw_set_radar_params(ah);
2077 }
2078
ae8d2858 2079 return 0;
f078f209 2080}
7322fd19 2081EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2082
f1dc5600
S		 2083/******************************/
2084/* Power Management (Chipset) */
2085/******************************/
2086
42d5bc3f
LR		 2087/*
2088 * Notify Power Mgt is disabled in self-generated frames.
2089 * If requested, force chip to sleep.
2090 */
31604cf0 2091static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2092{
f1dc5600 2093 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2094
a4a2954f 2095 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2096 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2097 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2098 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2099 /* xxx Required for WLAN only case ? */
2100 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2101 udelay(100);
2102 }
2577c6e8 2103
31604cf0
SM		 2104 /*
2105 * Clear the RTC force wake bit to allow the
2106 * mac to go to sleep.
2107 */
2108 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2109
153dccd4 2110 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2111 udelay(100);
2577c6e8 2112
31604cf0
SM		 2113 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2114 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2115
31604cf0
SM		 2116 /* Shutdown chip. Active low */
2117 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2118 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2119 udelay(2);
f1dc5600 2120 }
9a658d2b
LR		 2121
2122 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2123 if (AR_SREV_9300_20_OR_LATER(ah))
2124 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2125}
2126
bbd79af5
LR		 2127/*
2128 * Notify Power Management is enabled in self-generating
2129 * frames. If request, set power mode of chip to
2130 * auto/normal. Duration in units of 128us (1/8 TU).
2131 */
31604cf0 2132static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2133{
31604cf0 2134 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2135
f1dc5600 2136 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2137
31604cf0
SM		 2138 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2139 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2140 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2141 AR_RTC_FORCE_WAKE_ON_INT);
2142 } else {
2577c6e8 2143
31604cf0
SM		 2144 /* When chip goes into network sleep, it could be waken
2145 * up by MCI_INT interrupt caused by BT's HW messages
2146 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2147 * rate (~100us). This will cause chip to leave and
2148 * re-enter network sleep mode frequently, which in
2149 * consequence will have WLAN MCI HW to generate lots of
2150 * SYS_WAKING and SYS_SLEEPING messages which will make
2151 * BT CPU to busy to process.
2152 */
153dccd4
RM		 2153 if (ath9k_hw_mci_is_enabled(ah))
2154 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2155 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2156 /*
2157 * Clear the RTC force wake bit to allow the
2158 * mac to go to sleep.
2159 */
153dccd4 2160 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2161
153dccd4 2162 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2163 udelay(30);
f078f209 2164 }
9a658d2b
LR		 2165
2166 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2167 if (AR_SREV_9300_20_OR_LATER(ah))
2168 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2169}
2170
31604cf0 2171static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2172{
f1dc5600
S		 2173 u32 val;
2174 int i;
f078f209 2175
9a658d2b
LR		 2176 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2177 if (AR_SREV_9300_20_OR_LATER(ah)) {
2178 REG_WRITE(ah, AR_WA, ah->WARegVal);
2179 udelay(10);
2180 }
2181
31604cf0
SM		 2182 if ((REG_READ(ah, AR_RTC_STATUS) &
2183 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2184 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2185 return false;
f1dc5600 2186 }
31604cf0
SM		 2187 if (!AR_SREV_9300_20_OR_LATER(ah))
2188 ath9k_hw_init_pll(ah, NULL);
2189 }
2190 if (AR_SREV_9100(ah))
2191 REG_SET_BIT(ah, AR_RTC_RESET,
2192 AR_RTC_RESET_EN);
2193
2194 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2195 AR_RTC_FORCE_WAKE_EN);
04575f21 2196 if (AR_SREV_9100(ah))
3683a07b 2197 mdelay(10);
04575f21
SM		 2198 else
2199 udelay(50);
f078f209 2200
31604cf0
SM		 2201 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2202 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2203 if (val == AR_RTC_STATUS_ON)
2204 break;
2205 udelay(50);
f1dc5600
S		 2206 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2207 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2208 }
2209 if (i == 0) {
2210 ath_err(ath9k_hw_common(ah),
2211 "Failed to wakeup in %uus\n",
2212 POWER_UP_TIME / 20);
2213 return false;
f078f209
LR		 2214 }
2215
cdbe408d
RM		 2216 if (ath9k_hw_mci_is_enabled(ah))
2217 ar9003_mci_set_power_awake(ah);
2218
f1dc5600 2219 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2220
f1dc5600 2221 return true;
f078f209
LR		 2222}
2223
9ecdef4b 2224bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2225{
c46917bb 2226 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2227 int status = true;
f1dc5600
S		 2228 static const char *modes[] = {
2229 "AWAKE",
2230 "FULL-SLEEP",
2231 "NETWORK SLEEP",
2232 "UNDEFINED"
2233 };
f1dc5600 2234
cbdec975
GJ		 2235 if (ah->power_mode == mode)
2236 return status;
2237
d2182b69 2238 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2239 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2240
2241 switch (mode) {
2242 case ATH9K_PM_AWAKE:
31604cf0 2243 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2244 break;
2245 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2246 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2247 ar9003_mci_set_full_sleep(ah);
1010911e 2248
31604cf0 2249 ath9k_set_power_sleep(ah);
2660b81a 2250 ah->chip_fullsleep = true;
f1dc5600
S		 2251 break;
2252 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2253 ath9k_set_power_network_sleep(ah);
f1dc5600 2254 break;
f078f209 2255 default:
3800276a 2256 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2257 return false;
2258 }
2660b81a 2259 ah->power_mode = mode;
f1dc5600 2260
69f4aab1
LR		 2261 /*
2262 * XXX: If this warning never comes up after a while then
2263 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2264 * ath9k_hw_setpower() return type void.
2265 */
97dcec57
SM		 2266
2267 if (!(ah->ah_flags & AH_UNPLUGGED))
2268 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2269
f1dc5600 2270 return status;
f078f209 2271}
7322fd19 2272EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2273
f1dc5600
S		 2274/*******************/
2275/* Beacon Handling */
2276/*******************/
2277
cbe61d8a 2278void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2279{
f078f209
LR		 2280 int flags = 0;
2281
7d0d0df0
S		 2282 ENABLE_REGWRITE_BUFFER(ah);
2283
2660b81a 2284 switch (ah->opmode) {
d97809db 2285 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2286 REG_SET_BIT(ah, AR_TXCFG,
2287 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2288 case NL80211_IFTYPE_MESH_POINT:
d97809db 2289 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2290 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2291 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2292 TU_TO_USEC(ah->config.dma_beacon_response_time));
2293 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2294 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2295 flags |=
2296 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2297 break;
d97809db 2298 default:
d2182b69
JP		 2299 ath_dbg(ath9k_hw_common(ah), BEACON,
2300 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2301 return;
2302 break;
f078f209
LR		 2303 }
2304
dd347f2f
FF		 2305 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2306 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2307 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2308
7d0d0df0 2309 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2310
f078f209
LR		 2311 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2312}
7322fd19 2313EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2314
cbe61d8a 2315void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2316 const struct ath9k_beacon_state *bs)
f078f209
LR		 2317{
2318 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2319 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2320 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2321
7d0d0df0
S		 2322 ENABLE_REGWRITE_BUFFER(ah);
2323
4ed15762
FF		 2324 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2325 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2326 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2327
7d0d0df0 2328 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2329
f078f209
LR		 2330 REG_RMW_FIELD(ah, AR_RSSI_THR,
2331 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2332
f29f5c08 2333 beaconintval = bs->bs_intval;
f078f209
LR		 2334
2335 if (bs->bs_sleepduration > beaconintval)
2336 beaconintval = bs->bs_sleepduration;
2337
2338 dtimperiod = bs->bs_dtimperiod;
2339 if (bs->bs_sleepduration > dtimperiod)
2340 dtimperiod = bs->bs_sleepduration;
2341
2342 if (beaconintval == dtimperiod)
2343 nextTbtt = bs->bs_nextdtim;
2344 else
2345 nextTbtt = bs->bs_nexttbtt;
2346
58bb9ca8
JD		 2347 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);
2348 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);
2349 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);
2350 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);
f078f209 2351
7d0d0df0
S		 2352 ENABLE_REGWRITE_BUFFER(ah);
2353
4ed15762
FF		 2354 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2355 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2356
f1dc5600
S		 2357 REG_WRITE(ah, AR_SLEEP1,
2358 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2359 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2360
f1dc5600
S		 2361 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2362 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2363 else
2364 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2365
f1dc5600
S		 2366 REG_WRITE(ah, AR_SLEEP2,
2367 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2368
4ed15762
FF		 2369 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2370 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2371
7d0d0df0 2372 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2373
f1dc5600
S		 2374 REG_SET_BIT(ah, AR_TIMER_MODE,
2375 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2376 AR_DTIM_TIMER_EN);
f078f209 2377
4af9cf4f
S		 2378 /* TSF Out of Range Threshold */
2379 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2380}
7322fd19 2381EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2382
f1dc5600
S		 2383/*******************/
2384/* HW Capabilities */
2385/*******************/
2386
6054069a
FF		 2387static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2388{
2389 eeprom_chainmask &= chip_chainmask;
2390 if (eeprom_chainmask)
2391 return eeprom_chainmask;
2392 else
2393 return chip_chainmask;
2394}
2395
9a66af33
ZK		 2396/**
2397 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2398 * @ah: the atheros hardware data structure
2399 *
2400 * We enable DFS support upstream on chipsets which have passed a series
2401 * of tests. The testing requirements are going to be documented. Desired
2402 * test requirements are documented at:
2403 *
2404 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2405 *
2406 * Once a new chipset gets properly tested an individual commit can be used
2407 * to document the testing for DFS for that chipset.
2408 */
2409static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2410{
2411
2412 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2413 /* for temporary testing DFS with 9280 */
2414 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2415 /* AR9580 will likely be our first target to get testing on */
2416 case AR_SREV_VERSION_9580:
73e4937d 2417 return true;
9a66af33
ZK		 2418 default:
2419 return false;
2420 }
2421}
2422
a01ab81b
MP		 2423static void ath9k_gpio_cap_init(struct ath_hw *ah)
2424{
2425 struct ath9k_hw_capabilities *pCap = &ah->caps;
2426
2427 if (AR_SREV_9271(ah)) {
2428 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2429 pCap->gpio_mask = AR9271_GPIO_MASK;
2430 } else if (AR_DEVID_7010(ah)) {
2431 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2432 pCap->gpio_mask = AR7010_GPIO_MASK;
2433 } else if (AR_SREV_9287(ah)) {
2434 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2435 pCap->gpio_mask = AR9287_GPIO_MASK;
2436 } else if (AR_SREV_9285(ah)) {
2437 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2438 pCap->gpio_mask = AR9285_GPIO_MASK;
2439 } else if (AR_SREV_9280(ah)) {
2440 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2441 pCap->gpio_mask = AR9280_GPIO_MASK;
2442 } else if (AR_SREV_9300(ah)) {
2443 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2444 pCap->gpio_mask = AR9300_GPIO_MASK;
2445 } else if (AR_SREV_9330(ah)) {
2446 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2447 pCap->gpio_mask = AR9330_GPIO_MASK;
2448 } else if (AR_SREV_9340(ah)) {
2449 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2450 pCap->gpio_mask = AR9340_GPIO_MASK;
2451 } else if (AR_SREV_9462(ah)) {
2452 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2453 pCap->gpio_mask = AR9462_GPIO_MASK;
2454 } else if (AR_SREV_9485(ah)) {
2455 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2456 pCap->gpio_mask = AR9485_GPIO_MASK;
2457 } else if (AR_SREV_9531(ah)) {
2458 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2459 pCap->gpio_mask = AR9531_GPIO_MASK;
2460 } else if (AR_SREV_9550(ah)) {
2461 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2462 pCap->gpio_mask = AR9550_GPIO_MASK;
2463 } else if (AR_SREV_9561(ah)) {
2464 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2465 pCap->gpio_mask = AR9561_GPIO_MASK;
2466 } else if (AR_SREV_9565(ah)) {
2467 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2468 pCap->gpio_mask = AR9565_GPIO_MASK;
2469 } else if (AR_SREV_9580(ah)) {
2470 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2471 pCap->gpio_mask = AR9580_GPIO_MASK;
2472 } else {
2473 pCap->num_gpio_pins = AR_NUM_GPIO;
2474 pCap->gpio_mask = AR_GPIO_MASK;
2475 }
2476}
2477
a9a29ce6 2478int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2479{
2660b81a 2480 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2481 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2482 struct ath_common *common = ath9k_hw_common(ah);
608b88cb 2483
0ff2b5c0 2484 u16 eeval;
47c80de6 2485 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2486
f74df6fb 2487 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2488 regulatory->current_rd = eeval;
f078f209 2489
2660b81a 2490 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2491 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2492 if (regulatory->current_rd == 0x64 ||
2493 regulatory->current_rd == 0x65)
2494 regulatory->current_rd += 5;
2495 else if (regulatory->current_rd == 0x41)
2496 regulatory->current_rd = 0x43;
d2182b69
JP		 2497 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2498 regulatory->current_rd);
f1dc5600 2499 }
f078f209 2500
f74df6fb 2501 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3468968e
FF		 2502
2503 if (eeval & AR5416_OPFLAGS_11A) {
2504 if (ah->disable_5ghz)
2505 ath_warn(common, "disabling 5GHz band\n");
2506 else
2507 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
a9a29ce6
GJ		 2508 }
2509
3468968e
FF		 2510 if (eeval & AR5416_OPFLAGS_11G) {
2511 if (ah->disable_2ghz)
2512 ath_warn(common, "disabling 2GHz band\n");
2513 else
2514 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2515 }
f078f209 2516
3468968e
FF		 2517 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2518 ath_err(common, "both bands are disabled\n");
2519 return -EINVAL;
2520 }
f1dc5600 2521
db7b542e
MP		 2522 ath9k_gpio_cap_init(ah);
2523
e41db61d
SM		 2524 if (AR_SREV_9485(ah) ||
2525 AR_SREV_9285(ah) ||
2526 AR_SREV_9330(ah) ||
2527 AR_SREV_9565(ah))
ee79ccd9 2528 pCap->chip_chainmask = 1;
6054069a 2529 else if (!AR_SREV_9280_20_OR_LATER(ah))
ee79ccd9
SM		 2530 pCap->chip_chainmask = 7;
2531 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2532 AR_SREV_9340(ah) ||
2533 AR_SREV_9462(ah) ||
2534 AR_SREV_9531(ah))
2535 pCap->chip_chainmask = 3;
6054069a 2536 else
ee79ccd9 2537 pCap->chip_chainmask = 7;
6054069a 2538
f74df6fb 2539 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2540 /*
2541 * For AR9271 we will temporarilly uses the rx chainmax as read from
2542 * the EEPROM.
2543 */
8147f5de 2544 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2545 !(eeval & AR5416_OPFLAGS_11A) &&
2546 !(AR_SREV_9271(ah)))
2547 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2548 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2549 else if (AR_SREV_9100(ah))
2550 pCap->rx_chainmask = 0x7;
8147f5de 2551 else
d7e7d229 2552 /* Use rx_chainmask from EEPROM. */
8147f5de 2553 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2554
ee79ccd9
SM		 2555 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2556 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2557 ah->txchainmask = pCap->tx_chainmask;
2558 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2559
7a37081e 2560 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2561
02d2ebb2
FF		 2562 /* enable key search for every frame in an aggregate */
2563 if (AR_SREV_9300_20_OR_LATER(ah))
2564 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2565
ce2220d1
BR		 2566 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2567
0db156e9 2568 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2569 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2570 else
2571 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2572
1b2538b2 2573 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2574 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2575 else
f1dc5600 2576 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2577
74e13060 2578#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2579 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2580 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2581 ah->rfkill_gpio =
2582 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2583 ah->rfkill_polarity =
2584 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2585
2586 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2587 }
f1dc5600 2588#endif
d5d1154f 2589 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2590 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2591 else
2592 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2593
e7594072 2594 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2595 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2596 else
2597 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2598
ceb26445 2599 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2600 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
ede6a5e7
MP		 2601 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2602 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2603 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2604
ceb26445
VT		 2605 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2606 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2607 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2608 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2609 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2610 } else {
2611 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2612 if (AR_SREV_9280_20(ah))
6b42e8d0 2613 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2614 }
1adf02ff 2615
6c84ce08
VT		 2616 if (AR_SREV_9300_20_OR_LATER(ah))
2617 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2618
ede6a5e7
MP		 2619 if (AR_SREV_9561(ah))
2620 ah->ent_mode = 0x3BDA000;
2621 else if (AR_SREV_9300_20_OR_LATER(ah))
6ee63f55
SB		 2622 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2623
a42acef0 2624 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2625 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2626
f85c3371 2627 if (AR_SREV_9285(ah)) {
754dc536
VT		 2628 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2629 ant_div_ctl1 =
2630 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2631 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2632 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2633 ath_info(common, "Enable LNA combining\n");
2634 }
754dc536 2635 }
f85c3371
SM		 2636 }
2637
ea066d5a
MSS		 2638 if (AR_SREV_9300_20_OR_LATER(ah)) {
2639 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2640 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2641 }
2642
06236e53 2643 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2644 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2645 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2646 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2647 ath_info(common, "Enable LNA combining\n");
2648 }
21d2c63a 2649 }
754dc536 2650
9a66af33
ZK		 2651 if (ath9k_hw_dfs_tested(ah))
2652 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2653
47c80de6
VT		 2654 tx_chainmask = pCap->tx_chainmask;
2655 rx_chainmask = pCap->rx_chainmask;
2656 while (tx_chainmask || rx_chainmask) {
2657 if (tx_chainmask & BIT(0))
2658 pCap->max_txchains++;
2659 if (rx_chainmask & BIT(0))
2660 pCap->max_rxchains++;
2661
2662 tx_chainmask >>= 1;
2663 rx_chainmask >>= 1;
2664 }
2665
a4a2954f 2666 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2667 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2668 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2669
2b5e54e2 2670 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2671 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2672 }
2673
0f21ee8d
SM		 2674 if (AR_SREV_9300_20_OR_LATER(ah) &&
2675 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2676 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2677
12a44422
SM		 2678#ifdef CONFIG_ATH9K_WOW
2679 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2680 ah->wow.max_patterns = MAX_NUM_PATTERN;
2681 else
2682 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2683#endif
2684
a9a29ce6 2685 return 0;
f078f209
LR		 2686}
2687
f1dc5600
S		 2688/****************************/
2689/* GPIO / RFKILL / Antennae */
2690/****************************/
f078f209 2691
b2d70d49 2692static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
f1dc5600
S		 2693{
2694 int addr;
2695 u32 gpio_shift, tmp;
f078f209 2696
f1dc5600
S		 2697 if (gpio > 11)
2698 addr = AR_GPIO_OUTPUT_MUX3;
2699 else if (gpio > 5)
2700 addr = AR_GPIO_OUTPUT_MUX2;
2701 else
2702 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2703
f1dc5600 2704 gpio_shift = (gpio % 6) * 5;
f078f209 2705
b2d70d49
MP		 2706 if (AR_SREV_9280_20_OR_LATER(ah) ||
2707 (addr != AR_GPIO_OUTPUT_MUX1)) {
f1dc5600
S		 2708 REG_RMW(ah, addr, (type << gpio_shift),
2709 (0x1f << gpio_shift));
f078f209 2710 } else {
f1dc5600
S		 2711 tmp = REG_READ(ah, addr);
2712 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2713 tmp &= ~(0x1f << gpio_shift);
2714 tmp |= (type << gpio_shift);
2715 REG_WRITE(ah, addr, tmp);
f078f209 2716 }
f078f209
LR		 2717}
2718
b2d70d49
MP		 2719/* BSP should set the corresponding MUX register correctly.
2720 */
2721static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2722 const char *label)
f078f209 2723{
b2d70d49
MP		 2724 if (ah->caps.gpio_requested & BIT(gpio))
2725 return;
f078f209 2726
b2d70d49
MP		 2727 /* may be requested by BSP, free anyway */
2728 gpio_free(gpio);
f078f209 2729
b2d70d49 2730 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label))
88c1f4f6 2731 return;
f078f209 2732
b2d70d49 2733 ah->caps.gpio_requested |= BIT(gpio);
f078f209
LR		 2734}
2735
b2d70d49
MP		 2736static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2737 u32 ah_signal_type)
f078f209 2738{
b2d70d49 2739 u32 gpio_set, gpio_shift = gpio;
f078f209 2740
88c1f4f6 2741 if (AR_DEVID_7010(ah)) {
b2d70d49
MP		 2742 gpio_set = out ?
2743 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;
2744 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2745 AR7010_GPIO_OE_MASK << gpio_shift);
2746 } else if (AR_SREV_SOC(ah)) {
2747 gpio_set = out ? 1 : 0;
2748 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2749 gpio_set << gpio_shift);
2750 } else {
2751 gpio_shift = gpio << 1;
2752 gpio_set = out ?
2753 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;
2754 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2755 AR_GPIO_OE_OUT_DRV << gpio_shift);
2756
2757 if (out)
2758 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2759 }
f078f209
LR		 2760}
2761
b2d70d49
MP		 2762static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2763 const char *label, u32 ah_signal_type)
f078f209 2764{
b2d70d49 2765 WARN_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2766
b2d70d49
MP		 2767 if (BIT(gpio) & ah->caps.gpio_mask)
2768 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2769 else if (AR_SREV_SOC(ah))
2770 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2771 else
2772 WARN_ON(1);
2773}
f078f209 2774
b2d70d49
MP		 2775void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2776{
2777 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
f078f209 2778}
b2d70d49 2779EXPORT_SYMBOL(ath9k_hw_gpio_request_in);
f078f209 2780
b2d70d49
MP		 2781void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2782 u32 ah_signal_type)
f078f209 2783{
b2d70d49
MP		 2784 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2785}
2786EXPORT_SYMBOL(ath9k_hw_gpio_request_out);
2787
2788void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2789{
2790 if (!AR_SREV_SOC(ah))
88c1f4f6 2791 return;
b2d70d49
MP		 2792
2793 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2794
2795 if (ah->caps.gpio_requested & BIT(gpio)) {
2796 gpio_free(gpio);
2797 ah->caps.gpio_requested &= ~BIT(gpio);
88c1f4f6 2798 }
b2d70d49
MP		 2799}
2800EXPORT_SYMBOL(ath9k_hw_gpio_free);
88c1f4f6 2801
b2d70d49
MP		 2802u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2803{
2804 u32 val = 0xffffffff;
5b5fa355 2805
b2d70d49
MP		 2806#define MS_REG_READ(x, y) \
2807 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y))
2808
2809 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2810
2811 if (BIT(gpio) & ah->caps.gpio_mask) {
2812 if (AR_SREV_9271(ah))
2813 val = MS_REG_READ(AR9271, gpio);
2814 else if (AR_SREV_9287(ah))
2815 val = MS_REG_READ(AR9287, gpio);
2816 else if (AR_SREV_9285(ah))
2817 val = MS_REG_READ(AR9285, gpio);
2818 else if (AR_SREV_9280(ah))
2819 val = MS_REG_READ(AR928X, gpio);
2820 else if (AR_DEVID_7010(ah))
2821 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2822 else if (AR_SREV_9300_20_OR_LATER(ah))
2823 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio);
2824 else
2825 val = MS_REG_READ(AR, gpio);
2826 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2827 val = gpio_get_value(gpio) & BIT(gpio);
2828 } else {
2829 WARN_ON(1);
2830 }
2831
91851cc7 2832 return !!val;
f078f209 2833}
b2d70d49 2834EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2835
b2d70d49 2836void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
61b559de 2837{
b2d70d49 2838 WARN_ON(gpio >= ah->caps.num_gpio_pins);
61b559de 2839
b2d70d49
MP		 2840 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2841 val = !val;
2842 else
2843 val = !!val;
2844
2845 if (BIT(gpio) & ah->caps.gpio_mask) {
2846 u32 out_addr = AR_DEVID_7010(ah) ?
2847 AR7010_GPIO_OUT : AR_GPIO_IN_OUT;
2848
2849 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2850 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2851 gpio_set_value(gpio, val);
2852 } else {
2853 WARN_ON(1);
2854 }
61b559de 2855}
b2d70d49 2856EXPORT_SYMBOL(ath9k_hw_set_gpio);
61b559de 2857
cbe61d8a 2858void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2859{
f1dc5600 2860 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2861}
7322fd19 2862EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2863
f1dc5600
S		 2864/*********************/
2865/* General Operation */
2866/*********************/
2867
cbe61d8a 2868u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2869{
f1dc5600
S		 2870 u32 bits = REG_READ(ah, AR_RX_FILTER);
2871 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2872
f1dc5600
S		 2873 if (phybits & AR_PHY_ERR_RADAR)
2874 bits |= ATH9K_RX_FILTER_PHYRADAR;
2875 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2876 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2877
f1dc5600 2878 return bits;
f078f209 2879}
7322fd19 2880EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2881
cbe61d8a 2882void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2883{
f1dc5600 2884 u32 phybits;
f078f209 2885
7d0d0df0
S		 2886 ENABLE_REGWRITE_BUFFER(ah);
2887
7ea310be
S		 2888 REG_WRITE(ah, AR_RX_FILTER, bits);
2889
f1dc5600
S		 2890 phybits = 0;
2891 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2892 phybits |= AR_PHY_ERR_RADAR;
2893 if (bits & ATH9K_RX_FILTER_PHYERR)
2894 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2895 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2896
f1dc5600 2897 if (phybits)
ca7a4deb 2898 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2899 else
ca7a4deb 2900 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2901
2902 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2903}
7322fd19 2904EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2905
cbe61d8a 2906bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2907{
99922a45
RM		 2908 if (ath9k_hw_mci_is_enabled(ah))
2909 ar9003_mci_bt_gain_ctrl(ah);
2910
63a75b91
SB		 2911 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2912 return false;
2913
2914 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2915 ah->htc_reset_init = true;
63a75b91 2916 return true;
f1dc5600 2917}
7322fd19 2918EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2919
cbe61d8a 2920bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2921{
9ecdef4b 2922 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2923 return false;
f078f209 2924
63a75b91
SB		 2925 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2926 return false;
2927
2928 ath9k_hw_init_pll(ah, NULL);
2929 return true;
f078f209 2930}
7322fd19 2931EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2932
ca2c68cc
FF		 2933static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2934{
2935 enum eeprom_param gain_param;
2936
2937 if (IS_CHAN_2GHZ(chan))
2938 gain_param = EEP_ANTENNA_GAIN_2G;
2939 else
2940 gain_param = EEP_ANTENNA_GAIN_5G;
2941
2942 return ah->eep_ops->get_eeprom(ah, gain_param);
2943}
2944
64ea57d0
GJ		 2945void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2946 bool test)
ca2c68cc
FF		 2947{
2948 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2949 struct ieee80211_channel *channel;
71f5137b 2950 int chan_pwr, new_pwr;
bd7d62f0 2951 u16 ctl = NO_CTL;
ca2c68cc
FF		 2952
2953 if (!chan)
2954 return;
2955
bd7d62f0
FF		 2956 if (!test)
2957 ctl = ath9k_regd_get_ctl(reg, chan);
2958
ca2c68cc
FF		 2959 channel = chan->chan;
2960 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2961 new_pwr = min_t(int, chan_pwr, reg->power_limit);
ca2c68cc 2962
bd7d62f0 2963 ah->eep_ops->set_txpower(ah, chan, ctl,
71f5137b 2964 get_antenna_gain(ah, chan), new_pwr, test);
ca2c68cc
FF		 2965}
2966
de40f316 2967void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2968{
ca2c68cc 2969 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2970 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2971 struct ieee80211_channel *channel = chan->chan;
9c204b46 2972
48ef5c42 2973 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2974 if (test)
ca2c68cc 2975 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2976
64ea57d0 2977 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2978
ca2c68cc
FF		 2979 if (test)
2980 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2981}
7322fd19 2982EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2983
cbe61d8a 2984void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2985{
2660b81a 2986 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2987}
7322fd19 2988EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2989
cbe61d8a 2990void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2991{
f1dc5600
S		 2992 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2993 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2994}
7322fd19 2995EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2996
f2b2143e 2997void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2998{
1510718d
LR		 2999 struct ath_common *common = ath9k_hw_common(ah);
3000
3001 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3002 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3003 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 3004}
7322fd19 3005EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 3006
1c0fc65e
BP		 3007#define ATH9K_MAX_TSF_READ 10
3008
cbe61d8a 3009u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 3010{
1c0fc65e
BP		 3011 u32 tsf_lower, tsf_upper1, tsf_upper2;
3012 int i;
3013
3014 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
3015 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
3016 tsf_lower = REG_READ(ah, AR_TSF_L32);
3017 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
3018 if (tsf_upper2 == tsf_upper1)
3019 break;
3020 tsf_upper1 = tsf_upper2;
3021 }
f078f209 3022
1c0fc65e 3023 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 3024
1c0fc65e 3025 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 3026}
7322fd19 3027EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 3028
cbe61d8a 3029void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 3030{
27abe060 3031 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 3032 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 3033}
7322fd19 3034EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 3035
cbe61d8a 3036void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 3037{
f9b604f6
GJ		 3038 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3039 AH_TSF_WRITE_TIMEOUT))
d2182b69 3040 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 3041 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 3042
f1dc5600
S		 3043 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3044}
7322fd19 3045EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 3046
60ca9f87 3047void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 3048{
60ca9f87 3049 if (set)
2660b81a 3050 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3051 else
2660b81a 3052 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 3053}
7322fd19 3054EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 3055
e4744ec7 3056void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 3057{
3058 u32 macmode;
3059
e4744ec7 3060 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3061 macmode = AR_2040_JOINED_RX_CLEAR;
3062 else
3063 macmode = 0;
f078f209 3064
f1dc5600 3065 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3066}
ff155a45
VT		 3067
3068/* HW Generic timers configuration */
3069
3070static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3071{
3072 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3073 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3074 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3075 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3076 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3077 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3078 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3079 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3080 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3081 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3082 AR_NDP2_TIMER_MODE, 0x0002},
3083 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3084 AR_NDP2_TIMER_MODE, 0x0004},
3085 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3086 AR_NDP2_TIMER_MODE, 0x0008},
3087 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3088 AR_NDP2_TIMER_MODE, 0x0010},
3089 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3090 AR_NDP2_TIMER_MODE, 0x0020},
3091 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3092 AR_NDP2_TIMER_MODE, 0x0040},
3093 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3094 AR_NDP2_TIMER_MODE, 0x0080}
3095};
3096
3097/* HW generic timer primitives */
3098
dd347f2f 3099u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 3100{
3101 return REG_READ(ah, AR_TSF_L32);
3102}
dd347f2f 3103EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45 3104
f4c34af4
SM		 3105void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3106{
3107 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3108
3109 if (timer_table->tsf2_enabled) {
3110 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3111 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3112 }
3113}
3114
ff155a45
VT		 3115struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3116 void (*trigger)(void *),
3117 void (*overflow)(void *),
3118 void *arg,
3119 u8 timer_index)
3120{
3121 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3122 struct ath_gen_timer *timer;
3123
c67ce339 3124 if ((timer_index < AR_FIRST_NDP_TIMER) ||
f4c34af4
SM		 3125 (timer_index >= ATH_MAX_GEN_TIMER))
3126 return NULL;
3127
3128 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3129 !AR_SREV_9300_20_OR_LATER(ah))
c67ce339
FF		 3130 return NULL;
3131
ff155a45 3132 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 3133 if (timer == NULL)
ff155a45 3134 return NULL;
ff155a45
VT		 3135
3136 /* allocate a hardware generic timer slot */
3137 timer_table->timers[timer_index] = timer;
3138 timer->index = timer_index;
3139 timer->trigger = trigger;
3140 timer->overflow = overflow;
3141 timer->arg = arg;
3142
f4c34af4
SM		 3143 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3144 timer_table->tsf2_enabled = true;
3145 ath9k_hw_gen_timer_start_tsf2(ah);
3146 }
3147
ff155a45
VT		 3148 return timer;
3149}
7322fd19 3150EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3151
cd9bf689
LR		 3152void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3153 struct ath_gen_timer *timer,
c67ce339 3154 u32 timer_next,
cd9bf689 3155 u32 timer_period)
ff155a45
VT		 3156{
3157 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 3158 u32 mask = 0;
788f6875 3159
c67ce339 3160 timer_table->timer_mask |= BIT(timer->index);
ff155a45 3161
ff155a45
VT		 3162 /*
3163 * Program generic timer registers
3164 */
3165 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3166 timer_next);
3167 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3168 timer_period);
3169 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3170 gen_tmr_configuration[timer->index].mode_mask);
3171
a4a2954f 3172 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3173 /*
423e38e8 3174 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3175 * to use. But we still follow the old rule, 0 - 7 use tsf and
3176 * 8 - 15 use tsf2.
3177 */
3178 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3179 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3180 (1 << timer->index));
3181 else
3182 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3183 (1 << timer->index));
3184 }
3185
c67ce339
FF		 3186 if (timer->trigger)
3187 mask |= SM(AR_GENTMR_BIT(timer->index),
3188 AR_IMR_S5_GENTIMER_TRIG);
3189 if (timer->overflow)
3190 mask |= SM(AR_GENTMR_BIT(timer->index),
3191 AR_IMR_S5_GENTIMER_THRESH);
3192
3193 REG_SET_BIT(ah, AR_IMR_S5, mask);
3194
3195 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3196 ah->imask |= ATH9K_INT_GENTIMER;
3197 ath9k_hw_set_interrupts(ah);
3198 }
ff155a45 3199}
7322fd19 3200EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3201
cd9bf689 3202void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3203{
3204 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3205
ff155a45
VT		 3206 /* Clear generic timer enable bits. */
3207 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3208 gen_tmr_configuration[timer->index].mode_mask);
3209
b7f59766
SM		 3210 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3211 /*
3212 * Need to switch back to TSF if it was using TSF2.
3213 */
3214 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3215 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3216 (1 << timer->index));
3217 }
3218 }
3219
ff155a45
VT		 3220 /* Disable both trigger and thresh interrupt masks */
3221 REG_CLR_BIT(ah, AR_IMR_S5,
3222 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3223 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3224
c67ce339
FF		 3225 timer_table->timer_mask &= ~BIT(timer->index);
3226
3227 if (timer_table->timer_mask == 0) {
3228 ah->imask &= ~ATH9K_INT_GENTIMER;
3229 ath9k_hw_set_interrupts(ah);
3230 }
ff155a45 3231}
7322fd19 3232EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3233
3234void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3235{
3236 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3237
3238 /* free the hardware generic timer slot */
3239 timer_table->timers[timer->index] = NULL;
3240 kfree(timer);
3241}
7322fd19 3242EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3243
3244/*
3245 * Generic Timer Interrupts handling
3246 */
3247void ath_gen_timer_isr(struct ath_hw *ah)
3248{
3249 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3250 struct ath_gen_timer *timer;
c67ce339
FF		 3251 unsigned long trigger_mask, thresh_mask;
3252 unsigned int index;
ff155a45
VT		 3253
3254 /* get hardware generic timer interrupt status */
3255 trigger_mask = ah->intr_gen_timer_trigger;
3256 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3257 trigger_mask &= timer_table->timer_mask;
3258 thresh_mask &= timer_table->timer_mask;
ff155a45 3259
c67ce339 3260 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3261 timer = timer_table->timers[index];
c67ce339
FF		 3262 if (!timer)
3263 continue;
3264 if (!timer->overflow)
3265 continue;
a6a172b2
FF		 3266
3267 trigger_mask &= ~BIT(index);
ff155a45
VT		 3268 timer->overflow(timer->arg);
3269 }
3270
c67ce339 3271 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3272 timer = timer_table->timers[index];
c67ce339
FF		 3273 if (!timer)
3274 continue;
3275 if (!timer->trigger)
3276 continue;
ff155a45
VT		 3277 timer->trigger(timer->arg);
3278 }
3279}
7322fd19 3280EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3281
05020d23
S		 3282/********/
3283/* HTC */
3284/********/
3285
2da4f01a
LR		 3286static struct {
3287 u32 version;
3288 const char * name;
3289} ath_mac_bb_names[] = {
3290 /* Devices with external radios */
3291 { AR_SREV_VERSION_5416_PCI, "5416" },
3292 { AR_SREV_VERSION_5416_PCIE, "5418" },
3293 { AR_SREV_VERSION_9100, "9100" },
3294 { AR_SREV_VERSION_9160, "9160" },
3295 /* Single-chip solutions */
3296 { AR_SREV_VERSION_9280, "9280" },
3297 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3298 { AR_SREV_VERSION_9287, "9287" },
3299 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3300 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3301 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3302 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3303 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3304 { AR_SREV_VERSION_9462, "9462" },
485124cb 3305 { AR_SREV_VERSION_9550, "9550" },
77fac465 3306 { AR_SREV_VERSION_9565, "9565" },
c08148bb 3307 { AR_SREV_VERSION_9531, "9531" },
1165dd90 3308 { AR_SREV_VERSION_9561, "9561" },
2da4f01a
LR		 3309};
3310
3311/* For devices with external radios */
3312static struct {
3313 u16 version;
3314 const char * name;
3315} ath_rf_names[] = {
3316 { 0, "5133" },
3317 { AR_RAD5133_SREV_MAJOR, "5133" },
3318 { AR_RAD5122_SREV_MAJOR, "5122" },
3319 { AR_RAD2133_SREV_MAJOR, "2133" },
3320 { AR_RAD2122_SREV_MAJOR, "2122" }
3321};
3322
3323/*
3324 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3325 */
f934c4d9 3326static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3327{
3328 int i;
3329
3330 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3331 if (ath_mac_bb_names[i].version == mac_bb_version) {
3332 return ath_mac_bb_names[i].name;
3333 }
3334 }
3335
3336 return "????";
3337}
2da4f01a
LR		 3338
3339/*
3340 * Return the RF name. "????" is returned if the RF is unknown.
3341 * Used for devices with external radios.
3342 */
f934c4d9 3343static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3344{
3345 int i;
3346
3347 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3348 if (ath_rf_names[i].version == rf_version) {
3349 return ath_rf_names[i].name;
3350 }
3351 }
3352
3353 return "????";
3354}
f934c4d9
LR		 3355
3356void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3357{
3358 int used;
3359
3360 /* chipsets >= AR9280 are single-chip */
7a37081e 3361 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3362 used = scnprintf(hw_name, len,
3363 "Atheros AR%s Rev:%x",
3364 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3365 ah->hw_version.macRev);
f934c4d9
LR		 3366 }
3367 else {
5e88ba62
ZK		 3368 used = scnprintf(hw_name, len,
3369 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3370 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3371 ah->hw_version.macRev,
3372 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3373 & AR_RADIO_SREV_MAJOR)),
3374 ah->hw_version.phyRev);
f934c4d9
LR		 3375 }
3376
3377 hw_name[used] = '\0';
3378}
3379EXPORT_SYMBOL(ath9k_hw_name);
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