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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ce111bad LR |
21 | static void ath_cache_conf_rate(struct ath_softc *sc, |
22 | struct ieee80211_conf *conf) | |
ff37e337 | 23 | { |
030bb495 LR |
24 | switch (conf->channel->band) { |
25 | case IEEE80211_BAND_2GHZ: | |
26 | if (conf_is_ht20(conf)) | |
545750d3 | 27 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; |
030bb495 | 28 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 29 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; |
030bb495 | 30 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 31 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; |
96742256 | 32 | else |
545750d3 | 33 | sc->cur_rate_mode = ATH9K_MODE_11G; |
030bb495 LR |
34 | break; |
35 | case IEEE80211_BAND_5GHZ: | |
36 | if (conf_is_ht20(conf)) | |
545750d3 | 37 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; |
030bb495 | 38 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 39 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; |
030bb495 | 40 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 41 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; |
030bb495 | 42 | else |
545750d3 | 43 | sc->cur_rate_mode = ATH9K_MODE_11A; |
030bb495 LR |
44 | break; |
45 | default: | |
ce111bad | 46 | BUG_ON(1); |
030bb495 LR |
47 | break; |
48 | } | |
ff37e337 S |
49 | } |
50 | ||
51 | static void ath_update_txpow(struct ath_softc *sc) | |
52 | { | |
cbe61d8a | 53 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 54 | |
17d7904d S |
55 | if (sc->curtxpow != sc->config.txpowlimit) { |
56 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 | 57 | /* read back in case value is clamped */ |
9cc3271f | 58 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
ff37e337 S |
59 | } |
60 | } | |
61 | ||
62 | static u8 parse_mpdudensity(u8 mpdudensity) | |
63 | { | |
64 | /* | |
65 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
66 | * 0 for no restriction | |
67 | * 1 for 1/4 us | |
68 | * 2 for 1/2 us | |
69 | * 3 for 1 us | |
70 | * 4 for 2 us | |
71 | * 5 for 4 us | |
72 | * 6 for 8 us | |
73 | * 7 for 16 us | |
74 | */ | |
75 | switch (mpdudensity) { | |
76 | case 0: | |
77 | return 0; | |
78 | case 1: | |
79 | case 2: | |
80 | case 3: | |
81 | /* Our lower layer calculations limit our precision to | |
82 | 1 microsecond */ | |
83 | return 1; | |
84 | case 4: | |
85 | return 2; | |
86 | case 5: | |
87 | return 4; | |
88 | case 6: | |
89 | return 8; | |
90 | case 7: | |
91 | return 16; | |
92 | default: | |
93 | return 0; | |
94 | } | |
95 | } | |
96 | ||
82880a7c VT |
97 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
98 | struct ieee80211_hw *hw) | |
99 | { | |
100 | struct ieee80211_channel *curchan = hw->conf.channel; | |
101 | struct ath9k_channel *channel; | |
102 | u8 chan_idx; | |
103 | ||
104 | chan_idx = curchan->hw_value; | |
105 | channel = &sc->sc_ah->channels[chan_idx]; | |
106 | ath9k_update_ichannel(sc, hw, channel); | |
107 | return channel; | |
108 | } | |
109 | ||
55624204 | 110 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
111 | { |
112 | unsigned long flags; | |
113 | bool ret; | |
114 | ||
9ecdef4b LR |
115 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
116 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
117 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
118 | |
119 | return ret; | |
120 | } | |
121 | ||
a91d75ae LR |
122 | void ath9k_ps_wakeup(struct ath_softc *sc) |
123 | { | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
127 | if (++sc->ps_usecount != 1) | |
128 | goto unlock; | |
129 | ||
9ecdef4b | 130 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
131 | |
132 | unlock: | |
133 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
134 | } | |
135 | ||
136 | void ath9k_ps_restore(struct ath_softc *sc) | |
137 | { | |
138 | unsigned long flags; | |
139 | ||
140 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
141 | if (--sc->ps_usecount != 0) | |
142 | goto unlock; | |
143 | ||
1dbfd9d4 VN |
144 | if (sc->ps_idle) |
145 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
146 | else if (sc->ps_enabled && | |
147 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
148 | PS_WAIT_FOR_CAB | |
149 | PS_WAIT_FOR_PSPOLL_DATA | | |
150 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 151 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
152 | |
153 | unlock: | |
154 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
155 | } | |
156 | ||
5ee08656 FF |
157 | static void ath_start_ani(struct ath_common *common) |
158 | { | |
159 | struct ath_hw *ah = common->ah; | |
160 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
161 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
162 | ||
163 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
164 | return; | |
165 | ||
166 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
167 | return; | |
168 | ||
169 | common->ani.longcal_timer = timestamp; | |
170 | common->ani.shortcal_timer = timestamp; | |
171 | common->ani.checkani_timer = timestamp; | |
172 | ||
173 | mod_timer(&common->ani.timer, | |
174 | jiffies + | |
175 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
176 | } | |
177 | ||
ff37e337 S |
178 | /* |
179 | * Set/change channels. If the channel is really being changed, it's done | |
180 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
181 | * DMA, then restart stuff. | |
182 | */ | |
0e2dedf9 JM |
183 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
184 | struct ath9k_channel *hchan) | |
ff37e337 | 185 | { |
20bd2a09 | 186 | struct ath_wiphy *aphy = hw->priv; |
cbe61d8a | 187 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 188 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 189 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 190 | bool fastcc = true, stopped; |
ae8d2858 | 191 | struct ieee80211_channel *channel = hw->conf.channel; |
20bd2a09 | 192 | struct ath9k_hw_cal_data *caldata = NULL; |
ae8d2858 | 193 | int r; |
ff37e337 S |
194 | |
195 | if (sc->sc_flags & SC_OP_INVALID) | |
196 | return -EIO; | |
197 | ||
5ee08656 FF |
198 | del_timer_sync(&common->ani.timer); |
199 | cancel_work_sync(&sc->paprd_work); | |
200 | cancel_work_sync(&sc->hw_check_work); | |
201 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
202 | ||
3cbb5dd7 VN |
203 | ath9k_ps_wakeup(sc); |
204 | ||
c0d7c7af LR |
205 | /* |
206 | * This is only performed if the channel settings have | |
207 | * actually changed. | |
208 | * | |
209 | * To switch channels clear any pending DMA operations; | |
210 | * wait long enough for the RX fifo to drain, reset the | |
211 | * hardware at the new frequency, and then re-enable | |
212 | * the relevant bits of the h/w. | |
213 | */ | |
214 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 215 | ath_drain_all_txq(sc, false); |
c0d7c7af | 216 | stopped = ath_stoprecv(sc); |
ff37e337 | 217 | |
c0d7c7af LR |
218 | /* XXX: do not flush receive queue here. We don't want |
219 | * to flush data frames already in queue because of | |
220 | * changing channel. */ | |
ff37e337 | 221 | |
5ee08656 | 222 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) |
c0d7c7af LR |
223 | fastcc = false; |
224 | ||
20bd2a09 FF |
225 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
226 | caldata = &aphy->caldata; | |
227 | ||
c46917bb | 228 | ath_print(common, ATH_DBG_CONFIG, |
1e51b2ff | 229 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", |
c46917bb | 230 | sc->sc_ah->curchan->channel, |
1e51b2ff LR |
231 | channel->center_freq, conf_is_ht40(conf), |
232 | fastcc); | |
ff37e337 | 233 | |
c0d7c7af LR |
234 | spin_lock_bh(&sc->sc_resetlock); |
235 | ||
20bd2a09 | 236 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
c0d7c7af | 237 | if (r) { |
c46917bb | 238 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 239 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
240 | "reset status %d\n", |
241 | channel->center_freq, r); | |
c0d7c7af | 242 | spin_unlock_bh(&sc->sc_resetlock); |
3989279c | 243 | goto ps_restore; |
ff37e337 | 244 | } |
c0d7c7af LR |
245 | spin_unlock_bh(&sc->sc_resetlock); |
246 | ||
c0d7c7af | 247 | if (ath_startrecv(sc) != 0) { |
c46917bb LR |
248 | ath_print(common, ATH_DBG_FATAL, |
249 | "Unable to restart recv logic\n"); | |
3989279c GJ |
250 | r = -EIO; |
251 | goto ps_restore; | |
c0d7c7af LR |
252 | } |
253 | ||
254 | ath_cache_conf_rate(sc, &hw->conf); | |
255 | ath_update_txpow(sc); | |
3069168c | 256 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c | 257 | |
5ee08656 FF |
258 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL | SC_OP_SCANNING))) { |
259 | ath_start_ani(common); | |
260 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); | |
261 | ath_beacon_config(sc, NULL); | |
262 | } | |
263 | ||
3989279c | 264 | ps_restore: |
3cbb5dd7 | 265 | ath9k_ps_restore(sc); |
3989279c | 266 | return r; |
ff37e337 S |
267 | } |
268 | ||
9f42c2b6 FF |
269 | static void ath_paprd_activate(struct ath_softc *sc) |
270 | { | |
271 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 272 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9f42c2b6 FF |
273 | int chain; |
274 | ||
20bd2a09 | 275 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
276 | return; |
277 | ||
278 | ath9k_ps_wakeup(sc); | |
ddfef792 | 279 | ar9003_paprd_enable(ah, false); |
9f42c2b6 FF |
280 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
281 | if (!(ah->caps.tx_chainmask & BIT(chain))) | |
282 | continue; | |
283 | ||
20bd2a09 | 284 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
285 | } |
286 | ||
287 | ar9003_paprd_enable(ah, true); | |
288 | ath9k_ps_restore(sc); | |
289 | } | |
290 | ||
291 | void ath_paprd_calibrate(struct work_struct *work) | |
292 | { | |
293 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
294 | struct ieee80211_hw *hw = sc->hw; | |
295 | struct ath_hw *ah = sc->sc_ah; | |
296 | struct ieee80211_hdr *hdr; | |
297 | struct sk_buff *skb = NULL; | |
298 | struct ieee80211_tx_info *tx_info; | |
299 | int band = hw->conf.channel->band; | |
300 | struct ieee80211_supported_band *sband = &sc->sbands[band]; | |
301 | struct ath_tx_control txctl; | |
20bd2a09 | 302 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9f42c2b6 FF |
303 | int qnum, ftype; |
304 | int chain_ok = 0; | |
305 | int chain; | |
306 | int len = 1800; | |
307 | int time_left; | |
308 | int i; | |
309 | ||
20bd2a09 FF |
310 | if (!caldata) |
311 | return; | |
312 | ||
9f42c2b6 FF |
313 | skb = alloc_skb(len, GFP_KERNEL); |
314 | if (!skb) | |
315 | return; | |
316 | ||
317 | tx_info = IEEE80211_SKB_CB(skb); | |
318 | ||
319 | skb_put(skb, len); | |
320 | memset(skb->data, 0, len); | |
321 | hdr = (struct ieee80211_hdr *)skb->data; | |
322 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
323 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 324 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
325 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
326 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
327 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
328 | ||
329 | memset(&txctl, 0, sizeof(txctl)); | |
330 | qnum = sc->tx.hwq_map[WME_AC_BE]; | |
331 | txctl.txq = &sc->tx.txq[qnum]; | |
332 | ||
47399f1a | 333 | ath9k_ps_wakeup(sc); |
9f42c2b6 FF |
334 | ar9003_paprd_init_table(ah); |
335 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | |
336 | if (!(ah->caps.tx_chainmask & BIT(chain))) | |
337 | continue; | |
338 | ||
339 | chain_ok = 0; | |
340 | memset(tx_info, 0, sizeof(*tx_info)); | |
341 | tx_info->band = band; | |
342 | ||
343 | for (i = 0; i < 4; i++) { | |
344 | tx_info->control.rates[i].idx = sband->n_bitrates - 1; | |
345 | tx_info->control.rates[i].count = 6; | |
346 | } | |
347 | ||
348 | init_completion(&sc->paprd_complete); | |
349 | ar9003_paprd_setup_gain_table(ah, chain); | |
350 | txctl.paprd = BIT(chain); | |
351 | if (ath_tx_start(hw, skb, &txctl) != 0) | |
352 | break; | |
353 | ||
354 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
ca369eb4 | 355 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); |
9f42c2b6 FF |
356 | if (!time_left) { |
357 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | |
358 | "Timeout waiting for paprd training on " | |
359 | "TX chain %d\n", | |
360 | chain); | |
ca369eb4 | 361 | goto fail_paprd; |
9f42c2b6 FF |
362 | } |
363 | ||
364 | if (!ar9003_paprd_is_done(ah)) | |
365 | break; | |
366 | ||
20bd2a09 | 367 | if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) |
9f42c2b6 FF |
368 | break; |
369 | ||
370 | chain_ok = 1; | |
371 | } | |
372 | kfree_skb(skb); | |
373 | ||
374 | if (chain_ok) { | |
20bd2a09 | 375 | caldata->paprd_done = true; |
9f42c2b6 FF |
376 | ath_paprd_activate(sc); |
377 | } | |
378 | ||
ca369eb4 | 379 | fail_paprd: |
9f42c2b6 FF |
380 | ath9k_ps_restore(sc); |
381 | } | |
382 | ||
ff37e337 S |
383 | /* |
384 | * This routine performs the periodic noise floor calibration function | |
385 | * that is used to adjust and optimize the chip performance. This | |
386 | * takes environmental changes (location, temperature) into account. | |
387 | * When the task is complete, it reschedules itself depending on the | |
388 | * appropriate interval that was calculated. | |
389 | */ | |
55624204 | 390 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 391 | { |
20977d3e S |
392 | struct ath_softc *sc = (struct ath_softc *)data; |
393 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 394 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
395 | bool longcal = false; |
396 | bool shortcal = false; | |
397 | bool aniflag = false; | |
398 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e FF |
399 | u32 cal_interval, short_cal_interval, long_cal_interval; |
400 | ||
401 | if (ah->caldata && ah->caldata->nfcal_interference) | |
402 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
403 | else | |
404 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 405 | |
20977d3e S |
406 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
407 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 408 | |
1ffc1c61 JM |
409 | /* Only calibrate if awake */ |
410 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
411 | goto set_timer; | |
412 | ||
413 | ath9k_ps_wakeup(sc); | |
414 | ||
ff37e337 | 415 | /* Long calibration runs independently of short calibration. */ |
6044474e | 416 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 417 | longcal = true; |
c46917bb | 418 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 419 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
420 | } |
421 | ||
17d7904d | 422 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
423 | if (!common->ani.caldone) { |
424 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 425 | shortcal = true; |
c46917bb LR |
426 | ath_print(common, ATH_DBG_ANI, |
427 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
428 | common->ani.shortcal_timer = timestamp; |
429 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
430 | } |
431 | } else { | |
3d536acf | 432 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 433 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
434 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
435 | if (common->ani.caldone) | |
436 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
437 | } |
438 | } | |
439 | ||
440 | /* Verify whether we must check ANI */ | |
e36b27af LR |
441 | if ((timestamp - common->ani.checkani_timer) >= |
442 | ah->config.ani_poll_interval) { | |
ff37e337 | 443 | aniflag = true; |
3d536acf | 444 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
445 | } |
446 | ||
447 | /* Skip all processing if there's nothing to do. */ | |
448 | if (longcal || shortcal || aniflag) { | |
449 | /* Call ANI routine if necessary */ | |
450 | if (aniflag) | |
22e66a4c | 451 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
452 | |
453 | /* Perform calibration if necessary */ | |
454 | if (longcal || shortcal) { | |
3d536acf | 455 | common->ani.caldone = |
43c27613 LR |
456 | ath9k_hw_calibrate(ah, |
457 | ah->curchan, | |
458 | common->rx_chainmask, | |
459 | longcal); | |
379f0440 S |
460 | |
461 | if (longcal) | |
3d536acf | 462 | common->ani.noise_floor = ath9k_hw_getchan_noise(ah, |
379f0440 S |
463 | ah->curchan); |
464 | ||
c46917bb LR |
465 | ath_print(common, ATH_DBG_ANI, |
466 | " calibrate chan %u/%x nf: %d\n", | |
467 | ah->curchan->channel, | |
468 | ah->curchan->channelFlags, | |
3d536acf | 469 | common->ani.noise_floor); |
ff37e337 S |
470 | } |
471 | } | |
472 | ||
1ffc1c61 JM |
473 | ath9k_ps_restore(sc); |
474 | ||
20977d3e | 475 | set_timer: |
ff37e337 S |
476 | /* |
477 | * Set timer interval based on previous results. | |
478 | * The interval must be the shortest necessary to satisfy ANI, | |
479 | * short calibration and long calibration. | |
480 | */ | |
aac9207e | 481 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 482 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
483 | cal_interval = min(cal_interval, |
484 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 485 | if (!common->ani.caldone) |
20977d3e | 486 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 487 | |
3d536acf | 488 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
489 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
490 | if (!ah->caldata->paprd_done) | |
9f42c2b6 FF |
491 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
492 | else | |
493 | ath_paprd_activate(sc); | |
494 | } | |
ff37e337 S |
495 | } |
496 | ||
497 | /* | |
498 | * Update tx/rx chainmask. For legacy association, | |
499 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
500 | * the chainmask configuration, for bt coexistence, use |
501 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 502 | */ |
0e2dedf9 | 503 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 504 | { |
af03abec | 505 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 506 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 507 | |
5ee08656 | 508 | if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht || |
766ec4a9 | 509 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
510 | common->tx_chainmask = ah->caps.tx_chainmask; |
511 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 512 | } else { |
43c27613 LR |
513 | common->tx_chainmask = 1; |
514 | common->rx_chainmask = 1; | |
ff37e337 S |
515 | } |
516 | ||
43c27613 | 517 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 518 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
519 | common->tx_chainmask, |
520 | common->rx_chainmask); | |
ff37e337 S |
521 | } |
522 | ||
523 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
524 | { | |
525 | struct ath_node *an; | |
526 | ||
527 | an = (struct ath_node *)sta->drv_priv; | |
528 | ||
87792efc | 529 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 530 | ath_tx_node_init(sc, an); |
9e98ac65 | 531 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
532 | sta->ht_cap.ampdu_factor); |
533 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 534 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 535 | } |
ff37e337 S |
536 | } |
537 | ||
538 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
539 | { | |
540 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
541 | ||
542 | if (sc->sc_flags & SC_OP_TXAGGR) | |
543 | ath_tx_node_cleanup(sc, an); | |
544 | } | |
545 | ||
347809fc FF |
546 | void ath_hw_check(struct work_struct *work) |
547 | { | |
548 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
549 | int i; | |
550 | ||
551 | ath9k_ps_wakeup(sc); | |
552 | ||
553 | for (i = 0; i < 3; i++) { | |
554 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
555 | goto out; | |
556 | ||
557 | msleep(1); | |
558 | } | |
559 | ath_reset(sc, false); | |
560 | ||
561 | out: | |
562 | ath9k_ps_restore(sc); | |
563 | } | |
564 | ||
55624204 | 565 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
566 | { |
567 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 568 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 569 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 570 | |
17d7904d | 571 | u32 status = sc->intrstatus; |
b5c80475 | 572 | u32 rxmask; |
ff37e337 | 573 | |
153e080d VT |
574 | ath9k_ps_wakeup(sc); |
575 | ||
347809fc | 576 | if (status & ATH9K_INT_FATAL) { |
ff37e337 | 577 | ath_reset(sc, false); |
153e080d | 578 | ath9k_ps_restore(sc); |
ff37e337 | 579 | return; |
063d8be3 | 580 | } |
ff37e337 | 581 | |
347809fc FF |
582 | if (!ath9k_hw_check_alive(ah)) |
583 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); | |
584 | ||
b5c80475 FF |
585 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
586 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
587 | ATH9K_INT_RXORN); | |
588 | else | |
589 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
590 | ||
591 | if (status & rxmask) { | |
063d8be3 | 592 | spin_lock_bh(&sc->rx.rxflushlock); |
b5c80475 FF |
593 | |
594 | /* Check for high priority Rx first */ | |
595 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
596 | (status & ATH9K_INT_RXHP)) | |
597 | ath_rx_tasklet(sc, 0, true); | |
598 | ||
599 | ath_rx_tasklet(sc, 0, false); | |
063d8be3 | 600 | spin_unlock_bh(&sc->rx.rxflushlock); |
ff37e337 S |
601 | } |
602 | ||
e5003249 VT |
603 | if (status & ATH9K_INT_TX) { |
604 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
605 | ath_tx_edma_tasklet(sc); | |
606 | else | |
607 | ath_tx_tasklet(sc); | |
608 | } | |
063d8be3 | 609 | |
96148326 | 610 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
611 | /* |
612 | * TSF sync does not look correct; remain awake to sync with | |
613 | * the next Beacon. | |
614 | */ | |
c46917bb LR |
615 | ath_print(common, ATH_DBG_PS, |
616 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 617 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
618 | } |
619 | ||
766ec4a9 | 620 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
621 | if (status & ATH9K_INT_GENTIMER) |
622 | ath_gen_timer_isr(sc->sc_ah); | |
623 | ||
ff37e337 | 624 | /* re-enable hardware interrupt */ |
3069168c | 625 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 626 | ath9k_ps_restore(sc); |
ff37e337 S |
627 | } |
628 | ||
6baff7f9 | 629 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 630 | { |
063d8be3 S |
631 | #define SCHED_INTR ( \ |
632 | ATH9K_INT_FATAL | \ | |
633 | ATH9K_INT_RXORN | \ | |
634 | ATH9K_INT_RXEOL | \ | |
635 | ATH9K_INT_RX | \ | |
b5c80475 FF |
636 | ATH9K_INT_RXLP | \ |
637 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
638 | ATH9K_INT_TX | \ |
639 | ATH9K_INT_BMISS | \ | |
640 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
641 | ATH9K_INT_TSFOOR | \ |
642 | ATH9K_INT_GENTIMER) | |
063d8be3 | 643 | |
ff37e337 | 644 | struct ath_softc *sc = dev; |
cbe61d8a | 645 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
646 | enum ath9k_int status; |
647 | bool sched = false; | |
648 | ||
063d8be3 S |
649 | /* |
650 | * The hardware is not ready/present, don't | |
651 | * touch anything. Note this can happen early | |
652 | * on if the IRQ is shared. | |
653 | */ | |
654 | if (sc->sc_flags & SC_OP_INVALID) | |
655 | return IRQ_NONE; | |
ff37e337 | 656 | |
063d8be3 S |
657 | |
658 | /* shared irq, not for us */ | |
659 | ||
153e080d | 660 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 661 | return IRQ_NONE; |
063d8be3 S |
662 | |
663 | /* | |
664 | * Figure out the reason(s) for the interrupt. Note | |
665 | * that the hal returns a pseudo-ISR that may include | |
666 | * bits we haven't explicitly enabled so we mask the | |
667 | * value to insure we only process bits we requested. | |
668 | */ | |
669 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 670 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 671 | |
063d8be3 S |
672 | /* |
673 | * If there are no status bits set, then this interrupt was not | |
674 | * for me (should have been caught above). | |
675 | */ | |
153e080d | 676 | if (!status) |
063d8be3 | 677 | return IRQ_NONE; |
ff37e337 | 678 | |
063d8be3 S |
679 | /* Cache the status */ |
680 | sc->intrstatus = status; | |
681 | ||
682 | if (status & SCHED_INTR) | |
683 | sched = true; | |
684 | ||
685 | /* | |
686 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
687 | * chip immediately. | |
688 | */ | |
b5c80475 FF |
689 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
690 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
691 | goto chip_reset; |
692 | ||
08578b8f LR |
693 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
694 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
695 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
696 | goto chip_reset; | |
697 | } | |
698 | ||
063d8be3 S |
699 | if (status & ATH9K_INT_SWBA) |
700 | tasklet_schedule(&sc->bcon_tasklet); | |
701 | ||
702 | if (status & ATH9K_INT_TXURN) | |
703 | ath9k_hw_updatetxtriglevel(ah, true); | |
704 | ||
b5c80475 FF |
705 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
706 | if (status & ATH9K_INT_RXEOL) { | |
707 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
708 | ath9k_hw_set_interrupts(ah, ah->imask); | |
709 | } | |
710 | } | |
711 | ||
063d8be3 | 712 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 713 | /* |
063d8be3 S |
714 | * Disable interrupts until we service the MIB |
715 | * interrupt; otherwise it will continue to | |
716 | * fire. | |
ff37e337 | 717 | */ |
063d8be3 S |
718 | ath9k_hw_set_interrupts(ah, 0); |
719 | /* | |
720 | * Let the hal handle the event. We assume | |
721 | * it will clear whatever condition caused | |
722 | * the interrupt. | |
723 | */ | |
22e66a4c | 724 | ath9k_hw_procmibevent(ah); |
3069168c | 725 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 726 | } |
ff37e337 | 727 | |
153e080d VT |
728 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
729 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
730 | /* Clear RxAbort bit so that we can |
731 | * receive frames */ | |
9ecdef4b | 732 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 733 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 734 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 735 | } |
063d8be3 S |
736 | |
737 | chip_reset: | |
ff37e337 | 738 | |
817e11de S |
739 | ath_debug_stat_interrupt(sc, status); |
740 | ||
ff37e337 S |
741 | if (sched) { |
742 | /* turn off every interrupt except SWBA */ | |
3069168c | 743 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
744 | tasklet_schedule(&sc->intr_tq); |
745 | } | |
746 | ||
747 | return IRQ_HANDLED; | |
063d8be3 S |
748 | |
749 | #undef SCHED_INTR | |
ff37e337 S |
750 | } |
751 | ||
f078f209 | 752 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 753 | struct ieee80211_channel *chan, |
094d05dc | 754 | enum nl80211_channel_type channel_type) |
f078f209 LR |
755 | { |
756 | u32 chanmode = 0; | |
f078f209 LR |
757 | |
758 | switch (chan->band) { | |
759 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
760 | switch(channel_type) { |
761 | case NL80211_CHAN_NO_HT: | |
762 | case NL80211_CHAN_HT20: | |
f078f209 | 763 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
764 | break; |
765 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 766 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
767 | break; |
768 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 769 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
770 | break; |
771 | } | |
f078f209 LR |
772 | break; |
773 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
774 | switch(channel_type) { |
775 | case NL80211_CHAN_NO_HT: | |
776 | case NL80211_CHAN_HT20: | |
f078f209 | 777 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
778 | break; |
779 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 780 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
781 | break; |
782 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 783 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
784 | break; |
785 | } | |
f078f209 LR |
786 | break; |
787 | default: | |
788 | break; | |
789 | } | |
790 | ||
791 | return chanmode; | |
792 | } | |
793 | ||
8feceb67 | 794 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 795 | struct ieee80211_vif *vif, |
8feceb67 | 796 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 797 | { |
f2b2143e | 798 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 799 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 800 | |
8feceb67 | 801 | if (bss_conf->assoc) { |
c46917bb LR |
802 | ath_print(common, ATH_DBG_CONFIG, |
803 | "Bss Info ASSOC %d, bssid: %pM\n", | |
804 | bss_conf->aid, common->curbssid); | |
f078f209 | 805 | |
8feceb67 | 806 | /* New association, store aid */ |
1510718d | 807 | common->curaid = bss_conf->aid; |
f2b2143e | 808 | ath9k_hw_write_associd(ah); |
2664f201 SB |
809 | |
810 | /* | |
811 | * Request a re-configuration of Beacon related timers | |
812 | * on the receipt of the first Beacon frame (i.e., | |
813 | * after time sync with the AP). | |
814 | */ | |
1b04b930 | 815 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 816 | |
8feceb67 | 817 | /* Configure the beacon */ |
2c3db3d5 | 818 | ath_beacon_config(sc, vif); |
f078f209 | 819 | |
8feceb67 | 820 | /* Reset rssi stats */ |
22e66a4c | 821 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 822 | |
6c3118e2 | 823 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 824 | ath_start_ani(common); |
8feceb67 | 825 | } else { |
c46917bb | 826 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 827 | common->curaid = 0; |
f38faa31 | 828 | /* Stop ANI */ |
6c3118e2 | 829 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 830 | del_timer_sync(&common->ani.timer); |
f078f209 | 831 | } |
8feceb67 | 832 | } |
f078f209 | 833 | |
68a89116 | 834 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 835 | { |
cbe61d8a | 836 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 837 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 838 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 839 | int r; |
500c064d | 840 | |
3cbb5dd7 | 841 | ath9k_ps_wakeup(sc); |
93b1b37f | 842 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 843 | |
159cd468 VT |
844 | if (!ah->curchan) |
845 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
846 | ||
d2f5b3a6 | 847 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 848 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 849 | if (r) { |
c46917bb | 850 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 851 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
852 | "reset status %d\n", |
853 | channel->center_freq, r); | |
500c064d VT |
854 | } |
855 | spin_unlock_bh(&sc->sc_resetlock); | |
856 | ||
857 | ath_update_txpow(sc); | |
858 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
859 | ath_print(common, ATH_DBG_FATAL, |
860 | "Unable to restart recv logic\n"); | |
500c064d VT |
861 | return; |
862 | } | |
863 | ||
864 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 865 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
866 | |
867 | /* Re-Enable interrupts */ | |
3069168c | 868 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
869 | |
870 | /* Enable LED */ | |
08fc5c1b | 871 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 872 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 873 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 874 | |
68a89116 | 875 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 876 | ath9k_ps_restore(sc); |
500c064d VT |
877 | } |
878 | ||
68a89116 | 879 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 880 | { |
cbe61d8a | 881 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 882 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 883 | int r; |
500c064d | 884 | |
3cbb5dd7 | 885 | ath9k_ps_wakeup(sc); |
68a89116 | 886 | ieee80211_stop_queues(hw); |
500c064d | 887 | |
982723df VN |
888 | /* |
889 | * Keep the LED on when the radio is disabled | |
890 | * during idle unassociated state. | |
891 | */ | |
892 | if (!sc->ps_idle) { | |
893 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
894 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
895 | } | |
500c064d VT |
896 | |
897 | /* Disable interrupts */ | |
898 | ath9k_hw_set_interrupts(ah, 0); | |
899 | ||
043a0405 | 900 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
901 | ath_stoprecv(sc); /* turn off frame recv */ |
902 | ath_flushrecv(sc); /* flush recv queue */ | |
903 | ||
159cd468 | 904 | if (!ah->curchan) |
68a89116 | 905 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 906 | |
500c064d | 907 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 908 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 909 | if (r) { |
c46917bb | 910 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 911 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
912 | "reset status %d\n", |
913 | channel->center_freq, r); | |
500c064d VT |
914 | } |
915 | spin_unlock_bh(&sc->sc_resetlock); | |
916 | ||
917 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 918 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 919 | ath9k_ps_restore(sc); |
9ecdef4b | 920 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
921 | } |
922 | ||
ff37e337 S |
923 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
924 | { | |
cbe61d8a | 925 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 926 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 927 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 928 | int r; |
ff37e337 | 929 | |
2ab81d4a S |
930 | /* Stop ANI */ |
931 | del_timer_sync(&common->ani.timer); | |
932 | ||
cc9c378a S |
933 | ieee80211_stop_queues(hw); |
934 | ||
ff37e337 | 935 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 936 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
937 | ath_stoprecv(sc); |
938 | ath_flushrecv(sc); | |
939 | ||
940 | spin_lock_bh(&sc->sc_resetlock); | |
20bd2a09 | 941 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); |
ae8d2858 | 942 | if (r) |
c46917bb LR |
943 | ath_print(common, ATH_DBG_FATAL, |
944 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
945 | spin_unlock_bh(&sc->sc_resetlock); |
946 | ||
947 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
948 | ath_print(common, ATH_DBG_FATAL, |
949 | "Unable to start recv logic\n"); | |
ff37e337 S |
950 | |
951 | /* | |
952 | * We may be doing a reset in response to a request | |
953 | * that changes the channel so update any state that | |
954 | * might change as a result. | |
955 | */ | |
ce111bad | 956 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
957 | |
958 | ath_update_txpow(sc); | |
959 | ||
960 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 961 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 962 | |
3069168c | 963 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
964 | |
965 | if (retry_tx) { | |
966 | int i; | |
967 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
968 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
969 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
970 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
971 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
972 | } |
973 | } | |
974 | } | |
975 | ||
cc9c378a S |
976 | ieee80211_wake_queues(hw); |
977 | ||
2ab81d4a S |
978 | /* Start ANI */ |
979 | ath_start_ani(common); | |
980 | ||
ae8d2858 | 981 | return r; |
ff37e337 S |
982 | } |
983 | ||
ebe297c3 | 984 | static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
ff37e337 S |
985 | { |
986 | int qnum; | |
987 | ||
988 | switch (queue) { | |
989 | case 0: | |
1d2231e2 | 990 | qnum = sc->tx.hwq_map[WME_AC_VO]; |
ff37e337 S |
991 | break; |
992 | case 1: | |
1d2231e2 | 993 | qnum = sc->tx.hwq_map[WME_AC_VI]; |
ff37e337 S |
994 | break; |
995 | case 2: | |
1d2231e2 | 996 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
997 | break; |
998 | case 3: | |
1d2231e2 | 999 | qnum = sc->tx.hwq_map[WME_AC_BK]; |
ff37e337 S |
1000 | break; |
1001 | default: | |
1d2231e2 | 1002 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
1003 | break; |
1004 | } | |
1005 | ||
1006 | return qnum; | |
1007 | } | |
1008 | ||
1009 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1010 | { | |
1011 | int qnum; | |
1012 | ||
1013 | switch (queue) { | |
1d2231e2 | 1014 | case WME_AC_VO: |
ff37e337 S |
1015 | qnum = 0; |
1016 | break; | |
1d2231e2 | 1017 | case WME_AC_VI: |
ff37e337 S |
1018 | qnum = 1; |
1019 | break; | |
1d2231e2 | 1020 | case WME_AC_BE: |
ff37e337 S |
1021 | qnum = 2; |
1022 | break; | |
1d2231e2 | 1023 | case WME_AC_BK: |
ff37e337 S |
1024 | qnum = 3; |
1025 | break; | |
1026 | default: | |
1027 | qnum = -1; | |
1028 | break; | |
1029 | } | |
1030 | ||
1031 | return qnum; | |
1032 | } | |
1033 | ||
5f8e077c LR |
1034 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1035 | * this redundant data */ | |
0e2dedf9 JM |
1036 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1037 | struct ath9k_channel *ichan) | |
5f8e077c | 1038 | { |
5f8e077c LR |
1039 | struct ieee80211_channel *chan = hw->conf.channel; |
1040 | struct ieee80211_conf *conf = &hw->conf; | |
1041 | ||
1042 | ichan->channel = chan->center_freq; | |
1043 | ichan->chan = chan; | |
1044 | ||
1045 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1046 | ichan->chanmode = CHANNEL_G; | |
8813262e | 1047 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
1048 | } else { |
1049 | ichan->chanmode = CHANNEL_A; | |
1050 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1051 | } | |
1052 | ||
25c56eec | 1053 | if (conf_is_ht(conf)) |
5f8e077c LR |
1054 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
1055 | conf->channel_type); | |
5f8e077c LR |
1056 | } |
1057 | ||
ff37e337 S |
1058 | /**********************/ |
1059 | /* mac80211 callbacks */ | |
1060 | /**********************/ | |
1061 | ||
8feceb67 | 1062 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1063 | { |
bce048d7 JM |
1064 | struct ath_wiphy *aphy = hw->priv; |
1065 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1066 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1067 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1068 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1069 | struct ath9k_channel *init_channel; |
82880a7c | 1070 | int r; |
f078f209 | 1071 | |
c46917bb LR |
1072 | ath_print(common, ATH_DBG_CONFIG, |
1073 | "Starting driver with initial channel: %d MHz\n", | |
1074 | curchan->center_freq); | |
f078f209 | 1075 | |
141b38b6 S |
1076 | mutex_lock(&sc->mutex); |
1077 | ||
9580a222 JM |
1078 | if (ath9k_wiphy_started(sc)) { |
1079 | if (sc->chan_idx == curchan->hw_value) { | |
1080 | /* | |
1081 | * Already on the operational channel, the new wiphy | |
1082 | * can be marked active. | |
1083 | */ | |
1084 | aphy->state = ATH_WIPHY_ACTIVE; | |
1085 | ieee80211_wake_queues(hw); | |
1086 | } else { | |
1087 | /* | |
1088 | * Another wiphy is on another channel, start the new | |
1089 | * wiphy in paused state. | |
1090 | */ | |
1091 | aphy->state = ATH_WIPHY_PAUSED; | |
1092 | ieee80211_stop_queues(hw); | |
1093 | } | |
1094 | mutex_unlock(&sc->mutex); | |
1095 | return 0; | |
1096 | } | |
1097 | aphy->state = ATH_WIPHY_ACTIVE; | |
1098 | ||
8feceb67 | 1099 | /* setup initial channel */ |
f078f209 | 1100 | |
82880a7c | 1101 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1102 | |
82880a7c | 1103 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1104 | |
1105 | /* Reset SERDES registers */ | |
af03abec | 1106 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1107 | |
1108 | /* | |
1109 | * The basic interface to setting the hardware in a good | |
1110 | * state is ``reset''. On return the hardware is known to | |
1111 | * be powered up and with interrupts disabled. This must | |
1112 | * be followed by initialization of the appropriate bits | |
1113 | * and then setup of the interrupt mask. | |
1114 | */ | |
1115 | spin_lock_bh(&sc->sc_resetlock); | |
20bd2a09 | 1116 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1117 | if (r) { |
c46917bb LR |
1118 | ath_print(common, ATH_DBG_FATAL, |
1119 | "Unable to reset hardware; reset status %d " | |
1120 | "(freq %u MHz)\n", r, | |
1121 | curchan->center_freq); | |
ff37e337 | 1122 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 1123 | goto mutex_unlock; |
ff37e337 S |
1124 | } |
1125 | spin_unlock_bh(&sc->sc_resetlock); | |
1126 | ||
1127 | /* | |
1128 | * This is needed only to setup initial state | |
1129 | * but it's best done after a reset. | |
1130 | */ | |
1131 | ath_update_txpow(sc); | |
8feceb67 | 1132 | |
ff37e337 S |
1133 | /* |
1134 | * Setup the hardware after reset: | |
1135 | * The receive engine is set going. | |
1136 | * Frame transmit is handled entirely | |
1137 | * in the frame output path; there's nothing to do | |
1138 | * here except setup the interrupt mask. | |
1139 | */ | |
1140 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
1141 | ath_print(common, ATH_DBG_FATAL, |
1142 | "Unable to start recv logic\n"); | |
141b38b6 S |
1143 | r = -EIO; |
1144 | goto mutex_unlock; | |
f078f209 | 1145 | } |
8feceb67 | 1146 | |
ff37e337 | 1147 | /* Setup our intr mask. */ |
b5c80475 FF |
1148 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1149 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1150 | ATH9K_INT_GLOBAL; | |
1151 | ||
1152 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1153 | ah->imask |= ATH9K_INT_RXHP | |
1154 | ATH9K_INT_RXLP | | |
1155 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1156 | else |
1157 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1158 | |
af03abec | 1159 | if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
3069168c | 1160 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1161 | |
af03abec | 1162 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1163 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1164 | |
ce111bad | 1165 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1166 | |
1167 | sc->sc_flags &= ~SC_OP_INVALID; | |
1168 | ||
1169 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1170 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1171 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1172 | |
bce048d7 | 1173 | ieee80211_wake_queues(hw); |
ff37e337 | 1174 | |
42935eca | 1175 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1176 | |
766ec4a9 LR |
1177 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1178 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1179 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1180 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1181 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1182 | |
5bb12791 LR |
1183 | if (common->bus_ops->bt_coex_prep) |
1184 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1185 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1186 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1187 | } |
1188 | ||
141b38b6 S |
1189 | mutex_unlock: |
1190 | mutex_unlock(&sc->mutex); | |
1191 | ||
ae8d2858 | 1192 | return r; |
f078f209 LR |
1193 | } |
1194 | ||
8feceb67 VT |
1195 | static int ath9k_tx(struct ieee80211_hw *hw, |
1196 | struct sk_buff *skb) | |
f078f209 | 1197 | { |
528f0c6b | 1198 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1199 | struct ath_wiphy *aphy = hw->priv; |
1200 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1201 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1202 | struct ath_tx_control txctl; |
1bc14880 BP |
1203 | int padpos, padsize; |
1204 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
84642d6b | 1205 | int qnum; |
528f0c6b | 1206 | |
8089cc47 | 1207 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1208 | ath_print(common, ATH_DBG_XMIT, |
1209 | "ath9k: %s: TX in unexpected wiphy state " | |
1210 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1211 | goto exit; |
1212 | } | |
1213 | ||
96148326 | 1214 | if (sc->ps_enabled) { |
dc8c4585 JM |
1215 | /* |
1216 | * mac80211 does not set PM field for normal data frames, so we | |
1217 | * need to update that based on the current PS mode. | |
1218 | */ | |
1219 | if (ieee80211_is_data(hdr->frame_control) && | |
1220 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1221 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1222 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1223 | "while in PS mode\n"); | |
dc8c4585 JM |
1224 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1225 | } | |
1226 | } | |
1227 | ||
9a23f9ca JM |
1228 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1229 | /* | |
1230 | * We are using PS-Poll and mac80211 can request TX while in | |
1231 | * power save mode. Need to wake up hardware for the TX to be | |
1232 | * completed and if needed, also for RX of buffered frames. | |
1233 | */ | |
9a23f9ca | 1234 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1235 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1236 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1237 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
c46917bb LR |
1238 | ath_print(common, ATH_DBG_PS, |
1239 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1240 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1241 | } else { |
c46917bb LR |
1242 | ath_print(common, ATH_DBG_PS, |
1243 | "Wake up to complete TX\n"); | |
1b04b930 | 1244 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1245 | } |
1246 | /* | |
1247 | * The actual restore operation will happen only after | |
1248 | * the sc_flags bit is cleared. We are just dropping | |
1249 | * the ps_usecount here. | |
1250 | */ | |
1251 | ath9k_ps_restore(sc); | |
1252 | } | |
1253 | ||
528f0c6b | 1254 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1255 | |
8feceb67 VT |
1256 | /* |
1257 | * As a temporary workaround, assign seq# here; this will likely need | |
1258 | * to be cleaned up to work better with Beacon transmission and virtual | |
1259 | * BSSes. | |
1260 | */ | |
1261 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1262 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1263 | sc->tx.seq_no += 0x10; |
8feceb67 | 1264 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1265 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1266 | } |
f078f209 | 1267 | |
8feceb67 | 1268 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1269 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1270 | padsize = padpos & 3; | |
1271 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1272 | if (skb_headroom(skb) < padsize) |
1273 | return -1; | |
1274 | skb_push(skb, padsize); | |
1bc14880 | 1275 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1276 | } |
1277 | ||
84642d6b FF |
1278 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1279 | txctl.txq = &sc->tx.txq[qnum]; | |
528f0c6b | 1280 | |
c46917bb | 1281 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1282 | |
c52f33d0 | 1283 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1284 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1285 | goto exit; |
8feceb67 VT |
1286 | } |
1287 | ||
528f0c6b S |
1288 | return 0; |
1289 | exit: | |
1290 | dev_kfree_skb_any(skb); | |
8feceb67 | 1291 | return 0; |
f078f209 LR |
1292 | } |
1293 | ||
8feceb67 | 1294 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1295 | { |
bce048d7 JM |
1296 | struct ath_wiphy *aphy = hw->priv; |
1297 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1298 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1299 | struct ath_common *common = ath9k_hw_common(ah); |
447a42c2 | 1300 | int i; |
f078f209 | 1301 | |
4c483817 S |
1302 | mutex_lock(&sc->mutex); |
1303 | ||
9580a222 JM |
1304 | aphy->state = ATH_WIPHY_INACTIVE; |
1305 | ||
9a75c2ff VN |
1306 | if (led_blink) |
1307 | cancel_delayed_work_sync(&sc->ath_led_blink_work); | |
1308 | ||
c94dbff7 | 1309 | cancel_delayed_work_sync(&sc->tx_complete_work); |
9f42c2b6 | 1310 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1311 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1312 | |
447a42c2 RM |
1313 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1314 | if (sc->sec_wiphy[i]) | |
1315 | break; | |
1316 | } | |
1317 | ||
1318 | if (i == sc->num_sec_wiphy) { | |
c94dbff7 LR |
1319 | cancel_delayed_work_sync(&sc->wiphy_work); |
1320 | cancel_work_sync(&sc->chan_work); | |
1321 | } | |
1322 | ||
9c84b797 | 1323 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1324 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1325 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1326 | return; |
1327 | } | |
8feceb67 | 1328 | |
9580a222 JM |
1329 | if (ath9k_wiphy_started(sc)) { |
1330 | mutex_unlock(&sc->mutex); | |
1331 | return; /* another wiphy still in use */ | |
1332 | } | |
1333 | ||
3867cf6a S |
1334 | /* Ensure HW is awake when we try to shut it down. */ |
1335 | ath9k_ps_wakeup(sc); | |
1336 | ||
766ec4a9 | 1337 | if (ah->btcoex_hw.enabled) { |
af03abec | 1338 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1339 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1340 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1341 | } |
1342 | ||
ff37e337 S |
1343 | /* make sure h/w will not generate any interrupt |
1344 | * before setting the invalid flag. */ | |
af03abec | 1345 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
1346 | |
1347 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1348 | ath_drain_all_txq(sc, false); |
ff37e337 | 1349 | ath_stoprecv(sc); |
af03abec | 1350 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1351 | } else |
b77f483f | 1352 | sc->rx.rxlink = NULL; |
ff37e337 | 1353 | |
ff37e337 | 1354 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1355 | ath9k_hw_disable(ah); |
1356 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1357 | ath9k_ps_restore(sc); |
1358 | ||
1359 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1360 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1361 | |
1362 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1363 | |
141b38b6 S |
1364 | mutex_unlock(&sc->mutex); |
1365 | ||
c46917bb | 1366 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1367 | } |
1368 | ||
8feceb67 | 1369 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1370 | struct ieee80211_vif *vif) |
f078f209 | 1371 | { |
bce048d7 JM |
1372 | struct ath_wiphy *aphy = hw->priv; |
1373 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1374 | struct ath_hw *ah = sc->sc_ah; |
1375 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1376 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1377 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1378 | int ret = 0; |
8feceb67 | 1379 | |
141b38b6 S |
1380 | mutex_lock(&sc->mutex); |
1381 | ||
3069168c | 1382 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
8ca21f01 JM |
1383 | sc->nvifs > 0) { |
1384 | ret = -ENOBUFS; | |
1385 | goto out; | |
1386 | } | |
1387 | ||
1ed32e4f | 1388 | switch (vif->type) { |
05c914fe | 1389 | case NL80211_IFTYPE_STATION: |
d97809db | 1390 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1391 | break; |
05c914fe | 1392 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1393 | case NL80211_IFTYPE_AP: |
9cb5412b | 1394 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1395 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1396 | ret = -ENOBUFS; | |
1397 | goto out; | |
1398 | } | |
1ed32e4f | 1399 | ic_opmode = vif->type; |
f078f209 LR |
1400 | break; |
1401 | default: | |
c46917bb | 1402 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1403 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1404 | ret = -EOPNOTSUPP; |
1405 | goto out; | |
f078f209 LR |
1406 | } |
1407 | ||
c46917bb LR |
1408 | ath_print(common, ATH_DBG_CONFIG, |
1409 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1410 | |
17d7904d | 1411 | /* Set the VIF opmode */ |
5640b08e S |
1412 | avp->av_opmode = ic_opmode; |
1413 | avp->av_bslot = -1; | |
1414 | ||
2c3db3d5 | 1415 | sc->nvifs++; |
8ca21f01 | 1416 | |
3069168c | 1417 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
8ca21f01 JM |
1418 | ath9k_set_bssid_mask(hw); |
1419 | ||
2c3db3d5 JM |
1420 | if (sc->nvifs > 1) |
1421 | goto out; /* skip global settings for secondary vif */ | |
1422 | ||
b238e90e | 1423 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1424 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1425 | sc->sc_flags |= SC_OP_TSF_RESET; |
1426 | } | |
5640b08e | 1427 | |
5640b08e | 1428 | /* Set the device opmode */ |
3069168c | 1429 | ah->opmode = ic_opmode; |
5640b08e | 1430 | |
4e30ffa2 VN |
1431 | /* |
1432 | * Enable MIB interrupts when there are hardware phy counters. | |
1433 | * Note we only do this (at the moment) for station mode. | |
1434 | */ | |
1ed32e4f JB |
1435 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1436 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1437 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1438 | if (ah->config.enable_ani) |
1439 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1440 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1441 | } |
1442 | ||
3069168c | 1443 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1444 | |
1ed32e4f JB |
1445 | if (vif->type == NL80211_IFTYPE_AP || |
1446 | vif->type == NL80211_IFTYPE_ADHOC || | |
6c3118e2 VT |
1447 | vif->type == NL80211_IFTYPE_MONITOR) { |
1448 | sc->sc_flags |= SC_OP_ANI_RUN; | |
3d536acf | 1449 | ath_start_ani(common); |
6c3118e2 | 1450 | } |
6f255425 | 1451 | |
2c3db3d5 | 1452 | out: |
141b38b6 | 1453 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1454 | return ret; |
f078f209 LR |
1455 | } |
1456 | ||
8feceb67 | 1457 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1458 | struct ieee80211_vif *vif) |
f078f209 | 1459 | { |
bce048d7 JM |
1460 | struct ath_wiphy *aphy = hw->priv; |
1461 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1462 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1463 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1464 | int i; |
f078f209 | 1465 | |
c46917bb | 1466 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1467 | |
141b38b6 S |
1468 | mutex_lock(&sc->mutex); |
1469 | ||
6f255425 | 1470 | /* Stop ANI */ |
6c3118e2 | 1471 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 1472 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1473 | |
8feceb67 | 1474 | /* Reclaim beacon resources */ |
9cb5412b PE |
1475 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1476 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1477 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1478 | ath9k_ps_wakeup(sc); |
b77f483f | 1479 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1480 | ath9k_ps_restore(sc); |
580f0b8a | 1481 | } |
f078f209 | 1482 | |
74401773 | 1483 | ath_beacon_return(sc, avp); |
8feceb67 | 1484 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1485 | |
2c3db3d5 | 1486 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1487 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1488 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1489 | "slot\n", __func__); | |
1490 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1491 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1492 | } |
1493 | } | |
1494 | ||
17d7904d | 1495 | sc->nvifs--; |
141b38b6 S |
1496 | |
1497 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1498 | } |
1499 | ||
3f7c5c10 SB |
1500 | void ath9k_enable_ps(struct ath_softc *sc) |
1501 | { | |
3069168c PR |
1502 | struct ath_hw *ah = sc->sc_ah; |
1503 | ||
3f7c5c10 | 1504 | sc->ps_enabled = true; |
3069168c PR |
1505 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1506 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1507 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1508 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1509 | } |
fdf76622 | 1510 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1511 | } |
3f7c5c10 SB |
1512 | } |
1513 | ||
e8975581 | 1514 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1515 | { |
bce048d7 JM |
1516 | struct ath_wiphy *aphy = hw->priv; |
1517 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1518 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8975581 | 1519 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 1520 | struct ath_hw *ah = sc->sc_ah; |
194b7c13 | 1521 | bool disable_radio; |
f078f209 | 1522 | |
aa33de09 | 1523 | mutex_lock(&sc->mutex); |
141b38b6 | 1524 | |
194b7c13 LR |
1525 | /* |
1526 | * Leave this as the first check because we need to turn on the | |
1527 | * radio if it was disabled before prior to processing the rest | |
1528 | * of the changes. Likewise we must only disable the radio towards | |
1529 | * the end. | |
1530 | */ | |
64839170 | 1531 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1532 | bool enable_radio; |
1533 | bool all_wiphys_idle; | |
1534 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1535 | |
1536 | spin_lock_bh(&sc->wiphy_lock); | |
1537 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1538 | ath9k_set_wiphy_idle(aphy, idle); |
1539 | ||
11446011 | 1540 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1541 | |
1542 | /* | |
1543 | * After we unlock here its possible another wiphy | |
1544 | * can be re-renabled so to account for that we will | |
1545 | * only disable the radio toward the end of this routine | |
1546 | * if by then all wiphys are still idle. | |
1547 | */ | |
64839170 LR |
1548 | spin_unlock_bh(&sc->wiphy_lock); |
1549 | ||
194b7c13 | 1550 | if (enable_radio) { |
1dbfd9d4 | 1551 | sc->ps_idle = false; |
68a89116 | 1552 | ath_radio_enable(sc, hw); |
c46917bb LR |
1553 | ath_print(common, ATH_DBG_CONFIG, |
1554 | "not-idle: enabling radio\n"); | |
64839170 LR |
1555 | } |
1556 | } | |
1557 | ||
e7824a50 LR |
1558 | /* |
1559 | * We just prepare to enable PS. We have to wait until our AP has | |
1560 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1561 | * those ACKs and end up retransmitting the same null data frames. | |
1562 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1563 | */ | |
3cbb5dd7 VN |
1564 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
1565 | if (conf->flags & IEEE80211_CONF_PS) { | |
1b04b930 | 1566 | sc->ps_flags |= PS_ENABLED; |
e7824a50 LR |
1567 | /* |
1568 | * At this point we know hardware has received an ACK | |
1569 | * of a previously sent null data frame. | |
1570 | */ | |
1b04b930 S |
1571 | if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { |
1572 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; | |
3f7c5c10 | 1573 | ath9k_enable_ps(sc); |
e7824a50 | 1574 | } |
3cbb5dd7 | 1575 | } else { |
96148326 | 1576 | sc->ps_enabled = false; |
1b04b930 S |
1577 | sc->ps_flags &= ~(PS_ENABLED | |
1578 | PS_NULLFUNC_COMPLETED); | |
9ecdef4b | 1579 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8782b41d VN |
1580 | if (!(ah->caps.hw_caps & |
1581 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
1582 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1b04b930 S |
1583 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | |
1584 | PS_WAIT_FOR_CAB | | |
1585 | PS_WAIT_FOR_PSPOLL_DATA | | |
1586 | PS_WAIT_FOR_TX_ACK); | |
3069168c PR |
1587 | if (ah->imask & ATH9K_INT_TIM_TIMER) { |
1588 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
8782b41d | 1589 | ath9k_hw_set_interrupts(sc->sc_ah, |
3069168c | 1590 | ah->imask); |
8782b41d | 1591 | } |
3cbb5dd7 VN |
1592 | } |
1593 | } | |
1594 | } | |
1595 | ||
199afd9d S |
1596 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1597 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1598 | ath_print(common, ATH_DBG_CONFIG, | |
1599 | "HW opmode set to Monitor mode\n"); | |
1600 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; | |
1601 | } | |
1602 | } | |
1603 | ||
4797938c | 1604 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1605 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1606 | int pos = curchan->hw_value; |
ae5eb026 | 1607 | |
0e2dedf9 JM |
1608 | aphy->chan_idx = pos; |
1609 | aphy->chan_is_ht = conf_is_ht(conf); | |
5ee08656 FF |
1610 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1611 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1612 | else | |
1613 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1614 | |
8089cc47 JM |
1615 | if (aphy->state == ATH_WIPHY_SCAN || |
1616 | aphy->state == ATH_WIPHY_ACTIVE) | |
1617 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1618 | else { | |
1619 | /* | |
1620 | * Do not change operational channel based on a paused | |
1621 | * wiphy changes. | |
1622 | */ | |
1623 | goto skip_chan_change; | |
1624 | } | |
0e2dedf9 | 1625 | |
c46917bb LR |
1626 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1627 | curchan->center_freq); | |
f078f209 | 1628 | |
5f8e077c | 1629 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1630 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1631 | |
ecf70441 | 1632 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1633 | |
0e2dedf9 | 1634 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1635 | ath_print(common, ATH_DBG_FATAL, |
1636 | "Unable to set channel\n"); | |
aa33de09 | 1637 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1638 | return -EINVAL; |
1639 | } | |
094d05dc | 1640 | } |
f078f209 | 1641 | |
8089cc47 | 1642 | skip_chan_change: |
c9f6a656 | 1643 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1644 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1645 | ath_update_txpow(sc); |
1646 | } | |
f078f209 | 1647 | |
194b7c13 LR |
1648 | spin_lock_bh(&sc->wiphy_lock); |
1649 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1650 | spin_unlock_bh(&sc->wiphy_lock); | |
1651 | ||
64839170 | 1652 | if (disable_radio) { |
c46917bb | 1653 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1654 | sc->ps_idle = true; |
68a89116 | 1655 | ath_radio_disable(sc, hw); |
64839170 LR |
1656 | } |
1657 | ||
aa33de09 | 1658 | mutex_unlock(&sc->mutex); |
141b38b6 | 1659 | |
f078f209 LR |
1660 | return 0; |
1661 | } | |
1662 | ||
8feceb67 VT |
1663 | #define SUPPORTED_FILTERS \ |
1664 | (FIF_PROMISC_IN_BSS | \ | |
1665 | FIF_ALLMULTI | \ | |
1666 | FIF_CONTROL | \ | |
af6a3fc7 | 1667 | FIF_PSPOLL | \ |
8feceb67 VT |
1668 | FIF_OTHER_BSS | \ |
1669 | FIF_BCN_PRBRESP_PROMISC | \ | |
1670 | FIF_FCSFAIL) | |
c83be688 | 1671 | |
8feceb67 VT |
1672 | /* FIXME: sc->sc_full_reset ? */ |
1673 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1674 | unsigned int changed_flags, | |
1675 | unsigned int *total_flags, | |
3ac64bee | 1676 | u64 multicast) |
8feceb67 | 1677 | { |
bce048d7 JM |
1678 | struct ath_wiphy *aphy = hw->priv; |
1679 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1680 | u32 rfilt; |
f078f209 | 1681 | |
8feceb67 VT |
1682 | changed_flags &= SUPPORTED_FILTERS; |
1683 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1684 | |
b77f483f | 1685 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1686 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1687 | rfilt = ath_calcrxfilter(sc); |
1688 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1689 | ath9k_ps_restore(sc); |
f078f209 | 1690 | |
c46917bb LR |
1691 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1692 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1693 | } |
f078f209 | 1694 | |
4ca77860 JB |
1695 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1696 | struct ieee80211_vif *vif, | |
1697 | struct ieee80211_sta *sta) | |
8feceb67 | 1698 | { |
bce048d7 JM |
1699 | struct ath_wiphy *aphy = hw->priv; |
1700 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1701 | |
4ca77860 JB |
1702 | ath_node_attach(sc, sta); |
1703 | ||
1704 | return 0; | |
1705 | } | |
1706 | ||
1707 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1708 | struct ieee80211_vif *vif, | |
1709 | struct ieee80211_sta *sta) | |
1710 | { | |
1711 | struct ath_wiphy *aphy = hw->priv; | |
1712 | struct ath_softc *sc = aphy->sc; | |
1713 | ||
1714 | ath_node_detach(sc, sta); | |
1715 | ||
1716 | return 0; | |
f078f209 LR |
1717 | } |
1718 | ||
141b38b6 | 1719 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1720 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1721 | { |
bce048d7 JM |
1722 | struct ath_wiphy *aphy = hw->priv; |
1723 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1724 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1725 | struct ath9k_tx_queue_info qi; |
1726 | int ret = 0, qnum; | |
f078f209 | 1727 | |
8feceb67 VT |
1728 | if (queue >= WME_NUM_AC) |
1729 | return 0; | |
f078f209 | 1730 | |
141b38b6 S |
1731 | mutex_lock(&sc->mutex); |
1732 | ||
1ffb0610 S |
1733 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1734 | ||
8feceb67 VT |
1735 | qi.tqi_aifs = params->aifs; |
1736 | qi.tqi_cwmin = params->cw_min; | |
1737 | qi.tqi_cwmax = params->cw_max; | |
1738 | qi.tqi_burstTime = params->txop; | |
1739 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1740 | |
c46917bb LR |
1741 | ath_print(common, ATH_DBG_CONFIG, |
1742 | "Configure tx [queue/halq] [%d/%d], " | |
1743 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1744 | queue, qnum, params->aifs, params->cw_min, | |
1745 | params->cw_max, params->txop); | |
f078f209 | 1746 | |
8feceb67 VT |
1747 | ret = ath_txq_update(sc, qnum, &qi); |
1748 | if (ret) | |
c46917bb | 1749 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1750 | |
94db2936 | 1751 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1d2231e2 | 1752 | if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret) |
94db2936 VN |
1753 | ath_beaconq_config(sc); |
1754 | ||
141b38b6 S |
1755 | mutex_unlock(&sc->mutex); |
1756 | ||
8feceb67 VT |
1757 | return ret; |
1758 | } | |
f078f209 | 1759 | |
8feceb67 VT |
1760 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1761 | enum set_key_cmd cmd, | |
dc822b5d JB |
1762 | struct ieee80211_vif *vif, |
1763 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1764 | struct ieee80211_key_conf *key) |
1765 | { | |
bce048d7 JM |
1766 | struct ath_wiphy *aphy = hw->priv; |
1767 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1768 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1769 | int ret = 0; |
f078f209 | 1770 | |
b3bd89ce JM |
1771 | if (modparam_nohwcrypt) |
1772 | return -ENOSPC; | |
1773 | ||
141b38b6 | 1774 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1775 | ath9k_ps_wakeup(sc); |
c46917bb | 1776 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1777 | |
8feceb67 VT |
1778 | switch (cmd) { |
1779 | case SET_KEY: | |
1f03baad | 1780 | ret = ath9k_cmn_key_config(common, vif, sta, key); |
6ace2891 JM |
1781 | if (ret >= 0) { |
1782 | key->hw_key_idx = ret; | |
8feceb67 VT |
1783 | /* push IV and Michael MIC generation to stack */ |
1784 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1785 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1786 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1787 | if (sc->sc_ah->sw_mgmt_crypto && |
1788 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1789 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1790 | ret = 0; |
8feceb67 VT |
1791 | } |
1792 | break; | |
1793 | case DISABLE_KEY: | |
1f03baad | 1794 | ath9k_cmn_key_delete(common, key); |
8feceb67 VT |
1795 | break; |
1796 | default: | |
1797 | ret = -EINVAL; | |
1798 | } | |
f078f209 | 1799 | |
3cbb5dd7 | 1800 | ath9k_ps_restore(sc); |
141b38b6 S |
1801 | mutex_unlock(&sc->mutex); |
1802 | ||
8feceb67 VT |
1803 | return ret; |
1804 | } | |
f078f209 | 1805 | |
8feceb67 VT |
1806 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1807 | struct ieee80211_vif *vif, | |
1808 | struct ieee80211_bss_conf *bss_conf, | |
1809 | u32 changed) | |
1810 | { | |
bce048d7 JM |
1811 | struct ath_wiphy *aphy = hw->priv; |
1812 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1813 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1814 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1815 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1816 | int slottime; |
c6089ccc | 1817 | int error; |
f078f209 | 1818 | |
141b38b6 S |
1819 | mutex_lock(&sc->mutex); |
1820 | ||
c6089ccc S |
1821 | if (changed & BSS_CHANGED_BSSID) { |
1822 | /* Set BSSID */ | |
1823 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1824 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1825 | common->curaid = 0; |
f2b2143e | 1826 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1827 | |
c6089ccc S |
1828 | /* Set aggregation protection mode parameters */ |
1829 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1830 | |
c6089ccc S |
1831 | /* Only legacy IBSS for now */ |
1832 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1833 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1834 | |
c6089ccc S |
1835 | ath_print(common, ATH_DBG_CONFIG, |
1836 | "BSSID: %pM aid: 0x%x\n", | |
1837 | common->curbssid, common->curaid); | |
2d0ddec5 | 1838 | |
c6089ccc S |
1839 | /* need to reconfigure the beacon */ |
1840 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1841 | } | |
2d0ddec5 | 1842 | |
c6089ccc S |
1843 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1844 | if ((changed & BSS_CHANGED_BEACON) || | |
1845 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1846 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1847 | error = ath_beacon_alloc(aphy, vif); | |
1848 | if (!error) | |
1849 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1850 | } |
1851 | ||
1852 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1853 | if (bss_conf->use_short_slot) | |
1854 | slottime = 9; | |
1855 | else | |
1856 | slottime = 20; | |
1857 | if (vif->type == NL80211_IFTYPE_AP) { | |
1858 | /* | |
1859 | * Defer update, so that connected stations can adjust | |
1860 | * their settings at the same time. | |
1861 | * See beacon.c for more details | |
1862 | */ | |
1863 | sc->beacon.slottime = slottime; | |
1864 | sc->beacon.updateslot = UPDATE; | |
1865 | } else { | |
1866 | ah->slottime = slottime; | |
1867 | ath9k_hw_init_global_settings(ah); | |
1868 | } | |
2d0ddec5 JB |
1869 | } |
1870 | ||
c6089ccc S |
1871 | /* Disable transmission of beacons */ |
1872 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1873 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1874 | |
c6089ccc S |
1875 | if (changed & BSS_CHANGED_BEACON_INT) { |
1876 | sc->beacon_interval = bss_conf->beacon_int; | |
1877 | /* | |
1878 | * In case of AP mode, the HW TSF has to be reset | |
1879 | * when the beacon interval changes. | |
1880 | */ | |
1881 | if (vif->type == NL80211_IFTYPE_AP) { | |
1882 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1883 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1884 | error = ath_beacon_alloc(aphy, vif); |
1885 | if (!error) | |
1886 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1887 | } else { |
1888 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1889 | } |
1890 | } | |
1891 | ||
8feceb67 | 1892 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1893 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1894 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1895 | if (bss_conf->use_short_preamble) |
1896 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1897 | else | |
1898 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1899 | } | |
f078f209 | 1900 | |
8feceb67 | 1901 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1902 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1903 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1904 | if (bss_conf->use_cts_prot && |
1905 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1906 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1907 | else | |
1908 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1909 | } | |
f078f209 | 1910 | |
8feceb67 | 1911 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1912 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1913 | bss_conf->assoc); |
5640b08e | 1914 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 1915 | } |
141b38b6 S |
1916 | |
1917 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1918 | } |
f078f209 | 1919 | |
8feceb67 VT |
1920 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1921 | { | |
1922 | u64 tsf; | |
bce048d7 JM |
1923 | struct ath_wiphy *aphy = hw->priv; |
1924 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1925 | |
141b38b6 S |
1926 | mutex_lock(&sc->mutex); |
1927 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
1928 | mutex_unlock(&sc->mutex); | |
f078f209 | 1929 | |
8feceb67 VT |
1930 | return tsf; |
1931 | } | |
f078f209 | 1932 | |
3b5d665b AF |
1933 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1934 | { | |
bce048d7 JM |
1935 | struct ath_wiphy *aphy = hw->priv; |
1936 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1937 | |
141b38b6 S |
1938 | mutex_lock(&sc->mutex); |
1939 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
1940 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
1941 | } |
1942 | ||
8feceb67 VT |
1943 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1944 | { | |
bce048d7 JM |
1945 | struct ath_wiphy *aphy = hw->priv; |
1946 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 1947 | |
141b38b6 | 1948 | mutex_lock(&sc->mutex); |
21526d57 LR |
1949 | |
1950 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1951 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1952 | ath9k_ps_restore(sc); |
1953 | ||
141b38b6 | 1954 | mutex_unlock(&sc->mutex); |
8feceb67 | 1955 | } |
f078f209 | 1956 | |
8feceb67 | 1957 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1958 | struct ieee80211_vif *vif, |
141b38b6 S |
1959 | enum ieee80211_ampdu_mlme_action action, |
1960 | struct ieee80211_sta *sta, | |
1961 | u16 tid, u16 *ssn) | |
8feceb67 | 1962 | { |
bce048d7 JM |
1963 | struct ath_wiphy *aphy = hw->priv; |
1964 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1965 | int ret = 0; |
f078f209 | 1966 | |
85ad181e JB |
1967 | local_bh_disable(); |
1968 | ||
8feceb67 VT |
1969 | switch (action) { |
1970 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
1971 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
1972 | ret = -ENOTSUPP; | |
8feceb67 VT |
1973 | break; |
1974 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1975 | break; |
1976 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1977 | ath9k_ps_wakeup(sc); |
f83da965 | 1978 | ath_tx_aggr_start(sc, sta, tid, ssn); |
c951ad35 | 1979 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1980 | ath9k_ps_restore(sc); |
8feceb67 VT |
1981 | break; |
1982 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1983 | ath9k_ps_wakeup(sc); |
f83da965 | 1984 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1985 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1986 | ath9k_ps_restore(sc); |
8feceb67 | 1987 | break; |
b1720231 | 1988 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1989 | ath9k_ps_wakeup(sc); |
8469cdef | 1990 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1991 | ath9k_ps_restore(sc); |
8469cdef | 1992 | break; |
8feceb67 | 1993 | default: |
c46917bb LR |
1994 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1995 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
1996 | } |
1997 | ||
85ad181e JB |
1998 | local_bh_enable(); |
1999 | ||
8feceb67 | 2000 | return ret; |
f078f209 LR |
2001 | } |
2002 | ||
62dad5b0 BP |
2003 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2004 | struct survey_info *survey) | |
2005 | { | |
2006 | struct ath_wiphy *aphy = hw->priv; | |
2007 | struct ath_softc *sc = aphy->sc; | |
2008 | struct ath_hw *ah = sc->sc_ah; | |
2009 | struct ath_common *common = ath9k_hw_common(ah); | |
2010 | struct ieee80211_conf *conf = &hw->conf; | |
2011 | ||
2012 | if (idx != 0) | |
2013 | return -ENOENT; | |
2014 | ||
2015 | survey->channel = conf->channel; | |
2016 | survey->filled = SURVEY_INFO_NOISE_DBM; | |
2017 | survey->noise = common->ani.noise_floor; | |
2018 | ||
2019 | return 0; | |
2020 | } | |
2021 | ||
0c98de65 S |
2022 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2023 | { | |
bce048d7 JM |
2024 | struct ath_wiphy *aphy = hw->priv; |
2025 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2026 | |
3d832611 | 2027 | mutex_lock(&sc->mutex); |
8089cc47 | 2028 | if (ath9k_wiphy_scanning(sc)) { |
8089cc47 | 2029 | /* |
30888338 LR |
2030 | * There is a race here in mac80211 but fixing it requires |
2031 | * we revisit how we handle the scan complete callback. | |
2032 | * After mac80211 fixes we will not have configured hardware | |
2033 | * to the home channel nor would we have configured the RX | |
2034 | * filter yet. | |
8089cc47 | 2035 | */ |
3d832611 | 2036 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
2037 | return; |
2038 | } | |
2039 | ||
2040 | aphy->state = ATH_WIPHY_SCAN; | |
2041 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
0c98de65 | 2042 | sc->sc_flags |= SC_OP_SCANNING; |
3d832611 | 2043 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2044 | } |
2045 | ||
30888338 LR |
2046 | /* |
2047 | * XXX: this requires a revisit after the driver | |
2048 | * scan_complete gets moved to another place/removed in mac80211. | |
2049 | */ | |
0c98de65 S |
2050 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) |
2051 | { | |
bce048d7 JM |
2052 | struct ath_wiphy *aphy = hw->priv; |
2053 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2054 | |
3d832611 | 2055 | mutex_lock(&sc->mutex); |
8089cc47 | 2056 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 2057 | sc->sc_flags &= ~SC_OP_SCANNING; |
3d832611 | 2058 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2059 | } |
2060 | ||
e239d859 FF |
2061 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2062 | { | |
2063 | struct ath_wiphy *aphy = hw->priv; | |
2064 | struct ath_softc *sc = aphy->sc; | |
2065 | struct ath_hw *ah = sc->sc_ah; | |
2066 | ||
2067 | mutex_lock(&sc->mutex); | |
2068 | ah->coverage_class = coverage_class; | |
2069 | ath9k_hw_init_global_settings(ah); | |
2070 | mutex_unlock(&sc->mutex); | |
2071 | } | |
2072 | ||
6baff7f9 | 2073 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2074 | .tx = ath9k_tx, |
2075 | .start = ath9k_start, | |
2076 | .stop = ath9k_stop, | |
2077 | .add_interface = ath9k_add_interface, | |
2078 | .remove_interface = ath9k_remove_interface, | |
2079 | .config = ath9k_config, | |
8feceb67 | 2080 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2081 | .sta_add = ath9k_sta_add, |
2082 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2083 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2084 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2085 | .set_key = ath9k_set_key, |
8feceb67 | 2086 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2087 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2088 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2089 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2090 | .get_survey = ath9k_get_survey, |
0c98de65 S |
2091 | .sw_scan_start = ath9k_sw_scan_start, |
2092 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2093 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2094 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2095 | }; |