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Commit | Line | Data |
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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
b7f080cf | 17 | #include <linux/dma-mapping.h> |
394cf0a1 | 18 | #include "ath9k.h" |
b622a720 | 19 | #include "ar9003_mac.h" |
f078f209 LR |
20 | |
21 | #define BITS_PER_BYTE 8 | |
22 | #define OFDM_PLCP_BITS 22 | |
f078f209 LR |
23 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) |
24 | #define L_STF 8 | |
25 | #define L_LTF 8 | |
26 | #define L_SIG 4 | |
27 | #define HT_SIG 8 | |
28 | #define HT_STF 4 | |
29 | #define HT_LTF(_ns) (4 * (_ns)) | |
30 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
31 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
aa5955c3 FF |
32 | #define TIME_SYMBOLS(t) ((t) >> 2) |
33 | #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) | |
f078f209 LR |
34 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) |
35 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
36 | ||
f078f209 | 37 | |
c6663876 | 38 | static u16 bits_per_symbol[][2] = { |
f078f209 LR |
39 | /* 20MHz 40MHz */ |
40 | { 26, 54 }, /* 0: BPSK */ | |
41 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
42 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
43 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
44 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
45 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
46 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
47 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
f078f209 LR |
48 | }; |
49 | ||
82b873af | 50 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
44f1d26c FF |
51 | struct ath_atx_tid *tid, struct sk_buff *skb); |
52 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |
d94a461d FF |
53 | int tx_flags, struct ath_txq *txq, |
54 | struct ieee80211_sta *sta); | |
e8324357 | 55 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 56 | struct ath_txq *txq, struct list_head *bf_q, |
d94a461d | 57 | struct ieee80211_sta *sta, |
156369fa | 58 | struct ath_tx_status *ts, int txok); |
102e0572 | 59 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
fce041be | 60 | struct list_head *head, bool internal); |
0cdd5c60 FF |
61 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
62 | struct ath_tx_status *ts, int nframes, int nbad, | |
3afd21e7 | 63 | int txok); |
90fa539c FF |
64 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
65 | int seqno); | |
44f1d26c FF |
66 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
67 | struct ath_txq *txq, | |
68 | struct ath_atx_tid *tid, | |
249ee722 | 69 | struct sk_buff *skb); |
50f08edf THJ |
70 | static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, |
71 | struct ath_tx_control *txctl); | |
c4288390 | 72 | |
545750d3 | 73 | enum { |
0e668cde FF |
74 | MCS_HT20, |
75 | MCS_HT20_SGI, | |
545750d3 FF |
76 | MCS_HT40, |
77 | MCS_HT40_SGI, | |
78 | }; | |
79 | ||
e8324357 S |
80 | /*********************/ |
81 | /* Aggregation logic */ | |
82 | /*********************/ | |
f078f209 | 83 | |
d94a461d FF |
84 | static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) |
85 | { | |
86 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
87 | struct ieee80211_sta *sta = info->status.status_driver_data[0]; | |
88 | ||
3fd2f544 FF |
89 | if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS | |
90 | IEEE80211_TX_STATUS_EOSP)) { | |
d94a461d FF |
91 | ieee80211_tx_status(hw, skb); |
92 | return; | |
93 | } | |
94 | ||
95 | if (sta) | |
96 | ieee80211_tx_status_noskb(hw, sta, info); | |
97 | ||
98 | dev_kfree_skb(skb); | |
99 | } | |
100 | ||
ef1b6cd9 | 101 | void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) |
1512a486 | 102 | __releases(&txq->axq_lock) |
23de5dc9 | 103 | { |
d94a461d | 104 | struct ieee80211_hw *hw = sc->hw; |
23de5dc9 FF |
105 | struct sk_buff_head q; |
106 | struct sk_buff *skb; | |
107 | ||
108 | __skb_queue_head_init(&q); | |
109 | skb_queue_splice_init(&txq->complete_q, &q); | |
110 | spin_unlock_bh(&txq->axq_lock); | |
111 | ||
112 | while ((skb = __skb_dequeue(&q))) | |
d94a461d | 113 | ath_tx_status(hw, skb); |
23de5dc9 FF |
114 | } |
115 | ||
63fefa05 | 116 | void __ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
ff37e337 | 117 | { |
0453531e FF |
118 | struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; |
119 | struct ath_chanctx *ctx = avp->chanctx; | |
63fefa05 THJ |
120 | struct ath_acq *acq; |
121 | struct list_head *tid_list; | |
122 | u8 acno = TID_TO_WME_AC(tid->tidno); | |
0453531e | 123 | |
63fefa05 | 124 | if (!ctx || !list_empty(&tid->list)) |
0453531e | 125 | return; |
ff37e337 | 126 | |
63fefa05 THJ |
127 | |
128 | acq = &ctx->acq[acno]; | |
129 | if ((sc->airtime_flags & AIRTIME_USE_NEW_QUEUES) && | |
130 | tid->an->airtime_deficit[acno] > 0) | |
131 | tid_list = &acq->acq_new; | |
132 | else | |
133 | tid_list = &acq->acq_old; | |
134 | ||
135 | list_add_tail(&tid->list, tid_list); | |
e8324357 | 136 | } |
f078f209 | 137 | |
63fefa05 THJ |
138 | void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
139 | { | |
140 | struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; | |
141 | struct ath_chanctx *ctx = avp->chanctx; | |
142 | struct ath_acq *acq; | |
143 | ||
144 | if (!ctx || !list_empty(&tid->list)) | |
145 | return; | |
146 | ||
147 | acq = &ctx->acq[TID_TO_WME_AC(tid->tidno)]; | |
148 | spin_lock_bh(&acq->lock); | |
149 | __ath_tx_queue_tid(sc, tid); | |
150 | spin_unlock_bh(&acq->lock); | |
151 | } | |
152 | ||
153 | ||
50f08edf THJ |
154 | void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue) |
155 | { | |
156 | struct ath_softc *sc = hw->priv; | |
157 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
158 | struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv; | |
159 | struct ath_txq *txq = tid->txq; | |
160 | ||
161 | ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n", | |
162 | queue->sta ? queue->sta->addr : queue->vif->addr, | |
163 | tid->tidno); | |
164 | ||
165 | ath_txq_lock(sc, txq); | |
166 | ||
167 | tid->has_queued = true; | |
63fefa05 | 168 | ath_tx_queue_tid(sc, tid); |
50f08edf THJ |
169 | ath_txq_schedule(sc, txq); |
170 | ||
171 | ath_txq_unlock(sc, txq); | |
172 | } | |
173 | ||
2d42efc4 | 174 | static struct ath_frame_info *get_frame_info(struct sk_buff *skb) |
76e45221 FF |
175 | { |
176 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 FF |
177 | BUILD_BUG_ON(sizeof(struct ath_frame_info) > |
178 | sizeof(tx_info->rate_driver_data)); | |
179 | return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; | |
76e45221 FF |
180 | } |
181 | ||
156369fa FF |
182 | static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) |
183 | { | |
f89d1bc4 FF |
184 | if (!tid->an->sta) |
185 | return; | |
186 | ||
156369fa FF |
187 | ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, |
188 | seqno << IEEE80211_SEQ_SEQ_SHIFT); | |
189 | } | |
190 | ||
79acac07 FF |
191 | static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, |
192 | struct ath_buf *bf) | |
193 | { | |
194 | ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, | |
195 | ARRAY_SIZE(bf->rates)); | |
196 | } | |
197 | ||
a4943ccb FF |
198 | static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, |
199 | struct sk_buff *skb) | |
200 | { | |
d954cd77 | 201 | struct ath_frame_info *fi = get_frame_info(skb); |
d954cd77 | 202 | int q = fi->txq; |
a4943ccb | 203 | |
d954cd77 | 204 | if (q < 0) |
a4943ccb FF |
205 | return; |
206 | ||
d954cd77 | 207 | txq = sc->tx.txq_map[q]; |
a4943ccb FF |
208 | if (WARN_ON(--txq->pending_frames < 0)) |
209 | txq->pending_frames = 0; | |
210 | ||
a4943ccb FF |
211 | } |
212 | ||
1803d02d FF |
213 | static struct ath_atx_tid * |
214 | ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) | |
215 | { | |
39731b78 | 216 | u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; |
1803d02d FF |
217 | return ATH_AN_2_TID(an, tidno); |
218 | } | |
219 | ||
50f08edf THJ |
220 | static struct sk_buff * |
221 | ath_tid_pull(struct ath_atx_tid *tid) | |
222 | { | |
223 | struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv); | |
224 | struct ath_softc *sc = tid->an->sc; | |
225 | struct ieee80211_hw *hw = sc->hw; | |
226 | struct ath_tx_control txctl = { | |
227 | .txq = tid->txq, | |
228 | .sta = tid->an->sta, | |
229 | }; | |
230 | struct sk_buff *skb; | |
231 | struct ath_frame_info *fi; | |
232 | int q; | |
233 | ||
234 | if (!tid->has_queued) | |
235 | return NULL; | |
236 | ||
237 | skb = ieee80211_tx_dequeue(hw, txq); | |
238 | if (!skb) { | |
239 | tid->has_queued = false; | |
240 | return NULL; | |
241 | } | |
242 | ||
243 | if (ath_tx_prepare(hw, skb, &txctl)) { | |
244 | ieee80211_free_txskb(hw, skb); | |
245 | return NULL; | |
246 | } | |
247 | ||
248 | q = skb_get_queue_mapping(skb); | |
249 | if (tid->txq == sc->tx.txq_map[q]) { | |
250 | fi = get_frame_info(skb); | |
251 | fi->txq = q; | |
252 | ++tid->txq->pending_frames; | |
253 | } | |
254 | ||
255 | return skb; | |
256 | } | |
257 | ||
258 | ||
a7586ee4 FF |
259 | static bool ath_tid_has_buffered(struct ath_atx_tid *tid) |
260 | { | |
50f08edf | 261 | return !skb_queue_empty(&tid->retry_q) || tid->has_queued; |
a7586ee4 FF |
262 | } |
263 | ||
264 | static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid) | |
265 | { | |
bb195ff6 FF |
266 | struct sk_buff *skb; |
267 | ||
268 | skb = __skb_dequeue(&tid->retry_q); | |
269 | if (!skb) | |
50f08edf | 270 | skb = ath_tid_pull(tid); |
bb195ff6 FF |
271 | |
272 | return skb; | |
a7586ee4 FF |
273 | } |
274 | ||
08c96abd | 275 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 276 | { |
592fa228 | 277 | struct ath_txq *txq = tid->txq; |
56dc6336 | 278 | struct sk_buff *skb; |
e8324357 S |
279 | struct ath_buf *bf; |
280 | struct list_head bf_head; | |
90fa539c | 281 | struct ath_tx_status ts; |
2d42efc4 | 282 | struct ath_frame_info *fi; |
156369fa | 283 | bool sendbar = false; |
f078f209 | 284 | |
90fa539c | 285 | INIT_LIST_HEAD(&bf_head); |
e6a9854b | 286 | |
90fa539c | 287 | memset(&ts, 0, sizeof(ts)); |
f078f209 | 288 | |
2800e82b | 289 | while ((skb = __skb_dequeue(&tid->retry_q))) { |
56dc6336 FF |
290 | fi = get_frame_info(skb); |
291 | bf = fi->bf; | |
249ee722 | 292 | if (!bf) { |
2800e82b FF |
293 | ath_txq_skb_done(sc, txq, skb); |
294 | ieee80211_free_txskb(sc->hw, skb); | |
295 | continue; | |
249ee722 FF |
296 | } |
297 | ||
8fed1408 | 298 | if (fi->baw_tracked) { |
6a0ddaef | 299 | ath_tx_update_baw(sc, tid, bf->bf_state.seqno); |
156369fa | 300 | sendbar = true; |
90fa539c | 301 | } |
2800e82b FF |
302 | |
303 | list_add_tail(&bf->list, &bf_head); | |
d94a461d | 304 | ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); |
528f0c6b | 305 | } |
f078f209 | 306 | |
08c96abd | 307 | if (sendbar) { |
23de5dc9 | 308 | ath_txq_unlock(sc, txq); |
156369fa | 309 | ath_send_bar(tid, tid->seq_start); |
23de5dc9 FF |
310 | ath_txq_lock(sc, txq); |
311 | } | |
528f0c6b | 312 | } |
f078f209 | 313 | |
e8324357 S |
314 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
315 | int seqno) | |
528f0c6b | 316 | { |
e8324357 | 317 | int index, cindex; |
f078f209 | 318 | |
e8324357 S |
319 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
320 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 321 | |
81ee13ba | 322 | __clear_bit(cindex, tid->tx_buf); |
528f0c6b | 323 | |
81ee13ba | 324 | while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { |
e8324357 S |
325 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); |
326 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
f9437543 FF |
327 | if (tid->bar_index >= 0) |
328 | tid->bar_index--; | |
e8324357 | 329 | } |
528f0c6b | 330 | } |
f078f209 | 331 | |
e8324357 | 332 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
8fed1408 | 333 | struct ath_buf *bf) |
528f0c6b | 334 | { |
8fed1408 FF |
335 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
336 | u16 seqno = bf->bf_state.seqno; | |
e8324357 | 337 | int index, cindex; |
528f0c6b | 338 | |
2d3bcba0 | 339 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
e8324357 | 340 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); |
81ee13ba | 341 | __set_bit(cindex, tid->tx_buf); |
8fed1408 | 342 | fi->baw_tracked = 1; |
f078f209 | 343 | |
e8324357 S |
344 | if (index >= ((tid->baw_tail - tid->baw_head) & |
345 | (ATH_TID_MAX_BUFS - 1))) { | |
346 | tid->baw_tail = cindex; | |
347 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 348 | } |
f078f209 LR |
349 | } |
350 | ||
e8324357 S |
351 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
352 | struct ath_atx_tid *tid) | |
f078f209 | 353 | |
f078f209 | 354 | { |
56dc6336 | 355 | struct sk_buff *skb; |
e8324357 S |
356 | struct ath_buf *bf; |
357 | struct list_head bf_head; | |
db1a052b | 358 | struct ath_tx_status ts; |
2d42efc4 | 359 | struct ath_frame_info *fi; |
db1a052b FF |
360 | |
361 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 362 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 363 | |
a7586ee4 | 364 | while ((skb = ath_tid_dequeue(tid))) { |
56dc6336 FF |
365 | fi = get_frame_info(skb); |
366 | bf = fi->bf; | |
f078f209 | 367 | |
44f1d26c | 368 | if (!bf) { |
d94a461d | 369 | ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL); |
44f1d26c FF |
370 | continue; |
371 | } | |
372 | ||
56dc6336 | 373 | list_add_tail(&bf->list, &bf_head); |
d94a461d | 374 | ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); |
e8324357 | 375 | } |
f078f209 LR |
376 | } |
377 | ||
fec247c0 | 378 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
da647626 | 379 | struct sk_buff *skb, int count) |
f078f209 | 380 | { |
8b7f8532 | 381 | struct ath_frame_info *fi = get_frame_info(skb); |
f11cc949 | 382 | struct ath_buf *bf = fi->bf; |
e8324357 | 383 | struct ieee80211_hdr *hdr; |
da647626 | 384 | int prev = fi->retries; |
f078f209 | 385 | |
fec247c0 | 386 | TX_STAT_INC(txq->axq_qnum, a_retries); |
da647626 FF |
387 | fi->retries += count; |
388 | ||
389 | if (prev > 0) | |
2d42efc4 | 390 | return; |
f078f209 | 391 | |
e8324357 S |
392 | hdr = (struct ieee80211_hdr *)skb->data; |
393 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f11cc949 FF |
394 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, |
395 | sizeof(*hdr), DMA_TO_DEVICE); | |
f078f209 LR |
396 | } |
397 | ||
0a8cea84 | 398 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
d43f3015 | 399 | { |
0a8cea84 | 400 | struct ath_buf *bf = NULL; |
d43f3015 S |
401 | |
402 | spin_lock_bh(&sc->tx.txbuflock); | |
0a8cea84 FF |
403 | |
404 | if (unlikely(list_empty(&sc->tx.txbuf))) { | |
8a46097a VT |
405 | spin_unlock_bh(&sc->tx.txbuflock); |
406 | return NULL; | |
407 | } | |
0a8cea84 FF |
408 | |
409 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); | |
410 | list_del(&bf->list); | |
411 | ||
d43f3015 S |
412 | spin_unlock_bh(&sc->tx.txbuflock); |
413 | ||
0a8cea84 FF |
414 | return bf; |
415 | } | |
416 | ||
417 | static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) | |
418 | { | |
419 | spin_lock_bh(&sc->tx.txbuflock); | |
420 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
421 | spin_unlock_bh(&sc->tx.txbuflock); | |
422 | } | |
423 | ||
424 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) | |
425 | { | |
426 | struct ath_buf *tbf; | |
427 | ||
428 | tbf = ath_tx_get_buffer(sc); | |
429 | if (WARN_ON(!tbf)) | |
430 | return NULL; | |
431 | ||
d43f3015 S |
432 | ATH_TXBUF_RESET(tbf); |
433 | ||
434 | tbf->bf_mpdu = bf->bf_mpdu; | |
435 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
d826c832 | 436 | memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); |
d43f3015 | 437 | tbf->bf_state = bf->bf_state; |
86c7d8d4 | 438 | tbf->bf_state.stale = false; |
d43f3015 S |
439 | |
440 | return tbf; | |
441 | } | |
442 | ||
b572d033 FF |
443 | static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, |
444 | struct ath_tx_status *ts, int txok, | |
445 | int *nframes, int *nbad) | |
446 | { | |
2d42efc4 | 447 | struct ath_frame_info *fi; |
b572d033 FF |
448 | u16 seq_st = 0; |
449 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
450 | int ba_index; | |
451 | int isaggr = 0; | |
452 | ||
453 | *nbad = 0; | |
454 | *nframes = 0; | |
455 | ||
b572d033 FF |
456 | isaggr = bf_isaggr(bf); |
457 | if (isaggr) { | |
458 | seq_st = ts->ts_seqnum; | |
459 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
460 | } | |
461 | ||
462 | while (bf) { | |
2d42efc4 | 463 | fi = get_frame_info(bf->bf_mpdu); |
6a0ddaef | 464 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); |
b572d033 FF |
465 | |
466 | (*nframes)++; | |
467 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
468 | (*nbad)++; | |
469 | ||
470 | bf = bf->bf_next; | |
471 | } | |
472 | } | |
473 | ||
474 | ||
d43f3015 S |
475 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, |
476 | struct ath_buf *bf, struct list_head *bf_q, | |
d94a461d | 477 | struct ieee80211_sta *sta, |
315c457f | 478 | struct ath_atx_tid *tid, |
1381559b | 479 | struct ath_tx_status *ts, int txok) |
f078f209 | 480 | { |
e8324357 S |
481 | struct ath_node *an = NULL; |
482 | struct sk_buff *skb; | |
1286ec6d | 483 | struct ieee80211_hdr *hdr; |
76d5a9e8 | 484 | struct ieee80211_tx_info *tx_info; |
d43f3015 | 485 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
56dc6336 FF |
486 | struct list_head bf_head; |
487 | struct sk_buff_head bf_pending; | |
156369fa | 488 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; |
f078f209 | 489 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 | 490 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
6fe7cc71 | 491 | bool rc_update = true, isba; |
78c4653a | 492 | struct ieee80211_tx_rate rates[4]; |
2d42efc4 | 493 | struct ath_frame_info *fi; |
ebd02287 | 494 | int nframes; |
daa5c408 | 495 | bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); |
da647626 | 496 | int i, retries; |
156369fa | 497 | int bar_index = -1; |
f078f209 | 498 | |
a22be22a | 499 | skb = bf->bf_mpdu; |
1286ec6d S |
500 | hdr = (struct ieee80211_hdr *)skb->data; |
501 | ||
76d5a9e8 | 502 | tx_info = IEEE80211_SKB_CB(skb); |
76d5a9e8 | 503 | |
79acac07 | 504 | memcpy(rates, bf->rates, sizeof(rates)); |
78c4653a | 505 | |
da647626 FF |
506 | retries = ts->ts_longretry + 1; |
507 | for (i = 0; i < ts->ts_rateindex; i++) | |
508 | retries += rates[i].count; | |
509 | ||
1286ec6d | 510 | if (!sta) { |
31e79a59 FF |
511 | INIT_LIST_HEAD(&bf_head); |
512 | while (bf) { | |
513 | bf_next = bf->bf_next; | |
514 | ||
50676b81 | 515 | if (!bf->bf_state.stale || bf_next != NULL) |
31e79a59 FF |
516 | list_move_tail(&bf->list, &bf_head); |
517 | ||
d94a461d | 518 | ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0); |
31e79a59 FF |
519 | |
520 | bf = bf_next; | |
521 | } | |
1286ec6d | 522 | return; |
f078f209 LR |
523 | } |
524 | ||
1286ec6d | 525 | an = (struct ath_node *)sta->drv_priv; |
156369fa | 526 | seq_first = tid->seq_start; |
6fe7cc71 | 527 | isba = ts->ts_flags & ATH9K_TX_BA; |
1286ec6d | 528 | |
b11b160d FF |
529 | /* |
530 | * The hardware occasionally sends a tx status for the wrong TID. | |
531 | * In this case, the BA status cannot be considered valid and all | |
532 | * subframes need to be retransmitted | |
6fe7cc71 SE |
533 | * |
534 | * Only BlockAcks have a TID and therefore normal Acks cannot be | |
535 | * checked | |
b11b160d | 536 | */ |
1803d02d | 537 | if (isba && tid->tidno != ts->tid) |
b11b160d FF |
538 | txok = false; |
539 | ||
e8324357 | 540 | isaggr = bf_isaggr(bf); |
d43f3015 | 541 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 542 | |
d43f3015 | 543 | if (isaggr && txok) { |
db1a052b FF |
544 | if (ts->ts_flags & ATH9K_TX_BA) { |
545 | seq_st = ts->ts_seqnum; | |
546 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 547 | } else { |
d43f3015 S |
548 | /* |
549 | * AR5416 can become deaf/mute when BA | |
550 | * issue happens. Chip needs to be reset. | |
551 | * But AP code may have sychronization issues | |
552 | * when perform internal reset in this routine. | |
553 | * Only enable reset in STA mode for now. | |
554 | */ | |
2660b81a | 555 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 556 | needreset = 1; |
e8324357 | 557 | } |
f078f209 LR |
558 | } |
559 | ||
56dc6336 | 560 | __skb_queue_head_init(&bf_pending); |
f078f209 | 561 | |
b572d033 | 562 | ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); |
e8324357 | 563 | while (bf) { |
6a0ddaef FF |
564 | u16 seqno = bf->bf_state.seqno; |
565 | ||
f0b8220c | 566 | txfail = txpending = sendbar = 0; |
e8324357 | 567 | bf_next = bf->bf_next; |
f078f209 | 568 | |
78c4653a FF |
569 | skb = bf->bf_mpdu; |
570 | tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 | 571 | fi = get_frame_info(skb); |
78c4653a | 572 | |
897d7fd9 FF |
573 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || |
574 | !tid->active) { | |
08c96abd FF |
575 | /* |
576 | * Outside of the current BlockAck window, | |
577 | * maybe part of a previous session | |
578 | */ | |
579 | txfail = 1; | |
580 | } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { | |
e8324357 S |
581 | /* transmit completion, subframe is |
582 | * acked by block ack */ | |
0934af23 | 583 | acked_cnt++; |
e8324357 S |
584 | } else if (!isaggr && txok) { |
585 | /* transmit completion */ | |
0934af23 | 586 | acked_cnt++; |
b0477013 FF |
587 | } else if (flush) { |
588 | txpending = 1; | |
589 | } else if (fi->retries < ATH_MAX_SW_RETRIES) { | |
590 | if (txok || !an->sleeping) | |
591 | ath_tx_set_retry(sc, txq, bf->bf_mpdu, | |
592 | retries); | |
593 | ||
594 | txpending = 1; | |
e8324357 | 595 | } else { |
b0477013 FF |
596 | txfail = 1; |
597 | txfail_cnt++; | |
598 | bar_index = max_t(int, bar_index, | |
599 | ATH_BA_INDEX(seq_first, seqno)); | |
e8324357 | 600 | } |
f078f209 | 601 | |
fce041be FF |
602 | /* |
603 | * Make sure the last desc is reclaimed if it | |
604 | * not a holding desc. | |
605 | */ | |
56dc6336 | 606 | INIT_LIST_HEAD(&bf_head); |
50676b81 | 607 | if (bf_next != NULL || !bf_last->bf_state.stale) |
d43f3015 | 608 | list_move_tail(&bf->list, &bf_head); |
f078f209 | 609 | |
08c96abd | 610 | if (!txpending) { |
e8324357 S |
611 | /* |
612 | * complete the acked-ones/xretried ones; update | |
613 | * block-ack window | |
614 | */ | |
6a0ddaef | 615 | ath_tx_update_baw(sc, tid, seqno); |
f078f209 | 616 | |
8a92e2ee | 617 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
78c4653a | 618 | memcpy(tx_info->control.rates, rates, sizeof(rates)); |
3afd21e7 | 619 | ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); |
8a92e2ee | 620 | rc_update = false; |
982e0395 LB |
621 | if (bf == bf->bf_lastbf) |
622 | ath_dynack_sample_tx_ts(sc->sc_ah, | |
623 | bf->bf_mpdu, | |
fc62b3c9 | 624 | ts, sta); |
8a92e2ee VT |
625 | } |
626 | ||
d94a461d | 627 | ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts, |
156369fa | 628 | !txfail); |
e8324357 | 629 | } else { |
86a22acf FF |
630 | if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { |
631 | tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; | |
632 | ieee80211_sta_eosp(sta); | |
633 | } | |
d43f3015 | 634 | /* retry the un-acked ones */ |
50676b81 | 635 | if (bf->bf_next == NULL && bf_last->bf_state.stale) { |
b0477013 FF |
636 | struct ath_buf *tbf; |
637 | ||
638 | tbf = ath_clone_txbuf(sc, bf_last); | |
639 | /* | |
640 | * Update tx baw and complete the | |
641 | * frame with failed status if we | |
642 | * run out of tx buf. | |
643 | */ | |
644 | if (!tbf) { | |
b0477013 | 645 | ath_tx_update_baw(sc, tid, seqno); |
b0477013 FF |
646 | |
647 | ath_tx_complete_buf(sc, bf, txq, | |
d94a461d FF |
648 | &bf_head, NULL, ts, |
649 | 0); | |
b0477013 FF |
650 | bar_index = max_t(int, bar_index, |
651 | ATH_BA_INDEX(seq_first, seqno)); | |
652 | break; | |
c41d92dc | 653 | } |
b0477013 FF |
654 | |
655 | fi->bf = tbf; | |
e8324357 S |
656 | } |
657 | ||
658 | /* | |
659 | * Put this buffer to the temporary pending | |
660 | * queue to retain ordering | |
661 | */ | |
56dc6336 | 662 | __skb_queue_tail(&bf_pending, skb); |
e8324357 S |
663 | } |
664 | ||
665 | bf = bf_next; | |
f078f209 | 666 | } |
f078f209 | 667 | |
4cee7861 | 668 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
56dc6336 | 669 | if (!skb_queue_empty(&bf_pending)) { |
5519541d | 670 | if (an->sleeping) |
042ec453 | 671 | ieee80211_sta_set_buffered(sta, tid->tidno, true); |
5519541d | 672 | |
bb195ff6 | 673 | skb_queue_splice_tail(&bf_pending, &tid->retry_q); |
26a64259 | 674 | if (!an->sleeping) { |
63fefa05 | 675 | ath_tx_queue_tid(sc, tid); |
26a64259 | 676 | |
adfbda62 | 677 | if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) |
592fa228 | 678 | tid->clear_ps_filter = true; |
26a64259 | 679 | } |
4cee7861 FF |
680 | } |
681 | ||
23de5dc9 FF |
682 | if (bar_index >= 0) { |
683 | u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); | |
684 | ||
685 | if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) | |
686 | tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); | |
687 | ||
688 | ath_txq_unlock(sc, txq); | |
689 | ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); | |
690 | ath_txq_lock(sc, txq); | |
691 | } | |
692 | ||
124b979b RM |
693 | if (needreset) |
694 | ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); | |
e8324357 | 695 | } |
f078f209 | 696 | |
81b51950 FF |
697 | static bool bf_is_ampdu_not_probing(struct ath_buf *bf) |
698 | { | |
699 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
700 | return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); | |
701 | } | |
702 | ||
a6e56d74 FF |
703 | static void ath_tx_count_airtime(struct ath_softc *sc, struct ath_node *an, |
704 | struct ath_atx_tid *tid, struct ath_buf *bf, | |
705 | struct ath_tx_status *ts) | |
63fefa05 | 706 | { |
a6e56d74 | 707 | struct ath_txq *txq = tid->txq; |
63fefa05 | 708 | u32 airtime = 0; |
a6e56d74 | 709 | int i; |
63fefa05 THJ |
710 | |
711 | airtime += ts->duration * (ts->ts_longretry + 1); | |
a6e56d74 FF |
712 | for(i = 0; i < ts->ts_rateindex; i++) { |
713 | int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i); | |
714 | airtime += rate_dur * bf->rates[i].count; | |
715 | } | |
63fefa05 | 716 | |
a6e56d74 FF |
717 | if (sc->airtime_flags & AIRTIME_USE_TX) { |
718 | int q = txq->mac80211_qnum; | |
719 | struct ath_acq *acq = &sc->cur_chan->acq[q]; | |
63fefa05 | 720 | |
63fefa05 | 721 | spin_lock_bh(&acq->lock); |
a6e56d74 FF |
722 | an->airtime_deficit[q] -= airtime; |
723 | if (an->airtime_deficit[q] <= 0) | |
724 | __ath_tx_queue_tid(sc, tid); | |
63fefa05 THJ |
725 | spin_unlock_bh(&acq->lock); |
726 | } | |
727 | ath_debug_airtime(sc, an, 0, airtime); | |
63fefa05 THJ |
728 | } |
729 | ||
81b51950 FF |
730 | static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, |
731 | struct ath_tx_status *ts, struct ath_buf *bf, | |
732 | struct list_head *bf_head) | |
733 | { | |
d94a461d | 734 | struct ieee80211_hw *hw = sc->hw; |
0c585dda | 735 | struct ieee80211_tx_info *info; |
d94a461d FF |
736 | struct ieee80211_sta *sta; |
737 | struct ieee80211_hdr *hdr; | |
315c457f | 738 | struct ath_atx_tid *tid = NULL; |
81b51950 FF |
739 | bool txok, flush; |
740 | ||
741 | txok = !(ts->ts_status & ATH9K_TXERR_MASK); | |
742 | flush = !!(ts->ts_status & ATH9K_TX_FLUSH); | |
743 | txq->axq_tx_inprogress = false; | |
744 | ||
745 | txq->axq_depth--; | |
746 | if (bf_is_ampdu_not_probing(bf)) | |
747 | txq->axq_ampdu_depth--; | |
748 | ||
315dd114 FF |
749 | ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, |
750 | ts->ts_rateindex); | |
d94a461d FF |
751 | |
752 | hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; | |
753 | sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); | |
315c457f FF |
754 | if (sta) { |
755 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
756 | tid = ath_get_skb_tid(sc, an, bf->bf_mpdu); | |
a6e56d74 | 757 | ath_tx_count_airtime(sc, an, tid, bf, ts); |
315c457f FF |
758 | if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) |
759 | tid->clear_ps_filter = true; | |
760 | } | |
d94a461d | 761 | |
81b51950 | 762 | if (!bf_isampdu(bf)) { |
0c585dda FF |
763 | if (!flush) { |
764 | info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
765 | memcpy(info->control.rates, bf->rates, | |
766 | sizeof(info->control.rates)); | |
81b51950 | 767 | ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); |
fc62b3c9 LB |
768 | ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts, |
769 | sta); | |
0c585dda | 770 | } |
d94a461d | 771 | ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok); |
81b51950 | 772 | } else |
315c457f | 773 | ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok); |
81b51950 | 774 | |
73364b0c | 775 | if (!flush) |
81b51950 FF |
776 | ath_txq_schedule(sc, txq); |
777 | } | |
778 | ||
1a6e9d0f RM |
779 | static bool ath_lookup_legacy(struct ath_buf *bf) |
780 | { | |
781 | struct sk_buff *skb; | |
782 | struct ieee80211_tx_info *tx_info; | |
783 | struct ieee80211_tx_rate *rates; | |
784 | int i; | |
785 | ||
786 | skb = bf->bf_mpdu; | |
787 | tx_info = IEEE80211_SKB_CB(skb); | |
788 | rates = tx_info->control.rates; | |
789 | ||
059ee09b FF |
790 | for (i = 0; i < 4; i++) { |
791 | if (!rates[i].count || rates[i].idx < 0) | |
792 | break; | |
793 | ||
1a6e9d0f RM |
794 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) |
795 | return true; | |
796 | } | |
797 | ||
798 | return false; | |
799 | } | |
800 | ||
e8324357 S |
801 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
802 | struct ath_atx_tid *tid) | |
f078f209 | 803 | { |
528f0c6b S |
804 | struct sk_buff *skb; |
805 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 806 | struct ieee80211_tx_rate *rates; |
d43f3015 | 807 | u32 max_4ms_framelen, frmlen; |
c0ac53fa | 808 | u16 aggr_limit, bt_aggr_limit, legacy = 0; |
592fa228 | 809 | int q = tid->txq->mac80211_qnum; |
e8324357 | 810 | int i; |
528f0c6b | 811 | |
a22be22a | 812 | skb = bf->bf_mpdu; |
528f0c6b | 813 | tx_info = IEEE80211_SKB_CB(skb); |
0c585dda | 814 | rates = bf->rates; |
528f0c6b | 815 | |
e8324357 S |
816 | /* |
817 | * Find the lowest frame length among the rate series that will have a | |
aa5955c3 | 818 | * 4ms (or TXOP limited) transmit duration. |
e8324357 S |
819 | */ |
820 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 821 | |
e8324357 | 822 | for (i = 0; i < 4; i++) { |
b0477013 | 823 | int modeidx; |
e8324357 | 824 | |
b0477013 FF |
825 | if (!rates[i].count) |
826 | continue; | |
545750d3 | 827 | |
b0477013 FF |
828 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { |
829 | legacy = 1; | |
830 | break; | |
f078f209 | 831 | } |
b0477013 FF |
832 | |
833 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
834 | modeidx = MCS_HT40; | |
835 | else | |
836 | modeidx = MCS_HT20; | |
837 | ||
838 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
839 | modeidx++; | |
840 | ||
aa5955c3 | 841 | frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; |
b0477013 | 842 | max_4ms_framelen = min(max_4ms_framelen, frmlen); |
f078f209 | 843 | } |
e63835b0 | 844 | |
f078f209 | 845 | /* |
e8324357 S |
846 | * limit aggregate size by the minimum rate if rate selected is |
847 | * not a probe rate, if rate selected is a probe rate then | |
848 | * avoid aggregation of this packet. | |
f078f209 | 849 | */ |
e8324357 S |
850 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
851 | return 0; | |
f078f209 | 852 | |
c0ac53fa SM |
853 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); |
854 | ||
855 | /* | |
856 | * Override the default aggregation limit for BTCOEX. | |
857 | */ | |
858 | bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); | |
859 | if (bt_aggr_limit) | |
860 | aggr_limit = bt_aggr_limit; | |
f078f209 | 861 | |
4ef70841 S |
862 | if (tid->an->maxampdu) |
863 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 864 | |
e8324357 S |
865 | return aggr_limit; |
866 | } | |
f078f209 | 867 | |
e8324357 | 868 | /* |
d43f3015 | 869 | * Returns the number of delimiters to be added to |
e8324357 | 870 | * meet the minimum required mpdudensity. |
e8324357 S |
871 | */ |
872 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
7a12dfdb RM |
873 | struct ath_buf *bf, u16 frmlen, |
874 | bool first_subfrm) | |
e8324357 | 875 | { |
7a12dfdb | 876 | #define FIRST_DESC_NDELIMS 60 |
4ef70841 | 877 | u32 nsymbits, nsymbols; |
e8324357 | 878 | u16 minlen; |
545750d3 | 879 | u8 flags, rix; |
c6663876 | 880 | int width, streams, half_gi, ndelim, mindelim; |
2d42efc4 | 881 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
e8324357 S |
882 | |
883 | /* Select standard number of delimiters based on frame length alone */ | |
884 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
885 | |
886 | /* | |
e8324357 S |
887 | * If encryption enabled, hardware requires some more padding between |
888 | * subframes. | |
889 | * TODO - this could be improved to be dependent on the rate. | |
890 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 891 | */ |
4f6760b0 RM |
892 | if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && |
893 | !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) | |
e8324357 | 894 | ndelim += ATH_AGGR_ENCRYPTDELIM; |
f078f209 | 895 | |
7a12dfdb RM |
896 | /* |
897 | * Add delimiter when using RTS/CTS with aggregation | |
898 | * and non enterprise AR9003 card | |
899 | */ | |
3459731a FF |
900 | if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && |
901 | (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) | |
7a12dfdb RM |
902 | ndelim = max(ndelim, FIRST_DESC_NDELIMS); |
903 | ||
e8324357 S |
904 | /* |
905 | * Convert desired mpdu density from microeconds to bytes based | |
906 | * on highest rate in rate series (i.e. first rate) to determine | |
907 | * required minimum length for subframe. Take into account | |
908 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 909 | * |
e8324357 S |
910 | * If there is no mpdu density restriction, no further calculation |
911 | * is needed. | |
912 | */ | |
4ef70841 S |
913 | |
914 | if (tid->an->mpdudensity == 0) | |
e8324357 | 915 | return ndelim; |
f078f209 | 916 | |
79acac07 FF |
917 | rix = bf->rates[0].idx; |
918 | flags = bf->rates[0].flags; | |
e8324357 S |
919 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; |
920 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 921 | |
e8324357 | 922 | if (half_gi) |
4ef70841 | 923 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 924 | else |
4ef70841 | 925 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 926 | |
e8324357 S |
927 | if (nsymbols == 0) |
928 | nsymbols = 1; | |
f078f209 | 929 | |
c6663876 FF |
930 | streams = HT_RC_2_STREAMS(rix); |
931 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | |
e8324357 | 932 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; |
f078f209 | 933 | |
e8324357 | 934 | if (frmlen < minlen) { |
e8324357 S |
935 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
936 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
937 | } |
938 | ||
e8324357 | 939 | return ndelim; |
f078f209 LR |
940 | } |
941 | ||
86a22acf FF |
942 | static struct ath_buf * |
943 | ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, | |
50f08edf | 944 | struct ath_atx_tid *tid) |
f078f209 | 945 | { |
73364b0c | 946 | struct ieee80211_tx_info *tx_info; |
2d42efc4 | 947 | struct ath_frame_info *fi; |
50f08edf | 948 | struct sk_buff *skb, *first_skb = NULL; |
86a22acf | 949 | struct ath_buf *bf; |
6a0ddaef | 950 | u16 seqno; |
f078f209 | 951 | |
86a22acf | 952 | while (1) { |
50f08edf | 953 | skb = ath_tid_dequeue(tid); |
86a22acf FF |
954 | if (!skb) |
955 | break; | |
956 | ||
56dc6336 FF |
957 | fi = get_frame_info(skb); |
958 | bf = fi->bf; | |
44f1d26c | 959 | if (!fi->bf) |
249ee722 | 960 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); |
563299d8 FF |
961 | else |
962 | bf->bf_state.stale = false; | |
56dc6336 | 963 | |
249ee722 | 964 | if (!bf) { |
a4943ccb | 965 | ath_txq_skb_done(sc, txq, skb); |
249ee722 | 966 | ieee80211_free_txskb(sc->hw, skb); |
44f1d26c | 967 | continue; |
249ee722 | 968 | } |
44f1d26c | 969 | |
73364b0c FF |
970 | bf->bf_next = NULL; |
971 | bf->bf_lastbf = bf; | |
972 | ||
973 | tx_info = IEEE80211_SKB_CB(skb); | |
974 | tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
c01fac1c FF |
975 | |
976 | /* | |
977 | * No aggregation session is running, but there may be frames | |
978 | * from a previous session or a failed attempt in the queue. | |
979 | * Send them out as normal data frames | |
980 | */ | |
981 | if (!tid->active) | |
982 | tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; | |
983 | ||
73364b0c FF |
984 | if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { |
985 | bf->bf_state.bf_type = 0; | |
986 | return bf; | |
987 | } | |
988 | ||
399c6489 | 989 | bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; |
44f1d26c | 990 | seqno = bf->bf_state.seqno; |
f078f209 | 991 | |
d43f3015 | 992 | /* do not step over block-ack window */ |
50f08edf THJ |
993 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { |
994 | __skb_queue_tail(&tid->retry_q, skb); | |
995 | ||
996 | /* If there are other skbs in the retry q, they are | |
997 | * probably within the BAW, so loop immediately to get | |
998 | * one of them. Otherwise the queue can get stuck. */ | |
999 | if (!skb_queue_is_first(&tid->retry_q, skb) && | |
1000 | !WARN_ON(skb == first_skb)) { | |
1001 | if(!first_skb) /* infinite loop prevention */ | |
1002 | first_skb = skb; | |
1003 | continue; | |
1004 | } | |
e8324357 | 1005 | break; |
50f08edf | 1006 | } |
f078f209 | 1007 | |
f9437543 FF |
1008 | if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { |
1009 | struct ath_tx_status ts = {}; | |
1010 | struct list_head bf_head; | |
1011 | ||
1012 | INIT_LIST_HEAD(&bf_head); | |
1013 | list_add(&bf->list, &bf_head); | |
f9437543 | 1014 | ath_tx_update_baw(sc, tid, seqno); |
d94a461d | 1015 | ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); |
f9437543 FF |
1016 | continue; |
1017 | } | |
1018 | ||
86a22acf FF |
1019 | return bf; |
1020 | } | |
1021 | ||
1022 | return NULL; | |
1023 | } | |
1024 | ||
50f08edf | 1025 | static int |
2800e82b FF |
1026 | ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, |
1027 | struct ath_atx_tid *tid, struct list_head *bf_q, | |
50f08edf | 1028 | struct ath_buf *bf_first) |
86a22acf FF |
1029 | { |
1030 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) | |
2800e82b | 1031 | struct ath_buf *bf = bf_first, *bf_prev = NULL; |
a1cd94d3 | 1032 | int nframes = 0, ndelim; |
86a22acf | 1033 | u16 aggr_limit = 0, al = 0, bpad = 0, |
a1cd94d3 | 1034 | al_delta, h_baw = tid->baw_size / 2; |
86a22acf FF |
1035 | struct ieee80211_tx_info *tx_info; |
1036 | struct ath_frame_info *fi; | |
1037 | struct sk_buff *skb; | |
50f08edf | 1038 | |
86a22acf | 1039 | |
2800e82b FF |
1040 | bf = bf_first; |
1041 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
86a22acf | 1042 | |
50f08edf THJ |
1043 | while (bf) |
1044 | { | |
86a22acf FF |
1045 | skb = bf->bf_mpdu; |
1046 | fi = get_frame_info(skb); | |
1047 | ||
d43f3015 | 1048 | /* do not exceed aggregation limit */ |
2d42efc4 | 1049 | al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; |
a1cd94d3 FF |
1050 | if (nframes) { |
1051 | if (aggr_limit < al + bpad + al_delta || | |
2800e82b | 1052 | ath_lookup_legacy(bf) || nframes >= h_baw) |
50f08edf | 1053 | goto stop; |
f078f209 | 1054 | |
a1cd94d3 | 1055 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
2800e82b FF |
1056 | if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || |
1057 | !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) | |
50f08edf | 1058 | goto stop; |
e8324357 | 1059 | } |
f078f209 | 1060 | |
d43f3015 | 1061 | /* add padding for previous frame to aggregation length */ |
e8324357 | 1062 | al += bpad + al_delta; |
f078f209 | 1063 | |
e8324357 S |
1064 | /* |
1065 | * Get the delimiters needed to meet the MPDU | |
1066 | * density for this node. | |
1067 | */ | |
7a12dfdb RM |
1068 | ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, |
1069 | !nframes); | |
e8324357 | 1070 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 1071 | |
7a12dfdb | 1072 | nframes++; |
e8324357 | 1073 | bf->bf_next = NULL; |
f078f209 | 1074 | |
d43f3015 | 1075 | /* link buffers of this frame to the aggregate */ |
8fed1408 FF |
1076 | if (!fi->baw_tracked) |
1077 | ath_tx_addto_baw(sc, tid, bf); | |
399c6489 | 1078 | bf->bf_state.ndelim = ndelim; |
56dc6336 | 1079 | |
56dc6336 | 1080 | list_add_tail(&bf->list, bf_q); |
399c6489 | 1081 | if (bf_prev) |
e8324357 | 1082 | bf_prev->bf_next = bf; |
399c6489 | 1083 | |
e8324357 | 1084 | bf_prev = bf; |
fec247c0 | 1085 | |
50f08edf THJ |
1086 | bf = ath_tx_get_tid_subframe(sc, txq, tid); |
1087 | } | |
1088 | goto finish; | |
1089 | stop: | |
1090 | __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); | |
1091 | finish: | |
2800e82b FF |
1092 | bf = bf_first; |
1093 | bf->bf_lastbf = bf_prev; | |
1094 | ||
1095 | if (bf == bf_prev) { | |
1096 | al = get_frame_info(bf->bf_mpdu)->framelen; | |
1097 | bf->bf_state.bf_type = BUF_AMPDU; | |
1098 | } else { | |
1099 | TX_STAT_INC(txq->axq_qnum, a_aggr); | |
1100 | } | |
1101 | ||
50f08edf | 1102 | return al; |
e8324357 S |
1103 | #undef PADBYTES |
1104 | } | |
f078f209 | 1105 | |
38dad7ba FF |
1106 | /* |
1107 | * rix - rate index | |
1108 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1109 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1110 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1111 | */ | |
63fefa05 THJ |
1112 | u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, |
1113 | int width, int half_gi, bool shortPreamble) | |
38dad7ba FF |
1114 | { |
1115 | u32 nbits, nsymbits, duration, nsymbols; | |
1116 | int streams; | |
1117 | ||
1118 | /* find number of symbols: PLCP + data */ | |
1119 | streams = HT_RC_2_STREAMS(rix); | |
1120 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1121 | nsymbits = bits_per_symbol[rix % 8][width] * streams; | |
1122 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1123 | ||
1124 | if (!half_gi) | |
1125 | duration = SYMBOL_TIME(nsymbols); | |
1126 | else | |
1127 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1128 | ||
1129 | /* addup duration for legacy/ht training and signal fields */ | |
1130 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1131 | ||
1132 | return duration; | |
1133 | } | |
1134 | ||
aa5955c3 FF |
1135 | static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) |
1136 | { | |
1137 | int streams = HT_RC_2_STREAMS(mcs); | |
1138 | int symbols, bits; | |
1139 | int bytes = 0; | |
1140 | ||
727b662c | 1141 | usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); |
aa5955c3 FF |
1142 | symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); |
1143 | bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; | |
1144 | bits -= OFDM_PLCP_BITS; | |
1145 | bytes = bits / 8; | |
aa5955c3 FF |
1146 | if (bytes > 65532) |
1147 | bytes = 65532; | |
1148 | ||
1149 | return bytes; | |
1150 | } | |
1151 | ||
1152 | void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) | |
1153 | { | |
1154 | u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; | |
1155 | int mcs; | |
1156 | ||
1157 | /* 4ms is the default (and maximum) duration */ | |
1158 | if (!txop || txop > 4096) | |
1159 | txop = 4096; | |
1160 | ||
1161 | cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; | |
1162 | cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; | |
1163 | cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; | |
1164 | cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; | |
1165 | for (mcs = 0; mcs < 32; mcs++) { | |
1166 | cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); | |
1167 | cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); | |
1168 | cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); | |
1169 | cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); | |
1170 | } | |
1171 | } | |
1172 | ||
8b537686 | 1173 | static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, |
9ddad58b | 1174 | u8 rateidx, bool is_40, bool is_cck) |
8b537686 LB |
1175 | { |
1176 | u8 max_power; | |
9ddad58b LB |
1177 | struct sk_buff *skb; |
1178 | struct ath_frame_info *fi; | |
1179 | struct ieee80211_tx_info *info; | |
8b537686 LB |
1180 | struct ath_hw *ah = sc->sc_ah; |
1181 | ||
9ddad58b | 1182 | if (sc->tx99_state || !ah->tpc_enabled) |
8b537686 LB |
1183 | return MAX_RATE_POWER; |
1184 | ||
9ddad58b | 1185 | skb = bf->bf_mpdu; |
97bf8615 | 1186 | fi = get_frame_info(skb); |
f6738218 | 1187 | info = IEEE80211_SKB_CB(skb); |
9ddad58b | 1188 | |
8b537686 | 1189 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
9ddad58b | 1190 | int txpower = fi->tx_power; |
8b537686 | 1191 | |
9ddad58b LB |
1192 | if (is_40) { |
1193 | u8 power_ht40delta; | |
1194 | struct ar5416_eeprom_def *eep = &ah->eeprom.def; | |
9bff7428 | 1195 | u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah); |
8b537686 | 1196 | |
9bff7428 | 1197 | if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) { |
9ddad58b LB |
1198 | bool is_2ghz; |
1199 | struct modal_eep_header *pmodal; | |
1200 | ||
57fbcce3 | 1201 | is_2ghz = info->band == NL80211_BAND_2GHZ; |
9ddad58b LB |
1202 | pmodal = &eep->modalHeader[is_2ghz]; |
1203 | power_ht40delta = pmodal->ht40PowerIncForPdadc; | |
1204 | } else { | |
1205 | power_ht40delta = 2; | |
1206 | } | |
1207 | txpower += power_ht40delta; | |
1208 | } | |
1209 | ||
1210 | if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || | |
1211 | AR_SREV_9271(ah)) { | |
1212 | txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; | |
1213 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1214 | s8 power_offset; | |
1215 | ||
1216 | power_offset = ah->eep_ops->get_eeprom(ah, | |
1217 | EEP_PWR_TABLE_OFFSET); | |
1218 | txpower -= 2 * power_offset; | |
1219 | } | |
1220 | ||
1221 | if (OLC_FOR_AR9280_20_LATER && is_cck) | |
1222 | txpower -= 2; | |
1223 | ||
1224 | txpower = max(txpower, 0); | |
f6738218 LB |
1225 | max_power = min_t(u8, ah->tx_power[rateidx], txpower); |
1226 | ||
1227 | /* XXX: clamp minimum TX power at 1 for AR9160 since if | |
1228 | * max_power is set to 0, frames are transmitted at max | |
1229 | * TX power | |
1230 | */ | |
1231 | if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) | |
1232 | max_power = 1; | |
9ddad58b | 1233 | } else if (!bf->bf_state.bfs_paprd) { |
8b537686 | 1234 | if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC)) |
97bf8615 | 1235 | max_power = min_t(u8, ah->tx_power_stbc[rateidx], |
f6738218 | 1236 | fi->tx_power); |
8b537686 | 1237 | else |
97bf8615 | 1238 | max_power = min_t(u8, ah->tx_power[rateidx], |
f6738218 | 1239 | fi->tx_power); |
8b537686 LB |
1240 | } else { |
1241 | max_power = ah->paprd_training_power; | |
1242 | } | |
f6738218 LB |
1243 | |
1244 | return max_power; | |
8b537686 LB |
1245 | } |
1246 | ||
493cf04f | 1247 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, |
a3835e9f | 1248 | struct ath_tx_info *info, int len, bool rts) |
38dad7ba FF |
1249 | { |
1250 | struct ath_hw *ah = sc->sc_ah; | |
13f71050 | 1251 | struct ath_common *common = ath9k_hw_common(ah); |
38dad7ba FF |
1252 | struct sk_buff *skb; |
1253 | struct ieee80211_tx_info *tx_info; | |
1254 | struct ieee80211_tx_rate *rates; | |
1255 | const struct ieee80211_rate *rate; | |
1256 | struct ieee80211_hdr *hdr; | |
80b08a8d | 1257 | struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); |
a3835e9f | 1258 | u32 rts_thresh = sc->hw->wiphy->rts_threshold; |
493cf04f FF |
1259 | int i; |
1260 | u8 rix = 0; | |
38dad7ba FF |
1261 | |
1262 | skb = bf->bf_mpdu; | |
1263 | tx_info = IEEE80211_SKB_CB(skb); | |
79acac07 | 1264 | rates = bf->rates; |
38dad7ba | 1265 | hdr = (struct ieee80211_hdr *)skb->data; |
493cf04f FF |
1266 | |
1267 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ | |
1268 | info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); | |
80b08a8d | 1269 | info->rtscts_rate = fi->rtscts_rate; |
38dad7ba | 1270 | |
79acac07 | 1271 | for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { |
9ddad58b | 1272 | bool is_40, is_sgi, is_sp, is_cck; |
38dad7ba FF |
1273 | int phy; |
1274 | ||
1275 | if (!rates[i].count || (rates[i].idx < 0)) | |
1276 | continue; | |
1277 | ||
1278 | rix = rates[i].idx; | |
493cf04f | 1279 | info->rates[i].Tries = rates[i].count; |
38dad7ba | 1280 | |
a3835e9f SM |
1281 | /* |
1282 | * Handle RTS threshold for unaggregated HT frames. | |
1283 | */ | |
1284 | if (bf_isampdu(bf) && !bf_isaggr(bf) && | |
1285 | (rates[i].flags & IEEE80211_TX_RC_MCS) && | |
1286 | unlikely(rts_thresh != (u32) -1)) { | |
1287 | if (!rts_thresh || (len > rts_thresh)) | |
1288 | rts = true; | |
1289 | } | |
1290 | ||
1291 | if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
493cf04f FF |
1292 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
1293 | info->flags |= ATH9K_TXDESC_RTSENA; | |
38dad7ba | 1294 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
493cf04f FF |
1295 | info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
1296 | info->flags |= ATH9K_TXDESC_CTSENA; | |
38dad7ba FF |
1297 | } |
1298 | ||
1299 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
493cf04f | 1300 | info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; |
38dad7ba | 1301 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) |
493cf04f | 1302 | info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; |
38dad7ba FF |
1303 | |
1304 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); | |
1305 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | |
1306 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | |
1307 | ||
1308 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | |
1309 | /* MCS rates */ | |
493cf04f FF |
1310 | info->rates[i].Rate = rix | 0x80; |
1311 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, | |
1312 | ah->txchainmask, info->rates[i].Rate); | |
1313 | info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, | |
38dad7ba FF |
1314 | is_40, is_sgi, is_sp); |
1315 | if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) | |
493cf04f | 1316 | info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; |
8b537686 | 1317 | |
9ddad58b LB |
1318 | info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, |
1319 | is_40, false); | |
38dad7ba FF |
1320 | continue; |
1321 | } | |
1322 | ||
1323 | /* legacy rates */ | |
13f71050 | 1324 | rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; |
57fbcce3 | 1325 | if ((tx_info->band == NL80211_BAND_2GHZ) && |
38dad7ba FF |
1326 | !(rate->flags & IEEE80211_RATE_ERP_G)) |
1327 | phy = WLAN_RC_PHY_CCK; | |
1328 | else | |
1329 | phy = WLAN_RC_PHY_OFDM; | |
1330 | ||
493cf04f | 1331 | info->rates[i].Rate = rate->hw_value; |
38dad7ba FF |
1332 | if (rate->hw_value_short) { |
1333 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
493cf04f | 1334 | info->rates[i].Rate |= rate->hw_value_short; |
38dad7ba FF |
1335 | } else { |
1336 | is_sp = false; | |
1337 | } | |
1338 | ||
1339 | if (bf->bf_state.bfs_paprd) | |
493cf04f | 1340 | info->rates[i].ChSel = ah->txchainmask; |
38dad7ba | 1341 | else |
493cf04f FF |
1342 | info->rates[i].ChSel = ath_txchainmask_reduction(sc, |
1343 | ah->txchainmask, info->rates[i].Rate); | |
38dad7ba | 1344 | |
493cf04f | 1345 | info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, |
38dad7ba | 1346 | phy, rate->bitrate * 100, len, rix, is_sp); |
8b537686 | 1347 | |
9ddad58b LB |
1348 | is_cck = IS_CCK_RATE(info->rates[i].Rate); |
1349 | info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, | |
1350 | is_cck); | |
38dad7ba FF |
1351 | } |
1352 | ||
1353 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
1354 | if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) | |
493cf04f | 1355 | info->flags &= ~ATH9K_TXDESC_RTSENA; |
38dad7ba FF |
1356 | |
1357 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | |
493cf04f FF |
1358 | if (info->flags & ATH9K_TXDESC_RTSENA) |
1359 | info->flags &= ~ATH9K_TXDESC_CTSENA; | |
1360 | } | |
38dad7ba | 1361 | |
493cf04f FF |
1362 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1363 | { | |
1364 | struct ieee80211_hdr *hdr; | |
1365 | enum ath9k_pkt_type htype; | |
1366 | __le16 fc; | |
1367 | ||
1368 | hdr = (struct ieee80211_hdr *)skb->data; | |
1369 | fc = hdr->frame_control; | |
38dad7ba | 1370 | |
493cf04f FF |
1371 | if (ieee80211_is_beacon(fc)) |
1372 | htype = ATH9K_PKT_TYPE_BEACON; | |
1373 | else if (ieee80211_is_probe_resp(fc)) | |
1374 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1375 | else if (ieee80211_is_atim(fc)) | |
1376 | htype = ATH9K_PKT_TYPE_ATIM; | |
1377 | else if (ieee80211_is_pspoll(fc)) | |
1378 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1379 | else | |
1380 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1381 | ||
1382 | return htype; | |
38dad7ba FF |
1383 | } |
1384 | ||
493cf04f FF |
1385 | static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, |
1386 | struct ath_txq *txq, int len) | |
399c6489 FF |
1387 | { |
1388 | struct ath_hw *ah = sc->sc_ah; | |
86a22acf | 1389 | struct ath_buf *bf_first = NULL; |
493cf04f | 1390 | struct ath_tx_info info; |
a3835e9f SM |
1391 | u32 rts_thresh = sc->hw->wiphy->rts_threshold; |
1392 | bool rts = false; | |
399c6489 | 1393 | |
493cf04f FF |
1394 | memset(&info, 0, sizeof(info)); |
1395 | info.is_first = true; | |
1396 | info.is_last = true; | |
493cf04f FF |
1397 | info.qcu = txq->axq_qnum; |
1398 | ||
399c6489 | 1399 | while (bf) { |
493cf04f | 1400 | struct sk_buff *skb = bf->bf_mpdu; |
86a22acf | 1401 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
493cf04f | 1402 | struct ath_frame_info *fi = get_frame_info(skb); |
86a22acf | 1403 | bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); |
493cf04f FF |
1404 | |
1405 | info.type = get_hw_packet_type(skb); | |
399c6489 | 1406 | if (bf->bf_next) |
493cf04f | 1407 | info.link = bf->bf_next->bf_daddr; |
399c6489 | 1408 | else |
89f927af | 1409 | info.link = (sc->tx99_state) ? bf->bf_daddr : 0; |
493cf04f | 1410 | |
86a22acf FF |
1411 | if (!bf_first) { |
1412 | bf_first = bf; | |
1413 | ||
89f927af LR |
1414 | if (!sc->tx99_state) |
1415 | info.flags = ATH9K_TXDESC_INTREQ; | |
86a22acf FF |
1416 | if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || |
1417 | txq == sc->tx.uapsdq) | |
1418 | info.flags |= ATH9K_TXDESC_CLRDMASK; | |
1419 | ||
1420 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1421 | info.flags |= ATH9K_TXDESC_NOACK; | |
1422 | if (tx_info->flags & IEEE80211_TX_CTL_LDPC) | |
1423 | info.flags |= ATH9K_TXDESC_LDPC; | |
1424 | ||
1425 | if (bf->bf_state.bfs_paprd) | |
1426 | info.flags |= (u32) bf->bf_state.bfs_paprd << | |
1427 | ATH9K_TXDESC_PAPRD_S; | |
1428 | ||
a3835e9f SM |
1429 | /* |
1430 | * mac80211 doesn't handle RTS threshold for HT because | |
1431 | * the decision has to be taken based on AMPDU length | |
1432 | * and aggregation is done entirely inside ath9k. | |
1433 | * Set the RTS/CTS flag for the first subframe based | |
1434 | * on the threshold. | |
1435 | */ | |
1436 | if (aggr && (bf == bf_first) && | |
1437 | unlikely(rts_thresh != (u32) -1)) { | |
1438 | /* | |
1439 | * "len" is the size of the entire AMPDU. | |
1440 | */ | |
1441 | if (!rts_thresh || (len > rts_thresh)) | |
1442 | rts = true; | |
1443 | } | |
bbf807bc FF |
1444 | |
1445 | if (!aggr) | |
1446 | len = fi->framelen; | |
1447 | ||
a3835e9f | 1448 | ath_buf_set_rate(sc, bf, &info, len, rts); |
86a22acf FF |
1449 | } |
1450 | ||
42cecc34 JL |
1451 | info.buf_addr[0] = bf->bf_buf_addr; |
1452 | info.buf_len[0] = skb->len; | |
493cf04f FF |
1453 | info.pkt_len = fi->framelen; |
1454 | info.keyix = fi->keyix; | |
1455 | info.keytype = fi->keytype; | |
1456 | ||
1457 | if (aggr) { | |
399c6489 | 1458 | if (bf == bf_first) |
493cf04f | 1459 | info.aggr = AGGR_BUF_FIRST; |
86a22acf | 1460 | else if (bf == bf_first->bf_lastbf) |
493cf04f FF |
1461 | info.aggr = AGGR_BUF_LAST; |
1462 | else | |
1463 | info.aggr = AGGR_BUF_MIDDLE; | |
399c6489 | 1464 | |
493cf04f FF |
1465 | info.ndelim = bf->bf_state.ndelim; |
1466 | info.aggr_len = len; | |
399c6489 FF |
1467 | } |
1468 | ||
86a22acf FF |
1469 | if (bf == bf_first->bf_lastbf) |
1470 | bf_first = NULL; | |
1471 | ||
493cf04f | 1472 | ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); |
399c6489 FF |
1473 | bf = bf->bf_next; |
1474 | } | |
1475 | } | |
1476 | ||
2800e82b FF |
1477 | static void |
1478 | ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, | |
1479 | struct ath_atx_tid *tid, struct list_head *bf_q, | |
50f08edf | 1480 | struct ath_buf *bf_first) |
2800e82b FF |
1481 | { |
1482 | struct ath_buf *bf = bf_first, *bf_prev = NULL; | |
2800e82b FF |
1483 | int nframes = 0; |
1484 | ||
1485 | do { | |
1486 | struct ieee80211_tx_info *tx_info; | |
2800e82b FF |
1487 | |
1488 | nframes++; | |
2800e82b FF |
1489 | list_add_tail(&bf->list, bf_q); |
1490 | if (bf_prev) | |
1491 | bf_prev->bf_next = bf; | |
1492 | bf_prev = bf; | |
1493 | ||
1494 | if (nframes >= 2) | |
1495 | break; | |
1496 | ||
50f08edf | 1497 | bf = ath_tx_get_tid_subframe(sc, txq, tid); |
2800e82b FF |
1498 | if (!bf) |
1499 | break; | |
1500 | ||
1501 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); | |
50f08edf THJ |
1502 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
1503 | __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); | |
2800e82b | 1504 | break; |
50f08edf | 1505 | } |
2800e82b FF |
1506 | |
1507 | ath_set_rates(tid->an->vif, tid->an->sta, bf); | |
1508 | } while (1); | |
1509 | } | |
1510 | ||
020f20f6 | 1511 | static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
63fefa05 | 1512 | struct ath_atx_tid *tid) |
e8324357 | 1513 | { |
d43f3015 | 1514 | struct ath_buf *bf; |
399c6489 | 1515 | struct ieee80211_tx_info *tx_info; |
e8324357 | 1516 | struct list_head bf_q; |
2800e82b | 1517 | int aggr_len = 0; |
50f08edf | 1518 | bool aggr; |
f078f209 | 1519 | |
020f20f6 FF |
1520 | if (!ath_tid_has_buffered(tid)) |
1521 | return false; | |
f078f209 | 1522 | |
020f20f6 | 1523 | INIT_LIST_HEAD(&bf_q); |
e8324357 | 1524 | |
50f08edf | 1525 | bf = ath_tx_get_tid_subframe(sc, txq, tid); |
020f20f6 FF |
1526 | if (!bf) |
1527 | return false; | |
f078f209 | 1528 | |
020f20f6 FF |
1529 | tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); |
1530 | aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); | |
1531 | if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || | |
50f08edf THJ |
1532 | (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { |
1533 | __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); | |
020f20f6 FF |
1534 | return false; |
1535 | } | |
2800e82b | 1536 | |
020f20f6 FF |
1537 | ath_set_rates(tid->an->vif, tid->an->sta, bf); |
1538 | if (aggr) | |
50f08edf | 1539 | aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf); |
020f20f6 | 1540 | else |
50f08edf | 1541 | ath_tx_form_burst(sc, txq, tid, &bf_q, bf); |
2800e82b | 1542 | |
020f20f6 FF |
1543 | if (list_empty(&bf_q)) |
1544 | return false; | |
f078f209 | 1545 | |
592fa228 FF |
1546 | if (tid->clear_ps_filter || tid->an->no_ps_filter) { |
1547 | tid->clear_ps_filter = false; | |
020f20f6 FF |
1548 | tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; |
1549 | } | |
f078f209 | 1550 | |
020f20f6 FF |
1551 | ath_tx_fill_desc(sc, bf, txq, aggr_len); |
1552 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); | |
1553 | return true; | |
e8324357 S |
1554 | } |
1555 | ||
231c3a1f FF |
1556 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
1557 | u16 tid, u16 *ssn) | |
e8324357 | 1558 | { |
58bb9ca8 | 1559 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 1560 | struct ath_atx_tid *txtid; |
919123d2 | 1561 | struct ath_txq *txq; |
e8324357 | 1562 | struct ath_node *an; |
313eb87f | 1563 | u8 density; |
e8324357 | 1564 | |
58bb9ca8 JD |
1565 | ath_dbg(common, XMIT, "%s called\n", __func__); |
1566 | ||
e8324357 | 1567 | an = (struct ath_node *)sta->drv_priv; |
f83da965 | 1568 | txtid = ATH_AN_2_TID(an, tid); |
592fa228 | 1569 | txq = txtid->txq; |
919123d2 FF |
1570 | |
1571 | ath_txq_lock(sc, txq); | |
231c3a1f | 1572 | |
313eb87f SE |
1573 | /* update ampdu factor/density, they may have changed. This may happen |
1574 | * in HT IBSS when a beacon with HT-info is received after the station | |
1575 | * has already been added. | |
1576 | */ | |
dd5ee59b | 1577 | if (sta->ht_cap.ht_supported) { |
5b502c86 SM |
1578 | an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
1579 | sta->ht_cap.ampdu_factor)) - 1; | |
313eb87f SE |
1580 | density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); |
1581 | an->mpdudensity = density; | |
1582 | } | |
1583 | ||
08c96abd | 1584 | txtid->active = true; |
49447f2f | 1585 | *ssn = txtid->seq_start = txtid->seq_next; |
f9437543 | 1586 | txtid->bar_index = -1; |
231c3a1f | 1587 | |
2ed72229 FF |
1588 | memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); |
1589 | txtid->baw_head = txtid->baw_tail = 0; | |
1590 | ||
919123d2 FF |
1591 | ath_txq_unlock_complete(sc, txq); |
1592 | ||
231c3a1f | 1593 | return 0; |
e8324357 | 1594 | } |
f078f209 | 1595 | |
08c96abd | 1596 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 | 1597 | { |
58bb9ca8 | 1598 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 S |
1599 | struct ath_node *an = (struct ath_node *)sta->drv_priv; |
1600 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
592fa228 | 1601 | struct ath_txq *txq = txtid->txq; |
f078f209 | 1602 | |
58bb9ca8 JD |
1603 | ath_dbg(common, XMIT, "%s called\n", __func__); |
1604 | ||
23de5dc9 | 1605 | ath_txq_lock(sc, txq); |
08c96abd | 1606 | txtid->active = false; |
08c96abd | 1607 | ath_tx_flush_tid(sc, txtid); |
23de5dc9 | 1608 | ath_txq_unlock_complete(sc, txq); |
e8324357 | 1609 | } |
f078f209 | 1610 | |
042ec453 JB |
1611 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
1612 | struct ath_node *an) | |
5519541d | 1613 | { |
58bb9ca8 | 1614 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
5519541d | 1615 | struct ath_atx_tid *tid; |
5519541d | 1616 | struct ath_txq *txq; |
5519541d FF |
1617 | int tidno; |
1618 | ||
58bb9ca8 JD |
1619 | ath_dbg(common, XMIT, "%s called\n", __func__); |
1620 | ||
50f08edf THJ |
1621 | for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { |
1622 | tid = ath_node_to_tid(an, tidno); | |
592fa228 | 1623 | txq = tid->txq; |
5519541d | 1624 | |
23de5dc9 | 1625 | ath_txq_lock(sc, txq); |
5519541d | 1626 | |
d70d848a | 1627 | if (list_empty(&tid->list)) { |
21f8aaee SG |
1628 | ath_txq_unlock(sc, txq); |
1629 | continue; | |
1630 | } | |
1631 | ||
50f08edf THJ |
1632 | if (!skb_queue_empty(&tid->retry_q)) |
1633 | ieee80211_sta_set_buffered(sta, tid->tidno, true); | |
5519541d | 1634 | |
d70d848a | 1635 | list_del_init(&tid->list); |
5519541d | 1636 | |
23de5dc9 | 1637 | ath_txq_unlock(sc, txq); |
042ec453 | 1638 | } |
5519541d FF |
1639 | } |
1640 | ||
1641 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) | |
1642 | { | |
58bb9ca8 | 1643 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
5519541d | 1644 | struct ath_atx_tid *tid; |
5519541d FF |
1645 | struct ath_txq *txq; |
1646 | int tidno; | |
1647 | ||
58bb9ca8 JD |
1648 | ath_dbg(common, XMIT, "%s called\n", __func__); |
1649 | ||
50f08edf THJ |
1650 | for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { |
1651 | tid = ath_node_to_tid(an, tidno); | |
592fa228 | 1652 | txq = tid->txq; |
5519541d | 1653 | |
23de5dc9 | 1654 | ath_txq_lock(sc, txq); |
592fa228 | 1655 | tid->clear_ps_filter = true; |
62e54dbb | 1656 | if (ath_tid_has_buffered(tid)) { |
63fefa05 | 1657 | ath_tx_queue_tid(sc, tid); |
5519541d FF |
1658 | ath_txq_schedule(sc, txq); |
1659 | } | |
23de5dc9 | 1660 | ath_txq_unlock_complete(sc, txq); |
5519541d FF |
1661 | } |
1662 | } | |
1663 | ||
86a22acf FF |
1664 | void ath9k_release_buffered_frames(struct ieee80211_hw *hw, |
1665 | struct ieee80211_sta *sta, | |
1666 | u16 tids, int nframes, | |
1667 | enum ieee80211_frame_release_type reason, | |
1668 | bool more_data) | |
1669 | { | |
1670 | struct ath_softc *sc = hw->priv; | |
1671 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
1672 | struct ath_txq *txq = sc->tx.uapsdq; | |
1673 | struct ieee80211_tx_info *info; | |
1674 | struct list_head bf_q; | |
1675 | struct ath_buf *bf_tail = NULL, *bf; | |
1676 | int sent = 0; | |
1677 | int i; | |
1678 | ||
1679 | INIT_LIST_HEAD(&bf_q); | |
1680 | for (i = 0; tids && nframes; i++, tids >>= 1) { | |
1681 | struct ath_atx_tid *tid; | |
1682 | ||
1683 | if (!(tids & 1)) | |
1684 | continue; | |
1685 | ||
1686 | tid = ATH_AN_2_TID(an, i); | |
86a22acf | 1687 | |
592fa228 | 1688 | ath_txq_lock(sc, tid->txq); |
a7586ee4 | 1689 | while (nframes > 0) { |
50f08edf | 1690 | bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid); |
86a22acf FF |
1691 | if (!bf) |
1692 | break; | |
1693 | ||
86a22acf FF |
1694 | list_add_tail(&bf->list, &bf_q); |
1695 | ath_set_rates(tid->an->vif, tid->an->sta, bf); | |
20e6e55a FF |
1696 | if (bf_isampdu(bf)) { |
1697 | ath_tx_addto_baw(sc, tid, bf); | |
1698 | bf->bf_state.bf_type &= ~BUF_AGGR; | |
1699 | } | |
86a22acf FF |
1700 | if (bf_tail) |
1701 | bf_tail->bf_next = bf; | |
1702 | ||
1703 | bf_tail = bf; | |
1704 | nframes--; | |
1705 | sent++; | |
1706 | TX_STAT_INC(txq->axq_qnum, a_queued_hw); | |
1707 | ||
50f08edf | 1708 | if (an->sta && skb_queue_empty(&tid->retry_q)) |
86a22acf FF |
1709 | ieee80211_sta_set_buffered(an->sta, i, false); |
1710 | } | |
592fa228 | 1711 | ath_txq_unlock_complete(sc, tid->txq); |
86a22acf FF |
1712 | } |
1713 | ||
1714 | if (list_empty(&bf_q)) | |
1715 | return; | |
1716 | ||
1717 | info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); | |
1718 | info->flags |= IEEE80211_TX_STATUS_EOSP; | |
1719 | ||
1720 | bf = list_first_entry(&bf_q, struct ath_buf, list); | |
1721 | ath_txq_lock(sc, txq); | |
1722 | ath_tx_fill_desc(sc, bf, txq, 0); | |
1723 | ath_tx_txqaddbuf(sc, txq, &bf_q, false); | |
1724 | ath_txq_unlock(sc, txq); | |
1725 | } | |
1726 | ||
e8324357 S |
1727 | /********************/ |
1728 | /* Queue Management */ | |
1729 | /********************/ | |
f078f209 | 1730 | |
e8324357 | 1731 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 1732 | { |
cbe61d8a | 1733 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1734 | struct ath9k_tx_queue_info qi; |
066dae93 | 1735 | static const int subtype_txq_to_hwq[] = { |
bea843c7 SM |
1736 | [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, |
1737 | [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, | |
1738 | [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, | |
1739 | [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, | |
066dae93 | 1740 | }; |
60f2d1d5 | 1741 | int axq_qnum, i; |
f078f209 | 1742 | |
e8324357 | 1743 | memset(&qi, 0, sizeof(qi)); |
066dae93 | 1744 | qi.tqi_subtype = subtype_txq_to_hwq[subtype]; |
e8324357 S |
1745 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; |
1746 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
1747 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
1748 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
1749 | |
1750 | /* | |
e8324357 S |
1751 | * Enable interrupts only for EOL and DESC conditions. |
1752 | * We mark tx descriptors to receive a DESC interrupt | |
1753 | * when a tx queue gets deep; otherwise waiting for the | |
1754 | * EOL to reap descriptors. Note that this is done to | |
1755 | * reduce interrupt load and this only defers reaping | |
1756 | * descriptors, never transmitting frames. Aside from | |
1757 | * reducing interrupts this also permits more concurrency. | |
1758 | * The only potential downside is if the tx queue backs | |
1759 | * up in which case the top half of the kernel may backup | |
1760 | * due to a lack of tx descriptors. | |
1761 | * | |
1762 | * The UAPSD queue is an exception, since we take a desc- | |
1763 | * based intr on the EOSP frames. | |
f078f209 | 1764 | */ |
afe754d6 | 1765 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
ce8fdf6e | 1766 | qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; |
afe754d6 VT |
1767 | } else { |
1768 | if (qtype == ATH9K_TX_QUEUE_UAPSD) | |
1769 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
1770 | else | |
1771 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
1772 | TXQ_FLAG_TXDESCINT_ENABLE; | |
1773 | } | |
60f2d1d5 BG |
1774 | axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); |
1775 | if (axq_qnum == -1) { | |
f078f209 | 1776 | /* |
e8324357 S |
1777 | * NB: don't print a message, this happens |
1778 | * normally on parts with too few tx queues | |
f078f209 | 1779 | */ |
e8324357 | 1780 | return NULL; |
f078f209 | 1781 | } |
60f2d1d5 BG |
1782 | if (!ATH_TXQ_SETUP(sc, axq_qnum)) { |
1783 | struct ath_txq *txq = &sc->tx.txq[axq_qnum]; | |
f078f209 | 1784 | |
60f2d1d5 BG |
1785 | txq->axq_qnum = axq_qnum; |
1786 | txq->mac80211_qnum = -1; | |
e8324357 | 1787 | txq->axq_link = NULL; |
23de5dc9 | 1788 | __skb_queue_head_init(&txq->complete_q); |
e8324357 | 1789 | INIT_LIST_HEAD(&txq->axq_q); |
e8324357 S |
1790 | spin_lock_init(&txq->axq_lock); |
1791 | txq->axq_depth = 0; | |
4b3ba66a | 1792 | txq->axq_ampdu_depth = 0; |
164ace38 | 1793 | txq->axq_tx_inprogress = false; |
60f2d1d5 | 1794 | sc->tx.txqsetup |= 1<<axq_qnum; |
e5003249 VT |
1795 | |
1796 | txq->txq_headidx = txq->txq_tailidx = 0; | |
1797 | for (i = 0; i < ATH_TXFIFO_DEPTH; i++) | |
1798 | INIT_LIST_HEAD(&txq->txq_fifo[i]); | |
e8324357 | 1799 | } |
60f2d1d5 | 1800 | return &sc->tx.txq[axq_qnum]; |
f078f209 LR |
1801 | } |
1802 | ||
e8324357 S |
1803 | int ath_txq_update(struct ath_softc *sc, int qnum, |
1804 | struct ath9k_tx_queue_info *qinfo) | |
1805 | { | |
cbe61d8a | 1806 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
1807 | int error = 0; |
1808 | struct ath9k_tx_queue_info qi; | |
1809 | ||
9680e8a3 | 1810 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
1811 | |
1812 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
1813 | qi.tqi_aifs = qinfo->tqi_aifs; | |
1814 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
1815 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
1816 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
1817 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
1818 | ||
1819 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
3800276a JP |
1820 | ath_err(ath9k_hw_common(sc->sc_ah), |
1821 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
1822 | error = -EIO; |
1823 | } else { | |
1824 | ath9k_hw_resettxqueue(ah, qnum); | |
1825 | } | |
1826 | ||
1827 | return error; | |
1828 | } | |
1829 | ||
1830 | int ath_cabq_update(struct ath_softc *sc) | |
1831 | { | |
1832 | struct ath9k_tx_queue_info qi; | |
ca900ac9 | 1833 | struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; |
e8324357 | 1834 | int qnum = sc->beacon.cabq->axq_qnum; |
f078f209 | 1835 | |
e8324357 | 1836 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1837 | |
3b3e0efb | 1838 | qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * |
7f329bbb | 1839 | ATH_CABQ_READY_TIME) / 100; |
e8324357 S |
1840 | ath_txq_update(sc, qnum, &qi); |
1841 | ||
1842 | return 0; | |
f078f209 LR |
1843 | } |
1844 | ||
fce041be | 1845 | static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, |
1381559b | 1846 | struct list_head *list) |
f078f209 | 1847 | { |
e8324357 S |
1848 | struct ath_buf *bf, *lastbf; |
1849 | struct list_head bf_head; | |
db1a052b FF |
1850 | struct ath_tx_status ts; |
1851 | ||
1852 | memset(&ts, 0, sizeof(ts)); | |
daa5c408 | 1853 | ts.ts_status = ATH9K_TX_FLUSH; |
e8324357 | 1854 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1855 | |
fce041be FF |
1856 | while (!list_empty(list)) { |
1857 | bf = list_first_entry(list, struct ath_buf, list); | |
f078f209 | 1858 | |
50676b81 | 1859 | if (bf->bf_state.stale) { |
fce041be | 1860 | list_del(&bf->list); |
f078f209 | 1861 | |
fce041be FF |
1862 | ath_tx_return_buffer(sc, bf); |
1863 | continue; | |
e8324357 | 1864 | } |
f078f209 | 1865 | |
e8324357 | 1866 | lastbf = bf->bf_lastbf; |
fce041be | 1867 | list_cut_position(&bf_head, list, &lastbf->list); |
81b51950 | 1868 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
f078f209 | 1869 | } |
fce041be | 1870 | } |
f078f209 | 1871 | |
fce041be FF |
1872 | /* |
1873 | * Drain a given TX queue (could be Beacon or Data) | |
1874 | * | |
1875 | * This assumes output has been stopped and | |
1876 | * we do not need to block ath_tx_tasklet. | |
1877 | */ | |
1381559b | 1878 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) |
fce041be | 1879 | { |
d94a461d | 1880 | rcu_read_lock(); |
23de5dc9 FF |
1881 | ath_txq_lock(sc, txq); |
1882 | ||
e5003249 | 1883 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
fce041be | 1884 | int idx = txq->txq_tailidx; |
e5003249 | 1885 | |
fce041be | 1886 | while (!list_empty(&txq->txq_fifo[idx])) { |
1381559b | 1887 | ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); |
fce041be FF |
1888 | |
1889 | INCR(idx, ATH_TXFIFO_DEPTH); | |
e5003249 | 1890 | } |
fce041be | 1891 | txq->txq_tailidx = idx; |
e5003249 | 1892 | } |
e609e2ea | 1893 | |
fce041be FF |
1894 | txq->axq_link = NULL; |
1895 | txq->axq_tx_inprogress = false; | |
1381559b | 1896 | ath_drain_txq_list(sc, txq, &txq->axq_q); |
fce041be | 1897 | |
23de5dc9 | 1898 | ath_txq_unlock_complete(sc, txq); |
d94a461d | 1899 | rcu_read_unlock(); |
f078f209 LR |
1900 | } |
1901 | ||
1381559b | 1902 | bool ath_drain_all_txq(struct ath_softc *sc) |
f078f209 | 1903 | { |
cbe61d8a | 1904 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1905 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 | 1906 | struct ath_txq *txq; |
34d25810 FF |
1907 | int i; |
1908 | u32 npend = 0; | |
043a0405 | 1909 | |
eefa01dd | 1910 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) |
080e1a25 | 1911 | return true; |
043a0405 | 1912 | |
0d51cccc | 1913 | ath9k_hw_abort_tx_dma(ah); |
043a0405 | 1914 | |
0d51cccc | 1915 | /* Check if any queue remains active */ |
043a0405 | 1916 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
0d51cccc FF |
1917 | if (!ATH_TXQ_SETUP(sc, i)) |
1918 | continue; | |
1919 | ||
10ffb6a7 FF |
1920 | if (!sc->tx.txq[i].axq_depth) |
1921 | continue; | |
1922 | ||
34d25810 FF |
1923 | if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) |
1924 | npend |= BIT(i); | |
043a0405 S |
1925 | } |
1926 | ||
e60ac9c7 FF |
1927 | if (npend) { |
1928 | RESET_STAT_INC(sc, RESET_TX_DMA_ERROR); | |
1929 | ath_dbg(common, RESET, | |
1930 | "Failed to stop TX DMA, queues=0x%03x!\n", npend); | |
1931 | } | |
043a0405 S |
1932 | |
1933 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
92460412 FF |
1934 | if (!ATH_TXQ_SETUP(sc, i)) |
1935 | continue; | |
1936 | ||
92460412 | 1937 | txq = &sc->tx.txq[i]; |
1381559b | 1938 | ath_draintxq(sc, txq); |
043a0405 | 1939 | } |
080e1a25 FF |
1940 | |
1941 | return !npend; | |
e8324357 | 1942 | } |
f078f209 | 1943 | |
043a0405 | 1944 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1945 | { |
043a0405 S |
1946 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1947 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1948 | } |
f078f209 | 1949 | |
0453531e | 1950 | /* For each acq entry, for each tid, try to schedule packets |
7755bad9 BG |
1951 | * for transmit until ampdu_depth has reached min Q depth. |
1952 | */ | |
e8324357 S |
1953 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1954 | { | |
eefa01dd | 1955 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
63fefa05 | 1956 | struct ath_atx_tid *tid; |
592fa228 | 1957 | struct list_head *tid_list; |
63fefa05 THJ |
1958 | struct ath_acq *acq; |
1959 | bool active = AIRTIME_ACTIVE(sc->airtime_flags); | |
f078f209 | 1960 | |
0453531e FF |
1961 | if (txq->mac80211_qnum < 0) |
1962 | return; | |
1963 | ||
4d9f634b SM |
1964 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) |
1965 | return; | |
1966 | ||
bff11766 | 1967 | spin_lock_bh(&sc->chan_lock); |
23bc2021 | 1968 | rcu_read_lock(); |
63fefa05 | 1969 | acq = &sc->cur_chan->acq[txq->mac80211_qnum]; |
23bc2021 | 1970 | |
63fefa05 THJ |
1971 | if (sc->cur_chan->stopped) |
1972 | goto out; | |
7755bad9 | 1973 | |
63fefa05 THJ |
1974 | begin: |
1975 | tid_list = &acq->acq_new; | |
1976 | if (list_empty(tid_list)) { | |
1977 | tid_list = &acq->acq_old; | |
1978 | if (list_empty(tid_list)) | |
1979 | goto out; | |
1980 | } | |
1981 | tid = list_first_entry(tid_list, struct ath_atx_tid, list); | |
1982 | ||
1983 | if (active && tid->an->airtime_deficit[txq->mac80211_qnum] <= 0) { | |
1984 | spin_lock_bh(&acq->lock); | |
1985 | tid->an->airtime_deficit[txq->mac80211_qnum] += ATH_AIRTIME_QUANTUM; | |
1986 | list_move_tail(&tid->list, &acq->acq_old); | |
1987 | spin_unlock_bh(&acq->lock); | |
1988 | goto begin; | |
1989 | } | |
1990 | ||
1991 | if (!ath_tid_has_buffered(tid)) { | |
1992 | spin_lock_bh(&acq->lock); | |
1993 | if ((tid_list == &acq->acq_new) && !list_empty(&acq->acq_old)) | |
1994 | list_move_tail(&tid->list, &acq->acq_old); | |
1995 | else { | |
1996 | list_del_init(&tid->list); | |
1997 | } | |
1998 | spin_unlock_bh(&acq->lock); | |
1999 | goto begin; | |
2000 | } | |
020f20f6 | 2001 | |
020f20f6 | 2002 | |
63fefa05 THJ |
2003 | /* |
2004 | * If we succeed in scheduling something, immediately restart to make | |
2005 | * sure we keep the HW busy. | |
2006 | */ | |
2007 | if(ath_tx_sched_aggr(sc, txq, tid)) { | |
2008 | if (!active) { | |
2009 | spin_lock_bh(&acq->lock); | |
2010 | list_move_tail(&tid->list, &acq->acq_old); | |
2011 | spin_unlock_bh(&acq->lock); | |
020f20f6 | 2012 | } |
63fefa05 | 2013 | goto begin; |
e8324357 | 2014 | } |
23bc2021 | 2015 | |
63fefa05 | 2016 | out: |
23bc2021 | 2017 | rcu_read_unlock(); |
bff11766 | 2018 | spin_unlock_bh(&sc->chan_lock); |
e8324357 | 2019 | } |
f078f209 | 2020 | |
0453531e FF |
2021 | void ath_txq_schedule_all(struct ath_softc *sc) |
2022 | { | |
2023 | struct ath_txq *txq; | |
2024 | int i; | |
2025 | ||
2026 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { | |
2027 | txq = sc->tx.txq_map[i]; | |
2028 | ||
2029 | spin_lock_bh(&txq->axq_lock); | |
2030 | ath_txq_schedule(sc, txq); | |
2031 | spin_unlock_bh(&txq->axq_lock); | |
2032 | } | |
2033 | } | |
2034 | ||
e8324357 S |
2035 | /***********/ |
2036 | /* TX, DMA */ | |
2037 | /***********/ | |
2038 | ||
f078f209 | 2039 | /* |
e8324357 S |
2040 | * Insert a chain of ath_buf (descriptors) on a txq and |
2041 | * assume the descriptors are already chained together by caller. | |
f078f209 | 2042 | */ |
e8324357 | 2043 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
fce041be | 2044 | struct list_head *head, bool internal) |
f078f209 | 2045 | { |
cbe61d8a | 2046 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 2047 | struct ath_common *common = ath9k_hw_common(ah); |
fce041be FF |
2048 | struct ath_buf *bf, *bf_last; |
2049 | bool puttxbuf = false; | |
2050 | bool edma; | |
f078f209 | 2051 | |
e8324357 S |
2052 | /* |
2053 | * Insert the frame on the outbound list and | |
2054 | * pass it on to the hardware. | |
2055 | */ | |
f078f209 | 2056 | |
e8324357 S |
2057 | if (list_empty(head)) |
2058 | return; | |
f078f209 | 2059 | |
fce041be | 2060 | edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
e8324357 | 2061 | bf = list_first_entry(head, struct ath_buf, list); |
fce041be | 2062 | bf_last = list_entry(head->prev, struct ath_buf, list); |
f078f209 | 2063 | |
d2182b69 JP |
2064 | ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", |
2065 | txq->axq_qnum, txq->axq_depth); | |
f078f209 | 2066 | |
fce041be FF |
2067 | if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { |
2068 | list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); | |
e5003249 | 2069 | INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); |
fce041be | 2070 | puttxbuf = true; |
e8324357 | 2071 | } else { |
e5003249 VT |
2072 | list_splice_tail_init(head, &txq->axq_q); |
2073 | ||
fce041be FF |
2074 | if (txq->axq_link) { |
2075 | ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); | |
d2182b69 | 2076 | ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", |
226afe68 JP |
2077 | txq->axq_qnum, txq->axq_link, |
2078 | ito64(bf->bf_daddr), bf->bf_desc); | |
fce041be FF |
2079 | } else if (!edma) |
2080 | puttxbuf = true; | |
2081 | ||
2082 | txq->axq_link = bf_last->bf_desc; | |
2083 | } | |
2084 | ||
2085 | if (puttxbuf) { | |
2086 | TX_STAT_INC(txq->axq_qnum, puttxbuf); | |
2087 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
d2182b69 | 2088 | ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", |
fce041be FF |
2089 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); |
2090 | } | |
2091 | ||
89f927af | 2092 | if (!edma || sc->tx99_state) { |
8d8d3fdc | 2093 | TX_STAT_INC(txq->axq_qnum, txstart); |
e5003249 | 2094 | ath9k_hw_txstart(ah, txq->axq_qnum); |
e8324357 | 2095 | } |
fce041be FF |
2096 | |
2097 | if (!internal) { | |
f56e121d FF |
2098 | while (bf) { |
2099 | txq->axq_depth++; | |
2100 | if (bf_is_ampdu_not_probing(bf)) | |
2101 | txq->axq_ampdu_depth++; | |
2102 | ||
440c1c87 FF |
2103 | bf_last = bf->bf_lastbf; |
2104 | bf = bf_last->bf_next; | |
2105 | bf_last->bf_next = NULL; | |
f56e121d | 2106 | } |
fce041be | 2107 | } |
e8324357 | 2108 | } |
f078f209 | 2109 | |
82b873af | 2110 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
44f1d26c | 2111 | struct ath_atx_tid *tid, struct sk_buff *skb) |
e8324357 | 2112 | { |
f69727fd | 2113 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
44f1d26c FF |
2114 | struct ath_frame_info *fi = get_frame_info(skb); |
2115 | struct list_head bf_head; | |
f69727fd | 2116 | struct ath_buf *bf = fi->bf; |
44f1d26c FF |
2117 | |
2118 | INIT_LIST_HEAD(&bf_head); | |
2119 | list_add_tail(&bf->list, &bf_head); | |
399c6489 | 2120 | bf->bf_state.bf_type = 0; |
f69727fd FF |
2121 | if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { |
2122 | bf->bf_state.bf_type = BUF_AMPDU; | |
2123 | ath_tx_addto_baw(sc, tid, bf); | |
2124 | } | |
e8324357 | 2125 | |
8c6e3093 | 2126 | bf->bf_next = NULL; |
d43f3015 | 2127 | bf->bf_lastbf = bf; |
493cf04f | 2128 | ath_tx_fill_desc(sc, bf, txq, fi->framelen); |
44f1d26c | 2129 | ath_tx_txqaddbuf(sc, txq, &bf_head, false); |
fec247c0 | 2130 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
2131 | } |
2132 | ||
36323f81 TH |
2133 | static void setup_frame_info(struct ieee80211_hw *hw, |
2134 | struct ieee80211_sta *sta, | |
2135 | struct sk_buff *skb, | |
2d42efc4 | 2136 | int framelen) |
e8324357 S |
2137 | { |
2138 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2d42efc4 | 2139 | struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; |
6a0ddaef | 2140 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
80b08a8d | 2141 | const struct ieee80211_rate *rate; |
2d42efc4 | 2142 | struct ath_frame_info *fi = get_frame_info(skb); |
93ae2dd2 | 2143 | struct ath_node *an = NULL; |
2d42efc4 | 2144 | enum ath9k_key_type keytype; |
80b08a8d | 2145 | bool short_preamble = false; |
f6738218 | 2146 | u8 txpower; |
80b08a8d FF |
2147 | |
2148 | /* | |
2149 | * We check if Short Preamble is needed for the CTS rate by | |
2150 | * checking the BSS's global flag. | |
2151 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
2152 | */ | |
2153 | if (tx_info->control.vif && | |
2154 | tx_info->control.vif->bss_conf.use_short_preamble) | |
2155 | short_preamble = true; | |
e8324357 | 2156 | |
80b08a8d | 2157 | rate = ieee80211_get_rts_cts_rate(hw, tx_info); |
2d42efc4 | 2158 | keytype = ath9k_cmn_get_hw_crypto_keytype(skb); |
e8324357 | 2159 | |
93ae2dd2 FF |
2160 | if (sta) |
2161 | an = (struct ath_node *) sta->drv_priv; | |
2162 | ||
f6738218 LB |
2163 | if (tx_info->control.vif) { |
2164 | struct ieee80211_vif *vif = tx_info->control.vif; | |
2165 | ||
2166 | txpower = 2 * vif->bss_conf.txpower; | |
2167 | } else { | |
2168 | struct ath_softc *sc = hw->priv; | |
2169 | ||
2170 | txpower = sc->cur_chan->cur_txpower; | |
2171 | } | |
2172 | ||
2d42efc4 | 2173 | memset(fi, 0, sizeof(*fi)); |
d954cd77 | 2174 | fi->txq = -1; |
2d42efc4 FF |
2175 | if (hw_key) |
2176 | fi->keyix = hw_key->hw_key_idx; | |
93ae2dd2 FF |
2177 | else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) |
2178 | fi->keyix = an->ps_key; | |
2d42efc4 FF |
2179 | else |
2180 | fi->keyix = ATH9K_TXKEYIX_INVALID; | |
2181 | fi->keytype = keytype; | |
2182 | fi->framelen = framelen; | |
f6738218 | 2183 | fi->tx_power = txpower; |
09b029b6 LR |
2184 | |
2185 | if (!rate) | |
2186 | return; | |
80b08a8d FF |
2187 | fi->rtscts_rate = rate->hw_value; |
2188 | if (short_preamble) | |
2189 | fi->rtscts_rate |= rate->hw_value_short; | |
e8324357 S |
2190 | } |
2191 | ||
ea066d5a MSS |
2192 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) |
2193 | { | |
2194 | struct ath_hw *ah = sc->sc_ah; | |
2195 | struct ath9k_channel *curchan = ah->curchan; | |
365d2ebc | 2196 | |
8896934c | 2197 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && |
d77bf3eb | 2198 | (chainmask == 0x7) && (rate < 0x90)) |
ea066d5a | 2199 | return 0x3; |
365d2ebc SM |
2200 | else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && |
2201 | IS_CCK_RATE(rate)) | |
2202 | return 0x2; | |
ea066d5a MSS |
2203 | else |
2204 | return chainmask; | |
2205 | } | |
2206 | ||
44f1d26c FF |
2207 | /* |
2208 | * Assign a descriptor (and sequence number if necessary, | |
2209 | * and map buffer for DMA. Frees skb on error | |
2210 | */ | |
fa05f87a | 2211 | static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, |
04caf863 | 2212 | struct ath_txq *txq, |
fa05f87a | 2213 | struct ath_atx_tid *tid, |
249ee722 | 2214 | struct sk_buff *skb) |
f078f209 | 2215 | { |
82b873af | 2216 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2d42efc4 | 2217 | struct ath_frame_info *fi = get_frame_info(skb); |
fa05f87a | 2218 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
82b873af | 2219 | struct ath_buf *bf; |
fd09c85f | 2220 | int fragno; |
fa05f87a | 2221 | u16 seqno; |
82b873af FF |
2222 | |
2223 | bf = ath_tx_get_buffer(sc); | |
2224 | if (!bf) { | |
d2182b69 | 2225 | ath_dbg(common, XMIT, "TX buffers are full\n"); |
249ee722 | 2226 | return NULL; |
82b873af | 2227 | } |
e022edbd | 2228 | |
528f0c6b | 2229 | ATH_TXBUF_RESET(bf); |
f078f209 | 2230 | |
5998be87 | 2231 | if (tid && ieee80211_is_data_present(hdr->frame_control)) { |
fd09c85f | 2232 | fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; |
fa05f87a FF |
2233 | seqno = tid->seq_next; |
2234 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); | |
fd09c85f SM |
2235 | |
2236 | if (fragno) | |
2237 | hdr->seq_ctrl |= cpu_to_le16(fragno); | |
2238 | ||
2239 | if (!ieee80211_has_morefrags(hdr->frame_control)) | |
2240 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
2241 | ||
fa05f87a FF |
2242 | bf->bf_state.seqno = seqno; |
2243 | } | |
2244 | ||
f078f209 | 2245 | bf->bf_mpdu = skb; |
f8316df1 | 2246 | |
c1739eb3 BG |
2247 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
2248 | skb->len, DMA_TO_DEVICE); | |
2249 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { | |
f8316df1 | 2250 | bf->bf_mpdu = NULL; |
6cf9e995 | 2251 | bf->bf_buf_addr = 0; |
3800276a JP |
2252 | ath_err(ath9k_hw_common(sc->sc_ah), |
2253 | "dma_mapping_error() on TX\n"); | |
82b873af | 2254 | ath_tx_return_buffer(sc, bf); |
249ee722 | 2255 | return NULL; |
f8316df1 LR |
2256 | } |
2257 | ||
56dc6336 | 2258 | fi->bf = bf; |
04caf863 FF |
2259 | |
2260 | return bf; | |
2261 | } | |
2262 | ||
ca14405e SM |
2263 | void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) |
2264 | { | |
2265 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2266 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
2267 | struct ieee80211_vif *vif = info->control.vif; | |
2268 | struct ath_vif *avp; | |
2269 | ||
2270 | if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) | |
2271 | return; | |
2272 | ||
2273 | if (!vif) | |
2274 | return; | |
2275 | ||
2276 | avp = (struct ath_vif *)vif->drv_priv; | |
2277 | ||
2278 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
2279 | avp->seq_no += 0x10; | |
2280 | ||
2281 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
2282 | hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); | |
2283 | } | |
2284 | ||
59505c02 FF |
2285 | static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, |
2286 | struct ath_tx_control *txctl) | |
f078f209 | 2287 | { |
28d16708 FF |
2288 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
2289 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
36323f81 | 2290 | struct ieee80211_sta *sta = txctl->sta; |
f59a59fe | 2291 | struct ieee80211_vif *vif = info->control.vif; |
f89d1bc4 | 2292 | struct ath_vif *avp; |
9ac58615 | 2293 | struct ath_softc *sc = hw->priv; |
04caf863 | 2294 | int frmlen = skb->len + FCS_LEN; |
59505c02 | 2295 | int padpos, padsize; |
f078f209 | 2296 | |
a9927ba3 BG |
2297 | /* NOTE: sta can be NULL according to net/mac80211.h */ |
2298 | if (sta) | |
2299 | txctl->an = (struct ath_node *)sta->drv_priv; | |
f89d1bc4 FF |
2300 | else if (vif && ieee80211_is_data(hdr->frame_control)) { |
2301 | avp = (void *)vif->drv_priv; | |
2302 | txctl->an = &avp->mcast_node; | |
2303 | } | |
a9927ba3 | 2304 | |
04caf863 FF |
2305 | if (info->control.hw_key) |
2306 | frmlen += info->control.hw_key->icv_len; | |
2307 | ||
ca14405e | 2308 | ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); |
f078f209 | 2309 | |
59505c02 FF |
2310 | if ((vif && vif->type != NL80211_IFTYPE_AP && |
2311 | vif->type != NL80211_IFTYPE_AP_VLAN) || | |
2312 | !ieee80211_is_data(hdr->frame_control)) | |
2313 | info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; | |
2314 | ||
42cecc34 | 2315 | /* Add the padding after the header if this is not already done */ |
c60c9929 | 2316 | padpos = ieee80211_hdrlen(hdr->frame_control); |
42cecc34 JL |
2317 | padsize = padpos & 3; |
2318 | if (padsize && skb->len > padpos) { | |
2319 | if (skb_headroom(skb) < padsize) | |
2320 | return -ENOMEM; | |
28d16708 | 2321 | |
42cecc34 JL |
2322 | skb_push(skb, padsize); |
2323 | memmove(skb->data, skb->data + padsize, padpos); | |
f078f209 | 2324 | } |
f078f209 | 2325 | |
36323f81 | 2326 | setup_frame_info(hw, sta, skb, frmlen); |
59505c02 FF |
2327 | return 0; |
2328 | } | |
2329 | ||
2d42efc4 | 2330 | |
59505c02 FF |
2331 | /* Upon failure caller should free skb */ |
2332 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, | |
2333 | struct ath_tx_control *txctl) | |
2334 | { | |
2335 | struct ieee80211_hdr *hdr; | |
2336 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
2337 | struct ieee80211_sta *sta = txctl->sta; | |
2338 | struct ieee80211_vif *vif = info->control.vif; | |
d954cd77 | 2339 | struct ath_frame_info *fi = get_frame_info(skb); |
befcf7e7 | 2340 | struct ath_vif *avp = NULL; |
59505c02 FF |
2341 | struct ath_softc *sc = hw->priv; |
2342 | struct ath_txq *txq = txctl->txq; | |
2343 | struct ath_atx_tid *tid = NULL; | |
50f08edf | 2344 | struct ath_node *an = NULL; |
59505c02 | 2345 | struct ath_buf *bf; |
50f08edf | 2346 | bool ps_resp; |
d7017461 | 2347 | int q, ret; |
59505c02 | 2348 | |
befcf7e7 FF |
2349 | if (vif) |
2350 | avp = (void *)vif->drv_priv; | |
2351 | ||
6b127c71 SM |
2352 | ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); |
2353 | ||
59505c02 FF |
2354 | ret = ath_tx_prepare(hw, skb, txctl); |
2355 | if (ret) | |
2356 | return ret; | |
2357 | ||
2358 | hdr = (struct ieee80211_hdr *) skb->data; | |
2d42efc4 FF |
2359 | /* |
2360 | * At this point, the vif, hw_key and sta pointers in the tx control | |
2361 | * info are no longer valid (overwritten by the ath_frame_info data. | |
2362 | */ | |
2363 | ||
28d16708 | 2364 | q = skb_get_queue_mapping(skb); |
23de5dc9 | 2365 | |
50f08edf | 2366 | if (ps_resp) |
f2c7a793 | 2367 | txq = sc->tx.uapsdq; |
bdc21457 | 2368 | |
50f08edf THJ |
2369 | if (txctl->sta) { |
2370 | an = (struct ath_node *) sta->drv_priv; | |
2371 | tid = ath_get_skb_tid(sc, an, skb); | |
2372 | } | |
2800e82b | 2373 | |
50f08edf THJ |
2374 | ath_txq_lock(sc, txq); |
2375 | if (txq == sc->tx.txq_map[q]) { | |
2376 | fi->txq = q; | |
2377 | ++txq->pending_frames; | |
bdc21457 FF |
2378 | } |
2379 | ||
f2c7a793 | 2380 | bf = ath_tx_setup_buffer(sc, txq, tid, skb); |
bdc21457 | 2381 | if (!bf) { |
a4943ccb | 2382 | ath_txq_skb_done(sc, txq, skb); |
bdc21457 FF |
2383 | if (txctl->paprd) |
2384 | dev_kfree_skb_any(skb); | |
2385 | else | |
2386 | ieee80211_free_txskb(sc->hw, skb); | |
2387 | goto out; | |
2388 | } | |
2389 | ||
2390 | bf->bf_state.bfs_paprd = txctl->paprd; | |
2391 | ||
2392 | if (txctl->paprd) | |
2393 | bf->bf_state.bfs_paprd_timestamp = jiffies; | |
2394 | ||
79acac07 | 2395 | ath_set_rates(vif, sta, bf); |
f2c7a793 | 2396 | ath_tx_send_normal(sc, txq, tid, skb); |
3ad29529 | 2397 | |
bdc21457 | 2398 | out: |
23de5dc9 | 2399 | ath_txq_unlock(sc, txq); |
3ad29529 | 2400 | |
44f1d26c | 2401 | return 0; |
f078f209 LR |
2402 | } |
2403 | ||
59505c02 FF |
2404 | void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
2405 | struct sk_buff *skb) | |
2406 | { | |
2407 | struct ath_softc *sc = hw->priv; | |
2408 | struct ath_tx_control txctl = { | |
2409 | .txq = sc->beacon.cabq | |
2410 | }; | |
2411 | struct ath_tx_info info = {}; | |
2412 | struct ieee80211_hdr *hdr; | |
2413 | struct ath_buf *bf_tail = NULL; | |
2414 | struct ath_buf *bf; | |
2415 | LIST_HEAD(bf_q); | |
2416 | int duration = 0; | |
2417 | int max_duration; | |
2418 | ||
2419 | max_duration = | |
ca900ac9 RM |
2420 | sc->cur_chan->beacon.beacon_interval * 1000 * |
2421 | sc->cur_chan->beacon.dtim_period / ATH_BCBUF; | |
59505c02 FF |
2422 | |
2423 | do { | |
2424 | struct ath_frame_info *fi = get_frame_info(skb); | |
2425 | ||
2426 | if (ath_tx_prepare(hw, skb, &txctl)) | |
2427 | break; | |
2428 | ||
2429 | bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); | |
2430 | if (!bf) | |
2431 | break; | |
2432 | ||
2433 | bf->bf_lastbf = bf; | |
2434 | ath_set_rates(vif, NULL, bf); | |
a3835e9f | 2435 | ath_buf_set_rate(sc, bf, &info, fi->framelen, false); |
59505c02 FF |
2436 | duration += info.rates[0].PktDuration; |
2437 | if (bf_tail) | |
2438 | bf_tail->bf_next = bf; | |
2439 | ||
2440 | list_add_tail(&bf->list, &bf_q); | |
2441 | bf_tail = bf; | |
2442 | skb = NULL; | |
2443 | ||
2444 | if (duration > max_duration) | |
2445 | break; | |
2446 | ||
2447 | skb = ieee80211_get_buffered_bc(hw, vif); | |
2448 | } while(skb); | |
2449 | ||
2450 | if (skb) | |
2451 | ieee80211_free_txskb(hw, skb); | |
2452 | ||
2453 | if (list_empty(&bf_q)) | |
2454 | return; | |
2455 | ||
2456 | bf = list_first_entry(&bf_q, struct ath_buf, list); | |
2457 | hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; | |
2458 | ||
92cd4032 MK |
2459 | if (hdr->frame_control & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) { |
2460 | hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
59505c02 FF |
2461 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, |
2462 | sizeof(*hdr), DMA_TO_DEVICE); | |
2463 | } | |
2464 | ||
2465 | ath_txq_lock(sc, txctl.txq); | |
2466 | ath_tx_fill_desc(sc, bf, txctl.txq, 0); | |
2467 | ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); | |
2468 | TX_STAT_INC(txctl.txq->axq_qnum, queued); | |
2469 | ath_txq_unlock(sc, txctl.txq); | |
2470 | } | |
2471 | ||
e8324357 S |
2472 | /*****************/ |
2473 | /* TX Completion */ | |
2474 | /*****************/ | |
528f0c6b | 2475 | |
e8324357 | 2476 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
d94a461d FF |
2477 | int tx_flags, struct ath_txq *txq, |
2478 | struct ieee80211_sta *sta) | |
528f0c6b | 2479 | { |
e8324357 | 2480 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c46917bb | 2481 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 | 2482 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
a4943ccb | 2483 | int padpos, padsize; |
07c15a3f | 2484 | unsigned long flags; |
528f0c6b | 2485 | |
d2182b69 | 2486 | ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 2487 | |
51dea9be | 2488 | if (sc->sc_ah->caldata) |
4b9b42bf | 2489 | set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); |
51dea9be | 2490 | |
2b5b8f19 SM |
2491 | if (!(tx_flags & ATH_TX_ERROR)) { |
2492 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
2493 | tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; | |
2494 | else | |
2495 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
2496 | } | |
528f0c6b | 2497 | |
d94a461d FF |
2498 | if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { |
2499 | padpos = ieee80211_hdrlen(hdr->frame_control); | |
2500 | padsize = padpos & 3; | |
2501 | if (padsize && skb->len>padpos+padsize) { | |
2502 | /* | |
2503 | * Remove MAC header padding before giving the frame back to | |
2504 | * mac80211. | |
2505 | */ | |
2506 | memmove(skb->data + padsize, skb->data, padpos); | |
2507 | skb_pull(skb, padsize); | |
2508 | } | |
e8324357 | 2509 | } |
528f0c6b | 2510 | |
07c15a3f | 2511 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
c8e8868e | 2512 | if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { |
1b04b930 | 2513 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; |
d2182b69 | 2514 | ath_dbg(common, PS, |
226afe68 | 2515 | "Going back to sleep after having received TX status (0x%lx)\n", |
1b04b930 S |
2516 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
2517 | PS_WAIT_FOR_CAB | | |
2518 | PS_WAIT_FOR_PSPOLL_DATA | | |
2519 | PS_WAIT_FOR_TX_ACK)); | |
9a23f9ca | 2520 | } |
07c15a3f | 2521 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca | 2522 | |
a4943ccb | 2523 | ath_txq_skb_done(sc, txq, skb); |
d94a461d FF |
2524 | tx_info->status.status_driver_data[0] = sta; |
2525 | __skb_queue_tail(&txq->complete_q, skb); | |
e8324357 | 2526 | } |
f078f209 | 2527 | |
e8324357 | 2528 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 2529 | struct ath_txq *txq, struct list_head *bf_q, |
d94a461d | 2530 | struct ieee80211_sta *sta, |
156369fa | 2531 | struct ath_tx_status *ts, int txok) |
f078f209 | 2532 | { |
e8324357 | 2533 | struct sk_buff *skb = bf->bf_mpdu; |
3afd21e7 | 2534 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
e8324357 | 2535 | unsigned long flags; |
6b2c4032 | 2536 | int tx_flags = 0; |
f078f209 | 2537 | |
55797b1a | 2538 | if (!txok) |
6b2c4032 | 2539 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 2540 | |
3afd21e7 FF |
2541 | if (ts->ts_status & ATH9K_TXERR_FILT) |
2542 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
2543 | ||
c1739eb3 | 2544 | dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); |
6cf9e995 | 2545 | bf->bf_buf_addr = 0; |
89f927af LR |
2546 | if (sc->tx99_state) |
2547 | goto skip_tx_complete; | |
9f42c2b6 FF |
2548 | |
2549 | if (bf->bf_state.bfs_paprd) { | |
9cf04dcc MSS |
2550 | if (time_after(jiffies, |
2551 | bf->bf_state.bfs_paprd_timestamp + | |
2552 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) | |
ca369eb4 | 2553 | dev_kfree_skb_any(skb); |
78a18172 | 2554 | else |
ca369eb4 | 2555 | complete(&sc->paprd_complete); |
9f42c2b6 | 2556 | } else { |
55797b1a | 2557 | ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); |
d94a461d | 2558 | ath_tx_complete(sc, skb, tx_flags, txq, sta); |
9f42c2b6 | 2559 | } |
89f927af | 2560 | skip_tx_complete: |
6cf9e995 BG |
2561 | /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't |
2562 | * accidentally reference it later. | |
2563 | */ | |
2564 | bf->bf_mpdu = NULL; | |
e8324357 S |
2565 | |
2566 | /* | |
2567 | * Return the list of ath_buf of this mpdu to free queue | |
2568 | */ | |
2569 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
2570 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
2571 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
2572 | } |
2573 | ||
0cdd5c60 FF |
2574 | static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, |
2575 | struct ath_tx_status *ts, int nframes, int nbad, | |
3afd21e7 | 2576 | int txok) |
f078f209 | 2577 | { |
a22be22a | 2578 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 2579 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 | 2580 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
0cdd5c60 | 2581 | struct ieee80211_hw *hw = sc->hw; |
f0c255a0 | 2582 | struct ath_hw *ah = sc->sc_ah; |
8a92e2ee | 2583 | u8 i, tx_rateindex; |
f078f209 | 2584 | |
95e4acb7 | 2585 | if (txok) |
db1a052b | 2586 | tx_info->status.ack_signal = ts->ts_rssi; |
95e4acb7 | 2587 | |
db1a052b | 2588 | tx_rateindex = ts->ts_rateindex; |
8a92e2ee VT |
2589 | WARN_ON(tx_rateindex >= hw->max_rates); |
2590 | ||
3afd21e7 | 2591 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
d969847c | 2592 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; |
f078f209 | 2593 | |
b572d033 | 2594 | BUG_ON(nbad > nframes); |
ebd02287 | 2595 | } |
185d1589 RM |
2596 | tx_info->status.ampdu_len = nframes; |
2597 | tx_info->status.ampdu_ack_len = nframes - nbad; | |
ebd02287 | 2598 | |
db1a052b | 2599 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && |
3afd21e7 | 2600 | (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { |
f0c255a0 FF |
2601 | /* |
2602 | * If an underrun error is seen assume it as an excessive | |
2603 | * retry only if max frame trigger level has been reached | |
2604 | * (2 KB for single stream, and 4 KB for dual stream). | |
2605 | * Adjust the long retry as if the frame was tried | |
2606 | * hw->max_rate_tries times to affect how rate control updates | |
2607 | * PER for the failed rate. | |
2608 | * In case of congestion on the bus penalizing this type of | |
2609 | * underruns should help hardware actually transmit new frames | |
2610 | * successfully by eventually preferring slower rates. | |
2611 | * This itself should also alleviate congestion on the bus. | |
2612 | */ | |
3afd21e7 FF |
2613 | if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | |
2614 | ATH9K_TX_DELIM_UNDERRUN)) && | |
2615 | ieee80211_is_data(hdr->frame_control) && | |
83860c59 | 2616 | ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) |
f0c255a0 FF |
2617 | tx_info->status.rates[tx_rateindex].count = |
2618 | hw->max_rate_tries; | |
f078f209 | 2619 | } |
8a92e2ee | 2620 | |
545750d3 | 2621 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) { |
8a92e2ee | 2622 | tx_info->status.rates[i].count = 0; |
545750d3 FF |
2623 | tx_info->status.rates[i].idx = -1; |
2624 | } | |
8a92e2ee | 2625 | |
78c4653a | 2626 | tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; |
f078f209 LR |
2627 | } |
2628 | ||
e8324357 | 2629 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 2630 | { |
cbe61d8a | 2631 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 2632 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 2633 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 2634 | struct list_head bf_head; |
e8324357 | 2635 | struct ath_desc *ds; |
29bffa96 | 2636 | struct ath_tx_status ts; |
e8324357 | 2637 | int status; |
f078f209 | 2638 | |
d2182b69 | 2639 | ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", |
226afe68 JP |
2640 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), |
2641 | txq->axq_link); | |
f078f209 | 2642 | |
23de5dc9 | 2643 | ath_txq_lock(sc, txq); |
f078f209 | 2644 | for (;;) { |
eefa01dd | 2645 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) |
236de514 FF |
2646 | break; |
2647 | ||
f078f209 LR |
2648 | if (list_empty(&txq->axq_q)) { |
2649 | txq->axq_link = NULL; | |
73364b0c | 2650 | ath_txq_schedule(sc, txq); |
f078f209 LR |
2651 | break; |
2652 | } | |
f078f209 LR |
2653 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2654 | ||
e8324357 S |
2655 | /* |
2656 | * There is a race condition that a BH gets scheduled | |
2657 | * after sw writes TxE and before hw re-load the last | |
2658 | * descriptor to get the newly chained one. | |
2659 | * Software must keep the last DONE descriptor as a | |
2660 | * holding descriptor - software does so by marking | |
2661 | * it with the STALE flag. | |
2662 | */ | |
2663 | bf_held = NULL; | |
50676b81 | 2664 | if (bf->bf_state.stale) { |
e8324357 | 2665 | bf_held = bf; |
fce041be | 2666 | if (list_is_last(&bf_held->list, &txq->axq_q)) |
e8324357 | 2667 | break; |
fce041be FF |
2668 | |
2669 | bf = list_entry(bf_held->list.next, struct ath_buf, | |
2670 | list); | |
f078f209 LR |
2671 | } |
2672 | ||
2673 | lastbf = bf->bf_lastbf; | |
e8324357 | 2674 | ds = lastbf->bf_desc; |
f078f209 | 2675 | |
29bffa96 FF |
2676 | memset(&ts, 0, sizeof(ts)); |
2677 | status = ath9k_hw_txprocdesc(ah, ds, &ts); | |
fce041be | 2678 | if (status == -EINPROGRESS) |
e8324357 | 2679 | break; |
fce041be | 2680 | |
2dac4fb9 | 2681 | TX_STAT_INC(txq->axq_qnum, txprocdesc); |
f078f209 | 2682 | |
e8324357 S |
2683 | /* |
2684 | * Remove ath_buf's of the same transmit unit from txq, | |
2685 | * however leave the last descriptor back as the holding | |
2686 | * descriptor for hw. | |
2687 | */ | |
50676b81 | 2688 | lastbf->bf_state.stale = true; |
e8324357 | 2689 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2690 | if (!list_is_singular(&lastbf->list)) |
2691 | list_cut_position(&bf_head, | |
2692 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2693 | |
fce041be | 2694 | if (bf_held) { |
0a8cea84 | 2695 | list_del(&bf_held->list); |
0a8cea84 | 2696 | ath_tx_return_buffer(sc, bf_held); |
e8324357 | 2697 | } |
f078f209 | 2698 | |
fce041be | 2699 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
8469cdef | 2700 | } |
23de5dc9 | 2701 | ath_txq_unlock_complete(sc, txq); |
8469cdef S |
2702 | } |
2703 | ||
e8324357 | 2704 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2705 | { |
239c795d FF |
2706 | struct ath_hw *ah = sc->sc_ah; |
2707 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; | |
e8324357 | 2708 | int i; |
f078f209 | 2709 | |
d94a461d | 2710 | rcu_read_lock(); |
e8324357 S |
2711 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2712 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2713 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 | 2714 | } |
d94a461d | 2715 | rcu_read_unlock(); |
f078f209 LR |
2716 | } |
2717 | ||
e5003249 VT |
2718 | void ath_tx_edma_tasklet(struct ath_softc *sc) |
2719 | { | |
fce041be | 2720 | struct ath_tx_status ts; |
e5003249 VT |
2721 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2722 | struct ath_hw *ah = sc->sc_ah; | |
2723 | struct ath_txq *txq; | |
2724 | struct ath_buf *bf, *lastbf; | |
2725 | struct list_head bf_head; | |
99ba6a46 | 2726 | struct list_head *fifo_list; |
e5003249 | 2727 | int status; |
e5003249 | 2728 | |
d94a461d | 2729 | rcu_read_lock(); |
e5003249 | 2730 | for (;;) { |
eefa01dd | 2731 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) |
236de514 FF |
2732 | break; |
2733 | ||
fce041be | 2734 | status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); |
e5003249 VT |
2735 | if (status == -EINPROGRESS) |
2736 | break; | |
2737 | if (status == -EIO) { | |
d2182b69 | 2738 | ath_dbg(common, XMIT, "Error processing tx status\n"); |
e5003249 VT |
2739 | break; |
2740 | } | |
2741 | ||
4e0ad259 FF |
2742 | /* Process beacon completions separately */ |
2743 | if (ts.qid == sc->beacon.beaconq) { | |
2744 | sc->beacon.tx_processed = true; | |
2745 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
d074e8d5 | 2746 | |
27babf9f SM |
2747 | if (ath9k_is_chanctx_enabled()) { |
2748 | ath_chanctx_event(sc, NULL, | |
2749 | ATH_CHANCTX_EVENT_BEACON_SENT); | |
2750 | } | |
2751 | ||
4effc6fd | 2752 | ath9k_csa_update(sc); |
e5003249 | 2753 | continue; |
4e0ad259 | 2754 | } |
e5003249 | 2755 | |
fce041be | 2756 | txq = &sc->tx.txq[ts.qid]; |
e5003249 | 2757 | |
23de5dc9 | 2758 | ath_txq_lock(sc, txq); |
fce041be | 2759 | |
78ef731c SM |
2760 | TX_STAT_INC(txq->axq_qnum, txprocdesc); |
2761 | ||
99ba6a46 FF |
2762 | fifo_list = &txq->txq_fifo[txq->txq_tailidx]; |
2763 | if (list_empty(fifo_list)) { | |
23de5dc9 | 2764 | ath_txq_unlock(sc, txq); |
d1f1c0e2 | 2765 | break; |
e5003249 VT |
2766 | } |
2767 | ||
99ba6a46 | 2768 | bf = list_first_entry(fifo_list, struct ath_buf, list); |
50676b81 | 2769 | if (bf->bf_state.stale) { |
99ba6a46 FF |
2770 | list_del(&bf->list); |
2771 | ath_tx_return_buffer(sc, bf); | |
2772 | bf = list_first_entry(fifo_list, struct ath_buf, list); | |
2773 | } | |
2774 | ||
e5003249 VT |
2775 | lastbf = bf->bf_lastbf; |
2776 | ||
2777 | INIT_LIST_HEAD(&bf_head); | |
99ba6a46 FF |
2778 | if (list_is_last(&lastbf->list, fifo_list)) { |
2779 | list_splice_tail_init(fifo_list, &bf_head); | |
fce041be | 2780 | INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); |
e5003249 | 2781 | |
fce041be FF |
2782 | if (!list_empty(&txq->axq_q)) { |
2783 | struct list_head bf_q; | |
60f2d1d5 | 2784 | |
fce041be FF |
2785 | INIT_LIST_HEAD(&bf_q); |
2786 | txq->axq_link = NULL; | |
2787 | list_splice_tail_init(&txq->axq_q, &bf_q); | |
2788 | ath_tx_txqaddbuf(sc, txq, &bf_q, true); | |
2789 | } | |
99ba6a46 | 2790 | } else { |
50676b81 | 2791 | lastbf->bf_state.stale = true; |
99ba6a46 FF |
2792 | if (bf != lastbf) |
2793 | list_cut_position(&bf_head, fifo_list, | |
2794 | lastbf->list.prev); | |
fce041be | 2795 | } |
86271e46 | 2796 | |
fce041be | 2797 | ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); |
23de5dc9 | 2798 | ath_txq_unlock_complete(sc, txq); |
e5003249 | 2799 | } |
d94a461d | 2800 | rcu_read_unlock(); |
e5003249 VT |
2801 | } |
2802 | ||
e8324357 S |
2803 | /*****************/ |
2804 | /* Init, Cleanup */ | |
2805 | /*****************/ | |
f078f209 | 2806 | |
5088c2f1 VT |
2807 | static int ath_txstatus_setup(struct ath_softc *sc, int size) |
2808 | { | |
2809 | struct ath_descdma *dd = &sc->txsdma; | |
2810 | u8 txs_len = sc->sc_ah->caps.txs_len; | |
2811 | ||
2812 | dd->dd_desc_len = size * txs_len; | |
b81950b1 FF |
2813 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
2814 | &dd->dd_desc_paddr, GFP_KERNEL); | |
5088c2f1 VT |
2815 | if (!dd->dd_desc) |
2816 | return -ENOMEM; | |
2817 | ||
2818 | return 0; | |
2819 | } | |
2820 | ||
2821 | static int ath_tx_edma_init(struct ath_softc *sc) | |
2822 | { | |
2823 | int err; | |
2824 | ||
2825 | err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); | |
2826 | if (!err) | |
2827 | ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, | |
2828 | sc->txsdma.dd_desc_paddr, | |
2829 | ATH_TXSTATUS_RING_SIZE); | |
2830 | ||
2831 | return err; | |
2832 | } | |
2833 | ||
e8324357 | 2834 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2835 | { |
c46917bb | 2836 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2837 | int error = 0; |
f078f209 | 2838 | |
797fe5cb | 2839 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2840 | |
797fe5cb | 2841 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
4adfcded | 2842 | "tx", nbufs, 1, 1); |
797fe5cb | 2843 | if (error != 0) { |
3800276a JP |
2844 | ath_err(common, |
2845 | "Failed to allocate tx descriptors: %d\n", error); | |
b81950b1 | 2846 | return error; |
797fe5cb | 2847 | } |
f078f209 | 2848 | |
797fe5cb | 2849 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
5088c2f1 | 2850 | "beacon", ATH_BCBUF, 1, 1); |
797fe5cb | 2851 | if (error != 0) { |
3800276a JP |
2852 | ath_err(common, |
2853 | "Failed to allocate beacon descriptors: %d\n", error); | |
b81950b1 | 2854 | return error; |
797fe5cb | 2855 | } |
f078f209 | 2856 | |
b81950b1 | 2857 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
5088c2f1 | 2858 | error = ath_tx_edma_init(sc); |
f078f209 | 2859 | |
e8324357 | 2860 | return error; |
f078f209 LR |
2861 | } |
2862 | ||
f078f209 LR |
2863 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) |
2864 | { | |
c5170163 | 2865 | struct ath_atx_tid *tid; |
c5170163 | 2866 | int tidno, acno; |
f078f209 | 2867 | |
63fefa05 THJ |
2868 | for (acno = 0; acno < IEEE80211_NUM_ACS; acno++) |
2869 | an->airtime_deficit[acno] = ATH_AIRTIME_QUANTUM; | |
2870 | ||
50f08edf THJ |
2871 | for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { |
2872 | tid = ath_node_to_tid(an, tidno); | |
c5170163 S |
2873 | tid->an = an; |
2874 | tid->tidno = tidno; | |
2875 | tid->seq_start = tid->seq_next = 0; | |
2876 | tid->baw_size = WME_MAX_BA; | |
2877 | tid->baw_head = tid->baw_tail = 0; | |
08c96abd | 2878 | tid->active = false; |
592fa228 | 2879 | tid->clear_ps_filter = true; |
50f08edf | 2880 | tid->has_queued = false; |
bb195ff6 | 2881 | __skb_queue_head_init(&tid->retry_q); |
d70d848a | 2882 | INIT_LIST_HEAD(&tid->list); |
c5170163 | 2883 | acno = TID_TO_WME_AC(tidno); |
592fa228 | 2884 | tid->txq = sc->tx.txq_map[acno]; |
50f08edf THJ |
2885 | |
2886 | if (!an->sta) | |
2887 | break; /* just one multicast ath_atx_tid */ | |
f078f209 LR |
2888 | } |
2889 | } | |
2890 | ||
b5aa9bf9 | 2891 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 | 2892 | { |
2b40994c | 2893 | struct ath_atx_tid *tid; |
f078f209 | 2894 | struct ath_txq *txq; |
066dae93 | 2895 | int tidno; |
e8324357 | 2896 | |
00f0b164 THJ |
2897 | rcu_read_lock(); |
2898 | ||
50f08edf THJ |
2899 | for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { |
2900 | tid = ath_node_to_tid(an, tidno); | |
592fa228 | 2901 | txq = tid->txq; |
f078f209 | 2902 | |
23de5dc9 | 2903 | ath_txq_lock(sc, txq); |
2b40994c | 2904 | |
d70d848a FF |
2905 | if (!list_empty(&tid->list)) |
2906 | list_del_init(&tid->list); | |
2b40994c | 2907 | |
2b40994c | 2908 | ath_tid_drain(sc, txq, tid); |
08c96abd | 2909 | tid->active = false; |
2b40994c | 2910 | |
23de5dc9 | 2911 | ath_txq_unlock(sc, txq); |
50f08edf THJ |
2912 | |
2913 | if (!an->sta) | |
2914 | break; /* just one multicast ath_atx_tid */ | |
f078f209 | 2915 | } |
00f0b164 THJ |
2916 | |
2917 | rcu_read_unlock(); | |
f078f209 | 2918 | } |
89f927af | 2919 | |
ef6b19e4 SM |
2920 | #ifdef CONFIG_ATH9K_TX99 |
2921 | ||
89f927af LR |
2922 | int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, |
2923 | struct ath_tx_control *txctl) | |
2924 | { | |
2925 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2926 | struct ath_frame_info *fi = get_frame_info(skb); | |
2927 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2928 | struct ath_buf *bf; | |
2929 | int padpos, padsize; | |
2930 | ||
2931 | padpos = ieee80211_hdrlen(hdr->frame_control); | |
2932 | padsize = padpos & 3; | |
2933 | ||
2934 | if (padsize && skb->len > padpos) { | |
2935 | if (skb_headroom(skb) < padsize) { | |
2936 | ath_dbg(common, XMIT, | |
2937 | "tx99 padding failed\n"); | |
ba38a171 | 2938 | return -EINVAL; |
89f927af LR |
2939 | } |
2940 | ||
2941 | skb_push(skb, padsize); | |
2942 | memmove(skb->data, skb->data + padsize, padpos); | |
2943 | } | |
2944 | ||
2945 | fi->keyix = ATH9K_TXKEYIX_INVALID; | |
2946 | fi->framelen = skb->len + FCS_LEN; | |
2947 | fi->keytype = ATH9K_KEY_TYPE_CLEAR; | |
2948 | ||
2949 | bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); | |
2950 | if (!bf) { | |
2951 | ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); | |
2952 | return -EINVAL; | |
2953 | } | |
2954 | ||
d976ee0a | 2955 | ath_set_rates(sc->tx99_vif, NULL, bf); |
89f927af LR |
2956 | |
2957 | ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); | |
2958 | ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); | |
2959 | ||
2960 | ath_tx_send_normal(sc, txctl->txq, NULL, skb); | |
2961 | ||
2962 | return 0; | |
2963 | } | |
ef6b19e4 SM |
2964 | |
2965 | #endif /* CONFIG_ATH9K_TX99 */ |