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b43: Pass more RX flags to mac80211
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath9k / hw.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
394cf0a1 20#include "ath9k.h"
f078f209
LR		 21#include "initvals.h"
22
138ab2e4
VT		 23static int btcoex_enable;
24module_param(btcoex_enable, bool, 0);
25MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
4febf7b8
LR		 27#define ATH9K_CLOCK_RATE_CCK 22
28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 30
cbe61d8a
S		 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 33 enum ath9k_ht_macmode macmode);
cbe61d8a 34static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 35 struct ar5416_eeprom_def *pEepData,
f1dc5600 36 u32 reg, u32 value);
cbe61d8a
S		 37static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
f078f209 39
f1dc5600
S		 40/********************/
41/* Helper Functions */
42/********************/
f078f209 43
cbe61d8a 44static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 45{
4febf7b8 46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 47
2660b81a 48 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 52
4febf7b8 53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 54}
f078f209 55
cbe61d8a 56static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 57{
4febf7b8 58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 59
4febf7b8 60 if (conf_is_ht40(conf))
f1dc5600
S		 61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64}
f078f209 65
cbe61d8a 66static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 67{
4febf7b8 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 69
2660b81a 70 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 75}
76
cbe61d8a 77static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 78{
4febf7b8 79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 80
4febf7b8 81 if (conf_is_ht40(conf))
f1dc5600
S		 82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85}
f078f209 86
0caa7b14 87bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 88{
89 int i;
90
0caa7b14
S		 91 BUG_ON(timeout < AH_TIME_QUANTUM);
92
93 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 94 if ((REG_READ(ah, reg) & mask) == val)
95 return true;
96
97 udelay(AH_TIME_QUANTUM);
98 }
04bd4638
S		 99
100 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
0caa7b14
S		 101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 103
f1dc5600 104 return false;
f078f209
LR		 105}
106
107u32 ath9k_hw_reverse_bits(u32 val, u32 n)
108{
109 u32 retval;
110 int i;
111
112 for (i = 0, retval = 0; i < n; i++) {
113 retval = (retval << 1) | (val & 1);
114 val >>= 1;
115 }
116 return retval;
117}
118
cbe61d8a 119bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 120 u16 flags, u16 *low,
121 u16 *high)
f078f209 122{
2660b81a 123 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 124
f1dc5600
S		 125 if (flags & CHANNEL_5GHZ) {
126 *low = pCap->low_5ghz_chan;
127 *high = pCap->high_5ghz_chan;
128 return true;
f078f209 129 }
f1dc5600
S		 130 if ((flags & CHANNEL_2GHZ)) {
131 *low = pCap->low_2ghz_chan;
132 *high = pCap->high_2ghz_chan;
133 return true;
134 }
135 return false;
f078f209
LR		 136}
137
cbe61d8a 138u16 ath9k_hw_computetxtime(struct ath_hw *ah,
e63835b0 139 struct ath_rate_table *rates,
f1dc5600
S		 140 u32 frameLen, u16 rateix,
141 bool shortPreamble)
f078f209 142{
f1dc5600
S		 143 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
144 u32 kbps;
f078f209 145
e63835b0 146 kbps = rates->info[rateix].ratekbps;
f078f209 147
f1dc5600
S		 148 if (kbps == 0)
149 return 0;
f078f209 150
f1dc5600 151 switch (rates->info[rateix].phy) {
46d14a58 152 case WLAN_RC_PHY_CCK:
f1dc5600 153 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 154 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 155 phyTime >>= 1;
156 numBits = frameLen << 3;
157 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
158 break;
46d14a58 159 case WLAN_RC_PHY_OFDM:
2660b81a 160 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
162 numBits = OFDM_PLCP_BITS + (frameLen << 3);
163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164 txTime = OFDM_SIFS_TIME_QUARTER
165 + OFDM_PREAMBLE_TIME_QUARTER
166 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 167 } else if (ah->curchan &&
168 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_HALF +
173 OFDM_PREAMBLE_TIME_HALF
174 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
175 } else {
176 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
177 numBits = OFDM_PLCP_BITS + (frameLen << 3);
178 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
179 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
180 + (numSymbols * OFDM_SYMBOL_TIME);
181 }
182 break;
183 default:
04bd4638
S		 184 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
185 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 186 rates->info[rateix].phy, rateix);
187 txTime = 0;
188 break;
189 }
f078f209 190
f1dc5600
S		 191 return txTime;
192}
f078f209 193
cbe61d8a 194void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 195 struct ath9k_channel *chan,
196 struct chan_centers *centers)
f078f209 197{
f1dc5600 198 int8_t extoff;
f078f209 199
f1dc5600
S		 200 if (!IS_CHAN_HT40(chan)) {
201 centers->ctl_center = centers->ext_center =
202 centers->synth_center = chan->channel;
203 return;
f078f209 204 }
f078f209 205
f1dc5600
S		 206 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
207 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
208 centers->synth_center =
209 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
210 extoff = 1;
211 } else {
212 centers->synth_center =
213 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
214 extoff = -1;
215 }
f078f209 216
f1dc5600
S		 217 centers->ctl_center =
218 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
219 centers->ext_center =
220 centers->synth_center + (extoff *
2660b81a 221 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
f1dc5600 222 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209
LR		 223}
224
f1dc5600
S		 225/******************/
226/* Chip Revisions */
227/******************/
228
cbe61d8a 229static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 230{
f1dc5600 231 u32 val;
f078f209 232
f1dc5600 233 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 234
f1dc5600
S		 235 if (val == 0xFF) {
236 val = REG_READ(ah, AR_SREV);
d535a42a
S		 237 ah->hw_version.macVersion =
238 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
239 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 240 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 241 } else {
242 if (!AR_SREV_9100(ah))
d535a42a 243 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 244
d535a42a 245 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 246
d535a42a 247 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 248 ah->is_pciexpress = true;
f1dc5600 249 }
f078f209
LR		 250}
251
cbe61d8a 252static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 253{
f1dc5600
S		 254 u32 val;
255 int i;
f078f209 256
f1dc5600 257 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 258
f1dc5600
S		 259 for (i = 0; i < 8; i++)
260 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
261 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
262 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 263
f1dc5600 264 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 265}
266
f1dc5600
S		 267/************************************/
268/* HW Attach, Detach, Init Routines */
269/************************************/
270
cbe61d8a 271static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 272{
feed029c 273 if (AR_SREV_9100(ah))
f1dc5600 274 return;
f078f209 275
f1dc5600
S		 276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 285
f1dc5600 286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 287}
288
cbe61d8a 289static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 290{
f1dc5600
S		 291 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
292 u32 regHold[2];
293 u32 patternData[4] = { 0x55555555,
294 0xaaaaaaaa,
295 0x66666666,
296 0x99999999 };
297 int i, j;
f078f209 298
f1dc5600
S		 299 for (i = 0; i < 2; i++) {
300 u32 addr = regAddr[i];
301 u32 wrData, rdData;
f078f209 302
f1dc5600
S		 303 regHold[i] = REG_READ(ah, addr);
304 for (j = 0; j < 0x100; j++) {
305 wrData = (j << 16) | j;
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (rdData != wrData) {
309 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 310 "address test failed "
f1dc5600 311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 312 addr, wrData, rdData);
f1dc5600
S		 313 return false;
314 }
315 }
316 for (j = 0; j < 4; j++) {
317 wrData = patternData[j];
318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr);
320 if (wrData != rdData) {
321 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 322 "address test failed "
f1dc5600 323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 324 addr, wrData, rdData);
f1dc5600
S		 325 return false;
326 }
f078f209 327 }
f1dc5600 328 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 329 }
f1dc5600 330 udelay(100);
cbe61d8a 331
f078f209
LR		 332 return true;
333}
334
f1dc5600 335static const char *ath9k_hw_devname(u16 devid)
f078f209 336{
f1dc5600
S		 337 switch (devid) {
338 case AR5416_DEVID_PCI:
f1dc5600 339 return "Atheros 5416";
392dff83
BP		 340 case AR5416_DEVID_PCIE:
341 return "Atheros 5418";
f1dc5600
S		 342 case AR9160_DEVID_PCI:
343 return "Atheros 9160";
0c1aa495
GJ		 344 case AR5416_AR9100_DEVID:
345 return "Atheros 9100";
f1dc5600
S		 346 case AR9280_DEVID_PCI:
347 case AR9280_DEVID_PCIE:
348 return "Atheros 9280";
e7594072
SB		 349 case AR9285_DEVID_PCIE:
350 return "Atheros 9285";
f078f209
LR		 351 }
352
f1dc5600
S		 353 return NULL;
354}
f078f209 355
cbe61d8a 356static void ath9k_hw_set_defaults(struct ath_hw *ah)
f1dc5600
S		 357{
358 int i;
f078f209 359
2660b81a
S		 360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
366 ah->config.pcie_l1skp_enable = 0;
367 ah->config.pcie_clock_req = 0;
368 ah->config.pcie_power_reset = 0x100;
369 ah->config.pcie_restore = 0;
370 ah->config.pcie_waen = 0;
371 ah->config.analog_shiftreg = 1;
372 ah->config.ht_enable = 1;
373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
377 ah->config.enable_ani = 1;
378 ah->config.noise_immunity_level = 4;
379 ah->config.ofdm_weaksignal_det = 1;
380 ah->config.cck_weaksignal_thr = 0;
381 ah->config.spur_immunity_level = 2;
382 ah->config.firstep_level = 0;
383 ah->config.rssi_thr_high = 40;
384 ah->config.rssi_thr_low = 7;
385 ah->config.diversity_control = 0;
386 ah->config.antenna_switch_swap = 0;
f078f209 387
f1dc5600 388 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 389 ah->config.spurchans[i][0] = AR_NO_SPUR;
390 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 391 }
392
2660b81a 393 ah->config.intr_mitigation = 1;
f078f209
LR		 394}
395
cbe61d8a
S		 396static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
397 int *status)
f078f209 398{
cbe61d8a 399 struct ath_hw *ah;
f078f209 400
cbe61d8a
S		 401 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
402 if (ah == NULL) {
f078f209 403 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 404 "Cannot allocate memory for state block\n");
f078f209
LR		 405 *status = -ENOMEM;
406 return NULL;
407 }
408
f078f209 409 ah->ah_sc = sc;
d535a42a 410 ah->hw_version.magic = AR5416_MAGIC;
d6bad496 411 ah->regulatory.country_code = CTRY_DEFAULT;
d535a42a
S		 412 ah->hw_version.devid = devid;
413 ah->hw_version.subvendorid = 0;
f078f209
LR		 414
415 ah->ah_flags = 0;
416 if ((devid == AR5416_AR9100_DEVID))
d535a42a 417 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 418 if (!AR_SREV_9100(ah))
419 ah->ah_flags = AH_USE_EEPROM;
420
d6bad496
S		 421 ah->regulatory.power_limit = MAX_RATE_POWER;
422 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
2660b81a
S		 423 ah->atim_window = 0;
424 ah->diversity_control = ah->config.diversity_control;
425 ah->antenna_switch_swap =
426 ah->config.antenna_switch_swap;
427 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
428 ah->beacon_interval = 100;
429 ah->enable_32kHz_clock = DONT_USE_32KHZ;
430 ah->slottime = (u32) -1;
431 ah->acktimeout = (u32) -1;
432 ah->ctstimeout = (u32) -1;
433 ah->globaltxtimeout = (u32) -1;
434
435 ah->gbeacon_rate = 0;
f078f209 436
cbe61d8a 437 return ah;
f078f209
LR		 438}
439
cbe61d8a 440static int ath9k_hw_rfattach(struct ath_hw *ah)
f078f209 441{
f1dc5600
S		 442 bool rfStatus = false;
443 int ecode = 0;
f078f209 444
f1dc5600
S		 445 rfStatus = ath9k_hw_init_rf(ah, &ecode);
446 if (!rfStatus) {
447 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 448 "RF setup failed, status %u\n", ecode);
f1dc5600
S		 449 return ecode;
450 }
f078f209 451
f1dc5600 452 return 0;
f078f209
LR		 453}
454
cbe61d8a 455static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 456{
f1dc5600
S		 457 u32 val;
458
459 REG_WRITE(ah, AR_PHY(0), 0x00000007);
460
461 val = ath9k_hw_get_radiorev(ah);
462 switch (val & AR_RADIO_SREV_MAJOR) {
463 case 0:
464 val = AR_RAD5133_SREV_MAJOR;
465 break;
466 case AR_RAD5133_SREV_MAJOR:
467 case AR_RAD5122_SREV_MAJOR:
468 case AR_RAD2133_SREV_MAJOR:
469 case AR_RAD2122_SREV_MAJOR:
470 break;
f078f209 471 default:
f1dc5600 472 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 473 "5G Radio Chip Rev 0x%02X is not "
f1dc5600 474 "supported by this driver\n",
d535a42a 475 ah->hw_version.analog5GhzRev);
f1dc5600 476 return -EOPNOTSUPP;
f078f209 477 }
f078f209 478
d535a42a 479 ah->hw_version.analog5GhzRev = val;
f078f209 480
f1dc5600 481 return 0;
f078f209
LR		 482}
483
cbe61d8a 484static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209
LR		 485{
486 u32 sum;
487 int i;
488 u16 eeval;
f078f209
LR		 489
490 sum = 0;
491 for (i = 0; i < 3; i++) {
f74df6fb 492 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 493 sum += eeval;
ba52da58
S		 494 ah->macaddr[2 * i] = eeval >> 8;
495 ah->macaddr[2 * i + 1] = eeval & 0xff;
f078f209
LR		 496 }
497 if (sum == 0 || sum == 0xffff * 3) {
498 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 499 "mac address read failed: %pM\n",
ba52da58 500 ah->macaddr);
f078f209
LR		 501 return -EADDRNOTAVAIL;
502 }
503
504 return 0;
505}
506
cbe61d8a 507static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 508{
509 u32 rxgain_type;
9f804202 510
f74df6fb
S		 511 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
512 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 513
514 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 515 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 516 ar9280Modes_backoff_13db_rxgain_9280_2,
517 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
518 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 519 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 520 ar9280Modes_backoff_23db_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
522 else
2660b81a 523 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 524 ar9280Modes_original_rxgain_9280_2,
525 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 526 } else {
2660b81a 527 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 528 ar9280Modes_original_rxgain_9280_2,
529 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 530 }
9f804202
SB		 531}
532
cbe61d8a 533static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 534{
535 u32 txgain_type;
9f804202 536
f74df6fb
S		 537 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
538 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 539
540 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 541 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 542 ar9280Modes_high_power_tx_gain_9280_2,
543 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
544 else
2660b81a 545 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 546 ar9280Modes_original_tx_gain_9280_2,
547 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 548 } else {
2660b81a 549 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 550 ar9280Modes_original_tx_gain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 552 }
9f804202
SB		 553}
554
cbe61d8a 555static int ath9k_hw_post_attach(struct ath_hw *ah)
f078f209 556{
f1dc5600 557 int ecode;
f078f209 558
f1dc5600
S		 559 if (!ath9k_hw_chip_test(ah)) {
560 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 561 "hardware self-test failed\n");
f1dc5600 562 return -ENODEV;
f078f209 563 }
f078f209 564
f1dc5600
S		 565 ecode = ath9k_hw_rf_claim(ah);
566 if (ecode != 0)
f078f209 567 return ecode;
f078f209 568
f1dc5600
S		 569 ecode = ath9k_hw_eeprom_attach(ah);
570 if (ecode != 0)
571 return ecode;
572 ecode = ath9k_hw_rfattach(ah);
573 if (ecode != 0)
574 return ecode;
f078f209 575
f1dc5600
S		 576 if (!AR_SREV_9100(ah)) {
577 ath9k_hw_ani_setup(ah);
578 ath9k_hw_ani_attach(ah);
f078f209
LR		 579 }
580
f078f209
LR		 581 return 0;
582}
583
cbe61d8a
S		 584static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
585 int *status)
f078f209 586{
cbe61d8a 587 struct ath_hw *ah;
f1dc5600 588 int ecode;
f6688cd8 589 u32 i, j;
f078f209 590
cbe61d8a
S		 591 ah = ath9k_hw_newstate(devid, sc, status);
592 if (ah == NULL)
f1dc5600 593 return NULL;
f078f209 594
f1dc5600 595 ath9k_hw_set_defaults(ah);
f078f209 596
2660b81a
S		 597 if (ah->config.intr_mitigation != 0)
598 ah->intr_mitigation = true;
f078f209 599
f1dc5600 600 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
cbe61d8a 601 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
f1dc5600
S		 602 ecode = -EIO;
603 goto bad;
604 }
f078f209 605
f1dc5600 606 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
cbe61d8a 607 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
f1dc5600
S		 608 ecode = -EIO;
609 goto bad;
610 }
f078f209 611
2660b81a 612 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
d535a42a 613 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
2660b81a 614 ah->config.serialize_regmode =
f1dc5600 615 SER_REG_MODE_ON;
f078f209 616 } else {
2660b81a 617 ah->config.serialize_regmode =
f1dc5600 618 SER_REG_MODE_OFF;
f078f209
LR		 619 }
620 }
f078f209 621
cbe61d8a 622 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
2660b81a 623 ah->config.serialize_regmode);
f078f209 624
d535a42a
S		 625 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
626 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
627 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
e7594072 628 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
cbe61d8a 629 DPRINTF(sc, ATH_DBG_RESET,
04bd4638 630 "Mac Chip Rev 0x%02x.%x is not supported by "
d535a42a
S		 631 "this driver\n", ah->hw_version.macVersion,
632 ah->hw_version.macRev);
f1dc5600
S		 633 ecode = -EOPNOTSUPP;
634 goto bad;
635 }
f078f209 636
f1dc5600 637 if (AR_SREV_9100(ah)) {
2660b81a
S		 638 ah->iq_caldata.calData = &iq_cal_multi_sample;
639 ah->supp_cals = IQ_MISMATCH_CAL;
640 ah->is_pciexpress = false;
f1dc5600 641 }
d535a42a 642 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
f078f209 643
f1dc5600
S		 644 if (AR_SREV_9160_10_OR_LATER(ah)) {
645 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 646 ah->iq_caldata.calData = &iq_cal_single_sample;
647 ah->adcgain_caldata.calData =
f1dc5600 648 &adc_gain_cal_single_sample;
2660b81a 649 ah->adcdc_caldata.calData =
f1dc5600 650 &adc_dc_cal_single_sample;
2660b81a 651 ah->adcdc_calinitdata.calData =
f1dc5600
S		 652 &adc_init_dc_cal;
653 } else {
2660b81a
S		 654 ah->iq_caldata.calData = &iq_cal_multi_sample;
655 ah->adcgain_caldata.calData =
f1dc5600 656 &adc_gain_cal_multi_sample;
2660b81a 657 ah->adcdc_caldata.calData =
f1dc5600 658 &adc_dc_cal_multi_sample;
2660b81a 659 ah->adcdc_calinitdata.calData =
f1dc5600
S		 660 &adc_init_dc_cal;
661 }
2660b81a 662 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 663 }
f078f209 664
f1dc5600 665 if (AR_SREV_9160(ah)) {
2660b81a
S		 666 ah->config.enable_ani = 1;
667 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
f1dc5600
S		 668 ATH9K_ANI_FIRSTEP_LEVEL);
669 } else {
2660b81a 670 ah->ani_function = ATH9K_ANI_ALL;
f1dc5600 671 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 672 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
f1dc5600 673 }
f078f209 674 }
f078f209 675
cbe61d8a 676 DPRINTF(sc, ATH_DBG_RESET,
04bd4638 677 "This Mac Chip Rev 0x%02x.%x is \n",
d535a42a 678 ah->hw_version.macVersion, ah->hw_version.macRev);
f078f209 679
e7594072 680 if (AR_SREV_9285_12_OR_LATER(ah)) {
2660b81a 681 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 682 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 683 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 684 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
685
2660b81a
S		 686 if (ah->config.pcie_clock_req) {
687 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 688 ar9285PciePhy_clkreq_off_L1_9285_1_2,
689 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
690 } else {
2660b81a 691 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 692 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
693 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
694 2);
695 }
696 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 697 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 698 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 699 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 700 ARRAY_SIZE(ar9285Common_9285), 2);
701
2660b81a
S		 702 if (ah->config.pcie_clock_req) {
703 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 704 ar9285PciePhy_clkreq_off_L1_9285,
705 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
706 } else {
2660b81a 707 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 708 ar9285PciePhy_clkreq_always_on_L1_9285,
709 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
710 }
711 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 712 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 713 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 714 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 715 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 716
2660b81a
S		 717 if (ah->config.pcie_clock_req) {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 719 ar9280PciePhy_clkreq_off_L1_9280,
720 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
721 } else {
2660b81a 722 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 723 ar9280PciePhy_clkreq_always_on_L1_9280,
724 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
725 }
2660b81a 726 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 727 ar9280Modes_fast_clock_9280_2,
728 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
729 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 730 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 731 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 732 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 733 ARRAY_SIZE(ar9280Common_9280), 2);
734 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 735 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 736 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 737 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 738 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 739 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 740 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 741 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 742 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 743 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 744 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 745 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 746 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 747 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 748 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 749 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 750 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 751 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 752 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 753 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 754 ARRAY_SIZE(ar5416Bank7_9160), 2);
755 if (AR_SREV_9160_11(ah)) {
2660b81a 756 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 757 ar5416Addac_91601_1,
758 ARRAY_SIZE(ar5416Addac_91601_1), 2);
759 } else {
2660b81a 760 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 761 ARRAY_SIZE(ar5416Addac_9160), 2);
762 }
763 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 764 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 765 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 766 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 767 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 768 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 769 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 770 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 771 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 772 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 773 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 774 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 775 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 776 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 777 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 778 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 779 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 780 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 781 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 782 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 783 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 784 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 785 ARRAY_SIZE(ar5416Addac_9100), 2);
786 } else {
2660b81a 787 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 788 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 789 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 790 ARRAY_SIZE(ar5416Common), 2);
2660b81a 791 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 792 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 793 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 794 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 795 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 796 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 797 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 798 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 799 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 800 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 801 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 802 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 803 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 804 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 805 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 806 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 807 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 808 ARRAY_SIZE(ar5416Addac), 2);
f078f209 809 }
f078f209 810
2660b81a 811 if (ah->is_pciexpress)
f1dc5600
S		 812 ath9k_hw_configpcipowersave(ah, 0);
813 else
814 ath9k_hw_disablepcie(ah);
f078f209 815
f1dc5600
S		 816 ecode = ath9k_hw_post_attach(ah);
817 if (ecode != 0)
818 goto bad;
f078f209 819
9f804202 820 /* rxgain table */
e7594072 821 if (AR_SREV_9280_20(ah))
9f804202
SB		 822 ath9k_hw_init_rxgain_ini(ah);
823
824 /* txgain table */
e7594072 825 if (AR_SREV_9280_20(ah))
9f804202
SB		 826 ath9k_hw_init_txgain_ini(ah);
827
06d0f066
S		 828 if (!ath9k_hw_fill_cap_info(ah)) {
829 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
830 ecode = -EINVAL;
831 goto bad;
832 }
833
834 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
835 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
836
837 /* EEPROM Fixup */
2660b81a
S		 838 for (i = 0; i < ah->iniModes.ia_rows; i++) {
839 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 840
2660b81a
S		 841 for (j = 1; j < ah->iniModes.ia_columns; j++) {
842 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 843
2660b81a 844 INI_RA(&ah->iniModes, i, j) =
e7594072 845 ath9k_hw_ini_fixup(ah,
2660b81a 846 &ah->eeprom.def,
f1dc5600
S		 847 reg, val);
848 }
f078f209 849 }
f1dc5600 850 }
f6688cd8 851
f1dc5600
S		 852 ecode = ath9k_hw_init_macaddr(ah);
853 if (ecode != 0) {
cbe61d8a 854 DPRINTF(sc, ATH_DBG_RESET,
04bd4638 855 "failed initializing mac address\n");
f1dc5600 856 goto bad;
f078f209
LR		 857 }
858
f1dc5600 859 if (AR_SREV_9285(ah))
2660b81a 860 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 861 else
2660b81a 862 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 863
f1dc5600 864 ath9k_init_nfcal_hist_buffer(ah);
f078f209 865
f1dc5600
S		 866 return ah;
867bad:
cbe61d8a
S		 868 if (ah)
869 ath9k_hw_detach(ah);
f1dc5600
S		 870 if (status)
871 *status = ecode;
f078f209 872
f1dc5600 873 return NULL;
f078f209
LR		 874}
875
cbe61d8a 876static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 877 struct ath9k_channel *chan)
f078f209 878{
f1dc5600 879 u32 synthDelay;
f078f209 880
f1dc5600 881 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 882 if (IS_CHAN_B(chan))
f1dc5600
S		 883 synthDelay = (4 * synthDelay) / 22;
884 else
885 synthDelay /= 10;
f078f209 886
f1dc5600 887 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 888
f1dc5600 889 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 890}
891
cbe61d8a 892static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 893{
f1dc5600
S		 894 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
895 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 896
f1dc5600
S		 897 REG_WRITE(ah, AR_QOS_NO_ACK,
898 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
899 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
900 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
901
902 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
903 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
904 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
905 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
906 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 907}
908
cbe61d8a 909static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 910 struct ath9k_channel *chan)
f078f209 911{
f1dc5600 912 u32 pll;
f078f209 913
f1dc5600
S		 914 if (AR_SREV_9100(ah)) {
915 if (chan && IS_CHAN_5GHZ(chan))
916 pll = 0x1450;
f078f209 917 else
f1dc5600
S		 918 pll = 0x1458;
919 } else {
920 if (AR_SREV_9280_10_OR_LATER(ah)) {
921 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 922
f1dc5600
S		 923 if (chan && IS_CHAN_HALF_RATE(chan))
924 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
925 else if (chan && IS_CHAN_QUARTER_RATE(chan))
926 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 927
f1dc5600
S		 928 if (chan && IS_CHAN_5GHZ(chan)) {
929 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 930
f078f209 931
f1dc5600
S		 932 if (AR_SREV_9280_20(ah)) {
933 if (((chan->channel % 20) == 0)
934 || ((chan->channel % 10) == 0))
935 pll = 0x2850;
936 else
937 pll = 0x142c;
938 }
939 } else {
940 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
941 }
f078f209 942
f1dc5600 943 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 944
f1dc5600 945 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 946
f1dc5600
S		 947 if (chan && IS_CHAN_HALF_RATE(chan))
948 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
949 else if (chan && IS_CHAN_QUARTER_RATE(chan))
950 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 951
f1dc5600
S		 952 if (chan && IS_CHAN_5GHZ(chan))
953 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
954 else
955 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
956 } else {
957 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 958
f1dc5600
S		 959 if (chan && IS_CHAN_HALF_RATE(chan))
960 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
961 else if (chan && IS_CHAN_QUARTER_RATE(chan))
962 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 963
f1dc5600
S		 964 if (chan && IS_CHAN_5GHZ(chan))
965 pll |= SM(0xa, AR_RTC_PLL_DIV);
966 else
967 pll |= SM(0xb, AR_RTC_PLL_DIV);
968 }
969 }
d03a66c1 970 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 971
f1dc5600
S		 972 udelay(RTC_PLL_SETTLE_DELAY);
973
974 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 975}
976
cbe61d8a 977static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 978{
f078f209
LR		 979 int rx_chainmask, tx_chainmask;
980
2660b81a
S		 981 rx_chainmask = ah->rxchainmask;
982 tx_chainmask = ah->txchainmask;
f078f209
LR		 983
984 switch (rx_chainmask) {
985 case 0x5:
986 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
987 AR_PHY_SWAP_ALT_CHAIN);
988 case 0x3:
d535a42a 989 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
f078f209
LR		 990 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
991 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
992 break;
993 }
994 case 0x1:
995 case 0x2:
f078f209
LR		 996 case 0x7:
997 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
998 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
999 break;
1000 default:
1001 break;
1002 }
1003
1004 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1005 if (tx_chainmask == 0x5) {
1006 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1007 AR_PHY_SWAP_ALT_CHAIN);
1008 }
1009 if (AR_SREV_9100(ah))
1010 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1011 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1012}
1013
cbe61d8a 1014static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1015 enum nl80211_iftype opmode)
f078f209 1016{
2660b81a 1017 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1018 AR_IMR_TXURN |
1019 AR_IMR_RXERR |
1020 AR_IMR_RXORN |
1021 AR_IMR_BCNMISC;
f078f209 1022
2660b81a
S		 1023 if (ah->intr_mitigation)
1024 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1025 else
2660b81a 1026 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1027
2660b81a 1028 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1029
d97809db 1030 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1031 ah->mask_reg |= AR_IMR_MIB;
f078f209 1032
2660b81a 1033 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1034 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1035
f1dc5600
S		 1036 if (!AR_SREV_9100(ah)) {
1037 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1038 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1039 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1040 }
f078f209
LR		 1041}
1042
cbe61d8a 1043static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1044{
f078f209 1045 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
04bd4638 1046 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
2660b81a 1047 ah->acktimeout = (u32) -1;
f078f209
LR		 1048 return false;
1049 } else {
1050 REG_RMW_FIELD(ah, AR_TIME_OUT,
1051 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1052 ah->acktimeout = us;
f078f209
LR		 1053 return true;
1054 }
1055}
1056
cbe61d8a 1057static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1058{
f078f209 1059 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
04bd4638 1060 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
2660b81a 1061 ah->ctstimeout = (u32) -1;
f078f209
LR		 1062 return false;
1063 } else {
1064 REG_RMW_FIELD(ah, AR_TIME_OUT,
1065 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1066 ah->ctstimeout = us;
f078f209
LR		 1067 return true;
1068 }
1069}
f1dc5600 1070
cbe61d8a 1071static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1072{
f078f209
LR		 1073 if (tu > 0xFFFF) {
1074 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
04bd4638 1075 "bad global tx timeout %u\n", tu);
2660b81a 1076 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1077 return false;
1078 } else {
1079 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1080 ah->globaltxtimeout = tu;
f078f209
LR		 1081 return true;
1082 }
1083}
1084
cbe61d8a 1085static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1086{
2660b81a
S		 1087 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1088 ah->misc_mode);
f078f209 1089
2660b81a 1090 if (ah->misc_mode != 0)
f1dc5600 1091 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1092 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1093 if (ah->slottime != (u32) -1)
1094 ath9k_hw_setslottime(ah, ah->slottime);
1095 if (ah->acktimeout != (u32) -1)
1096 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1097 if (ah->ctstimeout != (u32) -1)
1098 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1099 if (ah->globaltxtimeout != (u32) -1)
1100 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1101}
1102
1103const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1104{
1105 return vendorid == ATHEROS_VENDOR_ID ?
1106 ath9k_hw_devname(devid) : NULL;
1107}
1108
cbe61d8a 1109void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600
S		 1110{
1111 if (!AR_SREV_9100(ah))
1112 ath9k_hw_ani_detach(ah);
1113
1114 ath9k_hw_rfdetach(ah);
1115 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1116 kfree(ah);
1117}
1118
cbe61d8a 1119struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
f1dc5600 1120{
cbe61d8a 1121 struct ath_hw *ah = NULL;
f1dc5600
S		 1122
1123 switch (devid) {
1124 case AR5416_DEVID_PCI:
1125 case AR5416_DEVID_PCIE:
0c1aa495 1126 case AR5416_AR9100_DEVID:
f1dc5600
S		 1127 case AR9160_DEVID_PCI:
1128 case AR9280_DEVID_PCI:
1129 case AR9280_DEVID_PCIE:
e7594072 1130 case AR9285_DEVID_PCIE:
cbe61d8a 1131 ah = ath9k_hw_do_attach(devid, sc, error);
f1dc5600
S		 1132 break;
1133 default:
f1dc5600
S		 1134 *error = -ENXIO;
1135 break;
f078f209 1136 }
f1dc5600
S		 1137
1138 return ah;
1139}
1140
1141/*******/
1142/* INI */
1143/*******/
1144
cbe61d8a 1145static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1146 struct ath9k_channel *chan)
1147{
8aa15e15
SB		 1148 /*
1149 * Set the RX_ABORT and RX_DIS and clear if off only after
1150 * RXE is set for MAC. This prevents frames with corrupted
1151 * descriptor status.
1152 */
1153 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1154
1155
f1dc5600
S		 1156 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1157 AR_SREV_9280_10_OR_LATER(ah))
1158 return;
1159
1160 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1161}
1162
cbe61d8a 1163static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1164 struct ar5416_eeprom_def *pEepData,
f1dc5600 1165 u32 reg, u32 value)
f078f209 1166{
f1dc5600 1167 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1168
d535a42a 1169 switch (ah->hw_version.devid) {
f1dc5600
S		 1170 case AR9280_DEVID_PCI:
1171 if (reg == 0x7894) {
1172 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1173 "ini VAL: %x EEPROM: %x\n", value,
1174 (pBase->version & 0xff));
1175
1176 if ((pBase->version & 0xff) > 0x0a) {
1177 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1178 "PWDCLKIND: %d\n",
1179 pBase->pwdclkind);
1180 value &= ~AR_AN_TOP2_PWDCLKIND;
1181 value |= AR_AN_TOP2_PWDCLKIND &
1182 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1183 } else {
1184 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1185 "PWDCLKIND Earlier Rev\n");
1186 }
1187
1188 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1189 "final ini VAL: %x\n", value);
1190 }
1191 break;
1192 }
1193
1194 return value;
f078f209
LR		 1195}
1196
cbe61d8a 1197static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1198 struct ar5416_eeprom_def *pEepData,
1199 u32 reg, u32 value)
1200{
2660b81a 1201 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1202 return value;
1203 else
1204 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1205}
1206
8bd1d07f
SB		 1207static void ath9k_olc_init(struct ath_hw *ah)
1208{
1209 u32 i;
1210
1211 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1212 ah->originalGain[i] =
1213 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1214 AR_PHY_TX_GAIN);
1215 ah->PDADCdelta = 0;
1216}
1217
cbe61d8a 1218static int ath9k_hw_process_ini(struct ath_hw *ah,
f1dc5600
S		 1219 struct ath9k_channel *chan,
1220 enum ath9k_ht_macmode macmode)
f078f209
LR		 1221{
1222 int i, regWrites = 0;
5f8e077c 1223 struct ieee80211_channel *channel = chan->chan;
f078f209
LR		 1224 u32 modesIndex, freqIndex;
1225 int status;
1226
1227 switch (chan->chanmode) {
1228 case CHANNEL_A:
1229 case CHANNEL_A_HT20:
1230 modesIndex = 1;
1231 freqIndex = 1;
1232 break;
1233 case CHANNEL_A_HT40PLUS:
1234 case CHANNEL_A_HT40MINUS:
1235 modesIndex = 2;
1236 freqIndex = 1;
1237 break;
1238 case CHANNEL_G:
1239 case CHANNEL_G_HT20:
1240 case CHANNEL_B:
1241 modesIndex = 4;
1242 freqIndex = 2;
1243 break;
1244 case CHANNEL_G_HT40PLUS:
1245 case CHANNEL_G_HT40MINUS:
1246 modesIndex = 3;
1247 freqIndex = 2;
1248 break;
1249
1250 default:
1251 return -EINVAL;
1252 }
1253
1254 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1255 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1256 ah->eep_ops->set_addac(ah, chan);
f078f209
LR		 1257
1258 if (AR_SREV_5416_V22_OR_LATER(ah)) {
2660b81a 1259 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1260 } else {
1261 struct ar5416IniArray temp;
1262 u32 addacSize =
2660b81a
S		 1263 sizeof(u32) * ah->iniAddac.ia_rows *
1264 ah->iniAddac.ia_columns;
f078f209 1265
2660b81a
S		 1266 memcpy(ah->addac5416_21,
1267 ah->iniAddac.ia_array, addacSize);
f078f209 1268
2660b81a 1269 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1270
2660b81a
S		 1271 temp.ia_array = ah->addac5416_21;
1272 temp.ia_columns = ah->iniAddac.ia_columns;
1273 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1274 REG_WRITE_ARRAY(&temp, 1, regWrites);
1275 }
f1dc5600 1276
f078f209
LR		 1277 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1278
2660b81a
S		 1279 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1280 u32 reg = INI_RA(&ah->iniModes, i, 0);
1281 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1282
f078f209
LR		 1283 REG_WRITE(ah, reg, val);
1284
1285 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1286 && ah->config.analog_shiftreg) {
f078f209
LR		 1287 udelay(100);
1288 }
1289
1290 DO_DELAY(regWrites);
1291 }
1292
e7594072 1293 if (AR_SREV_9280(ah))
2660b81a 1294 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1295
e7594072 1296 if (AR_SREV_9280(ah))
2660b81a 1297 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1298
2660b81a
S		 1299 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1300 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1301 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1302
1303 REG_WRITE(ah, reg, val);
1304
1305 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1306 && ah->config.analog_shiftreg) {
f078f209
LR		 1307 udelay(100);
1308 }
1309
1310 DO_DELAY(regWrites);
1311 }
1312
1313 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1314
1315 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1316 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1317 regWrites);
1318 }
1319
1320 ath9k_hw_override_ini(ah, chan);
1321 ath9k_hw_set_regs(ah, chan, macmode);
1322 ath9k_hw_init_chain_masks(ah);
1323
8bd1d07f
SB		 1324 if (OLC_FOR_AR9280_20_LATER)
1325 ath9k_olc_init(ah);
1326
f74df6fb
S		 1327 status = ah->eep_ops->set_txpower(ah, chan,
1328 ath9k_regd_get_ctl(ah, chan),
1329 channel->max_antenna_gain * 2,
1330 channel->max_power * 2,
1331 min((u32) MAX_RATE_POWER,
1332 (u32) ah->regulatory.power_limit));
f078f209
LR		 1333 if (status != 0) {
1334 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 1335 "error init'ing transmit power\n");
f078f209
LR		 1336 return -EIO;
1337 }
1338
1339 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1340 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
04bd4638 1341 "ar5416SetRfRegs failed\n");
f078f209
LR		 1342 return -EIO;
1343 }
1344
1345 return 0;
1346}
1347
f1dc5600
S		 1348/****************************************/
1349/* Reset and Channel Switching Routines */
1350/****************************************/
1351
cbe61d8a 1352static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1353{
f1dc5600
S		 1354 u32 rfMode = 0;
1355
1356 if (chan == NULL)
1357 return;
1358
1359 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1360 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1361
1362 if (!AR_SREV_9280_10_OR_LATER(ah))
1363 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1364 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1365
1366 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1367 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1368
1369 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1370}
1371
cbe61d8a 1372static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1373{
1374 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1375}
1376
cbe61d8a 1377static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1378{
1379 u32 regval;
1380
1381 regval = REG_READ(ah, AR_AHB_MODE);
1382 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1383
1384 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1385 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1386
2660b81a 1387 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600
S		 1388
1389 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1390 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1391
1392 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1393
1394 if (AR_SREV_9285(ah)) {
1395 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1396 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1397 } else {
1398 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1399 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1400 }
1401}
1402
cbe61d8a 1403static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1404{
1405 u32 val;
1406
1407 val = REG_READ(ah, AR_STA_ID1);
1408 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1409 switch (opmode) {
d97809db 1410 case NL80211_IFTYPE_AP:
f1dc5600
S		 1411 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1412 | AR_STA_ID1_KSRCH_MODE);
1413 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1414 break;
d97809db 1415 case NL80211_IFTYPE_ADHOC:
f1dc5600
S		 1416 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1417 | AR_STA_ID1_KSRCH_MODE);
1418 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1419 break;
d97809db
CM		 1420 case NL80211_IFTYPE_STATION:
1421 case NL80211_IFTYPE_MONITOR:
f1dc5600 1422 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1423 break;
f1dc5600
S		 1424 }
1425}
1426
cbe61d8a 1427static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1428 u32 coef_scaled,
1429 u32 *coef_mantissa,
1430 u32 *coef_exponent)
1431{
1432 u32 coef_exp, coef_man;
1433
1434 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1435 if ((coef_scaled >> coef_exp) & 0x1)
1436 break;
1437
1438 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1439
1440 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1441
1442 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1443 *coef_exponent = coef_exp - 16;
1444}
1445
cbe61d8a 1446static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1447 struct ath9k_channel *chan)
1448{
1449 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1450 u32 clockMhzScaled = 0x64000000;
1451 struct chan_centers centers;
1452
1453 if (IS_CHAN_HALF_RATE(chan))
1454 clockMhzScaled = clockMhzScaled >> 1;
1455 else if (IS_CHAN_QUARTER_RATE(chan))
1456 clockMhzScaled = clockMhzScaled >> 2;
1457
1458 ath9k_hw_get_channel_centers(ah, chan, &centers);
1459 coef_scaled = clockMhzScaled / centers.synth_center;
1460
1461 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1462 &ds_coef_exp);
1463
1464 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1465 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1466 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1467 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1468
1469 coef_scaled = (9 * coef_scaled) / 10;
1470
1471 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1472 &ds_coef_exp);
1473
1474 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1475 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1476 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1477 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1478}
1479
cbe61d8a 1480static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1481{
1482 u32 rst_flags;
1483 u32 tmpReg;
1484
70768496
S		 1485 if (AR_SREV_9100(ah)) {
1486 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1487 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1488 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1489 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1490 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1491 }
1492
f1dc5600
S		 1493 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1494 AR_RTC_FORCE_WAKE_ON_INT);
1495
1496 if (AR_SREV_9100(ah)) {
1497 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1498 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1499 } else {
1500 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1501 if (tmpReg &
1502 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1503 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1504 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1505 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1506 } else {
1507 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1508 }
1509
1510 rst_flags = AR_RTC_RC_MAC_WARM;
1511 if (type == ATH9K_RESET_COLD)
1512 rst_flags |= AR_RTC_RC_MAC_COLD;
1513 }
1514
d03a66c1 1515 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1516 udelay(50);
1517
d03a66c1 1518 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1519 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
f1dc5600 1520 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 1521 "RTC stuck in MAC reset\n");
f1dc5600
S		 1522 return false;
1523 }
1524
1525 if (!AR_SREV_9100(ah))
1526 REG_WRITE(ah, AR_RC, 0);
1527
1528 ath9k_hw_init_pll(ah, NULL);
1529
1530 if (AR_SREV_9100(ah))
1531 udelay(50);
1532
1533 return true;
1534}
1535
cbe61d8a 1536static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1537{
1538 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1539 AR_RTC_FORCE_WAKE_ON_INT);
1540
d03a66c1 1541 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1542 udelay(2);
d03a66c1 1543 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1544
1545 if (!ath9k_hw_wait(ah,
1546 AR_RTC_STATUS,
1547 AR_RTC_STATUS_M,
0caa7b14
S		 1548 AR_RTC_STATUS_ON,
1549 AH_WAIT_TIMEOUT)) {
04bd4638 1550 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1551 return false;
f078f209
LR		 1552 }
1553
f1dc5600
S		 1554 ath9k_hw_read_revisions(ah);
1555
1556 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1557}
1558
cbe61d8a 1559static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1560{
1561 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1562 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1563
1564 switch (type) {
1565 case ATH9K_RESET_POWER_ON:
1566 return ath9k_hw_set_reset_power_on(ah);
1567 break;
1568 case ATH9K_RESET_WARM:
1569 case ATH9K_RESET_COLD:
1570 return ath9k_hw_set_reset(ah, type);
1571 break;
1572 default:
1573 return false;
1574 }
f078f209
LR		 1575}
1576
cbe61d8a 1577static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 1578 enum ath9k_ht_macmode macmode)
f078f209 1579{
f1dc5600 1580 u32 phymode;
e7594072 1581 u32 enableDacFifo = 0;
f078f209 1582
e7594072
SB		 1583 if (AR_SREV_9285_10_OR_LATER(ah))
1584 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1585 AR_PHY_FC_ENABLE_DAC_FIFO);
1586
f1dc5600 1587 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1588 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1589
1590 if (IS_CHAN_HT40(chan)) {
1591 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1592
f1dc5600
S		 1593 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1594 (chan->chanmode == CHANNEL_G_HT40PLUS))
1595 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1596
2660b81a 1597 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
f1dc5600 1598 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1599 }
f1dc5600
S		 1600 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1601
1602 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1603
f1dc5600
S		 1604 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1605 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1606}
1607
cbe61d8a 1608static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1609 struct ath9k_channel *chan)
f078f209 1610{
8bd1d07f
SB		 1611 if (OLC_FOR_AR9280_20_LATER) {
1612 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1613 return false;
1614 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1615 return false;
f078f209 1616
f1dc5600
S		 1617 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1618 return false;
f078f209 1619
2660b81a 1620 ah->chip_fullsleep = false;
f1dc5600 1621 ath9k_hw_init_pll(ah, chan);
f1dc5600 1622 ath9k_hw_set_rfmode(ah, chan);
f078f209 1623
f1dc5600 1624 return true;
f078f209
LR		 1625}
1626
cbe61d8a 1627static bool ath9k_hw_channel_change(struct ath_hw *ah,
f1dc5600
S		 1628 struct ath9k_channel *chan,
1629 enum ath9k_ht_macmode macmode)
f078f209 1630{
5f8e077c 1631 struct ieee80211_channel *channel = chan->chan;
f078f209 1632 u32 synthDelay, qnum;
f078f209
LR		 1633
1634 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1635 if (ath9k_hw_numtxpending(ah, qnum)) {
1636 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
04bd4638 1637 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1638 return false;
1639 }
1640 }
1641
1642 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1643 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1644 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
04bd4638
S		 1645 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1646 "Could not kill baseband RX\n");
f078f209
LR		 1647 return false;
1648 }
1649
1650 ath9k_hw_set_regs(ah, chan, macmode);
1651
1652 if (AR_SREV_9280_10_OR_LATER(ah)) {
1653 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1654 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1655 "failed to set channel\n");
f078f209
LR		 1656 return false;
1657 }
1658 } else {
1659 if (!(ath9k_hw_set_channel(ah, chan))) {
1660 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
04bd4638 1661 "failed to set channel\n");
f078f209
LR		 1662 return false;
1663 }
1664 }
1665
f74df6fb
S		 1666 if (ah->eep_ops->set_txpower(ah, chan,
1667 ath9k_regd_get_ctl(ah, chan),
1668 channel->max_antenna_gain * 2,
1669 channel->max_power * 2,
1670 min((u32) MAX_RATE_POWER,
1671 (u32) ah->regulatory.power_limit)) != 0) {
f078f209 1672 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 1673 "error init'ing transmit power\n");
f078f209
LR		 1674 return false;
1675 }
1676
1677 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1678 if (IS_CHAN_B(chan))
f078f209
LR		 1679 synthDelay = (4 * synthDelay) / 22;
1680 else
1681 synthDelay /= 10;
1682
1683 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1684
1685 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1686
f1dc5600
S		 1687 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1688 ath9k_hw_set_delta_slope(ah, chan);
1689
1690 if (AR_SREV_9280_10_OR_LATER(ah))
1691 ath9k_hw_9280_spur_mitigate(ah, chan);
1692 else
1693 ath9k_hw_spur_mitigate(ah, chan);
1694
1695 if (!chan->oneTimeCalsDone)
1696 chan->oneTimeCalsDone = true;
1697
1698 return true;
1699}
1700
cbe61d8a 1701static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 1702{
1703 int bb_spur = AR_NO_SPUR;
1704 int freq;
1705 int bin, cur_bin;
1706 int bb_spur_off, spur_subchannel_sd;
1707 int spur_freq_sd;
1708 int spur_delta_phase;
1709 int denominator;
1710 int upper, lower, cur_vit_mask;
1711 int tmp, newVal;
1712 int i;
1713 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1714 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1715 };
1716 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1717 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1718 };
1719 int inc[4] = { 0, 100, 0, 0 };
1720 struct chan_centers centers;
1721
1722 int8_t mask_m[123];
1723 int8_t mask_p[123];
1724 int8_t mask_amt;
1725 int tmp_mask;
1726 int cur_bb_spur;
1727 bool is2GHz = IS_CHAN_2GHZ(chan);
1728
1729 memset(&mask_m, 0, sizeof(int8_t) * 123);
1730 memset(&mask_p, 0, sizeof(int8_t) * 123);
1731
1732 ath9k_hw_get_channel_centers(ah, chan, &centers);
1733 freq = centers.synth_center;
1734
2660b81a 1735 ah->config.spurmode = SPUR_ENABLE_EEPROM;
f1dc5600 1736 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1737 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1738
1739 if (is2GHz)
1740 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1741 else
1742 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1743
1744 if (AR_NO_SPUR == cur_bb_spur)
1745 break;
1746 cur_bb_spur = cur_bb_spur - freq;
1747
1748 if (IS_CHAN_HT40(chan)) {
1749 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1750 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1751 bb_spur = cur_bb_spur;
1752 break;
1753 }
1754 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1755 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1756 bb_spur = cur_bb_spur;
1757 break;
1758 }
1759 }
1760
1761 if (AR_NO_SPUR == bb_spur) {
1762 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1763 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1764 return;
1765 } else {
1766 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1767 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1768 }
1769
1770 bin = bb_spur * 320;
1771
1772 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1773
1774 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1775 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1776 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1777 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1778 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1779
1780 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1781 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1782 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1783 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1784 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1785 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1786
1787 if (IS_CHAN_HT40(chan)) {
1788 if (bb_spur < 0) {
1789 spur_subchannel_sd = 1;
1790 bb_spur_off = bb_spur + 10;
1791 } else {
1792 spur_subchannel_sd = 0;
1793 bb_spur_off = bb_spur - 10;
1794 }
1795 } else {
1796 spur_subchannel_sd = 0;
1797 bb_spur_off = bb_spur;
1798 }
1799
1800 if (IS_CHAN_HT40(chan))
1801 spur_delta_phase =
1802 ((bb_spur * 262144) /
1803 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1804 else
1805 spur_delta_phase =
1806 ((bb_spur * 524288) /
1807 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1808
1809 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1810 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1811
1812 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1813 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1814 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1815 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1816
1817 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1818 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1819
1820 cur_bin = -6000;
1821 upper = bin + 100;
1822 lower = bin - 100;
1823
1824 for (i = 0; i < 4; i++) {
1825 int pilot_mask = 0;
1826 int chan_mask = 0;
1827 int bp = 0;
1828 for (bp = 0; bp < 30; bp++) {
1829 if ((cur_bin > lower) && (cur_bin < upper)) {
1830 pilot_mask = pilot_mask | 0x1 << bp;
1831 chan_mask = chan_mask | 0x1 << bp;
1832 }
1833 cur_bin += 100;
1834 }
1835 cur_bin += inc[i];
1836 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1837 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1838 }
1839
1840 cur_vit_mask = 6100;
1841 upper = bin + 120;
1842 lower = bin - 120;
1843
1844 for (i = 0; i < 123; i++) {
1845 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1846
1847 /* workaround for gcc bug #37014 */
a085ff71 1848 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 1849
a085ff71 1850 if (tmp_v < 75)
f1dc5600
S		 1851 mask_amt = 1;
1852 else
1853 mask_amt = 0;
1854 if (cur_vit_mask < 0)
1855 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1856 else
1857 mask_p[cur_vit_mask / 100] = mask_amt;
1858 }
1859 cur_vit_mask -= 100;
1860 }
1861
1862 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1863 | (mask_m[48] << 26) | (mask_m[49] << 24)
1864 | (mask_m[50] << 22) | (mask_m[51] << 20)
1865 | (mask_m[52] << 18) | (mask_m[53] << 16)
1866 | (mask_m[54] << 14) | (mask_m[55] << 12)
1867 | (mask_m[56] << 10) | (mask_m[57] << 8)
1868 | (mask_m[58] << 6) | (mask_m[59] << 4)
1869 | (mask_m[60] << 2) | (mask_m[61] << 0);
1870 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1871 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1872
1873 tmp_mask = (mask_m[31] << 28)
1874 | (mask_m[32] << 26) | (mask_m[33] << 24)
1875 | (mask_m[34] << 22) | (mask_m[35] << 20)
1876 | (mask_m[36] << 18) | (mask_m[37] << 16)
1877 | (mask_m[48] << 14) | (mask_m[39] << 12)
1878 | (mask_m[40] << 10) | (mask_m[41] << 8)
1879 | (mask_m[42] << 6) | (mask_m[43] << 4)
1880 | (mask_m[44] << 2) | (mask_m[45] << 0);
1881 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1882 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1883
1884 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1885 | (mask_m[18] << 26) | (mask_m[18] << 24)
1886 | (mask_m[20] << 22) | (mask_m[20] << 20)
1887 | (mask_m[22] << 18) | (mask_m[22] << 16)
1888 | (mask_m[24] << 14) | (mask_m[24] << 12)
1889 | (mask_m[25] << 10) | (mask_m[26] << 8)
1890 | (mask_m[27] << 6) | (mask_m[28] << 4)
1891 | (mask_m[29] << 2) | (mask_m[30] << 0);
1892 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1893 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1894
1895 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1896 | (mask_m[2] << 26) | (mask_m[3] << 24)
1897 | (mask_m[4] << 22) | (mask_m[5] << 20)
1898 | (mask_m[6] << 18) | (mask_m[7] << 16)
1899 | (mask_m[8] << 14) | (mask_m[9] << 12)
1900 | (mask_m[10] << 10) | (mask_m[11] << 8)
1901 | (mask_m[12] << 6) | (mask_m[13] << 4)
1902 | (mask_m[14] << 2) | (mask_m[15] << 0);
1903 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1904 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1905
1906 tmp_mask = (mask_p[15] << 28)
1907 | (mask_p[14] << 26) | (mask_p[13] << 24)
1908 | (mask_p[12] << 22) | (mask_p[11] << 20)
1909 | (mask_p[10] << 18) | (mask_p[9] << 16)
1910 | (mask_p[8] << 14) | (mask_p[7] << 12)
1911 | (mask_p[6] << 10) | (mask_p[5] << 8)
1912 | (mask_p[4] << 6) | (mask_p[3] << 4)
1913 | (mask_p[2] << 2) | (mask_p[1] << 0);
1914 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1915 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 1916
f1dc5600
S		 1917 tmp_mask = (mask_p[30] << 28)
1918 | (mask_p[29] << 26) | (mask_p[28] << 24)
1919 | (mask_p[27] << 22) | (mask_p[26] << 20)
1920 | (mask_p[25] << 18) | (mask_p[24] << 16)
1921 | (mask_p[23] << 14) | (mask_p[22] << 12)
1922 | (mask_p[21] << 10) | (mask_p[20] << 8)
1923 | (mask_p[19] << 6) | (mask_p[18] << 4)
1924 | (mask_p[17] << 2) | (mask_p[16] << 0);
1925 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1926 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 1927
f1dc5600
S		 1928 tmp_mask = (mask_p[45] << 28)
1929 | (mask_p[44] << 26) | (mask_p[43] << 24)
1930 | (mask_p[42] << 22) | (mask_p[41] << 20)
1931 | (mask_p[40] << 18) | (mask_p[39] << 16)
1932 | (mask_p[38] << 14) | (mask_p[37] << 12)
1933 | (mask_p[36] << 10) | (mask_p[35] << 8)
1934 | (mask_p[34] << 6) | (mask_p[33] << 4)
1935 | (mask_p[32] << 2) | (mask_p[31] << 0);
1936 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1937 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 1938
f1dc5600
S		 1939 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1940 | (mask_p[59] << 26) | (mask_p[58] << 24)
1941 | (mask_p[57] << 22) | (mask_p[56] << 20)
1942 | (mask_p[55] << 18) | (mask_p[54] << 16)
1943 | (mask_p[53] << 14) | (mask_p[52] << 12)
1944 | (mask_p[51] << 10) | (mask_p[50] << 8)
1945 | (mask_p[49] << 6) | (mask_p[48] << 4)
1946 | (mask_p[47] << 2) | (mask_p[46] << 0);
1947 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1948 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 1949}
1950
cbe61d8a 1951static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1952{
f1dc5600
S		 1953 int bb_spur = AR_NO_SPUR;
1954 int bin, cur_bin;
1955 int spur_freq_sd;
1956 int spur_delta_phase;
1957 int denominator;
1958 int upper, lower, cur_vit_mask;
1959 int tmp, new;
1960 int i;
1961 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1962 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1963 };
1964 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1965 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1966 };
1967 int inc[4] = { 0, 100, 0, 0 };
f078f209 1968
f1dc5600
S		 1969 int8_t mask_m[123];
1970 int8_t mask_p[123];
1971 int8_t mask_amt;
1972 int tmp_mask;
1973 int cur_bb_spur;
1974 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 1975
f1dc5600
S		 1976 memset(&mask_m, 0, sizeof(int8_t) * 123);
1977 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 1978
f1dc5600 1979 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1980 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1981 if (AR_NO_SPUR == cur_bb_spur)
1982 break;
1983 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1984 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1985 bb_spur = cur_bb_spur;
1986 break;
1987 }
1988 }
f078f209 1989
f1dc5600
S		 1990 if (AR_NO_SPUR == bb_spur)
1991 return;
f078f209 1992
f1dc5600 1993 bin = bb_spur * 32;
f078f209 1994
f1dc5600
S		 1995 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1996 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1997 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1998 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1999 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2000
f1dc5600 2001 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2002
f1dc5600
S		 2003 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2004 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2005 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2006 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2007 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2008 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2009
f1dc5600
S		 2010 spur_delta_phase = ((bb_spur * 524288) / 100) &
2011 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2012
f1dc5600
S		 2013 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2014 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2015
f1dc5600
S		 2016 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2017 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2018 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2019 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2020
f1dc5600
S		 2021 cur_bin = -6000;
2022 upper = bin + 100;
2023 lower = bin - 100;
f078f209 2024
f1dc5600
S		 2025 for (i = 0; i < 4; i++) {
2026 int pilot_mask = 0;
2027 int chan_mask = 0;
2028 int bp = 0;
2029 for (bp = 0; bp < 30; bp++) {
2030 if ((cur_bin > lower) && (cur_bin < upper)) {
2031 pilot_mask = pilot_mask | 0x1 << bp;
2032 chan_mask = chan_mask | 0x1 << bp;
2033 }
2034 cur_bin += 100;
2035 }
2036 cur_bin += inc[i];
2037 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2038 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2039 }
f078f209 2040
f1dc5600
S		 2041 cur_vit_mask = 6100;
2042 upper = bin + 120;
2043 lower = bin - 120;
f078f209 2044
f1dc5600
S		 2045 for (i = 0; i < 123; i++) {
2046 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2047
f1dc5600 2048 /* workaround for gcc bug #37014 */
a085ff71 2049 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2050
a085ff71 2051 if (tmp_v < 75)
f1dc5600
S		 2052 mask_amt = 1;
2053 else
2054 mask_amt = 0;
2055 if (cur_vit_mask < 0)
2056 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2057 else
2058 mask_p[cur_vit_mask / 100] = mask_amt;
2059 }
2060 cur_vit_mask -= 100;
f078f209
LR		 2061 }
2062
f1dc5600
S		 2063 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2064 | (mask_m[48] << 26) | (mask_m[49] << 24)
2065 | (mask_m[50] << 22) | (mask_m[51] << 20)
2066 | (mask_m[52] << 18) | (mask_m[53] << 16)
2067 | (mask_m[54] << 14) | (mask_m[55] << 12)
2068 | (mask_m[56] << 10) | (mask_m[57] << 8)
2069 | (mask_m[58] << 6) | (mask_m[59] << 4)
2070 | (mask_m[60] << 2) | (mask_m[61] << 0);
2071 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2072 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2073
f1dc5600
S		 2074 tmp_mask = (mask_m[31] << 28)
2075 | (mask_m[32] << 26) | (mask_m[33] << 24)
2076 | (mask_m[34] << 22) | (mask_m[35] << 20)
2077 | (mask_m[36] << 18) | (mask_m[37] << 16)
2078 | (mask_m[48] << 14) | (mask_m[39] << 12)
2079 | (mask_m[40] << 10) | (mask_m[41] << 8)
2080 | (mask_m[42] << 6) | (mask_m[43] << 4)
2081 | (mask_m[44] << 2) | (mask_m[45] << 0);
2082 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2083 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2084
f1dc5600
S		 2085 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2086 | (mask_m[18] << 26) | (mask_m[18] << 24)
2087 | (mask_m[20] << 22) | (mask_m[20] << 20)
2088 | (mask_m[22] << 18) | (mask_m[22] << 16)
2089 | (mask_m[24] << 14) | (mask_m[24] << 12)
2090 | (mask_m[25] << 10) | (mask_m[26] << 8)
2091 | (mask_m[27] << 6) | (mask_m[28] << 4)
2092 | (mask_m[29] << 2) | (mask_m[30] << 0);
2093 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2094 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2095
f1dc5600
S		 2096 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2097 | (mask_m[2] << 26) | (mask_m[3] << 24)
2098 | (mask_m[4] << 22) | (mask_m[5] << 20)
2099 | (mask_m[6] << 18) | (mask_m[7] << 16)
2100 | (mask_m[8] << 14) | (mask_m[9] << 12)
2101 | (mask_m[10] << 10) | (mask_m[11] << 8)
2102 | (mask_m[12] << 6) | (mask_m[13] << 4)
2103 | (mask_m[14] << 2) | (mask_m[15] << 0);
2104 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2105 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2106
f1dc5600
S		 2107 tmp_mask = (mask_p[15] << 28)
2108 | (mask_p[14] << 26) | (mask_p[13] << 24)
2109 | (mask_p[12] << 22) | (mask_p[11] << 20)
2110 | (mask_p[10] << 18) | (mask_p[9] << 16)
2111 | (mask_p[8] << 14) | (mask_p[7] << 12)
2112 | (mask_p[6] << 10) | (mask_p[5] << 8)
2113 | (mask_p[4] << 6) | (mask_p[3] << 4)
2114 | (mask_p[2] << 2) | (mask_p[1] << 0);
2115 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2116 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2117
f1dc5600
S		 2118 tmp_mask = (mask_p[30] << 28)
2119 | (mask_p[29] << 26) | (mask_p[28] << 24)
2120 | (mask_p[27] << 22) | (mask_p[26] << 20)
2121 | (mask_p[25] << 18) | (mask_p[24] << 16)
2122 | (mask_p[23] << 14) | (mask_p[22] << 12)
2123 | (mask_p[21] << 10) | (mask_p[20] << 8)
2124 | (mask_p[19] << 6) | (mask_p[18] << 4)
2125 | (mask_p[17] << 2) | (mask_p[16] << 0);
2126 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2127 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2128
f1dc5600
S		 2129 tmp_mask = (mask_p[45] << 28)
2130 | (mask_p[44] << 26) | (mask_p[43] << 24)
2131 | (mask_p[42] << 22) | (mask_p[41] << 20)
2132 | (mask_p[40] << 18) | (mask_p[39] << 16)
2133 | (mask_p[38] << 14) | (mask_p[37] << 12)
2134 | (mask_p[36] << 10) | (mask_p[35] << 8)
2135 | (mask_p[34] << 6) | (mask_p[33] << 4)
2136 | (mask_p[32] << 2) | (mask_p[31] << 0);
2137 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2138 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2139
f1dc5600
S		 2140 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2141 | (mask_p[59] << 26) | (mask_p[58] << 24)
2142 | (mask_p[57] << 22) | (mask_p[56] << 20)
2143 | (mask_p[55] << 18) | (mask_p[54] << 16)
2144 | (mask_p[53] << 14) | (mask_p[52] << 12)
2145 | (mask_p[51] << 10) | (mask_p[50] << 8)
2146 | (mask_p[49] << 6) | (mask_p[48] << 4)
2147 | (mask_p[47] << 2) | (mask_p[46] << 0);
2148 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2149 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2150}
2151
cbe61d8a 2152int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 2153 bool bChannelChange)
f078f209 2154{
f078f209 2155 u32 saveLedState;
ae8d2858 2156 struct ath_softc *sc = ah->ah_sc;
2660b81a 2157 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 2158 u32 saveDefAntenna;
2159 u32 macStaId1;
ae8d2858 2160 int i, rx_chainmask, r;
f078f209 2161
2660b81a
S		 2162 ah->extprotspacing = sc->ht_extprotspacing;
2163 ah->txchainmask = sc->tx_chainmask;
2164 ah->rxchainmask = sc->rx_chainmask;
f078f209 2165
793c5929 2166 if (AR_SREV_9285(ah)) {
2660b81a
S		 2167 ah->txchainmask &= 0x1;
2168 ah->rxchainmask &= 0x1;
793c5929 2169 } else if (AR_SREV_9280(ah)) {
2660b81a
S		 2170 ah->txchainmask &= 0x3;
2171 ah->rxchainmask &= 0x3;
f078f209
LR		 2172 }
2173
ae8d2858
LR		 2174 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2175 return -EIO;
f078f209
LR		 2176
2177 if (curchan)
2178 ath9k_hw_getnf(ah, curchan);
2179
2180 if (bChannelChange &&
2660b81a
S		 2181 (ah->chip_fullsleep != true) &&
2182 (ah->curchan != NULL) &&
2183 (chan->channel != ah->curchan->channel) &&
f078f209 2184 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 2185 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
f078f209 2186 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2660b81a 2187 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
f078f209 2188
ae8d2858 2189 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2660b81a 2190 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 2191 ath9k_hw_start_nfcal(ah);
ae8d2858 2192 return 0;
f078f209
LR		 2193 }
2194 }
2195
2196 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2197 if (saveDefAntenna == 0)
2198 saveDefAntenna = 1;
2199
2200 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2201
2202 saveLedState = REG_READ(ah, AR_CFG_LED) &
2203 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2204 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2205
2206 ath9k_hw_mark_phy_inactive(ah);
2207
2208 if (!ath9k_hw_chip_reset(ah, chan)) {
04bd4638 2209 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
ae8d2858 2210 return -EINVAL;
f078f209
LR		 2211 }
2212
369391db
VT		 2213 if (AR_SREV_9280_10_OR_LATER(ah))
2214 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2215
ae8d2858
LR		 2216 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2217 if (r)
2218 return r;
f078f209 2219
0ced0e17
JM		 2220 /* Setup MFP options for CCMP */
2221 if (AR_SREV_9280_20_OR_LATER(ah)) {
2222 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2223 * frames when constructing CCMP AAD. */
2224 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2225 0xc7ff);
2226 ah->sw_mgmt_crypto = false;
2227 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2228 /* Disable hardware crypto for management frames */
2229 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2230 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2231 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2232 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2233 ah->sw_mgmt_crypto = true;
2234 } else
2235 ah->sw_mgmt_crypto = true;
2236
f078f209
LR		 2237 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2238 ath9k_hw_set_delta_slope(ah, chan);
2239
2240 if (AR_SREV_9280_10_OR_LATER(ah))
2241 ath9k_hw_9280_spur_mitigate(ah, chan);
2242 else
2243 ath9k_hw_spur_mitigate(ah, chan);
2244
f74df6fb 2245 if (!ah->eep_ops->set_board_values(ah, chan)) {
f078f209 2246 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
04bd4638 2247 "error setting board options\n");
ae8d2858 2248 return -EIO;
f078f209
LR		 2249 }
2250
2251 ath9k_hw_decrease_chain_power(ah, chan);
2252
ba52da58
S		 2253 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2254 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
f078f209
LR		 2255 | macStaId1
2256 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2257 | (ah->config.
60b67f51 2258 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2259 | ah->sta_id1_defaults);
2260 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2261
ba52da58
S		 2262 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2263 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 2264
2265 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2266
ba52da58
S		 2267 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2268 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2269 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 2270
2271 REG_WRITE(ah, AR_ISR, ~0);
2272
2273 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2274
2275 if (AR_SREV_9280_10_OR_LATER(ah)) {
ae8d2858
LR		 2276 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2277 return -EIO;
f078f209 2278 } else {
ae8d2858
LR		 2279 if (!(ath9k_hw_set_channel(ah, chan)))
2280 return -EIO;
f078f209
LR		 2281 }
2282
2283 for (i = 0; i < AR_NUM_DCU; i++)
2284 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2285
2660b81a
S		 2286 ah->intr_txqs = 0;
2287 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2288 ath9k_hw_resettxqueue(ah, i);
2289
2660b81a 2290 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2291 ath9k_hw_init_qos(ah);
2292
e97275cb 2293#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2294 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 2295 ath9k_enable_rfkill(ah);
2296#endif
f078f209
LR		 2297 ath9k_hw_init_user_settings(ah);
2298
f078f209
LR		 2299 REG_WRITE(ah, AR_STA_ID1,
2300 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2301
2302 ath9k_hw_set_dma(ah);
2303
2304 REG_WRITE(ah, AR_OBS, 8);
2305
2660b81a 2306 if (ah->intr_mitigation) {
f078f209
LR		 2307
2308 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2309 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2310 }
2311
2312 ath9k_hw_init_bb(ah, chan);
2313
ae8d2858
LR		 2314 if (!ath9k_hw_init_cal(ah, chan))
2315 return -EIO;;
f078f209 2316
2660b81a 2317 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2318 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2319 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2320 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2321 }
2322
2323 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2324
2325 if (AR_SREV_9100(ah)) {
2326 u32 mask;
2327 mask = REG_READ(ah, AR_CFG);
2328 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2329 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2330 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2331 } else {
2332 mask =
2333 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2334 REG_WRITE(ah, AR_CFG, mask);
2335 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2336 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2337 }
2338 } else {
2339#ifdef __BIG_ENDIAN
2340 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2341#endif
2342 }
2343
ae8d2858 2344 return 0;
f078f209
LR		 2345}
2346
f1dc5600
S		 2347/************************/
2348/* Key Cache Management */
2349/************************/
f078f209 2350
cbe61d8a 2351bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2352{
f1dc5600 2353 u32 keyType;
f078f209 2354
2660b81a 2355 if (entry >= ah->caps.keycache_size) {
f1dc5600 2356 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2357 "entry %u out of range\n", entry);
f078f209
LR		 2358 return false;
2359 }
2360
f1dc5600 2361 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2362
f1dc5600
S		 2363 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2364 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2365 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2366 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2367 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2368 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2369 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2370 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2371
f1dc5600
S		 2372 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2373 u16 micentry = entry + 64;
f078f209 2374
f1dc5600
S		 2375 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2376 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2377 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2378 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2379
f078f209
LR		 2380 }
2381
2660b81a 2382 if (ah->curchan == NULL)
f1dc5600 2383 return true;
f078f209
LR		 2384
2385 return true;
2386}
2387
cbe61d8a 2388bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2389{
f1dc5600 2390 u32 macHi, macLo;
f078f209 2391
2660b81a 2392 if (entry >= ah->caps.keycache_size) {
f1dc5600 2393 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2394 "entry %u out of range\n", entry);
f1dc5600 2395 return false;
f078f209
LR		 2396 }
2397
f1dc5600
S		 2398 if (mac != NULL) {
2399 macHi = (mac[5] << 8) | mac[4];
2400 macLo = (mac[3] << 24) |
2401 (mac[2] << 16) |
2402 (mac[1] << 8) |
2403 mac[0];
2404 macLo >>= 1;
2405 macLo |= (macHi & 1) << 31;
2406 macHi >>= 1;
f078f209 2407 } else {
f1dc5600 2408 macLo = macHi = 0;
f078f209 2409 }
f1dc5600
S		 2410 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2411 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2412
f1dc5600 2413 return true;
f078f209
LR		 2414}
2415
cbe61d8a 2416bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2417 const struct ath9k_keyval *k,
e0caf9ea 2418 const u8 *mac)
f078f209 2419{
2660b81a 2420 const struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 2421 u32 key0, key1, key2, key3, key4;
2422 u32 keyType;
f078f209 2423
f1dc5600
S		 2424 if (entry >= pCap->keycache_size) {
2425 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2426 "entry %u out of range\n", entry);
f1dc5600 2427 return false;
f078f209
LR		 2428 }
2429
f1dc5600
S		 2430 switch (k->kv_type) {
2431 case ATH9K_CIPHER_AES_OCB:
2432 keyType = AR_KEYTABLE_TYPE_AES;
2433 break;
2434 case ATH9K_CIPHER_AES_CCM:
2435 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2436 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2437 "AES-CCM not supported by mac rev 0x%x\n",
d535a42a 2438 ah->hw_version.macRev);
f1dc5600
S		 2439 return false;
2440 }
2441 keyType = AR_KEYTABLE_TYPE_CCM;
2442 break;
2443 case ATH9K_CIPHER_TKIP:
2444 keyType = AR_KEYTABLE_TYPE_TKIP;
2445 if (ATH9K_IS_MIC_ENABLED(ah)
2446 && entry + 64 >= pCap->keycache_size) {
2447 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2448 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2449 return false;
2450 }
2451 break;
2452 case ATH9K_CIPHER_WEP:
2453 if (k->kv_len < LEN_WEP40) {
2454 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2455 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2456 return false;
2457 }
2458 if (k->kv_len <= LEN_WEP40)
2459 keyType = AR_KEYTABLE_TYPE_40;
2460 else if (k->kv_len <= LEN_WEP104)
2461 keyType = AR_KEYTABLE_TYPE_104;
2462 else
2463 keyType = AR_KEYTABLE_TYPE_128;
2464 break;
2465 case ATH9K_CIPHER_CLR:
2466 keyType = AR_KEYTABLE_TYPE_CLR;
2467 break;
2468 default:
2469 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
04bd4638 2470 "cipher %u not supported\n", k->kv_type);
f1dc5600 2471 return false;
f078f209
LR		 2472 }
2473
e0caf9ea
JM		 2474 key0 = get_unaligned_le32(k->kv_val + 0);
2475 key1 = get_unaligned_le16(k->kv_val + 4);
2476 key2 = get_unaligned_le32(k->kv_val + 6);
2477 key3 = get_unaligned_le16(k->kv_val + 10);
2478 key4 = get_unaligned_le32(k->kv_val + 12);
f1dc5600
S		 2479 if (k->kv_len <= LEN_WEP104)
2480 key4 &= 0xff;
f078f209 2481
672903b3
JM		 2482 /*
2483 * Note: Key cache registers access special memory area that requires
2484 * two 32-bit writes to actually update the values in the internal
2485 * memory. Consequently, the exact order and pairs used here must be
2486 * maintained.
2487 */
2488
f1dc5600
S		 2489 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2490 u16 micentry = entry + 64;
f078f209 2491
672903b3
JM		 2492 /*
2493 * Write inverted key[47:0] first to avoid Michael MIC errors
2494 * on frames that could be sent or received at the same time.
2495 * The correct key will be written in the end once everything
2496 * else is ready.
2497 */
f1dc5600
S		 2498 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2499 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2500
2501 /* Write key[95:48] */
f1dc5600
S		 2502 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2503 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2504
2505 /* Write key[127:96] and key type */
f1dc5600
S		 2506 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2507 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2508
2509 /* Write MAC address for the entry */
f1dc5600 2510 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2511
2660b81a 2512 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2513 /*
2514 * TKIP uses two key cache entries:
2515 * Michael MIC TX/RX keys in the same key cache entry
2516 * (idx = main index + 64):
2517 * key0 [31:0] = RX key [31:0]
2518 * key1 [15:0] = TX key [31:16]
2519 * key1 [31:16] = reserved
2520 * key2 [31:0] = RX key [63:32]
2521 * key3 [15:0] = TX key [15:0]
2522 * key3 [31:16] = reserved
2523 * key4 [31:0] = TX key [63:32]
2524 */
f1dc5600 2525 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2526
f1dc5600
S		 2527 mic0 = get_unaligned_le32(k->kv_mic + 0);
2528 mic2 = get_unaligned_le32(k->kv_mic + 4);
2529 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2530 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2531 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2532
2533 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2534 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2535 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2536
2537 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2538 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2539 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2540
2541 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2542 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2543 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2544 AR_KEYTABLE_TYPE_CLR);
f078f209 2545
f1dc5600 2546 } else {
672903b3
JM		 2547 /*
2548 * TKIP uses four key cache entries (two for group
2549 * keys):
2550 * Michael MIC TX/RX keys are in different key cache
2551 * entries (idx = main index + 64 for TX and
2552 * main index + 32 + 96 for RX):
2553 * key0 [31:0] = TX/RX MIC key [31:0]
2554 * key1 [31:0] = reserved
2555 * key2 [31:0] = TX/RX MIC key [63:32]
2556 * key3 [31:0] = reserved
2557 * key4 [31:0] = reserved
2558 *
2559 * Upper layer code will call this function separately
2560 * for TX and RX keys when these registers offsets are
2561 * used.
2562 */
f1dc5600 2563 u32 mic0, mic2;
f078f209 2564
f1dc5600
S		 2565 mic0 = get_unaligned_le32(k->kv_mic + 0);
2566 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2567
2568 /* Write MIC key[31:0] */
f1dc5600
S		 2569 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2570 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2571
2572 /* Write MIC key[63:32] */
f1dc5600
S		 2573 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2574 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2575
2576 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2577 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2578 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2579 AR_KEYTABLE_TYPE_CLR);
2580 }
672903b3
JM		 2581
2582 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2583 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2584 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2585
2586 /*
2587 * Write the correct (un-inverted) key[47:0] last to enable
2588 * TKIP now that all other registers are set with correct
2589 * values.
2590 */
f1dc5600
S		 2591 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2592 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2593 } else {
672903b3 2594 /* Write key[47:0] */
f1dc5600
S		 2595 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2596 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2597
2598 /* Write key[95:48] */
f1dc5600
S		 2599 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2600 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2601
2602 /* Write key[127:96] and key type */
f1dc5600
S		 2603 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2604 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2605
672903b3 2606 /* Write MAC address for the entry */
f1dc5600
S		 2607 (void) ath9k_hw_keysetmac(ah, entry, mac);
2608 }
f078f209 2609
f078f209
LR		 2610 return true;
2611}
2612
cbe61d8a 2613bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2614{
2660b81a 2615 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2616 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2617 if (val & AR_KEYTABLE_VALID)
2618 return true;
2619 }
2620 return false;
f078f209
LR		 2621}
2622
f1dc5600
S		 2623/******************************/
2624/* Power Management (Chipset) */
2625/******************************/
2626
cbe61d8a 2627static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2628{
f1dc5600
S		 2629 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2630 if (setChip) {
2631 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2632 AR_RTC_FORCE_WAKE_EN);
2633 if (!AR_SREV_9100(ah))
2634 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2635
d03a66c1 2636 REG_CLR_BIT(ah, (AR_RTC_RESET),
f1dc5600
S		 2637 AR_RTC_RESET_EN);
2638 }
f078f209
LR		 2639}
2640
cbe61d8a 2641static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2642{
f1dc5600
S		 2643 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2644 if (setChip) {
2660b81a 2645 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2646
f1dc5600
S		 2647 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2648 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2649 AR_RTC_FORCE_WAKE_ON_INT);
2650 } else {
2651 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2652 AR_RTC_FORCE_WAKE_EN);
f078f209 2653 }
f078f209 2654 }
f078f209
LR		 2655}
2656
cbe61d8a 2657static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2658{
f1dc5600
S		 2659 u32 val;
2660 int i;
f078f209 2661
f1dc5600
S		 2662 if (setChip) {
2663 if ((REG_READ(ah, AR_RTC_STATUS) &
2664 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2665 if (ath9k_hw_set_reset_reg(ah,
2666 ATH9K_RESET_POWER_ON) != true) {
2667 return false;
2668 }
2669 }
2670 if (AR_SREV_9100(ah))
2671 REG_SET_BIT(ah, AR_RTC_RESET,
2672 AR_RTC_RESET_EN);
f078f209 2673
f1dc5600
S		 2674 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2675 AR_RTC_FORCE_WAKE_EN);
2676 udelay(50);
f078f209 2677
f1dc5600
S		 2678 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2679 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2680 if (val == AR_RTC_STATUS_ON)
2681 break;
2682 udelay(50);
2683 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2684 AR_RTC_FORCE_WAKE_EN);
f078f209 2685 }
f1dc5600
S		 2686 if (i == 0) {
2687 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2688 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2689 return false;
f078f209 2690 }
f078f209
LR		 2691 }
2692
f1dc5600 2693 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2694
f1dc5600 2695 return true;
f078f209
LR		 2696}
2697
cbe61d8a 2698bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2699{
cbe61d8a 2700 int status = true, setChip = true;
f1dc5600
S		 2701 static const char *modes[] = {
2702 "AWAKE",
2703 "FULL-SLEEP",
2704 "NETWORK SLEEP",
2705 "UNDEFINED"
2706 };
f1dc5600 2707
04bd4638 2708 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2660b81a 2709 modes[ah->power_mode], modes[mode],
f1dc5600
S		 2710 setChip ? "set chip " : "");
2711
2712 switch (mode) {
2713 case ATH9K_PM_AWAKE:
2714 status = ath9k_hw_set_power_awake(ah, setChip);
2715 break;
2716 case ATH9K_PM_FULL_SLEEP:
2717 ath9k_set_power_sleep(ah, setChip);
2660b81a 2718 ah->chip_fullsleep = true;
f1dc5600
S		 2719 break;
2720 case ATH9K_PM_NETWORK_SLEEP:
2721 ath9k_set_power_network_sleep(ah, setChip);
2722 break;
f078f209 2723 default:
f1dc5600 2724 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
04bd4638 2725 "Unknown power mode %u\n", mode);
f078f209
LR		 2726 return false;
2727 }
2660b81a 2728 ah->power_mode = mode;
f1dc5600
S		 2729
2730 return status;
f078f209
LR		 2731}
2732
24c1a280
LR		 2733/*
2734 * Helper for ASPM support.
2735 *
2736 * Disable PLL when in L0s as well as receiver clock when in L1.
2737 * This power saving option must be enabled through the SerDes.
2738 *
2739 * Programming the SerDes must go through the same 288 bit serial shift
2740 * register as the other analog registers. Hence the 9 writes.
2741 */
cbe61d8a 2742void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
f078f209 2743{
f1dc5600 2744 u8 i;
f078f209 2745
2660b81a 2746 if (ah->is_pciexpress != true)
f1dc5600 2747 return;
f078f209 2748
24c1a280 2749 /* Do not touch SerDes registers */
2660b81a 2750 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 2751 return;
2752
24c1a280 2753 /* Nothing to do on restore for 11N */
f1dc5600
S		 2754 if (restore)
2755 return;
2756
2757 if (AR_SREV_9280_20_OR_LATER(ah)) {
24c1a280
LR		 2758 /*
2759 * AR9280 2.0 or later chips use SerDes values from the
2760 * initvals.h initialized depending on chipset during
2761 * ath9k_hw_do_attach()
2762 */
2660b81a
S		 2763 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2764 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2765 INI_RA(&ah->iniPcieSerdes, i, 1));
f078f209 2766 }
f1dc5600 2767 } else if (AR_SREV_9280(ah) &&
d535a42a 2768 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
f1dc5600
S		 2769 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2770 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2771
24c1a280 2772 /* RX shut off when elecidle is asserted */
f1dc5600
S		 2773 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2774 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2775 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2776
24c1a280 2777 /* Shut off CLKREQ active in L1 */
2660b81a 2778 if (ah->config.pcie_clock_req)
f1dc5600
S		 2779 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2780 else
2781 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2782
2783 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2784 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2785 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2786
24c1a280 2787 /* Load the new settings */
f1dc5600
S		 2788 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2789
f1dc5600
S		 2790 } else {
2791 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2792 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
24c1a280
LR		 2793
2794 /* RX shut off when elecidle is asserted */
f1dc5600
S		 2795 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2796 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2797 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
24c1a280
LR		 2798
2799 /*
2800 * Ignore ah->ah_config.pcie_clock_req setting for
2801 * pre-AR9280 11n
2802 */
f1dc5600 2803 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 2804
f1dc5600
S		 2805 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2806 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2807 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280
LR		 2808
2809 /* Load the new settings */
f1dc5600 2810 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 2811 }
2812
6d08b9b9
LR		 2813 udelay(1000);
2814
24c1a280 2815 /* set bit 19 to allow forcing of pcie core into L1 state */
f1dc5600
S		 2816 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2817
24c1a280 2818 /* Several PCIe massages to ensure proper behaviour */
2660b81a
S		 2819 if (ah->config.pcie_waen) {
2820 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
f1dc5600 2821 } else {
e7594072
SB		 2822 if (AR_SREV_9285(ah))
2823 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
24c1a280
LR		 2824 /*
2825 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2826 * otherwise card may disappear.
2827 */
e7594072
SB		 2828 else if (AR_SREV_9280(ah))
2829 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
f1dc5600 2830 else
e7594072 2831 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
f1dc5600 2832 }
f078f209
LR		 2833}
2834
f1dc5600
S		 2835/**********************/
2836/* Interrupt Handling */
2837/**********************/
2838
cbe61d8a 2839bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 2840{
2841 u32 host_isr;
2842
2843 if (AR_SREV_9100(ah))
2844 return true;
2845
2846 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2847 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2848 return true;
2849
2850 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2851 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2852 && (host_isr != AR_INTR_SPURIOUS))
2853 return true;
2854
2855 return false;
2856}
2857
cbe61d8a 2858bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 2859{
2860 u32 isr = 0;
2861 u32 mask2 = 0;
2660b81a 2862 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 2863 u32 sync_cause = 0;
2864 bool fatal_int = false;
2865
2866 if (!AR_SREV_9100(ah)) {
2867 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2868 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2869 == AR_RTC_STATUS_ON) {
2870 isr = REG_READ(ah, AR_ISR);
2871 }
2872 }
2873
f1dc5600
S		 2874 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2875 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 2876
2877 *masked = 0;
2878
2879 if (!isr && !sync_cause)
2880 return false;
2881 } else {
2882 *masked = 0;
2883 isr = REG_READ(ah, AR_ISR);
2884 }
2885
2886 if (isr) {
f078f209
LR		 2887 if (isr & AR_ISR_BCNMISC) {
2888 u32 isr2;
2889 isr2 = REG_READ(ah, AR_ISR_S2);
2890 if (isr2 & AR_ISR_S2_TIM)
2891 mask2 |= ATH9K_INT_TIM;
2892 if (isr2 & AR_ISR_S2_DTIM)
2893 mask2 |= ATH9K_INT_DTIM;
2894 if (isr2 & AR_ISR_S2_DTIMSYNC)
2895 mask2 |= ATH9K_INT_DTIMSYNC;
2896 if (isr2 & (AR_ISR_S2_CABEND))
2897 mask2 |= ATH9K_INT_CABEND;
2898 if (isr2 & AR_ISR_S2_GTT)
2899 mask2 |= ATH9K_INT_GTT;
2900 if (isr2 & AR_ISR_S2_CST)
2901 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 2902 if (isr2 & AR_ISR_S2_TSFOOR)
2903 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 2904 }
2905
2906 isr = REG_READ(ah, AR_ISR_RAC);
2907 if (isr == 0xffffffff) {
2908 *masked = 0;
2909 return false;
2910 }
2911
2912 *masked = isr & ATH9K_INT_COMMON;
2913
2660b81a 2914 if (ah->intr_mitigation) {
f078f209
LR		 2915 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2916 *masked |= ATH9K_INT_RX;
2917 }
2918
2919 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2920 *masked |= ATH9K_INT_RX;
2921 if (isr &
2922 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2923 AR_ISR_TXEOL)) {
2924 u32 s0_s, s1_s;
2925
2926 *masked |= ATH9K_INT_TX;
2927
2928 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 2929 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2930 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 2931
2932 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 2933 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2934 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 2935 }
2936
2937 if (isr & AR_ISR_RXORN) {
2938 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2939 "receive FIFO overrun interrupt\n");
f078f209
LR		 2940 }
2941
2942 if (!AR_SREV_9100(ah)) {
60b67f51 2943 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2944 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2945 if (isr5 & AR_ISR_S5_TIM_TIMER)
2946 *masked |= ATH9K_INT_TIM_TIMER;
2947 }
2948 }
2949
2950 *masked |= mask2;
2951 }
f1dc5600 2952
f078f209
LR		 2953 if (AR_SREV_9100(ah))
2954 return true;
f1dc5600 2955
f078f209
LR		 2956 if (sync_cause) {
2957 fatal_int =
2958 (sync_cause &
2959 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2960 ? true : false;
2961
2962 if (fatal_int) {
2963 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2964 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2965 "received PCI FATAL interrupt\n");
f078f209
LR		 2966 }
2967 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2968 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2969 "received PCI PERR interrupt\n");
f078f209
LR		 2970 }
2971 }
2972 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2973 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2974 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2975 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2976 REG_WRITE(ah, AR_RC, 0);
2977 *masked |= ATH9K_INT_FATAL;
2978 }
2979 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2980 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 2981 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2982 }
2983
2984 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2985 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2986 }
f1dc5600 2987
f078f209
LR		 2988 return true;
2989}
2990
cbe61d8a 2991enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
f078f209 2992{
2660b81a 2993 return ah->mask_reg;
f078f209
LR		 2994}
2995
cbe61d8a 2996enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 2997{
2660b81a 2998 u32 omask = ah->mask_reg;
f078f209 2999 u32 mask, mask2;
2660b81a 3000 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 3001
04bd4638 3002 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 3003
3004 if (omask & ATH9K_INT_GLOBAL) {
04bd4638 3005 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 3006 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3007 (void) REG_READ(ah, AR_IER);
3008 if (!AR_SREV_9100(ah)) {
3009 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3010 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3011
3012 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3013 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3014 }
3015 }
3016
3017 mask = ints & ATH9K_INT_COMMON;
3018 mask2 = 0;
3019
3020 if (ints & ATH9K_INT_TX) {
2660b81a 3021 if (ah->txok_interrupt_mask)
f078f209 3022 mask |= AR_IMR_TXOK;
2660b81a 3023 if (ah->txdesc_interrupt_mask)
f078f209 3024 mask |= AR_IMR_TXDESC;
2660b81a 3025 if (ah->txerr_interrupt_mask)
f078f209 3026 mask |= AR_IMR_TXERR;
2660b81a 3027 if (ah->txeol_interrupt_mask)
f078f209
LR		 3028 mask |= AR_IMR_TXEOL;
3029 }
3030 if (ints & ATH9K_INT_RX) {
3031 mask |= AR_IMR_RXERR;
2660b81a 3032 if (ah->intr_mitigation)
f078f209
LR		 3033 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3034 else
3035 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 3036 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 3037 mask |= AR_IMR_GENTMR;
3038 }
3039
3040 if (ints & (ATH9K_INT_BMISC)) {
3041 mask |= AR_IMR_BCNMISC;
3042 if (ints & ATH9K_INT_TIM)
3043 mask2 |= AR_IMR_S2_TIM;
3044 if (ints & ATH9K_INT_DTIM)
3045 mask2 |= AR_IMR_S2_DTIM;
3046 if (ints & ATH9K_INT_DTIMSYNC)
3047 mask2 |= AR_IMR_S2_DTIMSYNC;
3048 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 3049 mask2 |= AR_IMR_S2_CABEND;
3050 if (ints & ATH9K_INT_TSFOOR)
3051 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 3052 }
3053
3054 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3055 mask |= AR_IMR_BCNMISC;
3056 if (ints & ATH9K_INT_GTT)
3057 mask2 |= AR_IMR_S2_GTT;
3058 if (ints & ATH9K_INT_CST)
3059 mask2 |= AR_IMR_S2_CST;
3060 }
3061
04bd4638 3062 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3063 REG_WRITE(ah, AR_IMR, mask);
3064 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3065 AR_IMR_S2_DTIM |
3066 AR_IMR_S2_DTIMSYNC |
3067 AR_IMR_S2_CABEND |
3068 AR_IMR_S2_CABTO |
3069 AR_IMR_S2_TSFOOR |
3070 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3071 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 3072 ah->mask_reg = ints;
f078f209 3073
60b67f51 3074 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3075 if (ints & ATH9K_INT_TIM_TIMER)
3076 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3077 else
3078 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3079 }
3080
3081 if (ints & ATH9K_INT_GLOBAL) {
04bd4638 3082 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3083 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3084 if (!AR_SREV_9100(ah)) {
3085 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3086 AR_INTR_MAC_IRQ);
3087 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3088
3089
3090 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3091 AR_INTR_SYNC_DEFAULT);
3092 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3093 AR_INTR_SYNC_DEFAULT);
3094 }
3095 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3096 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3097 }
3098
3099 return omask;
3100}
3101
f1dc5600
S		 3102/*******************/
3103/* Beacon Handling */
3104/*******************/
3105
cbe61d8a 3106void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 3107{
f078f209
LR		 3108 int flags = 0;
3109
2660b81a 3110 ah->beacon_interval = beacon_period;
f078f209 3111
2660b81a 3112 switch (ah->opmode) {
d97809db
CM		 3113 case NL80211_IFTYPE_STATION:
3114 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3115 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3116 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3117 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3118 flags |= AR_TBTT_TIMER_EN;
3119 break;
d97809db 3120 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 3121 REG_SET_BIT(ah, AR_TXCFG,
3122 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3123 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3124 TU_TO_USEC(next_beacon +
2660b81a
S		 3125 (ah->atim_window ? ah->
3126 atim_window : 1)));
f078f209 3127 flags |= AR_NDP_TIMER_EN;
d97809db 3128 case NL80211_IFTYPE_AP:
f078f209
LR		 3129 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3130 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3131 TU_TO_USEC(next_beacon -
2660b81a 3132 ah->config.
60b67f51 3133 dma_beacon_response_time));
f078f209
LR		 3134 REG_WRITE(ah, AR_NEXT_SWBA,
3135 TU_TO_USEC(next_beacon -
2660b81a 3136 ah->config.
60b67f51 3137 sw_beacon_response_time));
f078f209
LR		 3138 flags |=
3139 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3140 break;
d97809db
CM		 3141 default:
3142 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3143 "%s: unsupported opmode: %d\n",
2660b81a 3144 __func__, ah->opmode);
d97809db
CM		 3145 return;
3146 break;
f078f209
LR		 3147 }
3148
3149 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3150 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3151 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3152 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3153
3154 beacon_period &= ~ATH9K_BEACON_ENA;
3155 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3156 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3157 ath9k_hw_reset_tsf(ah);
3158 }
3159
3160 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3161}
3162
cbe61d8a 3163void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3164 const struct ath9k_beacon_state *bs)
f078f209
LR		 3165{
3166 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3167 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3168
3169 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3170
3171 REG_WRITE(ah, AR_BEACON_PERIOD,
3172 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3173 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3174 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3175
3176 REG_RMW_FIELD(ah, AR_RSSI_THR,
3177 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3178
3179 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3180
3181 if (bs->bs_sleepduration > beaconintval)
3182 beaconintval = bs->bs_sleepduration;
3183
3184 dtimperiod = bs->bs_dtimperiod;
3185 if (bs->bs_sleepduration > dtimperiod)
3186 dtimperiod = bs->bs_sleepduration;
3187
3188 if (beaconintval == dtimperiod)
3189 nextTbtt = bs->bs_nextdtim;
3190 else
3191 nextTbtt = bs->bs_nexttbtt;
3192
04bd4638
S		 3193 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3194 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3195 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3196 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3197
f1dc5600
S		 3198 REG_WRITE(ah, AR_NEXT_DTIM,
3199 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3200 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3201
f1dc5600
S		 3202 REG_WRITE(ah, AR_SLEEP1,
3203 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3204 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3205
f1dc5600
S		 3206 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3207 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3208 else
3209 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3210
f1dc5600
S		 3211 REG_WRITE(ah, AR_SLEEP2,
3212 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3213
f1dc5600
S		 3214 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3215 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3216
f1dc5600
S		 3217 REG_SET_BIT(ah, AR_TIMER_MODE,
3218 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3219 AR_DTIM_TIMER_EN);
f078f209 3220
4af9cf4f
S		 3221 /* TSF Out of Range Threshold */
3222 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209
LR		 3223}
3224
f1dc5600
S		 3225/*******************/
3226/* HW Capabilities */
3227/*******************/
3228
cbe61d8a 3229bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3230{
2660b81a 3231 struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600 3232 u16 capField = 0, eeval;
f078f209 3233
f74df6fb 3234 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
d6bad496 3235 ah->regulatory.current_rd = eeval;
f078f209 3236
f74df6fb 3237 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3238 if (AR_SREV_9285_10_OR_LATER(ah))
3239 eeval |= AR9285_RDEXT_DEFAULT;
d6bad496 3240 ah->regulatory.current_rd_ext = eeval;
f078f209 3241
f74df6fb 3242 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3243
2660b81a 3244 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3245 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
d6bad496
S		 3246 if (ah->regulatory.current_rd == 0x64 ||
3247 ah->regulatory.current_rd == 0x65)
3248 ah->regulatory.current_rd += 5;
3249 else if (ah->regulatory.current_rd == 0x41)
3250 ah->regulatory.current_rd = 0x43;
f1dc5600 3251 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
d6bad496 3252 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
f1dc5600 3253 }
f078f209 3254
f74df6fb 3255 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3256 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3257
f1dc5600
S		 3258 if (eeval & AR5416_OPFLAGS_11A) {
3259 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3260 if (ah->config.ht_enable) {
f1dc5600
S		 3261 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3262 set_bit(ATH9K_MODE_11NA_HT20,
3263 pCap->wireless_modes);
3264 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3265 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3266 pCap->wireless_modes);
3267 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3268 pCap->wireless_modes);
3269 }
f078f209 3270 }
f078f209
LR		 3271 }
3272
f1dc5600
S		 3273 if (eeval & AR5416_OPFLAGS_11G) {
3274 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3275 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3276 if (ah->config.ht_enable) {
f1dc5600
S		 3277 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3278 set_bit(ATH9K_MODE_11NG_HT20,
3279 pCap->wireless_modes);
3280 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3281 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3282 pCap->wireless_modes);
3283 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3284 pCap->wireless_modes);
3285 }
3286 }
f078f209 3287 }
f1dc5600 3288
f74df6fb 3289 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
8147f5de
S		 3290 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3291 !(eeval & AR5416_OPFLAGS_11A))
3292 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3293 else
3294 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3295
d535a42a 3296 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3297 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3298
f1dc5600
S		 3299 pCap->low_2ghz_chan = 2312;
3300 pCap->high_2ghz_chan = 2732;
f078f209 3301
f1dc5600
S		 3302 pCap->low_5ghz_chan = 4920;
3303 pCap->high_5ghz_chan = 6100;
f078f209 3304
f1dc5600
S		 3305 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3306 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3307 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3308
f1dc5600
S		 3309 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3310 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3311 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3312
f1dc5600 3313 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
f078f209 3314
2660b81a 3315 if (ah->config.ht_enable)
f1dc5600
S		 3316 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3317 else
3318 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3319
f1dc5600
S		 3320 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3321 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3322 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3323 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3324
f1dc5600
S		 3325 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3326 pCap->total_queues =
3327 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3328 else
3329 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3330
f1dc5600
S		 3331 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3332 pCap->keycache_size =
3333 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3334 else
3335 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3336
f1dc5600
S		 3337 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3338 pCap->num_mr_retries = 4;
3339 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3340
cb33c412
SB		 3341 if (AR_SREV_9285_10_OR_LATER(ah))
3342 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3343 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3344 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3345 else
3346 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3347
f1dc5600
S		 3348 if (AR_SREV_9280_10_OR_LATER(ah)) {
3349 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3350 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3351 } else {
3352 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3353 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
f078f209
LR		 3354 }
3355
f1dc5600
S		 3356 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3357 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3358 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3359 } else {
3360 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3361 }
3362
f1dc5600
S		 3363 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3364
e97275cb 3365#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3366 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3367 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3368 ah->rfkill_gpio =
3369 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3370 ah->rfkill_polarity =
3371 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3372
3373 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3374 }
f1dc5600 3375#endif
f078f209 3376
d535a42a
S		 3377 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3378 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3379 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3380 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3381 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
f1dc5600 3382 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3383 else
f1dc5600 3384 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3385
e7594072 3386 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3387 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3388 else
3389 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3390
d6bad496 3391 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3392 pCap->reg_cap =
3393 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3394 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3395 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3396 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3397 } else {
f1dc5600
S		 3398 pCap->reg_cap =
3399 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3400 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3401 }
f078f209 3402
f1dc5600
S		 3403 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3404
3405 pCap->num_antcfg_5ghz =
f74df6fb 3406 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3407 pCap->num_antcfg_2ghz =
f74df6fb 3408 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3409
138ab2e4 3410 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
c97c92d9 3411 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
2660b81a
S		 3412 ah->btactive_gpio = 6;
3413 ah->wlanactive_gpio = 5;
c97c92d9
VT		 3414 }
3415
f1dc5600 3416 return true;
f078f209
LR		 3417}
3418
cbe61d8a 3419bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3420 u32 capability, u32 *result)
f078f209 3421{
f1dc5600
S		 3422 switch (type) {
3423 case ATH9K_CAP_CIPHER:
3424 switch (capability) {
3425 case ATH9K_CIPHER_AES_CCM:
3426 case ATH9K_CIPHER_AES_OCB:
3427 case ATH9K_CIPHER_TKIP:
3428 case ATH9K_CIPHER_WEP:
3429 case ATH9K_CIPHER_MIC:
3430 case ATH9K_CIPHER_CLR:
3431 return true;
3432 default:
3433 return false;
3434 }
3435 case ATH9K_CAP_TKIP_MIC:
3436 switch (capability) {
3437 case 0:
3438 return true;
3439 case 1:
2660b81a 3440 return (ah->sta_id1_defaults &
f1dc5600
S		 3441 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3442 false;
3443 }
3444 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3445 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3446 false : true;
f1dc5600
S		 3447 case ATH9K_CAP_DIVERSITY:
3448 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3449 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3450 true : false;
f1dc5600
S		 3451 case ATH9K_CAP_MCAST_KEYSRCH:
3452 switch (capability) {
3453 case 0:
3454 return true;
3455 case 1:
3456 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3457 return false;
3458 } else {
2660b81a 3459 return (ah->sta_id1_defaults &
f1dc5600
S		 3460 AR_STA_ID1_MCAST_KSRCH) ? true :
3461 false;
3462 }
3463 }
3464 return false;
f1dc5600
S		 3465 case ATH9K_CAP_TXPOW:
3466 switch (capability) {
3467 case 0:
3468 return 0;
3469 case 1:
d6bad496 3470 *result = ah->regulatory.power_limit;
f1dc5600
S		 3471 return 0;
3472 case 2:
d6bad496 3473 *result = ah->regulatory.max_power_level;
f1dc5600
S		 3474 return 0;
3475 case 3:
d6bad496 3476 *result = ah->regulatory.tp_scale;
f1dc5600
S		 3477 return 0;
3478 }
3479 return false;
8bd1d07f
SB		 3480 case ATH9K_CAP_DS:
3481 return (AR_SREV_9280_20_OR_LATER(ah) &&
3482 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3483 ? false : true;
f1dc5600
S		 3484 default:
3485 return false;
f078f209 3486 }
f078f209
LR		 3487}
3488
cbe61d8a 3489bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3490 u32 capability, u32 setting, int *status)
f078f209 3491{
f1dc5600 3492 u32 v;
f078f209 3493
f1dc5600
S		 3494 switch (type) {
3495 case ATH9K_CAP_TKIP_MIC:
3496 if (setting)
2660b81a 3497 ah->sta_id1_defaults |=
f1dc5600
S		 3498 AR_STA_ID1_CRPT_MIC_ENABLE;
3499 else
2660b81a 3500 ah->sta_id1_defaults &=
f1dc5600
S		 3501 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3502 return true;
3503 case ATH9K_CAP_DIVERSITY:
3504 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3505 if (setting)
3506 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3507 else
3508 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3509 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3510 return true;
3511 case ATH9K_CAP_MCAST_KEYSRCH:
3512 if (setting)
2660b81a 3513 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3514 else
2660b81a 3515 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3516 return true;
f1dc5600
S		 3517 default:
3518 return false;
f078f209
LR		 3519 }
3520}
3521
f1dc5600
S		 3522/****************************/
3523/* GPIO / RFKILL / Antennae */
3524/****************************/
f078f209 3525
cbe61d8a 3526static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3527 u32 gpio, u32 type)
3528{
3529 int addr;
3530 u32 gpio_shift, tmp;
f078f209 3531
f1dc5600
S		 3532 if (gpio > 11)
3533 addr = AR_GPIO_OUTPUT_MUX3;
3534 else if (gpio > 5)
3535 addr = AR_GPIO_OUTPUT_MUX2;
3536 else
3537 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3538
f1dc5600 3539 gpio_shift = (gpio % 6) * 5;
f078f209 3540
f1dc5600
S		 3541 if (AR_SREV_9280_20_OR_LATER(ah)
3542 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3543 REG_RMW(ah, addr, (type << gpio_shift),
3544 (0x1f << gpio_shift));
f078f209 3545 } else {
f1dc5600
S		 3546 tmp = REG_READ(ah, addr);
3547 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3548 tmp &= ~(0x1f << gpio_shift);
3549 tmp |= (type << gpio_shift);
3550 REG_WRITE(ah, addr, tmp);
f078f209 3551 }
f078f209
LR		 3552}
3553
cbe61d8a 3554void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3555{
f1dc5600 3556 u32 gpio_shift;
f078f209 3557
2660b81a 3558 ASSERT(gpio < ah->caps.num_gpio_pins);
f078f209 3559
f1dc5600 3560 gpio_shift = gpio << 1;
f078f209 3561
f1dc5600
S		 3562 REG_RMW(ah,
3563 AR_GPIO_OE_OUT,
3564 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3565 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3566}
3567
cbe61d8a 3568u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3569{
cb33c412
SB		 3570#define MS_REG_READ(x, y) \
3571 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3572
2660b81a 3573 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3574 return 0xffffffff;
f078f209 3575
cb33c412
SB		 3576 if (AR_SREV_9285_10_OR_LATER(ah))
3577 return MS_REG_READ(AR9285, gpio) != 0;
3578 else if (AR_SREV_9280_10_OR_LATER(ah))
3579 return MS_REG_READ(AR928X, gpio) != 0;
3580 else
3581 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3582}
3583
cbe61d8a 3584void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3585 u32 ah_signal_type)
f078f209 3586{
f1dc5600 3587 u32 gpio_shift;
f078f209 3588
f1dc5600 3589 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3590
f1dc5600 3591 gpio_shift = 2 * gpio;
f078f209 3592
f1dc5600
S		 3593 REG_RMW(ah,
3594 AR_GPIO_OE_OUT,
3595 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3596 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3597}
3598
cbe61d8a 3599void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3600{
f1dc5600
S		 3601 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3602 AR_GPIO_BIT(gpio));
f078f209
LR		 3603}
3604
e97275cb 3605#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
cbe61d8a 3606void ath9k_enable_rfkill(struct ath_hw *ah)
f078f209 3607{
f1dc5600
S		 3608 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3609 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
f078f209 3610
f1dc5600
S		 3611 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3612 AR_GPIO_INPUT_MUX2_RFSILENT);
3613
2660b81a 3614 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
f1dc5600 3615 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
f078f209 3616}
f1dc5600 3617#endif
f078f209 3618
cbe61d8a 3619u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3620{
f1dc5600 3621 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3622}
3623
cbe61d8a 3624void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3625{
f1dc5600 3626 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3627}
3628
cbe61d8a 3629bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
f1dc5600
S		 3630 enum ath9k_ant_setting settings,
3631 struct ath9k_channel *chan,
3632 u8 *tx_chainmask,
3633 u8 *rx_chainmask,
3634 u8 *antenna_cfgd)
f078f209 3635{
f1dc5600 3636 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3637
f1dc5600
S		 3638 if (AR_SREV_9280(ah)) {
3639 if (!tx_chainmask_cfg) {
f078f209 3640
f1dc5600
S		 3641 tx_chainmask_cfg = *tx_chainmask;
3642 rx_chainmask_cfg = *rx_chainmask;
3643 }
f078f209 3644
f1dc5600
S		 3645 switch (settings) {
3646 case ATH9K_ANT_FIXED_A:
3647 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3648 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3649 *antenna_cfgd = true;
3650 break;
3651 case ATH9K_ANT_FIXED_B:
2660b81a 3652 if (ah->caps.tx_chainmask >
f1dc5600
S		 3653 ATH9K_ANTENNA1_CHAINMASK) {
3654 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3655 }
3656 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3657 *antenna_cfgd = true;
3658 break;
3659 case ATH9K_ANT_VARIABLE:
3660 *tx_chainmask = tx_chainmask_cfg;
3661 *rx_chainmask = rx_chainmask_cfg;
3662 *antenna_cfgd = true;
3663 break;
3664 default:
3665 break;
3666 }
3667 } else {
2660b81a 3668 ah->diversity_control = settings;
f078f209 3669 }
f078f209 3670
f1dc5600 3671 return true;
f078f209
LR		 3672}
3673
f1dc5600
S		 3674/*********************/
3675/* General Operation */
3676/*********************/
3677
cbe61d8a 3678u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3679{
f1dc5600
S		 3680 u32 bits = REG_READ(ah, AR_RX_FILTER);
3681 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3682
f1dc5600
S		 3683 if (phybits & AR_PHY_ERR_RADAR)
3684 bits |= ATH9K_RX_FILTER_PHYRADAR;
3685 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3686 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3687
f1dc5600 3688 return bits;
f078f209
LR		 3689}
3690
cbe61d8a 3691void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3692{
f1dc5600 3693 u32 phybits;
f078f209 3694
f1dc5600
S		 3695 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3696 phybits = 0;
3697 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3698 phybits |= AR_PHY_ERR_RADAR;
3699 if (bits & ATH9K_RX_FILTER_PHYERR)
3700 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3701 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3702
f1dc5600
S		 3703 if (phybits)
3704 REG_WRITE(ah, AR_RXCFG,
3705 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3706 else
3707 REG_WRITE(ah, AR_RXCFG,
3708 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3709}
f078f209 3710
cbe61d8a 3711bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600
S		 3712{
3713 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3714}
f078f209 3715
cbe61d8a 3716bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600
S		 3717{
3718 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3719 return false;
f078f209 3720
f1dc5600 3721 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3722}
3723
cbe61d8a 3724bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 3725{
2660b81a 3726 struct ath9k_channel *chan = ah->curchan;
5f8e077c 3727 struct ieee80211_channel *channel = chan->chan;
f078f209 3728
d6bad496 3729 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3730
f74df6fb
S		 3731 if (ah->eep_ops->set_txpower(ah, chan,
3732 ath9k_regd_get_ctl(ah, chan),
3733 channel->max_antenna_gain * 2,
3734 channel->max_power * 2,
3735 min((u32) MAX_RATE_POWER,
3736 (u32) ah->regulatory.power_limit)) != 0)
6f255425 3737 return false;
f1dc5600 3738
6f255425
LR		 3739 return true;
3740}
3741
cbe61d8a 3742void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 3743{
ba52da58 3744 memcpy(ah->macaddr, mac, ETH_ALEN);
f078f209
LR		 3745}
3746
cbe61d8a 3747void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 3748{
2660b81a 3749 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209
LR		 3750}
3751
cbe61d8a 3752void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 3753{
f1dc5600
S		 3754 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3755 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 3756}
3757
ba52da58 3758void ath9k_hw_setbssidmask(struct ath_softc *sc)
f078f209 3759{
ba52da58
S		 3760 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3761 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 3762}
3763
ba52da58 3764void ath9k_hw_write_associd(struct ath_softc *sc)
f078f209 3765{
ba52da58
S		 3766 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3767 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3768 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 3769}
3770
cbe61d8a 3771u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 3772{
f1dc5600 3773 u64 tsf;
f078f209 3774
f1dc5600
S		 3775 tsf = REG_READ(ah, AR_TSF_U32);
3776 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 3777
f1dc5600
S		 3778 return tsf;
3779}
f078f209 3780
cbe61d8a 3781void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060
AF		 3782{
3783 REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3784 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3785 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3786}
3787
cbe61d8a 3788void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600
S		 3789{
3790 int count;
f078f209 3791
f1dc5600
S		 3792 count = 0;
3793 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3794 count++;
3795 if (count > 10) {
3796 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 3797 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f1dc5600 3798 break;
f078f209 3799 }
f1dc5600
S		 3800 udelay(10);
3801 }
3802 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3803}
f078f209 3804
cbe61d8a 3805bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 3806{
f1dc5600 3807 if (setting)
2660b81a 3808 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3809 else
2660b81a 3810 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f078f209 3811
f1dc5600
S		 3812 return true;
3813}
f078f209 3814
cbe61d8a 3815bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 3816{
f1dc5600 3817 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
04bd4638 3818 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
2660b81a 3819 ah->slottime = (u32) -1;
f1dc5600
S		 3820 return false;
3821 } else {
3822 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 3823 ah->slottime = us;
f1dc5600 3824 return true;
f078f209 3825 }
f1dc5600
S		 3826}
3827
cbe61d8a 3828void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
f1dc5600
S		 3829{
3830 u32 macmode;
3831
3832 if (mode == ATH9K_HT_MACMODE_2040 &&
2660b81a 3833 !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3834 macmode = AR_2040_JOINED_RX_CLEAR;
3835 else
3836 macmode = 0;
f078f209 3837
f1dc5600 3838 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3839}
c97c92d9
VT		 3840
3841/***************************/
3842/* Bluetooth Coexistence */
3843/***************************/
3844
cbe61d8a 3845void ath9k_hw_btcoex_enable(struct ath_hw *ah)
c97c92d9
VT		 3846{
3847 /* connect bt_active to baseband */
3848 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3849 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3850 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3851
3852 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3853 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3854
3855 /* Set input mux for bt_active to gpio pin */
3856 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3857 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2660b81a 3858 ah->btactive_gpio);
c97c92d9
VT		 3859
3860 /* Configure the desired gpio port for input */
2660b81a 3861 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
c97c92d9
VT		 3862
3863 /* Configure the desired GPIO port for TX_FRAME output */
2660b81a 3864 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
c97c92d9
VT		 3865 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3866}
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