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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/printk.h> | |
21 | #include <linux/pci_ids.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/mmc/sdio.h> | |
26 | #include <linux/mmc/sdio_func.h> | |
27 | #include <linux/mmc/card.h> | |
28 | #include <linux/semaphore.h> | |
29 | #include <linux/firmware.h> | |
b7a57e76 | 30 | #include <linux/module.h> |
99ba15cd | 31 | #include <linux/bcma/bcma.h> |
4fc0d016 | 32 | #include <linux/debugfs.h> |
8dc01811 | 33 | #include <linux/vmalloc.h> |
668761ac | 34 | #include <linux/platform_data/brcmfmac-sdio.h> |
5b435de0 AS |
35 | #include <asm/unaligned.h> |
36 | #include <defs.h> | |
37 | #include <brcmu_wifi.h> | |
38 | #include <brcmu_utils.h> | |
39 | #include <brcm_hw_ids.h> | |
40 | #include <soc.h> | |
41 | #include "sdio_host.h" | |
a83369b6 | 42 | #include "sdio_chip.h" |
5b435de0 AS |
43 | |
44 | #define DCMD_RESP_TIMEOUT 2000 /* In milli second */ | |
45 | ||
8ae74654 | 46 | #ifdef DEBUG |
5b435de0 AS |
47 | |
48 | #define BRCMF_TRAP_INFO_SIZE 80 | |
49 | ||
50 | #define CBUF_LEN (128) | |
51 | ||
4fc0d016 AS |
52 | /* Device console log buffer state */ |
53 | #define CONSOLE_BUFFER_MAX 2024 | |
54 | ||
5b435de0 AS |
55 | struct rte_log_le { |
56 | __le32 buf; /* Can't be pointer on (64-bit) hosts */ | |
57 | __le32 buf_size; | |
58 | __le32 idx; | |
59 | char *_buf_compat; /* Redundant pointer for backward compat. */ | |
60 | }; | |
61 | ||
62 | struct rte_console { | |
63 | /* Virtual UART | |
64 | * When there is no UART (e.g. Quickturn), | |
65 | * the host should write a complete | |
66 | * input line directly into cbuf and then write | |
67 | * the length into vcons_in. | |
68 | * This may also be used when there is a real UART | |
69 | * (at risk of conflicting with | |
70 | * the real UART). vcons_out is currently unused. | |
71 | */ | |
72 | uint vcons_in; | |
73 | uint vcons_out; | |
74 | ||
75 | /* Output (logging) buffer | |
76 | * Console output is written to a ring buffer log_buf at index log_idx. | |
77 | * The host may read the output when it sees log_idx advance. | |
78 | * Output will be lost if the output wraps around faster than the host | |
79 | * polls. | |
80 | */ | |
81 | struct rte_log_le log_le; | |
82 | ||
83 | /* Console input line buffer | |
84 | * Characters are read one at a time into cbuf | |
85 | * until <CR> is received, then | |
86 | * the buffer is processed as a command line. | |
87 | * Also used for virtual UART. | |
88 | */ | |
89 | uint cbuf_idx; | |
90 | char cbuf[CBUF_LEN]; | |
91 | }; | |
92 | ||
8ae74654 | 93 | #endif /* DEBUG */ |
5b435de0 AS |
94 | #include <chipcommon.h> |
95 | ||
5b435de0 | 96 | #include "dhd_bus.h" |
5b435de0 | 97 | #include "dhd_dbg.h" |
40c1c249 | 98 | #include "tracepoint.h" |
5b435de0 AS |
99 | |
100 | #define TXQLEN 2048 /* bulk tx queue length */ | |
101 | #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ | |
102 | #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ | |
103 | #define PRIOMASK 7 | |
104 | ||
105 | #define TXRETRIES 2 /* # of retries for tx frames */ | |
106 | ||
107 | #define BRCMF_RXBOUND 50 /* Default for max rx frames in | |
108 | one scheduling */ | |
109 | ||
110 | #define BRCMF_TXBOUND 20 /* Default for max tx frames in | |
111 | one scheduling */ | |
112 | ||
113 | #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ | |
114 | ||
115 | #define MEMBLOCK 2048 /* Block size used for downloading | |
116 | of dongle image */ | |
117 | #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold | |
118 | biggest possible glom */ | |
119 | ||
120 | #define BRCMF_FIRSTREAD (1 << 6) | |
121 | ||
122 | ||
123 | /* SBSDIO_DEVICE_CTL */ | |
124 | ||
125 | /* 1: device will assert busy signal when receiving CMD53 */ | |
126 | #define SBSDIO_DEVCTL_SETBUSY 0x01 | |
127 | /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ | |
128 | #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 | |
129 | /* 1: mask all interrupts to host except the chipActive (rev 8) */ | |
130 | #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 | |
131 | /* 1: isolate internal sdio signals, put external pads in tri-state; requires | |
132 | * sdio bus power cycle to clear (rev 9) */ | |
133 | #define SBSDIO_DEVCTL_PADS_ISO 0x08 | |
134 | /* Force SD->SB reset mapping (rev 11) */ | |
135 | #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 | |
136 | /* Determined by CoreControl bit */ | |
137 | #define SBSDIO_DEVCTL_RST_CORECTL 0x00 | |
138 | /* Force backplane reset */ | |
139 | #define SBSDIO_DEVCTL_RST_BPRESET 0x10 | |
140 | /* Force no backplane reset */ | |
141 | #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 | |
142 | ||
5b435de0 AS |
143 | /* direct(mapped) cis space */ |
144 | ||
145 | /* MAPPED common CIS address */ | |
146 | #define SBSDIO_CIS_BASE_COMMON 0x1000 | |
147 | /* maximum bytes in one CIS */ | |
148 | #define SBSDIO_CIS_SIZE_LIMIT 0x200 | |
149 | /* cis offset addr is < 17 bits */ | |
150 | #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF | |
151 | ||
152 | /* manfid tuple length, include tuple, link bytes */ | |
153 | #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 | |
154 | ||
155 | /* intstatus */ | |
156 | #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ | |
157 | #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ | |
158 | #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ | |
159 | #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ | |
160 | #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ | |
161 | #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ | |
162 | #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ | |
163 | #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ | |
164 | #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ | |
165 | #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ | |
166 | #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ | |
167 | #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ | |
168 | #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ | |
169 | #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ | |
170 | #define I_PC (1 << 10) /* descriptor error */ | |
171 | #define I_PD (1 << 11) /* data error */ | |
172 | #define I_DE (1 << 12) /* Descriptor protocol Error */ | |
173 | #define I_RU (1 << 13) /* Receive descriptor Underflow */ | |
174 | #define I_RO (1 << 14) /* Receive fifo Overflow */ | |
175 | #define I_XU (1 << 15) /* Transmit fifo Underflow */ | |
176 | #define I_RI (1 << 16) /* Receive Interrupt */ | |
177 | #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ | |
178 | #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ | |
179 | #define I_XI (1 << 24) /* Transmit Interrupt */ | |
180 | #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ | |
181 | #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ | |
182 | #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ | |
183 | #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ | |
184 | #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ | |
185 | #define I_SRESET (1 << 30) /* CCCR RES interrupt */ | |
186 | #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ | |
187 | #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) | |
188 | #define I_DMA (I_RI | I_XI | I_ERRORS) | |
189 | ||
190 | /* corecontrol */ | |
191 | #define CC_CISRDY (1 << 0) /* CIS Ready */ | |
192 | #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ | |
193 | #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ | |
194 | #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ | |
195 | #define CC_XMTDATAAVAIL_MODE (1 << 4) | |
196 | #define CC_XMTDATAAVAIL_CTRL (1 << 5) | |
197 | ||
198 | /* SDA_FRAMECTRL */ | |
199 | #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ | |
200 | #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ | |
201 | #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ | |
202 | #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ | |
203 | ||
5b435de0 AS |
204 | /* |
205 | * Software allocation of To SB Mailbox resources | |
206 | */ | |
207 | ||
208 | /* tosbmailbox bits corresponding to intstatus bits */ | |
209 | #define SMB_NAK (1 << 0) /* Frame NAK */ | |
210 | #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ | |
211 | #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ | |
212 | #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ | |
213 | ||
214 | /* tosbmailboxdata */ | |
215 | #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ | |
216 | ||
217 | /* | |
218 | * Software allocation of To Host Mailbox resources | |
219 | */ | |
220 | ||
221 | /* intstatus bits */ | |
222 | #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ | |
223 | #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ | |
224 | #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ | |
225 | #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ | |
226 | ||
227 | /* tohostmailboxdata */ | |
228 | #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ | |
229 | #define HMB_DATA_DEVREADY 2 /* talk to host after enable */ | |
230 | #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ | |
231 | #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ | |
232 | ||
233 | #define HMB_DATA_FCDATA_MASK 0xff000000 | |
234 | #define HMB_DATA_FCDATA_SHIFT 24 | |
235 | ||
236 | #define HMB_DATA_VERSION_MASK 0x00ff0000 | |
237 | #define HMB_DATA_VERSION_SHIFT 16 | |
238 | ||
239 | /* | |
240 | * Software-defined protocol header | |
241 | */ | |
242 | ||
243 | /* Current protocol version */ | |
244 | #define SDPCM_PROT_VERSION 4 | |
245 | ||
5b435de0 AS |
246 | /* |
247 | * Shared structure between dongle and the host. | |
248 | * The structure contains pointers to trap or assert information. | |
249 | */ | |
4fc0d016 | 250 | #define SDPCM_SHARED_VERSION 0x0003 |
5b435de0 AS |
251 | #define SDPCM_SHARED_VERSION_MASK 0x00FF |
252 | #define SDPCM_SHARED_ASSERT_BUILT 0x0100 | |
253 | #define SDPCM_SHARED_ASSERT 0x0200 | |
254 | #define SDPCM_SHARED_TRAP 0x0400 | |
255 | ||
256 | /* Space for header read, limit for data packets */ | |
257 | #define MAX_HDR_READ (1 << 6) | |
258 | #define MAX_RX_DATASZ 2048 | |
259 | ||
260 | /* Maximum milliseconds to wait for F2 to come up */ | |
261 | #define BRCMF_WAIT_F2RDY 3000 | |
262 | ||
263 | /* Bump up limit on waiting for HT to account for first startup; | |
264 | * if the image is doing a CRC calculation before programming the PMU | |
265 | * for HT availability, it could take a couple hundred ms more, so | |
266 | * max out at a 1 second (1000000us). | |
267 | */ | |
268 | #undef PMU_MAX_TRANSITION_DLY | |
269 | #define PMU_MAX_TRANSITION_DLY 1000000 | |
270 | ||
271 | /* Value for ChipClockCSR during initial setup */ | |
272 | #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ | |
273 | SBSDIO_ALP_AVAIL_REQ) | |
274 | ||
275 | /* Flags for SDH calls */ | |
276 | #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) | |
277 | ||
382a9e0f FL |
278 | #define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */ |
279 | #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change | |
280 | * when idle | |
281 | */ | |
282 | #define BRCMF_IDLE_INTERVAL 1 | |
283 | ||
4a3da990 PH |
284 | #define KSO_WAIT_US 50 |
285 | #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) | |
286 | ||
5b435de0 AS |
287 | /* |
288 | * Conversion of 802.1D priority to precedence level | |
289 | */ | |
290 | static uint prio2prec(u32 prio) | |
291 | { | |
292 | return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? | |
293 | (prio^2) : prio; | |
294 | } | |
295 | ||
8ae74654 | 296 | #ifdef DEBUG |
5b435de0 AS |
297 | /* Device console log buffer state */ |
298 | struct brcmf_console { | |
299 | uint count; /* Poll interval msec counter */ | |
300 | uint log_addr; /* Log struct address (fixed) */ | |
301 | struct rte_log_le log_le; /* Log struct (host copy) */ | |
302 | uint bufsize; /* Size of log buffer */ | |
303 | u8 *buf; /* Log buffer (host copy) */ | |
304 | uint last; /* Last buffer read index */ | |
305 | }; | |
4fc0d016 AS |
306 | |
307 | struct brcmf_trap_info { | |
308 | __le32 type; | |
309 | __le32 epc; | |
310 | __le32 cpsr; | |
311 | __le32 spsr; | |
312 | __le32 r0; /* a1 */ | |
313 | __le32 r1; /* a2 */ | |
314 | __le32 r2; /* a3 */ | |
315 | __le32 r3; /* a4 */ | |
316 | __le32 r4; /* v1 */ | |
317 | __le32 r5; /* v2 */ | |
318 | __le32 r6; /* v3 */ | |
319 | __le32 r7; /* v4 */ | |
320 | __le32 r8; /* v5 */ | |
321 | __le32 r9; /* sb/v6 */ | |
322 | __le32 r10; /* sl/v7 */ | |
323 | __le32 r11; /* fp/v8 */ | |
324 | __le32 r12; /* ip */ | |
325 | __le32 r13; /* sp */ | |
326 | __le32 r14; /* lr */ | |
327 | __le32 pc; /* r15 */ | |
328 | }; | |
8ae74654 | 329 | #endif /* DEBUG */ |
5b435de0 AS |
330 | |
331 | struct sdpcm_shared { | |
332 | u32 flags; | |
333 | u32 trap_addr; | |
334 | u32 assert_exp_addr; | |
335 | u32 assert_file_addr; | |
336 | u32 assert_line; | |
337 | u32 console_addr; /* Address of struct rte_console */ | |
338 | u32 msgtrace_addr; | |
339 | u8 tag[32]; | |
4fc0d016 | 340 | u32 brpt_addr; |
5b435de0 AS |
341 | }; |
342 | ||
343 | struct sdpcm_shared_le { | |
344 | __le32 flags; | |
345 | __le32 trap_addr; | |
346 | __le32 assert_exp_addr; | |
347 | __le32 assert_file_addr; | |
348 | __le32 assert_line; | |
349 | __le32 console_addr; /* Address of struct rte_console */ | |
350 | __le32 msgtrace_addr; | |
351 | u8 tag[32]; | |
4fc0d016 | 352 | __le32 brpt_addr; |
5b435de0 AS |
353 | }; |
354 | ||
6bc52319 FL |
355 | /* dongle SDIO bus specific header info */ |
356 | struct brcmf_sdio_hdrinfo { | |
4754fcee FL |
357 | u8 seq_num; |
358 | u8 channel; | |
359 | u16 len; | |
360 | u16 len_left; | |
361 | u16 len_nxtfrm; | |
362 | u8 dat_offset; | |
363 | }; | |
5b435de0 AS |
364 | |
365 | /* misc chip info needed by some of the routines */ | |
5b435de0 | 366 | /* Private data for SDIO bus interaction */ |
e92eedf4 | 367 | struct brcmf_sdio { |
5b435de0 AS |
368 | struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ |
369 | struct chip_info *ci; /* Chip info struct */ | |
370 | char *vars; /* Variables (from CIS and/or other) */ | |
371 | uint varsz; /* Size of variables buffer */ | |
372 | ||
373 | u32 ramsize; /* Size of RAM in SOCRAM (bytes) */ | |
374 | ||
375 | u32 hostintmask; /* Copy of Host Interrupt Mask */ | |
4531603a FL |
376 | atomic_t intstatus; /* Intstatus bits (events) pending */ |
377 | atomic_t fcstate; /* State of dongle flow-control */ | |
5b435de0 AS |
378 | |
379 | uint blocksize; /* Block size of SDIO transfers */ | |
380 | uint roundup; /* Max roundup limit */ | |
381 | ||
382 | struct pktq txq; /* Queue length used for flow-control */ | |
383 | u8 flowcontrol; /* per prio flow control bitmask */ | |
384 | u8 tx_seq; /* Transmit sequence number (next) */ | |
385 | u8 tx_max; /* Maximum transmit sequence allowed */ | |
386 | ||
387 | u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN]; | |
388 | u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ | |
5b435de0 | 389 | u8 rx_seq; /* Receive sequence number (expected) */ |
6bc52319 | 390 | struct brcmf_sdio_hdrinfo cur_read; |
4754fcee | 391 | /* info of current read frame */ |
5b435de0 | 392 | bool rxskip; /* Skip receive (awaiting NAK ACK) */ |
4754fcee | 393 | bool rxpending; /* Data frame pending in dongle */ |
5b435de0 AS |
394 | |
395 | uint rxbound; /* Rx frames to read before resched */ | |
396 | uint txbound; /* Tx frames to send before resched */ | |
397 | uint txminmax; | |
398 | ||
399 | struct sk_buff *glomd; /* Packet containing glomming descriptor */ | |
b83db862 | 400 | struct sk_buff_head glom; /* Packet list for glommed superframe */ |
5b435de0 AS |
401 | uint glomerr; /* Glom packet read errors */ |
402 | ||
403 | u8 *rxbuf; /* Buffer for receiving control packets */ | |
404 | uint rxblen; /* Allocated length of rxbuf */ | |
405 | u8 *rxctl; /* Aligned pointer into rxbuf */ | |
dd43a01c | 406 | u8 *rxctl_orig; /* pointer for freeing rxctl */ |
5b435de0 | 407 | uint rxlen; /* Length of valid data in buffer */ |
dd43a01c | 408 | spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ |
5b435de0 AS |
409 | |
410 | u8 sdpcm_ver; /* Bus protocol reported by dongle */ | |
411 | ||
412 | bool intr; /* Use interrupts */ | |
413 | bool poll; /* Use polling */ | |
1d382273 | 414 | atomic_t ipend; /* Device interrupt is pending */ |
5b435de0 AS |
415 | uint spurious; /* Count of spurious interrupts */ |
416 | uint pollrate; /* Ticks between device polls */ | |
417 | uint polltick; /* Tick counter */ | |
5b435de0 | 418 | |
8ae74654 | 419 | #ifdef DEBUG |
5b435de0 AS |
420 | uint console_interval; |
421 | struct brcmf_console console; /* Console output polling support */ | |
422 | uint console_addr; /* Console address from shared struct */ | |
8ae74654 | 423 | #endif /* DEBUG */ |
5b435de0 | 424 | |
5b435de0 AS |
425 | uint clkstate; /* State of sd and backplane clock(s) */ |
426 | bool activity; /* Activity flag for clock down */ | |
427 | s32 idletime; /* Control for activity timeout */ | |
428 | s32 idlecount; /* Activity timeout counter */ | |
429 | s32 idleclock; /* How to set bus driver when idle */ | |
5b435de0 AS |
430 | bool rxflow_mode; /* Rx flow control mode */ |
431 | bool rxflow; /* Is rx flow control on */ | |
432 | bool alp_only; /* Don't use HT clock (ALP only) */ | |
5b435de0 | 433 | |
5b435de0 AS |
434 | u8 *ctrl_frame_buf; |
435 | u32 ctrl_frame_len; | |
436 | bool ctrl_frame_stat; | |
437 | ||
438 | spinlock_t txqlock; | |
439 | wait_queue_head_t ctrl_wait; | |
440 | wait_queue_head_t dcmd_resp_wait; | |
441 | ||
442 | struct timer_list timer; | |
443 | struct completion watchdog_wait; | |
444 | struct task_struct *watchdog_tsk; | |
445 | bool wd_timer_valid; | |
446 | uint save_ms; | |
447 | ||
f1e68c2e FL |
448 | struct workqueue_struct *brcmf_wq; |
449 | struct work_struct datawork; | |
fccfe930 | 450 | atomic_t dpc_tskcnt; |
5b435de0 | 451 | |
c8bf3484 | 452 | bool txoff; /* Transmit flow-controlled */ |
80969836 | 453 | struct brcmf_sdio_count sdcnt; |
4a3da990 PH |
454 | bool sr_enabled; /* SaveRestore enabled */ |
455 | bool sleeping; /* SDIO bus sleeping */ | |
706478cb FL |
456 | |
457 | u8 tx_hdrlen; /* sdio bus header length for tx packet */ | |
5b435de0 AS |
458 | }; |
459 | ||
5b435de0 AS |
460 | /* clkstate */ |
461 | #define CLK_NONE 0 | |
462 | #define CLK_SDONLY 1 | |
4a3da990 | 463 | #define CLK_PENDING 2 |
5b435de0 AS |
464 | #define CLK_AVAIL 3 |
465 | ||
8ae74654 | 466 | #ifdef DEBUG |
5b435de0 | 467 | static int qcount[NUMPRIO]; |
8ae74654 | 468 | #endif /* DEBUG */ |
5b435de0 | 469 | |
668761ac | 470 | #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ |
5b435de0 AS |
471 | |
472 | #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) | |
473 | ||
474 | /* Retry count for register access failures */ | |
475 | static const uint retry_limit = 2; | |
476 | ||
477 | /* Limit on rounding up frames */ | |
478 | static const uint max_roundup = 512; | |
479 | ||
480 | #define ALIGNMENT 4 | |
481 | ||
9d7d6f95 FL |
482 | enum brcmf_sdio_frmtype { |
483 | BRCMF_SDIO_FT_NORMAL, | |
484 | BRCMF_SDIO_FT_SUPER, | |
485 | BRCMF_SDIO_FT_SUB, | |
486 | }; | |
487 | ||
f2c44fe7 HM |
488 | #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin" |
489 | #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt" | |
490 | #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin" | |
491 | #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt" | |
492 | #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin" | |
493 | #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt" | |
494 | #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin" | |
495 | #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt" | |
496 | #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin" | |
497 | #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt" | |
498 | #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin" | |
499 | #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt" | |
500 | #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin" | |
501 | #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt" | |
502 | ||
503 | MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME); | |
504 | MODULE_FIRMWARE(BCM43143_NVRAM_NAME); | |
505 | MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME); | |
506 | MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME); | |
507 | MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME); | |
508 | MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME); | |
509 | MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME); | |
510 | MODULE_FIRMWARE(BCM4329_NVRAM_NAME); | |
511 | MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME); | |
512 | MODULE_FIRMWARE(BCM4330_NVRAM_NAME); | |
513 | MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME); | |
514 | MODULE_FIRMWARE(BCM4334_NVRAM_NAME); | |
515 | MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME); | |
516 | MODULE_FIRMWARE(BCM4335_NVRAM_NAME); | |
517 | ||
518 | struct brcmf_firmware_names { | |
519 | u32 chipid; | |
520 | u32 revmsk; | |
521 | const char *bin; | |
522 | const char *nv; | |
523 | }; | |
524 | ||
525 | enum brcmf_firmware_type { | |
526 | BRCMF_FIRMWARE_BIN, | |
527 | BRCMF_FIRMWARE_NVRAM | |
528 | }; | |
529 | ||
530 | #define BRCMF_FIRMWARE_NVRAM(name) \ | |
531 | name ## _FIRMWARE_NAME, name ## _NVRAM_NAME | |
532 | ||
533 | static const struct brcmf_firmware_names brcmf_fwname_data[] = { | |
534 | { BCM43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) }, | |
535 | { BCM43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) }, | |
536 | { BCM43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) }, | |
537 | { BCM4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) }, | |
538 | { BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) }, | |
539 | { BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) }, | |
540 | { BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) } | |
541 | }; | |
542 | ||
543 | ||
544 | static const struct firmware *brcmf_sdbrcm_get_fw(struct brcmf_sdio *bus, | |
545 | enum brcmf_firmware_type type) | |
546 | { | |
547 | const struct firmware *fw; | |
548 | const char *name; | |
549 | int err, i; | |
550 | ||
551 | for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) { | |
552 | if (brcmf_fwname_data[i].chipid == bus->ci->chip && | |
553 | brcmf_fwname_data[i].revmsk & BIT(bus->ci->chiprev)) { | |
554 | switch (type) { | |
555 | case BRCMF_FIRMWARE_BIN: | |
556 | name = brcmf_fwname_data[i].bin; | |
557 | break; | |
558 | case BRCMF_FIRMWARE_NVRAM: | |
559 | name = brcmf_fwname_data[i].nv; | |
560 | break; | |
561 | default: | |
562 | brcmf_err("invalid firmware type (%d)\n", type); | |
563 | return NULL; | |
564 | } | |
565 | goto found; | |
566 | } | |
567 | } | |
568 | brcmf_err("Unknown chipid %d [%d]\n", | |
569 | bus->ci->chip, bus->ci->chiprev); | |
570 | return NULL; | |
571 | ||
572 | found: | |
573 | err = request_firmware(&fw, name, &bus->sdiodev->func[2]->dev); | |
574 | if ((err) || (!fw)) { | |
575 | brcmf_err("fail to request firmware %s (%d)\n", name, err); | |
576 | return NULL; | |
577 | } | |
578 | ||
579 | return fw; | |
580 | } | |
581 | ||
5b435de0 AS |
582 | static void pkt_align(struct sk_buff *p, int len, int align) |
583 | { | |
584 | uint datalign; | |
585 | datalign = (unsigned long)(p->data); | |
586 | datalign = roundup(datalign, (align)) - datalign; | |
587 | if (datalign) | |
588 | skb_pull(p, datalign); | |
589 | __skb_trim(p, len); | |
590 | } | |
591 | ||
592 | /* To check if there's window offered */ | |
e92eedf4 | 593 | static bool data_ok(struct brcmf_sdio *bus) |
5b435de0 AS |
594 | { |
595 | return (u8)(bus->tx_max - bus->tx_seq) != 0 && | |
596 | ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; | |
597 | } | |
598 | ||
599 | /* | |
600 | * Reads a register in the SDIO hardware block. This block occupies a series of | |
601 | * adresses on the 32 bit backplane bus. | |
602 | */ | |
58692750 FL |
603 | static int |
604 | r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset) | |
5b435de0 | 605 | { |
99ba15cd | 606 | u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); |
79ae3957 | 607 | int ret; |
58692750 FL |
608 | |
609 | *regvar = brcmf_sdio_regrl(bus->sdiodev, | |
610 | bus->ci->c_inf[idx].base + offset, &ret); | |
611 | ||
612 | return ret; | |
5b435de0 AS |
613 | } |
614 | ||
58692750 FL |
615 | static int |
616 | w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) | |
5b435de0 | 617 | { |
99ba15cd | 618 | u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); |
e13ce26b | 619 | int ret; |
58692750 FL |
620 | |
621 | brcmf_sdio_regwl(bus->sdiodev, | |
622 | bus->ci->c_inf[idx].base + reg_offset, | |
623 | regval, &ret); | |
624 | ||
625 | return ret; | |
5b435de0 AS |
626 | } |
627 | ||
4a3da990 PH |
628 | static int |
629 | brcmf_sdbrcm_kso_control(struct brcmf_sdio *bus, bool on) | |
630 | { | |
631 | u8 wr_val = 0, rd_val, cmp_val, bmask; | |
632 | int err = 0; | |
633 | int try_cnt = 0; | |
634 | ||
635 | brcmf_dbg(TRACE, "Enter\n"); | |
636 | ||
637 | wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
638 | /* 1st KSO write goes to AOS wake up core if device is asleep */ | |
639 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
640 | wr_val, &err); | |
641 | if (err) { | |
642 | brcmf_err("SDIO_AOS KSO write error: %d\n", err); | |
643 | return err; | |
644 | } | |
645 | ||
646 | if (on) { | |
647 | /* device WAKEUP through KSO: | |
648 | * write bit 0 & read back until | |
649 | * both bits 0 (kso bit) & 1 (dev on status) are set | |
650 | */ | |
651 | cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | | |
652 | SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; | |
653 | bmask = cmp_val; | |
654 | usleep_range(2000, 3000); | |
655 | } else { | |
656 | /* Put device to sleep, turn off KSO */ | |
657 | cmp_val = 0; | |
658 | /* only check for bit0, bit1(dev on status) may not | |
659 | * get cleared right away | |
660 | */ | |
661 | bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; | |
662 | } | |
663 | ||
664 | do { | |
665 | /* reliable KSO bit set/clr: | |
666 | * the sdiod sleep write access is synced to PMU 32khz clk | |
667 | * just one write attempt may fail, | |
668 | * read it back until it matches written value | |
669 | */ | |
670 | rd_val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
671 | &err); | |
672 | if (((rd_val & bmask) == cmp_val) && !err) | |
673 | break; | |
674 | brcmf_dbg(SDIO, "KSO wr/rd retry:%d (max: %d) ERR:%x\n", | |
675 | try_cnt, MAX_KSO_ATTEMPTS, err); | |
676 | udelay(KSO_WAIT_US); | |
677 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
678 | wr_val, &err); | |
679 | } while (try_cnt++ < MAX_KSO_ATTEMPTS); | |
680 | ||
681 | return err; | |
682 | } | |
683 | ||
5b435de0 AS |
684 | #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND) |
685 | ||
686 | #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) | |
687 | ||
5b435de0 | 688 | /* Turn backplane clock on or off */ |
e92eedf4 | 689 | static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok) |
5b435de0 AS |
690 | { |
691 | int err; | |
692 | u8 clkctl, clkreq, devctl; | |
693 | unsigned long timeout; | |
694 | ||
c3203374 | 695 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
696 | |
697 | clkctl = 0; | |
698 | ||
4a3da990 PH |
699 | if (bus->sr_enabled) { |
700 | bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); | |
701 | return 0; | |
702 | } | |
703 | ||
5b435de0 AS |
704 | if (on) { |
705 | /* Request HT Avail */ | |
706 | clkreq = | |
707 | bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; | |
708 | ||
3bba829f FL |
709 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
710 | clkreq, &err); | |
5b435de0 | 711 | if (err) { |
5e8149f5 | 712 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
713 | return -EBADE; |
714 | } | |
715 | ||
5b435de0 | 716 | /* Check current status */ |
45db339c FL |
717 | clkctl = brcmf_sdio_regrb(bus->sdiodev, |
718 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 719 | if (err) { |
5e8149f5 | 720 | brcmf_err("HT Avail read error: %d\n", err); |
5b435de0 AS |
721 | return -EBADE; |
722 | } | |
723 | ||
724 | /* Go to pending and await interrupt if appropriate */ | |
725 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { | |
726 | /* Allow only clock-available interrupt */ | |
45db339c FL |
727 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
728 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 729 | if (err) { |
5e8149f5 | 730 | brcmf_err("Devctl error setting CA: %d\n", |
5b435de0 AS |
731 | err); |
732 | return -EBADE; | |
733 | } | |
734 | ||
735 | devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; | |
3bba829f FL |
736 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
737 | devctl, &err); | |
c3203374 | 738 | brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); |
5b435de0 AS |
739 | bus->clkstate = CLK_PENDING; |
740 | ||
741 | return 0; | |
742 | } else if (bus->clkstate == CLK_PENDING) { | |
743 | /* Cancel CA-only interrupt filter */ | |
45db339c | 744 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
5b435de0 AS |
745 | SBSDIO_DEVICE_CTL, &err); |
746 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
3bba829f FL |
747 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
748 | devctl, &err); | |
5b435de0 AS |
749 | } |
750 | ||
751 | /* Otherwise, wait here (polling) for HT Avail */ | |
752 | timeout = jiffies + | |
753 | msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); | |
754 | while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
45db339c FL |
755 | clkctl = brcmf_sdio_regrb(bus->sdiodev, |
756 | SBSDIO_FUNC1_CHIPCLKCSR, | |
757 | &err); | |
5b435de0 AS |
758 | if (time_after(jiffies, timeout)) |
759 | break; | |
760 | else | |
761 | usleep_range(5000, 10000); | |
762 | } | |
763 | if (err) { | |
5e8149f5 | 764 | brcmf_err("HT Avail request error: %d\n", err); |
5b435de0 AS |
765 | return -EBADE; |
766 | } | |
767 | if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { | |
5e8149f5 | 768 | brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", |
5b435de0 AS |
769 | PMU_MAX_TRANSITION_DLY, clkctl); |
770 | return -EBADE; | |
771 | } | |
772 | ||
773 | /* Mark clock available */ | |
774 | bus->clkstate = CLK_AVAIL; | |
c3203374 | 775 | brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); |
5b435de0 | 776 | |
8ae74654 | 777 | #if defined(DEBUG) |
23677ce3 | 778 | if (!bus->alp_only) { |
5b435de0 | 779 | if (SBSDIO_ALPONLY(clkctl)) |
5e8149f5 | 780 | brcmf_err("HT Clock should be on\n"); |
5b435de0 | 781 | } |
8ae74654 | 782 | #endif /* defined (DEBUG) */ |
5b435de0 AS |
783 | |
784 | bus->activity = true; | |
785 | } else { | |
786 | clkreq = 0; | |
787 | ||
788 | if (bus->clkstate == CLK_PENDING) { | |
789 | /* Cancel CA-only interrupt filter */ | |
45db339c FL |
790 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
791 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 792 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; |
3bba829f FL |
793 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
794 | devctl, &err); | |
5b435de0 AS |
795 | } |
796 | ||
797 | bus->clkstate = CLK_SDONLY; | |
3bba829f FL |
798 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
799 | clkreq, &err); | |
c3203374 | 800 | brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); |
5b435de0 | 801 | if (err) { |
5e8149f5 | 802 | brcmf_err("Failed access turning clock off: %d\n", |
5b435de0 AS |
803 | err); |
804 | return -EBADE; | |
805 | } | |
806 | } | |
807 | return 0; | |
808 | } | |
809 | ||
810 | /* Change idle/active SD state */ | |
e92eedf4 | 811 | static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on) |
5b435de0 | 812 | { |
c3203374 | 813 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
814 | |
815 | if (on) | |
816 | bus->clkstate = CLK_SDONLY; | |
817 | else | |
818 | bus->clkstate = CLK_NONE; | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
823 | /* Transition SD and backplane clock readiness */ | |
e92eedf4 | 824 | static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) |
5b435de0 | 825 | { |
8ae74654 | 826 | #ifdef DEBUG |
5b435de0 | 827 | uint oldstate = bus->clkstate; |
8ae74654 | 828 | #endif /* DEBUG */ |
5b435de0 | 829 | |
c3203374 | 830 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
831 | |
832 | /* Early exit if we're already there */ | |
833 | if (bus->clkstate == target) { | |
834 | if (target == CLK_AVAIL) { | |
835 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
836 | bus->activity = true; | |
837 | } | |
838 | return 0; | |
839 | } | |
840 | ||
841 | switch (target) { | |
842 | case CLK_AVAIL: | |
843 | /* Make sure SD clock is available */ | |
844 | if (bus->clkstate == CLK_NONE) | |
845 | brcmf_sdbrcm_sdclk(bus, true); | |
846 | /* Now request HT Avail on the backplane */ | |
847 | brcmf_sdbrcm_htclk(bus, true, pendok); | |
848 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
849 | bus->activity = true; | |
850 | break; | |
851 | ||
852 | case CLK_SDONLY: | |
853 | /* Remove HT request, or bring up SD clock */ | |
854 | if (bus->clkstate == CLK_NONE) | |
855 | brcmf_sdbrcm_sdclk(bus, true); | |
856 | else if (bus->clkstate == CLK_AVAIL) | |
857 | brcmf_sdbrcm_htclk(bus, false, false); | |
858 | else | |
5e8149f5 | 859 | brcmf_err("request for %d -> %d\n", |
5b435de0 AS |
860 | bus->clkstate, target); |
861 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
862 | break; | |
863 | ||
864 | case CLK_NONE: | |
865 | /* Make sure to remove HT request */ | |
866 | if (bus->clkstate == CLK_AVAIL) | |
867 | brcmf_sdbrcm_htclk(bus, false, false); | |
868 | /* Now remove the SD clock */ | |
869 | brcmf_sdbrcm_sdclk(bus, false); | |
870 | brcmf_sdbrcm_wd_timer(bus, 0); | |
871 | break; | |
872 | } | |
8ae74654 | 873 | #ifdef DEBUG |
c3203374 | 874 | brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); |
8ae74654 | 875 | #endif /* DEBUG */ |
5b435de0 AS |
876 | |
877 | return 0; | |
878 | } | |
879 | ||
4a3da990 PH |
880 | static int |
881 | brcmf_sdbrcm_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) | |
882 | { | |
883 | int err = 0; | |
884 | brcmf_dbg(TRACE, "Enter\n"); | |
885 | brcmf_dbg(SDIO, "request %s currently %s\n", | |
886 | (sleep ? "SLEEP" : "WAKE"), | |
887 | (bus->sleeping ? "SLEEP" : "WAKE")); | |
888 | ||
889 | /* If SR is enabled control bus state with KSO */ | |
890 | if (bus->sr_enabled) { | |
891 | /* Done if we're already in the requested state */ | |
892 | if (sleep == bus->sleeping) | |
893 | goto end; | |
894 | ||
895 | /* Going to sleep */ | |
896 | if (sleep) { | |
897 | /* Don't sleep if something is pending */ | |
898 | if (atomic_read(&bus->intstatus) || | |
899 | atomic_read(&bus->ipend) > 0 || | |
900 | (!atomic_read(&bus->fcstate) && | |
901 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
902 | data_ok(bus))) | |
903 | return -EBUSY; | |
904 | err = brcmf_sdbrcm_kso_control(bus, false); | |
905 | /* disable watchdog */ | |
906 | if (!err) | |
907 | brcmf_sdbrcm_wd_timer(bus, 0); | |
908 | } else { | |
909 | bus->idlecount = 0; | |
910 | err = brcmf_sdbrcm_kso_control(bus, true); | |
911 | } | |
912 | if (!err) { | |
913 | /* Change state */ | |
914 | bus->sleeping = sleep; | |
915 | brcmf_dbg(SDIO, "new state %s\n", | |
916 | (sleep ? "SLEEP" : "WAKE")); | |
917 | } else { | |
918 | brcmf_err("error while changing bus sleep state %d\n", | |
919 | err); | |
920 | return err; | |
921 | } | |
922 | } | |
923 | ||
924 | end: | |
925 | /* control clocks */ | |
926 | if (sleep) { | |
927 | if (!bus->sr_enabled) | |
928 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, pendok); | |
929 | } else { | |
930 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, pendok); | |
931 | } | |
932 | ||
933 | return err; | |
934 | ||
935 | } | |
936 | ||
e92eedf4 | 937 | static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus) |
5b435de0 AS |
938 | { |
939 | u32 intstatus = 0; | |
940 | u32 hmb_data; | |
941 | u8 fcbits; | |
58692750 | 942 | int ret; |
5b435de0 | 943 | |
c3203374 | 944 | brcmf_dbg(SDIO, "Enter\n"); |
5b435de0 AS |
945 | |
946 | /* Read mailbox data and ack that we did so */ | |
58692750 FL |
947 | ret = r_sdreg32(bus, &hmb_data, |
948 | offsetof(struct sdpcmd_regs, tohostmailboxdata)); | |
5b435de0 | 949 | |
58692750 | 950 | if (ret == 0) |
5b435de0 | 951 | w_sdreg32(bus, SMB_INT_ACK, |
58692750 | 952 | offsetof(struct sdpcmd_regs, tosbmailbox)); |
80969836 | 953 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
954 | |
955 | /* Dongle recomposed rx frames, accept them again */ | |
956 | if (hmb_data & HMB_DATA_NAKHANDLED) { | |
c3203374 | 957 | brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", |
5b435de0 AS |
958 | bus->rx_seq); |
959 | if (!bus->rxskip) | |
5e8149f5 | 960 | brcmf_err("unexpected NAKHANDLED!\n"); |
5b435de0 AS |
961 | |
962 | bus->rxskip = false; | |
963 | intstatus |= I_HMB_FRAME_IND; | |
964 | } | |
965 | ||
966 | /* | |
967 | * DEVREADY does not occur with gSPI. | |
968 | */ | |
969 | if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { | |
970 | bus->sdpcm_ver = | |
971 | (hmb_data & HMB_DATA_VERSION_MASK) >> | |
972 | HMB_DATA_VERSION_SHIFT; | |
973 | if (bus->sdpcm_ver != SDPCM_PROT_VERSION) | |
5e8149f5 | 974 | brcmf_err("Version mismatch, dongle reports %d, " |
5b435de0 AS |
975 | "expecting %d\n", |
976 | bus->sdpcm_ver, SDPCM_PROT_VERSION); | |
977 | else | |
c3203374 | 978 | brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", |
5b435de0 AS |
979 | bus->sdpcm_ver); |
980 | } | |
981 | ||
982 | /* | |
983 | * Flow Control has been moved into the RX headers and this out of band | |
984 | * method isn't used any more. | |
985 | * remaining backward compatible with older dongles. | |
986 | */ | |
987 | if (hmb_data & HMB_DATA_FC) { | |
988 | fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> | |
989 | HMB_DATA_FCDATA_SHIFT; | |
990 | ||
991 | if (fcbits & ~bus->flowcontrol) | |
80969836 | 992 | bus->sdcnt.fc_xoff++; |
5b435de0 AS |
993 | |
994 | if (bus->flowcontrol & ~fcbits) | |
80969836 | 995 | bus->sdcnt.fc_xon++; |
5b435de0 | 996 | |
80969836 | 997 | bus->sdcnt.fc_rcvd++; |
5b435de0 AS |
998 | bus->flowcontrol = fcbits; |
999 | } | |
1000 | ||
1001 | /* Shouldn't be any others */ | |
1002 | if (hmb_data & ~(HMB_DATA_DEVREADY | | |
1003 | HMB_DATA_NAKHANDLED | | |
1004 | HMB_DATA_FC | | |
1005 | HMB_DATA_FWREADY | | |
1006 | HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) | |
5e8149f5 | 1007 | brcmf_err("Unknown mailbox data content: 0x%02x\n", |
5b435de0 AS |
1008 | hmb_data); |
1009 | ||
1010 | return intstatus; | |
1011 | } | |
1012 | ||
e92eedf4 | 1013 | static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) |
5b435de0 AS |
1014 | { |
1015 | uint retries = 0; | |
1016 | u16 lastrbc; | |
1017 | u8 hi, lo; | |
1018 | int err; | |
1019 | ||
5e8149f5 | 1020 | brcmf_err("%sterminate frame%s\n", |
5b435de0 AS |
1021 | abort ? "abort command, " : "", |
1022 | rtx ? ", send NAK" : ""); | |
1023 | ||
1024 | if (abort) | |
1025 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
1026 | ||
3bba829f FL |
1027 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
1028 | SFC_RF_TERM, &err); | |
80969836 | 1029 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
1030 | |
1031 | /* Wait until the packet has been flushed (device/FIFO stable) */ | |
1032 | for (lastrbc = retries = 0xffff; retries > 0; retries--) { | |
45db339c | 1033 | hi = brcmf_sdio_regrb(bus->sdiodev, |
5c15c23a | 1034 | SBSDIO_FUNC1_RFRAMEBCHI, &err); |
45db339c | 1035 | lo = brcmf_sdio_regrb(bus->sdiodev, |
5c15c23a | 1036 | SBSDIO_FUNC1_RFRAMEBCLO, &err); |
80969836 | 1037 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
1038 | |
1039 | if ((hi == 0) && (lo == 0)) | |
1040 | break; | |
1041 | ||
1042 | if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { | |
5e8149f5 | 1043 | brcmf_err("count growing: last 0x%04x now 0x%04x\n", |
5b435de0 AS |
1044 | lastrbc, (hi << 8) + lo); |
1045 | } | |
1046 | lastrbc = (hi << 8) + lo; | |
1047 | } | |
1048 | ||
1049 | if (!retries) | |
5e8149f5 | 1050 | brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); |
5b435de0 | 1051 | else |
c3203374 | 1052 | brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); |
5b435de0 AS |
1053 | |
1054 | if (rtx) { | |
80969836 | 1055 | bus->sdcnt.rxrtx++; |
58692750 FL |
1056 | err = w_sdreg32(bus, SMB_NAK, |
1057 | offsetof(struct sdpcmd_regs, tosbmailbox)); | |
5b435de0 | 1058 | |
80969836 | 1059 | bus->sdcnt.f1regdata++; |
58692750 | 1060 | if (err == 0) |
5b435de0 AS |
1061 | bus->rxskip = true; |
1062 | } | |
1063 | ||
1064 | /* Clear partial in any case */ | |
4754fcee | 1065 | bus->cur_read.len = 0; |
5b435de0 AS |
1066 | |
1067 | /* If we can't reach the device, signal failure */ | |
5c15c23a | 1068 | if (err) |
712ac5b3 | 1069 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
1070 | } |
1071 | ||
9a95e60e | 1072 | /* return total length of buffer chain */ |
e92eedf4 | 1073 | static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus) |
9a95e60e AS |
1074 | { |
1075 | struct sk_buff *p; | |
1076 | uint total; | |
1077 | ||
1078 | total = 0; | |
1079 | skb_queue_walk(&bus->glom, p) | |
1080 | total += p->len; | |
1081 | return total; | |
1082 | } | |
1083 | ||
e92eedf4 | 1084 | static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus) |
046808da AS |
1085 | { |
1086 | struct sk_buff *cur, *next; | |
1087 | ||
1088 | skb_queue_walk_safe(&bus->glom, cur, next) { | |
1089 | skb_unlink(cur, &bus->glom); | |
1090 | brcmu_pkt_buf_free_skb(cur); | |
1091 | } | |
1092 | } | |
1093 | ||
6bc52319 FL |
1094 | /** |
1095 | * brcmfmac sdio bus specific header | |
1096 | * This is the lowest layer header wrapped on the packets transmitted between | |
1097 | * host and WiFi dongle which contains information needed for SDIO core and | |
1098 | * firmware | |
1099 | * | |
1100 | * It consists of 2 parts: hw header and software header | |
1101 | * hardware header (frame tag) - 4 bytes | |
1102 | * Byte 0~1: Frame length | |
1103 | * Byte 2~3: Checksum, bit-wise inverse of frame length | |
1104 | * software header - 8 bytes | |
1105 | * Byte 0: Rx/Tx sequence number | |
1106 | * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag | |
1107 | * Byte 2: Length of next data frame, reserved for Tx | |
1108 | * Byte 3: Data offset | |
1109 | * Byte 4: Flow control bits, reserved for Tx | |
1110 | * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet | |
1111 | * Byte 6~7: Reserved | |
1112 | */ | |
1113 | #define SDPCM_HWHDR_LEN 4 | |
1114 | #define SDPCM_SWHDR_LEN 8 | |
1115 | #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) | |
6bc52319 FL |
1116 | /* software header */ |
1117 | #define SDPCM_SEQ_MASK 0x000000ff | |
1118 | #define SDPCM_SEQ_WRAP 256 | |
1119 | #define SDPCM_CHANNEL_MASK 0x00000f00 | |
1120 | #define SDPCM_CHANNEL_SHIFT 8 | |
1121 | #define SDPCM_CONTROL_CHANNEL 0 /* Control */ | |
1122 | #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ | |
1123 | #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ | |
1124 | #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ | |
1125 | #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ | |
1126 | #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) | |
1127 | #define SDPCM_NEXTLEN_MASK 0x00ff0000 | |
1128 | #define SDPCM_NEXTLEN_SHIFT 16 | |
1129 | #define SDPCM_DOFFSET_MASK 0xff000000 | |
1130 | #define SDPCM_DOFFSET_SHIFT 24 | |
1131 | #define SDPCM_FCMASK_MASK 0x000000ff | |
1132 | #define SDPCM_WINDOW_MASK 0x0000ff00 | |
1133 | #define SDPCM_WINDOW_SHIFT 8 | |
1134 | ||
1135 | static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) | |
1136 | { | |
1137 | u32 hdrvalue; | |
1138 | hdrvalue = *(u32 *)swheader; | |
1139 | return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); | |
1140 | } | |
1141 | ||
1142 | static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, | |
1143 | struct brcmf_sdio_hdrinfo *rd, | |
1144 | enum brcmf_sdio_frmtype type) | |
4754fcee FL |
1145 | { |
1146 | u16 len, checksum; | |
1147 | u8 rx_seq, fc, tx_seq_max; | |
6bc52319 | 1148 | u32 swheader; |
4754fcee | 1149 | |
6bc52319 | 1150 | /* hw header */ |
4754fcee FL |
1151 | len = get_unaligned_le16(header); |
1152 | checksum = get_unaligned_le16(header + sizeof(u16)); | |
1153 | /* All zero means no more to read */ | |
1154 | if (!(len | checksum)) { | |
1155 | bus->rxpending = false; | |
10510589 | 1156 | return -ENODATA; |
4754fcee FL |
1157 | } |
1158 | if ((u16)(~(len ^ checksum))) { | |
5e8149f5 | 1159 | brcmf_err("HW header checksum error\n"); |
4754fcee FL |
1160 | bus->sdcnt.rx_badhdr++; |
1161 | brcmf_sdbrcm_rxfail(bus, false, false); | |
10510589 | 1162 | return -EIO; |
4754fcee FL |
1163 | } |
1164 | if (len < SDPCM_HDRLEN) { | |
5e8149f5 | 1165 | brcmf_err("HW header length error\n"); |
10510589 | 1166 | return -EPROTO; |
4754fcee | 1167 | } |
9d7d6f95 FL |
1168 | if (type == BRCMF_SDIO_FT_SUPER && |
1169 | (roundup(len, bus->blocksize) != rd->len)) { | |
5e8149f5 | 1170 | brcmf_err("HW superframe header length error\n"); |
10510589 | 1171 | return -EPROTO; |
9d7d6f95 FL |
1172 | } |
1173 | if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { | |
5e8149f5 | 1174 | brcmf_err("HW subframe header length error\n"); |
10510589 | 1175 | return -EPROTO; |
9d7d6f95 | 1176 | } |
4754fcee FL |
1177 | rd->len = len; |
1178 | ||
6bc52319 FL |
1179 | /* software header */ |
1180 | header += SDPCM_HWHDR_LEN; | |
1181 | swheader = le32_to_cpu(*(__le32 *)header); | |
1182 | if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { | |
5e8149f5 | 1183 | brcmf_err("Glom descriptor found in superframe head\n"); |
9d7d6f95 | 1184 | rd->len = 0; |
10510589 | 1185 | return -EINVAL; |
9d7d6f95 | 1186 | } |
6bc52319 FL |
1187 | rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); |
1188 | rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; | |
9d7d6f95 FL |
1189 | if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && |
1190 | type != BRCMF_SDIO_FT_SUPER) { | |
5e8149f5 | 1191 | brcmf_err("HW header length too long\n"); |
4754fcee FL |
1192 | bus->sdcnt.rx_toolong++; |
1193 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1194 | rd->len = 0; | |
10510589 | 1195 | return -EPROTO; |
4754fcee | 1196 | } |
9d7d6f95 | 1197 | if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { |
5e8149f5 | 1198 | brcmf_err("Wrong channel for superframe\n"); |
9d7d6f95 | 1199 | rd->len = 0; |
10510589 | 1200 | return -EINVAL; |
9d7d6f95 FL |
1201 | } |
1202 | if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && | |
1203 | rd->channel != SDPCM_EVENT_CHANNEL) { | |
5e8149f5 | 1204 | brcmf_err("Wrong channel for subframe\n"); |
9d7d6f95 | 1205 | rd->len = 0; |
10510589 | 1206 | return -EINVAL; |
9d7d6f95 | 1207 | } |
6bc52319 | 1208 | rd->dat_offset = brcmf_sdio_getdatoffset(header); |
4754fcee | 1209 | if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { |
5e8149f5 | 1210 | brcmf_err("seq %d: bad data offset\n", rx_seq); |
4754fcee FL |
1211 | bus->sdcnt.rx_badhdr++; |
1212 | brcmf_sdbrcm_rxfail(bus, false, false); | |
1213 | rd->len = 0; | |
10510589 | 1214 | return -ENXIO; |
4754fcee FL |
1215 | } |
1216 | if (rd->seq_num != rx_seq) { | |
5e8149f5 | 1217 | brcmf_err("seq %d: sequence number error, expect %d\n", |
4754fcee FL |
1218 | rx_seq, rd->seq_num); |
1219 | bus->sdcnt.rx_badseq++; | |
1220 | rd->seq_num = rx_seq; | |
1221 | } | |
9d7d6f95 FL |
1222 | /* no need to check the reset for subframe */ |
1223 | if (type == BRCMF_SDIO_FT_SUB) | |
10510589 | 1224 | return 0; |
6bc52319 | 1225 | rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; |
4754fcee FL |
1226 | if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { |
1227 | /* only warm for NON glom packet */ | |
1228 | if (rd->channel != SDPCM_GLOM_CHANNEL) | |
5e8149f5 | 1229 | brcmf_err("seq %d: next length error\n", rx_seq); |
4754fcee FL |
1230 | rd->len_nxtfrm = 0; |
1231 | } | |
6bc52319 FL |
1232 | swheader = le32_to_cpu(*(__le32 *)(header + 4)); |
1233 | fc = swheader & SDPCM_FCMASK_MASK; | |
4754fcee FL |
1234 | if (bus->flowcontrol != fc) { |
1235 | if (~bus->flowcontrol & fc) | |
1236 | bus->sdcnt.fc_xoff++; | |
1237 | if (bus->flowcontrol & ~fc) | |
1238 | bus->sdcnt.fc_xon++; | |
1239 | bus->sdcnt.fc_rcvd++; | |
1240 | bus->flowcontrol = fc; | |
1241 | } | |
6bc52319 | 1242 | tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; |
4754fcee | 1243 | if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { |
5e8149f5 | 1244 | brcmf_err("seq %d: max tx seq number error\n", rx_seq); |
4754fcee FL |
1245 | tx_seq_max = bus->tx_seq + 2; |
1246 | } | |
1247 | bus->tx_max = tx_seq_max; | |
1248 | ||
10510589 | 1249 | return 0; |
4754fcee FL |
1250 | } |
1251 | ||
6bc52319 FL |
1252 | static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) |
1253 | { | |
1254 | *(__le16 *)header = cpu_to_le16(frm_length); | |
1255 | *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); | |
1256 | } | |
1257 | ||
1258 | static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, | |
1259 | struct brcmf_sdio_hdrinfo *hd_info) | |
1260 | { | |
1261 | u32 sw_header; | |
1262 | ||
1263 | brcmf_sdio_update_hwhdr(header, hd_info->len); | |
1264 | ||
1265 | sw_header = bus->tx_seq; | |
1266 | sw_header |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & | |
1267 | SDPCM_CHANNEL_MASK; | |
1268 | sw_header |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & | |
1269 | SDPCM_DOFFSET_MASK; | |
1270 | *(((__le32 *)header) + 1) = cpu_to_le32(sw_header); | |
1271 | *(((__le32 *)header) + 2) = 0; | |
1272 | } | |
1273 | ||
e92eedf4 | 1274 | static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq) |
5b435de0 AS |
1275 | { |
1276 | u16 dlen, totlen; | |
1277 | u8 *dptr, num = 0; | |
cb7f7968 | 1278 | u32 align = 0; |
9d7d6f95 | 1279 | u16 sublen; |
0b45bf74 | 1280 | struct sk_buff *pfirst, *pnext; |
5b435de0 AS |
1281 | |
1282 | int errcode; | |
9d7d6f95 | 1283 | u8 doff, sfdoff; |
5b435de0 | 1284 | |
6bc52319 | 1285 | struct brcmf_sdio_hdrinfo rd_new; |
5b435de0 AS |
1286 | |
1287 | /* If packets, issue read(s) and send up packet chain */ | |
1288 | /* Return sequence numbers consumed? */ | |
1289 | ||
c3203374 | 1290 | brcmf_dbg(SDIO, "start: glomd %p glom %p\n", |
b83db862 | 1291 | bus->glomd, skb_peek(&bus->glom)); |
5b435de0 | 1292 | |
cb7f7968 FL |
1293 | if (bus->sdiodev->pdata) |
1294 | align = bus->sdiodev->pdata->sd_sgentry_align; | |
1295 | if (align < 4) | |
1296 | align = 4; | |
1297 | ||
5b435de0 AS |
1298 | /* If there's a descriptor, generate the packet chain */ |
1299 | if (bus->glomd) { | |
0b45bf74 | 1300 | pfirst = pnext = NULL; |
5b435de0 AS |
1301 | dlen = (u16) (bus->glomd->len); |
1302 | dptr = bus->glomd->data; | |
1303 | if (!dlen || (dlen & 1)) { | |
5e8149f5 | 1304 | brcmf_err("bad glomd len(%d), ignore descriptor\n", |
5b435de0 AS |
1305 | dlen); |
1306 | dlen = 0; | |
1307 | } | |
1308 | ||
1309 | for (totlen = num = 0; dlen; num++) { | |
1310 | /* Get (and move past) next length */ | |
1311 | sublen = get_unaligned_le16(dptr); | |
1312 | dlen -= sizeof(u16); | |
1313 | dptr += sizeof(u16); | |
1314 | if ((sublen < SDPCM_HDRLEN) || | |
1315 | ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { | |
5e8149f5 | 1316 | brcmf_err("descriptor len %d bad: %d\n", |
5b435de0 AS |
1317 | num, sublen); |
1318 | pnext = NULL; | |
1319 | break; | |
1320 | } | |
cb7f7968 | 1321 | if (sublen % align) { |
5e8149f5 | 1322 | brcmf_err("sublen %d not multiple of %d\n", |
cb7f7968 | 1323 | sublen, align); |
5b435de0 AS |
1324 | } |
1325 | totlen += sublen; | |
1326 | ||
1327 | /* For last frame, adjust read len so total | |
1328 | is a block multiple */ | |
1329 | if (!dlen) { | |
1330 | sublen += | |
1331 | (roundup(totlen, bus->blocksize) - totlen); | |
1332 | totlen = roundup(totlen, bus->blocksize); | |
1333 | } | |
1334 | ||
1335 | /* Allocate/chain packet for next subframe */ | |
cb7f7968 | 1336 | pnext = brcmu_pkt_buf_get_skb(sublen + align); |
5b435de0 | 1337 | if (pnext == NULL) { |
5e8149f5 | 1338 | brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", |
5b435de0 AS |
1339 | num, sublen); |
1340 | break; | |
1341 | } | |
b83db862 | 1342 | skb_queue_tail(&bus->glom, pnext); |
5b435de0 AS |
1343 | |
1344 | /* Adhere to start alignment requirements */ | |
cb7f7968 | 1345 | pkt_align(pnext, sublen, align); |
5b435de0 AS |
1346 | } |
1347 | ||
1348 | /* If all allocations succeeded, save packet chain | |
1349 | in bus structure */ | |
1350 | if (pnext) { | |
1351 | brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", | |
1352 | totlen, num); | |
4754fcee FL |
1353 | if (BRCMF_GLOM_ON() && bus->cur_read.len && |
1354 | totlen != bus->cur_read.len) { | |
5b435de0 | 1355 | brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", |
4754fcee | 1356 | bus->cur_read.len, totlen, rxseq); |
5b435de0 | 1357 | } |
5b435de0 AS |
1358 | pfirst = pnext = NULL; |
1359 | } else { | |
046808da | 1360 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 AS |
1361 | num = 0; |
1362 | } | |
1363 | ||
1364 | /* Done with descriptor packet */ | |
1365 | brcmu_pkt_buf_free_skb(bus->glomd); | |
1366 | bus->glomd = NULL; | |
4754fcee | 1367 | bus->cur_read.len = 0; |
5b435de0 AS |
1368 | } |
1369 | ||
1370 | /* Ok -- either we just generated a packet chain, | |
1371 | or had one from before */ | |
b83db862 | 1372 | if (!skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1373 | if (BRCMF_GLOM_ON()) { |
1374 | brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); | |
b83db862 | 1375 | skb_queue_walk(&bus->glom, pnext) { |
5b435de0 AS |
1376 | brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", |
1377 | pnext, (u8 *) (pnext->data), | |
1378 | pnext->len, pnext->len); | |
1379 | } | |
1380 | } | |
1381 | ||
b83db862 | 1382 | pfirst = skb_peek(&bus->glom); |
9a95e60e | 1383 | dlen = (u16) brcmf_sdbrcm_glom_len(bus); |
5b435de0 AS |
1384 | |
1385 | /* Do an SDIO read for the superframe. Configurable iovar to | |
1386 | * read directly into the chained packet, or allocate a large | |
1387 | * packet and and copy into the chain. | |
1388 | */ | |
38b0b0dd | 1389 | sdio_claim_host(bus->sdiodev->func[1]); |
354b75bf FL |
1390 | errcode = brcmf_sdcard_recv_chain(bus->sdiodev, |
1391 | bus->sdiodev->sbwad, | |
1392 | SDIO_FUNC_2, F2SYNC, &bus->glom); | |
38b0b0dd | 1393 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 1394 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1395 | |
1396 | /* On failure, kill the superframe, allow a couple retries */ | |
1397 | if (errcode < 0) { | |
5e8149f5 | 1398 | brcmf_err("glom read of %d bytes failed: %d\n", |
5b435de0 | 1399 | dlen, errcode); |
5b435de0 | 1400 | |
38b0b0dd | 1401 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1402 | if (bus->glomerr++ < 3) { |
1403 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1404 | } else { | |
1405 | bus->glomerr = 0; | |
1406 | brcmf_sdbrcm_rxfail(bus, true, false); | |
80969836 | 1407 | bus->sdcnt.rxglomfail++; |
046808da | 1408 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 | 1409 | } |
38b0b0dd | 1410 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1411 | return 0; |
1412 | } | |
1e023829 JP |
1413 | |
1414 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), | |
1415 | pfirst->data, min_t(int, pfirst->len, 48), | |
1416 | "SUPERFRAME:\n"); | |
5b435de0 | 1417 | |
9d7d6f95 FL |
1418 | rd_new.seq_num = rxseq; |
1419 | rd_new.len = dlen; | |
38b0b0dd | 1420 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1421 | errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, |
1422 | BRCMF_SDIO_FT_SUPER); | |
38b0b0dd | 1423 | sdio_release_host(bus->sdiodev->func[1]); |
9d7d6f95 | 1424 | bus->cur_read.len = rd_new.len_nxtfrm << 4; |
5b435de0 AS |
1425 | |
1426 | /* Remove superframe header, remember offset */ | |
9d7d6f95 FL |
1427 | skb_pull(pfirst, rd_new.dat_offset); |
1428 | sfdoff = rd_new.dat_offset; | |
0b45bf74 | 1429 | num = 0; |
5b435de0 AS |
1430 | |
1431 | /* Validate all the subframe headers */ | |
0b45bf74 AS |
1432 | skb_queue_walk(&bus->glom, pnext) { |
1433 | /* leave when invalid subframe is found */ | |
1434 | if (errcode) | |
1435 | break; | |
1436 | ||
9d7d6f95 FL |
1437 | rd_new.len = pnext->len; |
1438 | rd_new.seq_num = rxseq++; | |
38b0b0dd | 1439 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1440 | errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, |
1441 | BRCMF_SDIO_FT_SUB); | |
38b0b0dd | 1442 | sdio_release_host(bus->sdiodev->func[1]); |
1e023829 | 1443 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
9d7d6f95 | 1444 | pnext->data, 32, "subframe:\n"); |
5b435de0 | 1445 | |
0b45bf74 | 1446 | num++; |
5b435de0 AS |
1447 | } |
1448 | ||
1449 | if (errcode) { | |
1450 | /* Terminate frame on error, request | |
1451 | a couple retries */ | |
38b0b0dd | 1452 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1453 | if (bus->glomerr++ < 3) { |
1454 | /* Restore superframe header space */ | |
1455 | skb_push(pfirst, sfdoff); | |
1456 | brcmf_sdbrcm_rxfail(bus, true, true); | |
1457 | } else { | |
1458 | bus->glomerr = 0; | |
1459 | brcmf_sdbrcm_rxfail(bus, true, false); | |
80969836 | 1460 | bus->sdcnt.rxglomfail++; |
046808da | 1461 | brcmf_sdbrcm_free_glom(bus); |
5b435de0 | 1462 | } |
38b0b0dd | 1463 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee | 1464 | bus->cur_read.len = 0; |
5b435de0 AS |
1465 | return 0; |
1466 | } | |
1467 | ||
1468 | /* Basic SD framing looks ok - process each packet (header) */ | |
5b435de0 | 1469 | |
0b45bf74 | 1470 | skb_queue_walk_safe(&bus->glom, pfirst, pnext) { |
5b435de0 AS |
1471 | dptr = (u8 *) (pfirst->data); |
1472 | sublen = get_unaligned_le16(dptr); | |
6bc52319 | 1473 | doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); |
5b435de0 | 1474 | |
1e023829 | 1475 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
9d7d6f95 FL |
1476 | dptr, pfirst->len, |
1477 | "Rx Subframe Data:\n"); | |
5b435de0 AS |
1478 | |
1479 | __skb_trim(pfirst, sublen); | |
1480 | skb_pull(pfirst, doff); | |
1481 | ||
1482 | if (pfirst->len == 0) { | |
0b45bf74 | 1483 | skb_unlink(pfirst, &bus->glom); |
5b435de0 | 1484 | brcmu_pkt_buf_free_skb(pfirst); |
5b435de0 | 1485 | continue; |
5b435de0 AS |
1486 | } |
1487 | ||
1e023829 JP |
1488 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
1489 | pfirst->data, | |
1490 | min_t(int, pfirst->len, 32), | |
1491 | "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", | |
1492 | bus->glom.qlen, pfirst, pfirst->data, | |
1493 | pfirst->len, pfirst->next, | |
1494 | pfirst->prev); | |
5b435de0 | 1495 | } |
0b45bf74 | 1496 | /* sent any remaining packets up */ |
7cdf57d3 | 1497 | if (bus->glom.qlen) |
a43af515 | 1498 | brcmf_rx_frames(bus->sdiodev->dev, &bus->glom); |
5b435de0 | 1499 | |
80969836 AS |
1500 | bus->sdcnt.rxglomframes++; |
1501 | bus->sdcnt.rxglompkts += bus->glom.qlen; | |
5b435de0 AS |
1502 | } |
1503 | return num; | |
1504 | } | |
1505 | ||
e92eedf4 | 1506 | static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, |
5b435de0 AS |
1507 | bool *pending) |
1508 | { | |
1509 | DECLARE_WAITQUEUE(wait, current); | |
1510 | int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT); | |
1511 | ||
1512 | /* Wait until control frame is available */ | |
1513 | add_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1514 | set_current_state(TASK_INTERRUPTIBLE); | |
1515 | ||
1516 | while (!(*condition) && (!signal_pending(current) && timeout)) | |
1517 | timeout = schedule_timeout(timeout); | |
1518 | ||
1519 | if (signal_pending(current)) | |
1520 | *pending = true; | |
1521 | ||
1522 | set_current_state(TASK_RUNNING); | |
1523 | remove_wait_queue(&bus->dcmd_resp_wait, &wait); | |
1524 | ||
1525 | return timeout; | |
1526 | } | |
1527 | ||
e92eedf4 | 1528 | static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus) |
5b435de0 AS |
1529 | { |
1530 | if (waitqueue_active(&bus->dcmd_resp_wait)) | |
1531 | wake_up_interruptible(&bus->dcmd_resp_wait); | |
1532 | ||
1533 | return 0; | |
1534 | } | |
1535 | static void | |
e92eedf4 | 1536 | brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) |
5b435de0 AS |
1537 | { |
1538 | uint rdlen, pad; | |
dd43a01c | 1539 | u8 *buf = NULL, *rbuf; |
5b435de0 AS |
1540 | int sdret; |
1541 | ||
1542 | brcmf_dbg(TRACE, "Enter\n"); | |
1543 | ||
dd43a01c FL |
1544 | if (bus->rxblen) |
1545 | buf = vzalloc(bus->rxblen); | |
14f8dc49 | 1546 | if (!buf) |
dd43a01c | 1547 | goto done; |
14f8dc49 | 1548 | |
dd43a01c FL |
1549 | rbuf = bus->rxbuf; |
1550 | pad = ((unsigned long)rbuf % BRCMF_SDALIGN); | |
5b435de0 | 1551 | if (pad) |
dd43a01c | 1552 | rbuf += (BRCMF_SDALIGN - pad); |
5b435de0 AS |
1553 | |
1554 | /* Copy the already-read portion over */ | |
dd43a01c | 1555 | memcpy(buf, hdr, BRCMF_FIRSTREAD); |
5b435de0 AS |
1556 | if (len <= BRCMF_FIRSTREAD) |
1557 | goto gotpkt; | |
1558 | ||
1559 | /* Raise rdlen to next SDIO block to avoid tail command */ | |
1560 | rdlen = len - BRCMF_FIRSTREAD; | |
1561 | if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { | |
1562 | pad = bus->blocksize - (rdlen % bus->blocksize); | |
1563 | if ((pad <= bus->roundup) && (pad < bus->blocksize) && | |
b01a6b3c | 1564 | ((len + pad) < bus->sdiodev->bus_if->maxctl)) |
5b435de0 AS |
1565 | rdlen += pad; |
1566 | } else if (rdlen % BRCMF_SDALIGN) { | |
1567 | rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN); | |
1568 | } | |
1569 | ||
1570 | /* Satisfy length-alignment requirements */ | |
1571 | if (rdlen & (ALIGNMENT - 1)) | |
1572 | rdlen = roundup(rdlen, ALIGNMENT); | |
1573 | ||
1574 | /* Drop if the read is too big or it exceeds our maximum */ | |
b01a6b3c | 1575 | if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1576 | brcmf_err("%d-byte control read exceeds %d-byte buffer\n", |
b01a6b3c | 1577 | rdlen, bus->sdiodev->bus_if->maxctl); |
5b435de0 AS |
1578 | brcmf_sdbrcm_rxfail(bus, false, false); |
1579 | goto done; | |
1580 | } | |
1581 | ||
b01a6b3c | 1582 | if ((len - doff) > bus->sdiodev->bus_if->maxctl) { |
5e8149f5 | 1583 | brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", |
b01a6b3c | 1584 | len, len - doff, bus->sdiodev->bus_if->maxctl); |
80969836 | 1585 | bus->sdcnt.rx_toolong++; |
5b435de0 AS |
1586 | brcmf_sdbrcm_rxfail(bus, false, false); |
1587 | goto done; | |
1588 | } | |
1589 | ||
dd43a01c | 1590 | /* Read remain of frame body */ |
5b435de0 AS |
1591 | sdret = brcmf_sdcard_recv_buf(bus->sdiodev, |
1592 | bus->sdiodev->sbwad, | |
1593 | SDIO_FUNC_2, | |
dd43a01c | 1594 | F2SYNC, rbuf, rdlen); |
80969836 | 1595 | bus->sdcnt.f2rxdata++; |
5b435de0 AS |
1596 | |
1597 | /* Control frame failures need retransmission */ | |
1598 | if (sdret < 0) { | |
5e8149f5 | 1599 | brcmf_err("read %d control bytes failed: %d\n", |
5b435de0 | 1600 | rdlen, sdret); |
80969836 | 1601 | bus->sdcnt.rxc_errors++; |
5b435de0 AS |
1602 | brcmf_sdbrcm_rxfail(bus, true, true); |
1603 | goto done; | |
dd43a01c FL |
1604 | } else |
1605 | memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); | |
5b435de0 AS |
1606 | |
1607 | gotpkt: | |
1608 | ||
1e023829 | 1609 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
dd43a01c | 1610 | buf, len, "RxCtrl:\n"); |
5b435de0 AS |
1611 | |
1612 | /* Point to valid data and indicate its length */ | |
dd43a01c FL |
1613 | spin_lock_bh(&bus->rxctl_lock); |
1614 | if (bus->rxctl) { | |
5e8149f5 | 1615 | brcmf_err("last control frame is being processed.\n"); |
dd43a01c FL |
1616 | spin_unlock_bh(&bus->rxctl_lock); |
1617 | vfree(buf); | |
1618 | goto done; | |
1619 | } | |
1620 | bus->rxctl = buf + doff; | |
1621 | bus->rxctl_orig = buf; | |
5b435de0 | 1622 | bus->rxlen = len - doff; |
dd43a01c | 1623 | spin_unlock_bh(&bus->rxctl_lock); |
5b435de0 AS |
1624 | |
1625 | done: | |
1626 | /* Awake any waiters */ | |
1627 | brcmf_sdbrcm_dcmd_resp_wake(bus); | |
1628 | } | |
1629 | ||
1630 | /* Pad read to blocksize for efficiency */ | |
e92eedf4 | 1631 | static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) |
5b435de0 AS |
1632 | { |
1633 | if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { | |
1634 | *pad = bus->blocksize - (*rdlen % bus->blocksize); | |
1635 | if (*pad <= bus->roundup && *pad < bus->blocksize && | |
1636 | *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) | |
1637 | *rdlen += *pad; | |
1638 | } else if (*rdlen % BRCMF_SDALIGN) { | |
1639 | *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN); | |
1640 | } | |
1641 | } | |
1642 | ||
4754fcee | 1643 | static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 | 1644 | { |
5b435de0 | 1645 | struct sk_buff *pkt; /* Packet for event or data frames */ |
3aa7aad2 | 1646 | struct sk_buff_head pktlist; /* needed for bus interface */ |
5b435de0 | 1647 | u16 pad; /* Number of pad bytes to read */ |
5b435de0 | 1648 | uint rxleft = 0; /* Remaining number of frames allowed */ |
349e7104 | 1649 | int ret; /* Return code from calls */ |
5b435de0 | 1650 | uint rxcount = 0; /* Total frames read */ |
6bc52319 | 1651 | struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; |
4754fcee | 1652 | u8 head_read = 0; |
5b435de0 AS |
1653 | |
1654 | brcmf_dbg(TRACE, "Enter\n"); | |
1655 | ||
1656 | /* Not finished unless we encounter no more frames indication */ | |
4754fcee | 1657 | bus->rxpending = true; |
5b435de0 | 1658 | |
4754fcee | 1659 | for (rd->seq_num = bus->rx_seq, rxleft = maxframes; |
8d169aa0 | 1660 | !bus->rxskip && rxleft && |
712ac5b3 | 1661 | bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN; |
4754fcee | 1662 | rd->seq_num++, rxleft--) { |
5b435de0 AS |
1663 | |
1664 | /* Handle glomming separately */ | |
b83db862 | 1665 | if (bus->glomd || !skb_queue_empty(&bus->glom)) { |
5b435de0 AS |
1666 | u8 cnt; |
1667 | brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", | |
b83db862 | 1668 | bus->glomd, skb_peek(&bus->glom)); |
4754fcee | 1669 | cnt = brcmf_sdbrcm_rxglom(bus, rd->seq_num); |
5b435de0 | 1670 | brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); |
4754fcee | 1671 | rd->seq_num += cnt - 1; |
5b435de0 AS |
1672 | rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; |
1673 | continue; | |
1674 | } | |
1675 | ||
4754fcee FL |
1676 | rd->len_left = rd->len; |
1677 | /* read header first for unknow frame length */ | |
38b0b0dd | 1678 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee | 1679 | if (!rd->len) { |
349e7104 | 1680 | ret = brcmf_sdcard_recv_buf(bus->sdiodev, |
4754fcee FL |
1681 | bus->sdiodev->sbwad, |
1682 | SDIO_FUNC_2, F2SYNC, | |
1683 | bus->rxhdr, | |
1684 | BRCMF_FIRSTREAD); | |
1685 | bus->sdcnt.f2rxhdrs++; | |
349e7104 | 1686 | if (ret < 0) { |
5e8149f5 | 1687 | brcmf_err("RXHEADER FAILED: %d\n", |
349e7104 | 1688 | ret); |
4754fcee FL |
1689 | bus->sdcnt.rx_hdrfail++; |
1690 | brcmf_sdbrcm_rxfail(bus, true, true); | |
38b0b0dd | 1691 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1692 | continue; |
5b435de0 | 1693 | } |
5b435de0 | 1694 | |
4754fcee | 1695 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), |
1e023829 JP |
1696 | bus->rxhdr, SDPCM_HDRLEN, |
1697 | "RxHdr:\n"); | |
5b435de0 | 1698 | |
6bc52319 FL |
1699 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, |
1700 | BRCMF_SDIO_FT_NORMAL)) { | |
38b0b0dd | 1701 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1702 | if (!bus->rxpending) |
1703 | break; | |
1704 | else | |
1705 | continue; | |
5b435de0 AS |
1706 | } |
1707 | ||
4754fcee FL |
1708 | if (rd->channel == SDPCM_CONTROL_CHANNEL) { |
1709 | brcmf_sdbrcm_read_control(bus, bus->rxhdr, | |
1710 | rd->len, | |
1711 | rd->dat_offset); | |
1712 | /* prepare the descriptor for the next read */ | |
1713 | rd->len = rd->len_nxtfrm << 4; | |
1714 | rd->len_nxtfrm = 0; | |
1715 | /* treat all packet as event if we don't know */ | |
1716 | rd->channel = SDPCM_EVENT_CHANNEL; | |
38b0b0dd | 1717 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1718 | continue; |
1719 | } | |
4754fcee FL |
1720 | rd->len_left = rd->len > BRCMF_FIRSTREAD ? |
1721 | rd->len - BRCMF_FIRSTREAD : 0; | |
1722 | head_read = BRCMF_FIRSTREAD; | |
5b435de0 AS |
1723 | } |
1724 | ||
4754fcee | 1725 | brcmf_pad(bus, &pad, &rd->len_left); |
5b435de0 | 1726 | |
4754fcee FL |
1727 | pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + |
1728 | BRCMF_SDALIGN); | |
5b435de0 AS |
1729 | if (!pkt) { |
1730 | /* Give up on data, request rtx of events */ | |
5e8149f5 | 1731 | brcmf_err("brcmu_pkt_buf_get_skb failed\n"); |
4754fcee FL |
1732 | brcmf_sdbrcm_rxfail(bus, false, |
1733 | RETRYCHAN(rd->channel)); | |
38b0b0dd | 1734 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1735 | continue; |
1736 | } | |
4754fcee FL |
1737 | skb_pull(pkt, head_read); |
1738 | pkt_align(pkt, rd->len_left, BRCMF_SDALIGN); | |
5b435de0 | 1739 | |
349e7104 | 1740 | ret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad, |
5adfeb63 | 1741 | SDIO_FUNC_2, F2SYNC, pkt); |
80969836 | 1742 | bus->sdcnt.f2rxdata++; |
38b0b0dd | 1743 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1744 | |
349e7104 | 1745 | if (ret < 0) { |
5e8149f5 | 1746 | brcmf_err("read %d bytes from channel %d failed: %d\n", |
349e7104 | 1747 | rd->len, rd->channel, ret); |
5b435de0 | 1748 | brcmu_pkt_buf_free_skb(pkt); |
38b0b0dd | 1749 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee FL |
1750 | brcmf_sdbrcm_rxfail(bus, true, |
1751 | RETRYCHAN(rd->channel)); | |
38b0b0dd | 1752 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
1753 | continue; |
1754 | } | |
1755 | ||
4754fcee FL |
1756 | if (head_read) { |
1757 | skb_push(pkt, head_read); | |
1758 | memcpy(pkt->data, bus->rxhdr, head_read); | |
1759 | head_read = 0; | |
1760 | } else { | |
1761 | memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); | |
1762 | rd_new.seq_num = rd->seq_num; | |
38b0b0dd | 1763 | sdio_claim_host(bus->sdiodev->func[1]); |
6bc52319 FL |
1764 | if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, |
1765 | BRCMF_SDIO_FT_NORMAL)) { | |
4754fcee FL |
1766 | rd->len = 0; |
1767 | brcmu_pkt_buf_free_skb(pkt); | |
1768 | } | |
1769 | bus->sdcnt.rx_readahead_cnt++; | |
1770 | if (rd->len != roundup(rd_new.len, 16)) { | |
5e8149f5 | 1771 | brcmf_err("frame length mismatch:read %d, should be %d\n", |
4754fcee FL |
1772 | rd->len, |
1773 | roundup(rd_new.len, 16) >> 4); | |
1774 | rd->len = 0; | |
1775 | brcmf_sdbrcm_rxfail(bus, true, true); | |
38b0b0dd | 1776 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1777 | brcmu_pkt_buf_free_skb(pkt); |
1778 | continue; | |
1779 | } | |
38b0b0dd | 1780 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1781 | rd->len_nxtfrm = rd_new.len_nxtfrm; |
1782 | rd->channel = rd_new.channel; | |
1783 | rd->dat_offset = rd_new.dat_offset; | |
1784 | ||
1785 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && | |
1786 | BRCMF_DATA_ON()) && | |
1787 | BRCMF_HDRS_ON(), | |
1788 | bus->rxhdr, SDPCM_HDRLEN, | |
1789 | "RxHdr:\n"); | |
1790 | ||
1791 | if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { | |
5e8149f5 | 1792 | brcmf_err("readahead on control packet %d?\n", |
4754fcee FL |
1793 | rd_new.seq_num); |
1794 | /* Force retry w/normal header read */ | |
1795 | rd->len = 0; | |
38b0b0dd | 1796 | sdio_claim_host(bus->sdiodev->func[1]); |
4754fcee | 1797 | brcmf_sdbrcm_rxfail(bus, false, true); |
38b0b0dd | 1798 | sdio_release_host(bus->sdiodev->func[1]); |
4754fcee FL |
1799 | brcmu_pkt_buf_free_skb(pkt); |
1800 | continue; | |
1801 | } | |
1802 | } | |
5b435de0 | 1803 | |
1e023829 | 1804 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), |
4754fcee | 1805 | pkt->data, rd->len, "Rx Data:\n"); |
5b435de0 | 1806 | |
5b435de0 | 1807 | /* Save superframe descriptor and allocate packet frame */ |
4754fcee | 1808 | if (rd->channel == SDPCM_GLOM_CHANNEL) { |
6bc52319 | 1809 | if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { |
5b435de0 | 1810 | brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", |
4754fcee | 1811 | rd->len); |
1e023829 | 1812 | brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), |
4754fcee | 1813 | pkt->data, rd->len, |
1e023829 | 1814 | "Glom Data:\n"); |
4754fcee | 1815 | __skb_trim(pkt, rd->len); |
5b435de0 AS |
1816 | skb_pull(pkt, SDPCM_HDRLEN); |
1817 | bus->glomd = pkt; | |
1818 | } else { | |
5e8149f5 | 1819 | brcmf_err("%s: glom superframe w/o " |
5b435de0 | 1820 | "descriptor!\n", __func__); |
38b0b0dd | 1821 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 1822 | brcmf_sdbrcm_rxfail(bus, false, false); |
38b0b0dd | 1823 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 1824 | } |
4754fcee FL |
1825 | /* prepare the descriptor for the next read */ |
1826 | rd->len = rd->len_nxtfrm << 4; | |
1827 | rd->len_nxtfrm = 0; | |
1828 | /* treat all packet as event if we don't know */ | |
1829 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
1830 | continue; |
1831 | } | |
1832 | ||
1833 | /* Fill in packet len and prio, deliver upward */ | |
4754fcee FL |
1834 | __skb_trim(pkt, rd->len); |
1835 | skb_pull(pkt, rd->dat_offset); | |
1836 | ||
1837 | /* prepare the descriptor for the next read */ | |
1838 | rd->len = rd->len_nxtfrm << 4; | |
1839 | rd->len_nxtfrm = 0; | |
1840 | /* treat all packet as event if we don't know */ | |
1841 | rd->channel = SDPCM_EVENT_CHANNEL; | |
5b435de0 AS |
1842 | |
1843 | if (pkt->len == 0) { | |
1844 | brcmu_pkt_buf_free_skb(pkt); | |
1845 | continue; | |
5b435de0 AS |
1846 | } |
1847 | ||
3aa7aad2 AS |
1848 | skb_queue_head_init(&pktlist); |
1849 | skb_queue_tail(&pktlist, pkt); | |
a43af515 | 1850 | brcmf_rx_frames(bus->sdiodev->dev, &pktlist); |
5b435de0 | 1851 | } |
4754fcee | 1852 | |
5b435de0 | 1853 | rxcount = maxframes - rxleft; |
5b435de0 AS |
1854 | /* Message if we hit the limit */ |
1855 | if (!rxleft) | |
4754fcee | 1856 | brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); |
5b435de0 | 1857 | else |
5b435de0 AS |
1858 | brcmf_dbg(DATA, "processed %d frames\n", rxcount); |
1859 | /* Back off rxseq if awaiting rtx, update rx_seq */ | |
1860 | if (bus->rxskip) | |
4754fcee FL |
1861 | rd->seq_num--; |
1862 | bus->rx_seq = rd->seq_num; | |
5b435de0 AS |
1863 | |
1864 | return rxcount; | |
1865 | } | |
1866 | ||
5b435de0 | 1867 | static void |
e92eedf4 | 1868 | brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus) |
5b435de0 AS |
1869 | { |
1870 | if (waitqueue_active(&bus->ctrl_wait)) | |
1871 | wake_up_interruptible(&bus->ctrl_wait); | |
1872 | return; | |
1873 | } | |
1874 | ||
5491c11c FL |
1875 | /** |
1876 | * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for | |
1877 | * bus layer usage. | |
1878 | */ | |
b05e9254 | 1879 | /* flag marking a dummy skb added for DMA alignment requirement */ |
5491c11c | 1880 | #define ALIGN_SKB_FLAG 0x8000 |
b05e9254 | 1881 | /* bit mask of data length chopped from the previous packet */ |
5491c11c FL |
1882 | #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff |
1883 | ||
b05e9254 FL |
1884 | /** |
1885 | * brcmf_sdio_txpkt_prep - packet preparation for transmit | |
1886 | * @bus: brcmf_sdio structure pointer | |
1887 | * @pktq: packet list pointer | |
1888 | * @chan: virtual channel to transmit the packet | |
1889 | * | |
1890 | * Processes to be applied to the packet | |
1891 | * - Align data buffer pointer | |
1892 | * - Align data buffer length | |
1893 | * - Prepare header | |
1894 | * Return: negative value if there is error | |
1895 | */ | |
1896 | static int | |
1897 | brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, | |
1898 | uint chan) | |
5b435de0 | 1899 | { |
6bc52319 | 1900 | u16 head_pad, tail_pad, tail_chop, head_align, sg_align; |
b05e9254 FL |
1901 | int ntail; |
1902 | struct sk_buff *pkt_next, *pkt_new; | |
1903 | u8 *dat_buf; | |
1904 | unsigned blksize = bus->sdiodev->func[SDIO_FUNC_2]->cur_blksize; | |
6bc52319 | 1905 | struct brcmf_sdio_hdrinfo hd_info = {0}; |
b05e9254 FL |
1906 | |
1907 | /* SDIO ADMA requires at least 32 bit alignment */ | |
1908 | head_align = 4; | |
1909 | sg_align = 4; | |
1910 | if (bus->sdiodev->pdata) { | |
1911 | head_align = bus->sdiodev->pdata->sd_head_align > 4 ? | |
1912 | bus->sdiodev->pdata->sd_head_align : 4; | |
1913 | sg_align = bus->sdiodev->pdata->sd_sgentry_align > 4 ? | |
1914 | bus->sdiodev->pdata->sd_sgentry_align : 4; | |
1915 | } | |
1916 | /* sg entry alignment should be a divisor of block size */ | |
1917 | WARN_ON(blksize % sg_align); | |
5b435de0 | 1918 | |
b05e9254 FL |
1919 | pkt_next = pktq->next; |
1920 | dat_buf = (u8 *)(pkt_next->data); | |
5b435de0 | 1921 | |
b05e9254 FL |
1922 | /* Check head padding */ |
1923 | head_pad = ((unsigned long)dat_buf % head_align); | |
1924 | if (head_pad) { | |
1925 | if (skb_headroom(pkt_next) < head_pad) { | |
9c1a043a | 1926 | bus->sdiodev->bus_if->tx_realloc++; |
b05e9254 FL |
1927 | head_pad = 0; |
1928 | if (skb_cow(pkt_next, head_pad)) | |
1929 | return -ENOMEM; | |
5b435de0 | 1930 | } |
b05e9254 FL |
1931 | skb_push(pkt_next, head_pad); |
1932 | dat_buf = (u8 *)(pkt_next->data); | |
706478cb | 1933 | memset(dat_buf, 0, head_pad + bus->tx_hdrlen); |
5b435de0 | 1934 | } |
5b435de0 | 1935 | |
b05e9254 FL |
1936 | /* Check tail padding */ |
1937 | pkt_new = NULL; | |
1938 | tail_chop = pkt_next->len % sg_align; | |
1939 | tail_pad = sg_align - tail_chop; | |
1940 | tail_pad += blksize - (pkt_next->len + tail_pad) % blksize; | |
1941 | if (skb_tailroom(pkt_next) < tail_pad && pkt_next->len > blksize) { | |
1942 | pkt_new = brcmu_pkt_buf_get_skb(tail_pad + tail_chop); | |
1943 | if (pkt_new == NULL) | |
1944 | return -ENOMEM; | |
1945 | memcpy(pkt_new->data, | |
1946 | pkt_next->data + pkt_next->len - tail_chop, | |
1947 | tail_chop); | |
5491c11c | 1948 | *(u32 *)(pkt_new->cb) = ALIGN_SKB_FLAG + tail_chop; |
b05e9254 FL |
1949 | skb_trim(pkt_next, pkt_next->len - tail_chop); |
1950 | __skb_queue_after(pktq, pkt_next, pkt_new); | |
1951 | } else { | |
1952 | ntail = pkt_next->data_len + tail_pad - | |
1953 | (pkt_next->end - pkt_next->tail); | |
1954 | if (skb_cloned(pkt_next) || ntail > 0) | |
1955 | if (pskb_expand_head(pkt_next, 0, ntail, GFP_ATOMIC)) | |
1956 | return -ENOMEM; | |
1957 | if (skb_linearize(pkt_next)) | |
1958 | return -ENOMEM; | |
1959 | dat_buf = (u8 *)(pkt_next->data); | |
1960 | __skb_put(pkt_next, tail_pad); | |
1961 | } | |
5b435de0 | 1962 | |
b05e9254 | 1963 | /* Now prep the header */ |
b05e9254 | 1964 | if (pkt_new) |
6bc52319 | 1965 | hd_info.len = pkt_next->len + tail_chop; |
b05e9254 | 1966 | else |
6bc52319 FL |
1967 | hd_info.len = pkt_next->len - tail_pad; |
1968 | hd_info.channel = chan; | |
706478cb | 1969 | hd_info.dat_offset = head_pad + bus->tx_hdrlen; |
6bc52319 | 1970 | brcmf_sdio_hdpack(bus, dat_buf, &hd_info); |
b05e9254 FL |
1971 | |
1972 | if (BRCMF_BYTES_ON() && | |
1973 | ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || | |
1974 | (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) | |
6bc52319 | 1975 | brcmf_dbg_hex_dump(true, pkt_next, hd_info.len, "Tx Frame:\n"); |
b05e9254 | 1976 | else if (BRCMF_HDRS_ON()) |
706478cb | 1977 | brcmf_dbg_hex_dump(true, pkt_next, head_pad + bus->tx_hdrlen, |
b05e9254 | 1978 | "Tx Header:\n"); |
5b435de0 | 1979 | |
b05e9254 FL |
1980 | return 0; |
1981 | } | |
5b435de0 | 1982 | |
b05e9254 FL |
1983 | /** |
1984 | * brcmf_sdio_txpkt_postp - packet post processing for transmit | |
1985 | * @bus: brcmf_sdio structure pointer | |
1986 | * @pktq: packet list pointer | |
1987 | * | |
1988 | * Processes to be applied to the packet | |
1989 | * - Remove head padding | |
1990 | * - Remove tail padding | |
1991 | */ | |
1992 | static void | |
1993 | brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) | |
1994 | { | |
1995 | u8 *hdr; | |
1996 | u32 dat_offset; | |
1997 | u32 dummy_flags, chop_len; | |
1998 | struct sk_buff *pkt_next, *tmp, *pkt_prev; | |
1999 | ||
2000 | skb_queue_walk_safe(pktq, pkt_next, tmp) { | |
2001 | dummy_flags = *(u32 *)(pkt_next->cb); | |
5491c11c FL |
2002 | if (dummy_flags & ALIGN_SKB_FLAG) { |
2003 | chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; | |
b05e9254 FL |
2004 | if (chop_len) { |
2005 | pkt_prev = pkt_next->prev; | |
2006 | memcpy(pkt_prev->data + pkt_prev->len, | |
2007 | pkt_next->data, chop_len); | |
2008 | skb_put(pkt_prev, chop_len); | |
2009 | } | |
2010 | __skb_unlink(pkt_next, pktq); | |
2011 | brcmu_pkt_buf_free_skb(pkt_next); | |
2012 | } else { | |
6bc52319 | 2013 | hdr = pkt_next->data + SDPCM_HWHDR_LEN; |
b05e9254 FL |
2014 | dat_offset = le32_to_cpu(*(__le32 *)hdr); |
2015 | dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> | |
2016 | SDPCM_DOFFSET_SHIFT; | |
2017 | skb_pull(pkt_next, dat_offset); | |
2018 | } | |
5b435de0 | 2019 | } |
b05e9254 | 2020 | } |
5b435de0 | 2021 | |
b05e9254 FL |
2022 | /* Writes a HW/SW header into the packet and sends it. */ |
2023 | /* Assumes: (a) header space already there, (b) caller holds lock */ | |
2024 | static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt, | |
2025 | uint chan) | |
2026 | { | |
2027 | int ret; | |
2028 | int i; | |
2029 | struct sk_buff_head localq; | |
2030 | ||
2031 | brcmf_dbg(TRACE, "Enter\n"); | |
2032 | ||
2033 | __skb_queue_head_init(&localq); | |
2034 | __skb_queue_tail(&localq, pkt); | |
2035 | ret = brcmf_sdio_txpkt_prep(bus, &localq, chan); | |
2036 | if (ret) | |
2037 | goto done; | |
5b435de0 | 2038 | |
38b0b0dd | 2039 | sdio_claim_host(bus->sdiodev->func[1]); |
5adfeb63 | 2040 | ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad, |
b05e9254 | 2041 | SDIO_FUNC_2, F2SYNC, &localq); |
80969836 | 2042 | bus->sdcnt.f2txdata++; |
5b435de0 AS |
2043 | |
2044 | if (ret < 0) { | |
2045 | /* On failure, abort the command and terminate the frame */ | |
2046 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2047 | ret); | |
80969836 | 2048 | bus->sdcnt.tx_sderrs++; |
5b435de0 AS |
2049 | |
2050 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
3bba829f FL |
2051 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
2052 | SFC_WF_TERM, NULL); | |
80969836 | 2053 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
2054 | |
2055 | for (i = 0; i < 3; i++) { | |
2056 | u8 hi, lo; | |
45db339c FL |
2057 | hi = brcmf_sdio_regrb(bus->sdiodev, |
2058 | SBSDIO_FUNC1_WFRAMEBCHI, NULL); | |
2059 | lo = brcmf_sdio_regrb(bus->sdiodev, | |
2060 | SBSDIO_FUNC1_WFRAMEBCLO, NULL); | |
80969836 | 2061 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
2062 | if ((hi == 0) && (lo == 0)) |
2063 | break; | |
2064 | } | |
2065 | ||
2066 | } | |
38b0b0dd | 2067 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 2068 | if (ret == 0) |
6bc52319 | 2069 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; |
5b435de0 AS |
2070 | |
2071 | done: | |
b05e9254 FL |
2072 | brcmf_sdio_txpkt_postp(bus, &localq); |
2073 | __skb_dequeue_tail(&localq); | |
a886f7f4 | 2074 | brcmf_txcomplete(bus->sdiodev->dev, pkt, ret == 0); |
5b435de0 AS |
2075 | return ret; |
2076 | } | |
2077 | ||
e92eedf4 | 2078 | static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes) |
5b435de0 AS |
2079 | { |
2080 | struct sk_buff *pkt; | |
2081 | u32 intstatus = 0; | |
5b435de0 AS |
2082 | int ret = 0, prec_out; |
2083 | uint cnt = 0; | |
5b435de0 AS |
2084 | u8 tx_prec_map; |
2085 | ||
5b435de0 AS |
2086 | brcmf_dbg(TRACE, "Enter\n"); |
2087 | ||
2088 | tx_prec_map = ~bus->flowcontrol; | |
2089 | ||
2090 | /* Send frames until the limit or some other event */ | |
2091 | for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) { | |
2092 | spin_lock_bh(&bus->txqlock); | |
2093 | pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out); | |
2094 | if (pkt == NULL) { | |
2095 | spin_unlock_bh(&bus->txqlock); | |
2096 | break; | |
2097 | } | |
2098 | spin_unlock_bh(&bus->txqlock); | |
5b435de0 | 2099 | |
7f4bceec | 2100 | ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL); |
5b435de0 AS |
2101 | |
2102 | /* In poll mode, need to check for other events */ | |
2103 | if (!bus->intr && cnt) { | |
2104 | /* Check device status, signal pending interrupt */ | |
38b0b0dd | 2105 | sdio_claim_host(bus->sdiodev->func[1]); |
5c15c23a FL |
2106 | ret = r_sdreg32(bus, &intstatus, |
2107 | offsetof(struct sdpcmd_regs, | |
2108 | intstatus)); | |
38b0b0dd | 2109 | sdio_release_host(bus->sdiodev->func[1]); |
80969836 | 2110 | bus->sdcnt.f2txdata++; |
5c15c23a | 2111 | if (ret != 0) |
5b435de0 AS |
2112 | break; |
2113 | if (intstatus & bus->hostintmask) | |
1d382273 | 2114 | atomic_set(&bus->ipend, 1); |
5b435de0 AS |
2115 | } |
2116 | } | |
2117 | ||
2118 | /* Deflow-control stack if needed */ | |
05dde977 | 2119 | if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) && |
c8bf3484 | 2120 | bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { |
90d03ff7 HM |
2121 | bus->txoff = false; |
2122 | brcmf_txflowblock(bus->sdiodev->dev, false); | |
c8bf3484 | 2123 | } |
5b435de0 AS |
2124 | |
2125 | return cnt; | |
2126 | } | |
2127 | ||
a9ffda88 FL |
2128 | static void brcmf_sdbrcm_bus_stop(struct device *dev) |
2129 | { | |
2130 | u32 local_hostintmask; | |
2131 | u8 saveclk; | |
a9ffda88 FL |
2132 | int err; |
2133 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
0a332e46 | 2134 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
a9ffda88 FL |
2135 | struct brcmf_sdio *bus = sdiodev->bus; |
2136 | ||
2137 | brcmf_dbg(TRACE, "Enter\n"); | |
2138 | ||
2139 | if (bus->watchdog_tsk) { | |
2140 | send_sig(SIGTERM, bus->watchdog_tsk, 1); | |
2141 | kthread_stop(bus->watchdog_tsk); | |
2142 | bus->watchdog_tsk = NULL; | |
2143 | } | |
2144 | ||
38b0b0dd | 2145 | sdio_claim_host(bus->sdiodev->func[1]); |
a9ffda88 | 2146 | |
a9ffda88 | 2147 | /* Enable clock for device interrupts */ |
4a3da990 | 2148 | brcmf_sdbrcm_bus_sleep(bus, false, false); |
a9ffda88 FL |
2149 | |
2150 | /* Disable and clear interrupts at the chip level also */ | |
58692750 | 2151 | w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask)); |
a9ffda88 FL |
2152 | local_hostintmask = bus->hostintmask; |
2153 | bus->hostintmask = 0; | |
2154 | ||
2155 | /* Change our idea of bus state */ | |
2156 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; | |
2157 | ||
2158 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
45db339c FL |
2159 | saveclk = brcmf_sdio_regrb(bus->sdiodev, |
2160 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
a9ffda88 | 2161 | if (!err) { |
3bba829f FL |
2162 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
2163 | (saveclk | SBSDIO_FORCE_HT), &err); | |
a9ffda88 FL |
2164 | } |
2165 | if (err) | |
5e8149f5 | 2166 | brcmf_err("Failed to force clock for F2: err %d\n", err); |
a9ffda88 FL |
2167 | |
2168 | /* Turn off the bus (F2), free any pending packets */ | |
2169 | brcmf_dbg(INTR, "disable SDIO interrupts\n"); | |
3bba829f FL |
2170 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1, |
2171 | NULL); | |
a9ffda88 FL |
2172 | |
2173 | /* Clear any pending interrupts now that F2 is disabled */ | |
2174 | w_sdreg32(bus, local_hostintmask, | |
58692750 | 2175 | offsetof(struct sdpcmd_regs, intstatus)); |
a9ffda88 FL |
2176 | |
2177 | /* Turn off the backplane clock (only) */ | |
2178 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
38b0b0dd | 2179 | sdio_release_host(bus->sdiodev->func[1]); |
a9ffda88 FL |
2180 | |
2181 | /* Clear the data packet queues */ | |
2182 | brcmu_pktq_flush(&bus->txq, true, NULL, NULL); | |
2183 | ||
2184 | /* Clear any held glomming stuff */ | |
2185 | if (bus->glomd) | |
2186 | brcmu_pkt_buf_free_skb(bus->glomd); | |
2187 | brcmf_sdbrcm_free_glom(bus); | |
2188 | ||
2189 | /* Clear rx control and wake any waiters */ | |
dd43a01c | 2190 | spin_lock_bh(&bus->rxctl_lock); |
a9ffda88 | 2191 | bus->rxlen = 0; |
dd43a01c | 2192 | spin_unlock_bh(&bus->rxctl_lock); |
a9ffda88 FL |
2193 | brcmf_sdbrcm_dcmd_resp_wake(bus); |
2194 | ||
2195 | /* Reset some F2 state stuff */ | |
2196 | bus->rxskip = false; | |
2197 | bus->tx_seq = bus->rx_seq = 0; | |
a9ffda88 FL |
2198 | } |
2199 | ||
ba89bf19 FL |
2200 | static inline void brcmf_sdbrcm_clrintr(struct brcmf_sdio *bus) |
2201 | { | |
2202 | unsigned long flags; | |
2203 | ||
668761ac HM |
2204 | if (bus->sdiodev->oob_irq_requested) { |
2205 | spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags); | |
2206 | if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) { | |
2207 | enable_irq(bus->sdiodev->pdata->oob_irq_nr); | |
2208 | bus->sdiodev->irq_en = true; | |
2209 | } | |
2210 | spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags); | |
ba89bf19 | 2211 | } |
ba89bf19 | 2212 | } |
ba89bf19 | 2213 | |
4531603a FL |
2214 | static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) |
2215 | { | |
2216 | u8 idx; | |
2217 | u32 addr; | |
2218 | unsigned long val; | |
2219 | int n, ret; | |
2220 | ||
2221 | idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); | |
2222 | addr = bus->ci->c_inf[idx].base + | |
2223 | offsetof(struct sdpcmd_regs, intstatus); | |
2224 | ||
2225 | ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, false); | |
2226 | bus->sdcnt.f1regdata++; | |
2227 | if (ret != 0) | |
2228 | val = 0; | |
2229 | ||
2230 | val &= bus->hostintmask; | |
2231 | atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); | |
2232 | ||
2233 | /* Clear interrupts */ | |
2234 | if (val) { | |
2235 | ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, true); | |
2236 | bus->sdcnt.f1regdata++; | |
2237 | } | |
2238 | ||
2239 | if (ret) { | |
2240 | atomic_set(&bus->intstatus, 0); | |
2241 | } else if (val) { | |
2242 | for_each_set_bit(n, &val, 32) | |
2243 | set_bit(n, (unsigned long *)&bus->intstatus.counter); | |
2244 | } | |
2245 | ||
2246 | return ret; | |
2247 | } | |
2248 | ||
f1e68c2e | 2249 | static void brcmf_sdbrcm_dpc(struct brcmf_sdio *bus) |
5b435de0 | 2250 | { |
4531603a FL |
2251 | u32 newstatus = 0; |
2252 | unsigned long intstatus; | |
5b435de0 AS |
2253 | uint rxlimit = bus->rxbound; /* Rx frames to read before resched */ |
2254 | uint txlimit = bus->txbound; /* Tx frames to send before resched */ | |
2255 | uint framecnt = 0; /* Temporary counter of tx/rx frames */ | |
4531603a | 2256 | int err = 0, n; |
5b435de0 AS |
2257 | |
2258 | brcmf_dbg(TRACE, "Enter\n"); | |
2259 | ||
38b0b0dd | 2260 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2261 | |
2262 | /* If waiting for HTAVAIL, check status */ | |
4a3da990 | 2263 | if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { |
5b435de0 AS |
2264 | u8 clkctl, devctl = 0; |
2265 | ||
8ae74654 | 2266 | #ifdef DEBUG |
5b435de0 | 2267 | /* Check for inconsistent device control */ |
45db339c FL |
2268 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
2269 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 2270 | if (err) { |
5e8149f5 | 2271 | brcmf_err("error reading DEVCTL: %d\n", err); |
712ac5b3 | 2272 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 | 2273 | } |
8ae74654 | 2274 | #endif /* DEBUG */ |
5b435de0 AS |
2275 | |
2276 | /* Read CSR, if clock on switch to AVAIL, else ignore */ | |
45db339c FL |
2277 | clkctl = brcmf_sdio_regrb(bus->sdiodev, |
2278 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 2279 | if (err) { |
5e8149f5 | 2280 | brcmf_err("error reading CSR: %d\n", |
5b435de0 | 2281 | err); |
712ac5b3 | 2282 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2283 | } |
2284 | ||
c3203374 | 2285 | brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", |
5b435de0 AS |
2286 | devctl, clkctl); |
2287 | ||
2288 | if (SBSDIO_HTAV(clkctl)) { | |
45db339c FL |
2289 | devctl = brcmf_sdio_regrb(bus->sdiodev, |
2290 | SBSDIO_DEVICE_CTL, &err); | |
5b435de0 | 2291 | if (err) { |
5e8149f5 | 2292 | brcmf_err("error reading DEVCTL: %d\n", |
5b435de0 | 2293 | err); |
712ac5b3 | 2294 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2295 | } |
2296 | devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; | |
3bba829f FL |
2297 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, |
2298 | devctl, &err); | |
5b435de0 | 2299 | if (err) { |
5e8149f5 | 2300 | brcmf_err("error writing DEVCTL: %d\n", |
5b435de0 | 2301 | err); |
712ac5b3 | 2302 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
2303 | } |
2304 | bus->clkstate = CLK_AVAIL; | |
5b435de0 AS |
2305 | } |
2306 | } | |
2307 | ||
5b435de0 | 2308 | /* Make sure backplane clock is on */ |
4a3da990 | 2309 | brcmf_sdbrcm_bus_sleep(bus, false, true); |
5b435de0 AS |
2310 | |
2311 | /* Pending interrupt indicates new device status */ | |
1d382273 FL |
2312 | if (atomic_read(&bus->ipend) > 0) { |
2313 | atomic_set(&bus->ipend, 0); | |
4531603a | 2314 | err = brcmf_sdio_intr_rstatus(bus); |
5b435de0 AS |
2315 | } |
2316 | ||
4531603a FL |
2317 | /* Start with leftover status bits */ |
2318 | intstatus = atomic_xchg(&bus->intstatus, 0); | |
5b435de0 AS |
2319 | |
2320 | /* Handle flow-control change: read new state in case our ack | |
2321 | * crossed another change interrupt. If change still set, assume | |
2322 | * FC ON for safety, let next loop through do the debounce. | |
2323 | */ | |
2324 | if (intstatus & I_HMB_FC_CHANGE) { | |
2325 | intstatus &= ~I_HMB_FC_CHANGE; | |
5c15c23a FL |
2326 | err = w_sdreg32(bus, I_HMB_FC_CHANGE, |
2327 | offsetof(struct sdpcmd_regs, intstatus)); | |
5b435de0 | 2328 | |
5c15c23a FL |
2329 | err = r_sdreg32(bus, &newstatus, |
2330 | offsetof(struct sdpcmd_regs, intstatus)); | |
80969836 | 2331 | bus->sdcnt.f1regdata += 2; |
4531603a FL |
2332 | atomic_set(&bus->fcstate, |
2333 | !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); | |
5b435de0 AS |
2334 | intstatus |= (newstatus & bus->hostintmask); |
2335 | } | |
2336 | ||
2337 | /* Handle host mailbox indication */ | |
2338 | if (intstatus & I_HMB_HOST_INT) { | |
2339 | intstatus &= ~I_HMB_HOST_INT; | |
2340 | intstatus |= brcmf_sdbrcm_hostmail(bus); | |
2341 | } | |
2342 | ||
38b0b0dd | 2343 | sdio_release_host(bus->sdiodev->func[1]); |
7cdf57d3 | 2344 | |
5b435de0 AS |
2345 | /* Generally don't ask for these, can get CRC errors... */ |
2346 | if (intstatus & I_WR_OOSYNC) { | |
5e8149f5 | 2347 | brcmf_err("Dongle reports WR_OOSYNC\n"); |
5b435de0 AS |
2348 | intstatus &= ~I_WR_OOSYNC; |
2349 | } | |
2350 | ||
2351 | if (intstatus & I_RD_OOSYNC) { | |
5e8149f5 | 2352 | brcmf_err("Dongle reports RD_OOSYNC\n"); |
5b435de0 AS |
2353 | intstatus &= ~I_RD_OOSYNC; |
2354 | } | |
2355 | ||
2356 | if (intstatus & I_SBINT) { | |
5e8149f5 | 2357 | brcmf_err("Dongle reports SBINT\n"); |
5b435de0 AS |
2358 | intstatus &= ~I_SBINT; |
2359 | } | |
2360 | ||
2361 | /* Would be active due to wake-wlan in gSPI */ | |
2362 | if (intstatus & I_CHIPACTIVE) { | |
2363 | brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); | |
2364 | intstatus &= ~I_CHIPACTIVE; | |
2365 | } | |
2366 | ||
2367 | /* Ignore frame indications if rxskip is set */ | |
2368 | if (bus->rxskip) | |
2369 | intstatus &= ~I_HMB_FRAME_IND; | |
2370 | ||
2371 | /* On frame indication, read available frames */ | |
03d5c360 | 2372 | if (PKT_AVAILABLE() && bus->clkstate == CLK_AVAIL) { |
4754fcee FL |
2373 | framecnt = brcmf_sdio_readframes(bus, rxlimit); |
2374 | if (!bus->rxpending) | |
5b435de0 AS |
2375 | intstatus &= ~I_HMB_FRAME_IND; |
2376 | rxlimit -= min(framecnt, rxlimit); | |
2377 | } | |
2378 | ||
2379 | /* Keep still-pending events for next scheduling */ | |
4531603a FL |
2380 | if (intstatus) { |
2381 | for_each_set_bit(n, &intstatus, 32) | |
2382 | set_bit(n, (unsigned long *)&bus->intstatus.counter); | |
2383 | } | |
5b435de0 | 2384 | |
ba89bf19 FL |
2385 | brcmf_sdbrcm_clrintr(bus); |
2386 | ||
5b435de0 AS |
2387 | if (data_ok(bus) && bus->ctrl_frame_stat && |
2388 | (bus->clkstate == CLK_AVAIL)) { | |
03d5c360 | 2389 | int i; |
5b435de0 | 2390 | |
38b0b0dd | 2391 | sdio_claim_host(bus->sdiodev->func[1]); |
03d5c360 | 2392 | err = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad, |
2c208890 | 2393 | SDIO_FUNC_2, F2SYNC, bus->ctrl_frame_buf, |
5adfeb63 | 2394 | (u32) bus->ctrl_frame_len); |
5b435de0 | 2395 | |
03d5c360 | 2396 | if (err < 0) { |
5b435de0 AS |
2397 | /* On failure, abort the command and |
2398 | terminate the frame */ | |
2399 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
03d5c360 | 2400 | err); |
80969836 | 2401 | bus->sdcnt.tx_sderrs++; |
5b435de0 AS |
2402 | |
2403 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2404 | ||
3bba829f | 2405 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
5c15c23a | 2406 | SFC_WF_TERM, &err); |
80969836 | 2407 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
2408 | |
2409 | for (i = 0; i < 3; i++) { | |
2410 | u8 hi, lo; | |
45db339c FL |
2411 | hi = brcmf_sdio_regrb(bus->sdiodev, |
2412 | SBSDIO_FUNC1_WFRAMEBCHI, | |
5c15c23a | 2413 | &err); |
45db339c FL |
2414 | lo = brcmf_sdio_regrb(bus->sdiodev, |
2415 | SBSDIO_FUNC1_WFRAMEBCLO, | |
5c15c23a | 2416 | &err); |
80969836 | 2417 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
2418 | if ((hi == 0) && (lo == 0)) |
2419 | break; | |
2420 | } | |
2421 | ||
03d5c360 | 2422 | } else { |
6bc52319 | 2423 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; |
03d5c360 | 2424 | } |
38b0b0dd | 2425 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2426 | bus->ctrl_frame_stat = false; |
2427 | brcmf_sdbrcm_wait_event_wakeup(bus); | |
2428 | } | |
2429 | /* Send queued frames (limit 1 if rx may still be pending) */ | |
4531603a | 2430 | else if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && |
5b435de0 AS |
2431 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit |
2432 | && data_ok(bus)) { | |
4754fcee FL |
2433 | framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : |
2434 | txlimit; | |
5b435de0 AS |
2435 | framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt); |
2436 | txlimit -= framecnt; | |
2437 | } | |
2438 | ||
5c15c23a | 2439 | if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) || (err != 0)) { |
5e8149f5 | 2440 | brcmf_err("failed backplane access over SDIO, halting operation\n"); |
712ac5b3 | 2441 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
4531603a FL |
2442 | atomic_set(&bus->intstatus, 0); |
2443 | } else if (atomic_read(&bus->intstatus) || | |
2444 | atomic_read(&bus->ipend) > 0 || | |
2445 | (!atomic_read(&bus->fcstate) && | |
2446 | brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && | |
2447 | data_ok(bus)) || PKT_AVAILABLE()) { | |
fccfe930 | 2448 | atomic_inc(&bus->dpc_tskcnt); |
5b435de0 AS |
2449 | } |
2450 | ||
5b435de0 AS |
2451 | /* If we're done for now, turn off clock request. */ |
2452 | if ((bus->clkstate != CLK_PENDING) | |
2453 | && bus->idletime == BRCMF_IDLE_IMMEDIATE) { | |
2454 | bus->activity = false; | |
4a3da990 | 2455 | brcmf_dbg(SDIO, "idle state\n"); |
38b0b0dd | 2456 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 2457 | brcmf_sdbrcm_bus_sleep(bus, true, false); |
38b0b0dd | 2458 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 2459 | } |
5b435de0 AS |
2460 | } |
2461 | ||
e2432b67 AS |
2462 | static struct pktq *brcmf_sdbrcm_bus_gettxq(struct device *dev) |
2463 | { | |
2464 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); | |
2465 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; | |
2466 | struct brcmf_sdio *bus = sdiodev->bus; | |
2467 | ||
2468 | return &bus->txq; | |
2469 | } | |
2470 | ||
b9692d17 | 2471 | static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt) |
5b435de0 AS |
2472 | { |
2473 | int ret = -EBADE; | |
2474 | uint datalen, prec; | |
bf347bb9 | 2475 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2476 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
bf347bb9 | 2477 | struct brcmf_sdio *bus = sdiodev->bus; |
4061f895 | 2478 | ulong flags; |
5b435de0 AS |
2479 | |
2480 | brcmf_dbg(TRACE, "Enter\n"); | |
2481 | ||
2482 | datalen = pkt->len; | |
2483 | ||
2484 | /* Add space for the header */ | |
706478cb | 2485 | skb_push(pkt, bus->tx_hdrlen); |
5b435de0 AS |
2486 | /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ |
2487 | ||
2488 | prec = prio2prec((pkt->priority & PRIOMASK)); | |
2489 | ||
2490 | /* Check for existing queue, current flow-control, | |
2491 | pending event, or pending clock */ | |
2492 | brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); | |
80969836 | 2493 | bus->sdcnt.fcqueued++; |
5b435de0 AS |
2494 | |
2495 | /* Priority based enq */ | |
4061f895 | 2496 | spin_lock_irqsave(&bus->txqlock, flags); |
23677ce3 | 2497 | if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) { |
706478cb | 2498 | skb_pull(pkt, bus->tx_hdrlen); |
5e8149f5 | 2499 | brcmf_err("out of bus->txq !!!\n"); |
5b435de0 AS |
2500 | ret = -ENOSR; |
2501 | } else { | |
2502 | ret = 0; | |
2503 | } | |
5b435de0 | 2504 | |
c8bf3484 | 2505 | if (pktq_len(&bus->txq) >= TXHI) { |
90d03ff7 HM |
2506 | bus->txoff = true; |
2507 | brcmf_txflowblock(bus->sdiodev->dev, true); | |
c8bf3484 | 2508 | } |
4061f895 | 2509 | spin_unlock_irqrestore(&bus->txqlock, flags); |
5b435de0 | 2510 | |
8ae74654 | 2511 | #ifdef DEBUG |
5b435de0 AS |
2512 | if (pktq_plen(&bus->txq, prec) > qcount[prec]) |
2513 | qcount[prec] = pktq_plen(&bus->txq, prec); | |
2514 | #endif | |
f1e68c2e | 2515 | |
fccfe930 AS |
2516 | if (atomic_read(&bus->dpc_tskcnt) == 0) { |
2517 | atomic_inc(&bus->dpc_tskcnt); | |
f1e68c2e | 2518 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
2519 | } |
2520 | ||
2521 | return ret; | |
2522 | } | |
2523 | ||
8ae74654 | 2524 | #ifdef DEBUG |
5b435de0 AS |
2525 | #define CONSOLE_LINE_MAX 192 |
2526 | ||
e92eedf4 | 2527 | static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus) |
5b435de0 AS |
2528 | { |
2529 | struct brcmf_console *c = &bus->console; | |
2530 | u8 line[CONSOLE_LINE_MAX], ch; | |
2531 | u32 n, idx, addr; | |
2532 | int rv; | |
2533 | ||
2534 | /* Don't do anything until FWREADY updates console address */ | |
2535 | if (bus->console_addr == 0) | |
2536 | return 0; | |
2537 | ||
2538 | /* Read console log struct */ | |
2539 | addr = bus->console_addr + offsetof(struct rte_console, log_le); | |
ba540b01 FL |
2540 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, |
2541 | sizeof(c->log_le)); | |
5b435de0 AS |
2542 | if (rv < 0) |
2543 | return rv; | |
2544 | ||
2545 | /* Allocate console buffer (one time only) */ | |
2546 | if (c->buf == NULL) { | |
2547 | c->bufsize = le32_to_cpu(c->log_le.buf_size); | |
2548 | c->buf = kmalloc(c->bufsize, GFP_ATOMIC); | |
2549 | if (c->buf == NULL) | |
2550 | return -ENOMEM; | |
2551 | } | |
2552 | ||
2553 | idx = le32_to_cpu(c->log_le.idx); | |
2554 | ||
2555 | /* Protect against corrupt value */ | |
2556 | if (idx > c->bufsize) | |
2557 | return -EBADE; | |
2558 | ||
2559 | /* Skip reading the console buffer if the index pointer | |
2560 | has not moved */ | |
2561 | if (idx == c->last) | |
2562 | return 0; | |
2563 | ||
2564 | /* Read the console buffer */ | |
2565 | addr = le32_to_cpu(c->log_le.buf); | |
ba540b01 | 2566 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); |
5b435de0 AS |
2567 | if (rv < 0) |
2568 | return rv; | |
2569 | ||
2570 | while (c->last != idx) { | |
2571 | for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { | |
2572 | if (c->last == idx) { | |
2573 | /* This would output a partial line. | |
2574 | * Instead, back up | |
2575 | * the buffer pointer and output this | |
2576 | * line next time around. | |
2577 | */ | |
2578 | if (c->last >= n) | |
2579 | c->last -= n; | |
2580 | else | |
2581 | c->last = c->bufsize - n; | |
2582 | goto break2; | |
2583 | } | |
2584 | ch = c->buf[c->last]; | |
2585 | c->last = (c->last + 1) % c->bufsize; | |
2586 | if (ch == '\n') | |
2587 | break; | |
2588 | line[n] = ch; | |
2589 | } | |
2590 | ||
2591 | if (n > 0) { | |
2592 | if (line[n - 1] == '\r') | |
2593 | n--; | |
2594 | line[n] = 0; | |
18aad4f8 | 2595 | pr_debug("CONSOLE: %s\n", line); |
5b435de0 AS |
2596 | } |
2597 | } | |
2598 | break2: | |
2599 | ||
2600 | return 0; | |
2601 | } | |
8ae74654 | 2602 | #endif /* DEBUG */ |
5b435de0 | 2603 | |
e92eedf4 | 2604 | static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len) |
5b435de0 AS |
2605 | { |
2606 | int i; | |
2607 | int ret; | |
2608 | ||
2609 | bus->ctrl_frame_stat = false; | |
5adfeb63 AS |
2610 | ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad, |
2611 | SDIO_FUNC_2, F2SYNC, frame, len); | |
5b435de0 AS |
2612 | |
2613 | if (ret < 0) { | |
2614 | /* On failure, abort the command and terminate the frame */ | |
2615 | brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n", | |
2616 | ret); | |
80969836 | 2617 | bus->sdcnt.tx_sderrs++; |
5b435de0 AS |
2618 | |
2619 | brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2); | |
2620 | ||
3bba829f FL |
2621 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, |
2622 | SFC_WF_TERM, NULL); | |
80969836 | 2623 | bus->sdcnt.f1regdata++; |
5b435de0 AS |
2624 | |
2625 | for (i = 0; i < 3; i++) { | |
2626 | u8 hi, lo; | |
45db339c FL |
2627 | hi = brcmf_sdio_regrb(bus->sdiodev, |
2628 | SBSDIO_FUNC1_WFRAMEBCHI, NULL); | |
2629 | lo = brcmf_sdio_regrb(bus->sdiodev, | |
2630 | SBSDIO_FUNC1_WFRAMEBCLO, NULL); | |
80969836 | 2631 | bus->sdcnt.f1regdata += 2; |
5b435de0 AS |
2632 | if (hi == 0 && lo == 0) |
2633 | break; | |
2634 | } | |
2635 | return ret; | |
2636 | } | |
2637 | ||
6bc52319 | 2638 | bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; |
5b435de0 AS |
2639 | |
2640 | return ret; | |
2641 | } | |
2642 | ||
fcf094f4 | 2643 | static int |
47a1ce78 | 2644 | brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
2645 | { |
2646 | u8 *frame; | |
2647 | u16 len; | |
5b435de0 AS |
2648 | uint retries = 0; |
2649 | u8 doff = 0; | |
2650 | int ret = -1; | |
47a1ce78 | 2651 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 2652 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
47a1ce78 | 2653 | struct brcmf_sdio *bus = sdiodev->bus; |
6bc52319 | 2654 | struct brcmf_sdio_hdrinfo hd_info = {0}; |
5b435de0 AS |
2655 | |
2656 | brcmf_dbg(TRACE, "Enter\n"); | |
2657 | ||
2658 | /* Back the pointer to make a room for bus header */ | |
706478cb FL |
2659 | frame = msg - bus->tx_hdrlen; |
2660 | len = (msglen += bus->tx_hdrlen); | |
5b435de0 AS |
2661 | |
2662 | /* Add alignment padding (optional for ctl frames) */ | |
2663 | doff = ((unsigned long)frame % BRCMF_SDALIGN); | |
2664 | if (doff) { | |
2665 | frame -= doff; | |
2666 | len += doff; | |
2667 | msglen += doff; | |
706478cb | 2668 | memset(frame, 0, doff + bus->tx_hdrlen); |
5b435de0 AS |
2669 | } |
2670 | /* precondition: doff < BRCMF_SDALIGN */ | |
706478cb | 2671 | doff += bus->tx_hdrlen; |
5b435de0 AS |
2672 | |
2673 | /* Round send length to next SDIO block */ | |
2674 | if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { | |
2675 | u16 pad = bus->blocksize - (len % bus->blocksize); | |
2676 | if ((pad <= bus->roundup) && (pad < bus->blocksize)) | |
2677 | len += pad; | |
2678 | } else if (len % BRCMF_SDALIGN) { | |
2679 | len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN); | |
2680 | } | |
2681 | ||
2682 | /* Satisfy length-alignment requirements */ | |
2683 | if (len & (ALIGNMENT - 1)) | |
2684 | len = roundup(len, ALIGNMENT); | |
2685 | ||
2686 | /* precondition: IS_ALIGNED((unsigned long)frame, 2) */ | |
2687 | ||
5b435de0 | 2688 | /* Make sure backplane clock is on */ |
38b0b0dd | 2689 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 2690 | brcmf_sdbrcm_bus_sleep(bus, false, false); |
38b0b0dd | 2691 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 | 2692 | |
6bc52319 FL |
2693 | hd_info.len = (u16)msglen; |
2694 | hd_info.channel = SDPCM_CONTROL_CHANNEL; | |
2695 | hd_info.dat_offset = doff; | |
2696 | brcmf_sdio_hdpack(bus, frame, &hd_info); | |
5b435de0 AS |
2697 | |
2698 | if (!data_ok(bus)) { | |
2699 | brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n", | |
2700 | bus->tx_max, bus->tx_seq); | |
2701 | bus->ctrl_frame_stat = true; | |
2702 | /* Send from dpc */ | |
2703 | bus->ctrl_frame_buf = frame; | |
2704 | bus->ctrl_frame_len = len; | |
2705 | ||
fd67dc83 FL |
2706 | wait_event_interruptible_timeout(bus->ctrl_wait, |
2707 | !bus->ctrl_frame_stat, | |
2708 | msecs_to_jiffies(2000)); | |
5b435de0 | 2709 | |
23677ce3 | 2710 | if (!bus->ctrl_frame_stat) { |
c3203374 | 2711 | brcmf_dbg(SDIO, "ctrl_frame_stat == false\n"); |
5b435de0 AS |
2712 | ret = 0; |
2713 | } else { | |
c3203374 | 2714 | brcmf_dbg(SDIO, "ctrl_frame_stat == true\n"); |
5b435de0 AS |
2715 | ret = -1; |
2716 | } | |
2717 | } | |
2718 | ||
2719 | if (ret == -1) { | |
1e023829 JP |
2720 | brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), |
2721 | frame, len, "Tx Frame:\n"); | |
2722 | brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && | |
2723 | BRCMF_HDRS_ON(), | |
2724 | frame, min_t(u16, len, 16), "TxHdr:\n"); | |
5b435de0 AS |
2725 | |
2726 | do { | |
38b0b0dd | 2727 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 2728 | ret = brcmf_tx_frame(bus, frame, len); |
38b0b0dd | 2729 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2730 | } while (ret < 0 && retries++ < TXRETRIES); |
2731 | } | |
2732 | ||
f1e68c2e | 2733 | if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && |
fccfe930 | 2734 | atomic_read(&bus->dpc_tskcnt) == 0) { |
5b435de0 | 2735 | bus->activity = false; |
38b0b0dd | 2736 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 2737 | brcmf_dbg(INFO, "idle\n"); |
5b435de0 | 2738 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, true); |
38b0b0dd | 2739 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
2740 | } |
2741 | ||
5b435de0 | 2742 | if (ret) |
80969836 | 2743 | bus->sdcnt.tx_ctlerrs++; |
5b435de0 | 2744 | else |
80969836 | 2745 | bus->sdcnt.tx_ctlpkts++; |
5b435de0 AS |
2746 | |
2747 | return ret ? -EIO : 0; | |
2748 | } | |
2749 | ||
80969836 | 2750 | #ifdef DEBUG |
4fc0d016 AS |
2751 | static inline bool brcmf_sdio_valid_shared_address(u32 addr) |
2752 | { | |
2753 | return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); | |
2754 | } | |
2755 | ||
2756 | static int brcmf_sdio_readshared(struct brcmf_sdio *bus, | |
2757 | struct sdpcm_shared *sh) | |
2758 | { | |
2759 | u32 addr; | |
2760 | int rv; | |
2761 | u32 shaddr = 0; | |
2762 | struct sdpcm_shared_le sh_le; | |
2763 | __le32 addr_le; | |
2764 | ||
1640f28f | 2765 | shaddr = bus->ci->rambase + bus->ramsize - 4; |
4fc0d016 AS |
2766 | |
2767 | /* | |
2768 | * Read last word in socram to determine | |
2769 | * address of sdpcm_shared structure | |
2770 | */ | |
38b0b0dd | 2771 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 2772 | brcmf_sdbrcm_bus_sleep(bus, false, false); |
ba540b01 | 2773 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4); |
b55de97f | 2774 | sdio_release_host(bus->sdiodev->func[1]); |
4fc0d016 AS |
2775 | if (rv < 0) |
2776 | return rv; | |
2777 | ||
2778 | addr = le32_to_cpu(addr_le); | |
2779 | ||
c3203374 | 2780 | brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr); |
4fc0d016 AS |
2781 | |
2782 | /* | |
2783 | * Check if addr is valid. | |
2784 | * NVRAM length at the end of memory should have been overwritten. | |
2785 | */ | |
2786 | if (!brcmf_sdio_valid_shared_address(addr)) { | |
5e8149f5 | 2787 | brcmf_err("invalid sdpcm_shared address 0x%08X\n", |
4fc0d016 AS |
2788 | addr); |
2789 | return -EINVAL; | |
2790 | } | |
2791 | ||
2792 | /* Read hndrte_shared structure */ | |
ba540b01 FL |
2793 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, |
2794 | sizeof(struct sdpcm_shared_le)); | |
4fc0d016 AS |
2795 | if (rv < 0) |
2796 | return rv; | |
2797 | ||
2798 | /* Endianness */ | |
2799 | sh->flags = le32_to_cpu(sh_le.flags); | |
2800 | sh->trap_addr = le32_to_cpu(sh_le.trap_addr); | |
2801 | sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); | |
2802 | sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); | |
2803 | sh->assert_line = le32_to_cpu(sh_le.assert_line); | |
2804 | sh->console_addr = le32_to_cpu(sh_le.console_addr); | |
2805 | sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); | |
2806 | ||
86dcd937 PH |
2807 | if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { |
2808 | brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", | |
4fc0d016 AS |
2809 | SDPCM_SHARED_VERSION, |
2810 | sh->flags & SDPCM_SHARED_VERSION_MASK); | |
2811 | return -EPROTO; | |
2812 | } | |
2813 | ||
2814 | return 0; | |
2815 | } | |
2816 | ||
2817 | static int brcmf_sdio_dump_console(struct brcmf_sdio *bus, | |
2818 | struct sdpcm_shared *sh, char __user *data, | |
2819 | size_t count) | |
2820 | { | |
2821 | u32 addr, console_ptr, console_size, console_index; | |
2822 | char *conbuf = NULL; | |
2823 | __le32 sh_val; | |
2824 | int rv; | |
2825 | loff_t pos = 0; | |
2826 | int nbytes = 0; | |
2827 | ||
2828 | /* obtain console information from device memory */ | |
2829 | addr = sh->console_addr + offsetof(struct rte_console, log_le); | |
ba540b01 FL |
2830 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, |
2831 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2832 | if (rv < 0) |
2833 | return rv; | |
2834 | console_ptr = le32_to_cpu(sh_val); | |
2835 | ||
2836 | addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); | |
ba540b01 FL |
2837 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, |
2838 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2839 | if (rv < 0) |
2840 | return rv; | |
2841 | console_size = le32_to_cpu(sh_val); | |
2842 | ||
2843 | addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); | |
ba540b01 FL |
2844 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, |
2845 | (u8 *)&sh_val, sizeof(u32)); | |
4fc0d016 AS |
2846 | if (rv < 0) |
2847 | return rv; | |
2848 | console_index = le32_to_cpu(sh_val); | |
2849 | ||
2850 | /* allocate buffer for console data */ | |
2851 | if (console_size <= CONSOLE_BUFFER_MAX) | |
2852 | conbuf = vzalloc(console_size+1); | |
2853 | ||
2854 | if (!conbuf) | |
2855 | return -ENOMEM; | |
2856 | ||
2857 | /* obtain the console data from device */ | |
2858 | conbuf[console_size] = '\0'; | |
ba540b01 FL |
2859 | rv = brcmf_sdio_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, |
2860 | console_size); | |
4fc0d016 AS |
2861 | if (rv < 0) |
2862 | goto done; | |
2863 | ||
2864 | rv = simple_read_from_buffer(data, count, &pos, | |
2865 | conbuf + console_index, | |
2866 | console_size - console_index); | |
2867 | if (rv < 0) | |
2868 | goto done; | |
2869 | ||
2870 | nbytes = rv; | |
2871 | if (console_index > 0) { | |
2872 | pos = 0; | |
2873 | rv = simple_read_from_buffer(data+nbytes, count, &pos, | |
2874 | conbuf, console_index - 1); | |
2875 | if (rv < 0) | |
2876 | goto done; | |
2877 | rv += nbytes; | |
2878 | } | |
2879 | done: | |
2880 | vfree(conbuf); | |
2881 | return rv; | |
2882 | } | |
2883 | ||
2884 | static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh, | |
2885 | char __user *data, size_t count) | |
2886 | { | |
2887 | int error, res; | |
2888 | char buf[350]; | |
2889 | struct brcmf_trap_info tr; | |
4fc0d016 AS |
2890 | loff_t pos = 0; |
2891 | ||
baa9e609 PH |
2892 | if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { |
2893 | brcmf_dbg(INFO, "no trap in firmware\n"); | |
4fc0d016 | 2894 | return 0; |
baa9e609 | 2895 | } |
4fc0d016 | 2896 | |
ba540b01 FL |
2897 | error = brcmf_sdio_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, |
2898 | sizeof(struct brcmf_trap_info)); | |
4fc0d016 AS |
2899 | if (error < 0) |
2900 | return error; | |
2901 | ||
4fc0d016 AS |
2902 | res = scnprintf(buf, sizeof(buf), |
2903 | "dongle trap info: type 0x%x @ epc 0x%08x\n" | |
2904 | " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" | |
2905 | " lr 0x%08x pc 0x%08x offset 0x%x\n" | |
2906 | " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" | |
2907 | " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", | |
2908 | le32_to_cpu(tr.type), le32_to_cpu(tr.epc), | |
2909 | le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), | |
2910 | le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), | |
9bd02c6b | 2911 | le32_to_cpu(tr.pc), sh->trap_addr, |
4fc0d016 AS |
2912 | le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), |
2913 | le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), | |
2914 | le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), | |
2915 | le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); | |
2916 | ||
baa9e609 | 2917 | return simple_read_from_buffer(data, count, &pos, buf, res); |
4fc0d016 AS |
2918 | } |
2919 | ||
2920 | static int brcmf_sdio_assert_info(struct brcmf_sdio *bus, | |
2921 | struct sdpcm_shared *sh, char __user *data, | |
2922 | size_t count) | |
2923 | { | |
2924 | int error = 0; | |
2925 | char buf[200]; | |
2926 | char file[80] = "?"; | |
2927 | char expr[80] = "<???>"; | |
2928 | int res; | |
2929 | loff_t pos = 0; | |
2930 | ||
2931 | if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { | |
2932 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
2933 | return 0; | |
2934 | } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { | |
2935 | brcmf_dbg(INFO, "no assert in dongle\n"); | |
2936 | return 0; | |
2937 | } | |
2938 | ||
38b0b0dd | 2939 | sdio_claim_host(bus->sdiodev->func[1]); |
4fc0d016 | 2940 | if (sh->assert_file_addr != 0) { |
ba540b01 FL |
2941 | error = brcmf_sdio_ramrw(bus->sdiodev, false, |
2942 | sh->assert_file_addr, (u8 *)file, 80); | |
4fc0d016 AS |
2943 | if (error < 0) |
2944 | return error; | |
2945 | } | |
2946 | if (sh->assert_exp_addr != 0) { | |
ba540b01 FL |
2947 | error = brcmf_sdio_ramrw(bus->sdiodev, false, |
2948 | sh->assert_exp_addr, (u8 *)expr, 80); | |
4fc0d016 AS |
2949 | if (error < 0) |
2950 | return error; | |
2951 | } | |
38b0b0dd | 2952 | sdio_release_host(bus->sdiodev->func[1]); |
4fc0d016 AS |
2953 | |
2954 | res = scnprintf(buf, sizeof(buf), | |
2955 | "dongle assert: %s:%d: assert(%s)\n", | |
2956 | file, sh->assert_line, expr); | |
2957 | return simple_read_from_buffer(data, count, &pos, buf, res); | |
2958 | } | |
2959 | ||
2960 | static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus) | |
2961 | { | |
2962 | int error; | |
2963 | struct sdpcm_shared sh; | |
2964 | ||
4fc0d016 | 2965 | error = brcmf_sdio_readshared(bus, &sh); |
4fc0d016 AS |
2966 | |
2967 | if (error < 0) | |
2968 | return error; | |
2969 | ||
2970 | if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) | |
2971 | brcmf_dbg(INFO, "firmware not built with -assert\n"); | |
2972 | else if (sh.flags & SDPCM_SHARED_ASSERT) | |
5e8149f5 | 2973 | brcmf_err("assertion in dongle\n"); |
4fc0d016 AS |
2974 | |
2975 | if (sh.flags & SDPCM_SHARED_TRAP) | |
5e8149f5 | 2976 | brcmf_err("firmware trap in dongle\n"); |
4fc0d016 AS |
2977 | |
2978 | return 0; | |
2979 | } | |
2980 | ||
2981 | static int brcmf_sdbrcm_died_dump(struct brcmf_sdio *bus, char __user *data, | |
2982 | size_t count, loff_t *ppos) | |
2983 | { | |
2984 | int error = 0; | |
2985 | struct sdpcm_shared sh; | |
2986 | int nbytes = 0; | |
2987 | loff_t pos = *ppos; | |
2988 | ||
2989 | if (pos != 0) | |
2990 | return 0; | |
2991 | ||
4fc0d016 AS |
2992 | error = brcmf_sdio_readshared(bus, &sh); |
2993 | if (error < 0) | |
2994 | goto done; | |
2995 | ||
2996 | error = brcmf_sdio_assert_info(bus, &sh, data, count); | |
2997 | if (error < 0) | |
2998 | goto done; | |
4fc0d016 | 2999 | nbytes = error; |
baa9e609 PH |
3000 | |
3001 | error = brcmf_sdio_trap_info(bus, &sh, data+nbytes, count); | |
4fc0d016 AS |
3002 | if (error < 0) |
3003 | goto done; | |
baa9e609 PH |
3004 | nbytes += error; |
3005 | ||
3006 | error = brcmf_sdio_dump_console(bus, &sh, data+nbytes, count); | |
3007 | if (error < 0) | |
3008 | goto done; | |
3009 | nbytes += error; | |
4fc0d016 | 3010 | |
baa9e609 PH |
3011 | error = nbytes; |
3012 | *ppos += nbytes; | |
4fc0d016 | 3013 | done: |
4fc0d016 AS |
3014 | return error; |
3015 | } | |
3016 | ||
3017 | static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data, | |
3018 | size_t count, loff_t *ppos) | |
3019 | { | |
3020 | struct brcmf_sdio *bus = f->private_data; | |
3021 | int res; | |
3022 | ||
3023 | res = brcmf_sdbrcm_died_dump(bus, data, count, ppos); | |
3024 | if (res > 0) | |
3025 | *ppos += res; | |
3026 | return (ssize_t)res; | |
3027 | } | |
3028 | ||
3029 | static const struct file_operations brcmf_sdio_forensic_ops = { | |
3030 | .owner = THIS_MODULE, | |
3031 | .open = simple_open, | |
3032 | .read = brcmf_sdio_forensic_read | |
3033 | }; | |
3034 | ||
80969836 AS |
3035 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3036 | { | |
3037 | struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; | |
4fc0d016 | 3038 | struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); |
80969836 | 3039 | |
4fc0d016 AS |
3040 | if (IS_ERR_OR_NULL(dentry)) |
3041 | return; | |
3042 | ||
3043 | debugfs_create_file("forensics", S_IRUGO, dentry, bus, | |
3044 | &brcmf_sdio_forensic_ops); | |
80969836 AS |
3045 | brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt); |
3046 | } | |
3047 | #else | |
4fc0d016 AS |
3048 | static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus) |
3049 | { | |
3050 | return 0; | |
3051 | } | |
3052 | ||
80969836 AS |
3053 | static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) |
3054 | { | |
3055 | } | |
3056 | #endif /* DEBUG */ | |
3057 | ||
fcf094f4 | 3058 | static int |
532cdd3b | 3059 | brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) |
5b435de0 AS |
3060 | { |
3061 | int timeleft; | |
3062 | uint rxlen = 0; | |
3063 | bool pending; | |
dd43a01c | 3064 | u8 *buf; |
532cdd3b | 3065 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3066 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
532cdd3b | 3067 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 AS |
3068 | |
3069 | brcmf_dbg(TRACE, "Enter\n"); | |
3070 | ||
3071 | /* Wait until control frame is available */ | |
3072 | timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending); | |
3073 | ||
dd43a01c | 3074 | spin_lock_bh(&bus->rxctl_lock); |
5b435de0 AS |
3075 | rxlen = bus->rxlen; |
3076 | memcpy(msg, bus->rxctl, min(msglen, rxlen)); | |
dd43a01c FL |
3077 | bus->rxctl = NULL; |
3078 | buf = bus->rxctl_orig; | |
3079 | bus->rxctl_orig = NULL; | |
5b435de0 | 3080 | bus->rxlen = 0; |
dd43a01c FL |
3081 | spin_unlock_bh(&bus->rxctl_lock); |
3082 | vfree(buf); | |
5b435de0 AS |
3083 | |
3084 | if (rxlen) { | |
3085 | brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", | |
3086 | rxlen, msglen); | |
3087 | } else if (timeleft == 0) { | |
5e8149f5 | 3088 | brcmf_err("resumed on timeout\n"); |
4fc0d016 | 3089 | brcmf_sdbrcm_checkdied(bus); |
23677ce3 | 3090 | } else if (pending) { |
5b435de0 AS |
3091 | brcmf_dbg(CTL, "cancelled\n"); |
3092 | return -ERESTARTSYS; | |
3093 | } else { | |
3094 | brcmf_dbg(CTL, "resumed for unknown reason?\n"); | |
4fc0d016 | 3095 | brcmf_sdbrcm_checkdied(bus); |
5b435de0 AS |
3096 | } |
3097 | ||
3098 | if (rxlen) | |
80969836 | 3099 | bus->sdcnt.rx_ctlpkts++; |
5b435de0 | 3100 | else |
80969836 | 3101 | bus->sdcnt.rx_ctlerrs++; |
5b435de0 AS |
3102 | |
3103 | return rxlen ? (int)rxlen : -ETIMEDOUT; | |
3104 | } | |
3105 | ||
069eddd9 | 3106 | static bool brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter) |
5b435de0 | 3107 | { |
99ba15cd | 3108 | struct chip_info *ci = bus->ci; |
5b435de0 AS |
3109 | |
3110 | /* To enter download state, disable ARM and reset SOCRAM. | |
3111 | * To exit download state, simply reset ARM (default is RAM boot). | |
3112 | */ | |
3113 | if (enter) { | |
3114 | bus->alp_only = true; | |
3115 | ||
069eddd9 | 3116 | brcmf_sdio_chip_enter_download(bus->sdiodev, ci); |
5b435de0 | 3117 | } else { |
069eddd9 FL |
3118 | if (!brcmf_sdio_chip_exit_download(bus->sdiodev, ci, bus->vars, |
3119 | bus->varsz)) | |
3120 | return false; | |
5b435de0 AS |
3121 | |
3122 | /* Allow HT Clock now that the ARM is running. */ | |
3123 | bus->alp_only = false; | |
3124 | ||
712ac5b3 | 3125 | bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD; |
5b435de0 | 3126 | } |
069eddd9 FL |
3127 | |
3128 | return true; | |
5b435de0 AS |
3129 | } |
3130 | ||
e92eedf4 | 3131 | static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus) |
5b435de0 | 3132 | { |
f2c44fe7 HM |
3133 | const struct firmware *fw; |
3134 | int err; | |
1640f28f | 3135 | int offset; |
f2c44fe7 HM |
3136 | int address; |
3137 | int len; | |
3138 | ||
3139 | fw = brcmf_sdbrcm_get_fw(bus, BRCMF_FIRMWARE_BIN); | |
3140 | if (fw == NULL) | |
3141 | return -ENOENT; | |
3142 | ||
3143 | if (brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_ARM_CR4) != | |
3144 | BRCMF_MAX_CORENUM) | |
3145 | memcpy(&bus->ci->rst_vec, fw->data, sizeof(bus->ci->rst_vec)); | |
3146 | ||
3147 | err = 0; | |
3148 | offset = 0; | |
3149 | address = bus->ci->rambase; | |
3150 | while (offset < fw->size) { | |
3151 | len = ((offset + MEMBLOCK) < fw->size) ? MEMBLOCK : | |
3152 | fw->size - offset; | |
3153 | err = brcmf_sdio_ramrw(bus->sdiodev, true, address, | |
3154 | (u8 *)&fw->data[offset], len); | |
3155 | if (err) { | |
5e8149f5 | 3156 | brcmf_err("error %d on writing %d membytes at 0x%08x\n", |
f2c44fe7 HM |
3157 | err, len, address); |
3158 | goto failure; | |
5b435de0 | 3159 | } |
f2c44fe7 HM |
3160 | offset += len; |
3161 | address += len; | |
5b435de0 AS |
3162 | } |
3163 | ||
f2c44fe7 HM |
3164 | failure: |
3165 | release_firmware(fw); | |
5b435de0 | 3166 | |
f2c44fe7 | 3167 | return err; |
5b435de0 AS |
3168 | } |
3169 | ||
3170 | /* | |
3171 | * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file | |
3172 | * and ending in a NUL. | |
3173 | * Removes carriage returns, empty lines, comment lines, and converts | |
3174 | * newlines to NULs. | |
3175 | * Shortens buffer as needed and pads with NULs. End of buffer is marked | |
3176 | * by two NULs. | |
3177 | */ | |
3178 | ||
f2c44fe7 HM |
3179 | static int brcmf_process_nvram_vars(struct brcmf_sdio *bus, |
3180 | const struct firmware *nv) | |
5b435de0 | 3181 | { |
d610cde3 | 3182 | char *varbuf; |
5b435de0 AS |
3183 | char *dp; |
3184 | bool findNewline; | |
3185 | int column; | |
d610cde3 FL |
3186 | int ret = 0; |
3187 | uint buf_len, n, len; | |
3188 | ||
f2c44fe7 | 3189 | len = nv->size; |
d610cde3 FL |
3190 | varbuf = vmalloc(len); |
3191 | if (!varbuf) | |
3192 | return -ENOMEM; | |
5b435de0 | 3193 | |
f2c44fe7 | 3194 | memcpy(varbuf, nv->data, len); |
5b435de0 AS |
3195 | dp = varbuf; |
3196 | ||
3197 | findNewline = false; | |
3198 | column = 0; | |
3199 | ||
3200 | for (n = 0; n < len; n++) { | |
3201 | if (varbuf[n] == 0) | |
3202 | break; | |
3203 | if (varbuf[n] == '\r') | |
3204 | continue; | |
3205 | if (findNewline && varbuf[n] != '\n') | |
3206 | continue; | |
3207 | findNewline = false; | |
3208 | if (varbuf[n] == '#') { | |
3209 | findNewline = true; | |
3210 | continue; | |
3211 | } | |
3212 | if (varbuf[n] == '\n') { | |
3213 | if (column == 0) | |
3214 | continue; | |
3215 | *dp++ = 0; | |
3216 | column = 0; | |
3217 | continue; | |
3218 | } | |
3219 | *dp++ = varbuf[n]; | |
3220 | column++; | |
3221 | } | |
3222 | buf_len = dp - varbuf; | |
5b435de0 AS |
3223 | while (dp < varbuf + n) |
3224 | *dp++ = 0; | |
3225 | ||
d610cde3 | 3226 | kfree(bus->vars); |
6d4ef680 AS |
3227 | /* roundup needed for download to device */ |
3228 | bus->varsz = roundup(buf_len + 1, 4); | |
d610cde3 FL |
3229 | bus->vars = kmalloc(bus->varsz, GFP_KERNEL); |
3230 | if (bus->vars == NULL) { | |
3231 | bus->varsz = 0; | |
3232 | ret = -ENOMEM; | |
3233 | goto err; | |
3234 | } | |
3235 | ||
3236 | /* copy the processed variables and add null termination */ | |
3237 | memcpy(bus->vars, varbuf, buf_len); | |
3238 | bus->vars[buf_len] = 0; | |
3239 | err: | |
3240 | vfree(varbuf); | |
3241 | return ret; | |
5b435de0 AS |
3242 | } |
3243 | ||
e92eedf4 | 3244 | static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus) |
5b435de0 | 3245 | { |
f2c44fe7 | 3246 | const struct firmware *nv; |
5b435de0 AS |
3247 | int ret; |
3248 | ||
f2c44fe7 HM |
3249 | nv = brcmf_sdbrcm_get_fw(bus, BRCMF_FIRMWARE_NVRAM); |
3250 | if (nv == NULL) | |
3251 | return -ENOENT; | |
5b435de0 | 3252 | |
f2c44fe7 | 3253 | ret = brcmf_process_nvram_vars(bus, nv); |
5b435de0 | 3254 | |
f2c44fe7 | 3255 | release_firmware(nv); |
5b435de0 AS |
3256 | |
3257 | return ret; | |
3258 | } | |
3259 | ||
e92eedf4 | 3260 | static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus) |
5b435de0 AS |
3261 | { |
3262 | int bcmerror = -1; | |
3263 | ||
3264 | /* Keep arm in reset */ | |
069eddd9 | 3265 | if (!brcmf_sdbrcm_download_state(bus, true)) { |
5e8149f5 | 3266 | brcmf_err("error placing ARM core in reset\n"); |
5b435de0 AS |
3267 | goto err; |
3268 | } | |
3269 | ||
5b435de0 | 3270 | if (brcmf_sdbrcm_download_code_file(bus)) { |
5e8149f5 | 3271 | brcmf_err("dongle image file download failed\n"); |
5b435de0 AS |
3272 | goto err; |
3273 | } | |
3274 | ||
3eaa956c | 3275 | if (brcmf_sdbrcm_download_nvram(bus)) { |
5e8149f5 | 3276 | brcmf_err("dongle nvram file download failed\n"); |
3eaa956c FL |
3277 | goto err; |
3278 | } | |
5b435de0 AS |
3279 | |
3280 | /* Take arm out of reset */ | |
069eddd9 | 3281 | if (!brcmf_sdbrcm_download_state(bus, false)) { |
5e8149f5 | 3282 | brcmf_err("error getting out of ARM core reset\n"); |
5b435de0 AS |
3283 | goto err; |
3284 | } | |
3285 | ||
3286 | bcmerror = 0; | |
3287 | ||
3288 | err: | |
3289 | return bcmerror; | |
3290 | } | |
3291 | ||
4a3da990 PH |
3292 | static bool brcmf_sdbrcm_sr_capable(struct brcmf_sdio *bus) |
3293 | { | |
3294 | u32 addr, reg; | |
3295 | ||
3296 | brcmf_dbg(TRACE, "Enter\n"); | |
3297 | ||
3298 | /* old chips with PMU version less than 17 don't support save restore */ | |
3299 | if (bus->ci->pmurev < 17) | |
3300 | return false; | |
3301 | ||
3302 | /* read PMU chipcontrol register 3*/ | |
3303 | addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr); | |
3304 | brcmf_sdio_regwl(bus->sdiodev, addr, 3, NULL); | |
3305 | addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data); | |
3306 | reg = brcmf_sdio_regrl(bus->sdiodev, addr, NULL); | |
3307 | ||
3308 | return (bool)reg; | |
3309 | } | |
3310 | ||
3311 | static void brcmf_sdbrcm_sr_init(struct brcmf_sdio *bus) | |
3312 | { | |
3313 | int err = 0; | |
3314 | u8 val; | |
3315 | ||
3316 | brcmf_dbg(TRACE, "Enter\n"); | |
3317 | ||
3318 | val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, | |
3319 | &err); | |
3320 | if (err) { | |
3321 | brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3322 | return; | |
3323 | } | |
3324 | ||
3325 | val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; | |
3326 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, | |
3327 | val, &err); | |
3328 | if (err) { | |
3329 | brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); | |
3330 | return; | |
3331 | } | |
3332 | ||
3333 | /* Add CMD14 Support */ | |
3334 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, | |
3335 | (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | | |
3336 | SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), | |
3337 | &err); | |
3338 | if (err) { | |
3339 | brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); | |
3340 | return; | |
3341 | } | |
3342 | ||
3343 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
3344 | SBSDIO_FORCE_HT, &err); | |
3345 | if (err) { | |
3346 | brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); | |
3347 | return; | |
3348 | } | |
3349 | ||
3350 | /* set flag */ | |
3351 | bus->sr_enabled = true; | |
3352 | brcmf_dbg(INFO, "SR enabled\n"); | |
3353 | } | |
3354 | ||
3355 | /* enable KSO bit */ | |
3356 | static int brcmf_sdbrcm_kso_init(struct brcmf_sdio *bus) | |
3357 | { | |
3358 | u8 val; | |
3359 | int err = 0; | |
3360 | ||
3361 | brcmf_dbg(TRACE, "Enter\n"); | |
3362 | ||
3363 | /* KSO bit added in SDIO core rev 12 */ | |
3364 | if (bus->ci->c_inf[1].rev < 12) | |
3365 | return 0; | |
3366 | ||
3367 | val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
3368 | &err); | |
3369 | if (err) { | |
3370 | brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); | |
3371 | return err; | |
3372 | } | |
3373 | ||
3374 | if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { | |
3375 | val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << | |
3376 | SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); | |
3377 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, | |
3378 | val, &err); | |
3379 | if (err) { | |
3380 | brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); | |
3381 | return err; | |
3382 | } | |
3383 | } | |
3384 | ||
3385 | return 0; | |
3386 | } | |
3387 | ||
3388 | ||
5b435de0 | 3389 | static bool |
e92eedf4 | 3390 | brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus) |
5b435de0 AS |
3391 | { |
3392 | bool ret; | |
3393 | ||
38b0b0dd FL |
3394 | sdio_claim_host(bus->sdiodev->func[1]); |
3395 | ||
5b435de0 AS |
3396 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); |
3397 | ||
3398 | ret = _brcmf_sdbrcm_download_firmware(bus) == 0; | |
3399 | ||
3400 | brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); | |
3401 | ||
38b0b0dd FL |
3402 | sdio_release_host(bus->sdiodev->func[1]); |
3403 | ||
5b435de0 AS |
3404 | return ret; |
3405 | } | |
3406 | ||
99a0b8ff | 3407 | static int brcmf_sdbrcm_bus_init(struct device *dev) |
5b435de0 | 3408 | { |
fa20b911 | 3409 | struct brcmf_bus *bus_if = dev_get_drvdata(dev); |
0a332e46 | 3410 | struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; |
fa20b911 | 3411 | struct brcmf_sdio *bus = sdiodev->bus; |
5b435de0 | 3412 | unsigned long timeout; |
5b435de0 AS |
3413 | u8 ready, enable; |
3414 | int err, ret = 0; | |
3415 | u8 saveclk; | |
3416 | ||
3417 | brcmf_dbg(TRACE, "Enter\n"); | |
3418 | ||
3419 | /* try to download image and nvram to the dongle */ | |
fa20b911 | 3420 | if (bus_if->state == BRCMF_BUS_DOWN) { |
5b435de0 AS |
3421 | if (!(brcmf_sdbrcm_download_firmware(bus))) |
3422 | return -1; | |
3423 | } | |
3424 | ||
712ac5b3 | 3425 | if (!bus->sdiodev->bus_if->drvr) |
5b435de0 AS |
3426 | return 0; |
3427 | ||
3428 | /* Start the watchdog timer */ | |
80969836 | 3429 | bus->sdcnt.tickcnt = 0; |
5b435de0 AS |
3430 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); |
3431 | ||
38b0b0dd | 3432 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3433 | |
3434 | /* Make sure backplane clock is on, needed to generate F2 interrupt */ | |
3435 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); | |
3436 | if (bus->clkstate != CLK_AVAIL) | |
3437 | goto exit; | |
3438 | ||
3439 | /* Force clocks on backplane to be sure F2 interrupt propagates */ | |
45db339c FL |
3440 | saveclk = brcmf_sdio_regrb(bus->sdiodev, |
3441 | SBSDIO_FUNC1_CHIPCLKCSR, &err); | |
5b435de0 | 3442 | if (!err) { |
3bba829f FL |
3443 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3444 | (saveclk | SBSDIO_FORCE_HT), &err); | |
5b435de0 AS |
3445 | } |
3446 | if (err) { | |
5e8149f5 | 3447 | brcmf_err("Failed to force clock for F2: err %d\n", err); |
5b435de0 AS |
3448 | goto exit; |
3449 | } | |
3450 | ||
3451 | /* Enable function 2 (frame transfers) */ | |
3452 | w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, | |
58692750 | 3453 | offsetof(struct sdpcmd_regs, tosbmailboxdata)); |
5b435de0 AS |
3454 | enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2); |
3455 | ||
3bba829f | 3456 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL); |
5b435de0 AS |
3457 | |
3458 | timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY); | |
3459 | ready = 0; | |
3460 | while (enable != ready) { | |
45db339c FL |
3461 | ready = brcmf_sdio_regrb(bus->sdiodev, |
3462 | SDIO_CCCR_IORx, NULL); | |
5b435de0 AS |
3463 | if (time_after(jiffies, timeout)) |
3464 | break; | |
3465 | else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50)) | |
3466 | /* prevent busy waiting if it takes too long */ | |
3467 | msleep_interruptible(20); | |
3468 | } | |
3469 | ||
3470 | brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready); | |
3471 | ||
3472 | /* If F2 successfully enabled, set core and enable interrupts */ | |
3473 | if (ready == enable) { | |
3474 | /* Set up the interrupt mask and enable interrupts */ | |
3475 | bus->hostintmask = HOSTINTMASK; | |
3476 | w_sdreg32(bus, bus->hostintmask, | |
58692750 | 3477 | offsetof(struct sdpcmd_regs, hostintmask)); |
5b435de0 | 3478 | |
3bba829f | 3479 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err); |
c0e89f08 | 3480 | } else { |
5b435de0 AS |
3481 | /* Disable F2 again */ |
3482 | enable = SDIO_FUNC_ENABLE_1; | |
3bba829f | 3483 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL); |
c0e89f08 | 3484 | ret = -ENODEV; |
5b435de0 AS |
3485 | } |
3486 | ||
4a3da990 PH |
3487 | if (brcmf_sdbrcm_sr_capable(bus)) { |
3488 | brcmf_sdbrcm_sr_init(bus); | |
3489 | } else { | |
3490 | /* Restore previous clock setting */ | |
3491 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, | |
3492 | saveclk, &err); | |
3493 | } | |
5b435de0 | 3494 | |
e2f93cc3 | 3495 | if (ret == 0) { |
ba89bf19 | 3496 | ret = brcmf_sdio_intr_register(bus->sdiodev); |
e2f93cc3 | 3497 | if (ret != 0) |
5e8149f5 | 3498 | brcmf_err("intr register failed:%d\n", ret); |
e2f93cc3 FL |
3499 | } |
3500 | ||
5b435de0 | 3501 | /* If we didn't come up, turn off backplane clock */ |
d9126e0c | 3502 | if (bus_if->state != BRCMF_BUS_DATA) |
5b435de0 AS |
3503 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); |
3504 | ||
3505 | exit: | |
38b0b0dd | 3506 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3507 | |
3508 | return ret; | |
3509 | } | |
3510 | ||
3511 | void brcmf_sdbrcm_isr(void *arg) | |
3512 | { | |
e92eedf4 | 3513 | struct brcmf_sdio *bus = (struct brcmf_sdio *) arg; |
5b435de0 AS |
3514 | |
3515 | brcmf_dbg(TRACE, "Enter\n"); | |
3516 | ||
3517 | if (!bus) { | |
5e8149f5 | 3518 | brcmf_err("bus is null pointer, exiting\n"); |
5b435de0 AS |
3519 | return; |
3520 | } | |
3521 | ||
712ac5b3 | 3522 | if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) { |
5e8149f5 | 3523 | brcmf_err("bus is down. we have nothing to do\n"); |
5b435de0 AS |
3524 | return; |
3525 | } | |
3526 | /* Count the interrupt call */ | |
80969836 | 3527 | bus->sdcnt.intrcount++; |
4531603a FL |
3528 | if (in_interrupt()) |
3529 | atomic_set(&bus->ipend, 1); | |
3530 | else | |
3531 | if (brcmf_sdio_intr_rstatus(bus)) { | |
5e8149f5 | 3532 | brcmf_err("failed backplane access\n"); |
4531603a FL |
3533 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
3534 | } | |
5b435de0 | 3535 | |
5b435de0 AS |
3536 | /* Disable additional interrupts (is this needed now)? */ |
3537 | if (!bus->intr) | |
5e8149f5 | 3538 | brcmf_err("isr w/o interrupt configured!\n"); |
5b435de0 | 3539 | |
fccfe930 | 3540 | atomic_inc(&bus->dpc_tskcnt); |
f1e68c2e | 3541 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3542 | } |
3543 | ||
cad2b26b | 3544 | static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus) |
5b435de0 | 3545 | { |
8ae74654 | 3546 | #ifdef DEBUG |
cad2b26b | 3547 | struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev); |
8ae74654 | 3548 | #endif /* DEBUG */ |
5b435de0 AS |
3549 | |
3550 | brcmf_dbg(TIMER, "Enter\n"); | |
3551 | ||
5b435de0 | 3552 | /* Poll period: check device if appropriate. */ |
4a3da990 PH |
3553 | if (!bus->sr_enabled && |
3554 | bus->poll && (++bus->polltick >= bus->pollrate)) { | |
5b435de0 AS |
3555 | u32 intstatus = 0; |
3556 | ||
3557 | /* Reset poll tick */ | |
3558 | bus->polltick = 0; | |
3559 | ||
3560 | /* Check device if no interrupts */ | |
80969836 AS |
3561 | if (!bus->intr || |
3562 | (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { | |
5b435de0 | 3563 | |
fccfe930 | 3564 | if (atomic_read(&bus->dpc_tskcnt) == 0) { |
5b435de0 | 3565 | u8 devpend; |
fccfe930 | 3566 | |
38b0b0dd | 3567 | sdio_claim_host(bus->sdiodev->func[1]); |
45db339c FL |
3568 | devpend = brcmf_sdio_regrb(bus->sdiodev, |
3569 | SDIO_CCCR_INTx, | |
3570 | NULL); | |
38b0b0dd | 3571 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3572 | intstatus = |
3573 | devpend & (INTR_STATUS_FUNC1 | | |
3574 | INTR_STATUS_FUNC2); | |
3575 | } | |
3576 | ||
3577 | /* If there is something, make like the ISR and | |
3578 | schedule the DPC */ | |
3579 | if (intstatus) { | |
80969836 | 3580 | bus->sdcnt.pollcnt++; |
1d382273 | 3581 | atomic_set(&bus->ipend, 1); |
5b435de0 | 3582 | |
fccfe930 | 3583 | atomic_inc(&bus->dpc_tskcnt); |
f1e68c2e | 3584 | queue_work(bus->brcmf_wq, &bus->datawork); |
5b435de0 AS |
3585 | } |
3586 | } | |
3587 | ||
3588 | /* Update interrupt tracking */ | |
80969836 | 3589 | bus->sdcnt.lastintrs = bus->sdcnt.intrcount; |
5b435de0 | 3590 | } |
8ae74654 | 3591 | #ifdef DEBUG |
5b435de0 | 3592 | /* Poll for console output periodically */ |
2def5c10 | 3593 | if (bus_if && bus_if->state == BRCMF_BUS_DATA && |
8d169aa0 | 3594 | bus->console_interval != 0) { |
5b435de0 AS |
3595 | bus->console.count += BRCMF_WD_POLL_MS; |
3596 | if (bus->console.count >= bus->console_interval) { | |
3597 | bus->console.count -= bus->console_interval; | |
38b0b0dd | 3598 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 | 3599 | /* Make sure backplane clock is on */ |
4a3da990 | 3600 | brcmf_sdbrcm_bus_sleep(bus, false, false); |
5b435de0 AS |
3601 | if (brcmf_sdbrcm_readconsole(bus) < 0) |
3602 | /* stop on error */ | |
3603 | bus->console_interval = 0; | |
38b0b0dd | 3604 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3605 | } |
3606 | } | |
8ae74654 | 3607 | #endif /* DEBUG */ |
5b435de0 AS |
3608 | |
3609 | /* On idle timeout clear activity flag and/or turn off clock */ | |
3610 | if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) { | |
3611 | if (++bus->idlecount >= bus->idletime) { | |
3612 | bus->idlecount = 0; | |
3613 | if (bus->activity) { | |
3614 | bus->activity = false; | |
3615 | brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS); | |
3616 | } else { | |
4a3da990 | 3617 | brcmf_dbg(SDIO, "idle\n"); |
38b0b0dd | 3618 | sdio_claim_host(bus->sdiodev->func[1]); |
4a3da990 | 3619 | brcmf_sdbrcm_bus_sleep(bus, true, false); |
38b0b0dd | 3620 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3621 | } |
3622 | } | |
3623 | } | |
3624 | ||
1d382273 | 3625 | return (atomic_read(&bus->ipend) > 0); |
5b435de0 AS |
3626 | } |
3627 | ||
f1e68c2e FL |
3628 | static void brcmf_sdio_dataworker(struct work_struct *work) |
3629 | { | |
3630 | struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, | |
3631 | datawork); | |
f1e68c2e | 3632 | |
fccfe930 | 3633 | while (atomic_read(&bus->dpc_tskcnt)) { |
f1e68c2e | 3634 | brcmf_sdbrcm_dpc(bus); |
fccfe930 | 3635 | atomic_dec(&bus->dpc_tskcnt); |
f1e68c2e | 3636 | } |
f1e68c2e FL |
3637 | } |
3638 | ||
e92eedf4 | 3639 | static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus) |
5b435de0 AS |
3640 | { |
3641 | brcmf_dbg(TRACE, "Enter\n"); | |
3642 | ||
3643 | kfree(bus->rxbuf); | |
3644 | bus->rxctl = bus->rxbuf = NULL; | |
3645 | bus->rxlen = 0; | |
5b435de0 AS |
3646 | } |
3647 | ||
e92eedf4 | 3648 | static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus) |
5b435de0 AS |
3649 | { |
3650 | brcmf_dbg(TRACE, "Enter\n"); | |
3651 | ||
b01a6b3c | 3652 | if (bus->sdiodev->bus_if->maxctl) { |
5b435de0 | 3653 | bus->rxblen = |
b01a6b3c | 3654 | roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), |
5b435de0 AS |
3655 | ALIGNMENT) + BRCMF_SDALIGN; |
3656 | bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); | |
3657 | if (!(bus->rxbuf)) | |
354b75bf | 3658 | return false; |
5b435de0 AS |
3659 | } |
3660 | ||
5b435de0 | 3661 | return true; |
5b435de0 AS |
3662 | } |
3663 | ||
5b435de0 | 3664 | static bool |
e92eedf4 | 3665 | brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva) |
5b435de0 AS |
3666 | { |
3667 | u8 clkctl = 0; | |
3668 | int err = 0; | |
3669 | int reg_addr; | |
3670 | u32 reg_val; | |
668761ac | 3671 | u32 drivestrength; |
5b435de0 AS |
3672 | |
3673 | bus->alp_only = true; | |
3674 | ||
38b0b0dd FL |
3675 | sdio_claim_host(bus->sdiodev->func[1]); |
3676 | ||
18aad4f8 | 3677 | pr_debug("F1 signature read @0x18000000=0x%4x\n", |
79ae3957 | 3678 | brcmf_sdio_regrl(bus->sdiodev, SI_ENUM_BASE, NULL)); |
5b435de0 AS |
3679 | |
3680 | /* | |
a97e4fc5 | 3681 | * Force PLL off until brcmf_sdio_chip_attach() |
5b435de0 AS |
3682 | * programs PLL control regs |
3683 | */ | |
3684 | ||
3bba829f FL |
3685 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, |
3686 | BRCMF_INIT_CLKCTL1, &err); | |
5b435de0 | 3687 | if (!err) |
45db339c | 3688 | clkctl = brcmf_sdio_regrb(bus->sdiodev, |
5b435de0 AS |
3689 | SBSDIO_FUNC1_CHIPCLKCSR, &err); |
3690 | ||
3691 | if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { | |
5e8149f5 | 3692 | brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", |
5b435de0 AS |
3693 | err, BRCMF_INIT_CLKCTL1, clkctl); |
3694 | goto fail; | |
3695 | } | |
3696 | ||
a97e4fc5 | 3697 | if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) { |
5e8149f5 | 3698 | brcmf_err("brcmf_sdio_chip_attach failed!\n"); |
5b435de0 AS |
3699 | goto fail; |
3700 | } | |
3701 | ||
4a3da990 PH |
3702 | if (brcmf_sdbrcm_kso_init(bus)) { |
3703 | brcmf_err("error enabling KSO\n"); | |
3704 | goto fail; | |
3705 | } | |
3706 | ||
668761ac HM |
3707 | if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength)) |
3708 | drivestrength = bus->sdiodev->pdata->drive_strength; | |
3709 | else | |
3710 | drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; | |
3711 | brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength); | |
5b435de0 | 3712 | |
454d2a88 | 3713 | /* Get info on the SOCRAM cores... */ |
5b435de0 AS |
3714 | bus->ramsize = bus->ci->ramsize; |
3715 | if (!(bus->ramsize)) { | |
5e8149f5 | 3716 | brcmf_err("failed to find SOCRAM memory!\n"); |
5b435de0 AS |
3717 | goto fail; |
3718 | } | |
3719 | ||
1e9ab4dd PH |
3720 | /* Set card control so an SDIO card reset does a WLAN backplane reset */ |
3721 | reg_val = brcmf_sdio_regrb(bus->sdiodev, | |
3722 | SDIO_CCCR_BRCM_CARDCTRL, &err); | |
3723 | if (err) | |
3724 | goto fail; | |
3725 | ||
3726 | reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; | |
3727 | ||
3728 | brcmf_sdio_regwb(bus->sdiodev, | |
3729 | SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); | |
3730 | if (err) | |
3731 | goto fail; | |
3732 | ||
3733 | /* set PMUControl so a backplane reset does PMU state reload */ | |
3734 | reg_addr = CORE_CC_REG(bus->ci->c_inf[0].base, | |
3735 | pmucontrol); | |
3736 | reg_val = brcmf_sdio_regrl(bus->sdiodev, | |
3737 | reg_addr, | |
3738 | &err); | |
3739 | if (err) | |
3740 | goto fail; | |
3741 | ||
3742 | reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); | |
3743 | ||
3744 | brcmf_sdio_regwl(bus->sdiodev, | |
3745 | reg_addr, | |
3746 | reg_val, | |
3747 | &err); | |
3748 | if (err) | |
3749 | goto fail; | |
3750 | ||
5b435de0 | 3751 | |
38b0b0dd FL |
3752 | sdio_release_host(bus->sdiodev->func[1]); |
3753 | ||
5b435de0 AS |
3754 | brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); |
3755 | ||
3756 | /* Locate an appropriately-aligned portion of hdrbuf */ | |
3757 | bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], | |
3758 | BRCMF_SDALIGN); | |
3759 | ||
3760 | /* Set the poll and/or interrupt flags */ | |
3761 | bus->intr = true; | |
3762 | bus->poll = false; | |
3763 | if (bus->poll) | |
3764 | bus->pollrate = 1; | |
3765 | ||
3766 | return true; | |
3767 | ||
3768 | fail: | |
38b0b0dd | 3769 | sdio_release_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3770 | return false; |
3771 | } | |
3772 | ||
e92eedf4 | 3773 | static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus) |
5b435de0 AS |
3774 | { |
3775 | brcmf_dbg(TRACE, "Enter\n"); | |
3776 | ||
38b0b0dd FL |
3777 | sdio_claim_host(bus->sdiodev->func[1]); |
3778 | ||
5b435de0 | 3779 | /* Disable F2 to clear any intermediate frame state on the dongle */ |
3bba829f FL |
3780 | brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, |
3781 | SDIO_FUNC_ENABLE_1, NULL); | |
5b435de0 | 3782 | |
712ac5b3 | 3783 | bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN; |
5b435de0 AS |
3784 | bus->rxflow = false; |
3785 | ||
3786 | /* Done with backplane-dependent accesses, can drop clock... */ | |
3bba829f | 3787 | brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); |
5b435de0 | 3788 | |
38b0b0dd FL |
3789 | sdio_release_host(bus->sdiodev->func[1]); |
3790 | ||
5b435de0 AS |
3791 | /* ...and initialize clock/power states */ |
3792 | bus->clkstate = CLK_SDONLY; | |
3793 | bus->idletime = BRCMF_IDLE_INTERVAL; | |
3794 | bus->idleclock = BRCMF_IDLE_ACTIVE; | |
3795 | ||
3796 | /* Query the F2 block size, set roundup accordingly */ | |
3797 | bus->blocksize = bus->sdiodev->func[2]->cur_blksize; | |
3798 | bus->roundup = min(max_roundup, bus->blocksize); | |
3799 | ||
4a3da990 PH |
3800 | /* SR state */ |
3801 | bus->sleeping = false; | |
3802 | bus->sr_enabled = false; | |
3803 | ||
5b435de0 AS |
3804 | return true; |
3805 | } | |
3806 | ||
3807 | static int | |
3808 | brcmf_sdbrcm_watchdog_thread(void *data) | |
3809 | { | |
e92eedf4 | 3810 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3811 | |
3812 | allow_signal(SIGTERM); | |
3813 | /* Run until signal received */ | |
3814 | while (1) { | |
3815 | if (kthread_should_stop()) | |
3816 | break; | |
3817 | if (!wait_for_completion_interruptible(&bus->watchdog_wait)) { | |
cad2b26b | 3818 | brcmf_sdbrcm_bus_watchdog(bus); |
5b435de0 | 3819 | /* Count the tick for reference */ |
80969836 | 3820 | bus->sdcnt.tickcnt++; |
5b435de0 AS |
3821 | } else |
3822 | break; | |
3823 | } | |
3824 | return 0; | |
3825 | } | |
3826 | ||
3827 | static void | |
3828 | brcmf_sdbrcm_watchdog(unsigned long data) | |
3829 | { | |
e92eedf4 | 3830 | struct brcmf_sdio *bus = (struct brcmf_sdio *)data; |
5b435de0 AS |
3831 | |
3832 | if (bus->watchdog_tsk) { | |
3833 | complete(&bus->watchdog_wait); | |
3834 | /* Reschedule the watchdog */ | |
3835 | if (bus->wd_timer_valid) | |
3836 | mod_timer(&bus->timer, | |
3837 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
3838 | } | |
3839 | } | |
3840 | ||
e92eedf4 | 3841 | static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus) |
5b435de0 AS |
3842 | { |
3843 | brcmf_dbg(TRACE, "Enter\n"); | |
3844 | ||
3845 | if (bus->ci) { | |
38b0b0dd | 3846 | sdio_claim_host(bus->sdiodev->func[1]); |
5b435de0 AS |
3847 | brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); |
3848 | brcmf_sdbrcm_clkctl(bus, CLK_NONE, false); | |
38b0b0dd | 3849 | sdio_release_host(bus->sdiodev->func[1]); |
a8a6c045 | 3850 | brcmf_sdio_chip_detach(&bus->ci); |
5b435de0 AS |
3851 | if (bus->vars && bus->varsz) |
3852 | kfree(bus->vars); | |
3853 | bus->vars = NULL; | |
3854 | } | |
3855 | ||
3856 | brcmf_dbg(TRACE, "Disconnected\n"); | |
3857 | } | |
3858 | ||
3859 | /* Detach and free everything */ | |
e92eedf4 | 3860 | static void brcmf_sdbrcm_release(struct brcmf_sdio *bus) |
5b435de0 AS |
3861 | { |
3862 | brcmf_dbg(TRACE, "Enter\n"); | |
4fc0d016 | 3863 | |
5b435de0 AS |
3864 | if (bus) { |
3865 | /* De-register interrupt handler */ | |
ba89bf19 | 3866 | brcmf_sdio_intr_unregister(bus->sdiodev); |
5b435de0 | 3867 | |
f1e68c2e | 3868 | cancel_work_sync(&bus->datawork); |
37ac5780 HM |
3869 | if (bus->brcmf_wq) |
3870 | destroy_workqueue(bus->brcmf_wq); | |
f1e68c2e | 3871 | |
5f947ad9 FL |
3872 | if (bus->sdiodev->bus_if->drvr) { |
3873 | brcmf_detach(bus->sdiodev->dev); | |
5b435de0 | 3874 | brcmf_sdbrcm_release_dongle(bus); |
5b435de0 AS |
3875 | } |
3876 | ||
3877 | brcmf_sdbrcm_release_malloc(bus); | |
3878 | ||
3879 | kfree(bus); | |
3880 | } | |
3881 | ||
3882 | brcmf_dbg(TRACE, "Disconnected\n"); | |
3883 | } | |
3884 | ||
d9cb2596 AS |
3885 | static struct brcmf_bus_ops brcmf_sdio_bus_ops = { |
3886 | .stop = brcmf_sdbrcm_bus_stop, | |
3887 | .init = brcmf_sdbrcm_bus_init, | |
3888 | .txdata = brcmf_sdbrcm_bus_txdata, | |
3889 | .txctl = brcmf_sdbrcm_bus_txctl, | |
3890 | .rxctl = brcmf_sdbrcm_bus_rxctl, | |
e2432b67 | 3891 | .gettxq = brcmf_sdbrcm_bus_gettxq, |
d9cb2596 AS |
3892 | }; |
3893 | ||
4175b88b | 3894 | void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev) |
5b435de0 AS |
3895 | { |
3896 | int ret; | |
e92eedf4 | 3897 | struct brcmf_sdio *bus; |
bbfd6a66 FL |
3898 | struct brcmf_bus_dcmd *dlst; |
3899 | u32 dngl_txglom; | |
cb7f7968 | 3900 | u32 txglomalign = 0; |
bbfd6a66 | 3901 | u8 idx; |
5b435de0 | 3902 | |
5b435de0 AS |
3903 | brcmf_dbg(TRACE, "Enter\n"); |
3904 | ||
3905 | /* We make an assumption about address window mappings: | |
3906 | * regsva == SI_ENUM_BASE*/ | |
3907 | ||
3908 | /* Allocate private bus interface state */ | |
e92eedf4 | 3909 | bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); |
5b435de0 AS |
3910 | if (!bus) |
3911 | goto fail; | |
3912 | ||
3913 | bus->sdiodev = sdiodev; | |
3914 | sdiodev->bus = bus; | |
b83db862 | 3915 | skb_queue_head_init(&bus->glom); |
5b435de0 AS |
3916 | bus->txbound = BRCMF_TXBOUND; |
3917 | bus->rxbound = BRCMF_RXBOUND; | |
3918 | bus->txminmax = BRCMF_TXMINMAX; | |
6bc52319 | 3919 | bus->tx_seq = SDPCM_SEQ_WRAP - 1; |
5b435de0 | 3920 | |
37ac5780 HM |
3921 | INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); |
3922 | bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq"); | |
3923 | if (bus->brcmf_wq == NULL) { | |
5e8149f5 | 3924 | brcmf_err("insufficient memory to create txworkqueue\n"); |
37ac5780 HM |
3925 | goto fail; |
3926 | } | |
3927 | ||
5b435de0 AS |
3928 | /* attempt to attach to the dongle */ |
3929 | if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) { | |
5e8149f5 | 3930 | brcmf_err("brcmf_sdbrcm_probe_attach failed\n"); |
5b435de0 AS |
3931 | goto fail; |
3932 | } | |
3933 | ||
dd43a01c | 3934 | spin_lock_init(&bus->rxctl_lock); |
5b435de0 AS |
3935 | spin_lock_init(&bus->txqlock); |
3936 | init_waitqueue_head(&bus->ctrl_wait); | |
3937 | init_waitqueue_head(&bus->dcmd_resp_wait); | |
3938 | ||
3939 | /* Set up the watchdog timer */ | |
3940 | init_timer(&bus->timer); | |
3941 | bus->timer.data = (unsigned long)bus; | |
3942 | bus->timer.function = brcmf_sdbrcm_watchdog; | |
3943 | ||
5b435de0 AS |
3944 | /* Initialize watchdog thread */ |
3945 | init_completion(&bus->watchdog_wait); | |
3946 | bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread, | |
3947 | bus, "brcmf_watchdog"); | |
3948 | if (IS_ERR(bus->watchdog_tsk)) { | |
02f77195 | 3949 | pr_warn("brcmf_watchdog thread failed to start\n"); |
5b435de0 AS |
3950 | bus->watchdog_tsk = NULL; |
3951 | } | |
3952 | /* Initialize DPC thread */ | |
fccfe930 | 3953 | atomic_set(&bus->dpc_tskcnt, 0); |
5b435de0 | 3954 | |
a9ffda88 | 3955 | /* Assign bus interface call back */ |
d9cb2596 AS |
3956 | bus->sdiodev->bus_if->dev = bus->sdiodev->dev; |
3957 | bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops; | |
75d907d3 AS |
3958 | bus->sdiodev->bus_if->chip = bus->ci->chip; |
3959 | bus->sdiodev->bus_if->chiprev = bus->ci->chiprev; | |
d9cb2596 | 3960 | |
706478cb FL |
3961 | /* default sdio bus header length for tx packet */ |
3962 | bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; | |
3963 | ||
3964 | /* Attach to the common layer, reserve hdr space */ | |
3965 | ret = brcmf_attach(bus->tx_hdrlen, bus->sdiodev->dev); | |
712ac5b3 | 3966 | if (ret != 0) { |
5e8149f5 | 3967 | brcmf_err("brcmf_attach failed\n"); |
5b435de0 AS |
3968 | goto fail; |
3969 | } | |
3970 | ||
3971 | /* Allocate buffers */ | |
3972 | if (!(brcmf_sdbrcm_probe_malloc(bus))) { | |
5e8149f5 | 3973 | brcmf_err("brcmf_sdbrcm_probe_malloc failed\n"); |
5b435de0 AS |
3974 | goto fail; |
3975 | } | |
3976 | ||
3977 | if (!(brcmf_sdbrcm_probe_init(bus))) { | |
5e8149f5 | 3978 | brcmf_err("brcmf_sdbrcm_probe_init failed\n"); |
5b435de0 AS |
3979 | goto fail; |
3980 | } | |
3981 | ||
80969836 | 3982 | brcmf_sdio_debugfs_create(bus); |
5b435de0 AS |
3983 | brcmf_dbg(INFO, "completed!!\n"); |
3984 | ||
bbfd6a66 FL |
3985 | /* sdio bus core specific dcmd */ |
3986 | idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV); | |
3987 | dlst = kzalloc(sizeof(struct brcmf_bus_dcmd), GFP_KERNEL); | |
c3d2bc35 FL |
3988 | if (dlst) { |
3989 | if (bus->ci->c_inf[idx].rev < 12) { | |
3990 | /* for sdio core rev < 12, disable txgloming */ | |
3991 | dngl_txglom = 0; | |
3992 | dlst->name = "bus:txglom"; | |
3993 | dlst->param = (char *)&dngl_txglom; | |
3994 | dlst->param_len = sizeof(u32); | |
3995 | } else { | |
3996 | /* otherwise, set txglomalign */ | |
cb7f7968 FL |
3997 | if (sdiodev->pdata) |
3998 | txglomalign = sdiodev->pdata->sd_sgentry_align; | |
3999 | /* SDIO ADMA requires at least 32 bit alignment */ | |
4000 | if (txglomalign < 4) | |
4001 | txglomalign = 4; | |
c3d2bc35 | 4002 | dlst->name = "bus:txglomalign"; |
cb7f7968 | 4003 | dlst->param = (char *)&txglomalign; |
c3d2bc35 FL |
4004 | dlst->param_len = sizeof(u32); |
4005 | } | |
bbfd6a66 FL |
4006 | list_add(&dlst->list, &bus->sdiodev->bus_if->dcmd_list); |
4007 | } | |
4008 | ||
5b435de0 | 4009 | /* if firmware path present try to download and bring up bus */ |
ed683c98 | 4010 | ret = brcmf_bus_start(bus->sdiodev->dev); |
5b435de0 | 4011 | if (ret != 0) { |
5e8149f5 | 4012 | brcmf_err("dongle is not responding\n"); |
1799ddf1 | 4013 | goto fail; |
5b435de0 | 4014 | } |
15d45b6f | 4015 | |
5b435de0 AS |
4016 | return bus; |
4017 | ||
4018 | fail: | |
4019 | brcmf_sdbrcm_release(bus); | |
4020 | return NULL; | |
4021 | } | |
4022 | ||
4023 | void brcmf_sdbrcm_disconnect(void *ptr) | |
4024 | { | |
e92eedf4 | 4025 | struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr; |
5b435de0 AS |
4026 | |
4027 | brcmf_dbg(TRACE, "Enter\n"); | |
4028 | ||
4029 | if (bus) | |
4030 | brcmf_sdbrcm_release(bus); | |
4031 | ||
4032 | brcmf_dbg(TRACE, "Disconnected\n"); | |
4033 | } | |
4034 | ||
5b435de0 | 4035 | void |
e92eedf4 | 4036 | brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick) |
5b435de0 | 4037 | { |
5b435de0 | 4038 | /* Totally stop the timer */ |
23677ce3 | 4039 | if (!wdtick && bus->wd_timer_valid) { |
5b435de0 AS |
4040 | del_timer_sync(&bus->timer); |
4041 | bus->wd_timer_valid = false; | |
4042 | bus->save_ms = wdtick; | |
4043 | return; | |
4044 | } | |
4045 | ||
ece960ea | 4046 | /* don't start the wd until fw is loaded */ |
712ac5b3 | 4047 | if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) |
ece960ea FL |
4048 | return; |
4049 | ||
5b435de0 AS |
4050 | if (wdtick) { |
4051 | if (bus->save_ms != BRCMF_WD_POLL_MS) { | |
23677ce3 | 4052 | if (bus->wd_timer_valid) |
5b435de0 AS |
4053 | /* Stop timer and restart at new value */ |
4054 | del_timer_sync(&bus->timer); | |
4055 | ||
4056 | /* Create timer again when watchdog period is | |
4057 | dynamically changed or in the first instance | |
4058 | */ | |
4059 | bus->timer.expires = | |
4060 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000; | |
4061 | add_timer(&bus->timer); | |
4062 | ||
4063 | } else { | |
4064 | /* Re arm the timer, at last watchdog period */ | |
4065 | mod_timer(&bus->timer, | |
4066 | jiffies + BRCMF_WD_POLL_MS * HZ / 1000); | |
4067 | } | |
4068 | ||
4069 | bus->wd_timer_valid = true; | |
4070 | bus->save_ms = wdtick; | |
4071 | } | |
4072 | } |