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iwlwifi: pcie: print less data upon firmware crash
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
553452e5
LK		 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
410dc5aa 27 * in the file called COPYING.
c85eb619
EG		 28 *
29 * Contact Information:
cb2f8277 30 * Intel Linux Wireless <linuxwifi@intel.com>
c85eb619
EG		 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
553452e5
LK		 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
afb84431 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
c85eb619
EG		 38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
a42a1844
EG		 67#include <linux/pci.h>
68#include <linux/pci-aspm.h>
e6bb4c9c 69#include <linux/interrupt.h>
87e5666c 70#include <linux/debugfs.h>
cf614297 71#include <linux/sched.h>
6d8f6eeb
EG		 72#include <linux/bitops.h>
73#include <linux/gfp.h>
48eb7b34 74#include <linux/vmalloc.h>
b3ff1270 75#include <linux/pm_runtime.h>
e6bb4c9c 76
82575102 77#include "iwl-drv.h"
c85eb619 78#include "iwl-trans.h"
522376d2
EG		 79#include "iwl-csr.h"
80#include "iwl-prph.h"
cb6bb128 81#include "iwl-scd.h"
7a10e3e4 82#include "iwl-agn-hw.h"
4d075007 83#include "iwl-fw-error-dump.h"
6468a01a 84#include "internal.h"
06d51e0d 85#include "iwl-fh.h"
0439bb62 86
fe45773b
AN		 87/* extended range in FW SRAM */
88#define IWL_FW_MEM_EXTENDED_START 0x40000
89#define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
c2d20201
EG		 91static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92{
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105}
106
96c285da 107static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
c2d20201
EG		 108{
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553452e5 110 struct page *page = NULL;
c2d20201 111 dma_addr_t phys;
96c285da 112 u32 size = 0;
c2d20201
EG		 113 u8 power;
114
96c285da
EG		 115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
c2d20201
EG		 127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
96c285da 135 for (power = max_power; power >= 11; power--) {
c2d20201
EG		 136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
553452e5 149 page = NULL;
c2d20201
EG		 150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
40a76905 158 if (WARN_ON_ONCE(!page))
c2d20201
EG		 159 return;
160
96c285da
EG		 161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
c2d20201
EG		 167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170}
171
a812cba9
AB		 172static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173{
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177}
178
179static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180{
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184}
185
ddaf5a5b 186static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 187{
66337b7c 188 if (trans->cfg->apmg_not_supported)
95411d04
AA		 189 return;
190
ddaf5a5b
JB		 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 199}
200
af634bee
EG		 201/* PCI registers */
202#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 203
7afe3705 204static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 205{
20d3b647 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 207 u16 lctl;
9180ac50 208 u16 cap;
af634bee 209
af634bee
EG		 210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
7afe3705 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 221 else
af634bee 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 230}
231
a6c684ee
EG		 232/*
233 * Start up NIC's basic functionality after it has been reset
7afe3705 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 235 * NOTE: This does not load uCode nor start the embedded processor
236 */
7afe3705 237static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 238{
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 268
7afe3705 269 iwl_pcie_apm_config(trans);
a6c684ee
EG		 270
271 /* Configure analog phase-lock-loop before activating to D0A */
77d76931
JB		 272 if (trans->cfg->base_params->pll_cfg)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
a6c684ee
EG		 274
275 /*
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
278 */
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
280
281 /*
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
285 */
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 289 if (ret < 0) {
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
291 goto out;
292 }
293
2d93aee1
EG		 294 if (trans->cfg->host_interrupt_operation_mode) {
295 /*
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
299 *
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
303 *
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
307 * seems to like it.
308 */
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
314 }
315
a6c684ee
EG		 316 /*
317 * Enable DMA clock and wait for it to stabilize.
318 *
3073d8c0
EH		 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 322 */
95411d04 323 if (!trans->cfg->apmg_not_supported) {
3073d8c0
EH		 324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
326 udelay(20);
327
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
331
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
335 }
889b1696 336
eb7ff77e 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 338
339out:
340 return ret;
341}
342
a812cba9
AB		 343/*
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
349 */
350static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
351{
352 int ret;
353 u32 apmg_gp1_reg;
354 u32 apmg_xtal_cfg_reg;
355 u32 dl_cfg_reg;
356
357 /* Force XTAL ON */
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 363 usleep_range(1000, 2000);
a812cba9
AB		 364
365 /*
366 * Set "initialization complete" bit to move adapter from
367 * D0U* --> D0A* (powered-up active) state.
368 */
369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
370
371 /*
372 * Wait for clock stabilization; once stabilized, access to
373 * device-internal resources is possible.
374 */
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
378 25000);
379 if (WARN_ON(ret < 0)) {
380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
381 /* Release XTAL ON request */
382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
384 return;
385 }
386
387 /*
388 * Clear "disable persistence" to avoid LP XTAL resetting when
389 * SHRD_HW_RST is applied in S3.
390 */
391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
392 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
393
394 /*
395 * Force APMG XTAL to be active to prevent its disabling by HW
396 * caused by APMG idle state.
397 */
398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
399 SHR_APMG_XTAL_CFG_REG);
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
401 apmg_xtal_cfg_reg |
402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
403
404 /*
405 * Reset entire device again - do controller reset (results in
406 * SHRD_HW_RST). Turn MAC off before proceeding.
407 */
408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 409 usleep_range(1000, 2000);
a812cba9
AB		 410
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
416
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
421
422 /*
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
425 */
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
428
429 /*
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
432 */
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
435
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
439
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
443 udelay(10);
444
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
447 apmg_xtal_cfg_reg &
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
449}
450
7afe3705 451static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 452{
453 int ret = 0;
454
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
457
458 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 461 if (ret < 0)
cc56feb2
EG		 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
463
464 IWL_DEBUG_INFO(trans, "stop master\n");
465
466 return ret;
467}
468
b7aaeae4 469static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 470{
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
472
b7aaeae4
EG		 473 if (op_mode_leave) {
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
476
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
c9fdec9f
EG		 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
483 CSR_RESET_LINK_PWR_MGMT_DISABLED);
b7aaeae4
EG		 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PREPARE |
486 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
c9fdec9f
EG		 487 mdelay(1);
488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
489 CSR_RESET_LINK_PWR_MGMT_DISABLED);
490 }
b7aaeae4
EG		 491 mdelay(5);
492 }
493
eb7ff77e 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 495
496 /* Stop device's DMA activity */
7afe3705 497 iwl_pcie_apm_stop_master(trans);
cc56feb2 498
a812cba9
AB		 499 if (trans->cfg->lp_xtal_workaround) {
500 iwl_pcie_apm_lp_xtal_enable(trans);
501 return;
502 }
503
cc56feb2
EG		 504 /* Reset the entire device */
505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 506 usleep_range(1000, 2000);
cc56feb2
EG		 507
508 /*
509 * Clear "initialization complete" bit to move adapter from
510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
511 */
512 iwl_clear_bit(trans, CSR_GP_CNTRL,
513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
514}
515
7afe3705 516static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 517{
7b11488f 518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 519
520 /* nic_init */
7b70bd63 521 spin_lock(&trans_pcie->irq_lock);
7afe3705 522 iwl_pcie_apm_init(trans);
392f8b78 523
7b70bd63 524 spin_unlock(&trans_pcie->irq_lock);
392f8b78 525
95411d04 526 iwl_pcie_set_pwr(trans, false);
392f8b78 527
ecdb975c 528 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 529
530 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 531 iwl_pcie_rx_init(trans);
392f8b78
EG		 532
533 /* Allocate or reset and init all Tx and Command queues */
f02831be 534 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 535 return -ENOMEM;
536
035f7ff2 537 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 538 /* enable shadow regs in HW */
20d3b647 539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 541 }
542
392f8b78
EG		 543 return 0;
544}
545
546#define HW_READY_TIMEOUT (50)
547
548/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 549static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 550{
551 int ret;
552
1042db2a 553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 555
556 /* See if we got it */
1042db2a 557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
560 HW_READY_TIMEOUT);
392f8b78 561
6a08f514
EG		 562 if (ret >= 0)
563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
564
6d8f6eeb 565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 566 return ret;
567}
568
569/* Note: returns standard 0/-ERROR code */
7afe3705 570static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 571{
572 int ret;
289e5501 573 int t = 0;
501fd989 574 int iter;
392f8b78 575
6d8f6eeb 576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 577
7afe3705 578 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 579 /* If the card is ready, exit 0 */
392f8b78
EG		 580 if (ret >= 0)
581 return 0;
582
c9fdec9f
EG		 583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
584 CSR_RESET_LINK_PWR_MGMT_DISABLED);
192185d6 585 usleep_range(1000, 2000);
c9fdec9f 586
501fd989
EG		 587 for (iter = 0; iter < 10; iter++) {
588 /* If HW is not ready, prepare the conditions to check again */
589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
590 CSR_HW_IF_CONFIG_REG_PREPARE);
591
592 do {
593 ret = iwl_pcie_set_hw_ready(trans);
03a19cbb
EG		 594 if (ret >= 0)
595 return 0;
392f8b78 596
501fd989
EG		 597 usleep_range(200, 1000);
598 t += 200;
599 } while (t < 150000);
600 msleep(25);
601 }
392f8b78 602
7f2ac8fb 603 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 604
392f8b78
EG		 605 return ret;
606}
607
cf614297
EG		 608/*
609 * ucode
610 */
564cdce7
SS		 611static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
612 u32 dst_addr, dma_addr_t phy_addr,
613 u32 byte_cnt)
cf614297 614{
bac842da
EG		 615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
617
618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
619 dst_addr);
620
621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
623
624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
625 (iwl_get_dma_hi_addr(phy_addr)
626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
627
628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
632
633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
564cdce7
SS		 637}
638
639static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans,
640 u32 dst_addr, dma_addr_t phy_addr,
641 u32 byte_cnt)
642{
643 /* Stop DMA channel */
644 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0);
645
646 /* Configure SRAM address */
647 iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR,
648 dst_addr);
649
650 /* Configure DRAM address - 64 bit */
651 iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr);
bac842da 652
564cdce7
SS		 653 /* Configure byte count to transfer */
654 iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt);
655
656 /* Enable the DRAM2SRAM to start */
657 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP |
658 TFH_SRV_DMA_TO_DRIVER |
659 TFH_SRV_DMA_START);
660}
661
662static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
663 u32 dst_addr, dma_addr_t phy_addr,
664 u32 byte_cnt)
665{
666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
667 unsigned long flags;
668 int ret;
669
670 trans_pcie->ucode_write_complete = false;
671
672 if (!iwl_trans_grab_nic_access(trans, &flags))
673 return -EIO;
674
675 if (trans->cfg->use_tfh)
676 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr,
677 byte_cnt);
678 else
679 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
680 byte_cnt);
bac842da 681 iwl_trans_release_nic_access(trans, &flags);
cf614297 682
13df1aab
JB		 683 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
684 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 685 if (!ret) {
83f84d7b 686 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 687 return -ETIMEDOUT;
688 }
689
690 return 0;
691}
692
7afe3705 693static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 694 const struct fw_desc *section)
cf614297 695{
83f84d7b
JB		 696 u8 *v_addr;
697 dma_addr_t p_addr;
baa21e83 698 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 699 int ret = 0;
700
83f84d7b
JB		 701 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
702 section_num);
703
c571573a
EG		 704 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
705 GFP_KERNEL | __GFP_NOWARN);
706 if (!v_addr) {
707 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
708 chunk_sz = PAGE_SIZE;
709 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
710 &p_addr, GFP_KERNEL);
711 if (!v_addr)
712 return -ENOMEM;
713 }
83f84d7b 714
c571573a 715 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 716 u32 copy_size, dst_addr;
717 bool extended_addr = false;
83f84d7b 718
c571573a 719 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 720 dst_addr = section->offset + offset;
721
722 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
723 dst_addr <= IWL_FW_MEM_EXTENDED_END)
724 extended_addr = true;
725
726 if (extended_addr)
727 iwl_set_bits_prph(trans, LMPM_CHICK,
728 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 729
83f84d7b 730 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 731 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
732 copy_size);
733
734 if (extended_addr)
735 iwl_clear_bits_prph(trans, LMPM_CHICK,
736 LMPM_CHICK_EXTENDED_ADDR_SPACE);
737
83f84d7b
JB		 738 if (ret) {
739 IWL_ERR(trans,
740 "Could not load the [%d] uCode section\n",
741 section_num);
742 break;
6dfa8d01 743 }
83f84d7b
JB		 744 }
745
c571573a 746 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 747 return ret;
748}
749
16bc119b
EH		 750/*
751 * Driver Takes the ownership on secure machine before FW load
752 * and prevent race with the BT load.
753 * W/A for ROM bug. (should be remove in the next Si step)
754 */
755static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
756{
757 u32 val, loop = 1000;
758
1e167071
EH		 759 /*
760 * Check the RSA semaphore is accessible.
761 * If the HW isn't locked and the rsa semaphore isn't accessible,
762 * we are in trouble.
763 */
16bc119b
EH		 764 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
765 if (val & (BIT(1) | BIT(17))) {
9fc515bc
EG		 766 IWL_DEBUG_INFO(trans,
767 "can't access the RSA semaphore it is write protected\n");
16bc119b
EH		 768 return 0;
769 }
770
771 /* take ownership on the AUX IF */
772 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
773 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
774
775 do {
776 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
777 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
778 if (val == 0x1) {
779 iwl_write_prph(trans, RSA_ENABLE, 0);
780 return 0;
781 }
782
783 udelay(10);
784 loop--;
785 } while (loop > 0);
786
787 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
788 return -EIO;
789}
790
5dd9c68a
EG		 791static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
792 const struct fw_img *image,
793 int cpu,
794 int *first_ucode_section)
e2d6f4e7
EH		 795{
796 int shift_param;
dcab8ecd
EH		 797 int i, ret = 0, sec_num = 0x1;
798 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 799
800 if (cpu == 1) {
801 shift_param = 0;
034846cf 802 *first_ucode_section = 0;
e2d6f4e7
EH		 803 } else {
804 shift_param = 16;
034846cf 805 (*first_ucode_section)++;
e2d6f4e7
EH		 806 }
807
eef187a7 808 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 809 last_read_idx = i;
810
a6c4fb44
MG		 811 /*
812 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
813 * CPU1 to CPU2.
814 * PAGING_SEPARATOR_SECTION delimiter - separate between
815 * CPU2 non paged to CPU2 paging sec.
816 */
034846cf 817 if (!image->sec[i].data ||
a6c4fb44
MG		 818 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
819 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 820 IWL_DEBUG_FW(trans,
821 "Break since Data not valid or Empty section, sec = %d\n",
822 i);
189fa2fa 823 break;
034846cf
EH		 824 }
825
189fa2fa
EH		 826 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
827 if (ret)
828 return ret;
dcab8ecd 829
d6a2c5c7
SS		 830 /* Notify ucode of loaded section number and status */
831 if (trans->cfg->use_tfh) {
832 val = iwl_read_prph(trans, UREG_UCODE_LOAD_STATUS);
833 val = val | (sec_num << shift_param);
834 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, val);
835 } else {
836 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
837 val = val | (sec_num << shift_param);
838 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
839 }
dcab8ecd 840 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 841 }
842
034846cf
EH		 843 *first_ucode_section = last_read_idx;
844
2aabdbdc
EG		 845 iwl_enable_interrupts(trans);
846
d6a2c5c7
SS		 847 if (trans->cfg->use_tfh) {
848 if (cpu == 1)
849 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
850 0xFFFF);
851 else
852 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
853 0xFFFFFFFF);
854 } else {
855 if (cpu == 1)
856 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
857 0xFFFF);
858 else
859 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
860 0xFFFFFFFF);
861 }
afb88917 862
189fa2fa
EH		 863 return 0;
864}
e2d6f4e7 865
189fa2fa
EH		 866static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
867 const struct fw_img *image,
034846cf
EH		 868 int cpu,
869 int *first_ucode_section)
189fa2fa 870{
189fa2fa 871 int i, ret = 0;
034846cf 872 u32 last_read_idx = 0;
189fa2fa 873
3ce4a038 874 if (cpu == 1)
034846cf 875 *first_ucode_section = 0;
3ce4a038 876 else
034846cf 877 (*first_ucode_section)++;
189fa2fa 878
eef187a7 879 for (i = *first_ucode_section; i < image->num_sec; i++) {
034846cf
EH		 880 last_read_idx = i;
881
a6c4fb44
MG		 882 /*
883 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
884 * CPU1 to CPU2.
885 * PAGING_SEPARATOR_SECTION delimiter - separate between
886 * CPU2 non paged to CPU2 paging sec.
887 */
034846cf 888 if (!image->sec[i].data ||
a6c4fb44
MG		 889 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
890 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
034846cf
EH		 891 IWL_DEBUG_FW(trans,
892 "Break since Data not valid or Empty section, sec = %d\n",
893 i);
189fa2fa 894 break;
034846cf
EH		 895 }
896
189fa2fa
EH		 897 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
898 if (ret)
899 return ret;
e2d6f4e7
EH		 900 }
901
034846cf
EH		 902 *first_ucode_section = last_read_idx;
903
e2d6f4e7
EH		 904 return 0;
905}
906
09e350f7
LK		 907static void iwl_pcie_apply_destination(struct iwl_trans *trans)
908{
909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
910 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
911 int i;
912
913 if (dest->version)
914 IWL_ERR(trans,
915 "DBG DEST version is %d - expect issues\n",
916 dest->version);
917
918 IWL_INFO(trans, "Applying debug destination %s\n",
919 get_fw_dbg_mode_string(dest->monitor_mode));
920
921 if (dest->monitor_mode == EXTERNAL_MODE)
96c285da 922 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
09e350f7
LK		 923 else
924 IWL_WARN(trans, "PCI should have external buffer debug\n");
925
926 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
927 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
928 u32 val = le32_to_cpu(dest->reg_ops[i].val);
929
930 switch (dest->reg_ops[i].op) {
931 case CSR_ASSIGN:
932 iwl_write32(trans, addr, val);
933 break;
934 case CSR_SETBIT:
935 iwl_set_bit(trans, addr, BIT(val));
936 break;
937 case CSR_CLEARBIT:
938 iwl_clear_bit(trans, addr, BIT(val));
939 break;
940 case PRPH_ASSIGN:
941 iwl_write_prph(trans, addr, val);
942 break;
943 case PRPH_SETBIT:
944 iwl_set_bits_prph(trans, addr, BIT(val));
945 break;
946 case PRPH_CLEARBIT:
947 iwl_clear_bits_prph(trans, addr, BIT(val));
948 break;
869f3b15
HD		 949 case PRPH_BLOCKBIT:
950 if (iwl_read_prph(trans, addr) & BIT(val)) {
951 IWL_ERR(trans,
952 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
953 val, addr);
954 goto monitor;
955 }
956 break;
09e350f7
LK		 957 default:
958 IWL_ERR(trans, "FW debug - unknown OP %d\n",
959 dest->reg_ops[i].op);
960 break;
961 }
962 }
963
869f3b15 964monitor:
09e350f7
LK		 965 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
966 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
967 trans_pcie->fw_mon_phys >> dest->base_shift);
62d7476d
EG		 968 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
969 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
970 (trans_pcie->fw_mon_phys +
971 trans_pcie->fw_mon_size - 256) >>
972 dest->end_shift);
973 else
974 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
975 (trans_pcie->fw_mon_phys +
976 trans_pcie->fw_mon_size) >>
977 dest->end_shift);
09e350f7
LK		 978 }
979}
980
7afe3705 981static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 982 const struct fw_img *image)
cf614297 983{
c2d20201 984 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 985 int ret = 0;
034846cf 986 int first_ucode_section;
cf614297 987
dcab8ecd 988 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 989 image->is_dual_cpus ? "Dual" : "Single");
990
dcab8ecd
EH		 991 /* load to FW the binary non secured sections of CPU1 */
992 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
993 if (ret)
994 return ret;
e2d6f4e7
EH		 995
996 if (image->is_dual_cpus) {
189fa2fa
EH		 997 /* set CPU2 header address */
998 iwl_write_prph(trans,
999 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1000 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 1001
189fa2fa 1002 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 1003 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1004 &first_ucode_section);
189fa2fa
EH		 1005 if (ret)
1006 return ret;
e2d6f4e7 1007 }
cf614297 1008
c2d20201
EG		 1009 /* supported for 7000 only for the moment */
1010 if (iwlwifi_mod_params.fw_monitor &&
1011 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
96c285da 1012 iwl_pcie_alloc_fw_monitor(trans, 0);
c2d20201
EG		 1013
1014 if (trans_pcie->fw_mon_size) {
1015 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1016 trans_pcie->fw_mon_phys >> 4);
1017 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1018 (trans_pcie->fw_mon_phys +
1019 trans_pcie->fw_mon_size) >> 4);
1020 }
09e350f7
LK		 1021 } else if (trans->dbg_dest_tlv) {
1022 iwl_pcie_apply_destination(trans);
c2d20201
EG		 1023 }
1024
2aabdbdc
EG		 1025 iwl_enable_interrupts(trans);
1026
e12ba844 1027 /* release CPU reset */
5dd9c68a 1028 iwl_write32(trans, CSR_RESET, 0);
e12ba844 1029
dcab8ecd
EH		 1030 return 0;
1031}
189fa2fa 1032
5dd9c68a
EG		 1033static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1034 const struct fw_img *image)
dcab8ecd
EH		 1035{
1036 int ret = 0;
1037 int first_ucode_section;
dcab8ecd
EH		 1038
1039 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1040 image->is_dual_cpus ? "Dual" : "Single");
1041
a2227ce2
EG		 1042 if (trans->dbg_dest_tlv)
1043 iwl_pcie_apply_destination(trans);
1044
16bc119b
EH		 1045 /* TODO: remove in the next Si step */
1046 ret = iwl_pcie_rsa_race_bug_wa(trans);
1047 if (ret)
1048 return ret;
1049
dcab8ecd
EH		 1050 /* configure the ucode to be ready to get the secured image */
1051 /* release CPU reset */
1052 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1053
1054 /* load to FW the binary Secured sections of CPU1 */
5dd9c68a
EG		 1055 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1056 &first_ucode_section);
dcab8ecd
EH		 1057 if (ret)
1058 return ret;
1059
1060 /* load to FW the binary sections of CPU2 */
47dbab26
EG		 1061 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1062 &first_ucode_section);
cf614297
EG		 1063}
1064
727c02df
SS		 1065static bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans)
1066{
1067 bool hw_rfkill = iwl_is_rfkill_set(trans);
1068
1069 if (hw_rfkill)
1070 set_bit(STATUS_RFKILL, &trans->status);
1071 else
1072 clear_bit(STATUS_RFKILL, &trans->status);
1073
1074 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1075
1076 return hw_rfkill;
1077}
1078
7ca00409
HD		 1079struct iwl_causes_list {
1080 u32 cause_num;
1081 u32 mask_reg;
1082 u8 addr;
1083};
1084
1085static struct iwl_causes_list causes_list[] = {
1086 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1087 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1088 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1089 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1090 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1091 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1092 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1093 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1094 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1095 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1096 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1097 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1098 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1099 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1100};
1101
1102static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1103{
1104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1105 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1106 int i;
1107
1108 /*
1109 * Access all non RX causes and map them to the default irq.
1110 * In case we are missing at least one interrupt vector,
1111 * the first interrupt vector will serve non-RX and FBQ causes.
1112 */
1113 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1114 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1115 iwl_clear_bit(trans, causes_list[i].mask_reg,
1116 causes_list[i].cause_num);
1117 }
1118}
1119
1120static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1121{
1122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1123 u32 offset =
1124 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1125 u32 val, idx;
1126
1127 /*
1128 * The first RX queue - fallback queue, which is designated for
1129 * management frame, command responses etc, is always mapped to the
1130 * first interrupt vector. The other RX queues are mapped to
1131 * the other (N - 2) interrupt vectors.
1132 */
1133 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1134 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1135 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1136 MSIX_FH_INT_CAUSES_Q(idx - offset));
1137 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1138 }
1139 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1140
1141 val = MSIX_FH_INT_CAUSES_Q(0);
1142 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1143 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1144 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1145
1146 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1147 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1148}
1149
83730058 1150static void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
7ca00409
HD		 1151{
1152 struct iwl_trans *trans = trans_pcie->trans;
1153
1154 if (!trans_pcie->msix_enabled) {
d7270d61
HD		 1155 if (trans->cfg->mq_rx_supported &&
1156 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
7ca00409
HD		 1157 iwl_write_prph(trans, UREG_CHICK,
1158 UREG_CHICK_MSI_ENABLE);
1159 return;
1160 }
d7270d61
HD		 1161 /*
1162 * The IVAR table needs to be configured again after reset,
1163 * but if the device is disabled, we can't write to
1164 * prph.
1165 */
1166 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1167 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
7ca00409
HD		 1168
1169 /*
1170 * Each cause from the causes list above and the RX causes is
1171 * represented as a byte in the IVAR table. The first nibble
1172 * represents the bound interrupt vector of the cause, the second
1173 * represents no auto clear for this cause. This will be set if its
1174 * interrupt vector is bound to serve other causes.
1175 */
1176 iwl_pcie_map_rx_causes(trans);
1177
1178 iwl_pcie_map_non_rx_causes(trans);
83730058
HD		 1179}
1180
1181static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1182{
1183 struct iwl_trans *trans = trans_pcie->trans;
1184
1185 iwl_pcie_conf_msix_hw(trans_pcie);
7ca00409 1186
83730058
HD		 1187 if (!trans_pcie->msix_enabled)
1188 return;
1189
1190 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
7ca00409 1191 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
83730058 1192 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
7ca00409
HD		 1193 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1194}
1195
fa9f3281 1196static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
ae2c30bf 1197{
43e58856 1198 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1199 bool hw_rfkill, was_hw_rfkill;
1200
fa9f3281
EG		 1201 lockdep_assert_held(&trans_pcie->mutex);
1202
1203 if (trans_pcie->is_down)
1204 return;
1205
1206 trans_pcie->is_down = true;
1207
3dc3374f 1208 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1209
43e58856 1210 /* tell the device to stop sending interrupts */
ae2c30bf 1211 iwl_disable_interrupts(trans);
ae2c30bf 1212
ab6cf8e8 1213 /* device going down, Stop using ICT table */
990aa6d7 1214 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1215
1216 /*
1217 * If a HW restart happens during firmware loading,
1218 * then the firmware loading might call this function
1219 * and later it might be called again due to the
1220 * restart. So don't process again if the device is
1221 * already dead.
1222 */
31b8b343 1223 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
a6bd005f
EG		 1224 IWL_DEBUG_INFO(trans,
1225 "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1226 iwl_pcie_tx_stop(trans);
9805c446 1227 iwl_pcie_rx_stop(trans);
6379103e 1228
ab6cf8e8 1229 /* Power-down device's busmaster DMA clocks */
95411d04 1230 if (!trans->cfg->apmg_not_supported) {
1aa02b5a
AA		 1231 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1232 APMG_CLK_VAL_DMA_CLK_RQT);
1233 udelay(5);
1234 }
ab6cf8e8
EG		 1235 }
1236
1237 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1238 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1239 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1240
1241 /* Stop the device, and put it in low power state */
b7aaeae4 1242 iwl_pcie_apm_stop(trans, false);
43e58856 1243
03d6c3b0
EG		 1244 /* stop and reset the on-board processor */
1245 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1246 usleep_range(1000, 2000);
03d6c3b0 1247
f4a1f04a
GBA		 1248 /*
1249 * Upon stop, the IVAR table gets erased, so msi-x won't
1250 * work. This causes a bug in RF-KILL flows, since the interrupt
1251 * that enables radio won't fire on the correct irq, and the
1252 * driver won't be able to handle the interrupt.
1253 * Configure the IVAR table again after reset.
1254 */
1255 iwl_pcie_conf_msix_hw(trans_pcie);
1256
03d6c3b0
EG		 1257 /*
1258 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1259 * This is a bug in certain verions of the hardware.
1260 * Certain devices also keep sending HW RF kill interrupt all
1261 * the time, unless the interrupt is ACKed even if the interrupt
1262 * should be masked. Re-ACK all the interrupts here.
43e58856 1263 */
43e58856 1264 iwl_disable_interrupts(trans);
43e58856 1265
74fda971 1266 /* clear all status bits */
eb7ff77e
AN		 1267 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1268 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1269 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1270 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1271
1272 /*
1273 * Even if we stop the HW, we still want the RF kill
1274 * interrupt
1275 */
1276 iwl_enable_rfkill_int(trans);
1277
1278 /*
1279 * Check again since the RF kill state may have changed while
1280 * all the interrupts were disabled, in this case we couldn't
1281 * receive the RF kill interrupt and update the state in the
1282 * op_mode.
3dc3374f
EG		 1283 * Don't call the op_mode if the rkfill state hasn't changed.
1284 * This allows the op_mode to call stop_device from the rfkill
1285 * notification without endless recursion. Under very rare
1286 * circumstances, we might have a small recursion if the rfkill
1287 * state changed exactly now while we were called from stop_device.
1288 * This is very unlikely but can happen and is supported.
a4082843
AN		 1289 */
1290 hw_rfkill = iwl_is_rfkill_set(trans);
1291 if (hw_rfkill)
eb7ff77e 1292 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1293 else
eb7ff77e 1294 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1295 if (hw_rfkill != was_hw_rfkill)
14cfca71 1296 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0 1297
a6bd005f 1298 /* re-take ownership to prevent other users from stealing the device */
655e5cf0 1299 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1300}
1301
2e5d4a8f
HD		 1302static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1303{
1304 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1305
1306 if (trans_pcie->msix_enabled) {
1307 int i;
1308
496d83ca 1309 for (i = 0; i < trans_pcie->alloc_vecs; i++)
2e5d4a8f
HD		 1310 synchronize_irq(trans_pcie->msix_entries[i].vector);
1311 } else {
1312 synchronize_irq(trans_pcie->pci_dev->irq);
1313 }
1314}
1315
a6bd005f
EG		 1316static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1317 const struct fw_img *fw, bool run_in_rfkill)
1318{
1319 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1320 bool hw_rfkill;
1321 int ret;
1322
1323 /* This may fail if AMT took ownership of the device */
1324 if (iwl_pcie_prepare_card_hw(trans)) {
1325 IWL_WARN(trans, "Exit HW not ready\n");
1326 ret = -EIO;
1327 goto out;
1328 }
1329
1330 iwl_enable_rfkill_int(trans);
1331
1332 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1333
1334 /*
1335 * We enabled the RF-Kill interrupt and the handler may very
1336 * well be running. Disable the interrupts to make sure no other
1337 * interrupt can be fired.
1338 */
1339 iwl_disable_interrupts(trans);
1340
1341 /* Make sure it finished running */
2e5d4a8f 1342 iwl_pcie_synchronize_irqs(trans);
a6bd005f
EG		 1343
1344 mutex_lock(&trans_pcie->mutex);
1345
1346 /* If platform's RF_KILL switch is NOT set to KILL */
727c02df 1347 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
a6bd005f
EG		 1348 if (hw_rfkill && !run_in_rfkill) {
1349 ret = -ERFKILL;
1350 goto out;
1351 }
1352
1353 /* Someone called stop_device, don't try to start_fw */
1354 if (trans_pcie->is_down) {
1355 IWL_WARN(trans,
1356 "Can't start_fw since the HW hasn't been started\n");
20aa99bb 1357 ret = -EIO;
a6bd005f
EG		 1358 goto out;
1359 }
1360
1361 /* make sure rfkill handshake bits are cleared */
1362 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1363 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1364 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1365
1366 /* clear (again), then enable host interrupts */
1367 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1368
1369 ret = iwl_pcie_nic_init(trans);
1370 if (ret) {
1371 IWL_ERR(trans, "Unable to init nic\n");
1372 goto out;
1373 }
1374
1375 /*
1376 * Now, we load the firmware and don't want to be interrupted, even
1377 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1378 * FH_TX interrupt which is needed to load the firmware). If the
1379 * RF-Kill switch is toggled, we will find out after having loaded
1380 * the firmware and return the proper value to the caller.
1381 */
1382 iwl_enable_fw_load_int(trans);
1383
1384 /* really make sure rfkill handshake bits are cleared */
1385 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1386 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1387
1388 /* Load the given image to the HW */
1389 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1390 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1391 else
1392 ret = iwl_pcie_load_given_ucode(trans, fw);
a6bd005f
EG		 1393
1394 /* re-check RF-Kill state since we may have missed the interrupt */
727c02df 1395 hw_rfkill = iwl_trans_check_hw_rf_kill(trans);
a6bd005f
EG		 1396 if (hw_rfkill && !run_in_rfkill)
1397 ret = -ERFKILL;
1398
1399out:
1400 mutex_unlock(&trans_pcie->mutex);
1401 return ret;
1402}
1403
1404static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1405{
1406 iwl_pcie_reset_ict(trans);
1407 iwl_pcie_tx_start(trans, scd_addr);
1408}
1409
fa9f3281
EG		 1410static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1411{
1412 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1413
1414 mutex_lock(&trans_pcie->mutex);
1415 _iwl_trans_pcie_stop_device(trans, low_power);
1416 mutex_unlock(&trans_pcie->mutex);
1417}
1418
14cfca71
JB		 1419void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1420{
fa9f3281
EG		 1421 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1422 IWL_TRANS_GET_PCIE_TRANS(trans);
1423
1424 lockdep_assert_held(&trans_pcie->mutex);
1425
14cfca71 1426 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
fa9f3281 1427 _iwl_trans_pcie_stop_device(trans, true);
ab6cf8e8
EG		 1428}
1429
23ae6128
MG		 1430static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1431 bool reset)
2dd4f9f7 1432{
23ae6128 1433 if (!reset) {
6dfb36c8
EP		 1434 /* Enable persistence mode to avoid reset */
1435 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1436 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1437 }
1438
2dd4f9f7 1439 iwl_disable_interrupts(trans);
debff618
JB		 1440
1441 /*
1442 * in testing mode, the host stays awake and the
1443 * hardware won't be reset (not even partially)
1444 */
1445 if (test)
1446 return;
1447
ddaf5a5b
JB		 1448 iwl_pcie_disable_ict(trans);
1449
2e5d4a8f 1450 iwl_pcie_synchronize_irqs(trans);
33b56af1 1451
2dd4f9f7
JB		 1452 iwl_clear_bit(trans, CSR_GP_CNTRL,
1453 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1454 iwl_clear_bit(trans, CSR_GP_CNTRL,
1455 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1456
1316d595
SS		 1457 iwl_pcie_enable_rx_wake(trans, false);
1458
23ae6128 1459 if (reset) {
6dfb36c8
EP		 1460 /*
1461 * reset TX queues -- some of their registers reset during S3
1462 * so if we don't reset everything here the D3 image would try
1463 * to execute some invalid memory upon resume
1464 */
1465 iwl_trans_pcie_tx_reset(trans);
1466 }
ddaf5a5b
JB		 1467
1468 iwl_pcie_set_pwr(trans, true);
1469}
1470
1471static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618 1472 enum iwl_d3_status *status,
23ae6128 1473 bool test, bool reset)
ddaf5a5b 1474{
d7270d61 1475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
ddaf5a5b
JB		 1476 u32 val;
1477 int ret;
1478
debff618
JB		 1479 if (test) {
1480 iwl_enable_interrupts(trans);
1481 *status = IWL_D3_STATUS_ALIVE;
1482 return 0;
1483 }
1484
1316d595
SS		 1485 iwl_pcie_enable_rx_wake(trans, true);
1486
ddaf5a5b 1487 /*
d7270d61
HD		 1488 * Reconfigure IVAR table in case of MSIX or reset ict table in
1489 * MSI mode since HW reset erased it.
1490 * Also enables interrupts - none will happen as
1491 * the device doesn't know we're waking it up, only when
1492 * the opmode actually tells it after this call.
ddaf5a5b 1493 */
d7270d61
HD		 1494 iwl_pcie_conf_msix_hw(trans_pcie);
1495 if (!trans_pcie->msix_enabled)
1496 iwl_pcie_reset_ict(trans);
18dcb9a9 1497 iwl_enable_interrupts(trans);
ddaf5a5b
JB		 1498
1499 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1500 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1501
01e58a28
EG		 1502 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1503 udelay(2);
1504
ddaf5a5b
JB		 1505 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1506 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1507 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1508 25000);
7f2ac8fb 1509 if (ret < 0) {
ddaf5a5b
JB		 1510 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1511 return ret;
1512 }
1513
a3ead656
EG		 1514 iwl_pcie_set_pwr(trans, false);
1515
23ae6128 1516 if (!reset) {
6dfb36c8
EP		 1517 iwl_clear_bit(trans, CSR_GP_CNTRL,
1518 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1519 } else {
1520 iwl_trans_pcie_tx_reset(trans);
ddaf5a5b 1521
6dfb36c8
EP		 1522 ret = iwl_pcie_rx_init(trans);
1523 if (ret) {
1524 IWL_ERR(trans,
1525 "Failed to resume the device (RX reset)\n");
1526 return ret;
1527 }
ddaf5a5b
JB		 1528 }
1529
a3ead656
EG		 1530 val = iwl_read32(trans, CSR_RESET);
1531 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1532 *status = IWL_D3_STATUS_RESET;
1533 else
1534 *status = IWL_D3_STATUS_ALIVE;
1535
ddaf5a5b 1536 return 0;
2dd4f9f7
JB		 1537}
1538
2e5d4a8f
HD		 1539static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1540 struct iwl_trans *trans)
1541{
1542 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
9fb064df 1543 int max_irqs, num_irqs, i, ret, nr_online_cpus;
2e5d4a8f 1544 u16 pci_cmd;
2e5d4a8f 1545
06f4b081
SS		 1546 if (!trans->cfg->mq_rx_supported)
1547 goto enable_msi;
1548
9fb064df
HD		 1549 nr_online_cpus = num_online_cpus();
1550 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
06f4b081
SS		 1551 for (i = 0; i < max_irqs; i++)
1552 trans_pcie->msix_entries[i].entry = i;
496d83ca 1553
06f4b081
SS		 1554 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1555 MSIX_MIN_INTERRUPT_VECTORS,
1556 max_irqs);
1557 if (num_irqs < 0) {
2e5d4a8f 1558 IWL_DEBUG_INFO(trans,
06f4b081
SS		 1559 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1560 num_irqs);
1561 goto enable_msi;
1562 }
1563 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
496d83ca 1564
06f4b081
SS		 1565 IWL_DEBUG_INFO(trans,
1566 "MSI-X enabled. %d interrupt vectors were allocated\n",
1567 num_irqs);
1568
1569 /*
1570 * In case the OS provides fewer interrupts than requested, different
1571 * causes will share the same interrupt vector as follows:
1572 * One interrupt less: non rx causes shared with FBQ.
1573 * Two interrupts less: non rx causes shared with FBQ and RSS.
1574 * More than two interrupts: we will use fewer RSS queues.
1575 */
9fb064df 1576 if (num_irqs <= nr_online_cpus) {
06f4b081
SS		 1577 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1578 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1579 IWL_SHARED_IRQ_FIRST_RSS;
9fb064df 1580 } else if (num_irqs == nr_online_cpus + 1) {
06f4b081
SS		 1581 trans_pcie->trans->num_rx_queues = num_irqs;
1582 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1583 } else {
1584 trans_pcie->trans->num_rx_queues = num_irqs - 1;
2e5d4a8f
HD		 1585 }
1586
06f4b081
SS		 1587 trans_pcie->alloc_vecs = num_irqs;
1588 trans_pcie->msix_enabled = true;
1589 return;
1590
1591enable_msi:
1592 ret = pci_enable_msi(pdev);
1593 if (ret) {
1594 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
2e5d4a8f
HD		 1595 /* enable rfkill interrupt: hw bug w/a */
1596 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1597 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1598 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1599 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1600 }
1601 }
1602}
1603
7c8d91eb
HD		 1604static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1605{
1606 int iter_rx_q, i, ret, cpu, offset;
1607 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1608
1609 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1610 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1611 offset = 1 + i;
1612 for (; i < iter_rx_q ; i++) {
1613 /*
1614 * Get the cpu prior to the place to search
1615 * (i.e. return will be > i - 1).
1616 */
1617 cpu = cpumask_next(i - offset, cpu_online_mask);
1618 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1619 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1620 &trans_pcie->affinity_mask[i]);
1621 if (ret)
1622 IWL_ERR(trans_pcie->trans,
1623 "Failed to set affinity mask for IRQ %d\n",
1624 i);
1625 }
1626}
1627
64fa3aff
SD		 1628static const char *queue_name(struct device *dev,
1629 struct iwl_trans_pcie *trans_p, int i)
1630{
1631 if (trans_p->shared_vec_mask) {
1632 int vec = trans_p->shared_vec_mask &
1633 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1634
1635 if (i == 0)
1636 return DRV_NAME ": shared IRQ";
1637
1638 return devm_kasprintf(dev, GFP_KERNEL,
1639 DRV_NAME ": queue %d", i + vec);
1640 }
1641 if (i == 0)
1642 return DRV_NAME ": default queue";
1643
1644 if (i == trans_p->alloc_vecs - 1)
1645 return DRV_NAME ": exception";
1646
1647 return devm_kasprintf(dev, GFP_KERNEL,
1648 DRV_NAME ": queue %d", i);
1649}
1650
2e5d4a8f
HD		 1651static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1652 struct iwl_trans_pcie *trans_pcie)
1653{
496d83ca 1654 int i;
2e5d4a8f 1655
496d83ca 1656 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2e5d4a8f 1657 int ret;
5a41a86c 1658 struct msix_entry *msix_entry;
64fa3aff
SD		 1659 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1660
1661 if (!qname)
1662 return -ENOMEM;
5a41a86c
SD		 1663
1664 msix_entry = &trans_pcie->msix_entries[i];
1665 ret = devm_request_threaded_irq(&pdev->dev,
1666 msix_entry->vector,
1667 iwl_pcie_msix_isr,
1668 (i == trans_pcie->def_irq) ?
1669 iwl_pcie_irq_msix_handler :
1670 iwl_pcie_irq_rx_msix_handler,
1671 IRQF_SHARED,
64fa3aff 1672 qname,
5a41a86c 1673 msix_entry);
2e5d4a8f 1674 if (ret) {
2e5d4a8f
HD		 1675 IWL_ERR(trans_pcie->trans,
1676 "Error allocating IRQ %d\n", i);
5a41a86c 1677
2e5d4a8f
HD		 1678 return ret;
1679 }
1680 }
7c8d91eb 1681 iwl_pcie_irq_set_affinity(trans_pcie->trans);
2e5d4a8f
HD		 1682
1683 return 0;
1684}
1685
fa9f3281 1686static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
e6bb4c9c 1687{
fa9f3281 1688 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a8b691e6 1689 int err;
e6bb4c9c 1690
fa9f3281
EG		 1691 lockdep_assert_held(&trans_pcie->mutex);
1692
7afe3705 1693 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1694 if (err) {
d6f1c316 1695 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1696 return err;
ebb7678d 1697 }
a6c684ee 1698
2997494f 1699 /* Reset the entire device */
ce836c76 1700 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b7a08b28 1701 usleep_range(1000, 2000);
2997494f 1702
7afe3705 1703 iwl_pcie_apm_init(trans);
a6c684ee 1704
2e5d4a8f 1705 iwl_pcie_init_msix(trans_pcie);
83730058 1706
226c02ca
EG		 1707 /* From now on, the op_mode will be kept updated about RF kill state */
1708 iwl_enable_rfkill_int(trans);
1709
fa9f3281
EG		 1710 /* Set is_down to false here so that...*/
1711 trans_pcie->is_down = false;
1712
727c02df
SS		 1713 /* ...rfkill can call stop_device and set it false if needed */
1714 iwl_trans_check_hw_rf_kill(trans);
d48e2074 1715
4cbb8e50
LC		 1716 /* Make sure we sync here, because we'll need full access later */
1717 if (low_power)
1718 pm_runtime_resume(trans->dev);
1719
a8b691e6 1720 return 0;
e6bb4c9c
EG		 1721}
1722
fa9f3281
EG		 1723static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1724{
1725 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1726 int ret;
1727
1728 mutex_lock(&trans_pcie->mutex);
1729 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1730 mutex_unlock(&trans_pcie->mutex);
1731
1732 return ret;
1733}
1734
a4082843 1735static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1736{
20d3b647 1737 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1738
fa9f3281
EG		 1739 mutex_lock(&trans_pcie->mutex);
1740
a4082843 1741 /* disable interrupts - don't enable HW RF kill interrupt */
ee7d737c 1742 iwl_disable_interrupts(trans);
ee7d737c 1743
b7aaeae4 1744 iwl_pcie_apm_stop(trans, true);
cc56feb2 1745
218733cf 1746 iwl_disable_interrupts(trans);
1df06bdc 1747
8d96bb61 1748 iwl_pcie_disable_ict(trans);
33b56af1 1749
fa9f3281 1750 mutex_unlock(&trans_pcie->mutex);
33b56af1 1751
2e5d4a8f 1752 iwl_pcie_synchronize_irqs(trans);
cc56feb2
EG		 1753}
1754
03905495
EG		 1755static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1756{
05f5b97e 1757 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1758}
1759
1760static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1761{
05f5b97e 1762 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1763}
1764
1765static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1766{
05f5b97e 1767 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1768}
1769
6a06b6c1
EG		 1770static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1771{
f9477c17
AP		 1772 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1773 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1774 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1775}
1776
1777static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1778 u32 val)
1779{
1780 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1781 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1782 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1783}
1784
c6f600fc 1785static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1786 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1787{
1788 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1789
1790 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1791 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
4cf677fd 1792 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
d663ee73
JB		 1793 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1794 trans_pcie->n_no_reclaim_cmds = 0;
1795 else
1796 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1797 if (trans_pcie->n_no_reclaim_cmds)
1798 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1799 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1800
6c4fbcbc
EG		 1801 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1802 trans_pcie->rx_page_order =
1803 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
7c5ba4a8 1804
046db346 1805 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1806 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
41837ca9 1807 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
f14d6b39 1808
21cb3222
JB		 1809 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1810 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1811
39bdb17e
SD		 1812 trans->command_groups = trans_cfg->command_groups;
1813 trans->command_groups_size = trans_cfg->command_groups_size;
1814
f14d6b39
JB		 1815 /* Initialize NAPI here - it should be before registering to mac80211
1816 * in the opmode but after the HW struct is allocated.
1817 * As this function may be called again in some corner cases don't
1818 * do anything if NAPI was already initialized.
1819 */
bce97731 1820 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
f14d6b39 1821 init_dummy_netdev(&trans_pcie->napi_dev);
c6f600fc
MV		 1822}
1823
d1ff5253 1824void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1825{
20d3b647 1826 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6eb5e529 1827 int i;
a42a1844 1828
2e5d4a8f 1829 iwl_pcie_synchronize_irqs(trans);
0aa86df6 1830
f02831be 1831 iwl_pcie_tx_free(trans);
9805c446 1832 iwl_pcie_rx_free(trans);
6379103e 1833
2e5d4a8f 1834 if (trans_pcie->msix_enabled) {
7c8d91eb
HD		 1835 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1836 irq_set_affinity_hint(
1837 trans_pcie->msix_entries[i].vector,
1838 NULL);
7c8d91eb 1839 }
2e5d4a8f 1840
2e5d4a8f
HD		 1841 trans_pcie->msix_enabled = false;
1842 } else {
2e5d4a8f 1843 iwl_pcie_free_ict(trans);
2e5d4a8f 1844 }
a42a1844 1845
c2d20201
EG		 1846 iwl_pcie_free_fw_monitor(trans);
1847
6eb5e529
EG		 1848 for_each_possible_cpu(i) {
1849 struct iwl_tso_hdr_page *p =
1850 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1851
1852 if (p->page)
1853 __free_page(p->page);
1854 }
1855
1856 free_percpu(trans_pcie->tso_hdr_page);
a2a57a35 1857 mutex_destroy(&trans_pcie->mutex);
7b501d10 1858 iwl_trans_free(trans);
34c1b7ba
EG		 1859}
1860
47107e84
DF		 1861static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1862{
47107e84 1863 if (state)
eb7ff77e 1864 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1865 else
eb7ff77e 1866 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1867}
1868
23ba9340
EG		 1869static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1870 unsigned long *flags)
7a65d170
EG		 1871{
1872 int ret;
cfb4e624
JB		 1873 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1874
1875 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1876
fc8a350d 1877 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1878 goto out;
1879
7a65d170 1880 /* this bit wakes up the NIC */
e139dc4a
LE		 1881 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1882 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1883 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1884 udelay(2);
7a65d170
EG		 1885
1886 /*
1887 * These bits say the device is running, and should keep running for
1888 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1889 * but they do not indicate that embedded SRAM is restored yet;
1890 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1891 * to/from host DRAM when sleeping/waking for power-saving.
1892 * Each direction takes approximately 1/4 millisecond; with this
1893 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1894 * series of register accesses are expected (e.g. reading Event Log),
1895 * to keep device from sleeping.
1896 *
1897 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1898 * SRAM is okay/restored. We don't check that here because this call
1899 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1900 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1901 *
1902 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1903 * and do not save/restore SRAM when power cycling.
1904 */
1905 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1906 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1907 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1908 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1909 if (unlikely(ret < 0)) {
1910 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
23ba9340
EG		 1911 WARN_ONCE(1,
1912 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1913 iwl_read32(trans, CSR_GP_CNTRL));
1914 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1915 return false;
7a65d170
EG		 1916 }
1917
b9439491 1918out:
e56b04ef
LE		 1919 /*
1920 * Fool sparse by faking we release the lock - sparse will
1921 * track nic_access anyway.
1922 */
cfb4e624 1923 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1924 return true;
1925}
1926
e56b04ef
LE		 1927static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1928 unsigned long *flags)
7a65d170 1929{
cfb4e624 1930 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1931
cfb4e624 1932 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1933
1934 /*
1935 * Fool sparse by faking we acquiring the lock - sparse will
1936 * track nic_access anyway.
1937 */
cfb4e624 1938 __acquire(&trans_pcie->reg_lock);
e56b04ef 1939
fc8a350d 1940 if (trans_pcie->cmd_hold_nic_awake)
b9439491
EG		 1941 goto out;
1942
e139dc4a
LE		 1943 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1944 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1945 /*
1946 * Above we read the CSR_GP_CNTRL register, which will flush
1947 * any previous writes, but we need the write that clears the
1948 * MAC_ACCESS_REQ bit to be performed before any other writes
1949 * scheduled on different CPUs (after we drop reg_lock).
1950 */
1951 mmiowb();
b9439491 1952out:
cfb4e624 1953 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1954}
1955
4fd442db
EG		 1956static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1957 void *buf, int dwords)
1958{
1959 unsigned long flags;
1960 int offs, ret = 0;
1961 u32 *vals = buf;
1962
23ba9340 1963 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1964 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1965 for (offs = 0; offs < dwords; offs++)
1966 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1967 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1968 } else {
1969 ret = -EBUSY;
1970 }
4fd442db
EG		 1971 return ret;
1972}
1973
1974static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1975 const void *buf, int dwords)
4fd442db
EG		 1976{
1977 unsigned long flags;
1978 int offs, ret = 0;
bf0fd5da 1979 const u32 *vals = buf;
4fd442db 1980
23ba9340 1981 if (iwl_trans_grab_nic_access(trans, &flags)) {
4fd442db
EG		 1982 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1983 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1984 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1985 vals ? vals[offs] : 0);
e56b04ef 1986 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1987 } else {
1988 ret = -EBUSY;
1989 }
4fd442db
EG		 1990 return ret;
1991}
7a65d170 1992
e0b8d405
EG		 1993static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1994 unsigned long txqs,
1995 bool freeze)
1996{
1997 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1998 int queue;
1999
2000 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2001 struct iwl_txq *txq = &trans_pcie->txq[queue];
2002 unsigned long now;
2003
2004 spin_lock_bh(&txq->lock);
2005
2006 now = jiffies;
2007
2008 if (txq->frozen == freeze)
2009 goto next_queue;
2010
2011 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2012 freeze ? "Freezing" : "Waking", queue);
2013
2014 txq->frozen = freeze;
2015
bb98ecd4 2016 if (txq->read_ptr == txq->write_ptr)
e0b8d405
EG		 2017 goto next_queue;
2018
2019 if (freeze) {
2020 if (unlikely(time_after(now,
2021 txq->stuck_timer.expires))) {
2022 /*
2023 * The timer should have fired, maybe it is
2024 * spinning right now on the lock.
2025 */
2026 goto next_queue;
2027 }
2028 /* remember how long until the timer fires */
2029 txq->frozen_expiry_remainder =
2030 txq->stuck_timer.expires - now;
2031 del_timer(&txq->stuck_timer);
2032 goto next_queue;
2033 }
2034
2035 /*
2036 * Wake a non-empty queue -> arm timer with the
2037 * remainder before it froze
2038 */
2039 mod_timer(&txq->stuck_timer,
2040 now + txq->frozen_expiry_remainder);
2041
2042next_queue:
2043 spin_unlock_bh(&txq->lock);
2044 }
2045}
2046
0cd58eaa
EG		 2047static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2048{
2049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2050 int i;
2051
2052 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2053 struct iwl_txq *txq = &trans_pcie->txq[i];
2054
2055 if (i == trans_pcie->cmd_queue)
2056 continue;
2057
2058 spin_lock_bh(&txq->lock);
2059
2060 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2061 txq->block--;
2062 if (!txq->block) {
2063 iwl_write32(trans, HBUS_TARG_WRPTR,
bb98ecd4 2064 txq->write_ptr | (i << 8));
0cd58eaa
EG		 2065 }
2066 } else if (block) {
2067 txq->block++;
2068 }
2069
2070 spin_unlock_bh(&txq->lock);
2071 }
2072}
2073
5f178cd2
EG		 2074#define IWL_FLUSH_WAIT_MS 2000
2075
38398efb
SS		 2076void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2077{
afb84431
EG		 2078 u32 txq_id = txq->id;
2079 u32 status;
2080 bool active;
2081 u8 fifo;
38398efb 2082
afb84431
EG		 2083 if (trans->cfg->use_tfh) {
2084 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2085 txq->read_ptr, txq->write_ptr);
ae79785f
SS		 2086 /* TODO: access new SCD registers and dump them */
2087 return;
38398efb 2088 }
afb84431
EG		 2089
2090 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2091 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2092 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2093
2094 IWL_ERR(trans,
2095 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2096 txq_id, active ? "" : "in", fifo,
2097 jiffies_to_msecs(txq->wd_timeout),
2098 txq->read_ptr, txq->write_ptr,
2099 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2100 (TFD_QUEUE_SIZE_MAX - 1),
2101 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2102 (TFD_QUEUE_SIZE_MAX - 1),
2103 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
38398efb
SS		 2104}
2105
3cafdbe6 2106static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 2107{
8ad71bef 2108 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2109 struct iwl_txq *txq;
5f178cd2
EG		 2110 int cnt;
2111 unsigned long now = jiffies;
2112 int ret = 0;
2113
2114 /* waiting for all the tx frames complete might take a while */
035f7ff2 2115 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 2116 u8 wr_ptr;
2117
9ba1947a 2118 if (cnt == trans_pcie->cmd_queue)
5f178cd2 2119 continue;
3cafdbe6
EG		 2120 if (!test_bit(cnt, trans_pcie->queue_used))
2121 continue;
2122 if (!(BIT(cnt) & txq_bm))
2123 continue;
748fa67c
EG		 2124
2125 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 2126 txq = &trans_pcie->txq[cnt];
bb98ecd4 2127 wr_ptr = ACCESS_ONCE(txq->write_ptr);
fa1a91fd 2128
bb98ecd4 2129 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
fa1a91fd
EG		 2130 !time_after(jiffies,
2131 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
bb98ecd4 2132 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
fa1a91fd
EG		 2133
2134 if (WARN_ONCE(wr_ptr != write_ptr,
2135 "WR pointer moved while flushing %d -> %d\n",
2136 wr_ptr, write_ptr))
2137 return -ETIMEDOUT;
192185d6 2138 usleep_range(1000, 2000);
fa1a91fd 2139 }
5f178cd2 2140
bb98ecd4 2141 if (txq->read_ptr != txq->write_ptr) {
1c3fea82
EG		 2142 IWL_ERR(trans,
2143 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 2144 ret = -ETIMEDOUT;
2145 break;
2146 }
748fa67c 2147 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 2148 }
1c3fea82 2149
38398efb
SS		 2150 if (ret)
2151 iwl_trans_pcie_log_scd_error(trans, txq);
1c3fea82 2152
5f178cd2
EG		 2153 return ret;
2154}
2155
e139dc4a
LE		 2156static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2157 u32 mask, u32 value)
2158{
e56b04ef 2159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 2160 unsigned long flags;
2161
e56b04ef 2162 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 2163 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 2164 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 2165}
2166
c24c7f58 2167static void iwl_trans_pcie_ref(struct iwl_trans *trans)
7616f334
EP		 2168{
2169 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2170
2171 if (iwlwifi_mod_params.d0i3_disable)
2172 return;
2173
b3ff1270 2174 pm_runtime_get(&trans_pcie->pci_dev->dev);
5d93f3a2
LC		 2175
2176#ifdef CONFIG_PM
2177 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2178 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2179#endif /* CONFIG_PM */
7616f334
EP		 2180}
2181
c24c7f58 2182static void iwl_trans_pcie_unref(struct iwl_trans *trans)
7616f334
EP		 2183{
2184 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7616f334
EP		 2185
2186 if (iwlwifi_mod_params.d0i3_disable)
2187 return;
2188
b3ff1270
LC		 2189 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2190 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
b3ff1270 2191
5d93f3a2
LC		 2192#ifdef CONFIG_PM
2193 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2194 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2195#endif /* CONFIG_PM */
7616f334
EP		 2196}
2197
ff620849
EG		 2198static const char *get_csr_string(int cmd)
2199{
d9fb6465 2200#define IWL_CMD(x) case x: return #x
ff620849
EG		 2201 switch (cmd) {
2202 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2203 IWL_CMD(CSR_INT_COALESCING);
2204 IWL_CMD(CSR_INT);
2205 IWL_CMD(CSR_INT_MASK);
2206 IWL_CMD(CSR_FH_INT_STATUS);
2207 IWL_CMD(CSR_GPIO_IN);
2208 IWL_CMD(CSR_RESET);
2209 IWL_CMD(CSR_GP_CNTRL);
2210 IWL_CMD(CSR_HW_REV);
2211 IWL_CMD(CSR_EEPROM_REG);
2212 IWL_CMD(CSR_EEPROM_GP);
2213 IWL_CMD(CSR_OTP_GP_REG);
2214 IWL_CMD(CSR_GIO_REG);
2215 IWL_CMD(CSR_GP_UCODE_REG);
2216 IWL_CMD(CSR_GP_DRIVER_REG);
2217 IWL_CMD(CSR_UCODE_DRV_GP1);
2218 IWL_CMD(CSR_UCODE_DRV_GP2);
2219 IWL_CMD(CSR_LED_REG);
2220 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2221 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2222 IWL_CMD(CSR_ANA_PLL_CFG);
2223 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 2224 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 2225 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2226 default:
2227 return "UNKNOWN";
2228 }
d9fb6465 2229#undef IWL_CMD
ff620849
EG		 2230}
2231
990aa6d7 2232void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 2233{
2234 int i;
2235 static const u32 csr_tbl[] = {
2236 CSR_HW_IF_CONFIG_REG,
2237 CSR_INT_COALESCING,
2238 CSR_INT,
2239 CSR_INT_MASK,
2240 CSR_FH_INT_STATUS,
2241 CSR_GPIO_IN,
2242 CSR_RESET,
2243 CSR_GP_CNTRL,
2244 CSR_HW_REV,
2245 CSR_EEPROM_REG,
2246 CSR_EEPROM_GP,
2247 CSR_OTP_GP_REG,
2248 CSR_GIO_REG,
2249 CSR_GP_UCODE_REG,
2250 CSR_GP_DRIVER_REG,
2251 CSR_UCODE_DRV_GP1,
2252 CSR_UCODE_DRV_GP2,
2253 CSR_LED_REG,
2254 CSR_DRAM_INT_TBL_REG,
2255 CSR_GIO_CHICKEN_BITS,
2256 CSR_ANA_PLL_CFG,
a812cba9 2257 CSR_MONITOR_STATUS_REG,
ff620849
EG		 2258 CSR_HW_REV_WA_REG,
2259 CSR_DBG_HPET_MEM_REG
2260 };
2261 IWL_ERR(trans, "CSR values:\n");
2262 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2263 "CSR_INT_PERIODIC_REG)\n");
2264 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2265 IWL_ERR(trans, " %25s: 0X%08x\n",
2266 get_csr_string(csr_tbl[i]),
1042db2a 2267 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 2268 }
2269}
2270
87e5666c
EG		 2271#ifdef CONFIG_IWLWIFI_DEBUGFS
2272/* create and remove of files */
2273#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 2274 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 2275 &iwl_dbgfs_##name##_ops)) \
9da987ac 2276 goto err; \
87e5666c
EG		 2277} while (0)
2278
2279/* file operation */
87e5666c 2280#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 2281static const struct file_operations iwl_dbgfs_##name##_ops = { \
2282 .read = iwl_dbgfs_##name##_read, \
234e3405 2283 .open = simple_open, \
87e5666c
EG		 2284 .llseek = generic_file_llseek, \
2285};
2286
16db88ba 2287#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 2288static const struct file_operations iwl_dbgfs_##name##_ops = { \
2289 .write = iwl_dbgfs_##name##_write, \
234e3405 2290 .open = simple_open, \
16db88ba
EG		 2291 .llseek = generic_file_llseek, \
2292};
2293
87e5666c 2294#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 2295static const struct file_operations iwl_dbgfs_##name##_ops = { \
2296 .write = iwl_dbgfs_##name##_write, \
2297 .read = iwl_dbgfs_##name##_read, \
234e3405 2298 .open = simple_open, \
87e5666c
EG		 2299 .llseek = generic_file_llseek, \
2300};
2301
87e5666c 2302static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 2303 char __user *user_buf,
2304 size_t count, loff_t *ppos)
8ad71bef 2305{
5a878bf6 2306 struct iwl_trans *trans = file->private_data;
8ad71bef 2307 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 2308 struct iwl_txq *txq;
87e5666c
EG		 2309 char *buf;
2310 int pos = 0;
2311 int cnt;
2312 int ret;
1745e440
WYG		 2313 size_t bufsz;
2314
e0b8d405 2315 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
87e5666c 2316
f9e75447 2317 if (!trans_pcie->txq)
87e5666c 2318 return -EAGAIN;
f9e75447 2319
87e5666c
EG		 2320 buf = kzalloc(bufsz, GFP_KERNEL);
2321 if (!buf)
2322 return -ENOMEM;
2323
035f7ff2 2324 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 2325 txq = &trans_pcie->txq[cnt];
87e5666c 2326 pos += scnprintf(buf + pos, bufsz - pos,
e0b8d405 2327 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
bb98ecd4 2328 cnt, txq->read_ptr, txq->write_ptr,
9eae88fa 2329 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62 2330 !!test_bit(cnt, trans_pcie->queue_stopped),
e0b8d405 2331 txq->need_update, txq->frozen,
f40faf62 2332 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 2333 }
2334 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2335 kfree(buf);
2336 return ret;
2337}
2338
2339static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 2340 char __user *user_buf,
2341 size_t count, loff_t *ppos)
2342{
5a878bf6 2343 struct iwl_trans *trans = file->private_data;
20d3b647 2344 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78485054
SS		 2345 char *buf;
2346 int pos = 0, i, ret;
2347 size_t bufsz = sizeof(buf);
2348
2349 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2350
2351 if (!trans_pcie->rxq)
2352 return -EAGAIN;
2353
2354 buf = kzalloc(bufsz, GFP_KERNEL);
2355 if (!buf)
2356 return -ENOMEM;
2357
2358 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2359 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2360
2361 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2362 i);
2363 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2364 rxq->read);
2365 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2366 rxq->write);
2367 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2368 rxq->write_actual);
2369 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2370 rxq->need_update);
2371 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2372 rxq->free_count);
2373 if (rxq->rb_stts) {
2374 pos += scnprintf(buf + pos, bufsz - pos,
2375 "\tclosed_rb_num: %u\n",
2376 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2377 0x0FFF);
2378 } else {
2379 pos += scnprintf(buf + pos, bufsz - pos,
2380 "\tclosed_rb_num: Not Allocated\n");
60c0a88f 2381 }
87e5666c 2382 }
78485054
SS		 2383 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2384 kfree(buf);
2385
2386 return ret;
87e5666c
EG		 2387}
2388
1f7b6172
EG		 2389static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2390 char __user *user_buf,
20d3b647
JB		 2391 size_t count, loff_t *ppos)
2392{
1f7b6172 2393 struct iwl_trans *trans = file->private_data;
20d3b647 2394 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2395 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2396
2397 int pos = 0;
2398 char *buf;
2399 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2400 ssize_t ret;
2401
2402 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 2403 if (!buf)
1f7b6172 2404 return -ENOMEM;
1f7b6172
EG		 2405
2406 pos += scnprintf(buf + pos, bufsz - pos,
2407 "Interrupt Statistics Report:\n");
2408
2409 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2410 isr_stats->hw);
2411 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2412 isr_stats->sw);
2413 if (isr_stats->sw || isr_stats->hw) {
2414 pos += scnprintf(buf + pos, bufsz - pos,
2415 "\tLast Restarting Code: 0x%X\n",
2416 isr_stats->err_code);
2417 }
2418#ifdef CONFIG_IWLWIFI_DEBUG
2419 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2420 isr_stats->sch);
2421 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2422 isr_stats->alive);
2423#endif
2424 pos += scnprintf(buf + pos, bufsz - pos,
2425 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2426
2427 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2428 isr_stats->ctkill);
2429
2430 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2431 isr_stats->wakeup);
2432
2433 pos += scnprintf(buf + pos, bufsz - pos,
2434 "Rx command responses:\t\t %u\n", isr_stats->rx);
2435
2436 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2437 isr_stats->tx);
2438
2439 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2440 isr_stats->unhandled);
2441
2442 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2443 kfree(buf);
2444 return ret;
2445}
2446
2447static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2448 const char __user *user_buf,
2449 size_t count, loff_t *ppos)
2450{
2451 struct iwl_trans *trans = file->private_data;
20d3b647 2452 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 2453 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2454
2455 char buf[8];
2456 int buf_size;
2457 u32 reset_flag;
2458
2459 memset(buf, 0, sizeof(buf));
2460 buf_size = min(count, sizeof(buf) - 1);
2461 if (copy_from_user(buf, user_buf, buf_size))
2462 return -EFAULT;
2463 if (sscanf(buf, "%x", &reset_flag) != 1)
2464 return -EFAULT;
2465 if (reset_flag == 0)
2466 memset(isr_stats, 0, sizeof(*isr_stats));
2467
2468 return count;
2469}
2470
16db88ba 2471static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 2472 const char __user *user_buf,
2473 size_t count, loff_t *ppos)
16db88ba
EG		 2474{
2475 struct iwl_trans *trans = file->private_data;
2476 char buf[8];
2477 int buf_size;
2478 int csr;
2479
2480 memset(buf, 0, sizeof(buf));
2481 buf_size = min(count, sizeof(buf) - 1);
2482 if (copy_from_user(buf, user_buf, buf_size))
2483 return -EFAULT;
2484 if (sscanf(buf, "%d", &csr) != 1)
2485 return -EFAULT;
2486
990aa6d7 2487 iwl_pcie_dump_csr(trans);
16db88ba
EG		 2488
2489 return count;
2490}
2491
16db88ba 2492static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 2493 char __user *user_buf,
2494 size_t count, loff_t *ppos)
16db88ba
EG		 2495{
2496 struct iwl_trans *trans = file->private_data;
94543a8d 2497 char *buf = NULL;
56c2477f 2498 ssize_t ret;
16db88ba 2499
56c2477f
JB		 2500 ret = iwl_dump_fh(trans, &buf);
2501 if (ret < 0)
2502 return ret;
2503 if (!buf)
2504 return -EINVAL;
2505 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2506 kfree(buf);
16db88ba
EG		 2507 return ret;
2508}
2509
1f7b6172 2510DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 2511DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 2512DEBUGFS_READ_FILE_OPS(rx_queue);
2513DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 2514DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c 2515
f8a1edb7
JB		 2516/* Create the debugfs files and directories */
2517int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
87e5666c 2518{
f8a1edb7
JB		 2519 struct dentry *dir = trans->dbgfs_dir;
2520
87e5666c
EG		 2521 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2522 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 2523 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 2524 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2525 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 2526 return 0;
9da987ac
MV		 2527
2528err:
2529 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2530 return -ENOMEM;
87e5666c 2531}
aadede6e 2532#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007 2533
6983ba69 2534static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
4d075007 2535{
3cd1980b 2536 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
4d075007
JB		 2537 u32 cmdlen = 0;
2538 int i;
2539
3cd1980b 2540 for (i = 0; i < trans_pcie->max_tbs; i++)
6983ba69 2541 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
4d075007
JB		 2542
2543 return cmdlen;
2544}
2545
bd7fc617
EG		 2546static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2547 struct iwl_fw_error_dump_data **data,
2548 int allocated_rb_nums)
2549{
2550 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2551 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
78485054
SS		 2552 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2553 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
bd7fc617
EG		 2554 u32 i, r, j, rb_len = 0;
2555
2556 spin_lock(&rxq->lock);
2557
2558 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2559
2560 for (i = rxq->read, j = 0;
2561 i != r && j < allocated_rb_nums;
2562 i = (i + 1) & RX_QUEUE_MASK, j++) {
2563 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2564 struct iwl_fw_error_dump_rb *rb;
2565
2566 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2567 DMA_FROM_DEVICE);
2568
2569 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2570
2571 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2572 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2573 rb = (void *)(*data)->data;
2574 rb->index = cpu_to_le32(i);
2575 memcpy(rb->data, page_address(rxb->page), max_len);
2576 /* remap the page for the free benefit */
2577 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2578 max_len,
2579 DMA_FROM_DEVICE);
2580
2581 *data = iwl_fw_error_next_data(*data);
2582 }
2583
2584 spin_unlock(&rxq->lock);
2585
2586 return rb_len;
2587}
473ad712
EG		 2588#define IWL_CSR_TO_DUMP (0x250)
2589
2590static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2591 struct iwl_fw_error_dump_data **data)
2592{
2593 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2594 __le32 *val;
2595 int i;
2596
2597 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2598 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2599 val = (void *)(*data)->data;
2600
2601 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2602 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2603
2604 *data = iwl_fw_error_next_data(*data);
2605
2606 return csr_len;
2607}
2608
06d51e0d
LK		 2609static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2610 struct iwl_fw_error_dump_data **data)
2611{
2612 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2613 unsigned long flags;
2614 __le32 *val;
2615 int i;
2616
23ba9340 2617 if (!iwl_trans_grab_nic_access(trans, &flags))
06d51e0d
LK		 2618 return 0;
2619
2620 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2621 (*data)->len = cpu_to_le32(fh_regs_len);
2622 val = (void *)(*data)->data;
2623
2624 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2625 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2626
2627 iwl_trans_release_nic_access(trans, &flags);
2628
2629 *data = iwl_fw_error_next_data(*data);
2630
2631 return sizeof(**data) + fh_regs_len;
2632}
2633
cc79ef66
LK		 2634static u32
2635iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2636 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2637 u32 monitor_len)
2638{
2639 u32 buf_size_in_dwords = (monitor_len >> 2);
2640 u32 *buffer = (u32 *)fw_mon_data->data;
2641 unsigned long flags;
2642 u32 i;
2643
23ba9340 2644 if (!iwl_trans_grab_nic_access(trans, &flags))
cc79ef66
LK		 2645 return 0;
2646
14ef1b43 2647 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
cc79ef66 2648 for (i = 0; i < buf_size_in_dwords; i++)
14ef1b43
GBA		 2649 buffer[i] = iwl_read_prph_no_grab(trans,
2650 MON_DMARB_RD_DATA_ADDR);
2651 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
cc79ef66
LK		 2652
2653 iwl_trans_release_nic_access(trans, &flags);
2654
2655 return monitor_len;
2656}
2657
36fb9017
OG		 2658static u32
2659iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2660 struct iwl_fw_error_dump_data **data,
2661 u32 monitor_len)
2662{
2663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2664 u32 len = 0;
2665
2666 if ((trans_pcie->fw_mon_page &&
2667 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2668 trans->dbg_dest_tlv) {
2669 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2670 u32 base, write_ptr, wrap_cnt;
2671
2672 /* If there was a dest TLV - use the values from there */
2673 if (trans->dbg_dest_tlv) {
2674 write_ptr =
2675 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2676 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2677 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2678 } else {
2679 base = MON_BUFF_BASE_ADDR;
2680 write_ptr = MON_BUFF_WRPTR;
2681 wrap_cnt = MON_BUFF_CYCLE_CNT;
2682 }
2683
2684 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2685 fw_mon_data = (void *)(*data)->data;
2686 fw_mon_data->fw_mon_wr_ptr =
2687 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2688 fw_mon_data->fw_mon_cycle_cnt =
2689 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2690 fw_mon_data->fw_mon_base_ptr =
2691 cpu_to_le32(iwl_read_prph(trans, base));
2692
2693 len += sizeof(**data) + sizeof(*fw_mon_data);
2694 if (trans_pcie->fw_mon_page) {
2695 /*
2696 * The firmware is now asserted, it won't write anything
2697 * to the buffer. CPU can take ownership to fetch the
2698 * data. The buffer will be handed back to the device
2699 * before the firmware will be restarted.
2700 */
2701 dma_sync_single_for_cpu(trans->dev,
2702 trans_pcie->fw_mon_phys,
2703 trans_pcie->fw_mon_size,
2704 DMA_FROM_DEVICE);
2705 memcpy(fw_mon_data->data,
2706 page_address(trans_pcie->fw_mon_page),
2707 trans_pcie->fw_mon_size);
2708
2709 monitor_len = trans_pcie->fw_mon_size;
2710 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2711 /*
2712 * Update pointers to reflect actual values after
2713 * shifting
2714 */
2715 base = iwl_read_prph(trans, base) <<
2716 trans->dbg_dest_tlv->base_shift;
2717 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2718 monitor_len / sizeof(u32));
2719 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2720 monitor_len =
2721 iwl_trans_pci_dump_marbh_monitor(trans,
2722 fw_mon_data,
2723 monitor_len);
2724 } else {
2725 /* Didn't match anything - output no monitor data */
2726 monitor_len = 0;
2727 }
2728
2729 len += monitor_len;
2730 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2731 }
2732
2733 return len;
2734}
2735
2736static struct iwl_trans_dump_data
2737*iwl_trans_pcie_dump_data(struct iwl_trans *trans,
a80c7a69 2738 const struct iwl_fw_dbg_trigger_tlv *trigger)
4d075007
JB		 2739{
2740 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2741 struct iwl_fw_error_dump_data *data;
2742 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2743 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2744 struct iwl_trans_dump_data *dump_data;
bd7fc617 2745 u32 len, num_rbs;
99684ae3 2746 u32 monitor_len;
4d075007 2747 int i, ptr;
96a6497b
SS		 2748 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2749 !trans->cfg->mq_rx_supported;
4d075007 2750
473ad712
EG		 2751 /* transport dump header */
2752 len = sizeof(*dump_data);
2753
2754 /* host commands */
2755 len += sizeof(*data) +
bb98ecd4 2756 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
c2d20201 2757
473ad712 2758 /* FW monitor */
99684ae3 2759 if (trans_pcie->fw_mon_page) {
c544e9c4 2760 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2761 trans_pcie->fw_mon_size;
2762 monitor_len = trans_pcie->fw_mon_size;
2763 } else if (trans->dbg_dest_tlv) {
2764 u32 base, end;
2765
2766 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2767 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2768
2769 base = iwl_read_prph(trans, base) <<
2770 trans->dbg_dest_tlv->base_shift;
2771 end = iwl_read_prph(trans, end) <<
2772 trans->dbg_dest_tlv->end_shift;
2773
2774 /* Make "end" point to the actual end */
cc79ef66
LK		 2775 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2776 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
99684ae3
LK		 2777 end += (1 << trans->dbg_dest_tlv->end_shift);
2778 monitor_len = end - base;
2779 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2780 monitor_len;
2781 } else {
2782 monitor_len = 0;
2783 }
c2d20201 2784
36fb9017
OG		 2785 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2786 dump_data = vzalloc(len);
2787 if (!dump_data)
2788 return NULL;
2789
2790 data = (void *)dump_data->data;
2791 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2792 dump_data->len = len;
2793
2794 return dump_data;
2795 }
2796
2797 /* CSR registers */
2798 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2799
36fb9017
OG		 2800 /* FH registers */
2801 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2802
2803 if (dump_rbs) {
78485054
SS		 2804 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2805 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
36fb9017 2806 /* RBs */
78485054 2807 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
36fb9017 2808 & 0x0FFF;
78485054 2809 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
36fb9017
OG		 2810 len += num_rbs * (sizeof(*data) +
2811 sizeof(struct iwl_fw_error_dump_rb) +
2812 (PAGE_SIZE << trans_pcie->rx_page_order));
2813 }
2814
48eb7b34
EG		 2815 dump_data = vzalloc(len);
2816 if (!dump_data)
2817 return NULL;
4d075007
JB		 2818
2819 len = 0;
48eb7b34 2820 data = (void *)dump_data->data;
4d075007
JB		 2821 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2822 txcmd = (void *)data->data;
2823 spin_lock_bh(&cmdq->lock);
bb98ecd4
SS		 2824 ptr = cmdq->write_ptr;
2825 for (i = 0; i < cmdq->n_window; i++) {
2826 u8 idx = get_cmd_index(cmdq, ptr);
4d075007
JB		 2827 u32 caplen, cmdlen;
2828
6983ba69
SS		 2829 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2830 trans_pcie->tfd_size * ptr);
4d075007
JB		 2831 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2832
2833 if (cmdlen) {
2834 len += sizeof(*txcmd) + caplen;
2835 txcmd->cmdlen = cpu_to_le32(cmdlen);
2836 txcmd->caplen = cpu_to_le32(caplen);
2837 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2838 txcmd = (void *)((u8 *)txcmd->data + caplen);
2839 }
2840
2841 ptr = iwl_queue_dec_wrap(ptr);
2842 }
2843 spin_unlock_bh(&cmdq->lock);
2844
2845 data->len = cpu_to_le32(len);
c2d20201 2846 len += sizeof(*data);
67c65f2c
EG		 2847 data = iwl_fw_error_next_data(data);
2848
473ad712 2849 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2850 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
bd7fc617
EG		 2851 if (dump_rbs)
2852 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
c2d20201 2853
36fb9017 2854 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
c2d20201 2855
48eb7b34
EG		 2856 dump_data->len = len;
2857
2858 return dump_data;
4d075007 2859}
87e5666c 2860
4cbb8e50
LC		 2861#ifdef CONFIG_PM_SLEEP
2862static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2863{
2864 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2865 return iwl_pci_fw_enter_d0i3(trans);
2866
2867 return 0;
2868}
2869
2870static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2871{
2872 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2873 iwl_pci_fw_exit_d0i3(trans);
2874}
2875#endif /* CONFIG_PM_SLEEP */
2876
d1ff5253 2877static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2878 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2879 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2880 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2881 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2882 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2883
ddaf5a5b
JB		 2884 .d3_suspend = iwl_trans_pcie_d3_suspend,
2885 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2886
4cbb8e50
LC		 2887#ifdef CONFIG_PM_SLEEP
2888 .suspend = iwl_trans_pcie_suspend,
2889 .resume = iwl_trans_pcie_resume,
2890#endif /* CONFIG_PM_SLEEP */
2891
f02831be 2892 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2893
e6bb4c9c 2894 .tx = iwl_trans_pcie_tx,
a0eaad71 2895 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2896
d0624be6 2897 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2898 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2899
8aacf4b7
SS		 2900 .get_txq_byte_table = iwl_trans_pcie_get_txq_byte_table,
2901
42db09c1
LK		 2902 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2903
990aa6d7 2904 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
e0b8d405 2905 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
0cd58eaa 2906 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
5f178cd2 2907
03905495
EG		 2908 .write8 = iwl_trans_pcie_write8,
2909 .write32 = iwl_trans_pcie_write32,
2910 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2911 .read_prph = iwl_trans_pcie_read_prph,
2912 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2913 .read_mem = iwl_trans_pcie_read_mem,
2914 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2915 .configure = iwl_trans_pcie_configure,
47107e84 2916 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2917 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2918 .release_nic_access = iwl_trans_pcie_release_nic_access,
2919 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2920
7616f334
EP		 2921 .ref = iwl_trans_pcie_ref,
2922 .unref = iwl_trans_pcie_unref,
2923
4d075007 2924 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2925};
a42a1844 2926
87ce05a2 2927struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2928 const struct pci_device_id *ent,
2929 const struct iwl_cfg *cfg)
a42a1844 2930{
a42a1844
EG		 2931 struct iwl_trans_pcie *trans_pcie;
2932 struct iwl_trans *trans;
96a6497b 2933 int ret, addr_size;
a42a1844 2934
5a41a86c
SD		 2935 ret = pcim_enable_device(pdev);
2936 if (ret)
2937 return ERR_PTR(ret);
2938
7b501d10
JB		 2939 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2940 &pdev->dev, cfg, &trans_ops_pcie, 0);
2941 if (!trans)
2942 return ERR_PTR(-ENOMEM);
a42a1844
EG		 2943
2944 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2945
a42a1844 2946 trans_pcie->trans = trans;
7b11488f 2947 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2948 spin_lock_init(&trans_pcie->reg_lock);
fa9f3281 2949 mutex_init(&trans_pcie->mutex);
13df1aab 2950 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
6eb5e529
EG		 2951 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2952 if (!trans_pcie->tso_hdr_page) {
2953 ret = -ENOMEM;
2954 goto out_no_pci;
2955 }
a42a1844 2956
d819c6cf 2957
f2532b04
EG		 2958 if (!cfg->base_params->pcie_l1_allowed) {
2959 /*
2960 * W/A - seems to solve weird behavior. We need to remove this
2961 * if we don't want to stay in L1 all the time. This wastes a
2962 * lot of power.
2963 */
2964 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2965 PCIE_LINK_STATE_L1 |
2966 PCIE_LINK_STATE_CLKPM);
2967 }
a42a1844 2968
6983ba69 2969 if (cfg->use_tfh) {
2c6262b7 2970 addr_size = 64;
3cd1980b 2971 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
8352e62a 2972 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
6983ba69 2973 } else {
2c6262b7 2974 addr_size = 36;
3cd1980b 2975 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
6983ba69
SS		 2976 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
2977 }
3cd1980b
SS		 2978 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
2979
a42a1844
EG		 2980 pci_set_master(pdev);
2981
96a6497b 2982 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
af3f2f74 2983 if (!ret)
96a6497b
SS		 2984 ret = pci_set_consistent_dma_mask(pdev,
2985 DMA_BIT_MASK(addr_size));
af3f2f74
EG		 2986 if (ret) {
2987 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2988 if (!ret)
2989 ret = pci_set_consistent_dma_mask(pdev,
20d3b647 2990 DMA_BIT_MASK(32));
a42a1844 2991 /* both attempts failed: */
af3f2f74 2992 if (ret) {
6a4b09f8 2993 dev_err(&pdev->dev, "No suitable DMA available\n");
5a41a86c 2994 goto out_no_pci;
a42a1844
EG		 2995 }
2996 }
2997
5a41a86c 2998 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
af3f2f74 2999 if (ret) {
5a41a86c
SD		 3000 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3001 goto out_no_pci;
a42a1844
EG		 3002 }
3003
5a41a86c 3004 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
a42a1844 3005 if (!trans_pcie->hw_base) {
5a41a86c 3006 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
af3f2f74 3007 ret = -ENODEV;
5a41a86c 3008 goto out_no_pci;
a42a1844
EG		 3009 }
3010
a42a1844
EG		 3011 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3012 * PCI Tx retries from interfering with C3 CPU state */
3013 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3014
83f7a85f
EG		 3015 trans->dev = &pdev->dev;
3016 trans_pcie->pci_dev = pdev;
3017 iwl_disable_interrupts(trans);
3018
08079a49 3019 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 3020 /*
3021 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3022 * changed, and now the revision step also includes bit 0-1 (no more
3023 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3024 * in the old format.
3025 */
7a42baa6
EH		 3026 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
3027 unsigned long flags;
7a42baa6 3028
b513ee7f 3029 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 3030 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 3031
f9e5554c
EG		 3032 ret = iwl_pcie_prepare_card_hw(trans);
3033 if (ret) {
3034 IWL_WARN(trans, "Exit HW not ready\n");
5a41a86c 3035 goto out_no_pci;
f9e5554c
EG		 3036 }
3037
7a42baa6
EH		 3038 /*
3039 * in-order to recognize C step driver should read chip version
3040 * id located at the AUX bus MISC address space.
3041 */
3042 iwl_set_bit(trans, CSR_GP_CNTRL,
3043 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3044 udelay(2);
3045
3046 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3047 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3048 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3049 25000);
3050 if (ret < 0) {
3051 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
5a41a86c 3052 goto out_no_pci;
7a42baa6
EH		 3053 }
3054
23ba9340 3055 if (iwl_trans_grab_nic_access(trans, &flags)) {
7a42baa6
EH		 3056 u32 hw_step;
3057
14ef1b43 3058 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
7a42baa6 3059 hw_step |= ENABLE_WFPM;
14ef1b43
GBA		 3060 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3061 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
7a42baa6
EH		 3062 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3063 if (hw_step == 0x3)
3064 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3065 (SILICON_C_STEP << 2);
3066 iwl_trans_release_nic_access(trans, &flags);
3067 }
3068 }
3069
1afb0ae4
HD		 3070 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3071
2e5d4a8f 3072 iwl_pcie_set_interrupt_capa(pdev, trans);
99673ee5 3073 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 3074 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3075 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 3076
69a10b29 3077 /* Initialize the wait queue for commands */
f946b529 3078 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 3079
4cbb8e50
LC		 3080 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3081
2e5d4a8f
HD		 3082 if (trans_pcie->msix_enabled) {
3083 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
5a41a86c 3084 goto out_no_pci;
2e5d4a8f
HD		 3085 } else {
3086 ret = iwl_pcie_alloc_ict(trans);
3087 if (ret)
5a41a86c 3088 goto out_no_pci;
a8b691e6 3089
5a41a86c
SD		 3090 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3091 iwl_pcie_isr,
3092 iwl_pcie_irq_handler,
3093 IRQF_SHARED, DRV_NAME, trans);
2e5d4a8f
HD		 3094 if (ret) {
3095 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3096 goto out_free_ict;
3097 }
3098 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3099 }
83f7a85f 3100
b3ff1270
LC		 3101#ifdef CONFIG_IWLWIFI_PCIE_RTPM
3102 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3103#else
3104 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3105#endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3106
a42a1844
EG		 3107 return trans;
3108
a8b691e6
JB		 3109out_free_ict:
3110 iwl_pcie_free_ict(trans);
a42a1844 3111out_no_pci:
6eb5e529 3112 free_percpu(trans_pcie->tso_hdr_page);
7b501d10 3113 iwl_trans_free(trans);
af3f2f74 3114 return ERR_PTR(ret);
a42a1844 3115}
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