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4bc85c13 WYG |
1 | /****************************************************************************** |
2 | * | |
be663ab6 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
4bc85c13 WYG |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
31 | ||
32 | #include <linux/kernel.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/pci-aspm.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/sched.h> | |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/netdevice.h> | |
4bc85c13 WYG |
43 | #include <linux/firmware.h> |
44 | #include <linux/etherdevice.h> | |
45 | #include <linux/if_arp.h> | |
46 | ||
47 | #include <net/ieee80211_radiotap.h> | |
48 | #include <net/mac80211.h> | |
49 | ||
50 | #include <asm/div64.h> | |
51 | ||
52 | #define DRV_NAME "iwl3945" | |
53 | ||
54 | #include "iwl-fh.h" | |
55 | #include "iwl-3945-fh.h" | |
56 | #include "iwl-commands.h" | |
57 | #include "iwl-sta.h" | |
58 | #include "iwl-3945.h" | |
59 | #include "iwl-core.h" | |
60 | #include "iwl-helpers.h" | |
61 | #include "iwl-dev.h" | |
62 | #include "iwl-spectrum.h" | |
4bc85c13 WYG |
63 | |
64 | /* | |
65 | * module name, copyright, version, etc. | |
66 | */ | |
67 | ||
68 | #define DRV_DESCRIPTION \ | |
69 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
70 | ||
be663ab6 | 71 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
4bc85c13 WYG |
72 | #define VD "d" |
73 | #else | |
74 | #define VD | |
75 | #endif | |
76 | ||
77 | /* | |
78 | * add "s" to indicate spectrum measurement included. | |
79 | * we add it here to be consistent with previous releases in which | |
80 | * this was configurable. | |
81 | */ | |
82 | #define DRV_VERSION IWLWIFI_VERSION VD "s" | |
be663ab6 | 83 | #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation" |
4bc85c13 WYG |
84 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
85 | ||
86 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
87 | MODULE_VERSION(DRV_VERSION); | |
88 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); | |
89 | MODULE_LICENSE("GPL"); | |
90 | ||
91 | /* module parameters */ | |
e2ebc833 | 92 | struct il_mod_params il3945_mod_params = { |
4bc85c13 WYG |
93 | .sw_crypto = 1, |
94 | .restart_fw = 1, | |
0263aa45 | 95 | .disable_hw_scan = 1, |
4bc85c13 WYG |
96 | /* the rest are 0 by default */ |
97 | }; | |
98 | ||
99 | /** | |
e2ebc833 | 100 | * il3945_get_antenna_flags - Get antenna flags for RXON command |
46bc8d4b | 101 | * @il: eeprom and antenna fields are used to determine antenna flags |
4bc85c13 | 102 | * |
46bc8d4b | 103 | * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed |
e2ebc833 | 104 | * il3945_mod_params.antenna specifies the antenna diversity mode: |
4bc85c13 | 105 | * |
e2ebc833 SG |
106 | * IL_ANTENNA_DIVERSITY - NIC selects best antenna by itself |
107 | * IL_ANTENNA_MAIN - Force MAIN antenna | |
108 | * IL_ANTENNA_AUX - Force AUX antenna | |
4bc85c13 | 109 | */ |
46bc8d4b | 110 | __le32 il3945_get_antenna_flags(const struct il_priv *il) |
4bc85c13 | 111 | { |
46bc8d4b | 112 | struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; |
4bc85c13 | 113 | |
e2ebc833 SG |
114 | switch (il3945_mod_params.antenna) { |
115 | case IL_ANTENNA_DIVERSITY: | |
4bc85c13 WYG |
116 | return 0; |
117 | ||
e2ebc833 | 118 | case IL_ANTENNA_MAIN: |
4bc85c13 WYG |
119 | if (eeprom->antenna_switch_type) |
120 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
121 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
122 | ||
e2ebc833 | 123 | case IL_ANTENNA_AUX: |
4bc85c13 WYG |
124 | if (eeprom->antenna_switch_type) |
125 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
126 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
127 | } | |
128 | ||
129 | /* bad antenna selector value */ | |
9406f797 | 130 | IL_ERR("Bad antenna selector value (0x%x)\n", |
e2ebc833 | 131 | il3945_mod_params.antenna); |
4bc85c13 WYG |
132 | |
133 | return 0; /* "diversity" is default if error */ | |
134 | } | |
135 | ||
46bc8d4b | 136 | static int il3945_set_ccmp_dynamic_key_info(struct il_priv *il, |
4bc85c13 WYG |
137 | struct ieee80211_key_conf *keyconf, |
138 | u8 sta_id) | |
139 | { | |
140 | unsigned long flags; | |
141 | __le16 key_flags = 0; | |
142 | int ret; | |
143 | ||
144 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); | |
145 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
146 | ||
46bc8d4b | 147 | if (sta_id == il->contexts[IL_RXON_CTX_BSS].bcast_sta_id) |
4bc85c13 WYG |
148 | key_flags |= STA_KEY_MULTICAST_MSK; |
149 | ||
150 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
151 | keyconf->hw_key_idx = keyconf->keyidx; | |
152 | key_flags &= ~STA_KEY_FLG_INVALID; | |
153 | ||
46bc8d4b SG |
154 | spin_lock_irqsave(&il->sta_lock, flags); |
155 | il->stations[sta_id].keyinfo.cipher = keyconf->cipher; | |
156 | il->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
157 | memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, | |
4bc85c13 WYG |
158 | keyconf->keylen); |
159 | ||
46bc8d4b | 160 | memcpy(il->stations[sta_id].sta.key.key, keyconf->key, |
4bc85c13 WYG |
161 | keyconf->keylen); |
162 | ||
46bc8d4b | 163 | if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK) |
4bc85c13 | 164 | == STA_KEY_FLG_NO_ENC) |
46bc8d4b SG |
165 | il->stations[sta_id].sta.key.key_offset = |
166 | il_get_free_ucode_key_index(il); | |
4bc85c13 WYG |
167 | /* else, we are overriding an existing key => no need to allocated room |
168 | * in uCode. */ | |
169 | ||
46bc8d4b | 170 | WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, |
4bc85c13 WYG |
171 | "no space for a new key"); |
172 | ||
46bc8d4b SG |
173 | il->stations[sta_id].sta.key.key_flags = key_flags; |
174 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
175 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
4bc85c13 | 176 | |
58de00a4 | 177 | D_INFO("hwcrypto: modify ucode station key info\n"); |
4bc85c13 | 178 | |
46bc8d4b SG |
179 | ret = il_send_add_sta(il, |
180 | &il->stations[sta_id].sta, CMD_ASYNC); | |
4bc85c13 | 181 | |
46bc8d4b | 182 | spin_unlock_irqrestore(&il->sta_lock, flags); |
4bc85c13 WYG |
183 | |
184 | return ret; | |
185 | } | |
186 | ||
46bc8d4b | 187 | static int il3945_set_tkip_dynamic_key_info(struct il_priv *il, |
4bc85c13 WYG |
188 | struct ieee80211_key_conf *keyconf, |
189 | u8 sta_id) | |
190 | { | |
191 | return -EOPNOTSUPP; | |
192 | } | |
193 | ||
46bc8d4b | 194 | static int il3945_set_wep_dynamic_key_info(struct il_priv *il, |
4bc85c13 WYG |
195 | struct ieee80211_key_conf *keyconf, |
196 | u8 sta_id) | |
197 | { | |
198 | return -EOPNOTSUPP; | |
199 | } | |
200 | ||
46bc8d4b | 201 | static int il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id) |
4bc85c13 WYG |
202 | { |
203 | unsigned long flags; | |
e2ebc833 | 204 | struct il_addsta_cmd sta_cmd; |
4bc85c13 | 205 | |
46bc8d4b SG |
206 | spin_lock_irqsave(&il->sta_lock, flags); |
207 | memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key)); | |
208 | memset(&il->stations[sta_id].sta.key, 0, | |
e2ebc833 | 209 | sizeof(struct il4965_keyinfo)); |
46bc8d4b SG |
210 | il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
211 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
212 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
213 | memcpy(&sta_cmd, &il->stations[sta_id].sta, sizeof(struct il_addsta_cmd)); | |
214 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
4bc85c13 | 215 | |
58de00a4 | 216 | D_INFO("hwcrypto: clear ucode station key info\n"); |
46bc8d4b | 217 | return il_send_add_sta(il, &sta_cmd, CMD_SYNC); |
4bc85c13 WYG |
218 | } |
219 | ||
46bc8d4b | 220 | static int il3945_set_dynamic_key(struct il_priv *il, |
4bc85c13 WYG |
221 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
222 | { | |
223 | int ret = 0; | |
224 | ||
225 | keyconf->hw_key_idx = HW_KEY_DYNAMIC; | |
226 | ||
227 | switch (keyconf->cipher) { | |
228 | case WLAN_CIPHER_SUITE_CCMP: | |
46bc8d4b | 229 | ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id); |
4bc85c13 WYG |
230 | break; |
231 | case WLAN_CIPHER_SUITE_TKIP: | |
46bc8d4b | 232 | ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id); |
4bc85c13 WYG |
233 | break; |
234 | case WLAN_CIPHER_SUITE_WEP40: | |
235 | case WLAN_CIPHER_SUITE_WEP104: | |
46bc8d4b | 236 | ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id); |
4bc85c13 WYG |
237 | break; |
238 | default: | |
9406f797 | 239 | IL_ERR("Unknown alg: %s alg=%x\n", __func__, |
4bc85c13 WYG |
240 | keyconf->cipher); |
241 | ret = -EINVAL; | |
242 | } | |
243 | ||
58de00a4 | 244 | D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n", |
4bc85c13 WYG |
245 | keyconf->cipher, keyconf->keylen, keyconf->keyidx, |
246 | sta_id, ret); | |
247 | ||
248 | return ret; | |
249 | } | |
250 | ||
46bc8d4b | 251 | static int il3945_remove_static_key(struct il_priv *il) |
4bc85c13 WYG |
252 | { |
253 | int ret = -EOPNOTSUPP; | |
254 | ||
255 | return ret; | |
256 | } | |
257 | ||
46bc8d4b | 258 | static int il3945_set_static_key(struct il_priv *il, |
4bc85c13 WYG |
259 | struct ieee80211_key_conf *key) |
260 | { | |
261 | if (key->cipher == WLAN_CIPHER_SUITE_WEP40 || | |
262 | key->cipher == WLAN_CIPHER_SUITE_WEP104) | |
263 | return -EOPNOTSUPP; | |
264 | ||
9406f797 | 265 | IL_ERR("Static key invalid: cipher %x\n", key->cipher); |
4bc85c13 WYG |
266 | return -EINVAL; |
267 | } | |
268 | ||
46bc8d4b | 269 | static void il3945_clear_free_frames(struct il_priv *il) |
4bc85c13 WYG |
270 | { |
271 | struct list_head *element; | |
272 | ||
58de00a4 | 273 | D_INFO("%d frames on pre-allocated heap on clear.\n", |
46bc8d4b | 274 | il->frames_count); |
4bc85c13 | 275 | |
46bc8d4b SG |
276 | while (!list_empty(&il->free_frames)) { |
277 | element = il->free_frames.next; | |
4bc85c13 | 278 | list_del(element); |
e2ebc833 | 279 | kfree(list_entry(element, struct il3945_frame, list)); |
46bc8d4b | 280 | il->frames_count--; |
4bc85c13 WYG |
281 | } |
282 | ||
46bc8d4b | 283 | if (il->frames_count) { |
9406f797 | 284 | IL_WARN("%d frames still in use. Did we lose one?\n", |
46bc8d4b SG |
285 | il->frames_count); |
286 | il->frames_count = 0; | |
4bc85c13 WYG |
287 | } |
288 | } | |
289 | ||
46bc8d4b | 290 | static struct il3945_frame *il3945_get_free_frame(struct il_priv *il) |
4bc85c13 | 291 | { |
e2ebc833 | 292 | struct il3945_frame *frame; |
4bc85c13 | 293 | struct list_head *element; |
46bc8d4b | 294 | if (list_empty(&il->free_frames)) { |
4bc85c13 WYG |
295 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); |
296 | if (!frame) { | |
9406f797 | 297 | IL_ERR("Could not allocate frame!\n"); |
4bc85c13 WYG |
298 | return NULL; |
299 | } | |
300 | ||
46bc8d4b | 301 | il->frames_count++; |
4bc85c13 WYG |
302 | return frame; |
303 | } | |
304 | ||
46bc8d4b | 305 | element = il->free_frames.next; |
4bc85c13 | 306 | list_del(element); |
e2ebc833 | 307 | return list_entry(element, struct il3945_frame, list); |
4bc85c13 WYG |
308 | } |
309 | ||
46bc8d4b | 310 | static void il3945_free_frame(struct il_priv *il, struct il3945_frame *frame) |
4bc85c13 WYG |
311 | { |
312 | memset(frame, 0, sizeof(*frame)); | |
46bc8d4b | 313 | list_add(&frame->list, &il->free_frames); |
4bc85c13 WYG |
314 | } |
315 | ||
46bc8d4b | 316 | unsigned int il3945_fill_beacon_frame(struct il_priv *il, |
4bc85c13 WYG |
317 | struct ieee80211_hdr *hdr, |
318 | int left) | |
319 | { | |
320 | ||
46bc8d4b | 321 | if (!il_is_associated(il, IL_RXON_CTX_BSS) || !il->beacon_skb) |
4bc85c13 WYG |
322 | return 0; |
323 | ||
46bc8d4b | 324 | if (il->beacon_skb->len > left) |
4bc85c13 WYG |
325 | return 0; |
326 | ||
46bc8d4b | 327 | memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len); |
4bc85c13 | 328 | |
46bc8d4b | 329 | return il->beacon_skb->len; |
4bc85c13 WYG |
330 | } |
331 | ||
46bc8d4b | 332 | static int il3945_send_beacon_cmd(struct il_priv *il) |
4bc85c13 | 333 | { |
e2ebc833 | 334 | struct il3945_frame *frame; |
4bc85c13 WYG |
335 | unsigned int frame_size; |
336 | int rc; | |
337 | u8 rate; | |
338 | ||
46bc8d4b | 339 | frame = il3945_get_free_frame(il); |
4bc85c13 WYG |
340 | |
341 | if (!frame) { | |
9406f797 | 342 | IL_ERR("Could not obtain free frame buffer for beacon " |
4bc85c13 WYG |
343 | "command.\n"); |
344 | return -ENOMEM; | |
345 | } | |
346 | ||
46bc8d4b SG |
347 | rate = il_get_lowest_plcp(il, |
348 | &il->contexts[IL_RXON_CTX_BSS]); | |
4bc85c13 | 349 | |
46bc8d4b | 350 | frame_size = il3945_hw_get_beacon_cmd(il, frame, rate); |
4bc85c13 | 351 | |
46bc8d4b | 352 | rc = il_send_cmd_pdu(il, REPLY_TX_BEACON, frame_size, |
4bc85c13 WYG |
353 | &frame->u.cmd[0]); |
354 | ||
46bc8d4b | 355 | il3945_free_frame(il, frame); |
4bc85c13 WYG |
356 | |
357 | return rc; | |
358 | } | |
359 | ||
46bc8d4b | 360 | static void il3945_unset_hw_params(struct il_priv *il) |
4bc85c13 | 361 | { |
46bc8d4b SG |
362 | if (il->_3945.shared_virt) |
363 | dma_free_coherent(&il->pci_dev->dev, | |
e2ebc833 | 364 | sizeof(struct il3945_shared), |
46bc8d4b SG |
365 | il->_3945.shared_virt, |
366 | il->_3945.shared_phys); | |
4bc85c13 WYG |
367 | } |
368 | ||
46bc8d4b | 369 | static void il3945_build_tx_cmd_hwcrypto(struct il_priv *il, |
4bc85c13 | 370 | struct ieee80211_tx_info *info, |
e2ebc833 | 371 | struct il_device_cmd *cmd, |
4bc85c13 WYG |
372 | struct sk_buff *skb_frag, |
373 | int sta_id) | |
374 | { | |
e2ebc833 | 375 | struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload; |
46bc8d4b | 376 | struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo; |
4bc85c13 WYG |
377 | |
378 | tx_cmd->sec_ctl = 0; | |
379 | ||
380 | switch (keyinfo->cipher) { | |
381 | case WLAN_CIPHER_SUITE_CCMP: | |
382 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
383 | memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen); | |
58de00a4 | 384 | D_TX("tx_cmd with AES hwcrypto\n"); |
4bc85c13 WYG |
385 | break; |
386 | ||
387 | case WLAN_CIPHER_SUITE_TKIP: | |
388 | break; | |
389 | ||
390 | case WLAN_CIPHER_SUITE_WEP104: | |
391 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
392 | /* fall through */ | |
393 | case WLAN_CIPHER_SUITE_WEP40: | |
394 | tx_cmd->sec_ctl |= TX_CMD_SEC_WEP | | |
395 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; | |
396 | ||
397 | memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen); | |
398 | ||
58de00a4 | 399 | D_TX("Configuring packet for WEP encryption " |
4bc85c13 WYG |
400 | "with key %d\n", info->control.hw_key->hw_key_idx); |
401 | break; | |
402 | ||
403 | default: | |
9406f797 | 404 | IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher); |
4bc85c13 WYG |
405 | break; |
406 | } | |
407 | } | |
408 | ||
409 | /* | |
410 | * handle build REPLY_TX command notification. | |
411 | */ | |
46bc8d4b | 412 | static void il3945_build_tx_cmd_basic(struct il_priv *il, |
e2ebc833 | 413 | struct il_device_cmd *cmd, |
4bc85c13 WYG |
414 | struct ieee80211_tx_info *info, |
415 | struct ieee80211_hdr *hdr, u8 std_id) | |
416 | { | |
e2ebc833 | 417 | struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload; |
4bc85c13 WYG |
418 | __le32 tx_flags = tx_cmd->tx_flags; |
419 | __le16 fc = hdr->frame_control; | |
420 | ||
421 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
422 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { | |
423 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
424 | if (ieee80211_is_mgmt(fc)) | |
425 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
426 | if (ieee80211_is_probe_resp(fc) && | |
427 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
428 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
429 | } else { | |
430 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
431 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
432 | } | |
433 | ||
434 | tx_cmd->sta_id = std_id; | |
435 | if (ieee80211_has_morefrags(fc)) | |
436 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
437 | ||
438 | if (ieee80211_is_data_qos(fc)) { | |
439 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
440 | tx_cmd->tid_tspec = qc[0] & 0xf; | |
441 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
442 | } else { | |
443 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
444 | } | |
445 | ||
46bc8d4b | 446 | il_tx_cmd_protection(il, info, fc, &tx_flags); |
4bc85c13 WYG |
447 | |
448 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
449 | if (ieee80211_is_mgmt(fc)) { | |
450 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
451 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); | |
452 | else | |
453 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
454 | } else { | |
455 | tx_cmd->timeout.pm_frame_timeout = 0; | |
456 | } | |
457 | ||
458 | tx_cmd->driver_txop = 0; | |
459 | tx_cmd->tx_flags = tx_flags; | |
460 | tx_cmd->next_frame_len = 0; | |
461 | } | |
462 | ||
463 | /* | |
464 | * start REPLY_TX command process | |
465 | */ | |
46bc8d4b | 466 | static int il3945_tx_skb(struct il_priv *il, struct sk_buff *skb) |
4bc85c13 WYG |
467 | { |
468 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
469 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
e2ebc833 SG |
470 | struct il3945_tx_cmd *tx_cmd; |
471 | struct il_tx_queue *txq = NULL; | |
472 | struct il_queue *q = NULL; | |
473 | struct il_device_cmd *out_cmd; | |
474 | struct il_cmd_meta *out_meta; | |
4bc85c13 WYG |
475 | dma_addr_t phys_addr; |
476 | dma_addr_t txcmd_phys; | |
477 | int txq_id = skb_get_queue_mapping(skb); | |
478 | u16 len, idx, hdr_len; | |
479 | u8 id; | |
480 | u8 unicast; | |
481 | u8 sta_id; | |
482 | u8 tid = 0; | |
483 | __le16 fc; | |
484 | u8 wait_write_ptr = 0; | |
485 | unsigned long flags; | |
486 | ||
46bc8d4b SG |
487 | spin_lock_irqsave(&il->lock, flags); |
488 | if (il_is_rfkill(il)) { | |
58de00a4 | 489 | D_DROP("Dropping - RF KILL\n"); |
4bc85c13 WYG |
490 | goto drop_unlock; |
491 | } | |
492 | ||
46bc8d4b | 493 | if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) == IL_INVALID_RATE) { |
9406f797 | 494 | IL_ERR("ERROR: No TX rate available.\n"); |
4bc85c13 WYG |
495 | goto drop_unlock; |
496 | } | |
497 | ||
498 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
499 | id = 0; | |
500 | ||
501 | fc = hdr->frame_control; | |
502 | ||
be663ab6 | 503 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
4bc85c13 | 504 | if (ieee80211_is_auth(fc)) |
58de00a4 | 505 | D_TX("Sending AUTH frame\n"); |
4bc85c13 | 506 | else if (ieee80211_is_assoc_req(fc)) |
58de00a4 | 507 | D_TX("Sending ASSOC frame\n"); |
4bc85c13 | 508 | else if (ieee80211_is_reassoc_req(fc)) |
58de00a4 | 509 | D_TX("Sending REASSOC frame\n"); |
4bc85c13 WYG |
510 | #endif |
511 | ||
46bc8d4b | 512 | spin_unlock_irqrestore(&il->lock, flags); |
4bc85c13 WYG |
513 | |
514 | hdr_len = ieee80211_hdrlen(fc); | |
515 | ||
516 | /* Find index into station table for destination station */ | |
e2ebc833 | 517 | sta_id = il_sta_id_or_broadcast( |
46bc8d4b | 518 | il, &il->contexts[IL_RXON_CTX_BSS], |
4bc85c13 | 519 | info->control.sta); |
e2ebc833 | 520 | if (sta_id == IL_INVALID_STATION) { |
58de00a4 | 521 | D_DROP("Dropping - INVALID STATION: %pM\n", |
4bc85c13 WYG |
522 | hdr->addr1); |
523 | goto drop; | |
524 | } | |
525 | ||
58de00a4 | 526 | D_RATE("station Id %d\n", sta_id); |
4bc85c13 WYG |
527 | |
528 | if (ieee80211_is_data_qos(fc)) { | |
529 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
530 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; | |
531 | if (unlikely(tid >= MAX_TID_COUNT)) | |
532 | goto drop; | |
533 | } | |
534 | ||
535 | /* Descriptor for chosen Tx queue */ | |
46bc8d4b | 536 | txq = &il->txq[txq_id]; |
4bc85c13 WYG |
537 | q = &txq->q; |
538 | ||
e2ebc833 | 539 | if ((il_queue_space(q) < q->high_mark)) |
4bc85c13 WYG |
540 | goto drop; |
541 | ||
46bc8d4b | 542 | spin_lock_irqsave(&il->lock, flags); |
4bc85c13 | 543 | |
e2ebc833 | 544 | idx = il_get_cmd_index(q, q->write_ptr, 0); |
4bc85c13 WYG |
545 | |
546 | /* Set up driver data for this TFD */ | |
e2ebc833 | 547 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct il_tx_info)); |
4bc85c13 | 548 | txq->txb[q->write_ptr].skb = skb; |
46bc8d4b | 549 | txq->txb[q->write_ptr].ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 WYG |
550 | |
551 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
552 | out_cmd = txq->cmd[idx]; | |
553 | out_meta = &txq->meta[idx]; | |
e2ebc833 | 554 | tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload; |
4bc85c13 WYG |
555 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
556 | memset(tx_cmd, 0, sizeof(*tx_cmd)); | |
557 | ||
558 | /* | |
559 | * Set up the Tx-command (not MAC!) header. | |
560 | * Store the chosen Tx queue and TFD index within the sequence field; | |
561 | * after Tx, uCode's Tx response will return this value so driver can | |
562 | * locate the frame within the tx queue and do post-tx processing. | |
563 | */ | |
564 | out_cmd->hdr.cmd = REPLY_TX; | |
565 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
566 | INDEX_TO_SEQ(q->write_ptr))); | |
567 | ||
568 | /* Copy MAC header from skb into command buffer */ | |
569 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
570 | ||
571 | ||
572 | if (info->control.hw_key) | |
46bc8d4b | 573 | il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id); |
4bc85c13 WYG |
574 | |
575 | /* TODO need this for burst mode later on */ | |
46bc8d4b | 576 | il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id); |
4bc85c13 WYG |
577 | |
578 | /* set is_hcca to 0; it probably will never be implemented */ | |
46bc8d4b | 579 | il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id, 0); |
4bc85c13 WYG |
580 | |
581 | /* Total # bytes to be transmitted */ | |
582 | len = (u16)skb->len; | |
583 | tx_cmd->len = cpu_to_le16(len); | |
584 | ||
46bc8d4b SG |
585 | il_dbg_log_tx_data_frame(il, len, hdr); |
586 | il_update_stats(il, true, fc, len); | |
4bc85c13 WYG |
587 | tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; |
588 | tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
589 | ||
590 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
591 | txq->need_update = 1; | |
592 | } else { | |
593 | wait_write_ptr = 1; | |
594 | txq->need_update = 0; | |
595 | } | |
596 | ||
58de00a4 | 597 | D_TX("sequence nr = 0X%x\n", |
4bc85c13 | 598 | le16_to_cpu(out_cmd->hdr.sequence)); |
58de00a4 | 599 | D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
46bc8d4b SG |
600 | il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd)); |
601 | il_print_hex_dump(il, IL_DL_TX, (u8 *)tx_cmd->hdr, | |
4bc85c13 WYG |
602 | ieee80211_hdrlen(fc)); |
603 | ||
604 | /* | |
605 | * Use the first empty entry in this queue's command buffer array | |
606 | * to contain the Tx command and MAC header concatenated together | |
607 | * (payload data will be in another buffer). | |
608 | * Size of this varies, due to varying MAC header length. | |
609 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
610 | * of the MAC header (device reads on dword boundaries). | |
611 | * We'll tell device about this padding later. | |
612 | */ | |
e2ebc833 SG |
613 | len = sizeof(struct il3945_tx_cmd) + |
614 | sizeof(struct il_cmd_header) + hdr_len; | |
4bc85c13 WYG |
615 | len = (len + 3) & ~3; |
616 | ||
617 | /* Physical address of this Tx command's header (not MAC header!), | |
618 | * within command buffer array. */ | |
46bc8d4b | 619 | txcmd_phys = pci_map_single(il->pci_dev, &out_cmd->hdr, |
4bc85c13 WYG |
620 | len, PCI_DMA_TODEVICE); |
621 | /* we do not map meta data ... so we can safely access address to | |
622 | * provide to unmap command*/ | |
623 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); | |
624 | dma_unmap_len_set(out_meta, len, len); | |
625 | ||
626 | /* Add buffer containing Tx command and MAC(!) header to TFD's | |
627 | * first entry */ | |
46bc8d4b | 628 | il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, |
4bc85c13 WYG |
629 | txcmd_phys, len, 1, 0); |
630 | ||
631 | ||
632 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
633 | * if any (802.11 null frames have no payload). */ | |
634 | len = skb->len - hdr_len; | |
635 | if (len) { | |
46bc8d4b | 636 | phys_addr = pci_map_single(il->pci_dev, skb->data + hdr_len, |
4bc85c13 | 637 | len, PCI_DMA_TODEVICE); |
46bc8d4b | 638 | il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, |
4bc85c13 WYG |
639 | phys_addr, len, |
640 | 0, U32_PAD(len)); | |
641 | } | |
642 | ||
643 | ||
644 | /* Tell device the write index *just past* this latest filled TFD */ | |
e2ebc833 | 645 | q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd); |
46bc8d4b SG |
646 | il_txq_update_write_ptr(il, txq); |
647 | spin_unlock_irqrestore(&il->lock, flags); | |
4bc85c13 | 648 | |
e2ebc833 | 649 | if ((il_queue_space(q) < q->high_mark) |
46bc8d4b | 650 | && il->mac80211_registered) { |
4bc85c13 | 651 | if (wait_write_ptr) { |
46bc8d4b | 652 | spin_lock_irqsave(&il->lock, flags); |
4bc85c13 | 653 | txq->need_update = 1; |
46bc8d4b SG |
654 | il_txq_update_write_ptr(il, txq); |
655 | spin_unlock_irqrestore(&il->lock, flags); | |
4bc85c13 WYG |
656 | } |
657 | ||
46bc8d4b | 658 | il_stop_queue(il, txq); |
4bc85c13 WYG |
659 | } |
660 | ||
661 | return 0; | |
662 | ||
663 | drop_unlock: | |
46bc8d4b | 664 | spin_unlock_irqrestore(&il->lock, flags); |
4bc85c13 WYG |
665 | drop: |
666 | return -1; | |
667 | } | |
668 | ||
46bc8d4b | 669 | static int il3945_get_measurement(struct il_priv *il, |
4bc85c13 WYG |
670 | struct ieee80211_measurement_params *params, |
671 | u8 type) | |
672 | { | |
e2ebc833 SG |
673 | struct il_spectrum_cmd spectrum; |
674 | struct il_rx_packet *pkt; | |
675 | struct il_host_cmd cmd = { | |
4bc85c13 WYG |
676 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
677 | .data = (void *)&spectrum, | |
678 | .flags = CMD_WANT_SKB, | |
679 | }; | |
680 | u32 add_time = le64_to_cpu(params->start_time); | |
681 | int rc; | |
682 | int spectrum_resp_status; | |
683 | int duration = le16_to_cpu(params->duration); | |
46bc8d4b | 684 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 | 685 | |
46bc8d4b SG |
686 | if (il_is_associated(il, IL_RXON_CTX_BSS)) |
687 | add_time = il_usecs_to_beacons(il, | |
688 | le64_to_cpu(params->start_time) - il->_3945.last_tsf, | |
4bc85c13 WYG |
689 | le16_to_cpu(ctx->timing.beacon_interval)); |
690 | ||
691 | memset(&spectrum, 0, sizeof(spectrum)); | |
692 | ||
693 | spectrum.channel_count = cpu_to_le16(1); | |
694 | spectrum.flags = | |
695 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
696 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
697 | cmd.len = sizeof(spectrum); | |
698 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
699 | ||
46bc8d4b | 700 | if (il_is_associated(il, IL_RXON_CTX_BSS)) |
4bc85c13 | 701 | spectrum.start_time = |
46bc8d4b SG |
702 | il_add_beacon_time(il, |
703 | il->_3945.last_beacon_time, add_time, | |
4bc85c13 WYG |
704 | le16_to_cpu(ctx->timing.beacon_interval)); |
705 | else | |
706 | spectrum.start_time = 0; | |
707 | ||
708 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
709 | spectrum.channels[0].channel = params->channel; | |
710 | spectrum.channels[0].type = type; | |
711 | if (ctx->active.flags & RXON_FLG_BAND_24G_MSK) | |
712 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | | |
713 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
714 | ||
46bc8d4b | 715 | rc = il_send_cmd_sync(il, &cmd); |
4bc85c13 WYG |
716 | if (rc) |
717 | return rc; | |
718 | ||
e2ebc833 SG |
719 | pkt = (struct il_rx_packet *)cmd.reply_page; |
720 | if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { | |
9406f797 | 721 | IL_ERR("Bad return from REPLY_RX_ON_ASSOC command\n"); |
4bc85c13 WYG |
722 | rc = -EIO; |
723 | } | |
724 | ||
725 | spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status); | |
726 | switch (spectrum_resp_status) { | |
727 | case 0: /* Command will be handled */ | |
728 | if (pkt->u.spectrum.id != 0xff) { | |
58de00a4 | 729 | D_INFO("Replaced existing measurement: %d\n", |
4bc85c13 | 730 | pkt->u.spectrum.id); |
46bc8d4b | 731 | il->measurement_status &= ~MEASUREMENT_READY; |
4bc85c13 | 732 | } |
46bc8d4b | 733 | il->measurement_status |= MEASUREMENT_ACTIVE; |
4bc85c13 WYG |
734 | rc = 0; |
735 | break; | |
736 | ||
737 | case 1: /* Command will not be handled */ | |
738 | rc = -EAGAIN; | |
739 | break; | |
740 | } | |
741 | ||
46bc8d4b | 742 | il_free_pages(il, cmd.reply_page); |
4bc85c13 WYG |
743 | |
744 | return rc; | |
745 | } | |
746 | ||
46bc8d4b | 747 | static void il3945_rx_reply_alive(struct il_priv *il, |
e2ebc833 | 748 | struct il_rx_mem_buffer *rxb) |
4bc85c13 | 749 | { |
e2ebc833 SG |
750 | struct il_rx_packet *pkt = rxb_addr(rxb); |
751 | struct il_alive_resp *palive; | |
4bc85c13 WYG |
752 | struct delayed_work *pwork; |
753 | ||
754 | palive = &pkt->u.alive_frame; | |
755 | ||
58de00a4 | 756 | D_INFO("Alive ucode status 0x%08X revision " |
4bc85c13 WYG |
757 | "0x%01X 0x%01X\n", |
758 | palive->is_valid, palive->ver_type, | |
759 | palive->ver_subtype); | |
760 | ||
761 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
58de00a4 | 762 | D_INFO("Initialization Alive received.\n"); |
46bc8d4b | 763 | memcpy(&il->card_alive_init, &pkt->u.alive_frame, |
e2ebc833 | 764 | sizeof(struct il_alive_resp)); |
46bc8d4b | 765 | pwork = &il->init_alive_start; |
4bc85c13 | 766 | } else { |
58de00a4 | 767 | D_INFO("Runtime Alive received.\n"); |
46bc8d4b | 768 | memcpy(&il->card_alive, &pkt->u.alive_frame, |
e2ebc833 | 769 | sizeof(struct il_alive_resp)); |
46bc8d4b SG |
770 | pwork = &il->alive_start; |
771 | il3945_disable_events(il); | |
4bc85c13 WYG |
772 | } |
773 | ||
774 | /* We delay the ALIVE response by 5ms to | |
775 | * give the HW RF Kill time to activate... */ | |
776 | if (palive->is_valid == UCODE_VALID_OK) | |
46bc8d4b | 777 | queue_delayed_work(il->workqueue, pwork, |
4bc85c13 WYG |
778 | msecs_to_jiffies(5)); |
779 | else | |
9406f797 | 780 | IL_WARN("uCode did not respond OK.\n"); |
4bc85c13 WYG |
781 | } |
782 | ||
46bc8d4b | 783 | static void il3945_rx_reply_add_sta(struct il_priv *il, |
e2ebc833 | 784 | struct il_rx_mem_buffer *rxb) |
4bc85c13 | 785 | { |
be663ab6 | 786 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
e2ebc833 | 787 | struct il_rx_packet *pkt = rxb_addr(rxb); |
4bc85c13 WYG |
788 | #endif |
789 | ||
58de00a4 | 790 | D_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); |
4bc85c13 WYG |
791 | } |
792 | ||
46bc8d4b | 793 | static void il3945_rx_beacon_notif(struct il_priv *il, |
e2ebc833 | 794 | struct il_rx_mem_buffer *rxb) |
4bc85c13 | 795 | { |
e2ebc833 SG |
796 | struct il_rx_packet *pkt = rxb_addr(rxb); |
797 | struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status); | |
be663ab6 | 798 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
4bc85c13 WYG |
799 | u8 rate = beacon->beacon_notify_hdr.rate; |
800 | ||
58de00a4 | 801 | D_RX("beacon status %x retries %d iss %d " |
4bc85c13 WYG |
802 | "tsf %d %d rate %d\n", |
803 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
804 | beacon->beacon_notify_hdr.failure_frame, | |
805 | le32_to_cpu(beacon->ibss_mgr_status), | |
806 | le32_to_cpu(beacon->high_tsf), | |
807 | le32_to_cpu(beacon->low_tsf), rate); | |
808 | #endif | |
809 | ||
46bc8d4b | 810 | il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); |
4bc85c13 | 811 | |
4bc85c13 WYG |
812 | } |
813 | ||
814 | /* Handle notification from uCode that card's power state is changing | |
815 | * due to software, hardware, or critical temperature RFKILL */ | |
46bc8d4b | 816 | static void il3945_rx_card_state_notif(struct il_priv *il, |
e2ebc833 | 817 | struct il_rx_mem_buffer *rxb) |
4bc85c13 | 818 | { |
e2ebc833 | 819 | struct il_rx_packet *pkt = rxb_addr(rxb); |
4bc85c13 | 820 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
46bc8d4b | 821 | unsigned long status = il->status; |
4bc85c13 | 822 | |
9406f797 | 823 | IL_WARN("Card state received: HW:%s SW:%s\n", |
4bc85c13 WYG |
824 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
825 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
826 | ||
841b2cca | 827 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
4bc85c13 WYG |
828 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
829 | ||
830 | if (flags & HW_CARD_DISABLED) | |
46bc8d4b | 831 | set_bit(STATUS_RF_KILL_HW, &il->status); |
4bc85c13 | 832 | else |
46bc8d4b | 833 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
4bc85c13 WYG |
834 | |
835 | ||
46bc8d4b | 836 | il_scan_cancel(il); |
4bc85c13 WYG |
837 | |
838 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
46bc8d4b SG |
839 | test_bit(STATUS_RF_KILL_HW, &il->status))) |
840 | wiphy_rfkill_set_hw_state(il->hw->wiphy, | |
841 | test_bit(STATUS_RF_KILL_HW, &il->status)); | |
4bc85c13 | 842 | else |
46bc8d4b | 843 | wake_up(&il->wait_command_queue); |
4bc85c13 WYG |
844 | } |
845 | ||
846 | /** | |
e2ebc833 | 847 | * il3945_setup_rx_handlers - Initialize Rx handler callbacks |
4bc85c13 WYG |
848 | * |
849 | * Setup the RX handlers for each of the reply types sent from the uCode | |
850 | * to the host. | |
851 | * | |
852 | * This function chains into the hardware specific files for them to setup | |
853 | * any hardware specific handlers as well. | |
854 | */ | |
46bc8d4b | 855 | static void il3945_setup_rx_handlers(struct il_priv *il) |
4bc85c13 | 856 | { |
46bc8d4b SG |
857 | il->rx_handlers[REPLY_ALIVE] = il3945_rx_reply_alive; |
858 | il->rx_handlers[REPLY_ADD_STA] = il3945_rx_reply_add_sta; | |
859 | il->rx_handlers[REPLY_ERROR] = il_rx_reply_error; | |
860 | il->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = il_rx_csa; | |
861 | il->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = | |
e2ebc833 | 862 | il_rx_spectrum_measure_notif; |
46bc8d4b SG |
863 | il->rx_handlers[PM_SLEEP_NOTIFICATION] = il_rx_pm_sleep_notif; |
864 | il->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = | |
e2ebc833 | 865 | il_rx_pm_debug_statistics_notif; |
46bc8d4b | 866 | il->rx_handlers[BEACON_NOTIFICATION] = il3945_rx_beacon_notif; |
4bc85c13 WYG |
867 | |
868 | /* | |
869 | * The same handler is used for both the REPLY to a discrete | |
870 | * statistics request from the host as well as for the periodic | |
871 | * statistics notifications (after received beacons) from the uCode. | |
872 | */ | |
46bc8d4b SG |
873 | il->rx_handlers[REPLY_STATISTICS_CMD] = il3945_reply_statistics; |
874 | il->rx_handlers[STATISTICS_NOTIFICATION] = il3945_hw_rx_statistics; | |
4bc85c13 | 875 | |
46bc8d4b SG |
876 | il_setup_rx_scan_handlers(il); |
877 | il->rx_handlers[CARD_STATE_NOTIFICATION] = il3945_rx_card_state_notif; | |
4bc85c13 WYG |
878 | |
879 | /* Set up hardware specific Rx handlers */ | |
46bc8d4b | 880 | il3945_hw_rx_handler_setup(il); |
4bc85c13 WYG |
881 | } |
882 | ||
883 | /************************** RX-FUNCTIONS ****************************/ | |
884 | /* | |
885 | * Rx theory of operation | |
886 | * | |
887 | * The host allocates 32 DMA target addresses and passes the host address | |
e2ebc833 | 888 | * to the firmware at register IL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is |
4bc85c13 WYG |
889 | * 0 to 31 |
890 | * | |
891 | * Rx Queue Indexes | |
892 | * The host/firmware share two index registers for managing the Rx buffers. | |
893 | * | |
894 | * The READ index maps to the first position that the firmware may be writing | |
895 | * to -- the driver can read up to (but not including) this position and get | |
896 | * good data. | |
897 | * The READ index is managed by the firmware once the card is enabled. | |
898 | * | |
899 | * The WRITE index maps to the last position the driver has read from -- the | |
900 | * position preceding WRITE is the last slot the firmware can place a packet. | |
901 | * | |
902 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
903 | * WRITE = READ. | |
904 | * | |
905 | * During initialization, the host sets up the READ queue position to the first | |
906 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
907 | * | |
908 | * When the firmware places a packet in a buffer, it will advance the READ index | |
909 | * and fire the RX interrupt. The driver can then query the READ index and | |
910 | * process as many packets as possible, moving the WRITE index forward as it | |
911 | * resets the Rx queue buffers with new memory. | |
912 | * | |
913 | * The management in the driver is as follows: | |
914 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
915 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
916 | * to replenish the iwl->rxq->rx_free. | |
e2ebc833 | 917 | * + In il3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
4bc85c13 WYG |
918 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
919 | * 'processed' and 'read' driver indexes as well) | |
920 | * + A received packet is processed and handed to the kernel network stack, | |
921 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
922 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
923 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
924 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
925 | * were enough free buffers and RX_STALLED is set it is cleared. | |
926 | * | |
927 | * | |
928 | * Driver sequence: | |
929 | * | |
e2ebc833 SG |
930 | * il3945_rx_replenish() Replenishes rx_free list from rx_used, and calls |
931 | * il3945_rx_queue_restock | |
932 | * il3945_rx_queue_restock() Moves available buffers from rx_free into Rx | |
4bc85c13 WYG |
933 | * queue, updates firmware pointers, and updates |
934 | * the WRITE index. If insufficient rx_free buffers | |
e2ebc833 | 935 | * are available, schedules il3945_rx_replenish |
4bc85c13 WYG |
936 | * |
937 | * -- enable interrupts -- | |
e2ebc833 | 938 | * ISR - il3945_rx() Detach il_rx_mem_buffers from pool up to the |
4bc85c13 WYG |
939 | * READ INDEX, detaching the SKB from the pool. |
940 | * Moves the packet buffer from queue to rx_used. | |
e2ebc833 | 941 | * Calls il3945_rx_queue_restock to refill any empty |
4bc85c13 WYG |
942 | * slots. |
943 | * ... | |
944 | * | |
945 | */ | |
946 | ||
947 | /** | |
e2ebc833 | 948 | * il3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
4bc85c13 | 949 | */ |
46bc8d4b | 950 | static inline __le32 il3945_dma_addr2rbd_ptr(struct il_priv *il, |
4bc85c13 WYG |
951 | dma_addr_t dma_addr) |
952 | { | |
953 | return cpu_to_le32((u32)dma_addr); | |
954 | } | |
955 | ||
956 | /** | |
e2ebc833 | 957 | * il3945_rx_queue_restock - refill RX queue from pre-allocated pool |
4bc85c13 WYG |
958 | * |
959 | * If there are slots in the RX queue that need to be restocked, | |
960 | * and we have free pre-allocated buffers, fill the ranks as much | |
961 | * as we can, pulling from rx_free. | |
962 | * | |
963 | * This moves the 'write' index forward to catch up with 'processed', and | |
964 | * also updates the memory address in the firmware to reference the new | |
965 | * target buffer. | |
966 | */ | |
46bc8d4b | 967 | static void il3945_rx_queue_restock(struct il_priv *il) |
4bc85c13 | 968 | { |
46bc8d4b | 969 | struct il_rx_queue *rxq = &il->rxq; |
4bc85c13 | 970 | struct list_head *element; |
e2ebc833 | 971 | struct il_rx_mem_buffer *rxb; |
4bc85c13 WYG |
972 | unsigned long flags; |
973 | int write; | |
974 | ||
975 | spin_lock_irqsave(&rxq->lock, flags); | |
976 | write = rxq->write & ~0x7; | |
e2ebc833 | 977 | while ((il_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
4bc85c13 WYG |
978 | /* Get next free Rx buffer, remove from free list */ |
979 | element = rxq->rx_free.next; | |
e2ebc833 | 980 | rxb = list_entry(element, struct il_rx_mem_buffer, list); |
4bc85c13 WYG |
981 | list_del(element); |
982 | ||
983 | /* Point to Rx buffer via next RBD in circular buffer */ | |
46bc8d4b | 984 | rxq->bd[rxq->write] = il3945_dma_addr2rbd_ptr(il, rxb->page_dma); |
4bc85c13 WYG |
985 | rxq->queue[rxq->write] = rxb; |
986 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
987 | rxq->free_count--; | |
988 | } | |
989 | spin_unlock_irqrestore(&rxq->lock, flags); | |
990 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
991 | * refill it */ | |
992 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
46bc8d4b | 993 | queue_work(il->workqueue, &il->rx_replenish); |
4bc85c13 WYG |
994 | |
995 | ||
996 | /* If we've added more space for the firmware to place data, tell it. | |
997 | * Increment device's write pointer in multiples of 8. */ | |
998 | if ((rxq->write_actual != (rxq->write & ~0x7)) | |
999 | || (abs(rxq->write - rxq->read) > 7)) { | |
1000 | spin_lock_irqsave(&rxq->lock, flags); | |
1001 | rxq->need_update = 1; | |
1002 | spin_unlock_irqrestore(&rxq->lock, flags); | |
46bc8d4b | 1003 | il_rx_queue_update_write_ptr(il, rxq); |
4bc85c13 WYG |
1004 | } |
1005 | } | |
1006 | ||
1007 | /** | |
e2ebc833 | 1008 | * il3945_rx_replenish - Move all used packet from rx_used to rx_free |
4bc85c13 WYG |
1009 | * |
1010 | * When moving to rx_free an SKB is allocated for the slot. | |
1011 | * | |
e2ebc833 | 1012 | * Also restock the Rx queue via il3945_rx_queue_restock. |
4bc85c13 WYG |
1013 | * This is called as a scheduled work item (except for during initialization) |
1014 | */ | |
46bc8d4b | 1015 | static void il3945_rx_allocate(struct il_priv *il, gfp_t priority) |
4bc85c13 | 1016 | { |
46bc8d4b | 1017 | struct il_rx_queue *rxq = &il->rxq; |
4bc85c13 | 1018 | struct list_head *element; |
e2ebc833 | 1019 | struct il_rx_mem_buffer *rxb; |
4bc85c13 WYG |
1020 | struct page *page; |
1021 | unsigned long flags; | |
1022 | gfp_t gfp_mask = priority; | |
1023 | ||
1024 | while (1) { | |
1025 | spin_lock_irqsave(&rxq->lock, flags); | |
1026 | ||
1027 | if (list_empty(&rxq->rx_used)) { | |
1028 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1029 | return; | |
1030 | } | |
1031 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1032 | ||
1033 | if (rxq->free_count > RX_LOW_WATERMARK) | |
1034 | gfp_mask |= __GFP_NOWARN; | |
1035 | ||
46bc8d4b | 1036 | if (il->hw_params.rx_page_order > 0) |
4bc85c13 WYG |
1037 | gfp_mask |= __GFP_COMP; |
1038 | ||
1039 | /* Alloc a new receive buffer */ | |
46bc8d4b | 1040 | page = alloc_pages(gfp_mask, il->hw_params.rx_page_order); |
4bc85c13 WYG |
1041 | if (!page) { |
1042 | if (net_ratelimit()) | |
58de00a4 | 1043 | D_INFO("Failed to allocate SKB buffer.\n"); |
4bc85c13 WYG |
1044 | if ((rxq->free_count <= RX_LOW_WATERMARK) && |
1045 | net_ratelimit()) | |
b6297cd2 | 1046 | IL_ERR("Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n", |
4bc85c13 WYG |
1047 | priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", |
1048 | rxq->free_count); | |
1049 | /* We don't reschedule replenish work here -- we will | |
1050 | * call the restock method and if it still needs | |
1051 | * more buffers it will schedule replenish */ | |
1052 | break; | |
1053 | } | |
1054 | ||
1055 | spin_lock_irqsave(&rxq->lock, flags); | |
1056 | if (list_empty(&rxq->rx_used)) { | |
1057 | spin_unlock_irqrestore(&rxq->lock, flags); | |
46bc8d4b | 1058 | __free_pages(page, il->hw_params.rx_page_order); |
4bc85c13 WYG |
1059 | return; |
1060 | } | |
1061 | element = rxq->rx_used.next; | |
e2ebc833 | 1062 | rxb = list_entry(element, struct il_rx_mem_buffer, list); |
4bc85c13 WYG |
1063 | list_del(element); |
1064 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1065 | ||
1066 | rxb->page = page; | |
1067 | /* Get physical address of RB/SKB */ | |
46bc8d4b SG |
1068 | rxb->page_dma = pci_map_page(il->pci_dev, page, 0, |
1069 | PAGE_SIZE << il->hw_params.rx_page_order, | |
4bc85c13 WYG |
1070 | PCI_DMA_FROMDEVICE); |
1071 | ||
1072 | spin_lock_irqsave(&rxq->lock, flags); | |
1073 | ||
1074 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1075 | rxq->free_count++; | |
46bc8d4b | 1076 | il->alloc_rxb_page++; |
4bc85c13 WYG |
1077 | |
1078 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1079 | } | |
1080 | } | |
1081 | ||
46bc8d4b | 1082 | void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq) |
4bc85c13 WYG |
1083 | { |
1084 | unsigned long flags; | |
1085 | int i; | |
1086 | spin_lock_irqsave(&rxq->lock, flags); | |
1087 | INIT_LIST_HEAD(&rxq->rx_free); | |
1088 | INIT_LIST_HEAD(&rxq->rx_used); | |
1089 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
1090 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
1091 | /* In the reset function, these buffers may have been allocated | |
1092 | * to an SKB, so we need to unmap and free potential storage */ | |
1093 | if (rxq->pool[i].page != NULL) { | |
46bc8d4b SG |
1094 | pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma, |
1095 | PAGE_SIZE << il->hw_params.rx_page_order, | |
4bc85c13 | 1096 | PCI_DMA_FROMDEVICE); |
46bc8d4b | 1097 | __il_free_pages(il, rxq->pool[i].page); |
4bc85c13 WYG |
1098 | rxq->pool[i].page = NULL; |
1099 | } | |
1100 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
1101 | } | |
1102 | ||
1103 | /* Set us so that we have processed and used all buffers, but have | |
1104 | * not restocked the Rx queue with fresh buffers */ | |
1105 | rxq->read = rxq->write = 0; | |
1106 | rxq->write_actual = 0; | |
1107 | rxq->free_count = 0; | |
1108 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1109 | } | |
1110 | ||
e2ebc833 | 1111 | void il3945_rx_replenish(void *data) |
4bc85c13 | 1112 | { |
46bc8d4b | 1113 | struct il_priv *il = data; |
4bc85c13 WYG |
1114 | unsigned long flags; |
1115 | ||
46bc8d4b | 1116 | il3945_rx_allocate(il, GFP_KERNEL); |
4bc85c13 | 1117 | |
46bc8d4b SG |
1118 | spin_lock_irqsave(&il->lock, flags); |
1119 | il3945_rx_queue_restock(il); | |
1120 | spin_unlock_irqrestore(&il->lock, flags); | |
4bc85c13 WYG |
1121 | } |
1122 | ||
46bc8d4b | 1123 | static void il3945_rx_replenish_now(struct il_priv *il) |
4bc85c13 | 1124 | { |
46bc8d4b | 1125 | il3945_rx_allocate(il, GFP_ATOMIC); |
4bc85c13 | 1126 | |
46bc8d4b | 1127 | il3945_rx_queue_restock(il); |
4bc85c13 WYG |
1128 | } |
1129 | ||
1130 | ||
1131 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
1132 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
1133 | * This free routine walks the list of POOL entries and if SKB is set to | |
1134 | * non NULL it is unmapped and freed | |
1135 | */ | |
46bc8d4b | 1136 | static void il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq) |
4bc85c13 WYG |
1137 | { |
1138 | int i; | |
1139 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
1140 | if (rxq->pool[i].page != NULL) { | |
46bc8d4b SG |
1141 | pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma, |
1142 | PAGE_SIZE << il->hw_params.rx_page_order, | |
4bc85c13 | 1143 | PCI_DMA_FROMDEVICE); |
46bc8d4b | 1144 | __il_free_pages(il, rxq->pool[i].page); |
4bc85c13 WYG |
1145 | rxq->pool[i].page = NULL; |
1146 | } | |
1147 | } | |
1148 | ||
46bc8d4b | 1149 | dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, |
4bc85c13 | 1150 | rxq->bd_dma); |
46bc8d4b | 1151 | dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status), |
4bc85c13 WYG |
1152 | rxq->rb_stts, rxq->rb_stts_dma); |
1153 | rxq->bd = NULL; | |
1154 | rxq->rb_stts = NULL; | |
1155 | } | |
1156 | ||
1157 | ||
1158 | /* Convert linear signal-to-noise ratio into dB */ | |
1159 | static u8 ratio2dB[100] = { | |
1160 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
1161 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
1162 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
1163 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
1164 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
1165 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
1166 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
1167 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
1168 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
1169 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
1170 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
1171 | }; | |
1172 | ||
1173 | /* Calculates a relative dB value from a ratio of linear | |
1174 | * (i.e. not dB) signal levels. | |
1175 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
e2ebc833 | 1176 | int il3945_calc_db_from_ratio(int sig_ratio) |
4bc85c13 WYG |
1177 | { |
1178 | /* 1000:1 or higher just report as 60 dB */ | |
1179 | if (sig_ratio >= 1000) | |
1180 | return 60; | |
1181 | ||
1182 | /* 100:1 or higher, divide by 10 and use table, | |
1183 | * add 20 dB to make up for divide by 10 */ | |
1184 | if (sig_ratio >= 100) | |
1185 | return 20 + (int)ratio2dB[sig_ratio/10]; | |
1186 | ||
1187 | /* We shouldn't see this */ | |
1188 | if (sig_ratio < 1) | |
1189 | return 0; | |
1190 | ||
1191 | /* Use table for ratios 1:1 - 99:1 */ | |
1192 | return (int)ratio2dB[sig_ratio]; | |
1193 | } | |
1194 | ||
1195 | /** | |
e2ebc833 | 1196 | * il3945_rx_handle - Main entry function for receiving responses from uCode |
4bc85c13 | 1197 | * |
46bc8d4b | 1198 | * Uses the il->rx_handlers callback function array to invoke |
4bc85c13 WYG |
1199 | * the appropriate handlers, including command responses, |
1200 | * frame-received notifications, and other notifications. | |
1201 | */ | |
46bc8d4b | 1202 | static void il3945_rx_handle(struct il_priv *il) |
4bc85c13 | 1203 | { |
e2ebc833 SG |
1204 | struct il_rx_mem_buffer *rxb; |
1205 | struct il_rx_packet *pkt; | |
46bc8d4b | 1206 | struct il_rx_queue *rxq = &il->rxq; |
4bc85c13 WYG |
1207 | u32 r, i; |
1208 | int reclaim; | |
1209 | unsigned long flags; | |
1210 | u8 fill_rx = 0; | |
1211 | u32 count = 8; | |
1212 | int total_empty = 0; | |
1213 | ||
1214 | /* uCode's read index (stored in shared DRAM) indicates the last Rx | |
1215 | * buffer that the driver may process (last buffer filled by ucode). */ | |
1216 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; | |
1217 | i = rxq->read; | |
1218 | ||
1219 | /* calculate total frames need to be restock after handling RX */ | |
1220 | total_empty = r - rxq->write_actual; | |
1221 | if (total_empty < 0) | |
1222 | total_empty += RX_QUEUE_SIZE; | |
1223 | ||
1224 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
1225 | fill_rx = 1; | |
1226 | /* Rx interrupt, but nothing sent from uCode */ | |
1227 | if (i == r) | |
58de00a4 | 1228 | D_RX("r = %d, i = %d\n", r, i); |
4bc85c13 WYG |
1229 | |
1230 | while (i != r) { | |
1231 | int len; | |
1232 | ||
1233 | rxb = rxq->queue[i]; | |
1234 | ||
1235 | /* If an RXB doesn't have a Rx queue slot associated with it, | |
1236 | * then a bug has been introduced in the queue refilling | |
1237 | * routines -- catch it here */ | |
1238 | BUG_ON(rxb == NULL); | |
1239 | ||
1240 | rxq->queue[i] = NULL; | |
1241 | ||
46bc8d4b SG |
1242 | pci_unmap_page(il->pci_dev, rxb->page_dma, |
1243 | PAGE_SIZE << il->hw_params.rx_page_order, | |
4bc85c13 WYG |
1244 | PCI_DMA_FROMDEVICE); |
1245 | pkt = rxb_addr(rxb); | |
1246 | ||
1247 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
1248 | len += sizeof(u32); /* account for status word */ | |
4bc85c13 WYG |
1249 | |
1250 | /* Reclaim a command buffer only if this packet is a response | |
1251 | * to a (driver-originated) command. | |
1252 | * If the packet (e.g. Rx frame) originated from uCode, | |
1253 | * there is no command buffer to reclaim. | |
1254 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1255 | * but apparently a few don't get set; catch them here. */ | |
1256 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1257 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
1258 | (pkt->hdr.cmd != REPLY_TX); | |
1259 | ||
1260 | /* Based on type of command response or notification, | |
1261 | * handle those that need handling via function in | |
e2ebc833 | 1262 | * rx_handlers table. See il3945_setup_rx_handlers() */ |
46bc8d4b | 1263 | if (il->rx_handlers[pkt->hdr.cmd]) { |
58de00a4 | 1264 | D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i, |
e2ebc833 | 1265 | il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
46bc8d4b SG |
1266 | il->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
1267 | il->rx_handlers[pkt->hdr.cmd] (il, rxb); | |
4bc85c13 WYG |
1268 | } else { |
1269 | /* No handling needed */ | |
58de00a4 | 1270 | D_RX( |
4bc85c13 | 1271 | "r %d i %d No handler needed for %s, 0x%02x\n", |
e2ebc833 | 1272 | r, i, il_get_cmd_string(pkt->hdr.cmd), |
4bc85c13 WYG |
1273 | pkt->hdr.cmd); |
1274 | } | |
1275 | ||
1276 | /* | |
1277 | * XXX: After here, we should always check rxb->page | |
1278 | * against NULL before touching it or its virtual | |
1279 | * memory (pkt). Because some rx_handler might have | |
1280 | * already taken or freed the pages. | |
1281 | */ | |
1282 | ||
1283 | if (reclaim) { | |
1284 | /* Invoke any callbacks, transfer the buffer to caller, | |
e2ebc833 | 1285 | * and fire off the (possibly) blocking il_send_cmd() |
4bc85c13 WYG |
1286 | * as we reclaim the driver command queue */ |
1287 | if (rxb->page) | |
46bc8d4b | 1288 | il_tx_cmd_complete(il, rxb); |
4bc85c13 | 1289 | else |
9406f797 | 1290 | IL_WARN("Claim null rxb?\n"); |
4bc85c13 WYG |
1291 | } |
1292 | ||
1293 | /* Reuse the page if possible. For notification packets and | |
1294 | * SKBs that fail to Rx correctly, add them back into the | |
1295 | * rx_free list for reuse later. */ | |
1296 | spin_lock_irqsave(&rxq->lock, flags); | |
1297 | if (rxb->page != NULL) { | |
46bc8d4b SG |
1298 | rxb->page_dma = pci_map_page(il->pci_dev, rxb->page, |
1299 | 0, PAGE_SIZE << il->hw_params.rx_page_order, | |
4bc85c13 WYG |
1300 | PCI_DMA_FROMDEVICE); |
1301 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1302 | rxq->free_count++; | |
1303 | } else | |
1304 | list_add_tail(&rxb->list, &rxq->rx_used); | |
1305 | ||
1306 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1307 | ||
1308 | i = (i + 1) & RX_QUEUE_MASK; | |
1309 | /* If there are a lot of unused frames, | |
1310 | * restock the Rx queue so ucode won't assert. */ | |
1311 | if (fill_rx) { | |
1312 | count++; | |
1313 | if (count >= 8) { | |
1314 | rxq->read = i; | |
46bc8d4b | 1315 | il3945_rx_replenish_now(il); |
4bc85c13 WYG |
1316 | count = 0; |
1317 | } | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /* Backtrack one entry */ | |
1322 | rxq->read = i; | |
1323 | if (fill_rx) | |
46bc8d4b | 1324 | il3945_rx_replenish_now(il); |
4bc85c13 | 1325 | else |
46bc8d4b | 1326 | il3945_rx_queue_restock(il); |
4bc85c13 WYG |
1327 | } |
1328 | ||
1329 | /* call this function to flush any scheduled tasklet */ | |
46bc8d4b | 1330 | static inline void il3945_synchronize_irq(struct il_priv *il) |
4bc85c13 WYG |
1331 | { |
1332 | /* wait to make sure we flush pending tasklet*/ | |
46bc8d4b SG |
1333 | synchronize_irq(il->pci_dev->irq); |
1334 | tasklet_kill(&il->irq_tasklet); | |
4bc85c13 WYG |
1335 | } |
1336 | ||
e2ebc833 | 1337 | static const char *il3945_desc_lookup(int i) |
4bc85c13 WYG |
1338 | { |
1339 | switch (i) { | |
1340 | case 1: | |
1341 | return "FAIL"; | |
1342 | case 2: | |
1343 | return "BAD_PARAM"; | |
1344 | case 3: | |
1345 | return "BAD_CHECKSUM"; | |
1346 | case 4: | |
1347 | return "NMI_INTERRUPT"; | |
1348 | case 5: | |
1349 | return "SYSASSERT"; | |
1350 | case 6: | |
1351 | return "FATAL_ERROR"; | |
1352 | } | |
1353 | ||
1354 | return "UNKNOWN"; | |
1355 | } | |
1356 | ||
1357 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1358 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1359 | ||
46bc8d4b | 1360 | void il3945_dump_nic_error_log(struct il_priv *il) |
4bc85c13 WYG |
1361 | { |
1362 | u32 i; | |
1363 | u32 desc, time, count, base, data1; | |
1364 | u32 blink1, blink2, ilink1, ilink2; | |
1365 | ||
46bc8d4b | 1366 | base = le32_to_cpu(il->card_alive.error_event_table_ptr); |
4bc85c13 | 1367 | |
e2ebc833 | 1368 | if (!il3945_hw_valid_rtc_data_addr(base)) { |
9406f797 | 1369 | IL_ERR("Not valid error log pointer 0x%08X\n", base); |
4bc85c13 WYG |
1370 | return; |
1371 | } | |
1372 | ||
1373 | ||
46bc8d4b | 1374 | count = il_read_targ_mem(il, base); |
4bc85c13 WYG |
1375 | |
1376 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
9406f797 SG |
1377 | IL_ERR("Start IWL Error Log Dump:\n"); |
1378 | IL_ERR("Status: 0x%08lX, count: %d\n", | |
46bc8d4b | 1379 | il->status, count); |
4bc85c13 WYG |
1380 | } |
1381 | ||
9406f797 | 1382 | IL_ERR("Desc Time asrtPC blink2 " |
4bc85c13 WYG |
1383 | "ilink1 nmiPC Line\n"); |
1384 | for (i = ERROR_START_OFFSET; | |
1385 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
1386 | i += ERROR_ELEM_SIZE) { | |
46bc8d4b | 1387 | desc = il_read_targ_mem(il, base + i); |
4bc85c13 | 1388 | time = |
46bc8d4b | 1389 | il_read_targ_mem(il, base + i + 1 * sizeof(u32)); |
4bc85c13 | 1390 | blink1 = |
46bc8d4b | 1391 | il_read_targ_mem(il, base + i + 2 * sizeof(u32)); |
4bc85c13 | 1392 | blink2 = |
46bc8d4b | 1393 | il_read_targ_mem(il, base + i + 3 * sizeof(u32)); |
4bc85c13 | 1394 | ilink1 = |
46bc8d4b | 1395 | il_read_targ_mem(il, base + i + 4 * sizeof(u32)); |
4bc85c13 | 1396 | ilink2 = |
46bc8d4b | 1397 | il_read_targ_mem(il, base + i + 5 * sizeof(u32)); |
4bc85c13 | 1398 | data1 = |
46bc8d4b | 1399 | il_read_targ_mem(il, base + i + 6 * sizeof(u32)); |
4bc85c13 | 1400 | |
9406f797 | 1401 | IL_ERR( |
4bc85c13 | 1402 | "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", |
e2ebc833 | 1403 | il3945_desc_lookup(desc), desc, time, blink1, blink2, |
4bc85c13 | 1404 | ilink1, ilink2, data1); |
4bc85c13 WYG |
1405 | } |
1406 | } | |
1407 | ||
46bc8d4b | 1408 | static void il3945_irq_tasklet(struct il_priv *il) |
4bc85c13 WYG |
1409 | { |
1410 | u32 inta, handled = 0; | |
1411 | u32 inta_fh; | |
1412 | unsigned long flags; | |
be663ab6 | 1413 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
4bc85c13 WYG |
1414 | u32 inta_mask; |
1415 | #endif | |
1416 | ||
46bc8d4b | 1417 | spin_lock_irqsave(&il->lock, flags); |
4bc85c13 WYG |
1418 | |
1419 | /* Ack/clear/reset pending uCode interrupts. | |
1420 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1421 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
841b2cca SG |
1422 | inta = _il_rd(il, CSR_INT); |
1423 | _il_wr(il, CSR_INT, inta); | |
4bc85c13 WYG |
1424 | |
1425 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1426 | * Any new interrupts that happen after this, either while we're | |
1427 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
841b2cca SG |
1428 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); |
1429 | _il_wr(il, CSR_FH_INT_STATUS, inta_fh); | |
4bc85c13 | 1430 | |
be663ab6 | 1431 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
46bc8d4b | 1432 | if (il_get_debug_level(il) & IL_DL_ISR) { |
4bc85c13 | 1433 | /* just for debug */ |
841b2cca | 1434 | inta_mask = _il_rd(il, CSR_INT_MASK); |
58de00a4 | 1435 | D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
4bc85c13 WYG |
1436 | inta, inta_mask, inta_fh); |
1437 | } | |
1438 | #endif | |
1439 | ||
46bc8d4b | 1440 | spin_unlock_irqrestore(&il->lock, flags); |
4bc85c13 WYG |
1441 | |
1442 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
1443 | * atomic, make sure that inta covers all the interrupts that | |
1444 | * we've discovered, even if FH interrupt came in just after | |
1445 | * reading CSR_INT. */ | |
1446 | if (inta_fh & CSR39_FH_INT_RX_MASK) | |
1447 | inta |= CSR_INT_BIT_FH_RX; | |
1448 | if (inta_fh & CSR39_FH_INT_TX_MASK) | |
1449 | inta |= CSR_INT_BIT_FH_TX; | |
1450 | ||
1451 | /* Now service all interrupt bits discovered above. */ | |
1452 | if (inta & CSR_INT_BIT_HW_ERR) { | |
9406f797 | 1453 | IL_ERR("Hardware error detected. Restarting.\n"); |
4bc85c13 WYG |
1454 | |
1455 | /* Tell the device to stop sending interrupts */ | |
46bc8d4b | 1456 | il_disable_interrupts(il); |
4bc85c13 | 1457 | |
46bc8d4b SG |
1458 | il->isr_stats.hw++; |
1459 | il_irq_handle_error(il); | |
4bc85c13 WYG |
1460 | |
1461 | handled |= CSR_INT_BIT_HW_ERR; | |
1462 | ||
1463 | return; | |
1464 | } | |
1465 | ||
be663ab6 | 1466 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
46bc8d4b | 1467 | if (il_get_debug_level(il) & (IL_DL_ISR)) { |
4bc85c13 WYG |
1468 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1469 | if (inta & CSR_INT_BIT_SCD) { | |
58de00a4 | 1470 | D_ISR("Scheduler finished to transmit " |
4bc85c13 | 1471 | "the frame/frames.\n"); |
46bc8d4b | 1472 | il->isr_stats.sch++; |
4bc85c13 WYG |
1473 | } |
1474 | ||
1475 | /* Alive notification via Rx interrupt will do the real work */ | |
1476 | if (inta & CSR_INT_BIT_ALIVE) { | |
58de00a4 | 1477 | D_ISR("Alive interrupt\n"); |
46bc8d4b | 1478 | il->isr_stats.alive++; |
4bc85c13 WYG |
1479 | } |
1480 | } | |
1481 | #endif | |
1482 | /* Safely ignore these bits for debug checks below */ | |
1483 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1484 | ||
1485 | /* Error detected by uCode */ | |
1486 | if (inta & CSR_INT_BIT_SW_ERR) { | |
9406f797 | 1487 | IL_ERR("Microcode SW error detected. " |
4bc85c13 | 1488 | "Restarting 0x%X.\n", inta); |
46bc8d4b SG |
1489 | il->isr_stats.sw++; |
1490 | il_irq_handle_error(il); | |
4bc85c13 WYG |
1491 | handled |= CSR_INT_BIT_SW_ERR; |
1492 | } | |
1493 | ||
1494 | /* uCode wakes up after power-down sleep */ | |
1495 | if (inta & CSR_INT_BIT_WAKEUP) { | |
58de00a4 | 1496 | D_ISR("Wakeup interrupt\n"); |
46bc8d4b SG |
1497 | il_rx_queue_update_write_ptr(il, &il->rxq); |
1498 | il_txq_update_write_ptr(il, &il->txq[0]); | |
1499 | il_txq_update_write_ptr(il, &il->txq[1]); | |
1500 | il_txq_update_write_ptr(il, &il->txq[2]); | |
1501 | il_txq_update_write_ptr(il, &il->txq[3]); | |
1502 | il_txq_update_write_ptr(il, &il->txq[4]); | |
1503 | il_txq_update_write_ptr(il, &il->txq[5]); | |
1504 | ||
1505 | il->isr_stats.wakeup++; | |
4bc85c13 WYG |
1506 | handled |= CSR_INT_BIT_WAKEUP; |
1507 | } | |
1508 | ||
1509 | /* All uCode command responses, including Tx command responses, | |
1510 | * Rx "responses" (frame-received notification), and other | |
1511 | * notifications from uCode come through here*/ | |
1512 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
46bc8d4b SG |
1513 | il3945_rx_handle(il); |
1514 | il->isr_stats.rx++; | |
4bc85c13 WYG |
1515 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1516 | } | |
1517 | ||
1518 | if (inta & CSR_INT_BIT_FH_TX) { | |
58de00a4 | 1519 | D_ISR("Tx interrupt\n"); |
46bc8d4b | 1520 | il->isr_stats.tx++; |
4bc85c13 | 1521 | |
841b2cca | 1522 | _il_wr(il, CSR_FH_INT_STATUS, (1 << 6)); |
0c1a94e2 | 1523 | il_wr(il, FH39_TCSR_CREDIT |
4bc85c13 WYG |
1524 | (FH39_SRVC_CHNL), 0x0); |
1525 | handled |= CSR_INT_BIT_FH_TX; | |
1526 | } | |
1527 | ||
1528 | if (inta & ~handled) { | |
9406f797 | 1529 | IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled); |
46bc8d4b | 1530 | il->isr_stats.unhandled++; |
4bc85c13 WYG |
1531 | } |
1532 | ||
46bc8d4b | 1533 | if (inta & ~il->inta_mask) { |
9406f797 | 1534 | IL_WARN("Disabled INTA bits 0x%08x were pending\n", |
46bc8d4b | 1535 | inta & ~il->inta_mask); |
9406f797 | 1536 | IL_WARN(" with FH_INT = 0x%08x\n", inta_fh); |
4bc85c13 WYG |
1537 | } |
1538 | ||
1539 | /* Re-enable all interrupts */ | |
1540 | /* only Re-enable if disabled by irq */ | |
46bc8d4b SG |
1541 | if (test_bit(STATUS_INT_ENABLED, &il->status)) |
1542 | il_enable_interrupts(il); | |
4bc85c13 | 1543 | |
be663ab6 | 1544 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
46bc8d4b | 1545 | if (il_get_debug_level(il) & (IL_DL_ISR)) { |
841b2cca SG |
1546 | inta = _il_rd(il, CSR_INT); |
1547 | inta_mask = _il_rd(il, CSR_INT_MASK); | |
1548 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); | |
58de00a4 | 1549 | D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4bc85c13 WYG |
1550 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1551 | } | |
1552 | #endif | |
1553 | } | |
1554 | ||
46bc8d4b | 1555 | static int il3945_get_channels_for_scan(struct il_priv *il, |
4bc85c13 WYG |
1556 | enum ieee80211_band band, |
1557 | u8 is_active, u8 n_probes, | |
e2ebc833 | 1558 | struct il3945_scan_channel *scan_ch, |
4bc85c13 WYG |
1559 | struct ieee80211_vif *vif) |
1560 | { | |
1561 | struct ieee80211_channel *chan; | |
1562 | const struct ieee80211_supported_band *sband; | |
e2ebc833 | 1563 | const struct il_channel_info *ch_info; |
4bc85c13 WYG |
1564 | u16 passive_dwell = 0; |
1565 | u16 active_dwell = 0; | |
1566 | int added, i; | |
1567 | ||
46bc8d4b | 1568 | sband = il_get_hw_mode(il, band); |
4bc85c13 WYG |
1569 | if (!sband) |
1570 | return 0; | |
1571 | ||
46bc8d4b SG |
1572 | active_dwell = il_get_active_dwell_time(il, band, n_probes); |
1573 | passive_dwell = il_get_passive_dwell_time(il, band, vif); | |
4bc85c13 WYG |
1574 | |
1575 | if (passive_dwell <= active_dwell) | |
1576 | passive_dwell = active_dwell + 1; | |
1577 | ||
46bc8d4b SG |
1578 | for (i = 0, added = 0; i < il->scan_request->n_channels; i++) { |
1579 | chan = il->scan_request->channels[i]; | |
4bc85c13 WYG |
1580 | |
1581 | if (chan->band != band) | |
1582 | continue; | |
1583 | ||
1584 | scan_ch->channel = chan->hw_value; | |
1585 | ||
46bc8d4b | 1586 | ch_info = il_get_channel_info(il, band, |
be663ab6 | 1587 | scan_ch->channel); |
e2ebc833 | 1588 | if (!il_is_channel_valid(ch_info)) { |
58de00a4 | 1589 | D_SCAN( |
be663ab6 WYG |
1590 | "Channel %d is INVALID for this band.\n", |
1591 | scan_ch->channel); | |
4bc85c13 WYG |
1592 | continue; |
1593 | } | |
1594 | ||
1595 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
1596 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
1597 | /* If passive , set up for auto-switch | |
1598 | * and use long active_dwell time. | |
1599 | */ | |
e2ebc833 | 1600 | if (!is_active || il_is_channel_passive(ch_info) || |
4bc85c13 WYG |
1601 | (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
1602 | scan_ch->type = 0; /* passive */ | |
46bc8d4b | 1603 | if (IL_UCODE_API(il->ucode_ver) == 1) |
4bc85c13 WYG |
1604 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); |
1605 | } else { | |
1606 | scan_ch->type = 1; /* active */ | |
1607 | } | |
1608 | ||
1609 | /* Set direct probe bits. These may be used both for active | |
1610 | * scan channels (probes gets sent right away), | |
1611 | * or for passive channels (probes get se sent only after | |
1612 | * hearing clear Rx packet).*/ | |
46bc8d4b | 1613 | if (IL_UCODE_API(il->ucode_ver) >= 2) { |
4bc85c13 WYG |
1614 | if (n_probes) |
1615 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); | |
1616 | } else { | |
1617 | /* uCode v1 does not allow setting direct probe bits on | |
1618 | * passive channel. */ | |
1619 | if ((scan_ch->type & 1) && n_probes) | |
1620 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); | |
1621 | } | |
1622 | ||
1623 | /* Set txpower levels to defaults */ | |
1624 | scan_ch->tpc.dsp_atten = 110; | |
1625 | /* scan_pwr_info->tpc.dsp_atten; */ | |
1626 | ||
1627 | /*scan_pwr_info->tpc.tx_gain; */ | |
1628 | if (band == IEEE80211_BAND_5GHZ) | |
1629 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; | |
1630 | else { | |
1631 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
1632 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
1633 | * power level: | |
1634 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; | |
1635 | */ | |
1636 | } | |
1637 | ||
58de00a4 | 1638 | D_SCAN("Scanning %d [%s %d]\n", |
4bc85c13 WYG |
1639 | scan_ch->channel, |
1640 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
1641 | (scan_ch->type & 1) ? | |
1642 | active_dwell : passive_dwell); | |
1643 | ||
1644 | scan_ch++; | |
1645 | added++; | |
1646 | } | |
1647 | ||
58de00a4 | 1648 | D_SCAN("total channels to scan %d\n", added); |
4bc85c13 WYG |
1649 | return added; |
1650 | } | |
1651 | ||
46bc8d4b | 1652 | static void il3945_init_hw_rates(struct il_priv *il, |
4bc85c13 WYG |
1653 | struct ieee80211_rate *rates) |
1654 | { | |
1655 | int i; | |
1656 | ||
e2ebc833 SG |
1657 | for (i = 0; i < IL_RATE_COUNT_LEGACY; i++) { |
1658 | rates[i].bitrate = il3945_rates[i].ieee * 5; | |
4bc85c13 WYG |
1659 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ |
1660 | rates[i].hw_value_short = i; | |
1661 | rates[i].flags = 0; | |
e2ebc833 | 1662 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IL_FIRST_OFDM_RATE)) { |
4bc85c13 WYG |
1663 | /* |
1664 | * If CCK != 1M then set short preamble rate flag. | |
1665 | */ | |
e2ebc833 | 1666 | rates[i].flags |= (il3945_rates[i].plcp == 10) ? |
4bc85c13 WYG |
1667 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
1668 | } | |
1669 | } | |
1670 | } | |
1671 | ||
1672 | /****************************************************************************** | |
1673 | * | |
1674 | * uCode download functions | |
1675 | * | |
1676 | ******************************************************************************/ | |
1677 | ||
46bc8d4b | 1678 | static void il3945_dealloc_ucode_pci(struct il_priv *il) |
4bc85c13 | 1679 | { |
46bc8d4b SG |
1680 | il_free_fw_desc(il->pci_dev, &il->ucode_code); |
1681 | il_free_fw_desc(il->pci_dev, &il->ucode_data); | |
1682 | il_free_fw_desc(il->pci_dev, &il->ucode_data_backup); | |
1683 | il_free_fw_desc(il->pci_dev, &il->ucode_init); | |
1684 | il_free_fw_desc(il->pci_dev, &il->ucode_init_data); | |
1685 | il_free_fw_desc(il->pci_dev, &il->ucode_boot); | |
4bc85c13 WYG |
1686 | } |
1687 | ||
1688 | /** | |
e2ebc833 | 1689 | * il3945_verify_inst_full - verify runtime uCode image in card vs. host, |
4bc85c13 WYG |
1690 | * looking at all data. |
1691 | */ | |
46bc8d4b | 1692 | static int il3945_verify_inst_full(struct il_priv *il, __le32 *image, u32 len) |
4bc85c13 WYG |
1693 | { |
1694 | u32 val; | |
1695 | u32 save_len = len; | |
1696 | int rc = 0; | |
1697 | u32 errcnt; | |
1698 | ||
58de00a4 | 1699 | D_INFO("ucode inst image size is %u\n", len); |
4bc85c13 | 1700 | |
0c1a94e2 | 1701 | il_wr(il, HBUS_TARG_MEM_RADDR, |
4bc85c13 WYG |
1702 | IWL39_RTC_INST_LOWER_BOUND); |
1703 | ||
1704 | errcnt = 0; | |
1705 | for (; len > 0; len -= sizeof(u32), image++) { | |
1706 | /* read data comes through single port, auto-incr addr */ | |
1707 | /* NOTE: Use the debugless read so we don't flood kernel log | |
e2ebc833 | 1708 | * if IL_DL_IO is set */ |
1c8cae57 | 1709 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); |
4bc85c13 | 1710 | if (val != le32_to_cpu(*image)) { |
9406f797 | 1711 | IL_ERR("uCode INST section is invalid at " |
4bc85c13 WYG |
1712 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
1713 | save_len - len, val, le32_to_cpu(*image)); | |
1714 | rc = -EIO; | |
1715 | errcnt++; | |
1716 | if (errcnt >= 20) | |
1717 | break; | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | ||
1722 | if (!errcnt) | |
58de00a4 | 1723 | D_INFO( |
4bc85c13 WYG |
1724 | "ucode image in INSTRUCTION memory is good\n"); |
1725 | ||
1726 | return rc; | |
1727 | } | |
1728 | ||
1729 | ||
1730 | /** | |
e2ebc833 | 1731 | * il3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
4bc85c13 WYG |
1732 | * using sample data 100 bytes apart. If these sample points are good, |
1733 | * it's a pretty good bet that everything between them is good, too. | |
1734 | */ | |
46bc8d4b | 1735 | static int il3945_verify_inst_sparse(struct il_priv *il, __le32 *image, u32 len) |
4bc85c13 WYG |
1736 | { |
1737 | u32 val; | |
1738 | int rc = 0; | |
1739 | u32 errcnt = 0; | |
1740 | u32 i; | |
1741 | ||
58de00a4 | 1742 | D_INFO("ucode inst image size is %u\n", len); |
4bc85c13 WYG |
1743 | |
1744 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
1745 | /* read data comes through single port, auto-incr addr */ | |
1746 | /* NOTE: Use the debugless read so we don't flood kernel log | |
e2ebc833 | 1747 | * if IL_DL_IO is set */ |
0c1a94e2 | 1748 | il_wr(il, HBUS_TARG_MEM_RADDR, |
4bc85c13 | 1749 | i + IWL39_RTC_INST_LOWER_BOUND); |
1c8cae57 | 1750 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); |
4bc85c13 WYG |
1751 | if (val != le32_to_cpu(*image)) { |
1752 | #if 0 /* Enable this if you want to see details */ | |
9406f797 | 1753 | IL_ERR("uCode INST section is invalid at " |
4bc85c13 WYG |
1754 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
1755 | i, val, *image); | |
1756 | #endif | |
1757 | rc = -EIO; | |
1758 | errcnt++; | |
1759 | if (errcnt >= 3) | |
1760 | break; | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | return rc; | |
1765 | } | |
1766 | ||
1767 | ||
1768 | /** | |
e2ebc833 | 1769 | * il3945_verify_ucode - determine which instruction image is in SRAM, |
4bc85c13 WYG |
1770 | * and verify its contents |
1771 | */ | |
46bc8d4b | 1772 | static int il3945_verify_ucode(struct il_priv *il) |
4bc85c13 WYG |
1773 | { |
1774 | __le32 *image; | |
1775 | u32 len; | |
1776 | int rc = 0; | |
1777 | ||
1778 | /* Try bootstrap */ | |
46bc8d4b SG |
1779 | image = (__le32 *)il->ucode_boot.v_addr; |
1780 | len = il->ucode_boot.len; | |
1781 | rc = il3945_verify_inst_sparse(il, image, len); | |
4bc85c13 | 1782 | if (rc == 0) { |
58de00a4 | 1783 | D_INFO("Bootstrap uCode is good in inst SRAM\n"); |
4bc85c13 WYG |
1784 | return 0; |
1785 | } | |
1786 | ||
1787 | /* Try initialize */ | |
46bc8d4b SG |
1788 | image = (__le32 *)il->ucode_init.v_addr; |
1789 | len = il->ucode_init.len; | |
1790 | rc = il3945_verify_inst_sparse(il, image, len); | |
4bc85c13 | 1791 | if (rc == 0) { |
58de00a4 | 1792 | D_INFO("Initialize uCode is good in inst SRAM\n"); |
4bc85c13 WYG |
1793 | return 0; |
1794 | } | |
1795 | ||
1796 | /* Try runtime/protocol */ | |
46bc8d4b SG |
1797 | image = (__le32 *)il->ucode_code.v_addr; |
1798 | len = il->ucode_code.len; | |
1799 | rc = il3945_verify_inst_sparse(il, image, len); | |
4bc85c13 | 1800 | if (rc == 0) { |
58de00a4 | 1801 | D_INFO("Runtime uCode is good in inst SRAM\n"); |
4bc85c13 WYG |
1802 | return 0; |
1803 | } | |
1804 | ||
9406f797 | 1805 | IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
4bc85c13 WYG |
1806 | |
1807 | /* Since nothing seems to match, show first several data entries in | |
1808 | * instruction SRAM, so maybe visual inspection will give a clue. | |
1809 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
46bc8d4b SG |
1810 | image = (__le32 *)il->ucode_boot.v_addr; |
1811 | len = il->ucode_boot.len; | |
1812 | rc = il3945_verify_inst_full(il, image, len); | |
4bc85c13 WYG |
1813 | |
1814 | return rc; | |
1815 | } | |
1816 | ||
46bc8d4b | 1817 | static void il3945_nic_start(struct il_priv *il) |
4bc85c13 WYG |
1818 | { |
1819 | /* Remove all resets to allow NIC to operate */ | |
841b2cca | 1820 | _il_wr(il, CSR_RESET, 0); |
4bc85c13 WYG |
1821 | } |
1822 | ||
1823 | #define IWL3945_UCODE_GET(item) \ | |
e2ebc833 | 1824 | static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\ |
4bc85c13 | 1825 | { \ |
be663ab6 | 1826 | return le32_to_cpu(ucode->v1.item); \ |
4bc85c13 WYG |
1827 | } |
1828 | ||
e2ebc833 | 1829 | static u32 il3945_ucode_get_header_size(u32 api_ver) |
4bc85c13 WYG |
1830 | { |
1831 | return 24; | |
1832 | } | |
1833 | ||
e2ebc833 | 1834 | static u8 *il3945_ucode_get_data(const struct il_ucode_header *ucode) |
4bc85c13 | 1835 | { |
be663ab6 | 1836 | return (u8 *) ucode->v1.data; |
4bc85c13 WYG |
1837 | } |
1838 | ||
1839 | IWL3945_UCODE_GET(inst_size); | |
1840 | IWL3945_UCODE_GET(data_size); | |
1841 | IWL3945_UCODE_GET(init_size); | |
1842 | IWL3945_UCODE_GET(init_data_size); | |
1843 | IWL3945_UCODE_GET(boot_size); | |
1844 | ||
1845 | /** | |
e2ebc833 | 1846 | * il3945_read_ucode - Read uCode images from disk file. |
4bc85c13 WYG |
1847 | * |
1848 | * Copy into buffers for card to fetch via bus-mastering | |
1849 | */ | |
46bc8d4b | 1850 | static int il3945_read_ucode(struct il_priv *il) |
4bc85c13 | 1851 | { |
e2ebc833 | 1852 | const struct il_ucode_header *ucode; |
4bc85c13 WYG |
1853 | int ret = -EINVAL, index; |
1854 | const struct firmware *ucode_raw; | |
1855 | /* firmware file name contains uCode/driver compatibility version */ | |
46bc8d4b SG |
1856 | const char *name_pre = il->cfg->fw_name_pre; |
1857 | const unsigned int api_max = il->cfg->ucode_api_max; | |
1858 | const unsigned int api_min = il->cfg->ucode_api_min; | |
4bc85c13 WYG |
1859 | char buf[25]; |
1860 | u8 *src; | |
1861 | size_t len; | |
1862 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; | |
1863 | ||
1864 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
1865 | * request_firmware() is synchronous, file is in memory on return. */ | |
1866 | for (index = api_max; index >= api_min; index--) { | |
1867 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
46bc8d4b | 1868 | ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev); |
4bc85c13 | 1869 | if (ret < 0) { |
9406f797 | 1870 | IL_ERR("%s firmware file req failed: %d\n", |
4bc85c13 WYG |
1871 | buf, ret); |
1872 | if (ret == -ENOENT) | |
1873 | continue; | |
1874 | else | |
1875 | goto error; | |
1876 | } else { | |
1877 | if (index < api_max) | |
9406f797 | 1878 | IL_ERR("Loaded firmware %s, " |
4bc85c13 WYG |
1879 | "which is deprecated. " |
1880 | " Please use API v%u instead.\n", | |
1881 | buf, api_max); | |
58de00a4 | 1882 | D_INFO("Got firmware '%s' file " |
4bc85c13 WYG |
1883 | "(%zd bytes) from disk\n", |
1884 | buf, ucode_raw->size); | |
1885 | break; | |
1886 | } | |
1887 | } | |
1888 | ||
1889 | if (ret < 0) | |
1890 | goto error; | |
1891 | ||
1892 | /* Make sure that we got at least our header! */ | |
e2ebc833 | 1893 | if (ucode_raw->size < il3945_ucode_get_header_size(1)) { |
9406f797 | 1894 | IL_ERR("File size way too small!\n"); |
4bc85c13 WYG |
1895 | ret = -EINVAL; |
1896 | goto err_release; | |
1897 | } | |
1898 | ||
1899 | /* Data from ucode file: header followed by uCode images */ | |
e2ebc833 | 1900 | ucode = (struct il_ucode_header *)ucode_raw->data; |
4bc85c13 | 1901 | |
46bc8d4b SG |
1902 | il->ucode_ver = le32_to_cpu(ucode->ver); |
1903 | api_ver = IL_UCODE_API(il->ucode_ver); | |
e2ebc833 SG |
1904 | inst_size = il3945_ucode_get_inst_size(ucode); |
1905 | data_size = il3945_ucode_get_data_size(ucode); | |
1906 | init_size = il3945_ucode_get_init_size(ucode); | |
1907 | init_data_size = il3945_ucode_get_init_data_size(ucode); | |
1908 | boot_size = il3945_ucode_get_boot_size(ucode); | |
1909 | src = il3945_ucode_get_data(ucode); | |
4bc85c13 WYG |
1910 | |
1911 | /* api_ver should match the api version forming part of the | |
1912 | * firmware filename ... but we don't check for that and only rely | |
1913 | * on the API version read from firmware header from here on forward */ | |
1914 | ||
1915 | if (api_ver < api_min || api_ver > api_max) { | |
9406f797 | 1916 | IL_ERR("Driver unable to support your firmware API. " |
4bc85c13 WYG |
1917 | "Driver supports v%u, firmware is v%u.\n", |
1918 | api_max, api_ver); | |
46bc8d4b | 1919 | il->ucode_ver = 0; |
4bc85c13 WYG |
1920 | ret = -EINVAL; |
1921 | goto err_release; | |
1922 | } | |
1923 | if (api_ver != api_max) | |
9406f797 | 1924 | IL_ERR("Firmware has old API version. Expected %u, " |
4bc85c13 WYG |
1925 | "got %u. New firmware can be obtained " |
1926 | "from http://www.intellinuxwireless.org.\n", | |
1927 | api_max, api_ver); | |
1928 | ||
9406f797 | 1929 | IL_INFO("loaded firmware version %u.%u.%u.%u\n", |
46bc8d4b SG |
1930 | IL_UCODE_MAJOR(il->ucode_ver), |
1931 | IL_UCODE_MINOR(il->ucode_ver), | |
1932 | IL_UCODE_API(il->ucode_ver), | |
1933 | IL_UCODE_SERIAL(il->ucode_ver)); | |
4bc85c13 | 1934 | |
46bc8d4b SG |
1935 | snprintf(il->hw->wiphy->fw_version, |
1936 | sizeof(il->hw->wiphy->fw_version), | |
4bc85c13 | 1937 | "%u.%u.%u.%u", |
46bc8d4b SG |
1938 | IL_UCODE_MAJOR(il->ucode_ver), |
1939 | IL_UCODE_MINOR(il->ucode_ver), | |
1940 | IL_UCODE_API(il->ucode_ver), | |
1941 | IL_UCODE_SERIAL(il->ucode_ver)); | |
1942 | ||
58de00a4 | 1943 | D_INFO("f/w package hdr ucode version raw = 0x%x\n", |
46bc8d4b | 1944 | il->ucode_ver); |
58de00a4 | 1945 | D_INFO("f/w package hdr runtime inst size = %u\n", |
4bc85c13 | 1946 | inst_size); |
58de00a4 | 1947 | D_INFO("f/w package hdr runtime data size = %u\n", |
4bc85c13 | 1948 | data_size); |
58de00a4 | 1949 | D_INFO("f/w package hdr init inst size = %u\n", |
4bc85c13 | 1950 | init_size); |
58de00a4 | 1951 | D_INFO("f/w package hdr init data size = %u\n", |
4bc85c13 | 1952 | init_data_size); |
58de00a4 | 1953 | D_INFO("f/w package hdr boot inst size = %u\n", |
4bc85c13 WYG |
1954 | boot_size); |
1955 | ||
1956 | ||
1957 | /* Verify size of file vs. image size info in file's header */ | |
e2ebc833 | 1958 | if (ucode_raw->size != il3945_ucode_get_header_size(api_ver) + |
4bc85c13 WYG |
1959 | inst_size + data_size + init_size + |
1960 | init_data_size + boot_size) { | |
1961 | ||
58de00a4 | 1962 | D_INFO( |
4bc85c13 WYG |
1963 | "uCode file size %zd does not match expected size\n", |
1964 | ucode_raw->size); | |
1965 | ret = -EINVAL; | |
1966 | goto err_release; | |
1967 | } | |
1968 | ||
1969 | /* Verify that uCode images will fit in card's SRAM */ | |
1970 | if (inst_size > IWL39_MAX_INST_SIZE) { | |
58de00a4 | 1971 | D_INFO("uCode instr len %d too large to fit in\n", |
4bc85c13 WYG |
1972 | inst_size); |
1973 | ret = -EINVAL; | |
1974 | goto err_release; | |
1975 | } | |
1976 | ||
1977 | if (data_size > IWL39_MAX_DATA_SIZE) { | |
58de00a4 | 1978 | D_INFO("uCode data len %d too large to fit in\n", |
4bc85c13 WYG |
1979 | data_size); |
1980 | ret = -EINVAL; | |
1981 | goto err_release; | |
1982 | } | |
1983 | if (init_size > IWL39_MAX_INST_SIZE) { | |
58de00a4 | 1984 | D_INFO( |
4bc85c13 WYG |
1985 | "uCode init instr len %d too large to fit in\n", |
1986 | init_size); | |
1987 | ret = -EINVAL; | |
1988 | goto err_release; | |
1989 | } | |
1990 | if (init_data_size > IWL39_MAX_DATA_SIZE) { | |
58de00a4 | 1991 | D_INFO( |
4bc85c13 WYG |
1992 | "uCode init data len %d too large to fit in\n", |
1993 | init_data_size); | |
1994 | ret = -EINVAL; | |
1995 | goto err_release; | |
1996 | } | |
1997 | if (boot_size > IWL39_MAX_BSM_SIZE) { | |
58de00a4 | 1998 | D_INFO( |
4bc85c13 WYG |
1999 | "uCode boot instr len %d too large to fit in\n", |
2000 | boot_size); | |
2001 | ret = -EINVAL; | |
2002 | goto err_release; | |
2003 | } | |
2004 | ||
2005 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2006 | ||
2007 | /* Runtime instructions and 2 copies of data: | |
2008 | * 1) unmodified from disk | |
2009 | * 2) backup cache for save/restore during power-downs */ | |
46bc8d4b SG |
2010 | il->ucode_code.len = inst_size; |
2011 | il_alloc_fw_desc(il->pci_dev, &il->ucode_code); | |
4bc85c13 | 2012 | |
46bc8d4b SG |
2013 | il->ucode_data.len = data_size; |
2014 | il_alloc_fw_desc(il->pci_dev, &il->ucode_data); | |
4bc85c13 | 2015 | |
46bc8d4b SG |
2016 | il->ucode_data_backup.len = data_size; |
2017 | il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup); | |
4bc85c13 | 2018 | |
46bc8d4b SG |
2019 | if (!il->ucode_code.v_addr || !il->ucode_data.v_addr || |
2020 | !il->ucode_data_backup.v_addr) | |
4bc85c13 WYG |
2021 | goto err_pci_alloc; |
2022 | ||
2023 | /* Initialization instructions and data */ | |
2024 | if (init_size && init_data_size) { | |
46bc8d4b SG |
2025 | il->ucode_init.len = init_size; |
2026 | il_alloc_fw_desc(il->pci_dev, &il->ucode_init); | |
4bc85c13 | 2027 | |
46bc8d4b SG |
2028 | il->ucode_init_data.len = init_data_size; |
2029 | il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data); | |
4bc85c13 | 2030 | |
46bc8d4b | 2031 | if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr) |
4bc85c13 WYG |
2032 | goto err_pci_alloc; |
2033 | } | |
2034 | ||
2035 | /* Bootstrap (instructions only, no data) */ | |
2036 | if (boot_size) { | |
46bc8d4b SG |
2037 | il->ucode_boot.len = boot_size; |
2038 | il_alloc_fw_desc(il->pci_dev, &il->ucode_boot); | |
4bc85c13 | 2039 | |
46bc8d4b | 2040 | if (!il->ucode_boot.v_addr) |
4bc85c13 WYG |
2041 | goto err_pci_alloc; |
2042 | } | |
2043 | ||
2044 | /* Copy images into buffers for card's bus-master reads ... */ | |
2045 | ||
2046 | /* Runtime instructions (first block of data in file) */ | |
2047 | len = inst_size; | |
58de00a4 | 2048 | D_INFO( |
4bc85c13 | 2049 | "Copying (but not loading) uCode instr len %zd\n", len); |
46bc8d4b | 2050 | memcpy(il->ucode_code.v_addr, src, len); |
4bc85c13 WYG |
2051 | src += len; |
2052 | ||
58de00a4 | 2053 | D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
46bc8d4b | 2054 | il->ucode_code.v_addr, (u32)il->ucode_code.p_addr); |
4bc85c13 WYG |
2055 | |
2056 | /* Runtime data (2nd block) | |
e2ebc833 | 2057 | * NOTE: Copy into backup buffer will be done in il3945_up() */ |
4bc85c13 | 2058 | len = data_size; |
58de00a4 | 2059 | D_INFO( |
4bc85c13 | 2060 | "Copying (but not loading) uCode data len %zd\n", len); |
46bc8d4b SG |
2061 | memcpy(il->ucode_data.v_addr, src, len); |
2062 | memcpy(il->ucode_data_backup.v_addr, src, len); | |
4bc85c13 WYG |
2063 | src += len; |
2064 | ||
2065 | /* Initialization instructions (3rd block) */ | |
2066 | if (init_size) { | |
2067 | len = init_size; | |
58de00a4 | 2068 | D_INFO( |
4bc85c13 | 2069 | "Copying (but not loading) init instr len %zd\n", len); |
46bc8d4b | 2070 | memcpy(il->ucode_init.v_addr, src, len); |
4bc85c13 WYG |
2071 | src += len; |
2072 | } | |
2073 | ||
2074 | /* Initialization data (4th block) */ | |
2075 | if (init_data_size) { | |
2076 | len = init_data_size; | |
58de00a4 | 2077 | D_INFO( |
4bc85c13 | 2078 | "Copying (but not loading) init data len %zd\n", len); |
46bc8d4b | 2079 | memcpy(il->ucode_init_data.v_addr, src, len); |
4bc85c13 WYG |
2080 | src += len; |
2081 | } | |
2082 | ||
2083 | /* Bootstrap instructions (5th block) */ | |
2084 | len = boot_size; | |
58de00a4 | 2085 | D_INFO( |
4bc85c13 | 2086 | "Copying (but not loading) boot instr len %zd\n", len); |
46bc8d4b | 2087 | memcpy(il->ucode_boot.v_addr, src, len); |
4bc85c13 WYG |
2088 | |
2089 | /* We have our copies now, allow OS release its copies */ | |
2090 | release_firmware(ucode_raw); | |
2091 | return 0; | |
2092 | ||
2093 | err_pci_alloc: | |
9406f797 | 2094 | IL_ERR("failed to allocate pci memory\n"); |
4bc85c13 | 2095 | ret = -ENOMEM; |
46bc8d4b | 2096 | il3945_dealloc_ucode_pci(il); |
4bc85c13 WYG |
2097 | |
2098 | err_release: | |
2099 | release_firmware(ucode_raw); | |
2100 | ||
2101 | error: | |
2102 | return ret; | |
2103 | } | |
2104 | ||
2105 | ||
2106 | /** | |
e2ebc833 | 2107 | * il3945_set_ucode_ptrs - Set uCode address location |
4bc85c13 WYG |
2108 | * |
2109 | * Tell initialization uCode where to find runtime uCode. | |
2110 | * | |
2111 | * BSM registers initially contain pointers to initialization uCode. | |
2112 | * We need to replace them to load runtime uCode inst and data, | |
2113 | * and to save runtime data when powering down. | |
2114 | */ | |
46bc8d4b | 2115 | static int il3945_set_ucode_ptrs(struct il_priv *il) |
4bc85c13 WYG |
2116 | { |
2117 | dma_addr_t pinst; | |
2118 | dma_addr_t pdata; | |
2119 | ||
2120 | /* bits 31:0 for 3945 */ | |
46bc8d4b SG |
2121 | pinst = il->ucode_code.p_addr; |
2122 | pdata = il->ucode_data_backup.p_addr; | |
4bc85c13 WYG |
2123 | |
2124 | /* Tell bootstrap uCode where to find image to load */ | |
46bc8d4b SG |
2125 | il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst); |
2126 | il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata); | |
2127 | il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, | |
2128 | il->ucode_data.len); | |
4bc85c13 WYG |
2129 | |
2130 | /* Inst byte count must be last to set up, bit 31 signals uCode | |
2131 | * that all new ptr/size info is in place */ | |
46bc8d4b SG |
2132 | il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, |
2133 | il->ucode_code.len | BSM_DRAM_INST_LOAD); | |
4bc85c13 | 2134 | |
58de00a4 | 2135 | D_INFO("Runtime uCode pointers are set.\n"); |
4bc85c13 WYG |
2136 | |
2137 | return 0; | |
2138 | } | |
2139 | ||
2140 | /** | |
e2ebc833 | 2141 | * il3945_init_alive_start - Called after REPLY_ALIVE notification received |
4bc85c13 WYG |
2142 | * |
2143 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
2144 | * | |
2145 | * Tell "initialize" uCode to go ahead and load the runtime uCode. | |
2146 | */ | |
46bc8d4b | 2147 | static void il3945_init_alive_start(struct il_priv *il) |
4bc85c13 WYG |
2148 | { |
2149 | /* Check alive response for "valid" sign from uCode */ | |
46bc8d4b | 2150 | if (il->card_alive_init.is_valid != UCODE_VALID_OK) { |
4bc85c13 WYG |
2151 | /* We had an error bringing up the hardware, so take it |
2152 | * all the way back down so we can try again */ | |
58de00a4 | 2153 | D_INFO("Initialize Alive failed.\n"); |
4bc85c13 WYG |
2154 | goto restart; |
2155 | } | |
2156 | ||
2157 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
2158 | * This is a paranoid check, because we would not have gotten the | |
2159 | * "initialize" alive if code weren't properly loaded. */ | |
46bc8d4b | 2160 | if (il3945_verify_ucode(il)) { |
4bc85c13 WYG |
2161 | /* Runtime instruction load was bad; |
2162 | * take it all the way back down so we can try again */ | |
58de00a4 | 2163 | D_INFO("Bad \"initialize\" uCode load.\n"); |
4bc85c13 WYG |
2164 | goto restart; |
2165 | } | |
2166 | ||
2167 | /* Send pointers to protocol/runtime uCode image ... init code will | |
2168 | * load and launch runtime uCode, which will send us another "Alive" | |
2169 | * notification. */ | |
58de00a4 | 2170 | D_INFO("Initialization Alive received.\n"); |
46bc8d4b | 2171 | if (il3945_set_ucode_ptrs(il)) { |
4bc85c13 WYG |
2172 | /* Runtime instruction load won't happen; |
2173 | * take it all the way back down so we can try again */ | |
58de00a4 | 2174 | D_INFO("Couldn't set up uCode pointers.\n"); |
4bc85c13 WYG |
2175 | goto restart; |
2176 | } | |
2177 | return; | |
2178 | ||
2179 | restart: | |
46bc8d4b | 2180 | queue_work(il->workqueue, &il->restart); |
4bc85c13 WYG |
2181 | } |
2182 | ||
2183 | /** | |
e2ebc833 | 2184 | * il3945_alive_start - called after REPLY_ALIVE notification received |
4bc85c13 | 2185 | * from protocol/runtime uCode (initialization uCode's |
e2ebc833 | 2186 | * Alive gets handled by il3945_init_alive_start()). |
4bc85c13 | 2187 | */ |
46bc8d4b | 2188 | static void il3945_alive_start(struct il_priv *il) |
4bc85c13 WYG |
2189 | { |
2190 | int thermal_spin = 0; | |
2191 | u32 rfkill; | |
46bc8d4b | 2192 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 | 2193 | |
58de00a4 | 2194 | D_INFO("Runtime Alive received.\n"); |
4bc85c13 | 2195 | |
46bc8d4b | 2196 | if (il->card_alive.is_valid != UCODE_VALID_OK) { |
4bc85c13 WYG |
2197 | /* We had an error bringing up the hardware, so take it |
2198 | * all the way back down so we can try again */ | |
58de00a4 | 2199 | D_INFO("Alive failed.\n"); |
4bc85c13 WYG |
2200 | goto restart; |
2201 | } | |
2202 | ||
2203 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2204 | * This is a paranoid check, because we would not have gotten the | |
2205 | * "runtime" alive if code weren't properly loaded. */ | |
46bc8d4b | 2206 | if (il3945_verify_ucode(il)) { |
4bc85c13 WYG |
2207 | /* Runtime instruction load was bad; |
2208 | * take it all the way back down so we can try again */ | |
58de00a4 | 2209 | D_INFO("Bad runtime uCode load.\n"); |
4bc85c13 WYG |
2210 | goto restart; |
2211 | } | |
2212 | ||
46bc8d4b | 2213 | rfkill = il_read_prph(il, APMG_RFKILL_REG); |
58de00a4 | 2214 | D_INFO("RFKILL status: 0x%x\n", rfkill); |
4bc85c13 WYG |
2215 | |
2216 | if (rfkill & 0x1) { | |
46bc8d4b | 2217 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
4bc85c13 WYG |
2218 | /* if RFKILL is not on, then wait for thermal |
2219 | * sensor in adapter to kick in */ | |
46bc8d4b | 2220 | while (il3945_hw_get_temperature(il) == 0) { |
4bc85c13 WYG |
2221 | thermal_spin++; |
2222 | udelay(10); | |
2223 | } | |
2224 | ||
2225 | if (thermal_spin) | |
58de00a4 | 2226 | D_INFO("Thermal calibration took %dus\n", |
4bc85c13 WYG |
2227 | thermal_spin * 10); |
2228 | } else | |
46bc8d4b | 2229 | set_bit(STATUS_RF_KILL_HW, &il->status); |
4bc85c13 WYG |
2230 | |
2231 | /* After the ALIVE response, we can send commands to 3945 uCode */ | |
46bc8d4b | 2232 | set_bit(STATUS_ALIVE, &il->status); |
4bc85c13 WYG |
2233 | |
2234 | /* Enable watchdog to monitor the driver tx queues */ | |
46bc8d4b | 2235 | il_setup_watchdog(il); |
4bc85c13 | 2236 | |
46bc8d4b | 2237 | if (il_is_rfkill(il)) |
4bc85c13 WYG |
2238 | return; |
2239 | ||
46bc8d4b | 2240 | ieee80211_wake_queues(il->hw); |
4bc85c13 | 2241 | |
46bc8d4b | 2242 | il->active_rate = IL_RATES_MASK_3945; |
4bc85c13 | 2243 | |
46bc8d4b | 2244 | il_power_update_mode(il, true); |
4bc85c13 | 2245 | |
46bc8d4b | 2246 | if (il_is_associated(il, IL_RXON_CTX_BSS)) { |
e2ebc833 SG |
2247 | struct il3945_rxon_cmd *active_rxon = |
2248 | (struct il3945_rxon_cmd *)(&ctx->active); | |
4bc85c13 WYG |
2249 | |
2250 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2251 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
2252 | } else { | |
2253 | /* Initialize our rx_config data */ | |
46bc8d4b | 2254 | il_connection_init_rx_config(il, ctx); |
4bc85c13 WYG |
2255 | } |
2256 | ||
2257 | /* Configure Bluetooth device coexistence support */ | |
46bc8d4b | 2258 | il_send_bt_config(il); |
4bc85c13 | 2259 | |
46bc8d4b | 2260 | set_bit(STATUS_READY, &il->status); |
4bc85c13 WYG |
2261 | |
2262 | /* Configure the adapter for unassociated operation */ | |
46bc8d4b | 2263 | il3945_commit_rxon(il, ctx); |
4bc85c13 | 2264 | |
46bc8d4b | 2265 | il3945_reg_txpower_periodic(il); |
4bc85c13 | 2266 | |
58de00a4 | 2267 | D_INFO("ALIVE processing complete.\n"); |
46bc8d4b | 2268 | wake_up(&il->wait_command_queue); |
4bc85c13 WYG |
2269 | |
2270 | return; | |
2271 | ||
2272 | restart: | |
46bc8d4b | 2273 | queue_work(il->workqueue, &il->restart); |
4bc85c13 WYG |
2274 | } |
2275 | ||
46bc8d4b | 2276 | static void il3945_cancel_deferred_work(struct il_priv *il); |
4bc85c13 | 2277 | |
46bc8d4b | 2278 | static void __il3945_down(struct il_priv *il) |
4bc85c13 WYG |
2279 | { |
2280 | unsigned long flags; | |
2281 | int exit_pending; | |
2282 | ||
58de00a4 | 2283 | D_INFO(DRV_NAME " is going down\n"); |
4bc85c13 | 2284 | |
46bc8d4b | 2285 | il_scan_cancel_timeout(il, 200); |
4bc85c13 | 2286 | |
46bc8d4b | 2287 | exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &il->status); |
4bc85c13 WYG |
2288 | |
2289 | /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set | |
2290 | * to prevent rearm timer */ | |
46bc8d4b | 2291 | del_timer_sync(&il->watchdog); |
4bc85c13 WYG |
2292 | |
2293 | /* Station information will now be cleared in device */ | |
46bc8d4b SG |
2294 | il_clear_ucode_stations(il, NULL); |
2295 | il_dealloc_bcast_stations(il); | |
2296 | il_clear_driver_stations(il); | |
4bc85c13 WYG |
2297 | |
2298 | /* Unblock any waiting calls */ | |
46bc8d4b | 2299 | wake_up_all(&il->wait_command_queue); |
4bc85c13 WYG |
2300 | |
2301 | /* Wipe out the EXIT_PENDING status bit if we are not actually | |
2302 | * exiting the module */ | |
2303 | if (!exit_pending) | |
46bc8d4b | 2304 | clear_bit(STATUS_EXIT_PENDING, &il->status); |
4bc85c13 WYG |
2305 | |
2306 | /* stop and reset the on-board processor */ | |
841b2cca | 2307 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
4bc85c13 WYG |
2308 | |
2309 | /* tell the device to stop sending interrupts */ | |
46bc8d4b SG |
2310 | spin_lock_irqsave(&il->lock, flags); |
2311 | il_disable_interrupts(il); | |
2312 | spin_unlock_irqrestore(&il->lock, flags); | |
2313 | il3945_synchronize_irq(il); | |
4bc85c13 | 2314 | |
46bc8d4b SG |
2315 | if (il->mac80211_registered) |
2316 | ieee80211_stop_queues(il->hw); | |
4bc85c13 | 2317 | |
e2ebc833 | 2318 | /* If we have not previously called il3945_init() then |
4bc85c13 | 2319 | * clear all bits but the RF Kill bits and return */ |
46bc8d4b SG |
2320 | if (!il_is_init(il)) { |
2321 | il->status = test_bit(STATUS_RF_KILL_HW, &il->status) << | |
4bc85c13 | 2322 | STATUS_RF_KILL_HW | |
46bc8d4b | 2323 | test_bit(STATUS_GEO_CONFIGURED, &il->status) << |
4bc85c13 | 2324 | STATUS_GEO_CONFIGURED | |
46bc8d4b | 2325 | test_bit(STATUS_EXIT_PENDING, &il->status) << |
4bc85c13 WYG |
2326 | STATUS_EXIT_PENDING; |
2327 | goto exit; | |
2328 | } | |
2329 | ||
2330 | /* ...otherwise clear out all the status bits but the RF Kill | |
2331 | * bit and continue taking the NIC down. */ | |
46bc8d4b | 2332 | il->status &= test_bit(STATUS_RF_KILL_HW, &il->status) << |
4bc85c13 | 2333 | STATUS_RF_KILL_HW | |
46bc8d4b | 2334 | test_bit(STATUS_GEO_CONFIGURED, &il->status) << |
4bc85c13 | 2335 | STATUS_GEO_CONFIGURED | |
46bc8d4b | 2336 | test_bit(STATUS_FW_ERROR, &il->status) << |
4bc85c13 | 2337 | STATUS_FW_ERROR | |
46bc8d4b | 2338 | test_bit(STATUS_EXIT_PENDING, &il->status) << |
4bc85c13 WYG |
2339 | STATUS_EXIT_PENDING; |
2340 | ||
46bc8d4b SG |
2341 | il3945_hw_txq_ctx_stop(il); |
2342 | il3945_hw_rxq_stop(il); | |
4bc85c13 WYG |
2343 | |
2344 | /* Power-down device's busmaster DMA clocks */ | |
46bc8d4b | 2345 | il_write_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
4bc85c13 WYG |
2346 | udelay(5); |
2347 | ||
2348 | /* Stop the device, and put it in low power state */ | |
46bc8d4b | 2349 | il_apm_stop(il); |
4bc85c13 WYG |
2350 | |
2351 | exit: | |
46bc8d4b | 2352 | memset(&il->card_alive, 0, sizeof(struct il_alive_resp)); |
4bc85c13 | 2353 | |
46bc8d4b SG |
2354 | if (il->beacon_skb) |
2355 | dev_kfree_skb(il->beacon_skb); | |
2356 | il->beacon_skb = NULL; | |
4bc85c13 WYG |
2357 | |
2358 | /* clear out any free frames */ | |
46bc8d4b | 2359 | il3945_clear_free_frames(il); |
4bc85c13 WYG |
2360 | } |
2361 | ||
46bc8d4b | 2362 | static void il3945_down(struct il_priv *il) |
4bc85c13 | 2363 | { |
46bc8d4b SG |
2364 | mutex_lock(&il->mutex); |
2365 | __il3945_down(il); | |
2366 | mutex_unlock(&il->mutex); | |
4bc85c13 | 2367 | |
46bc8d4b | 2368 | il3945_cancel_deferred_work(il); |
4bc85c13 WYG |
2369 | } |
2370 | ||
2371 | #define MAX_HW_RESTARTS 5 | |
2372 | ||
46bc8d4b | 2373 | static int il3945_alloc_bcast_station(struct il_priv *il) |
4bc85c13 | 2374 | { |
46bc8d4b | 2375 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 WYG |
2376 | unsigned long flags; |
2377 | u8 sta_id; | |
2378 | ||
46bc8d4b SG |
2379 | spin_lock_irqsave(&il->sta_lock, flags); |
2380 | sta_id = il_prep_station(il, ctx, | |
d2ddf621 | 2381 | il_bcast_addr, false, NULL); |
e2ebc833 | 2382 | if (sta_id == IL_INVALID_STATION) { |
9406f797 | 2383 | IL_ERR("Unable to prepare broadcast station\n"); |
46bc8d4b | 2384 | spin_unlock_irqrestore(&il->sta_lock, flags); |
4bc85c13 WYG |
2385 | |
2386 | return -EINVAL; | |
2387 | } | |
2388 | ||
46bc8d4b SG |
2389 | il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE; |
2390 | il->stations[sta_id].used |= IL_STA_BCAST; | |
2391 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
4bc85c13 WYG |
2392 | |
2393 | return 0; | |
2394 | } | |
2395 | ||
46bc8d4b | 2396 | static int __il3945_up(struct il_priv *il) |
4bc85c13 WYG |
2397 | { |
2398 | int rc, i; | |
2399 | ||
46bc8d4b | 2400 | rc = il3945_alloc_bcast_station(il); |
4bc85c13 WYG |
2401 | if (rc) |
2402 | return rc; | |
2403 | ||
46bc8d4b | 2404 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) { |
9406f797 | 2405 | IL_WARN("Exit pending; will not bring the NIC up\n"); |
4bc85c13 WYG |
2406 | return -EIO; |
2407 | } | |
2408 | ||
46bc8d4b | 2409 | if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) { |
9406f797 | 2410 | IL_ERR("ucode not available for device bring up\n"); |
4bc85c13 WYG |
2411 | return -EIO; |
2412 | } | |
2413 | ||
2414 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
841b2cca | 2415 | if (_il_rd(il, CSR_GP_CNTRL) & |
4bc85c13 | 2416 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
46bc8d4b | 2417 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
4bc85c13 | 2418 | else { |
46bc8d4b | 2419 | set_bit(STATUS_RF_KILL_HW, &il->status); |
9406f797 | 2420 | IL_WARN("Radio disabled by HW RF Kill switch\n"); |
4bc85c13 WYG |
2421 | return -ENODEV; |
2422 | } | |
2423 | ||
841b2cca | 2424 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
4bc85c13 | 2425 | |
46bc8d4b | 2426 | rc = il3945_hw_nic_init(il); |
4bc85c13 | 2427 | if (rc) { |
9406f797 | 2428 | IL_ERR("Unable to int nic\n"); |
4bc85c13 WYG |
2429 | return rc; |
2430 | } | |
2431 | ||
2432 | /* make sure rfkill handshake bits are cleared */ | |
841b2cca SG |
2433 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2434 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, | |
4bc85c13 WYG |
2435 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2436 | ||
2437 | /* clear (again), then enable host interrupts */ | |
841b2cca | 2438 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
46bc8d4b | 2439 | il_enable_interrupts(il); |
4bc85c13 WYG |
2440 | |
2441 | /* really make sure rfkill handshake bits are cleared */ | |
841b2cca SG |
2442 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2443 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
4bc85c13 WYG |
2444 | |
2445 | /* Copy original ucode data image from disk into backup cache. | |
2446 | * This will be used to initialize the on-board processor's | |
2447 | * data SRAM for a clean start when the runtime program first loads. */ | |
46bc8d4b SG |
2448 | memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr, |
2449 | il->ucode_data.len); | |
4bc85c13 WYG |
2450 | |
2451 | /* We return success when we resume from suspend and rf_kill is on. */ | |
46bc8d4b | 2452 | if (test_bit(STATUS_RF_KILL_HW, &il->status)) |
4bc85c13 WYG |
2453 | return 0; |
2454 | ||
2455 | for (i = 0; i < MAX_HW_RESTARTS; i++) { | |
2456 | ||
2457 | /* load bootstrap state machine, | |
2458 | * load bootstrap program into processor's memory, | |
2459 | * prepare to load the "initialize" uCode */ | |
46bc8d4b | 2460 | rc = il->cfg->ops->lib->load_ucode(il); |
4bc85c13 WYG |
2461 | |
2462 | if (rc) { | |
9406f797 | 2463 | IL_ERR( |
4bc85c13 WYG |
2464 | "Unable to set up bootstrap uCode: %d\n", rc); |
2465 | continue; | |
2466 | } | |
2467 | ||
2468 | /* start card; "initialize" will load runtime ucode */ | |
46bc8d4b | 2469 | il3945_nic_start(il); |
4bc85c13 | 2470 | |
58de00a4 | 2471 | D_INFO(DRV_NAME " is coming up\n"); |
4bc85c13 WYG |
2472 | |
2473 | return 0; | |
2474 | } | |
2475 | ||
46bc8d4b SG |
2476 | set_bit(STATUS_EXIT_PENDING, &il->status); |
2477 | __il3945_down(il); | |
2478 | clear_bit(STATUS_EXIT_PENDING, &il->status); | |
4bc85c13 WYG |
2479 | |
2480 | /* tried to restart and config the device for as long as our | |
2481 | * patience could withstand */ | |
9406f797 | 2482 | IL_ERR("Unable to initialize device after %d attempts.\n", i); |
4bc85c13 WYG |
2483 | return -EIO; |
2484 | } | |
2485 | ||
2486 | ||
2487 | /***************************************************************************** | |
2488 | * | |
2489 | * Workqueue callbacks | |
2490 | * | |
2491 | *****************************************************************************/ | |
2492 | ||
e2ebc833 | 2493 | static void il3945_bg_init_alive_start(struct work_struct *data) |
4bc85c13 | 2494 | { |
46bc8d4b | 2495 | struct il_priv *il = |
e2ebc833 | 2496 | container_of(data, struct il_priv, init_alive_start.work); |
4bc85c13 | 2497 | |
46bc8d4b SG |
2498 | mutex_lock(&il->mutex); |
2499 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) | |
28a6e577 | 2500 | goto out; |
4bc85c13 | 2501 | |
46bc8d4b | 2502 | il3945_init_alive_start(il); |
28a6e577 | 2503 | out: |
46bc8d4b | 2504 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
2505 | } |
2506 | ||
e2ebc833 | 2507 | static void il3945_bg_alive_start(struct work_struct *data) |
4bc85c13 | 2508 | { |
46bc8d4b | 2509 | struct il_priv *il = |
e2ebc833 | 2510 | container_of(data, struct il_priv, alive_start.work); |
4bc85c13 | 2511 | |
46bc8d4b SG |
2512 | mutex_lock(&il->mutex); |
2513 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) | |
28a6e577 | 2514 | goto out; |
4bc85c13 | 2515 | |
46bc8d4b | 2516 | il3945_alive_start(il); |
28a6e577 | 2517 | out: |
46bc8d4b | 2518 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
2519 | } |
2520 | ||
2521 | /* | |
2522 | * 3945 cannot interrupt driver when hardware rf kill switch toggles; | |
2523 | * driver must poll CSR_GP_CNTRL_REG register for change. This register | |
2524 | * *is* readable even when device has been SW_RESET into low power mode | |
2525 | * (e.g. during RF KILL). | |
2526 | */ | |
e2ebc833 | 2527 | static void il3945_rfkill_poll(struct work_struct *data) |
4bc85c13 | 2528 | { |
46bc8d4b | 2529 | struct il_priv *il = |
e2ebc833 | 2530 | container_of(data, struct il_priv, _3945.rfkill_poll.work); |
46bc8d4b | 2531 | bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &il->status); |
841b2cca | 2532 | bool new_rfkill = !(_il_rd(il, CSR_GP_CNTRL) |
4bc85c13 WYG |
2533 | & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); |
2534 | ||
2535 | if (new_rfkill != old_rfkill) { | |
2536 | if (new_rfkill) | |
46bc8d4b | 2537 | set_bit(STATUS_RF_KILL_HW, &il->status); |
4bc85c13 | 2538 | else |
46bc8d4b | 2539 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
4bc85c13 | 2540 | |
46bc8d4b | 2541 | wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill); |
4bc85c13 | 2542 | |
58de00a4 | 2543 | D_RF_KILL("RF_KILL bit toggled to %s.\n", |
4bc85c13 WYG |
2544 | new_rfkill ? "disable radio" : "enable radio"); |
2545 | } | |
2546 | ||
2547 | /* Keep this running, even if radio now enabled. This will be | |
2548 | * cancelled in mac_start() if system decides to start again */ | |
46bc8d4b | 2549 | queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, |
4bc85c13 WYG |
2550 | round_jiffies_relative(2 * HZ)); |
2551 | ||
2552 | } | |
2553 | ||
46bc8d4b | 2554 | int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif) |
4bc85c13 | 2555 | { |
e2ebc833 | 2556 | struct il_host_cmd cmd = { |
4bc85c13 | 2557 | .id = REPLY_SCAN_CMD, |
e2ebc833 | 2558 | .len = sizeof(struct il3945_scan_cmd), |
4bc85c13 WYG |
2559 | .flags = CMD_SIZE_HUGE, |
2560 | }; | |
e2ebc833 | 2561 | struct il3945_scan_cmd *scan; |
4bc85c13 WYG |
2562 | u8 n_probes = 0; |
2563 | enum ieee80211_band band; | |
2564 | bool is_active = false; | |
2565 | int ret; | |
dd6d2a8a | 2566 | u16 len; |
4bc85c13 | 2567 | |
46bc8d4b | 2568 | lockdep_assert_held(&il->mutex); |
4bc85c13 | 2569 | |
46bc8d4b SG |
2570 | if (!il->scan_cmd) { |
2571 | il->scan_cmd = kmalloc(sizeof(struct il3945_scan_cmd) + | |
e2ebc833 | 2572 | IL_MAX_SCAN_SIZE, GFP_KERNEL); |
46bc8d4b | 2573 | if (!il->scan_cmd) { |
58de00a4 | 2574 | D_SCAN("Fail to allocate scan memory\n"); |
4bc85c13 WYG |
2575 | return -ENOMEM; |
2576 | } | |
2577 | } | |
46bc8d4b | 2578 | scan = il->scan_cmd; |
e2ebc833 | 2579 | memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE); |
4bc85c13 | 2580 | |
e2ebc833 SG |
2581 | scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH; |
2582 | scan->quiet_time = IL_ACTIVE_QUIET_TIME; | |
4bc85c13 | 2583 | |
46bc8d4b | 2584 | if (il_is_associated(il, IL_RXON_CTX_BSS)) { |
dd6d2a8a | 2585 | u16 interval; |
4bc85c13 WYG |
2586 | u32 extra; |
2587 | u32 suspend_time = 100; | |
2588 | u32 scan_suspend_time = 100; | |
2589 | ||
58de00a4 | 2590 | D_INFO("Scanning while associated...\n"); |
4bc85c13 | 2591 | |
dd6d2a8a | 2592 | interval = vif->bss_conf.beacon_int; |
4bc85c13 WYG |
2593 | |
2594 | scan->suspend_time = 0; | |
2595 | scan->max_out_time = cpu_to_le32(200 * 1024); | |
2596 | if (!interval) | |
2597 | interval = suspend_time; | |
2598 | /* | |
2599 | * suspend time format: | |
2600 | * 0-19: beacon interval in usec (time before exec.) | |
2601 | * 20-23: 0 | |
2602 | * 24-31: number of beacons (suspend between channels) | |
2603 | */ | |
2604 | ||
2605 | extra = (suspend_time / interval) << 24; | |
2606 | scan_suspend_time = 0xFF0FFFFF & | |
2607 | (extra | ((suspend_time % interval) * 1024)); | |
2608 | ||
2609 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
58de00a4 | 2610 | D_SCAN("suspend_time 0x%X beacon interval %d\n", |
4bc85c13 WYG |
2611 | scan_suspend_time, interval); |
2612 | } | |
2613 | ||
46bc8d4b | 2614 | if (il->scan_request->n_ssids) { |
4bc85c13 | 2615 | int i, p = 0; |
58de00a4 | 2616 | D_SCAN("Kicking off active scan\n"); |
46bc8d4b | 2617 | for (i = 0; i < il->scan_request->n_ssids; i++) { |
4bc85c13 | 2618 | /* always does wildcard anyway */ |
46bc8d4b | 2619 | if (!il->scan_request->ssids[i].ssid_len) |
4bc85c13 WYG |
2620 | continue; |
2621 | scan->direct_scan[p].id = WLAN_EID_SSID; | |
2622 | scan->direct_scan[p].len = | |
46bc8d4b | 2623 | il->scan_request->ssids[i].ssid_len; |
4bc85c13 | 2624 | memcpy(scan->direct_scan[p].ssid, |
46bc8d4b SG |
2625 | il->scan_request->ssids[i].ssid, |
2626 | il->scan_request->ssids[i].ssid_len); | |
4bc85c13 WYG |
2627 | n_probes++; |
2628 | p++; | |
2629 | } | |
2630 | is_active = true; | |
2631 | } else | |
58de00a4 | 2632 | D_SCAN("Kicking off passive scan.\n"); |
4bc85c13 WYG |
2633 | |
2634 | /* We don't build a direct scan probe request; the uCode will do | |
2635 | * that based on the direct_mask added to each channel entry */ | |
2636 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; | |
46bc8d4b | 2637 | scan->tx_cmd.sta_id = il->contexts[IL_RXON_CTX_BSS].bcast_sta_id; |
4bc85c13 WYG |
2638 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
2639 | ||
2640 | /* flags + rate selection */ | |
2641 | ||
46bc8d4b | 2642 | switch (il->scan_band) { |
4bc85c13 WYG |
2643 | case IEEE80211_BAND_2GHZ: |
2644 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; | |
e2ebc833 | 2645 | scan->tx_cmd.rate = IL_RATE_1M_PLCP; |
4bc85c13 WYG |
2646 | band = IEEE80211_BAND_2GHZ; |
2647 | break; | |
2648 | case IEEE80211_BAND_5GHZ: | |
e2ebc833 | 2649 | scan->tx_cmd.rate = IL_RATE_6M_PLCP; |
4bc85c13 WYG |
2650 | band = IEEE80211_BAND_5GHZ; |
2651 | break; | |
2652 | default: | |
9406f797 | 2653 | IL_WARN("Invalid scan band\n"); |
4bc85c13 WYG |
2654 | return -EIO; |
2655 | } | |
2656 | ||
2657 | /* | |
2658 | * If active scaning is requested but a certain channel | |
2659 | * is marked passive, we can do active scanning if we | |
2660 | * detect transmissions. | |
2661 | */ | |
e2ebc833 SG |
2662 | scan->good_CRC_th = is_active ? IL_GOOD_CRC_TH_DEFAULT : |
2663 | IL_GOOD_CRC_TH_DISABLED; | |
4bc85c13 | 2664 | |
46bc8d4b SG |
2665 | len = il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data, |
2666 | vif->addr, il->scan_request->ie, | |
2667 | il->scan_request->ie_len, | |
e2ebc833 | 2668 | IL_MAX_SCAN_SIZE - sizeof(*scan)); |
dd6d2a8a SG |
2669 | scan->tx_cmd.len = cpu_to_le16(len); |
2670 | ||
4bc85c13 | 2671 | /* select Rx antennas */ |
46bc8d4b | 2672 | scan->flags |= il3945_get_antenna_flags(il); |
4bc85c13 | 2673 | |
46bc8d4b | 2674 | scan->channel_count = il3945_get_channels_for_scan(il, band, is_active, n_probes, |
dd6d2a8a | 2675 | (void *)&scan->data[len], vif); |
4bc85c13 | 2676 | if (scan->channel_count == 0) { |
58de00a4 | 2677 | D_SCAN("channel count %d\n", scan->channel_count); |
4bc85c13 WYG |
2678 | return -EIO; |
2679 | } | |
2680 | ||
2681 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + | |
e2ebc833 | 2682 | scan->channel_count * sizeof(struct il3945_scan_channel); |
4bc85c13 WYG |
2683 | cmd.data = scan; |
2684 | scan->len = cpu_to_le16(cmd.len); | |
2685 | ||
46bc8d4b SG |
2686 | set_bit(STATUS_SCAN_HW, &il->status); |
2687 | ret = il_send_cmd_sync(il, &cmd); | |
4bc85c13 | 2688 | if (ret) |
46bc8d4b | 2689 | clear_bit(STATUS_SCAN_HW, &il->status); |
4bc85c13 WYG |
2690 | return ret; |
2691 | } | |
2692 | ||
46bc8d4b | 2693 | void il3945_post_scan(struct il_priv *il) |
4bc85c13 | 2694 | { |
46bc8d4b | 2695 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 WYG |
2696 | |
2697 | /* | |
2698 | * Since setting the RXON may have been deferred while | |
2699 | * performing the scan, fire one off if needed | |
2700 | */ | |
2701 | if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging))) | |
46bc8d4b | 2702 | il3945_commit_rxon(il, ctx); |
4bc85c13 WYG |
2703 | } |
2704 | ||
e2ebc833 | 2705 | static void il3945_bg_restart(struct work_struct *data) |
4bc85c13 | 2706 | { |
46bc8d4b | 2707 | struct il_priv *il = container_of(data, struct il_priv, restart); |
4bc85c13 | 2708 | |
46bc8d4b | 2709 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) |
4bc85c13 WYG |
2710 | return; |
2711 | ||
46bc8d4b | 2712 | if (test_and_clear_bit(STATUS_FW_ERROR, &il->status)) { |
e2ebc833 | 2713 | struct il_rxon_context *ctx; |
46bc8d4b SG |
2714 | mutex_lock(&il->mutex); |
2715 | for_each_context(il, ctx) | |
4bc85c13 | 2716 | ctx->vif = NULL; |
46bc8d4b SG |
2717 | il->is_open = 0; |
2718 | mutex_unlock(&il->mutex); | |
2719 | il3945_down(il); | |
2720 | ieee80211_restart_hw(il->hw); | |
4bc85c13 | 2721 | } else { |
46bc8d4b | 2722 | il3945_down(il); |
4bc85c13 | 2723 | |
46bc8d4b SG |
2724 | mutex_lock(&il->mutex); |
2725 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) { | |
2726 | mutex_unlock(&il->mutex); | |
4bc85c13 | 2727 | return; |
28a6e577 | 2728 | } |
4bc85c13 | 2729 | |
46bc8d4b SG |
2730 | __il3945_up(il); |
2731 | mutex_unlock(&il->mutex); | |
4bc85c13 WYG |
2732 | } |
2733 | } | |
2734 | ||
e2ebc833 | 2735 | static void il3945_bg_rx_replenish(struct work_struct *data) |
4bc85c13 | 2736 | { |
46bc8d4b | 2737 | struct il_priv *il = |
e2ebc833 | 2738 | container_of(data, struct il_priv, rx_replenish); |
4bc85c13 | 2739 | |
46bc8d4b SG |
2740 | mutex_lock(&il->mutex); |
2741 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) | |
28a6e577 | 2742 | goto out; |
4bc85c13 | 2743 | |
46bc8d4b | 2744 | il3945_rx_replenish(il); |
28a6e577 | 2745 | out: |
46bc8d4b | 2746 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
2747 | } |
2748 | ||
46bc8d4b | 2749 | void il3945_post_associate(struct il_priv *il) |
4bc85c13 WYG |
2750 | { |
2751 | int rc = 0; | |
2752 | struct ieee80211_conf *conf = NULL; | |
46bc8d4b | 2753 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 | 2754 | |
46bc8d4b | 2755 | if (!ctx->vif || !il->is_open) |
4bc85c13 WYG |
2756 | return; |
2757 | ||
58de00a4 | 2758 | D_ASSOC("Associated as %d to: %pM\n", |
4bc85c13 WYG |
2759 | ctx->vif->bss_conf.aid, ctx->active.bssid_addr); |
2760 | ||
46bc8d4b | 2761 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) |
4bc85c13 WYG |
2762 | return; |
2763 | ||
46bc8d4b | 2764 | il_scan_cancel_timeout(il, 200); |
4bc85c13 | 2765 | |
46bc8d4b | 2766 | conf = il_ieee80211_get_hw_conf(il->hw); |
4bc85c13 WYG |
2767 | |
2768 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
46bc8d4b | 2769 | il3945_commit_rxon(il, ctx); |
4bc85c13 | 2770 | |
46bc8d4b | 2771 | rc = il_send_rxon_timing(il, ctx); |
4bc85c13 | 2772 | if (rc) |
9406f797 | 2773 | IL_WARN("REPLY_RXON_TIMING failed - " |
4bc85c13 WYG |
2774 | "Attempting to continue.\n"); |
2775 | ||
2776 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2777 | ||
2778 | ctx->staging.assoc_id = cpu_to_le16(ctx->vif->bss_conf.aid); | |
2779 | ||
58de00a4 | 2780 | D_ASSOC("assoc id %d beacon interval %d\n", |
4bc85c13 WYG |
2781 | ctx->vif->bss_conf.aid, ctx->vif->bss_conf.beacon_int); |
2782 | ||
2783 | if (ctx->vif->bss_conf.use_short_preamble) | |
2784 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2785 | else | |
2786 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2787 | ||
2788 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) { | |
2789 | if (ctx->vif->bss_conf.use_short_slot) | |
2790 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2791 | else | |
2792 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2793 | } | |
2794 | ||
46bc8d4b | 2795 | il3945_commit_rxon(il, ctx); |
4bc85c13 WYG |
2796 | |
2797 | switch (ctx->vif->type) { | |
2798 | case NL80211_IFTYPE_STATION: | |
46bc8d4b | 2799 | il3945_rate_scale_init(il->hw, IL_AP_ID); |
4bc85c13 WYG |
2800 | break; |
2801 | case NL80211_IFTYPE_ADHOC: | |
46bc8d4b | 2802 | il3945_send_beacon_cmd(il); |
4bc85c13 WYG |
2803 | break; |
2804 | default: | |
9406f797 | 2805 | IL_ERR("%s Should not be called in %d mode\n", |
4bc85c13 WYG |
2806 | __func__, ctx->vif->type); |
2807 | break; | |
2808 | } | |
2809 | } | |
2810 | ||
2811 | /***************************************************************************** | |
2812 | * | |
2813 | * mac80211 entry point functions | |
2814 | * | |
2815 | *****************************************************************************/ | |
2816 | ||
2817 | #define UCODE_READY_TIMEOUT (2 * HZ) | |
2818 | ||
e2ebc833 | 2819 | static int il3945_mac_start(struct ieee80211_hw *hw) |
4bc85c13 | 2820 | { |
46bc8d4b | 2821 | struct il_priv *il = hw->priv; |
4bc85c13 WYG |
2822 | int ret; |
2823 | ||
58de00a4 | 2824 | D_MAC80211("enter\n"); |
4bc85c13 WYG |
2825 | |
2826 | /* we should be verifying the device is ready to be opened */ | |
46bc8d4b | 2827 | mutex_lock(&il->mutex); |
4bc85c13 WYG |
2828 | |
2829 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... | |
2830 | * ucode filename and max sizes are card-specific. */ | |
2831 | ||
46bc8d4b SG |
2832 | if (!il->ucode_code.len) { |
2833 | ret = il3945_read_ucode(il); | |
4bc85c13 | 2834 | if (ret) { |
9406f797 | 2835 | IL_ERR("Could not read microcode: %d\n", ret); |
46bc8d4b | 2836 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
2837 | goto out_release_irq; |
2838 | } | |
2839 | } | |
2840 | ||
46bc8d4b | 2841 | ret = __il3945_up(il); |
4bc85c13 | 2842 | |
46bc8d4b | 2843 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
2844 | |
2845 | if (ret) | |
2846 | goto out_release_irq; | |
2847 | ||
58de00a4 | 2848 | D_INFO("Start UP work.\n"); |
4bc85c13 WYG |
2849 | |
2850 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from | |
2851 | * mac80211 will not be run successfully. */ | |
46bc8d4b SG |
2852 | ret = wait_event_timeout(il->wait_command_queue, |
2853 | test_bit(STATUS_READY, &il->status), | |
4bc85c13 WYG |
2854 | UCODE_READY_TIMEOUT); |
2855 | if (!ret) { | |
46bc8d4b | 2856 | if (!test_bit(STATUS_READY, &il->status)) { |
9406f797 | 2857 | IL_ERR( |
4bc85c13 WYG |
2858 | "Wait for START_ALIVE timeout after %dms.\n", |
2859 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
2860 | ret = -ETIMEDOUT; | |
2861 | goto out_release_irq; | |
2862 | } | |
2863 | } | |
2864 | ||
2865 | /* ucode is running and will send rfkill notifications, | |
2866 | * no need to poll the killswitch state anymore */ | |
46bc8d4b | 2867 | cancel_delayed_work(&il->_3945.rfkill_poll); |
4bc85c13 | 2868 | |
46bc8d4b | 2869 | il->is_open = 1; |
58de00a4 | 2870 | D_MAC80211("leave\n"); |
4bc85c13 WYG |
2871 | return 0; |
2872 | ||
2873 | out_release_irq: | |
46bc8d4b | 2874 | il->is_open = 0; |
58de00a4 | 2875 | D_MAC80211("leave - failed\n"); |
4bc85c13 WYG |
2876 | return ret; |
2877 | } | |
2878 | ||
e2ebc833 | 2879 | static void il3945_mac_stop(struct ieee80211_hw *hw) |
4bc85c13 | 2880 | { |
46bc8d4b | 2881 | struct il_priv *il = hw->priv; |
4bc85c13 | 2882 | |
58de00a4 | 2883 | D_MAC80211("enter\n"); |
4bc85c13 | 2884 | |
46bc8d4b | 2885 | if (!il->is_open) { |
58de00a4 | 2886 | D_MAC80211("leave - skip\n"); |
4bc85c13 WYG |
2887 | return; |
2888 | } | |
2889 | ||
46bc8d4b | 2890 | il->is_open = 0; |
4bc85c13 | 2891 | |
46bc8d4b | 2892 | il3945_down(il); |
4bc85c13 | 2893 | |
46bc8d4b | 2894 | flush_workqueue(il->workqueue); |
4bc85c13 WYG |
2895 | |
2896 | /* start polling the killswitch state again */ | |
46bc8d4b | 2897 | queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, |
4bc85c13 WYG |
2898 | round_jiffies_relative(2 * HZ)); |
2899 | ||
58de00a4 | 2900 | D_MAC80211("leave\n"); |
4bc85c13 WYG |
2901 | } |
2902 | ||
e2ebc833 | 2903 | static void il3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
4bc85c13 | 2904 | { |
46bc8d4b | 2905 | struct il_priv *il = hw->priv; |
4bc85c13 | 2906 | |
58de00a4 | 2907 | D_MAC80211("enter\n"); |
4bc85c13 | 2908 | |
58de00a4 | 2909 | D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
4bc85c13 WYG |
2910 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
2911 | ||
46bc8d4b | 2912 | if (il3945_tx_skb(il, skb)) |
4bc85c13 WYG |
2913 | dev_kfree_skb_any(skb); |
2914 | ||
58de00a4 | 2915 | D_MAC80211("leave\n"); |
4bc85c13 WYG |
2916 | } |
2917 | ||
46bc8d4b | 2918 | void il3945_config_ap(struct il_priv *il) |
4bc85c13 | 2919 | { |
46bc8d4b | 2920 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 WYG |
2921 | struct ieee80211_vif *vif = ctx->vif; |
2922 | int rc = 0; | |
2923 | ||
46bc8d4b | 2924 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) |
4bc85c13 WYG |
2925 | return; |
2926 | ||
2927 | /* The following should be done only at AP bring up */ | |
46bc8d4b | 2928 | if (!(il_is_associated(il, IL_RXON_CTX_BSS))) { |
4bc85c13 WYG |
2929 | |
2930 | /* RXON - unassoc (to set timing command) */ | |
2931 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
46bc8d4b | 2932 | il3945_commit_rxon(il, ctx); |
4bc85c13 WYG |
2933 | |
2934 | /* RXON Timing */ | |
46bc8d4b | 2935 | rc = il_send_rxon_timing(il, ctx); |
4bc85c13 | 2936 | if (rc) |
9406f797 | 2937 | IL_WARN("REPLY_RXON_TIMING failed - " |
4bc85c13 WYG |
2938 | "Attempting to continue.\n"); |
2939 | ||
2940 | ctx->staging.assoc_id = 0; | |
2941 | ||
2942 | if (vif->bss_conf.use_short_preamble) | |
2943 | ctx->staging.flags |= | |
2944 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2945 | else | |
2946 | ctx->staging.flags &= | |
2947 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2948 | ||
2949 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) { | |
2950 | if (vif->bss_conf.use_short_slot) | |
2951 | ctx->staging.flags |= | |
2952 | RXON_FLG_SHORT_SLOT_MSK; | |
2953 | else | |
2954 | ctx->staging.flags &= | |
2955 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2956 | } | |
2957 | /* restore RXON assoc */ | |
2958 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
46bc8d4b | 2959 | il3945_commit_rxon(il, ctx); |
4bc85c13 | 2960 | } |
46bc8d4b | 2961 | il3945_send_beacon_cmd(il); |
4bc85c13 WYG |
2962 | } |
2963 | ||
e2ebc833 | 2964 | static int il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
4bc85c13 WYG |
2965 | struct ieee80211_vif *vif, |
2966 | struct ieee80211_sta *sta, | |
2967 | struct ieee80211_key_conf *key) | |
2968 | { | |
46bc8d4b | 2969 | struct il_priv *il = hw->priv; |
4bc85c13 | 2970 | int ret = 0; |
e2ebc833 | 2971 | u8 sta_id = IL_INVALID_STATION; |
4bc85c13 WYG |
2972 | u8 static_key; |
2973 | ||
58de00a4 | 2974 | D_MAC80211("enter\n"); |
4bc85c13 | 2975 | |
e2ebc833 | 2976 | if (il3945_mod_params.sw_crypto) { |
58de00a4 | 2977 | D_MAC80211("leave - hwcrypto disabled\n"); |
4bc85c13 WYG |
2978 | return -EOPNOTSUPP; |
2979 | } | |
2980 | ||
2981 | /* | |
2982 | * To support IBSS RSN, don't program group keys in IBSS, the | |
2983 | * hardware will then not attempt to decrypt the frames. | |
2984 | */ | |
2985 | if (vif->type == NL80211_IFTYPE_ADHOC && | |
2986 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) | |
2987 | return -EOPNOTSUPP; | |
2988 | ||
46bc8d4b | 2989 | static_key = !il_is_associated(il, IL_RXON_CTX_BSS); |
4bc85c13 WYG |
2990 | |
2991 | if (!static_key) { | |
e2ebc833 | 2992 | sta_id = il_sta_id_or_broadcast( |
46bc8d4b | 2993 | il, &il->contexts[IL_RXON_CTX_BSS], sta); |
e2ebc833 | 2994 | if (sta_id == IL_INVALID_STATION) |
4bc85c13 WYG |
2995 | return -EINVAL; |
2996 | } | |
2997 | ||
46bc8d4b SG |
2998 | mutex_lock(&il->mutex); |
2999 | il_scan_cancel_timeout(il, 100); | |
4bc85c13 WYG |
3000 | |
3001 | switch (cmd) { | |
3002 | case SET_KEY: | |
3003 | if (static_key) | |
46bc8d4b | 3004 | ret = il3945_set_static_key(il, key); |
4bc85c13 | 3005 | else |
46bc8d4b | 3006 | ret = il3945_set_dynamic_key(il, key, sta_id); |
58de00a4 | 3007 | D_MAC80211("enable hwcrypto key\n"); |
4bc85c13 WYG |
3008 | break; |
3009 | case DISABLE_KEY: | |
3010 | if (static_key) | |
46bc8d4b | 3011 | ret = il3945_remove_static_key(il); |
4bc85c13 | 3012 | else |
46bc8d4b | 3013 | ret = il3945_clear_sta_key_info(il, sta_id); |
58de00a4 | 3014 | D_MAC80211("disable hwcrypto key\n"); |
4bc85c13 WYG |
3015 | break; |
3016 | default: | |
3017 | ret = -EINVAL; | |
3018 | } | |
3019 | ||
46bc8d4b | 3020 | mutex_unlock(&il->mutex); |
58de00a4 | 3021 | D_MAC80211("leave\n"); |
4bc85c13 WYG |
3022 | |
3023 | return ret; | |
3024 | } | |
3025 | ||
e2ebc833 | 3026 | static int il3945_mac_sta_add(struct ieee80211_hw *hw, |
4bc85c13 WYG |
3027 | struct ieee80211_vif *vif, |
3028 | struct ieee80211_sta *sta) | |
3029 | { | |
46bc8d4b | 3030 | struct il_priv *il = hw->priv; |
e2ebc833 | 3031 | struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv; |
4bc85c13 WYG |
3032 | int ret; |
3033 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; | |
3034 | u8 sta_id; | |
3035 | ||
58de00a4 | 3036 | D_INFO("received request to add station %pM\n", |
4bc85c13 | 3037 | sta->addr); |
46bc8d4b | 3038 | mutex_lock(&il->mutex); |
58de00a4 | 3039 | D_INFO("proceeding to add station %pM\n", |
4bc85c13 | 3040 | sta->addr); |
e2ebc833 | 3041 | sta_priv->common.sta_id = IL_INVALID_STATION; |
4bc85c13 WYG |
3042 | |
3043 | ||
46bc8d4b SG |
3044 | ret = il_add_station_common(il, |
3045 | &il->contexts[IL_RXON_CTX_BSS], | |
4bc85c13 WYG |
3046 | sta->addr, is_ap, sta, &sta_id); |
3047 | if (ret) { | |
9406f797 | 3048 | IL_ERR("Unable to add station %pM (%d)\n", |
4bc85c13 WYG |
3049 | sta->addr, ret); |
3050 | /* Should we return success if return code is EEXIST ? */ | |
46bc8d4b | 3051 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
3052 | return ret; |
3053 | } | |
3054 | ||
3055 | sta_priv->common.sta_id = sta_id; | |
3056 | ||
3057 | /* Initialize rate scaling */ | |
58de00a4 | 3058 | D_INFO("Initializing rate scaling for station %pM\n", |
4bc85c13 | 3059 | sta->addr); |
46bc8d4b SG |
3060 | il3945_rs_rate_init(il, sta, sta_id); |
3061 | mutex_unlock(&il->mutex); | |
4bc85c13 WYG |
3062 | |
3063 | return 0; | |
3064 | } | |
3065 | ||
e2ebc833 | 3066 | static void il3945_configure_filter(struct ieee80211_hw *hw, |
4bc85c13 WYG |
3067 | unsigned int changed_flags, |
3068 | unsigned int *total_flags, | |
3069 | u64 multicast) | |
3070 | { | |
46bc8d4b | 3071 | struct il_priv *il = hw->priv; |
4bc85c13 | 3072 | __le32 filter_or = 0, filter_nand = 0; |
46bc8d4b | 3073 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 WYG |
3074 | |
3075 | #define CHK(test, flag) do { \ | |
3076 | if (*total_flags & (test)) \ | |
3077 | filter_or |= (flag); \ | |
3078 | else \ | |
3079 | filter_nand |= (flag); \ | |
3080 | } while (0) | |
3081 | ||
58de00a4 | 3082 | D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", |
4bc85c13 WYG |
3083 | changed_flags, *total_flags); |
3084 | ||
3085 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
3086 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK); | |
3087 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); | |
3088 | ||
3089 | #undef CHK | |
3090 | ||
46bc8d4b | 3091 | mutex_lock(&il->mutex); |
4bc85c13 WYG |
3092 | |
3093 | ctx->staging.filter_flags &= ~filter_nand; | |
3094 | ctx->staging.filter_flags |= filter_or; | |
3095 | ||
3096 | /* | |
3097 | * Not committing directly because hardware can perform a scan, | |
3098 | * but even if hw is ready, committing here breaks for some reason, | |
3099 | * we'll eventually commit the filter flags change anyway. | |
3100 | */ | |
3101 | ||
46bc8d4b | 3102 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
3103 | |
3104 | /* | |
3105 | * Receiving all multicast frames is always enabled by the | |
e2ebc833 | 3106 | * default flags setup in il_connection_init_rx_config() |
4bc85c13 WYG |
3107 | * since we currently do not support programming multicast |
3108 | * filters into the device. | |
3109 | */ | |
3110 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
3111 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
3112 | } | |
3113 | ||
3114 | ||
3115 | /***************************************************************************** | |
3116 | * | |
3117 | * sysfs attributes | |
3118 | * | |
3119 | *****************************************************************************/ | |
3120 | ||
be663ab6 | 3121 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
4bc85c13 WYG |
3122 | |
3123 | /* | |
3124 | * The following adds a new attribute to the sysfs representation | |
3125 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
3126 | * used for controlling the debug level. | |
3127 | * | |
3128 | * See the level definitions in iwl for details. | |
3129 | * | |
3130 | * The debug_level being managed using sysfs below is a per device debug | |
3131 | * level that is used instead of the global debug level if it (the per | |
3132 | * device debug level) is set. | |
3133 | */ | |
e2ebc833 | 3134 | static ssize_t il3945_show_debug_level(struct device *d, |
4bc85c13 WYG |
3135 | struct device_attribute *attr, char *buf) |
3136 | { | |
46bc8d4b SG |
3137 | struct il_priv *il = dev_get_drvdata(d); |
3138 | return sprintf(buf, "0x%08X\n", il_get_debug_level(il)); | |
4bc85c13 | 3139 | } |
e2ebc833 | 3140 | static ssize_t il3945_store_debug_level(struct device *d, |
4bc85c13 WYG |
3141 | struct device_attribute *attr, |
3142 | const char *buf, size_t count) | |
3143 | { | |
46bc8d4b | 3144 | struct il_priv *il = dev_get_drvdata(d); |
4bc85c13 WYG |
3145 | unsigned long val; |
3146 | int ret; | |
3147 | ||
3148 | ret = strict_strtoul(buf, 0, &val); | |
3149 | if (ret) | |
9406f797 | 3150 | IL_INFO("%s is not in hex or decimal form.\n", buf); |
4bc85c13 | 3151 | else { |
46bc8d4b SG |
3152 | il->debug_level = val; |
3153 | if (il_alloc_traffic_mem(il)) | |
9406f797 | 3154 | IL_ERR( |
4bc85c13 WYG |
3155 | "Not enough memory to generate traffic log\n"); |
3156 | } | |
3157 | return strnlen(buf, count); | |
3158 | } | |
3159 | ||
3160 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
e2ebc833 | 3161 | il3945_show_debug_level, il3945_store_debug_level); |
4bc85c13 | 3162 | |
be663ab6 | 3163 | #endif /* CONFIG_IWLWIFI_LEGACY_DEBUG */ |
4bc85c13 | 3164 | |
e2ebc833 | 3165 | static ssize_t il3945_show_temperature(struct device *d, |
4bc85c13 WYG |
3166 | struct device_attribute *attr, char *buf) |
3167 | { | |
46bc8d4b | 3168 | struct il_priv *il = dev_get_drvdata(d); |
4bc85c13 | 3169 | |
46bc8d4b | 3170 | if (!il_is_alive(il)) |
4bc85c13 WYG |
3171 | return -EAGAIN; |
3172 | ||
46bc8d4b | 3173 | return sprintf(buf, "%d\n", il3945_hw_get_temperature(il)); |
4bc85c13 WYG |
3174 | } |
3175 | ||
e2ebc833 | 3176 | static DEVICE_ATTR(temperature, S_IRUGO, il3945_show_temperature, NULL); |
4bc85c13 | 3177 | |
e2ebc833 | 3178 | static ssize_t il3945_show_tx_power(struct device *d, |
4bc85c13 WYG |
3179 | struct device_attribute *attr, char *buf) |
3180 | { | |
46bc8d4b SG |
3181 | struct il_priv *il = dev_get_drvdata(d); |
3182 | return sprintf(buf, "%d\n", il->tx_power_user_lmt); | |
4bc85c13 WYG |
3183 | } |
3184 | ||
e2ebc833 | 3185 | static ssize_t il3945_store_tx_power(struct device *d, |
4bc85c13 WYG |
3186 | struct device_attribute *attr, |
3187 | const char *buf, size_t count) | |
3188 | { | |
46bc8d4b | 3189 | struct il_priv *il = dev_get_drvdata(d); |
4bc85c13 WYG |
3190 | char *p = (char *)buf; |
3191 | u32 val; | |
3192 | ||
3193 | val = simple_strtoul(p, &p, 10); | |
3194 | if (p == buf) | |
9406f797 | 3195 | IL_INFO(": %s is not in decimal form.\n", buf); |
4bc85c13 | 3196 | else |
46bc8d4b | 3197 | il3945_hw_reg_set_txpower(il, val); |
4bc85c13 WYG |
3198 | |
3199 | return count; | |
3200 | } | |
3201 | ||
e2ebc833 | 3202 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il3945_show_tx_power, il3945_store_tx_power); |
4bc85c13 | 3203 | |
e2ebc833 | 3204 | static ssize_t il3945_show_flags(struct device *d, |
4bc85c13 WYG |
3205 | struct device_attribute *attr, char *buf) |
3206 | { | |
46bc8d4b SG |
3207 | struct il_priv *il = dev_get_drvdata(d); |
3208 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; | |
4bc85c13 WYG |
3209 | |
3210 | return sprintf(buf, "0x%04X\n", ctx->active.flags); | |
3211 | } | |
3212 | ||
e2ebc833 | 3213 | static ssize_t il3945_store_flags(struct device *d, |
4bc85c13 WYG |
3214 | struct device_attribute *attr, |
3215 | const char *buf, size_t count) | |
3216 | { | |
46bc8d4b | 3217 | struct il_priv *il = dev_get_drvdata(d); |
4bc85c13 | 3218 | u32 flags = simple_strtoul(buf, NULL, 0); |
46bc8d4b | 3219 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; |
4bc85c13 | 3220 | |
46bc8d4b | 3221 | mutex_lock(&il->mutex); |
4bc85c13 WYG |
3222 | if (le32_to_cpu(ctx->staging.flags) != flags) { |
3223 | /* Cancel any currently running scans... */ | |
46bc8d4b | 3224 | if (il_scan_cancel_timeout(il, 100)) |
9406f797 | 3225 | IL_WARN("Could not cancel scan.\n"); |
4bc85c13 | 3226 | else { |
58de00a4 | 3227 | D_INFO("Committing rxon.flags = 0x%04X\n", |
4bc85c13 WYG |
3228 | flags); |
3229 | ctx->staging.flags = cpu_to_le32(flags); | |
46bc8d4b | 3230 | il3945_commit_rxon(il, ctx); |
4bc85c13 WYG |
3231 | } |
3232 | } | |
46bc8d4b | 3233 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
3234 | |
3235 | return count; | |
3236 | } | |
3237 | ||
e2ebc833 | 3238 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, il3945_show_flags, il3945_store_flags); |
4bc85c13 | 3239 | |
e2ebc833 | 3240 | static ssize_t il3945_show_filter_flags(struct device *d, |
4bc85c13 WYG |
3241 | struct device_attribute *attr, char *buf) |
3242 | { | |
46bc8d4b SG |
3243 | struct il_priv *il = dev_get_drvdata(d); |
3244 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; | |
4bc85c13 WYG |
3245 | |
3246 | return sprintf(buf, "0x%04X\n", | |
3247 | le32_to_cpu(ctx->active.filter_flags)); | |
3248 | } | |
3249 | ||
e2ebc833 | 3250 | static ssize_t il3945_store_filter_flags(struct device *d, |
4bc85c13 WYG |
3251 | struct device_attribute *attr, |
3252 | const char *buf, size_t count) | |
3253 | { | |
46bc8d4b SG |
3254 | struct il_priv *il = dev_get_drvdata(d); |
3255 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; | |
4bc85c13 WYG |
3256 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
3257 | ||
46bc8d4b | 3258 | mutex_lock(&il->mutex); |
4bc85c13 WYG |
3259 | if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) { |
3260 | /* Cancel any currently running scans... */ | |
46bc8d4b | 3261 | if (il_scan_cancel_timeout(il, 100)) |
9406f797 | 3262 | IL_WARN("Could not cancel scan.\n"); |
4bc85c13 | 3263 | else { |
58de00a4 | 3264 | D_INFO("Committing rxon.filter_flags = " |
4bc85c13 WYG |
3265 | "0x%04X\n", filter_flags); |
3266 | ctx->staging.filter_flags = | |
3267 | cpu_to_le32(filter_flags); | |
46bc8d4b | 3268 | il3945_commit_rxon(il, ctx); |
4bc85c13 WYG |
3269 | } |
3270 | } | |
46bc8d4b | 3271 | mutex_unlock(&il->mutex); |
4bc85c13 WYG |
3272 | |
3273 | return count; | |
3274 | } | |
3275 | ||
e2ebc833 SG |
3276 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, il3945_show_filter_flags, |
3277 | il3945_store_filter_flags); | |
4bc85c13 | 3278 | |
e2ebc833 | 3279 | static ssize_t il3945_show_measurement(struct device *d, |
4bc85c13 WYG |
3280 | struct device_attribute *attr, char *buf) |
3281 | { | |
46bc8d4b | 3282 | struct il_priv *il = dev_get_drvdata(d); |
e2ebc833 | 3283 | struct il_spectrum_notification measure_report; |
4bc85c13 WYG |
3284 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3285 | u8 *data = (u8 *)&measure_report; | |
3286 | unsigned long flags; | |
3287 | ||
46bc8d4b SG |
3288 | spin_lock_irqsave(&il->lock, flags); |
3289 | if (!(il->measurement_status & MEASUREMENT_READY)) { | |
3290 | spin_unlock_irqrestore(&il->lock, flags); | |
4bc85c13 WYG |
3291 | return 0; |
3292 | } | |
46bc8d4b SG |
3293 | memcpy(&measure_report, &il->measure_report, size); |
3294 | il->measurement_status = 0; | |
3295 | spin_unlock_irqrestore(&il->lock, flags); | |
4bc85c13 WYG |
3296 | |
3297 | while (size && (PAGE_SIZE - len)) { | |
3298 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3299 | PAGE_SIZE - len, 1); | |
3300 | len = strlen(buf); | |
3301 | if (PAGE_SIZE - len) | |
3302 | buf[len++] = '\n'; | |
3303 | ||
3304 | ofs += 16; | |
3305 | size -= min(size, 16U); | |
3306 | } | |
3307 | ||
3308 | return len; | |
3309 | } | |
3310 | ||
e2ebc833 | 3311 | static ssize_t il3945_store_measurement(struct device *d, |
4bc85c13 WYG |
3312 | struct device_attribute *attr, |
3313 | const char *buf, size_t count) | |
3314 | { | |
46bc8d4b SG |
3315 | struct il_priv *il = dev_get_drvdata(d); |
3316 | struct il_rxon_context *ctx = &il->contexts[IL_RXON_CTX_BSS]; | |
4bc85c13 WYG |
3317 | struct ieee80211_measurement_params params = { |
3318 | .channel = le16_to_cpu(ctx->active.channel), | |
46bc8d4b | 3319 | .start_time = cpu_to_le64(il->_3945.last_tsf), |
4bc85c13 WYG |
3320 | .duration = cpu_to_le16(1), |
3321 | }; | |
e2ebc833 | 3322 | u8 type = IL_MEASURE_BASIC; |
4bc85c13 WYG |
3323 | u8 buffer[32]; |
3324 | u8 channel; | |
3325 | ||
3326 | if (count) { | |
3327 | char *p = buffer; | |
3328 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
3329 | channel = simple_strtoul(p, NULL, 0); | |
3330 | if (channel) | |
3331 | params.channel = channel; | |
3332 | ||
3333 | p = buffer; | |
3334 | while (*p && *p != ' ') | |
3335 | p++; | |
3336 | if (*p) | |
3337 | type = simple_strtoul(p + 1, NULL, 0); | |
3338 | } | |
3339 | ||
58de00a4 | 3340 | D_INFO("Invoking measurement of type %d on " |
4bc85c13 | 3341 | "channel %d (for '%s')\n", type, params.channel, buf); |
46bc8d4b | 3342 | il3945_get_measurement(il, ¶ms, type); |
4bc85c13 WYG |
3343 | |
3344 | return count; | |
3345 | } | |
3346 | ||
3347 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
e2ebc833 | 3348 | il3945_show_measurement, il3945_store_measurement); |
4bc85c13 | 3349 | |
e2ebc833 | 3350 | static ssize_t il3945_store_retry_rate(struct device *d, |
4bc85c13 WYG |
3351 | struct device_attribute *attr, |
3352 | const char *buf, size_t count) | |
3353 | { | |
46bc8d4b | 3354 | struct il_priv *il = dev_get_drvdata(d); |
4bc85c13 | 3355 | |
46bc8d4b SG |
3356 | il->retry_rate = simple_strtoul(buf, NULL, 0); |
3357 | if (il->retry_rate <= 0) | |
3358 | il->retry_rate = 1; | |
4bc85c13 WYG |
3359 | |
3360 | return count; | |
3361 | } | |
3362 | ||
e2ebc833 | 3363 | static ssize_t il3945_show_retry_rate(struct device *d, |
4bc85c13 WYG |
3364 | struct device_attribute *attr, char *buf) |
3365 | { | |
46bc8d4b SG |
3366 | struct il_priv *il = dev_get_drvdata(d); |
3367 | return sprintf(buf, "%d", il->retry_rate); | |
4bc85c13 WYG |
3368 | } |
3369 | ||
e2ebc833 SG |
3370 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, il3945_show_retry_rate, |
3371 | il3945_store_retry_rate); | |
4bc85c13 WYG |
3372 | |
3373 | ||
e2ebc833 | 3374 | static ssize_t il3945_show_channels(struct device *d, |
4bc85c13 WYG |
3375 | struct device_attribute *attr, char *buf) |
3376 | { | |
3377 | /* all this shit doesn't belong into sysfs anyway */ | |
3378 | return 0; | |
3379 | } | |
3380 | ||
e2ebc833 | 3381 | static DEVICE_ATTR(channels, S_IRUSR, il3945_show_channels, NULL); |
4bc85c13 | 3382 | |
e2ebc833 | 3383 | static ssize_t il3945_show_antenna(struct device *d, |
4bc85c13 WYG |
3384 | struct device_attribute *attr, char *buf) |
3385 | { | |
46bc8d4b | 3386 | struct il_priv *il = dev_get_drvdata(d); |
4bc85c13 | 3387 | |
46bc8d4b | 3388 | if (!il_is_alive(il)) |
4bc85c13 WYG |
3389 | return -EAGAIN; |
3390 | ||
e2ebc833 | 3391 | return sprintf(buf, "%d\n", il3945_mod_params.antenna); |
4bc85c13 WYG |
3392 | } |
3393 | ||
e2ebc833 | 3394 | static ssize_t il3945_store_antenna(struct device *d, |
4bc85c13 WYG |
3395 | struct device_attribute *attr, |
3396 | const char *buf, size_t count) | |
3397 | { | |
46bc8d4b | 3398 | struct il_priv *il __maybe_unused = dev_get_drvdata(d); |
4bc85c13 WYG |
3399 | int ant; |
3400 | ||
3401 | if (count == 0) | |
3402 | return 0; | |
3403 | ||
3404 | if (sscanf(buf, "%1i", &ant) != 1) { | |
58de00a4 | 3405 | D_INFO("not in hex or decimal form.\n"); |
4bc85c13 WYG |
3406 | return count; |
3407 | } | |
3408 | ||
3409 | if ((ant >= 0) && (ant <= 2)) { | |
58de00a4 | 3410 | D_INFO("Setting antenna select to %d.\n", ant); |
e2ebc833 | 3411 | il3945_mod_params.antenna = (enum il3945_antenna)ant; |
4bc85c13 | 3412 | } else |
58de00a4 | 3413 | D_INFO("Bad antenna select value %d.\n", ant); |
4bc85c13 WYG |
3414 | |
3415 | ||
3416 | return count; | |
3417 | } | |
3418 | ||
e2ebc833 | 3419 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, il3945_show_antenna, il3945_store_antenna); |
4bc85c13 | 3420 | |
e2ebc833 | 3421 | static ssize_t il3945_show_status(struct device *d, |
4bc85c13 WYG |
3422 | struct device_attribute *attr, char *buf) |
3423 | { | |
46bc8d4b SG |
3424 | struct il_priv *il = dev_get_drvdata(d); |
3425 | if (!il_is_alive(il)) | |
4bc85c13 | 3426 | return -EAGAIN; |
46bc8d4b | 3427 | return sprintf(buf, "0x%08x\n", (int)il->status); |
4bc85c13 WYG |
3428 | } |
3429 | ||
e2ebc833 | 3430 | static DEVICE_ATTR(status, S_IRUGO, il3945_show_status, NULL); |
4bc85c13 | 3431 | |
e2ebc833 | 3432 | static ssize_t il3945_dump_error_log(struct device *d, |
4bc85c13 WYG |
3433 | struct device_attribute *attr, |
3434 | const char *buf, size_t count) | |
3435 | { | |
46bc8d4b | 3436 | struct il_priv *il = dev_get_drvdata(d); |
4bc85c13 WYG |
3437 | char *p = (char *)buf; |
3438 | ||
3439 | if (p[0] == '1') | |
46bc8d4b | 3440 | il3945_dump_nic_error_log(il); |
4bc85c13 WYG |
3441 | |
3442 | return strnlen(buf, count); | |
3443 | } | |
3444 | ||
e2ebc833 | 3445 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, il3945_dump_error_log); |
4bc85c13 WYG |
3446 | |
3447 | /***************************************************************************** | |
3448 | * | |
3449 | * driver setup and tear down | |
3450 | * | |
3451 | *****************************************************************************/ | |
3452 | ||
46bc8d4b | 3453 | static void il3945_setup_deferred_work(struct il_priv *il) |
4bc85c13 | 3454 | { |
46bc8d4b | 3455 | il->workqueue = create_singlethread_workqueue(DRV_NAME); |
4bc85c13 | 3456 | |
46bc8d4b | 3457 | init_waitqueue_head(&il->wait_command_queue); |
4bc85c13 | 3458 | |
46bc8d4b SG |
3459 | INIT_WORK(&il->restart, il3945_bg_restart); |
3460 | INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish); | |
3461 | INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start); | |
3462 | INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start); | |
3463 | INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll); | |
4bc85c13 | 3464 | |
46bc8d4b | 3465 | il_setup_scan_deferred_work(il); |
4bc85c13 | 3466 | |
46bc8d4b | 3467 | il3945_hw_setup_deferred_work(il); |
4bc85c13 | 3468 | |
46bc8d4b SG |
3469 | init_timer(&il->watchdog); |
3470 | il->watchdog.data = (unsigned long)il; | |
3471 | il->watchdog.function = il_bg_watchdog; | |
4bc85c13 | 3472 | |
46bc8d4b SG |
3473 | tasklet_init(&il->irq_tasklet, (void (*)(unsigned long)) |
3474 | il3945_irq_tasklet, (unsigned long)il); | |
4bc85c13 WYG |
3475 | } |
3476 | ||
46bc8d4b | 3477 | static void il3945_cancel_deferred_work(struct il_priv *il) |
4bc85c13 | 3478 | { |
46bc8d4b | 3479 | il3945_hw_cancel_deferred_work(il); |
4bc85c13 | 3480 | |
46bc8d4b SG |
3481 | cancel_delayed_work_sync(&il->init_alive_start); |
3482 | cancel_delayed_work(&il->alive_start); | |
4bc85c13 | 3483 | |
46bc8d4b | 3484 | il_cancel_scan_deferred_work(il); |
4bc85c13 WYG |
3485 | } |
3486 | ||
e2ebc833 | 3487 | static struct attribute *il3945_sysfs_entries[] = { |
4bc85c13 WYG |
3488 | &dev_attr_antenna.attr, |
3489 | &dev_attr_channels.attr, | |
3490 | &dev_attr_dump_errors.attr, | |
3491 | &dev_attr_flags.attr, | |
3492 | &dev_attr_filter_flags.attr, | |
3493 | &dev_attr_measurement.attr, | |
3494 | &dev_attr_retry_rate.attr, | |
3495 | &dev_attr_status.attr, | |
3496 | &dev_attr_temperature.attr, | |
3497 | &dev_attr_tx_power.attr, | |
be663ab6 | 3498 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
4bc85c13 WYG |
3499 | &dev_attr_debug_level.attr, |
3500 | #endif | |
3501 | NULL | |
3502 | }; | |
3503 | ||
e2ebc833 | 3504 | static struct attribute_group il3945_attribute_group = { |
4bc85c13 | 3505 | .name = NULL, /* put in device directory */ |
e2ebc833 | 3506 | .attrs = il3945_sysfs_entries, |
4bc85c13 WYG |
3507 | }; |
3508 | ||
e2ebc833 SG |
3509 | struct ieee80211_ops il3945_hw_ops = { |
3510 | .tx = il3945_mac_tx, | |
3511 | .start = il3945_mac_start, | |
3512 | .stop = il3945_mac_stop, | |
3513 | .add_interface = il_mac_add_interface, | |
3514 | .remove_interface = il_mac_remove_interface, | |
3515 | .change_interface = il_mac_change_interface, | |
3516 | .config = il_mac_config, | |
3517 | .configure_filter = il3945_configure_filter, | |
3518 | .set_key = il3945_mac_set_key, | |
3519 | .conf_tx = il_mac_conf_tx, | |
3520 | .reset_tsf = il_mac_reset_tsf, | |
3521 | .bss_info_changed = il_mac_bss_info_changed, | |
3522 | .hw_scan = il_mac_hw_scan, | |
3523 | .sta_add = il3945_mac_sta_add, | |
3524 | .sta_remove = il_mac_sta_remove, | |
3525 | .tx_last_beacon = il_mac_tx_last_beacon, | |
4bc85c13 WYG |
3526 | }; |
3527 | ||
46bc8d4b | 3528 | static int il3945_init_drv(struct il_priv *il) |
4bc85c13 WYG |
3529 | { |
3530 | int ret; | |
46bc8d4b | 3531 | struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; |
4bc85c13 | 3532 | |
46bc8d4b SG |
3533 | il->retry_rate = 1; |
3534 | il->beacon_skb = NULL; | |
4bc85c13 | 3535 | |
46bc8d4b SG |
3536 | spin_lock_init(&il->sta_lock); |
3537 | spin_lock_init(&il->hcmd_lock); | |
4bc85c13 | 3538 | |
46bc8d4b | 3539 | INIT_LIST_HEAD(&il->free_frames); |
4bc85c13 | 3540 | |
46bc8d4b | 3541 | mutex_init(&il->mutex); |
4bc85c13 | 3542 | |
46bc8d4b SG |
3543 | il->ieee_channels = NULL; |
3544 | il->ieee_rates = NULL; | |
3545 | il->band = IEEE80211_BAND_2GHZ; | |
4bc85c13 | 3546 | |
46bc8d4b SG |
3547 | il->iw_mode = NL80211_IFTYPE_STATION; |
3548 | il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF; | |
4bc85c13 WYG |
3549 | |
3550 | /* initialize force reset */ | |
46bc8d4b | 3551 | il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD; |
4bc85c13 | 3552 | |
4bc85c13 | 3553 | if (eeprom->version < EEPROM_3945_EEPROM_VERSION) { |
9406f797 | 3554 | IL_WARN("Unsupported EEPROM version: 0x%04X\n", |
4bc85c13 WYG |
3555 | eeprom->version); |
3556 | ret = -EINVAL; | |
3557 | goto err; | |
3558 | } | |
46bc8d4b | 3559 | ret = il_init_channel_map(il); |
4bc85c13 | 3560 | if (ret) { |
9406f797 | 3561 | IL_ERR("initializing regulatory failed: %d\n", ret); |
4bc85c13 WYG |
3562 | goto err; |
3563 | } | |
3564 | ||
3565 | /* Set up txpower settings in driver for all channels */ | |
46bc8d4b | 3566 | if (il3945_txpower_set_from_eeprom(il)) { |
4bc85c13 WYG |
3567 | ret = -EIO; |
3568 | goto err_free_channel_map; | |
3569 | } | |
3570 | ||
46bc8d4b | 3571 | ret = il_init_geos(il); |
4bc85c13 | 3572 | if (ret) { |
9406f797 | 3573 | IL_ERR("initializing geos failed: %d\n", ret); |
4bc85c13 WYG |
3574 | goto err_free_channel_map; |
3575 | } | |
46bc8d4b | 3576 | il3945_init_hw_rates(il, il->ieee_rates); |
4bc85c13 WYG |
3577 | |
3578 | return 0; | |
3579 | ||
3580 | err_free_channel_map: | |
46bc8d4b | 3581 | il_free_channel_map(il); |
4bc85c13 WYG |
3582 | err: |
3583 | return ret; | |
3584 | } | |
3585 | ||
3586 | #define IWL3945_MAX_PROBE_REQUEST 200 | |
3587 | ||
46bc8d4b | 3588 | static int il3945_setup_mac(struct il_priv *il) |
4bc85c13 WYG |
3589 | { |
3590 | int ret; | |
46bc8d4b | 3591 | struct ieee80211_hw *hw = il->hw; |
4bc85c13 WYG |
3592 | |
3593 | hw->rate_control_algorithm = "iwl-3945-rs"; | |
e2ebc833 SG |
3594 | hw->sta_data_size = sizeof(struct il3945_sta_priv); |
3595 | hw->vif_data_size = sizeof(struct il_vif_priv); | |
4bc85c13 WYG |
3596 | |
3597 | /* Tell mac80211 our characteristics */ | |
3598 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
3599 | IEEE80211_HW_SPECTRUM_MGMT; | |
3600 | ||
4bc85c13 | 3601 | hw->wiphy->interface_modes = |
46bc8d4b | 3602 | il->contexts[IL_RXON_CTX_BSS].interface_modes; |
4bc85c13 WYG |
3603 | |
3604 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | | |
3605 | WIPHY_FLAG_DISABLE_BEACON_HINTS | | |
3606 | WIPHY_FLAG_IBSS_RSN; | |
3607 | ||
3608 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945; | |
3609 | /* we create the 802.11 header and a zero-length SSID element */ | |
3610 | hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2; | |
3611 | ||
3612 | /* Default value; 4 EDCA QOS priorities */ | |
3613 | hw->queues = 4; | |
3614 | ||
46bc8d4b SG |
3615 | if (il->bands[IEEE80211_BAND_2GHZ].n_channels) |
3616 | il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3617 | &il->bands[IEEE80211_BAND_2GHZ]; | |
4bc85c13 | 3618 | |
46bc8d4b SG |
3619 | if (il->bands[IEEE80211_BAND_5GHZ].n_channels) |
3620 | il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3621 | &il->bands[IEEE80211_BAND_5GHZ]; | |
4bc85c13 | 3622 | |
46bc8d4b | 3623 | il_leds_init(il); |
4bc85c13 | 3624 | |
46bc8d4b | 3625 | ret = ieee80211_register_hw(il->hw); |
4bc85c13 | 3626 | if (ret) { |
9406f797 | 3627 | IL_ERR("Failed to register hw (error %d)\n", ret); |
4bc85c13 WYG |
3628 | return ret; |
3629 | } | |
46bc8d4b | 3630 | il->mac80211_registered = 1; |
4bc85c13 WYG |
3631 | |
3632 | return 0; | |
3633 | } | |
3634 | ||
e2ebc833 | 3635 | static int il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
4bc85c13 WYG |
3636 | { |
3637 | int err = 0, i; | |
46bc8d4b | 3638 | struct il_priv *il; |
4bc85c13 | 3639 | struct ieee80211_hw *hw; |
e2ebc833 SG |
3640 | struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data); |
3641 | struct il3945_eeprom *eeprom; | |
4bc85c13 WYG |
3642 | unsigned long flags; |
3643 | ||
3644 | /*********************** | |
3645 | * 1. Allocating HW data | |
3646 | * ********************/ | |
3647 | ||
3648 | /* mac80211 allocates memory for this device instance, including | |
46bc8d4b | 3649 | * space for this driver's ilate structure */ |
e2ebc833 | 3650 | hw = il_alloc_all(cfg); |
4bc85c13 WYG |
3651 | if (hw == NULL) { |
3652 | pr_err("Can not allocate network device\n"); | |
3653 | err = -ENOMEM; | |
3654 | goto out; | |
3655 | } | |
46bc8d4b | 3656 | il = hw->priv; |
4bc85c13 WYG |
3657 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3658 | ||
46bc8d4b | 3659 | il->cmd_queue = IWL39_CMD_QUEUE_NUM; |
4bc85c13 WYG |
3660 | |
3661 | /* 3945 has only one valid context */ | |
46bc8d4b | 3662 | il->valid_contexts = BIT(IL_RXON_CTX_BSS); |
4bc85c13 | 3663 | |
e2ebc833 | 3664 | for (i = 0; i < NUM_IL_RXON_CTX; i++) |
46bc8d4b SG |
3665 | il->contexts[i].ctxid = i; |
3666 | ||
3667 | il->contexts[IL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON; | |
3668 | il->contexts[IL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING; | |
3669 | il->contexts[IL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC; | |
3670 | il->contexts[IL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM; | |
3671 | il->contexts[IL_RXON_CTX_BSS].ap_sta_id = IL_AP_ID; | |
3672 | il->contexts[IL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY; | |
3673 | il->contexts[IL_RXON_CTX_BSS].interface_modes = | |
4bc85c13 WYG |
3674 | BIT(NL80211_IFTYPE_STATION) | |
3675 | BIT(NL80211_IFTYPE_ADHOC); | |
46bc8d4b SG |
3676 | il->contexts[IL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS; |
3677 | il->contexts[IL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS; | |
3678 | il->contexts[IL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS; | |
4bc85c13 WYG |
3679 | |
3680 | /* | |
3681 | * Disabling hardware scan means that mac80211 will perform scans | |
3682 | * "the hard way", rather than using device's scan. | |
3683 | */ | |
e2ebc833 | 3684 | if (il3945_mod_params.disable_hw_scan) { |
58de00a4 | 3685 | D_INFO("Disabling hw_scan\n"); |
e2ebc833 | 3686 | il3945_hw_ops.hw_scan = NULL; |
4bc85c13 WYG |
3687 | } |
3688 | ||
58de00a4 | 3689 | D_INFO("*** LOAD DRIVER ***\n"); |
46bc8d4b SG |
3690 | il->cfg = cfg; |
3691 | il->pci_dev = pdev; | |
3692 | il->inta_mask = CSR_INI_SET_MASK; | |
4bc85c13 | 3693 | |
46bc8d4b | 3694 | if (il_alloc_traffic_mem(il)) |
9406f797 | 3695 | IL_ERR("Not enough memory to generate traffic log\n"); |
4bc85c13 WYG |
3696 | |
3697 | /*************************** | |
3698 | * 2. Initializing PCI bus | |
3699 | * *************************/ | |
3700 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
3701 | PCIE_LINK_STATE_CLKPM); | |
3702 | ||
3703 | if (pci_enable_device(pdev)) { | |
3704 | err = -ENODEV; | |
3705 | goto out_ieee80211_free_hw; | |
3706 | } | |
3707 | ||
3708 | pci_set_master(pdev); | |
3709 | ||
3710 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
3711 | if (!err) | |
3712 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
3713 | if (err) { | |
9406f797 | 3714 | IL_WARN("No suitable DMA available.\n"); |
4bc85c13 WYG |
3715 | goto out_pci_disable_device; |
3716 | } | |
3717 | ||
46bc8d4b | 3718 | pci_set_drvdata(pdev, il); |
4bc85c13 WYG |
3719 | err = pci_request_regions(pdev, DRV_NAME); |
3720 | if (err) | |
3721 | goto out_pci_disable_device; | |
3722 | ||
3723 | /*********************** | |
3724 | * 3. Read REV Register | |
3725 | * ********************/ | |
46bc8d4b SG |
3726 | il->hw_base = pci_iomap(pdev, 0, 0); |
3727 | if (!il->hw_base) { | |
4bc85c13 WYG |
3728 | err = -ENODEV; |
3729 | goto out_pci_release_regions; | |
3730 | } | |
3731 | ||
58de00a4 | 3732 | D_INFO("pci_resource_len = 0x%08llx\n", |
4bc85c13 | 3733 | (unsigned long long) pci_resource_len(pdev, 0)); |
58de00a4 | 3734 | D_INFO("pci_resource_base = %p\n", il->hw_base); |
4bc85c13 WYG |
3735 | |
3736 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
3737 | * PCI Tx retries from interfering with C3 CPU state */ | |
3738 | pci_write_config_byte(pdev, 0x41, 0x00); | |
3739 | ||
3740 | /* these spin locks will be used in apm_ops.init and EEPROM access | |
3741 | * we should init now | |
3742 | */ | |
46bc8d4b SG |
3743 | spin_lock_init(&il->reg_lock); |
3744 | spin_lock_init(&il->lock); | |
4bc85c13 WYG |
3745 | |
3746 | /* | |
3747 | * stop and reset the on-board processor just in case it is in a | |
3748 | * strange state ... like being left stranded by a primary kernel | |
3749 | * and this is now the kdump kernel trying to start up | |
3750 | */ | |
841b2cca | 3751 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
4bc85c13 WYG |
3752 | |
3753 | /*********************** | |
3754 | * 4. Read EEPROM | |
3755 | * ********************/ | |
3756 | ||
3757 | /* Read the EEPROM */ | |
46bc8d4b | 3758 | err = il_eeprom_init(il); |
4bc85c13 | 3759 | if (err) { |
9406f797 | 3760 | IL_ERR("Unable to init EEPROM\n"); |
4bc85c13 WYG |
3761 | goto out_iounmap; |
3762 | } | |
3763 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
46bc8d4b | 3764 | eeprom = (struct il3945_eeprom *)il->eeprom; |
58de00a4 | 3765 | D_INFO("MAC address: %pM\n", eeprom->mac_address); |
46bc8d4b | 3766 | SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address); |
4bc85c13 WYG |
3767 | |
3768 | /*********************** | |
3769 | * 5. Setup HW Constants | |
3770 | * ********************/ | |
3771 | /* Device-specific setup */ | |
46bc8d4b | 3772 | if (il3945_hw_set_hw_params(il)) { |
9406f797 | 3773 | IL_ERR("failed to set hw settings\n"); |
4bc85c13 WYG |
3774 | goto out_eeprom_free; |
3775 | } | |
3776 | ||
3777 | /*********************** | |
46bc8d4b | 3778 | * 6. Setup il |
4bc85c13 WYG |
3779 | * ********************/ |
3780 | ||
46bc8d4b | 3781 | err = il3945_init_drv(il); |
4bc85c13 | 3782 | if (err) { |
9406f797 | 3783 | IL_ERR("initializing driver failed\n"); |
4bc85c13 WYG |
3784 | goto out_unset_hw_params; |
3785 | } | |
3786 | ||
9406f797 | 3787 | IL_INFO("Detected Intel Wireless WiFi Link %s\n", |
46bc8d4b | 3788 | il->cfg->name); |
4bc85c13 WYG |
3789 | |
3790 | /*********************** | |
3791 | * 7. Setup Services | |
3792 | * ********************/ | |
3793 | ||
46bc8d4b SG |
3794 | spin_lock_irqsave(&il->lock, flags); |
3795 | il_disable_interrupts(il); | |
3796 | spin_unlock_irqrestore(&il->lock, flags); | |
4bc85c13 | 3797 | |
46bc8d4b | 3798 | pci_enable_msi(il->pci_dev); |
4bc85c13 | 3799 | |
46bc8d4b SG |
3800 | err = request_irq(il->pci_dev->irq, il_isr, |
3801 | IRQF_SHARED, DRV_NAME, il); | |
4bc85c13 | 3802 | if (err) { |
9406f797 | 3803 | IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq); |
4bc85c13 WYG |
3804 | goto out_disable_msi; |
3805 | } | |
3806 | ||
e2ebc833 | 3807 | err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group); |
4bc85c13 | 3808 | if (err) { |
9406f797 | 3809 | IL_ERR("failed to create sysfs device attributes\n"); |
4bc85c13 WYG |
3810 | goto out_release_irq; |
3811 | } | |
3812 | ||
46bc8d4b SG |
3813 | il_set_rxon_channel(il, |
3814 | &il->bands[IEEE80211_BAND_2GHZ].channels[5], | |
3815 | &il->contexts[IL_RXON_CTX_BSS]); | |
3816 | il3945_setup_deferred_work(il); | |
3817 | il3945_setup_rx_handlers(il); | |
3818 | il_power_initialize(il); | |
4bc85c13 WYG |
3819 | |
3820 | /********************************* | |
3821 | * 8. Setup and Register mac80211 | |
3822 | * *******************************/ | |
3823 | ||
46bc8d4b | 3824 | il_enable_interrupts(il); |
4bc85c13 | 3825 | |
46bc8d4b | 3826 | err = il3945_setup_mac(il); |
4bc85c13 WYG |
3827 | if (err) |
3828 | goto out_remove_sysfs; | |
3829 | ||
46bc8d4b | 3830 | err = il_dbgfs_register(il, DRV_NAME); |
4bc85c13 | 3831 | if (err) |
9406f797 | 3832 | IL_ERR("failed to create debugfs files. Ignoring error: %d\n", err); |
4bc85c13 WYG |
3833 | |
3834 | /* Start monitoring the killswitch */ | |
46bc8d4b | 3835 | queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, |
4bc85c13 WYG |
3836 | 2 * HZ); |
3837 | ||
3838 | return 0; | |
3839 | ||
3840 | out_remove_sysfs: | |
46bc8d4b SG |
3841 | destroy_workqueue(il->workqueue); |
3842 | il->workqueue = NULL; | |
e2ebc833 | 3843 | sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group); |
4bc85c13 | 3844 | out_release_irq: |
46bc8d4b | 3845 | free_irq(il->pci_dev->irq, il); |
4bc85c13 | 3846 | out_disable_msi: |
46bc8d4b SG |
3847 | pci_disable_msi(il->pci_dev); |
3848 | il_free_geos(il); | |
3849 | il_free_channel_map(il); | |
4bc85c13 | 3850 | out_unset_hw_params: |
46bc8d4b | 3851 | il3945_unset_hw_params(il); |
4bc85c13 | 3852 | out_eeprom_free: |
46bc8d4b | 3853 | il_eeprom_free(il); |
4bc85c13 | 3854 | out_iounmap: |
46bc8d4b | 3855 | pci_iounmap(pdev, il->hw_base); |
4bc85c13 WYG |
3856 | out_pci_release_regions: |
3857 | pci_release_regions(pdev); | |
3858 | out_pci_disable_device: | |
3859 | pci_set_drvdata(pdev, NULL); | |
3860 | pci_disable_device(pdev); | |
3861 | out_ieee80211_free_hw: | |
46bc8d4b SG |
3862 | il_free_traffic_mem(il); |
3863 | ieee80211_free_hw(il->hw); | |
4bc85c13 WYG |
3864 | out: |
3865 | return err; | |
3866 | } | |
3867 | ||
e2ebc833 | 3868 | static void __devexit il3945_pci_remove(struct pci_dev *pdev) |
4bc85c13 | 3869 | { |
46bc8d4b | 3870 | struct il_priv *il = pci_get_drvdata(pdev); |
4bc85c13 WYG |
3871 | unsigned long flags; |
3872 | ||
46bc8d4b | 3873 | if (!il) |
4bc85c13 WYG |
3874 | return; |
3875 | ||
58de00a4 | 3876 | D_INFO("*** UNLOAD DRIVER ***\n"); |
4bc85c13 | 3877 | |
46bc8d4b | 3878 | il_dbgfs_unregister(il); |
4bc85c13 | 3879 | |
46bc8d4b | 3880 | set_bit(STATUS_EXIT_PENDING, &il->status); |
4bc85c13 | 3881 | |
46bc8d4b | 3882 | il_leds_exit(il); |
4bc85c13 | 3883 | |
46bc8d4b SG |
3884 | if (il->mac80211_registered) { |
3885 | ieee80211_unregister_hw(il->hw); | |
3886 | il->mac80211_registered = 0; | |
4bc85c13 | 3887 | } else { |
46bc8d4b | 3888 | il3945_down(il); |
4bc85c13 WYG |
3889 | } |
3890 | ||
3891 | /* | |
3892 | * Make sure device is reset to low power before unloading driver. | |
e2ebc833 SG |
3893 | * This may be redundant with il_down(), but there are paths to |
3894 | * run il_down() without calling apm_ops.stop(), and there are | |
3895 | * paths to avoid running il_down() at all before leaving driver. | |
4bc85c13 WYG |
3896 | * This (inexpensive) call *makes sure* device is reset. |
3897 | */ | |
46bc8d4b | 3898 | il_apm_stop(il); |
4bc85c13 WYG |
3899 | |
3900 | /* make sure we flush any pending irq or | |
3901 | * tasklet for the driver | |
3902 | */ | |
46bc8d4b SG |
3903 | spin_lock_irqsave(&il->lock, flags); |
3904 | il_disable_interrupts(il); | |
3905 | spin_unlock_irqrestore(&il->lock, flags); | |
4bc85c13 | 3906 | |
46bc8d4b | 3907 | il3945_synchronize_irq(il); |
4bc85c13 | 3908 | |
e2ebc833 | 3909 | sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group); |
4bc85c13 | 3910 | |
46bc8d4b | 3911 | cancel_delayed_work_sync(&il->_3945.rfkill_poll); |
4bc85c13 | 3912 | |
46bc8d4b | 3913 | il3945_dealloc_ucode_pci(il); |
4bc85c13 | 3914 | |
46bc8d4b SG |
3915 | if (il->rxq.bd) |
3916 | il3945_rx_queue_free(il, &il->rxq); | |
3917 | il3945_hw_txq_ctx_free(il); | |
4bc85c13 | 3918 | |
46bc8d4b | 3919 | il3945_unset_hw_params(il); |
4bc85c13 WYG |
3920 | |
3921 | /*netif_stop_queue(dev); */ | |
46bc8d4b | 3922 | flush_workqueue(il->workqueue); |
4bc85c13 | 3923 | |
e2ebc833 | 3924 | /* ieee80211_unregister_hw calls il3945_mac_stop, which flushes |
46bc8d4b | 3925 | * il->workqueue... so we can't take down the workqueue |
4bc85c13 | 3926 | * until now... */ |
46bc8d4b SG |
3927 | destroy_workqueue(il->workqueue); |
3928 | il->workqueue = NULL; | |
3929 | il_free_traffic_mem(il); | |
4bc85c13 | 3930 | |
46bc8d4b | 3931 | free_irq(pdev->irq, il); |
4bc85c13 WYG |
3932 | pci_disable_msi(pdev); |
3933 | ||
46bc8d4b | 3934 | pci_iounmap(pdev, il->hw_base); |
4bc85c13 WYG |
3935 | pci_release_regions(pdev); |
3936 | pci_disable_device(pdev); | |
3937 | pci_set_drvdata(pdev, NULL); | |
3938 | ||
46bc8d4b SG |
3939 | il_free_channel_map(il); |
3940 | il_free_geos(il); | |
3941 | kfree(il->scan_cmd); | |
3942 | if (il->beacon_skb) | |
3943 | dev_kfree_skb(il->beacon_skb); | |
4bc85c13 | 3944 | |
46bc8d4b | 3945 | ieee80211_free_hw(il->hw); |
4bc85c13 WYG |
3946 | } |
3947 | ||
3948 | ||
3949 | /***************************************************************************** | |
3950 | * | |
3951 | * driver and module entry point | |
3952 | * | |
3953 | *****************************************************************************/ | |
3954 | ||
e2ebc833 | 3955 | static struct pci_driver il3945_driver = { |
4bc85c13 | 3956 | .name = DRV_NAME, |
e2ebc833 SG |
3957 | .id_table = il3945_hw_card_ids, |
3958 | .probe = il3945_pci_probe, | |
3959 | .remove = __devexit_p(il3945_pci_remove), | |
3960 | .driver.pm = IL_LEGACY_PM_OPS, | |
4bc85c13 WYG |
3961 | }; |
3962 | ||
e2ebc833 | 3963 | static int __init il3945_init(void) |
4bc85c13 WYG |
3964 | { |
3965 | ||
3966 | int ret; | |
3967 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3968 | pr_info(DRV_COPYRIGHT "\n"); | |
3969 | ||
e2ebc833 | 3970 | ret = il3945_rate_control_register(); |
4bc85c13 WYG |
3971 | if (ret) { |
3972 | pr_err("Unable to register rate control algorithm: %d\n", ret); | |
3973 | return ret; | |
3974 | } | |
3975 | ||
e2ebc833 | 3976 | ret = pci_register_driver(&il3945_driver); |
4bc85c13 WYG |
3977 | if (ret) { |
3978 | pr_err("Unable to initialize PCI module\n"); | |
3979 | goto error_register; | |
3980 | } | |
3981 | ||
3982 | return ret; | |
3983 | ||
3984 | error_register: | |
e2ebc833 | 3985 | il3945_rate_control_unregister(); |
4bc85c13 WYG |
3986 | return ret; |
3987 | } | |
3988 | ||
e2ebc833 | 3989 | static void __exit il3945_exit(void) |
4bc85c13 | 3990 | { |
e2ebc833 SG |
3991 | pci_unregister_driver(&il3945_driver); |
3992 | il3945_rate_control_unregister(); | |
4bc85c13 WYG |
3993 | } |
3994 | ||
3995 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); | |
3996 | ||
e2ebc833 | 3997 | module_param_named(antenna, il3945_mod_params.antenna, int, S_IRUGO); |
4bc85c13 | 3998 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
e2ebc833 | 3999 | module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, S_IRUGO); |
4bc85c13 | 4000 | MODULE_PARM_DESC(swcrypto, |
be663ab6 | 4001 | "using software crypto (default 1 [software])"); |
e2ebc833 | 4002 | module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, |
be663ab6 | 4003 | int, S_IRUGO); |
0263aa45 | 4004 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)"); |
be663ab6 | 4005 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
d2ddf621 | 4006 | module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR); |
4bc85c13 WYG |
4007 | MODULE_PARM_DESC(debug, "debug output mask"); |
4008 | #endif | |
e2ebc833 | 4009 | module_param_named(fw_restart, il3945_mod_params.restart_fw, int, S_IRUGO); |
be663ab6 | 4010 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); |
4bc85c13 | 4011 | |
e2ebc833 SG |
4012 | module_exit(il3945_exit); |
4013 | module_init(il3945_init); |