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b305a080 WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
901069c7 | 5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
b305a080 WYG |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/sched.h> | |
34 | ||
35 | #include "iwl-dev.h" | |
36 | #include "iwl-core.h" | |
37 | #include "iwl-sta.h" | |
38 | #include "iwl-io.h" | |
74bcdb33 | 39 | #include "iwl-helpers.h" |
19e6cda0 | 40 | #include "iwl-agn-hw.h" |
8d801080 | 41 | #include "iwl-agn.h" |
b305a080 | 42 | |
74bcdb33 WYG |
43 | /* |
44 | * mac80211 queues, ACs, hardware queues, FIFOs. | |
45 | * | |
46 | * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues | |
47 | * | |
48 | * Mac80211 uses the following numbers, which we get as from it | |
49 | * by way of skb_get_queue_mapping(skb): | |
50 | * | |
51 | * VO 0 | |
52 | * VI 1 | |
53 | * BE 2 | |
54 | * BK 3 | |
55 | * | |
56 | * | |
57 | * Regular (not A-MPDU) frames are put into hardware queues corresponding | |
58 | * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their | |
59 | * own queue per aggregation session (RA/TID combination), such queues are | |
60 | * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In | |
61 | * order to map frames to the right queue, we also need an AC->hw queue | |
62 | * mapping. This is implemented here. | |
63 | * | |
64 | * Due to the way hw queues are set up (by the hw specific modules like | |
65 | * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity | |
66 | * mapping. | |
67 | */ | |
68 | ||
69 | static const u8 tid_to_ac[] = { | |
0c4ac342 JB |
70 | IEEE80211_AC_BE, |
71 | IEEE80211_AC_BK, | |
72 | IEEE80211_AC_BK, | |
73 | IEEE80211_AC_BE, | |
74 | IEEE80211_AC_VI, | |
75 | IEEE80211_AC_VI, | |
76 | IEEE80211_AC_VO, | |
77 | IEEE80211_AC_VO | |
74bcdb33 WYG |
78 | }; |
79 | ||
c2845d01 SZ |
80 | static inline int get_ac_from_tid(u16 tid) |
81 | { | |
82 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) | |
83 | return tid_to_ac[tid]; | |
84 | ||
85 | /* no support for TIDs 8-15 yet */ | |
86 | return -EINVAL; | |
87 | } | |
88 | ||
e72f368b | 89 | static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid) |
74bcdb33 WYG |
90 | { |
91 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) | |
e72f368b | 92 | return ctx->ac_to_fifo[tid_to_ac[tid]]; |
74bcdb33 WYG |
93 | |
94 | /* no support for TIDs 8-15 yet */ | |
95 | return -EINVAL; | |
96 | } | |
97 | ||
b305a080 WYG |
98 | /** |
99 | * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
100 | */ | |
94b00658 JB |
101 | static void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv, |
102 | struct iwl_tx_queue *txq, | |
103 | u16 byte_cnt) | |
b305a080 | 104 | { |
19e6cda0 | 105 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
b305a080 WYG |
106 | int write_ptr = txq->q.write_ptr; |
107 | int txq_id = txq->q.id; | |
108 | u8 sec_ctl = 0; | |
109 | u8 sta_id = 0; | |
110 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
111 | __le16 bc_ent; | |
112 | ||
113 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); | |
114 | ||
ccb6c1c0 JB |
115 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
116 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; | |
117 | ||
118 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
119 | case TX_CMD_SEC_CCM: | |
120 | len += CCMP_MIC_LEN; | |
121 | break; | |
122 | case TX_CMD_SEC_TKIP: | |
123 | len += TKIP_ICV_LEN; | |
124 | break; | |
125 | case TX_CMD_SEC_WEP: | |
126 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
127 | break; | |
b305a080 WYG |
128 | } |
129 | ||
130 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
131 | ||
132 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
133 | ||
134 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
135 | scd_bc_tbl[txq_id]. | |
136 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
137 | } | |
138 | ||
94b00658 JB |
139 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
140 | struct iwl_tx_queue *txq) | |
b305a080 | 141 | { |
19e6cda0 | 142 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
b305a080 WYG |
143 | int txq_id = txq->q.id; |
144 | int read_ptr = txq->q.read_ptr; | |
145 | u8 sta_id = 0; | |
146 | __le16 bc_ent; | |
147 | ||
148 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
149 | ||
13bb9483 | 150 | if (txq_id != priv->cmd_queue) |
b305a080 WYG |
151 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
152 | ||
153 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
154 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
155 | ||
156 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
157 | scd_bc_tbl[txq_id]. | |
158 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
159 | } | |
160 | ||
161 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, | |
162 | u16 txq_id) | |
163 | { | |
164 | u32 tbl_dw_addr; | |
165 | u32 tbl_dw; | |
166 | u16 scd_q2ratid; | |
167 | ||
168 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
169 | ||
170 | tbl_dw_addr = priv->scd_base_addr + | |
f4388adc | 171 | IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); |
b305a080 WYG |
172 | |
173 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
174 | ||
175 | if (txq_id & 0x1) | |
176 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
177 | else | |
178 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
179 | ||
180 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
186 | { | |
187 | /* Simply stop the queue, but don't change any configuration; | |
188 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
189 | iwl_write_prph(priv, | |
f4388adc WYG |
190 | IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id), |
191 | (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
192 | (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
b305a080 WYG |
193 | } |
194 | ||
195 | void iwlagn_set_wr_ptrs(struct iwl_priv *priv, | |
196 | int txq_id, u32 index) | |
197 | { | |
198 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
199 | (index & 0xff) | (txq_id << 8)); | |
f4388adc | 200 | iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index); |
b305a080 WYG |
201 | } |
202 | ||
203 | void iwlagn_tx_queue_set_status(struct iwl_priv *priv, | |
204 | struct iwl_tx_queue *txq, | |
205 | int tx_fifo_id, int scd_retry) | |
206 | { | |
207 | int txq_id = txq->q.id; | |
208 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; | |
209 | ||
f4388adc WYG |
210 | iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id), |
211 | (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
212 | (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) | | |
213 | (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) | | |
214 | IWLAGN_SCD_QUEUE_STTS_REG_MSK); | |
b305a080 WYG |
215 | |
216 | txq->sched_retry = scd_retry; | |
217 | ||
218 | IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n", | |
219 | active ? "Activate" : "Deactivate", | |
220 | scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); | |
221 | } | |
222 | ||
c8823ec1 | 223 | static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id, int tid) |
b305a080 | 224 | { |
19e6cda0 | 225 | if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || |
7cb1b088 WYG |
226 | (IWLAGN_FIRST_AMPDU_QUEUE + |
227 | priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) { | |
b305a080 WYG |
228 | IWL_WARN(priv, |
229 | "queue number out of range: %d, must be %d to %d\n", | |
19e6cda0 WYG |
230 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, |
231 | IWLAGN_FIRST_AMPDU_QUEUE + | |
7cb1b088 | 232 | priv->cfg->base_params->num_of_ampdu_queues - 1); |
b305a080 WYG |
233 | return -EINVAL; |
234 | } | |
235 | ||
b305a080 | 236 | /* Modify device's station table to Tx this TID */ |
c8823ec1 JB |
237 | return iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
238 | } | |
239 | ||
240 | void iwlagn_txq_agg_queue_setup(struct iwl_priv *priv, | |
241 | struct ieee80211_sta *sta, | |
242 | int tid, int frame_limit) | |
243 | { | |
244 | int sta_id, tx_fifo, txq_id, ssn_idx; | |
245 | u16 ra_tid; | |
246 | unsigned long flags; | |
247 | struct iwl_tid_data *tid_data; | |
248 | ||
249 | sta_id = iwl_sta_id(sta); | |
250 | if (WARN_ON(sta_id == IWL_INVALID_STATION)) | |
251 | return; | |
252 | if (WARN_ON(tid >= MAX_TID_COUNT)) | |
253 | return; | |
254 | ||
255 | spin_lock_irqsave(&priv->sta_lock, flags); | |
256 | tid_data = &priv->stations[sta_id].tid[tid]; | |
257 | ssn_idx = SEQ_TO_SN(tid_data->seq_number); | |
258 | txq_id = tid_data->agg.txq_id; | |
259 | tx_fifo = tid_data->agg.tx_fifo; | |
260 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
261 | ||
262 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
b305a080 WYG |
263 | |
264 | spin_lock_irqsave(&priv->lock, flags); | |
265 | ||
266 | /* Stop this Tx queue before configuring it */ | |
267 | iwlagn_tx_queue_stop_scheduler(priv, txq_id); | |
268 | ||
269 | /* Map receiver-address / traffic-ID to this queue */ | |
270 | iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
271 | ||
272 | /* Set this queue as a chain-building queue */ | |
f4388adc | 273 | iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id)); |
b305a080 WYG |
274 | |
275 | /* enable aggregations for the queue */ | |
f4388adc | 276 | iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id)); |
b305a080 WYG |
277 | |
278 | /* Place first TFD at index corresponding to start sequence number. | |
279 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
280 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
281 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
282 | iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx); | |
283 | ||
284 | /* Set up Tx window size and frame limit for this queue */ | |
285 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
f4388adc | 286 | IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + |
b305a080 | 287 | sizeof(u32), |
c8823ec1 | 288 | ((frame_limit << |
f4388adc WYG |
289 | IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & |
290 | IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
c8823ec1 | 291 | ((frame_limit << |
f4388adc WYG |
292 | IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & |
293 | IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
b305a080 | 294 | |
f4388adc | 295 | iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id)); |
b305a080 WYG |
296 | |
297 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
298 | iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
299 | ||
300 | spin_unlock_irqrestore(&priv->lock, flags); | |
b305a080 WYG |
301 | } |
302 | ||
7ffef13d JB |
303 | static int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
304 | u16 ssn_idx, u8 tx_fifo) | |
b305a080 | 305 | { |
19e6cda0 | 306 | if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || |
7cb1b088 WYG |
307 | (IWLAGN_FIRST_AMPDU_QUEUE + |
308 | priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) { | |
b305a080 WYG |
309 | IWL_ERR(priv, |
310 | "queue number out of range: %d, must be %d to %d\n", | |
19e6cda0 WYG |
311 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, |
312 | IWLAGN_FIRST_AMPDU_QUEUE + | |
7cb1b088 | 313 | priv->cfg->base_params->num_of_ampdu_queues - 1); |
b305a080 WYG |
314 | return -EINVAL; |
315 | } | |
316 | ||
317 | iwlagn_tx_queue_stop_scheduler(priv, txq_id); | |
318 | ||
f4388adc | 319 | iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id)); |
b305a080 WYG |
320 | |
321 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
322 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
323 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
324 | iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx); | |
325 | ||
f4388adc | 326 | iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id)); |
b305a080 WYG |
327 | iwl_txq_ctx_deactivate(priv, txq_id); |
328 | iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | /* | |
334 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
335 | * must be called under priv->lock and mac access | |
336 | */ | |
337 | void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask) | |
338 | { | |
f4388adc | 339 | iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask); |
b305a080 | 340 | } |
74bcdb33 | 341 | |
74bcdb33 WYG |
342 | /* |
343 | * handle build REPLY_TX command notification. | |
344 | */ | |
345 | static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv, | |
d44ae69e JB |
346 | struct sk_buff *skb, |
347 | struct iwl_tx_cmd *tx_cmd, | |
348 | struct ieee80211_tx_info *info, | |
349 | struct ieee80211_hdr *hdr, | |
350 | u8 std_id) | |
74bcdb33 WYG |
351 | { |
352 | __le16 fc = hdr->frame_control; | |
353 | __le32 tx_flags = tx_cmd->tx_flags; | |
354 | ||
355 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
356 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { | |
357 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
358 | if (ieee80211_is_mgmt(fc)) | |
359 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
360 | if (ieee80211_is_probe_resp(fc) && | |
361 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
362 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
363 | } else { | |
364 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
365 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
366 | } | |
367 | ||
368 | if (ieee80211_is_back_req(fc)) | |
369 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; | |
d44ae69e | 370 | else if (info->band == IEEE80211_BAND_2GHZ && |
7cb1b088 WYG |
371 | priv->cfg->bt_params && |
372 | priv->cfg->bt_params->advanced_bt_coexist && | |
d44ae69e JB |
373 | (ieee80211_is_auth(fc) || ieee80211_is_assoc_req(fc) || |
374 | ieee80211_is_reassoc_req(fc) || | |
375 | skb->protocol == cpu_to_be16(ETH_P_PAE))) | |
376 | tx_flags |= TX_CMD_FLG_IGNORE_BT; | |
74bcdb33 WYG |
377 | |
378 | ||
379 | tx_cmd->sta_id = std_id; | |
380 | if (ieee80211_has_morefrags(fc)) | |
381 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
382 | ||
383 | if (ieee80211_is_data_qos(fc)) { | |
384 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
385 | tx_cmd->tid_tspec = qc[0] & 0xf; | |
386 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
387 | } else { | |
388 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
389 | } | |
390 | ||
94597ab2 | 391 | priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags); |
74bcdb33 WYG |
392 | |
393 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
394 | if (ieee80211_is_mgmt(fc)) { | |
395 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
396 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); | |
397 | else | |
398 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
399 | } else { | |
400 | tx_cmd->timeout.pm_frame_timeout = 0; | |
401 | } | |
402 | ||
403 | tx_cmd->driver_txop = 0; | |
404 | tx_cmd->tx_flags = tx_flags; | |
405 | tx_cmd->next_frame_len = 0; | |
406 | } | |
407 | ||
408 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
409 | ||
410 | static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv, | |
411 | struct iwl_tx_cmd *tx_cmd, | |
412 | struct ieee80211_tx_info *info, | |
413 | __le16 fc) | |
414 | { | |
415 | u32 rate_flags; | |
416 | int rate_idx; | |
417 | u8 rts_retry_limit; | |
418 | u8 data_retry_limit; | |
419 | u8 rate_plcp; | |
420 | ||
421 | /* Set retry limit on DATA packets and Probe Responses*/ | |
422 | if (ieee80211_is_probe_resp(fc)) | |
423 | data_retry_limit = 3; | |
424 | else | |
b744cb79 | 425 | data_retry_limit = IWLAGN_DEFAULT_TX_RETRY; |
74bcdb33 WYG |
426 | tx_cmd->data_retry_limit = data_retry_limit; |
427 | ||
428 | /* Set retry limit on RTS packets */ | |
429 | rts_retry_limit = RTS_DFAULT_RETRY_LIMIT; | |
430 | if (data_retry_limit < rts_retry_limit) | |
431 | rts_retry_limit = data_retry_limit; | |
432 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
433 | ||
434 | /* DATA packets will use the uCode station table for rate/antenna | |
435 | * selection */ | |
436 | if (ieee80211_is_data(fc)) { | |
437 | tx_cmd->initial_rate_index = 0; | |
438 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
439 | return; | |
440 | } | |
441 | ||
442 | /** | |
443 | * If the current TX rate stored in mac80211 has the MCS bit set, it's | |
444 | * not really a TX rate. Thus, we use the lowest supported rate for | |
445 | * this band. Also use the lowest supported rate if the stored rate | |
446 | * index is invalid. | |
447 | */ | |
448 | rate_idx = info->control.rates[0].idx; | |
449 | if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS || | |
450 | (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY)) | |
451 | rate_idx = rate_lowest_index(&priv->bands[info->band], | |
452 | info->control.sta); | |
453 | /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ | |
454 | if (info->band == IEEE80211_BAND_5GHZ) | |
455 | rate_idx += IWL_FIRST_OFDM_RATE; | |
456 | /* Get PLCP rate for tx_cmd->rate_n_flags */ | |
457 | rate_plcp = iwl_rates[rate_idx].plcp; | |
458 | /* Zero out flags for this packet */ | |
459 | rate_flags = 0; | |
460 | ||
461 | /* Set CCK flag as needed */ | |
462 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
463 | rate_flags |= RATE_MCS_CCK_MSK; | |
464 | ||
74bcdb33 | 465 | /* Set up antennas */ |
7cb1b088 WYG |
466 | if (priv->cfg->bt_params && |
467 | priv->cfg->bt_params->advanced_bt_coexist && | |
468 | priv->bt_full_concurrent) { | |
bee008b7 WYG |
469 | /* operated as 1x1 in full concurrency mode */ |
470 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, | |
471 | first_antenna(priv->hw_params.valid_tx_ant)); | |
472 | } else | |
473 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, | |
0e1654fa | 474 | priv->hw_params.valid_tx_ant); |
74bcdb33 WYG |
475 | rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant); |
476 | ||
477 | /* Set the rate in the TX cmd */ | |
478 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); | |
479 | } | |
480 | ||
481 | static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
482 | struct ieee80211_tx_info *info, | |
483 | struct iwl_tx_cmd *tx_cmd, | |
484 | struct sk_buff *skb_frag, | |
485 | int sta_id) | |
486 | { | |
487 | struct ieee80211_key_conf *keyconf = info->control.hw_key; | |
488 | ||
97359d12 JB |
489 | switch (keyconf->cipher) { |
490 | case WLAN_CIPHER_SUITE_CCMP: | |
74bcdb33 WYG |
491 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; |
492 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); | |
493 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | |
494 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; | |
495 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); | |
496 | break; | |
497 | ||
97359d12 | 498 | case WLAN_CIPHER_SUITE_TKIP: |
74bcdb33 WYG |
499 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; |
500 | ieee80211_get_tkip_key(keyconf, skb_frag, | |
501 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); | |
502 | IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); | |
503 | break; | |
504 | ||
97359d12 JB |
505 | case WLAN_CIPHER_SUITE_WEP104: |
506 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
507 | /* fall through */ | |
508 | case WLAN_CIPHER_SUITE_WEP40: | |
74bcdb33 WYG |
509 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
510 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); | |
511 | ||
74bcdb33 WYG |
512 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); |
513 | ||
514 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " | |
515 | "with key %d\n", keyconf->keyidx); | |
516 | break; | |
517 | ||
518 | default: | |
97359d12 | 519 | IWL_ERR(priv, "Unknown encode cipher %x\n", keyconf->cipher); |
74bcdb33 WYG |
520 | break; |
521 | } | |
522 | } | |
523 | ||
524 | /* | |
525 | * start REPLY_TX command process | |
526 | */ | |
527 | int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |
528 | { | |
529 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
530 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
531 | struct ieee80211_sta *sta = info->control.sta; | |
532 | struct iwl_station_priv *sta_priv = NULL; | |
533 | struct iwl_tx_queue *txq; | |
534 | struct iwl_queue *q; | |
535 | struct iwl_device_cmd *out_cmd; | |
536 | struct iwl_cmd_meta *out_meta; | |
537 | struct iwl_tx_cmd *tx_cmd; | |
a194e324 | 538 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
8d56396a | 539 | int txq_id; |
74bcdb33 WYG |
540 | dma_addr_t phys_addr; |
541 | dma_addr_t txcmd_phys; | |
542 | dma_addr_t scratch_phys; | |
70f3876f | 543 | u16 len, firstlen, secondlen; |
74bcdb33 WYG |
544 | u16 seq_number = 0; |
545 | __le16 fc; | |
546 | u8 hdr_len; | |
547 | u8 sta_id; | |
548 | u8 wait_write_ptr = 0; | |
549 | u8 tid = 0; | |
550 | u8 *qc = NULL; | |
551 | unsigned long flags; | |
2e34034e | 552 | bool is_agg = false; |
74bcdb33 | 553 | |
9b9190d9 JB |
554 | /* |
555 | * If the frame needs to go out off-channel, then | |
556 | * we'll have put the PAN context to that channel, | |
557 | * so make the frame go out there. | |
558 | */ | |
559 | if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) | |
560 | ctx = &priv->contexts[IWL_RXON_CTX_PAN]; | |
561 | else if (info->control.vif) | |
a194e324 JB |
562 | ctx = iwl_rxon_ctx_from_vif(info->control.vif); |
563 | ||
74bcdb33 WYG |
564 | spin_lock_irqsave(&priv->lock, flags); |
565 | if (iwl_is_rfkill(priv)) { | |
566 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); | |
567 | goto drop_unlock; | |
568 | } | |
569 | ||
570 | fc = hdr->frame_control; | |
571 | ||
572 | #ifdef CONFIG_IWLWIFI_DEBUG | |
573 | if (ieee80211_is_auth(fc)) | |
574 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); | |
575 | else if (ieee80211_is_assoc_req(fc)) | |
576 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); | |
577 | else if (ieee80211_is_reassoc_req(fc)) | |
578 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); | |
579 | #endif | |
580 | ||
581 | hdr_len = ieee80211_hdrlen(fc); | |
582 | ||
2a87c26b | 583 | /* Find index into station table for destination station */ |
a194e324 | 584 | sta_id = iwl_sta_id_or_broadcast(priv, ctx, info->control.sta); |
74bcdb33 WYG |
585 | if (sta_id == IWL_INVALID_STATION) { |
586 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", | |
587 | hdr->addr1); | |
588 | goto drop_unlock; | |
589 | } | |
590 | ||
591 | IWL_DEBUG_TX(priv, "station Id %d\n", sta_id); | |
592 | ||
593 | if (sta) | |
594 | sta_priv = (void *)sta->drv_priv; | |
595 | ||
67158b67 JB |
596 | if (sta_priv && sta_priv->asleep && |
597 | (info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)) { | |
74bcdb33 WYG |
598 | /* |
599 | * This sends an asynchronous command to the device, | |
600 | * but we can rely on it being processed before the | |
601 | * next frame is processed -- and the next frame to | |
602 | * this station is the one that will consume this | |
603 | * counter. | |
604 | * For now set the counter to just 1 since we do not | |
605 | * support uAPSD yet. | |
606 | */ | |
607 | iwl_sta_modify_sleep_tx_count(priv, sta_id, 1); | |
608 | } | |
609 | ||
e72f368b JB |
610 | /* |
611 | * Send this frame after DTIM -- there's a special queue | |
612 | * reserved for this for contexts that support AP mode. | |
613 | */ | |
614 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { | |
615 | txq_id = ctx->mcast_queue; | |
616 | /* | |
617 | * The microcode will clear the more data | |
618 | * bit in the last frame it transmits. | |
619 | */ | |
620 | hdr->frame_control |= | |
621 | cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
622 | } else | |
623 | txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)]; | |
9c5ac091 RC |
624 | |
625 | /* irqs already disabled/saved above when locking priv->lock */ | |
626 | spin_lock(&priv->sta_lock); | |
627 | ||
74bcdb33 WYG |
628 | if (ieee80211_is_data_qos(fc)) { |
629 | qc = ieee80211_get_qos_ctl(hdr); | |
630 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; | |
9c5ac091 RC |
631 | if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) { |
632 | spin_unlock(&priv->sta_lock); | |
74bcdb33 | 633 | goto drop_unlock; |
9c5ac091 | 634 | } |
74bcdb33 WYG |
635 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
636 | seq_number &= IEEE80211_SCTL_SEQ; | |
637 | hdr->seq_ctrl = hdr->seq_ctrl & | |
638 | cpu_to_le16(IEEE80211_SCTL_FRAG); | |
639 | hdr->seq_ctrl |= cpu_to_le16(seq_number); | |
640 | seq_number += 0x10; | |
641 | /* aggregation is on for this <sta,tid> */ | |
642 | if (info->flags & IEEE80211_TX_CTL_AMPDU && | |
643 | priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) { | |
644 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; | |
2e34034e | 645 | is_agg = true; |
74bcdb33 WYG |
646 | } |
647 | } | |
648 | ||
649 | txq = &priv->txq[txq_id]; | |
74bcdb33 WYG |
650 | q = &txq->q; |
651 | ||
9c5ac091 RC |
652 | if (unlikely(iwl_queue_space(q) < q->high_mark)) { |
653 | spin_unlock(&priv->sta_lock); | |
74bcdb33 | 654 | goto drop_unlock; |
9c5ac091 | 655 | } |
74bcdb33 | 656 | |
9c5ac091 | 657 | if (ieee80211_is_data_qos(fc)) { |
74bcdb33 | 658 | priv->stations[sta_id].tid[tid].tfds_in_queue++; |
9c5ac091 RC |
659 | if (!ieee80211_has_morefrags(fc)) |
660 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
661 | } | |
662 | ||
663 | spin_unlock(&priv->sta_lock); | |
74bcdb33 WYG |
664 | |
665 | /* Set up driver data for this TFD */ | |
666 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
ff0d91c3 | 667 | txq->txb[q->write_ptr].skb = skb; |
c90cbbbd | 668 | txq->txb[q->write_ptr].ctx = ctx; |
74bcdb33 WYG |
669 | |
670 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
671 | out_cmd = txq->cmd[q->write_ptr]; | |
672 | out_meta = &txq->meta[q->write_ptr]; | |
673 | tx_cmd = &out_cmd->cmd.tx; | |
674 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
675 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
676 | ||
677 | /* | |
678 | * Set up the Tx-command (not MAC!) header. | |
679 | * Store the chosen Tx queue and TFD index within the sequence field; | |
680 | * after Tx, uCode's Tx response will return this value so driver can | |
681 | * locate the frame within the tx queue and do post-tx processing. | |
682 | */ | |
683 | out_cmd->hdr.cmd = REPLY_TX; | |
684 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
685 | INDEX_TO_SEQ(q->write_ptr))); | |
686 | ||
687 | /* Copy MAC header from skb into command buffer */ | |
688 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
689 | ||
690 | ||
691 | /* Total # bytes to be transmitted */ | |
692 | len = (u16)skb->len; | |
693 | tx_cmd->len = cpu_to_le16(len); | |
694 | ||
695 | if (info->control.hw_key) | |
696 | iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); | |
697 | ||
698 | /* TODO need this for burst mode later on */ | |
d44ae69e | 699 | iwlagn_tx_cmd_build_basic(priv, skb, tx_cmd, info, hdr, sta_id); |
74bcdb33 WYG |
700 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
701 | ||
702 | iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc); | |
703 | ||
704 | iwl_update_stats(priv, true, fc, len); | |
705 | /* | |
706 | * Use the first empty entry in this queue's command buffer array | |
707 | * to contain the Tx command and MAC header concatenated together | |
708 | * (payload data will be in another buffer). | |
709 | * Size of this varies, due to varying MAC header length. | |
710 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
711 | * of the MAC header (device reads on dword boundaries). | |
712 | * We'll tell device about this padding later. | |
713 | */ | |
714 | len = sizeof(struct iwl_tx_cmd) + | |
715 | sizeof(struct iwl_cmd_header) + hdr_len; | |
70f3876f | 716 | firstlen = (len + 3) & ~3; |
74bcdb33 WYG |
717 | |
718 | /* Tell NIC about any 2-byte padding after MAC header */ | |
70f3876f | 719 | if (firstlen != len) |
74bcdb33 WYG |
720 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
721 | ||
722 | /* Physical address of this Tx command's header (not MAC header!), | |
723 | * within command buffer array. */ | |
724 | txcmd_phys = pci_map_single(priv->pci_dev, | |
70f3876f | 725 | &out_cmd->hdr, firstlen, |
74bcdb33 | 726 | PCI_DMA_BIDIRECTIONAL); |
2e724443 | 727 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
70f3876f | 728 | dma_unmap_len_set(out_meta, len, firstlen); |
74bcdb33 WYG |
729 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
730 | * first entry */ | |
731 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, | |
70f3876f | 732 | txcmd_phys, firstlen, 1, 0); |
74bcdb33 WYG |
733 | |
734 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
735 | txq->need_update = 1; | |
74bcdb33 WYG |
736 | } else { |
737 | wait_write_ptr = 1; | |
738 | txq->need_update = 0; | |
739 | } | |
740 | ||
741 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
742 | * if any (802.11 null frames have no payload). */ | |
70f3876f SG |
743 | secondlen = skb->len - hdr_len; |
744 | if (secondlen > 0) { | |
74bcdb33 | 745 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, |
70f3876f | 746 | secondlen, PCI_DMA_TODEVICE); |
74bcdb33 | 747 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
70f3876f | 748 | phys_addr, secondlen, |
74bcdb33 WYG |
749 | 0, 0); |
750 | } | |
751 | ||
752 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
753 | offsetof(struct iwl_tx_cmd, scratch); | |
754 | ||
74bcdb33 WYG |
755 | /* take back ownership of DMA buffer to enable update */ |
756 | pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys, | |
70f3876f | 757 | firstlen, PCI_DMA_BIDIRECTIONAL); |
74bcdb33 WYG |
758 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
759 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
760 | ||
91dd6c27 | 761 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n", |
74bcdb33 | 762 | le16_to_cpu(out_cmd->hdr.sequence)); |
91dd6c27 | 763 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
74bcdb33 WYG |
764 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); |
765 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
766 | ||
767 | /* Set up entry for this TFD in Tx byte-count array */ | |
768 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | |
94b00658 JB |
769 | iwlagn_txq_update_byte_cnt_tbl(priv, txq, |
770 | le16_to_cpu(tx_cmd->len)); | |
74bcdb33 WYG |
771 | |
772 | pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys, | |
70f3876f | 773 | firstlen, PCI_DMA_BIDIRECTIONAL); |
74bcdb33 WYG |
774 | |
775 | trace_iwlwifi_dev_tx(priv, | |
776 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], | |
777 | sizeof(struct iwl_tfd), | |
778 | &out_cmd->hdr, firstlen, | |
779 | skb->data + hdr_len, secondlen); | |
780 | ||
781 | /* Tell device the write index *just past* this latest filled TFD */ | |
782 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
783 | iwl_txq_update_write_ptr(priv, txq); | |
784 | spin_unlock_irqrestore(&priv->lock, flags); | |
785 | ||
786 | /* | |
787 | * At this point the frame is "transmitted" successfully | |
788 | * and we will get a TX status notification eventually, | |
789 | * regardless of the value of ret. "ret" only indicates | |
790 | * whether or not we should update the write pointer. | |
791 | */ | |
792 | ||
2e34034e JB |
793 | /* |
794 | * Avoid atomic ops if it isn't an associated client. | |
795 | * Also, if this is a packet for aggregation, don't | |
796 | * increase the counter because the ucode will stop | |
797 | * aggregation queues when their respective station | |
798 | * goes to sleep. | |
799 | */ | |
800 | if (sta_priv && sta_priv->client && !is_agg) | |
74bcdb33 WYG |
801 | atomic_inc(&sta_priv->pending_frames); |
802 | ||
803 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { | |
804 | if (wait_write_ptr) { | |
805 | spin_lock_irqsave(&priv->lock, flags); | |
806 | txq->need_update = 1; | |
807 | iwl_txq_update_write_ptr(priv, txq); | |
808 | spin_unlock_irqrestore(&priv->lock, flags); | |
809 | } else { | |
549a04e0 | 810 | iwl_stop_queue(priv, txq); |
74bcdb33 WYG |
811 | } |
812 | } | |
813 | ||
814 | return 0; | |
815 | ||
816 | drop_unlock: | |
817 | spin_unlock_irqrestore(&priv->lock, flags); | |
818 | return -1; | |
819 | } | |
820 | ||
821 | static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv, | |
822 | struct iwl_dma_ptr *ptr, size_t size) | |
823 | { | |
824 | ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma, | |
825 | GFP_KERNEL); | |
826 | if (!ptr->addr) | |
827 | return -ENOMEM; | |
828 | ptr->size = size; | |
829 | return 0; | |
830 | } | |
831 | ||
832 | static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv, | |
833 | struct iwl_dma_ptr *ptr) | |
834 | { | |
835 | if (unlikely(!ptr->addr)) | |
836 | return; | |
837 | ||
838 | dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma); | |
839 | memset(ptr, 0, sizeof(*ptr)); | |
840 | } | |
841 | ||
842 | /** | |
843 | * iwlagn_hw_txq_ctx_free - Free TXQ Context | |
844 | * | |
845 | * Destroy all TX DMA queues and structures | |
846 | */ | |
847 | void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv) | |
848 | { | |
849 | int txq_id; | |
850 | ||
851 | /* Tx queues */ | |
852 | if (priv->txq) { | |
470058e0 | 853 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) |
13bb9483 | 854 | if (txq_id == priv->cmd_queue) |
74bcdb33 WYG |
855 | iwl_cmd_queue_free(priv); |
856 | else | |
857 | iwl_tx_queue_free(priv, txq_id); | |
858 | } | |
859 | iwlagn_free_dma_ptr(priv, &priv->kw); | |
860 | ||
861 | iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
862 | ||
863 | /* free tx queue structure */ | |
864 | iwl_free_txq_mem(priv); | |
865 | } | |
866 | ||
867 | /** | |
470058e0 ZY |
868 | * iwlagn_txq_ctx_alloc - allocate TX queue context |
869 | * Allocate all Tx DMA structures and initialize them | |
74bcdb33 WYG |
870 | * |
871 | * @param priv | |
872 | * @return error code | |
873 | */ | |
470058e0 | 874 | int iwlagn_txq_ctx_alloc(struct iwl_priv *priv) |
74bcdb33 | 875 | { |
470058e0 | 876 | int ret; |
74bcdb33 WYG |
877 | int txq_id, slots_num; |
878 | unsigned long flags; | |
879 | ||
880 | /* Free all tx/cmd queues and keep-warm buffer */ | |
881 | iwlagn_hw_txq_ctx_free(priv); | |
882 | ||
883 | ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls, | |
884 | priv->hw_params.scd_bc_tbls_size); | |
885 | if (ret) { | |
886 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); | |
887 | goto error_bc_tbls; | |
888 | } | |
889 | /* Alloc keep-warm buffer */ | |
890 | ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); | |
891 | if (ret) { | |
892 | IWL_ERR(priv, "Keep Warm allocation failed\n"); | |
893 | goto error_kw; | |
894 | } | |
895 | ||
896 | /* allocate tx queue structure */ | |
897 | ret = iwl_alloc_txq_mem(priv); | |
898 | if (ret) | |
899 | goto error; | |
900 | ||
901 | spin_lock_irqsave(&priv->lock, flags); | |
902 | ||
903 | /* Turn off all Tx DMA fifos */ | |
904 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
905 | ||
906 | /* Tell NIC where to find the "keep warm" buffer */ | |
907 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
908 | ||
909 | spin_unlock_irqrestore(&priv->lock, flags); | |
910 | ||
13bb9483 | 911 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ |
74bcdb33 | 912 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
13bb9483 | 913 | slots_num = (txq_id == priv->cmd_queue) ? |
74bcdb33 WYG |
914 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
915 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
916 | txq_id); | |
917 | if (ret) { | |
918 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); | |
919 | goto error; | |
920 | } | |
921 | } | |
922 | ||
923 | return ret; | |
924 | ||
925 | error: | |
926 | iwlagn_hw_txq_ctx_free(priv); | |
927 | iwlagn_free_dma_ptr(priv, &priv->kw); | |
928 | error_kw: | |
929 | iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
930 | error_bc_tbls: | |
931 | return ret; | |
932 | } | |
933 | ||
470058e0 ZY |
934 | void iwlagn_txq_ctx_reset(struct iwl_priv *priv) |
935 | { | |
936 | int txq_id, slots_num; | |
937 | unsigned long flags; | |
938 | ||
939 | spin_lock_irqsave(&priv->lock, flags); | |
940 | ||
941 | /* Turn off all Tx DMA fifos */ | |
942 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
943 | ||
944 | /* Tell NIC where to find the "keep warm" buffer */ | |
945 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
946 | ||
947 | spin_unlock_irqrestore(&priv->lock, flags); | |
948 | ||
949 | /* Alloc and init all Tx queues, including the command queue (#4) */ | |
950 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { | |
13bb9483 | 951 | slots_num = txq_id == priv->cmd_queue ? |
470058e0 ZY |
952 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
953 | iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id); | |
954 | } | |
955 | } | |
956 | ||
74bcdb33 | 957 | /** |
470058e0 | 958 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels |
74bcdb33 WYG |
959 | */ |
960 | void iwlagn_txq_ctx_stop(struct iwl_priv *priv) | |
961 | { | |
387f3381 | 962 | int ch, txq_id; |
74bcdb33 WYG |
963 | unsigned long flags; |
964 | ||
965 | /* Turn off all Tx DMA fifos */ | |
966 | spin_lock_irqsave(&priv->lock, flags); | |
967 | ||
968 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
969 | ||
970 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
971 | for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) { | |
972 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
9726f347 | 973 | if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, |
74bcdb33 | 974 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
9726f347 EG |
975 | 1000)) |
976 | IWL_ERR(priv, "Failing on timeout while stopping" | |
977 | " DMA channel %d [0x%08x]", ch, | |
978 | iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG)); | |
74bcdb33 WYG |
979 | } |
980 | spin_unlock_irqrestore(&priv->lock, flags); | |
387f3381 SG |
981 | |
982 | if (!priv->txq) | |
983 | return; | |
984 | ||
985 | /* Unmap DMA from host system and free skb's */ | |
986 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
987 | if (txq_id == priv->cmd_queue) | |
988 | iwl_cmd_queue_unmap(priv); | |
989 | else | |
990 | iwl_tx_queue_unmap(priv, txq_id); | |
74bcdb33 WYG |
991 | } |
992 | ||
993 | /* | |
994 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
995 | * Called only when finding queue for aggregation. | |
996 | * Should never return anything < 7, because they should already | |
997 | * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) | |
998 | */ | |
999 | static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv) | |
1000 | { | |
1001 | int txq_id; | |
1002 | ||
1003 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
1004 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
1005 | return txq_id; | |
1006 | return -1; | |
1007 | } | |
1008 | ||
832f47e3 | 1009 | int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif, |
619753ff | 1010 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
74bcdb33 WYG |
1011 | { |
1012 | int sta_id; | |
1013 | int tx_fifo; | |
1014 | int txq_id; | |
1015 | int ret; | |
1016 | unsigned long flags; | |
1017 | struct iwl_tid_data *tid_data; | |
1018 | ||
e72f368b | 1019 | tx_fifo = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid); |
74bcdb33 WYG |
1020 | if (unlikely(tx_fifo < 0)) |
1021 | return tx_fifo; | |
1022 | ||
1023 | IWL_WARN(priv, "%s on ra = %pM tid = %d\n", | |
619753ff | 1024 | __func__, sta->addr, tid); |
74bcdb33 | 1025 | |
619753ff | 1026 | sta_id = iwl_sta_id(sta); |
74bcdb33 WYG |
1027 | if (sta_id == IWL_INVALID_STATION) { |
1028 | IWL_ERR(priv, "Start AGG on invalid station\n"); | |
1029 | return -ENXIO; | |
1030 | } | |
1031 | if (unlikely(tid >= MAX_TID_COUNT)) | |
1032 | return -EINVAL; | |
1033 | ||
1034 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
1035 | IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n"); | |
1036 | return -ENXIO; | |
1037 | } | |
1038 | ||
1039 | txq_id = iwlagn_txq_ctx_activate_free(priv); | |
1040 | if (txq_id == -1) { | |
1041 | IWL_ERR(priv, "No free aggregation queue available\n"); | |
1042 | return -ENXIO; | |
1043 | } | |
1044 | ||
1045 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1046 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1047 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1048 | tid_data->agg.txq_id = txq_id; | |
c8823ec1 | 1049 | tid_data->agg.tx_fifo = tx_fifo; |
ea9b307f | 1050 | iwl_set_swq_id(&priv->txq[txq_id], get_ac_from_tid(tid), txq_id); |
74bcdb33 WYG |
1051 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
1052 | ||
c8823ec1 | 1053 | ret = iwlagn_txq_agg_enable(priv, txq_id, sta_id, tid); |
74bcdb33 WYG |
1054 | if (ret) |
1055 | return ret; | |
1056 | ||
9c5ac091 RC |
1057 | spin_lock_irqsave(&priv->sta_lock, flags); |
1058 | tid_data = &priv->stations[sta_id].tid[tid]; | |
74bcdb33 WYG |
1059 | if (tid_data->tfds_in_queue == 0) { |
1060 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); | |
1061 | tid_data->agg.state = IWL_AGG_ON; | |
619753ff | 1062 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
74bcdb33 WYG |
1063 | } else { |
1064 | IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n", | |
1065 | tid_data->tfds_in_queue); | |
1066 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1067 | } | |
9c5ac091 | 1068 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
74bcdb33 WYG |
1069 | return ret; |
1070 | } | |
1071 | ||
832f47e3 | 1072 | int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif, |
619753ff | 1073 | struct ieee80211_sta *sta, u16 tid) |
74bcdb33 | 1074 | { |
18c121d7 | 1075 | int tx_fifo_id, txq_id, sta_id, ssn; |
74bcdb33 WYG |
1076 | struct iwl_tid_data *tid_data; |
1077 | int write_ptr, read_ptr; | |
1078 | unsigned long flags; | |
1079 | ||
e72f368b | 1080 | tx_fifo_id = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid); |
74bcdb33 WYG |
1081 | if (unlikely(tx_fifo_id < 0)) |
1082 | return tx_fifo_id; | |
1083 | ||
619753ff | 1084 | sta_id = iwl_sta_id(sta); |
74bcdb33 WYG |
1085 | |
1086 | if (sta_id == IWL_INVALID_STATION) { | |
1087 | IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid); | |
1088 | return -ENXIO; | |
1089 | } | |
1090 | ||
9c5ac091 RC |
1091 | spin_lock_irqsave(&priv->sta_lock, flags); |
1092 | ||
74bcdb33 WYG |
1093 | tid_data = &priv->stations[sta_id].tid[tid]; |
1094 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1095 | txq_id = tid_data->agg.txq_id; | |
18c121d7 JB |
1096 | |
1097 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1098 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1099 | /* | |
1100 | * This can happen if the peer stops aggregation | |
1101 | * again before we've had a chance to drain the | |
1102 | * queue we selected previously, i.e. before the | |
1103 | * session was really started completely. | |
1104 | */ | |
1105 | IWL_DEBUG_HT(priv, "AGG stop before setup done\n"); | |
1106 | goto turn_off; | |
1107 | case IWL_AGG_ON: | |
1108 | break; | |
1109 | default: | |
1110 | IWL_WARN(priv, "Stopping AGG while state not ON or starting\n"); | |
1111 | } | |
1112 | ||
74bcdb33 WYG |
1113 | write_ptr = priv->txq[txq_id].q.write_ptr; |
1114 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1115 | ||
1116 | /* The queue is not empty */ | |
1117 | if (write_ptr != read_ptr) { | |
1118 | IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n"); | |
1119 | priv->stations[sta_id].tid[tid].agg.state = | |
1120 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
9c5ac091 | 1121 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
74bcdb33 WYG |
1122 | return 0; |
1123 | } | |
1124 | ||
1125 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); | |
18c121d7 | 1126 | turn_off: |
74bcdb33 WYG |
1127 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1128 | ||
9c5ac091 RC |
1129 | /* do not restore/save irqs */ |
1130 | spin_unlock(&priv->sta_lock); | |
1131 | spin_lock(&priv->lock); | |
1132 | ||
74bcdb33 WYG |
1133 | /* |
1134 | * the only reason this call can fail is queue number out of range, | |
1135 | * which can happen if uCode is reloaded and all the station | |
1136 | * information are lost. if it is outside the range, there is no need | |
1137 | * to deactivate the uCode queue, just return "success" to allow | |
1138 | * mac80211 to clean up it own data. | |
1139 | */ | |
7ffef13d | 1140 | iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo_id); |
74bcdb33 WYG |
1141 | spin_unlock_irqrestore(&priv->lock, flags); |
1142 | ||
619753ff | 1143 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
74bcdb33 WYG |
1144 | |
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | int iwlagn_txq_check_empty(struct iwl_priv *priv, | |
1149 | int sta_id, u8 tid, int txq_id) | |
1150 | { | |
1151 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1152 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1153 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
8bd413e6 JB |
1154 | struct iwl_rxon_context *ctx; |
1155 | ||
1156 | ctx = &priv->contexts[priv->stations[sta_id].ctxid]; | |
74bcdb33 | 1157 | |
a24d52f3 | 1158 | lockdep_assert_held(&priv->sta_lock); |
9c5ac091 | 1159 | |
74bcdb33 WYG |
1160 | switch (priv->stations[sta_id].tid[tid].agg.state) { |
1161 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1162 | /* We are reclaiming the last packet of the */ | |
1163 | /* aggregated HW queue */ | |
1164 | if ((txq_id == tid_data->agg.txq_id) && | |
1165 | (q->read_ptr == q->write_ptr)) { | |
1166 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); | |
e72f368b | 1167 | int tx_fifo = get_fifo_from_tid(ctx, tid); |
74bcdb33 | 1168 | IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n"); |
7ffef13d | 1169 | iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo); |
74bcdb33 | 1170 | tid_data->agg.state = IWL_AGG_OFF; |
8bd413e6 | 1171 | ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid); |
74bcdb33 WYG |
1172 | } |
1173 | break; | |
1174 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1175 | /* We are reclaiming the last packet of the queue */ | |
1176 | if (tid_data->tfds_in_queue == 0) { | |
1177 | IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n"); | |
1178 | tid_data->agg.state = IWL_AGG_ON; | |
8bd413e6 | 1179 | ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid); |
74bcdb33 WYG |
1180 | } |
1181 | break; | |
1182 | } | |
9c5ac091 | 1183 | |
74bcdb33 WYG |
1184 | return 0; |
1185 | } | |
1186 | ||
2e34034e JB |
1187 | static void iwlagn_non_agg_tx_status(struct iwl_priv *priv, |
1188 | struct iwl_rxon_context *ctx, | |
1189 | const u8 *addr1) | |
74bcdb33 | 1190 | { |
74bcdb33 WYG |
1191 | struct ieee80211_sta *sta; |
1192 | struct iwl_station_priv *sta_priv; | |
1193 | ||
6db6340c | 1194 | rcu_read_lock(); |
2e34034e | 1195 | sta = ieee80211_find_sta(ctx->vif, addr1); |
74bcdb33 WYG |
1196 | if (sta) { |
1197 | sta_priv = (void *)sta->drv_priv; | |
1198 | /* avoid atomic ops if this isn't a client */ | |
1199 | if (sta_priv->client && | |
1200 | atomic_dec_return(&sta_priv->pending_frames) == 0) | |
1201 | ieee80211_sta_block_awake(priv->hw, sta, false); | |
1202 | } | |
6db6340c | 1203 | rcu_read_unlock(); |
2e34034e JB |
1204 | } |
1205 | ||
1206 | static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info, | |
1207 | bool is_agg) | |
1208 | { | |
1209 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data; | |
1210 | ||
1211 | if (!is_agg) | |
1212 | iwlagn_non_agg_tx_status(priv, tx_info->ctx, hdr->addr1); | |
74bcdb33 | 1213 | |
8bd413e6 | 1214 | ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb); |
74bcdb33 WYG |
1215 | } |
1216 | ||
1217 | int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) | |
1218 | { | |
1219 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1220 | struct iwl_queue *q = &txq->q; | |
1221 | struct iwl_tx_info *tx_info; | |
1222 | int nfreed = 0; | |
1223 | struct ieee80211_hdr *hdr; | |
1224 | ||
1225 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
1226 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " | |
1227 | "is out of range [0-%d] %d %d.\n", txq_id, | |
1228 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | for (index = iwl_queue_inc_wrap(index, q->n_bd); | |
1233 | q->read_ptr != index; | |
1234 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1235 | ||
1236 | tx_info = &txq->txb[txq->q.read_ptr]; | |
b2502698 SG |
1237 | |
1238 | if (WARN_ON_ONCE(tx_info->skb == NULL)) | |
1239 | continue; | |
74bcdb33 | 1240 | |
ff0d91c3 | 1241 | hdr = (struct ieee80211_hdr *)tx_info->skb->data; |
b2502698 | 1242 | if (ieee80211_is_data_qos(hdr->frame_control)) |
74bcdb33 | 1243 | nfreed++; |
b2502698 SG |
1244 | |
1245 | iwlagn_tx_status(priv, tx_info, | |
1246 | txq_id >= IWLAGN_FIRST_AMPDU_QUEUE); | |
ff0d91c3 | 1247 | tx_info->skb = NULL; |
74bcdb33 | 1248 | |
94b00658 | 1249 | iwlagn_txq_inval_byte_cnt_tbl(priv, txq); |
74bcdb33 WYG |
1250 | |
1251 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); | |
1252 | } | |
1253 | return nfreed; | |
1254 | } | |
1255 | ||
1256 | /** | |
1257 | * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack | |
1258 | * | |
1259 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
1260 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
1261 | */ | |
1262 | static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |
1263 | struct iwl_ht_agg *agg, | |
1264 | struct iwl_compressed_ba_resp *ba_resp) | |
1265 | ||
1266 | { | |
d0eb6334 | 1267 | int sh; |
74bcdb33 WYG |
1268 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); |
1269 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
74bcdb33 | 1270 | struct ieee80211_tx_info *info; |
d0eb6334 | 1271 | u64 bitmap, sent_bitmap; |
74bcdb33 WYG |
1272 | |
1273 | if (unlikely(!agg->wait_for_ba)) { | |
822395b5 DF |
1274 | if (unlikely(ba_resp->bitmap)) |
1275 | IWL_ERR(priv, "Received BA when not expected\n"); | |
74bcdb33 WYG |
1276 | return -EINVAL; |
1277 | } | |
1278 | ||
1279 | /* Mark that the expected block-ack response arrived */ | |
1280 | agg->wait_for_ba = 0; | |
1281 | IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); | |
1282 | ||
1283 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
1284 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4); | |
d0eb6334 | 1285 | if (sh < 0) |
74bcdb33 WYG |
1286 | sh += 0x100; |
1287 | ||
d0eb6334 DH |
1288 | /* |
1289 | * Check for success or failure according to the | |
1290 | * transmitted bitmap and block-ack bitmap | |
1291 | */ | |
1292 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
1293 | sent_bitmap = bitmap & agg->bitmap; | |
1294 | ||
1295 | /* Sanity check values reported by uCode */ | |
1296 | if (ba_resp->txed_2_done > ba_resp->txed) { | |
1297 | IWL_DEBUG_TX_REPLY(priv, | |
1298 | "bogus sent(%d) and ack(%d) count\n", | |
1299 | ba_resp->txed, ba_resp->txed_2_done); | |
8829c9e2 | 1300 | /* |
d0eb6334 DH |
1301 | * set txed_2_done = txed, |
1302 | * so it won't impact rate scale | |
8829c9e2 | 1303 | */ |
d0eb6334 DH |
1304 | ba_resp->txed = ba_resp->txed_2_done; |
1305 | } | |
1306 | IWL_DEBUG_HT(priv, "agg frames sent:%d, acked:%d\n", | |
1307 | ba_resp->txed, ba_resp->txed_2_done); | |
9decde95 | 1308 | |
d0eb6334 DH |
1309 | /* Find the first ACKed frame to store the TX status */ |
1310 | while (sent_bitmap && !(sent_bitmap & 1)) { | |
1311 | agg->start_idx = (agg->start_idx + 1) & 0xff; | |
1312 | sent_bitmap >>= 1; | |
74bcdb33 | 1313 | } |
9decde95 | 1314 | |
ff0d91c3 | 1315 | info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb); |
74bcdb33 WYG |
1316 | memset(&info->status, 0, sizeof(info->status)); |
1317 | info->flags |= IEEE80211_TX_STAT_ACK; | |
1318 | info->flags |= IEEE80211_TX_STAT_AMPDU; | |
d0eb6334 DH |
1319 | info->status.ampdu_ack_len = ba_resp->txed_2_done; |
1320 | info->status.ampdu_len = ba_resp->txed; | |
8d801080 | 1321 | iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info); |
74bcdb33 | 1322 | |
74bcdb33 WYG |
1323 | return 0; |
1324 | } | |
1325 | ||
8d801080 WYG |
1326 | /** |
1327 | * translate ucode response to mac80211 tx status control values | |
1328 | */ | |
1329 | void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags, | |
1330 | struct ieee80211_tx_info *info) | |
1331 | { | |
1332 | struct ieee80211_tx_rate *r = &info->control.rates[0]; | |
1333 | ||
1334 | info->antenna_sel_tx = | |
1335 | ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); | |
1336 | if (rate_n_flags & RATE_MCS_HT_MSK) | |
1337 | r->flags |= IEEE80211_TX_RC_MCS; | |
1338 | if (rate_n_flags & RATE_MCS_GF_MSK) | |
1339 | r->flags |= IEEE80211_TX_RC_GREEN_FIELD; | |
1340 | if (rate_n_flags & RATE_MCS_HT40_MSK) | |
1341 | r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; | |
1342 | if (rate_n_flags & RATE_MCS_DUP_MSK) | |
1343 | r->flags |= IEEE80211_TX_RC_DUP_DATA; | |
1344 | if (rate_n_flags & RATE_MCS_SGI_MSK) | |
1345 | r->flags |= IEEE80211_TX_RC_SHORT_GI; | |
1346 | r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band); | |
1347 | } | |
1348 | ||
74bcdb33 WYG |
1349 | /** |
1350 | * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
1351 | * | |
1352 | * Handles block-acknowledge notification from device, which reports success | |
1353 | * of frames sent via aggregation. | |
1354 | */ | |
1355 | void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv, | |
1356 | struct iwl_rx_mem_buffer *rxb) | |
1357 | { | |
1358 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1359 | struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; | |
1360 | struct iwl_tx_queue *txq = NULL; | |
1361 | struct iwl_ht_agg *agg; | |
1362 | int index; | |
1363 | int sta_id; | |
1364 | int tid; | |
9c5ac091 | 1365 | unsigned long flags; |
74bcdb33 WYG |
1366 | |
1367 | /* "flow" corresponds to Tx queue */ | |
1368 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1369 | ||
1370 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
1371 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
1372 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
1373 | ||
1374 | if (scd_flow >= priv->hw_params.max_txq_num) { | |
1375 | IWL_ERR(priv, | |
1376 | "BUG_ON scd_flow is bigger than number of queues\n"); | |
1377 | return; | |
1378 | } | |
1379 | ||
1380 | txq = &priv->txq[scd_flow]; | |
1381 | sta_id = ba_resp->sta_id; | |
1382 | tid = ba_resp->tid; | |
1383 | agg = &priv->stations[sta_id].tid[tid].agg; | |
b561e827 | 1384 | if (unlikely(agg->txq_id != scd_flow)) { |
735df29a WYG |
1385 | /* |
1386 | * FIXME: this is a uCode bug which need to be addressed, | |
1387 | * log the information and return for now! | |
1388 | * since it is possible happen very often and in order | |
1389 | * not to fill the syslog, don't enable the logging by default | |
1390 | */ | |
1391 | IWL_DEBUG_TX_REPLY(priv, | |
1392 | "BA scd_flow %d does not match txq_id %d\n", | |
b561e827 SZ |
1393 | scd_flow, agg->txq_id); |
1394 | return; | |
1395 | } | |
74bcdb33 WYG |
1396 | |
1397 | /* Find index just before block-ack window */ | |
1398 | index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
1399 | ||
9c5ac091 | 1400 | spin_lock_irqsave(&priv->sta_lock, flags); |
74bcdb33 WYG |
1401 | |
1402 | IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, " | |
1403 | "sta_id = %d\n", | |
1404 | agg->wait_for_ba, | |
1405 | (u8 *) &ba_resp->sta_addr_lo32, | |
1406 | ba_resp->sta_id); | |
1407 | IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " | |
1408 | "%d, scd_ssn = %d\n", | |
1409 | ba_resp->tid, | |
1410 | ba_resp->seq_ctl, | |
1411 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
1412 | ba_resp->scd_flow, | |
1413 | ba_resp->scd_ssn); | |
91dd6c27 | 1414 | IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n", |
74bcdb33 WYG |
1415 | agg->start_idx, |
1416 | (unsigned long long)agg->bitmap); | |
1417 | ||
1418 | /* Update driver's record of ACK vs. not for each frame in window */ | |
1419 | iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp); | |
1420 | ||
1421 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
1422 | * block-ack window (we assume that they've been successfully | |
1423 | * transmitted ... if not, it's too late anyway). */ | |
1424 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
1425 | /* calculate mac80211 ampdu sw queue to wake */ | |
1426 | int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index); | |
1427 | iwl_free_tfds_in_queue(priv, sta_id, tid, freed); | |
1428 | ||
1429 | if ((iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1430 | priv->mac80211_registered && | |
1431 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) | |
549a04e0 | 1432 | iwl_wake_queue(priv, txq); |
74bcdb33 WYG |
1433 | |
1434 | iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow); | |
1435 | } | |
9c5ac091 RC |
1436 | |
1437 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
74bcdb33 | 1438 | } |
69fdb710 JB |
1439 | |
1440 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1441 | const char *iwl_get_tx_fail_reason(u32 status) | |
1442 | { | |
1443 | #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x | |
1444 | #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x | |
1445 | ||
1446 | switch (status & TX_STATUS_MSK) { | |
1447 | case TX_STATUS_SUCCESS: | |
1448 | return "SUCCESS"; | |
1449 | TX_STATUS_POSTPONE(DELAY); | |
1450 | TX_STATUS_POSTPONE(FEW_BYTES); | |
1451 | TX_STATUS_POSTPONE(BT_PRIO); | |
1452 | TX_STATUS_POSTPONE(QUIET_PERIOD); | |
1453 | TX_STATUS_POSTPONE(CALC_TTAK); | |
1454 | TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY); | |
1455 | TX_STATUS_FAIL(SHORT_LIMIT); | |
1456 | TX_STATUS_FAIL(LONG_LIMIT); | |
1457 | TX_STATUS_FAIL(FIFO_UNDERRUN); | |
1458 | TX_STATUS_FAIL(DRAIN_FLOW); | |
1459 | TX_STATUS_FAIL(RFKILL_FLUSH); | |
1460 | TX_STATUS_FAIL(LIFE_EXPIRE); | |
1461 | TX_STATUS_FAIL(DEST_PS); | |
1462 | TX_STATUS_FAIL(HOST_ABORTED); | |
1463 | TX_STATUS_FAIL(BT_RETRY); | |
1464 | TX_STATUS_FAIL(STA_INVALID); | |
1465 | TX_STATUS_FAIL(FRAG_DROPPED); | |
1466 | TX_STATUS_FAIL(TID_DISABLE); | |
1467 | TX_STATUS_FAIL(FIFO_FLUSHED); | |
1468 | TX_STATUS_FAIL(INSUFFICIENT_CF_POLL); | |
1469 | TX_STATUS_FAIL(PASSIVE_NO_RX); | |
1470 | TX_STATUS_FAIL(NO_BEACON_ON_RADAR); | |
1471 | } | |
1472 | ||
1473 | return "UNKNOWN"; | |
1474 | ||
1475 | #undef TX_STATUS_FAIL | |
1476 | #undef TX_STATUS_POSTPONE | |
1477 | } | |
1478 | #endif /* CONFIG_IWLWIFI_DEBUG */ |