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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2002 Intersil Americas Inc. |
3 | * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org> | |
4 | * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | * | |
19 | */ | |
20 | ||
1da177e4 | 21 | #include <linux/module.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include <linux/netdevice.h> | |
ff86a543 | 25 | #include <linux/ethtool.h> |
1da177e4 | 26 | #include <linux/pci.h> |
d43c36dc | 27 | #include <linux/sched.h> |
1da177e4 LT |
28 | #include <linux/etherdevice.h> |
29 | #include <linux/delay.h> | |
30 | #include <linux/if_arp.h> | |
31 | ||
32 | #include <asm/io.h> | |
33 | ||
34 | #include "prismcompat.h" | |
35 | #include "isl_38xx.h" | |
36 | #include "isl_ioctl.h" | |
37 | #include "islpci_dev.h" | |
38 | #include "islpci_mgt.h" | |
39 | #include "islpci_eth.h" | |
40 | #include "oid_mgt.h" | |
41 | ||
42 | #define ISL3877_IMAGE_FILE "isl3877" | |
43 | #define ISL3886_IMAGE_FILE "isl3886" | |
44 | #define ISL3890_IMAGE_FILE "isl3890" | |
a830e659 BH |
45 | MODULE_FIRMWARE(ISL3877_IMAGE_FILE); |
46 | MODULE_FIRMWARE(ISL3886_IMAGE_FILE); | |
47 | MODULE_FIRMWARE(ISL3890_IMAGE_FILE); | |
1da177e4 LT |
48 | |
49 | static int prism54_bring_down(islpci_private *); | |
50 | static int islpci_alloc_memory(islpci_private *); | |
1da177e4 LT |
51 | |
52 | /* Temporary dummy MAC address to use until firmware is loaded. | |
53 | * The idea there is that some tools (such as nameif) may query | |
54 | * the MAC address before the netdev is 'open'. By using a valid | |
55 | * OUI prefix, they can process the netdev properly. | |
56 | * Of course, this is not the final/real MAC address. It doesn't | |
57 | * matter, as you are suppose to be able to change it anytime via | |
58 | * ndev->set_mac_address. Jean II */ | |
59 | static const unsigned char dummy_mac[6] = { 0x00, 0x30, 0xB4, 0x00, 0x00, 0x00 }; | |
60 | ||
61 | static int | |
62 | isl_upload_firmware(islpci_private *priv) | |
63 | { | |
64 | u32 reg, rc; | |
65 | void __iomem *device_base = priv->device_base; | |
66 | ||
67 | /* clear the RAMBoot and the Reset bit */ | |
68 | reg = readl(device_base + ISL38XX_CTRL_STAT_REG); | |
69 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
70 | reg &= ~ISL38XX_CTRL_STAT_RAMBOOT; | |
71 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
72 | wmb(); | |
73 | udelay(ISL38XX_WRITEIO_DELAY); | |
74 | ||
75 | /* set the Reset bit without reading the register ! */ | |
76 | reg |= ISL38XX_CTRL_STAT_RESET; | |
77 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
78 | wmb(); | |
79 | udelay(ISL38XX_WRITEIO_DELAY); | |
80 | ||
81 | /* clear the Reset bit */ | |
82 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
83 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
84 | wmb(); | |
85 | ||
86 | /* wait a while for the device to reboot */ | |
87 | mdelay(50); | |
88 | ||
89 | { | |
90 | const struct firmware *fw_entry = NULL; | |
91 | long fw_len; | |
92 | const u32 *fw_ptr; | |
93 | ||
94 | rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV); | |
95 | if (rc) { | |
96 | printk(KERN_ERR | |
97 | "%s: request_firmware() failed for '%s'\n", | |
98 | "prism54", priv->firmware); | |
99 | return rc; | |
100 | } | |
101 | /* prepare the Direct Memory Base register */ | |
102 | reg = ISL38XX_DEV_FIRMWARE_ADDRES; | |
103 | ||
104 | fw_ptr = (u32 *) fw_entry->data; | |
105 | fw_len = fw_entry->size; | |
106 | ||
107 | if (fw_len % 4) { | |
108 | printk(KERN_ERR | |
109 | "%s: firmware '%s' size is not multiple of 32bit, aborting!\n", | |
110 | "prism54", priv->firmware); | |
111 | release_firmware(fw_entry); | |
112 | return -EILSEQ; /* Illegal byte sequence */; | |
113 | } | |
114 | ||
115 | while (fw_len > 0) { | |
116 | long _fw_len = | |
117 | (fw_len > | |
118 | ISL38XX_MEMORY_WINDOW_SIZE) ? | |
119 | ISL38XX_MEMORY_WINDOW_SIZE : fw_len; | |
120 | u32 __iomem *dev_fw_ptr = device_base + ISL38XX_DIRECT_MEM_WIN; | |
121 | ||
beb7dd86 | 122 | /* set the card's base address for writing the data */ |
1da177e4 LT |
123 | isl38xx_w32_flush(device_base, reg, |
124 | ISL38XX_DIR_MEM_BASE_REG); | |
125 | wmb(); /* be paranoid */ | |
126 | ||
127 | /* increment the write address for next iteration */ | |
128 | reg += _fw_len; | |
129 | fw_len -= _fw_len; | |
130 | ||
131 | /* write the data to the Direct Memory Window 32bit-wise */ | |
132 | /* memcpy_toio() doesn't guarantee 32bit writes :-| */ | |
133 | while (_fw_len > 0) { | |
134 | /* use non-swapping writel() */ | |
135 | __raw_writel(*fw_ptr, dev_fw_ptr); | |
136 | fw_ptr++, dev_fw_ptr++; | |
137 | _fw_len -= 4; | |
138 | } | |
139 | ||
140 | /* flush PCI posting */ | |
141 | (void) readl(device_base + ISL38XX_PCI_POSTING_FLUSH); | |
142 | wmb(); /* be paranoid again */ | |
143 | ||
144 | BUG_ON(_fw_len != 0); | |
145 | } | |
146 | ||
147 | BUG_ON(fw_len != 0); | |
148 | ||
149 | /* Firmware version is at offset 40 (also for "newmac") */ | |
150 | printk(KERN_DEBUG "%s: firmware version: %.8s\n", | |
151 | priv->ndev->name, fw_entry->data + 40); | |
152 | ||
153 | release_firmware(fw_entry); | |
154 | } | |
155 | ||
156 | /* now reset the device | |
157 | * clear the Reset & ClkRun bit, set the RAMBoot bit */ | |
158 | reg = readl(device_base + ISL38XX_CTRL_STAT_REG); | |
159 | reg &= ~ISL38XX_CTRL_STAT_CLKRUN; | |
160 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
161 | reg |= ISL38XX_CTRL_STAT_RAMBOOT; | |
162 | isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG); | |
163 | wmb(); | |
164 | udelay(ISL38XX_WRITEIO_DELAY); | |
165 | ||
166 | /* set the reset bit latches the host override and RAMBoot bits | |
167 | * into the device for operation when the reset bit is reset */ | |
168 | reg |= ISL38XX_CTRL_STAT_RESET; | |
169 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
170 | /* don't do flush PCI posting here! */ | |
171 | wmb(); | |
172 | udelay(ISL38XX_WRITEIO_DELAY); | |
173 | ||
174 | /* clear the reset bit should start the whole circus */ | |
175 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
176 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
177 | /* don't do flush PCI posting here! */ | |
178 | wmb(); | |
179 | udelay(ISL38XX_WRITEIO_DELAY); | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
184 | /****************************************************************************** | |
185 | Device Interrupt Handler | |
186 | ******************************************************************************/ | |
187 | ||
188 | irqreturn_t | |
7d12e780 | 189 | islpci_interrupt(int irq, void *config) |
1da177e4 LT |
190 | { |
191 | u32 reg; | |
192 | islpci_private *priv = config; | |
193 | struct net_device *ndev = priv->ndev; | |
194 | void __iomem *device = priv->device_base; | |
195 | int powerstate = ISL38XX_PSM_POWERSAVE_STATE; | |
196 | ||
197 | /* lock the interrupt handler */ | |
198 | spin_lock(&priv->slock); | |
199 | ||
200 | /* received an interrupt request on a shared IRQ line | |
201 | * first check whether the device is in sleep mode */ | |
202 | reg = readl(device + ISL38XX_CTRL_STAT_REG); | |
203 | if (reg & ISL38XX_CTRL_STAT_SLEEPMODE) | |
204 | /* device is in sleep mode, IRQ was generated by someone else */ | |
205 | { | |
206 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
207 | DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n"); | |
208 | #endif | |
209 | spin_unlock(&priv->slock); | |
210 | return IRQ_NONE; | |
211 | } | |
212 | ||
213 | ||
214 | /* check whether there is any source of interrupt on the device */ | |
215 | reg = readl(device + ISL38XX_INT_IDENT_REG); | |
216 | ||
217 | /* also check the contents of the Interrupt Enable Register, because this | |
218 | * will filter out interrupt sources from other devices on the same irq ! */ | |
219 | reg &= readl(device + ISL38XX_INT_EN_REG); | |
220 | reg &= ISL38XX_INT_SOURCES; | |
221 | ||
222 | if (reg != 0) { | |
223 | if (islpci_get_state(priv) != PRV_STATE_SLEEP) | |
224 | powerstate = ISL38XX_PSM_ACTIVE_STATE; | |
225 | ||
226 | /* reset the request bits in the Identification register */ | |
227 | isl38xx_w32_flush(device, reg, ISL38XX_INT_ACK_REG); | |
228 | ||
229 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
230 | DEBUG(SHOW_FUNCTION_CALLS, | |
4a89852c | 231 | "IRQ: Identification register 0x%p 0x%x\n", device, reg); |
1da177e4 LT |
232 | #endif |
233 | ||
234 | /* check for each bit in the register separately */ | |
235 | if (reg & ISL38XX_INT_IDENT_UPDATE) { | |
236 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
237 | /* Queue has been updated */ | |
4a89852c | 238 | DEBUG(SHOW_TRACING, "IRQ: Update flag\n"); |
1da177e4 LT |
239 | |
240 | DEBUG(SHOW_QUEUE_INDEXES, | |
241 | "CB drv Qs: [%i][%i][%i][%i][%i][%i]\n", | |
242 | le32_to_cpu(priv->control_block-> | |
243 | driver_curr_frag[0]), | |
244 | le32_to_cpu(priv->control_block-> | |
245 | driver_curr_frag[1]), | |
246 | le32_to_cpu(priv->control_block-> | |
247 | driver_curr_frag[2]), | |
248 | le32_to_cpu(priv->control_block-> | |
249 | driver_curr_frag[3]), | |
250 | le32_to_cpu(priv->control_block-> | |
251 | driver_curr_frag[4]), | |
252 | le32_to_cpu(priv->control_block-> | |
253 | driver_curr_frag[5]) | |
254 | ); | |
255 | ||
256 | DEBUG(SHOW_QUEUE_INDEXES, | |
257 | "CB dev Qs: [%i][%i][%i][%i][%i][%i]\n", | |
258 | le32_to_cpu(priv->control_block-> | |
259 | device_curr_frag[0]), | |
260 | le32_to_cpu(priv->control_block-> | |
261 | device_curr_frag[1]), | |
262 | le32_to_cpu(priv->control_block-> | |
263 | device_curr_frag[2]), | |
264 | le32_to_cpu(priv->control_block-> | |
265 | device_curr_frag[3]), | |
266 | le32_to_cpu(priv->control_block-> | |
267 | device_curr_frag[4]), | |
268 | le32_to_cpu(priv->control_block-> | |
269 | device_curr_frag[5]) | |
270 | ); | |
271 | #endif | |
272 | ||
273 | /* cleanup the data low transmit queue */ | |
274 | islpci_eth_cleanup_transmit(priv, priv->control_block); | |
275 | ||
276 | /* device is in active state, update the | |
277 | * powerstate flag if necessary */ | |
278 | powerstate = ISL38XX_PSM_ACTIVE_STATE; | |
279 | ||
280 | /* check all three queues in priority order | |
281 | * call the PIMFOR receive function until the | |
282 | * queue is empty */ | |
283 | if (isl38xx_in_queue(priv->control_block, | |
284 | ISL38XX_CB_RX_MGMTQ) != 0) { | |
285 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
286 | DEBUG(SHOW_TRACING, | |
287 | "Received frame in Management Queue\n"); | |
288 | #endif | |
289 | islpci_mgt_receive(ndev); | |
290 | ||
291 | islpci_mgt_cleanup_transmit(ndev); | |
292 | ||
293 | /* Refill slots in receive queue */ | |
294 | islpci_mgmt_rx_fill(ndev); | |
295 | ||
296 | /* no need to trigger the device, next | |
297 | islpci_mgt_transaction does it */ | |
298 | } | |
299 | ||
300 | while (isl38xx_in_queue(priv->control_block, | |
301 | ISL38XX_CB_RX_DATA_LQ) != 0) { | |
302 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
303 | DEBUG(SHOW_TRACING, | |
4a89852c | 304 | "Received frame in Data Low Queue\n"); |
1da177e4 LT |
305 | #endif |
306 | islpci_eth_receive(priv); | |
307 | } | |
308 | ||
309 | /* check whether the data transmit queues were full */ | |
310 | if (priv->data_low_tx_full) { | |
311 | /* check whether the transmit is not full anymore */ | |
312 | if (ISL38XX_CB_TX_QSIZE - | |
313 | isl38xx_in_queue(priv->control_block, | |
314 | ISL38XX_CB_TX_DATA_LQ) >= | |
315 | ISL38XX_MIN_QTHRESHOLD) { | |
316 | /* nope, the driver is ready for more network frames */ | |
317 | netif_wake_queue(priv->ndev); | |
318 | ||
319 | /* reset the full flag */ | |
320 | priv->data_low_tx_full = 0; | |
321 | } | |
322 | } | |
323 | } | |
324 | ||
325 | if (reg & ISL38XX_INT_IDENT_INIT) { | |
326 | /* Device has been initialized */ | |
327 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
328 | DEBUG(SHOW_TRACING, | |
4a89852c | 329 | "IRQ: Init flag, device initialized\n"); |
1da177e4 LT |
330 | #endif |
331 | wake_up(&priv->reset_done); | |
332 | } | |
333 | ||
334 | if (reg & ISL38XX_INT_IDENT_SLEEP) { | |
335 | /* Device intends to move to powersave state */ | |
336 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
4a89852c | 337 | DEBUG(SHOW_TRACING, "IRQ: Sleep flag\n"); |
1da177e4 LT |
338 | #endif |
339 | isl38xx_handle_sleep_request(priv->control_block, | |
340 | &powerstate, | |
341 | priv->device_base); | |
342 | } | |
343 | ||
344 | if (reg & ISL38XX_INT_IDENT_WAKEUP) { | |
345 | /* Device has been woken up to active state */ | |
346 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
4a89852c | 347 | DEBUG(SHOW_TRACING, "IRQ: Wakeup flag\n"); |
1da177e4 LT |
348 | #endif |
349 | ||
350 | isl38xx_handle_wakeup(priv->control_block, | |
351 | &powerstate, priv->device_base); | |
352 | } | |
353 | } else { | |
354 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
355 | DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n"); | |
356 | #endif | |
357 | spin_unlock(&priv->slock); | |
358 | return IRQ_NONE; | |
359 | } | |
360 | ||
361 | /* sleep -> ready */ | |
362 | if (islpci_get_state(priv) == PRV_STATE_SLEEP | |
363 | && powerstate == ISL38XX_PSM_ACTIVE_STATE) | |
364 | islpci_set_state(priv, PRV_STATE_READY); | |
365 | ||
366 | /* !sleep -> sleep */ | |
367 | if (islpci_get_state(priv) != PRV_STATE_SLEEP | |
368 | && powerstate == ISL38XX_PSM_POWERSAVE_STATE) | |
369 | islpci_set_state(priv, PRV_STATE_SLEEP); | |
370 | ||
371 | /* unlock the interrupt handler */ | |
372 | spin_unlock(&priv->slock); | |
373 | ||
374 | return IRQ_HANDLED; | |
375 | } | |
376 | ||
377 | /****************************************************************************** | |
378 | Network Interface Control & Statistical functions | |
379 | ******************************************************************************/ | |
380 | static int | |
381 | islpci_open(struct net_device *ndev) | |
382 | { | |
383 | u32 rc; | |
384 | islpci_private *priv = netdev_priv(ndev); | |
385 | ||
386 | /* reset data structures, upload firmware and reset device */ | |
387 | rc = islpci_reset(priv,1); | |
388 | if (rc) { | |
389 | prism54_bring_down(priv); | |
390 | return rc; /* Returns informative message */ | |
391 | } | |
392 | ||
393 | netif_start_queue(ndev); | |
7b463ced | 394 | |
85b442e3 LR |
395 | /* Turn off carrier if in STA or Ad-hoc mode. It will be turned on |
396 | * once the firmware receives a trap of being associated | |
397 | * (GEN_OID_LINKSTATE). In other modes (AP or WDS or monitor) we | |
398 | * should just leave the carrier on as its expected the firmware | |
399 | * won't send us a trigger. */ | |
400 | if (priv->iw_mode == IW_MODE_INFRA || priv->iw_mode == IW_MODE_ADHOC) | |
401 | netif_carrier_off(ndev); | |
402 | else | |
403 | netif_carrier_on(ndev); | |
1da177e4 LT |
404 | |
405 | return 0; | |
406 | } | |
407 | ||
408 | static int | |
409 | islpci_close(struct net_device *ndev) | |
410 | { | |
411 | islpci_private *priv = netdev_priv(ndev); | |
412 | ||
413 | printk(KERN_DEBUG "%s: islpci_close ()\n", ndev->name); | |
414 | ||
415 | netif_stop_queue(ndev); | |
416 | ||
417 | return prism54_bring_down(priv); | |
418 | } | |
419 | ||
420 | static int | |
421 | prism54_bring_down(islpci_private *priv) | |
422 | { | |
423 | void __iomem *device_base = priv->device_base; | |
424 | u32 reg; | |
425 | /* we are going to shutdown the device */ | |
426 | islpci_set_state(priv, PRV_STATE_PREBOOT); | |
427 | ||
428 | /* disable all device interrupts in case they weren't */ | |
93b2dd12 | 429 | isl38xx_disable_interrupts(priv->device_base); |
1da177e4 LT |
430 | |
431 | /* For safety reasons, we may want to ensure that no DMA transfer is | |
432 | * currently in progress by emptying the TX and RX queues. */ | |
433 | ||
434 | /* wait until interrupts have finished executing on other CPUs */ | |
435 | synchronize_irq(priv->pdev->irq); | |
436 | ||
437 | reg = readl(device_base + ISL38XX_CTRL_STAT_REG); | |
438 | reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT); | |
439 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
440 | wmb(); | |
441 | udelay(ISL38XX_WRITEIO_DELAY); | |
442 | ||
443 | reg |= ISL38XX_CTRL_STAT_RESET; | |
444 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
445 | wmb(); | |
446 | udelay(ISL38XX_WRITEIO_DELAY); | |
447 | ||
448 | /* clear the Reset bit */ | |
449 | reg &= ~ISL38XX_CTRL_STAT_RESET; | |
450 | writel(reg, device_base + ISL38XX_CTRL_STAT_REG); | |
451 | wmb(); | |
452 | ||
453 | /* wait a while for the device to reset */ | |
3173c890 | 454 | schedule_timeout_uninterruptible(msecs_to_jiffies(50)); |
1da177e4 LT |
455 | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static int | |
460 | islpci_upload_fw(islpci_private *priv) | |
461 | { | |
462 | islpci_state_t old_state; | |
463 | u32 rc; | |
464 | ||
465 | old_state = islpci_set_state(priv, PRV_STATE_BOOT); | |
466 | ||
467 | printk(KERN_DEBUG "%s: uploading firmware...\n", priv->ndev->name); | |
468 | ||
469 | rc = isl_upload_firmware(priv); | |
470 | if (rc) { | |
471 | /* error uploading the firmware */ | |
472 | printk(KERN_ERR "%s: could not upload firmware ('%s')\n", | |
473 | priv->ndev->name, priv->firmware); | |
474 | ||
475 | islpci_set_state(priv, old_state); | |
476 | return rc; | |
477 | } | |
478 | ||
479 | printk(KERN_DEBUG "%s: firmware upload complete\n", | |
480 | priv->ndev->name); | |
481 | ||
482 | islpci_set_state(priv, PRV_STATE_POSTBOOT); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static int | |
488 | islpci_reset_if(islpci_private *priv) | |
489 | { | |
490 | long remaining; | |
491 | int result = -ETIME; | |
492 | int count; | |
493 | ||
494 | DEFINE_WAIT(wait); | |
495 | prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE); | |
93b2dd12 | 496 | |
1da177e4 LT |
497 | /* now the last step is to reset the interface */ |
498 | isl38xx_interface_reset(priv->device_base, priv->device_host_address); | |
499 | islpci_set_state(priv, PRV_STATE_PREINIT); | |
500 | ||
501 | for(count = 0; count < 2 && result; count++) { | |
502 | /* The software reset acknowledge needs about 220 msec here. | |
503 | * Be conservative and wait for up to one second. */ | |
93b2dd12 | 504 | |
3173c890 | 505 | remaining = schedule_timeout_uninterruptible(HZ); |
1da177e4 LT |
506 | |
507 | if(remaining > 0) { | |
508 | result = 0; | |
509 | break; | |
510 | } | |
511 | ||
93b2dd12 | 512 | /* If we're here it's because our IRQ hasn't yet gone through. |
1da177e4 LT |
513 | * Retry a bit more... |
514 | */ | |
515 | printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n", | |
516 | priv->ndev->name); | |
517 | } | |
518 | ||
519 | finish_wait(&priv->reset_done, &wait); | |
520 | ||
521 | if (result) { | |
522 | printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name); | |
523 | return result; | |
524 | } | |
525 | ||
526 | islpci_set_state(priv, PRV_STATE_INIT); | |
527 | ||
528 | /* Now that the device is 100% up, let's allow | |
529 | * for the other interrupts -- | |
93b2dd12 | 530 | * NOTE: this is not *yet* true since we've only allowed the |
1da177e4 LT |
531 | * INIT interrupt on the IRQ line. We can perhaps poll |
532 | * the IRQ line until we know for sure the reset went through */ | |
533 | isl38xx_enable_common_interrupts(priv->device_base); | |
534 | ||
535 | down_write(&priv->mib_sem); | |
536 | result = mgt_commit(priv); | |
537 | if (result) { | |
538 | printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name); | |
539 | up_write(&priv->mib_sem); | |
540 | return result; | |
541 | } | |
542 | up_write(&priv->mib_sem); | |
543 | ||
544 | islpci_set_state(priv, PRV_STATE_READY); | |
545 | ||
546 | printk(KERN_DEBUG "%s: interface reset complete\n", priv->ndev->name); | |
547 | return 0; | |
548 | } | |
549 | ||
550 | int | |
551 | islpci_reset(islpci_private *priv, int reload_firmware) | |
552 | { | |
553 | isl38xx_control_block *cb = /* volatile not needed */ | |
554 | (isl38xx_control_block *) priv->control_block; | |
555 | unsigned counter; | |
556 | int rc; | |
557 | ||
558 | if (reload_firmware) | |
559 | islpci_set_state(priv, PRV_STATE_PREBOOT); | |
560 | else | |
561 | islpci_set_state(priv, PRV_STATE_POSTBOOT); | |
562 | ||
563 | printk(KERN_DEBUG "%s: resetting device...\n", priv->ndev->name); | |
564 | ||
565 | /* disable all device interrupts in case they weren't */ | |
566 | isl38xx_disable_interrupts(priv->device_base); | |
567 | ||
568 | /* flush all management queues */ | |
569 | priv->index_mgmt_tx = 0; | |
570 | priv->index_mgmt_rx = 0; | |
571 | ||
572 | /* clear the indexes in the frame pointer */ | |
573 | for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) { | |
574 | cb->driver_curr_frag[counter] = cpu_to_le32(0); | |
575 | cb->device_curr_frag[counter] = cpu_to_le32(0); | |
576 | } | |
577 | ||
578 | /* reset the mgmt receive queue */ | |
579 | for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) { | |
580 | isl38xx_fragment *frag = &cb->rx_data_mgmt[counter]; | |
581 | frag->size = cpu_to_le16(MGMT_FRAME_SIZE); | |
582 | frag->flags = 0; | |
583 | frag->address = cpu_to_le32(priv->mgmt_rx[counter].pci_addr); | |
584 | } | |
585 | ||
586 | for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { | |
587 | cb->rx_data_low[counter].address = | |
588 | cpu_to_le32((u32) priv->pci_map_rx_address[counter]); | |
589 | } | |
590 | ||
591 | /* since the receive queues are filled with empty fragments, now we can | |
592 | * set the corresponding indexes in the Control Block */ | |
593 | priv->control_block->driver_curr_frag[ISL38XX_CB_RX_DATA_LQ] = | |
594 | cpu_to_le32(ISL38XX_CB_RX_QSIZE); | |
595 | priv->control_block->driver_curr_frag[ISL38XX_CB_RX_MGMTQ] = | |
596 | cpu_to_le32(ISL38XX_CB_MGMT_QSIZE); | |
597 | ||
598 | /* reset the remaining real index registers and full flags */ | |
599 | priv->free_data_rx = 0; | |
600 | priv->free_data_tx = 0; | |
601 | priv->data_low_tx_full = 0; | |
602 | ||
603 | if (reload_firmware) { /* Should we load the firmware ? */ | |
604 | /* now that the data structures are cleaned up, upload | |
605 | * firmware and reset interface */ | |
606 | rc = islpci_upload_fw(priv); | |
607 | if (rc) { | |
608 | printk(KERN_ERR "%s: islpci_reset: failure\n", | |
609 | priv->ndev->name); | |
610 | return rc; | |
611 | } | |
612 | } | |
613 | ||
614 | /* finally reset interface */ | |
615 | rc = islpci_reset_if(priv); | |
616 | if (rc) | |
617 | printk(KERN_ERR "prism54: Your card/socket may be faulty, or IRQ line too busy :(\n"); | |
618 | return rc; | |
619 | } | |
620 | ||
1da177e4 LT |
621 | /****************************************************************************** |
622 | Network device configuration functions | |
623 | ******************************************************************************/ | |
624 | static int | |
625 | islpci_alloc_memory(islpci_private *priv) | |
626 | { | |
627 | int counter; | |
628 | ||
629 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
630 | printk(KERN_DEBUG "islpci_alloc_memory\n"); | |
631 | #endif | |
632 | ||
633 | /* remap the PCI device base address to accessable */ | |
634 | if (!(priv->device_base = | |
635 | ioremap(pci_resource_start(priv->pdev, 0), | |
636 | ISL38XX_PCI_MEM_SIZE))) { | |
637 | /* error in remapping the PCI device memory address range */ | |
4a89852c | 638 | printk(KERN_ERR "PCI memory remapping failed\n"); |
1da177e4 LT |
639 | return -1; |
640 | } | |
641 | ||
642 | /* memory layout for consistent DMA region: | |
643 | * | |
644 | * Area 1: Control Block for the device interface | |
645 | * Area 2: Power Save Mode Buffer for temporary frame storage. Be aware that | |
646 | * the number of supported stations in the AP determines the minimal | |
647 | * size of the buffer ! | |
648 | */ | |
649 | ||
650 | /* perform the allocation */ | |
651 | priv->driver_mem_address = pci_alloc_consistent(priv->pdev, | |
652 | HOST_MEM_BLOCK, | |
653 | &priv-> | |
654 | device_host_address); | |
655 | ||
656 | if (!priv->driver_mem_address) { | |
657 | /* error allocating the block of PCI memory */ | |
658 | printk(KERN_ERR "%s: could not allocate DMA memory, aborting!", | |
659 | "prism54"); | |
660 | return -1; | |
661 | } | |
662 | ||
663 | /* assign the Control Block to the first address of the allocated area */ | |
664 | priv->control_block = | |
665 | (isl38xx_control_block *) priv->driver_mem_address; | |
666 | ||
667 | /* set the Power Save Buffer pointer directly behind the CB */ | |
668 | priv->device_psm_buffer = | |
669 | priv->device_host_address + CONTROL_BLOCK_SIZE; | |
670 | ||
671 | /* make sure all buffer pointers are initialized */ | |
672 | for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) { | |
673 | priv->control_block->driver_curr_frag[counter] = cpu_to_le32(0); | |
674 | priv->control_block->device_curr_frag[counter] = cpu_to_le32(0); | |
675 | } | |
676 | ||
677 | priv->index_mgmt_rx = 0; | |
678 | memset(priv->mgmt_rx, 0, sizeof(priv->mgmt_rx)); | |
679 | memset(priv->mgmt_tx, 0, sizeof(priv->mgmt_tx)); | |
680 | ||
681 | /* allocate rx queue for management frames */ | |
682 | if (islpci_mgmt_rx_fill(priv->ndev) < 0) | |
683 | goto out_free; | |
684 | ||
685 | /* now get the data rx skb's */ | |
686 | memset(priv->data_low_rx, 0, sizeof (priv->data_low_rx)); | |
687 | memset(priv->pci_map_rx_address, 0, sizeof (priv->pci_map_rx_address)); | |
688 | ||
689 | for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { | |
690 | struct sk_buff *skb; | |
691 | ||
692 | /* allocate an sk_buff for received data frames storage | |
693 | * each frame on receive size consists of 1 fragment | |
694 | * include any required allignment operations */ | |
695 | if (!(skb = dev_alloc_skb(MAX_FRAGMENT_SIZE_RX + 2))) { | |
696 | /* error allocating an sk_buff structure elements */ | |
697 | printk(KERN_ERR "Error allocating skb.\n"); | |
698 | skb = NULL; | |
699 | goto out_free; | |
700 | } | |
701 | skb_reserve(skb, (4 - (long) skb->data) & 0x03); | |
702 | /* add the new allocated sk_buff to the buffer array */ | |
703 | priv->data_low_rx[counter] = skb; | |
704 | ||
705 | /* map the allocated skb data area to pci */ | |
706 | priv->pci_map_rx_address[counter] = | |
707 | pci_map_single(priv->pdev, (void *) skb->data, | |
708 | MAX_FRAGMENT_SIZE_RX + 2, | |
709 | PCI_DMA_FROMDEVICE); | |
710 | if (!priv->pci_map_rx_address[counter]) { | |
711 | /* error mapping the buffer to device | |
712 | accessable memory address */ | |
713 | printk(KERN_ERR "failed to map skb DMA'able\n"); | |
714 | goto out_free; | |
715 | } | |
716 | } | |
717 | ||
718 | prism54_acl_init(&priv->acl); | |
eab411f1 | 719 | prism54_wpa_bss_ie_init(priv); |
93b2dd12 | 720 | if (mgt_init(priv)) |
1da177e4 LT |
721 | goto out_free; |
722 | ||
723 | return 0; | |
724 | out_free: | |
725 | islpci_free_memory(priv); | |
726 | return -1; | |
727 | } | |
728 | ||
729 | int | |
730 | islpci_free_memory(islpci_private *priv) | |
731 | { | |
732 | int counter; | |
733 | ||
734 | if (priv->device_base) | |
735 | iounmap(priv->device_base); | |
736 | priv->device_base = NULL; | |
737 | ||
738 | /* free consistent DMA area... */ | |
739 | if (priv->driver_mem_address) | |
740 | pci_free_consistent(priv->pdev, HOST_MEM_BLOCK, | |
741 | priv->driver_mem_address, | |
742 | priv->device_host_address); | |
743 | ||
744 | /* clear some dangling pointers */ | |
745 | priv->driver_mem_address = NULL; | |
746 | priv->device_host_address = 0; | |
747 | priv->device_psm_buffer = 0; | |
748 | priv->control_block = NULL; | |
749 | ||
750 | /* clean up mgmt rx buffers */ | |
751 | for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) { | |
752 | struct islpci_membuf *buf = &priv->mgmt_rx[counter]; | |
753 | if (buf->pci_addr) | |
754 | pci_unmap_single(priv->pdev, buf->pci_addr, | |
755 | buf->size, PCI_DMA_FROMDEVICE); | |
756 | buf->pci_addr = 0; | |
b4558ea9 | 757 | kfree(buf->mem); |
1da177e4 LT |
758 | buf->size = 0; |
759 | buf->mem = NULL; | |
760 | } | |
761 | ||
762 | /* clean up data rx buffers */ | |
763 | for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) { | |
764 | if (priv->pci_map_rx_address[counter]) | |
765 | pci_unmap_single(priv->pdev, | |
766 | priv->pci_map_rx_address[counter], | |
767 | MAX_FRAGMENT_SIZE_RX + 2, | |
768 | PCI_DMA_FROMDEVICE); | |
769 | priv->pci_map_rx_address[counter] = 0; | |
770 | ||
771 | if (priv->data_low_rx[counter]) | |
772 | dev_kfree_skb(priv->data_low_rx[counter]); | |
773 | priv->data_low_rx[counter] = NULL; | |
774 | } | |
775 | ||
776 | /* Free the acces control list and the WPA list */ | |
777 | prism54_acl_clean(&priv->acl); | |
eab411f1 | 778 | prism54_wpa_bss_ie_clean(priv); |
1da177e4 LT |
779 | mgt_clean(priv); |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
784 | #if 0 | |
785 | static void | |
786 | islpci_set_multicast_list(struct net_device *dev) | |
787 | { | |
788 | /* put device into promisc mode and let network layer handle it */ | |
789 | } | |
790 | #endif | |
791 | ||
ff86a543 KE |
792 | static void islpci_ethtool_get_drvinfo(struct net_device *dev, |
793 | struct ethtool_drvinfo *info) | |
794 | { | |
795 | strcpy(info->driver, DRV_NAME); | |
796 | strcpy(info->version, DRV_VERSION); | |
797 | } | |
798 | ||
6685254f | 799 | static const struct ethtool_ops islpci_ethtool_ops = { |
ff86a543 KE |
800 | .get_drvinfo = islpci_ethtool_get_drvinfo, |
801 | }; | |
802 | ||
6685254f SH |
803 | static const struct net_device_ops islpci_netdev_ops = { |
804 | .ndo_open = islpci_open, | |
805 | .ndo_stop = islpci_close, | |
6685254f SH |
806 | .ndo_do_ioctl = prism54_ioctl, |
807 | .ndo_start_xmit = islpci_eth_transmit, | |
808 | .ndo_tx_timeout = islpci_eth_tx_timeout, | |
809 | .ndo_set_mac_address = prism54_set_mac_address, | |
810 | .ndo_change_mtu = eth_change_mtu, | |
6685254f SH |
811 | .ndo_validate_addr = eth_validate_addr, |
812 | }; | |
813 | ||
1da177e4 LT |
814 | struct net_device * |
815 | islpci_setup(struct pci_dev *pdev) | |
816 | { | |
817 | islpci_private *priv; | |
818 | struct net_device *ndev = alloc_etherdev(sizeof (islpci_private)); | |
819 | ||
820 | if (!ndev) | |
821 | return ndev; | |
822 | ||
1da177e4 LT |
823 | pci_set_drvdata(pdev, ndev); |
824 | #if defined(SET_NETDEV_DEV) | |
825 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
826 | #endif | |
827 | ||
828 | /* setup the structure members */ | |
829 | ndev->base_addr = pci_resource_start(pdev, 0); | |
830 | ndev->irq = pdev->irq; | |
831 | ||
832 | /* initialize the function pointers */ | |
6685254f SH |
833 | ndev->netdev_ops = &islpci_netdev_ops; |
834 | ndev->wireless_handlers = &prism54_handler_def; | |
ff86a543 | 835 | ndev->ethtool_ops = &islpci_ethtool_ops; |
1da177e4 | 836 | |
1da177e4 LT |
837 | /* ndev->set_multicast_list = &islpci_set_multicast_list; */ |
838 | ndev->addr_len = ETH_ALEN; | |
1da177e4 LT |
839 | /* Get a non-zero dummy MAC address for nameif. Jean II */ |
840 | memcpy(ndev->dev_addr, dummy_mac, 6); | |
841 | ||
1da177e4 | 842 | ndev->watchdog_timeo = ISLPCI_TX_TIMEOUT; |
1da177e4 LT |
843 | |
844 | /* allocate a private device structure to the network device */ | |
845 | priv = netdev_priv(ndev); | |
846 | priv->ndev = ndev; | |
847 | priv->pdev = pdev; | |
848 | priv->monitor_type = ARPHRD_IEEE80211; | |
849 | priv->ndev->type = (priv->iw_mode == IW_MODE_MONITOR) ? | |
850 | priv->monitor_type : ARPHRD_ETHER; | |
851 | ||
1da177e4 LT |
852 | /* Add pointers to enable iwspy support. */ |
853 | priv->wireless_data.spy_data = &priv->spy_data; | |
854 | ndev->wireless_data = &priv->wireless_data; | |
1da177e4 LT |
855 | |
856 | /* save the start and end address of the PCI memory area */ | |
857 | ndev->mem_start = (unsigned long) priv->device_base; | |
858 | ndev->mem_end = ndev->mem_start + ISL38XX_PCI_MEM_SIZE; | |
859 | ||
860 | #if VERBOSE > SHOW_ERROR_MESSAGES | |
861 | DEBUG(SHOW_TRACING, "PCI Memory remapped to 0x%p\n", priv->device_base); | |
862 | #endif | |
863 | ||
864 | init_waitqueue_head(&priv->reset_done); | |
865 | ||
866 | /* init the queue read locks, process wait counter */ | |
1b34fd39 | 867 | mutex_init(&priv->mgmt_lock); |
1da177e4 LT |
868 | priv->mgmt_received = NULL; |
869 | init_waitqueue_head(&priv->mgmt_wqueue); | |
f8139218 | 870 | mutex_init(&priv->stats_lock); |
1da177e4 LT |
871 | spin_lock_init(&priv->slock); |
872 | ||
873 | /* init state machine with off#1 state */ | |
874 | priv->state = PRV_STATE_OFF; | |
875 | priv->state_off = 1; | |
876 | ||
877 | /* initialize workqueue's */ | |
c4028958 | 878 | INIT_WORK(&priv->stats_work, prism54_update_stats); |
1da177e4 LT |
879 | priv->stats_timestamp = 0; |
880 | ||
c4028958 | 881 | INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake); |
1da177e4 LT |
882 | priv->reset_task_pending = 0; |
883 | ||
884 | /* allocate various memory areas */ | |
885 | if (islpci_alloc_memory(priv)) | |
886 | goto do_free_netdev; | |
887 | ||
888 | /* select the firmware file depending on the device id */ | |
889 | switch (pdev->device) { | |
890 | case 0x3877: | |
891 | strcpy(priv->firmware, ISL3877_IMAGE_FILE); | |
892 | break; | |
893 | ||
894 | case 0x3886: | |
895 | strcpy(priv->firmware, ISL3886_IMAGE_FILE); | |
896 | break; | |
897 | ||
898 | default: | |
899 | strcpy(priv->firmware, ISL3890_IMAGE_FILE); | |
900 | break; | |
901 | } | |
902 | ||
903 | if (register_netdev(ndev)) { | |
904 | DEBUG(SHOW_ERROR_MESSAGES, | |
4a89852c | 905 | "ERROR: register_netdev() failed\n"); |
1da177e4 LT |
906 | goto do_islpci_free_memory; |
907 | } | |
908 | ||
909 | return ndev; | |
910 | ||
911 | do_islpci_free_memory: | |
912 | islpci_free_memory(priv); | |
913 | do_free_netdev: | |
914 | pci_set_drvdata(pdev, NULL); | |
915 | free_netdev(ndev); | |
916 | priv = NULL; | |
917 | return NULL; | |
918 | } | |
919 | ||
920 | islpci_state_t | |
921 | islpci_set_state(islpci_private *priv, islpci_state_t new_state) | |
922 | { | |
923 | islpci_state_t old_state; | |
924 | ||
925 | /* lock */ | |
926 | old_state = priv->state; | |
927 | ||
928 | /* this means either a race condition or some serious error in | |
929 | * the driver code */ | |
930 | switch (new_state) { | |
931 | case PRV_STATE_OFF: | |
932 | priv->state_off++; | |
933 | default: | |
934 | priv->state = new_state; | |
935 | break; | |
936 | ||
937 | case PRV_STATE_PREBOOT: | |
938 | /* there are actually many off-states, enumerated by | |
939 | * state_off */ | |
940 | if (old_state == PRV_STATE_OFF) | |
941 | priv->state_off--; | |
942 | ||
943 | /* only if hw_unavailable is zero now it means we either | |
944 | * were in off#1 state, or came here from | |
945 | * somewhere else */ | |
946 | if (!priv->state_off) | |
947 | priv->state = new_state; | |
948 | break; | |
ee289b64 | 949 | } |
1da177e4 LT |
950 | #if 0 |
951 | printk(KERN_DEBUG "%s: state transition %d -> %d (off#%d)\n", | |
952 | priv->ndev->name, old_state, new_state, priv->state_off); | |
953 | #endif | |
954 | ||
955 | /* invariants */ | |
956 | BUG_ON(priv->state_off < 0); | |
957 | BUG_ON(priv->state_off && (priv->state != PRV_STATE_OFF)); | |
958 | BUG_ON(!priv->state_off && (priv->state == PRV_STATE_OFF)); | |
959 | ||
960 | /* unlock */ | |
961 | return old_state; | |
962 | } |