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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
42f61420 | 20 | #include <linux/cpu.h> |
fd63e9ce | 21 | #include <linux/delay.h> |
b60503ba MW |
22 | #include <linux/errno.h> |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
4cc09e2d | 25 | #include <linux/hdreg.h> |
5aff9382 | 26 | #include <linux/idr.h> |
b60503ba MW |
27 | #include <linux/init.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/kdev_t.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
2d55cd5f | 42 | #include <linux/timer.h> |
b60503ba | 43 | #include <linux/types.h> |
2f8e2c87 | 44 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 45 | #include <asm/unaligned.h> |
797a796a | 46 | |
f11bb3e2 CH |
47 | #include "nvme.h" |
48 | ||
9d43cf64 | 49 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 50 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
51 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
52 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 53 | |
adf68f21 CH |
54 | /* |
55 | * We handle AEN commands ourselves and don't even let the | |
56 | * block layer know about them. | |
57 | */ | |
f866fc42 | 58 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 59 | |
58ffacb5 MW |
60 | static int use_threaded_interrupts; |
61 | module_param(use_threaded_interrupts, int, 0); | |
62 | ||
8ffaadf7 JD |
63 | static bool use_cmb_sqes = true; |
64 | module_param(use_cmb_sqes, bool, 0644); | |
65 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
66 | ||
9a6b9458 | 67 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 68 | |
1c63dc66 CH |
69 | struct nvme_dev; |
70 | struct nvme_queue; | |
b3fffdef | 71 | |
4cc06521 | 72 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 73 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 74 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 75 | |
1c63dc66 CH |
76 | /* |
77 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
78 | */ | |
79 | struct nvme_dev { | |
1c63dc66 CH |
80 | struct nvme_queue **queues; |
81 | struct blk_mq_tag_set tagset; | |
82 | struct blk_mq_tag_set admin_tagset; | |
83 | u32 __iomem *dbs; | |
84 | struct device *dev; | |
85 | struct dma_pool *prp_page_pool; | |
86 | struct dma_pool *prp_small_pool; | |
87 | unsigned queue_count; | |
88 | unsigned online_queues; | |
89 | unsigned max_qid; | |
90 | int q_depth; | |
91 | u32 db_stride; | |
1c63dc66 | 92 | void __iomem *bar; |
1c63dc66 | 93 | struct work_struct reset_work; |
5c8809e6 | 94 | struct work_struct remove_work; |
2d55cd5f | 95 | struct timer_list watchdog_timer; |
77bf25ea | 96 | struct mutex shutdown_lock; |
1c63dc66 | 97 | bool subsystem; |
1c63dc66 CH |
98 | void __iomem *cmb; |
99 | dma_addr_t cmb_dma_addr; | |
100 | u64 cmb_size; | |
101 | u32 cmbsz; | |
202021c1 | 102 | u32 cmbloc; |
1c63dc66 | 103 | struct nvme_ctrl ctrl; |
db3cbfff | 104 | struct completion ioq_wait; |
4d115420 | 105 | }; |
1fa6aead | 106 | |
1c63dc66 CH |
107 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
108 | { | |
109 | return container_of(ctrl, struct nvme_dev, ctrl); | |
110 | } | |
111 | ||
b60503ba MW |
112 | /* |
113 | * An NVM Express queue. Each device has at least two (one for admin | |
114 | * commands and one for I/O commands). | |
115 | */ | |
116 | struct nvme_queue { | |
117 | struct device *q_dmadev; | |
091b6092 | 118 | struct nvme_dev *dev; |
3193f07b | 119 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
120 | spinlock_t q_lock; |
121 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 122 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 123 | volatile struct nvme_completion *cqes; |
42483228 | 124 | struct blk_mq_tags **tags; |
b60503ba MW |
125 | dma_addr_t sq_dma_addr; |
126 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
127 | u32 __iomem *q_db; |
128 | u16 q_depth; | |
6222d172 | 129 | s16 cq_vector; |
b60503ba MW |
130 | u16 sq_tail; |
131 | u16 cq_head; | |
c30341dc | 132 | u16 qid; |
e9539f47 MW |
133 | u8 cq_phase; |
134 | u8 cqe_seen; | |
b60503ba MW |
135 | }; |
136 | ||
71bd150c CH |
137 | /* |
138 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
139 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 140 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
141 | * allocated to store the PRP list. |
142 | */ | |
143 | struct nvme_iod { | |
d49187e9 | 144 | struct nvme_request req; |
f4800d6d CH |
145 | struct nvme_queue *nvmeq; |
146 | int aborted; | |
71bd150c | 147 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
148 | int nents; /* Used in scatterlist */ |
149 | int length; /* Of data, in bytes */ | |
150 | dma_addr_t first_dma; | |
bf684057 | 151 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
152 | struct scatterlist *sg; |
153 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
154 | }; |
155 | ||
156 | /* | |
157 | * Check we didin't inadvertently grow the command struct | |
158 | */ | |
159 | static inline void _nvme_check_size(void) | |
160 | { | |
161 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
162 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
163 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
164 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
165 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 166 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 167 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
168 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
169 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
170 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
171 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 172 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
173 | } |
174 | ||
ac3dd5bd JA |
175 | /* |
176 | * Max size of iod being embedded in the request payload | |
177 | */ | |
178 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 179 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
180 | |
181 | /* | |
182 | * Will slightly overestimate the number of pages needed. This is OK | |
183 | * as it only leads to a small amount of wasted memory for the lifetime of | |
184 | * the I/O. | |
185 | */ | |
186 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
187 | { | |
5fd4ce1b CH |
188 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
189 | dev->ctrl.page_size); | |
ac3dd5bd JA |
190 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
191 | } | |
192 | ||
f4800d6d CH |
193 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
194 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 195 | { |
f4800d6d CH |
196 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
197 | sizeof(struct scatterlist) * nseg; | |
198 | } | |
ac3dd5bd | 199 | |
f4800d6d CH |
200 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
201 | { | |
202 | return sizeof(struct nvme_iod) + | |
203 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
204 | } |
205 | ||
dca51e78 CH |
206 | static int nvmeq_irq(struct nvme_queue *nvmeq) |
207 | { | |
208 | return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector); | |
209 | } | |
210 | ||
a4aea562 MB |
211 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
212 | unsigned int hctx_idx) | |
e85248e5 | 213 | { |
a4aea562 MB |
214 | struct nvme_dev *dev = data; |
215 | struct nvme_queue *nvmeq = dev->queues[0]; | |
216 | ||
42483228 KB |
217 | WARN_ON(hctx_idx != 0); |
218 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
219 | WARN_ON(nvmeq->tags); | |
220 | ||
a4aea562 | 221 | hctx->driver_data = nvmeq; |
42483228 | 222 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 223 | return 0; |
e85248e5 MW |
224 | } |
225 | ||
4af0e21c KB |
226 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
227 | { | |
228 | struct nvme_queue *nvmeq = hctx->driver_data; | |
229 | ||
230 | nvmeq->tags = NULL; | |
231 | } | |
232 | ||
a4aea562 MB |
233 | static int nvme_admin_init_request(void *data, struct request *req, |
234 | unsigned int hctx_idx, unsigned int rq_idx, | |
235 | unsigned int numa_node) | |
22404274 | 236 | { |
a4aea562 | 237 | struct nvme_dev *dev = data; |
f4800d6d | 238 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
239 | struct nvme_queue *nvmeq = dev->queues[0]; |
240 | ||
241 | BUG_ON(!nvmeq); | |
f4800d6d | 242 | iod->nvmeq = nvmeq; |
a4aea562 | 243 | return 0; |
22404274 KB |
244 | } |
245 | ||
a4aea562 MB |
246 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
247 | unsigned int hctx_idx) | |
b60503ba | 248 | { |
a4aea562 | 249 | struct nvme_dev *dev = data; |
42483228 | 250 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 251 | |
42483228 KB |
252 | if (!nvmeq->tags) |
253 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 254 | |
42483228 | 255 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
256 | hctx->driver_data = nvmeq; |
257 | return 0; | |
b60503ba MW |
258 | } |
259 | ||
a4aea562 MB |
260 | static int nvme_init_request(void *data, struct request *req, |
261 | unsigned int hctx_idx, unsigned int rq_idx, | |
262 | unsigned int numa_node) | |
b60503ba | 263 | { |
a4aea562 | 264 | struct nvme_dev *dev = data; |
f4800d6d | 265 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
266 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
267 | ||
268 | BUG_ON(!nvmeq); | |
f4800d6d | 269 | iod->nvmeq = nvmeq; |
a4aea562 MB |
270 | return 0; |
271 | } | |
272 | ||
dca51e78 CH |
273 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
274 | { | |
275 | struct nvme_dev *dev = set->driver_data; | |
276 | ||
277 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
278 | } | |
279 | ||
b60503ba | 280 | /** |
adf68f21 | 281 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
282 | * @nvmeq: The queue to use |
283 | * @cmd: The command to send | |
284 | * | |
285 | * Safe to use from interrupt context | |
286 | */ | |
e3f879bf SB |
287 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
288 | struct nvme_command *cmd) | |
b60503ba | 289 | { |
a4aea562 MB |
290 | u16 tail = nvmeq->sq_tail; |
291 | ||
8ffaadf7 JD |
292 | if (nvmeq->sq_cmds_io) |
293 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
294 | else | |
295 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
296 | ||
b60503ba MW |
297 | if (++tail == nvmeq->q_depth) |
298 | tail = 0; | |
7547881d | 299 | writel(tail, nvmeq->q_db); |
b60503ba | 300 | nvmeq->sq_tail = tail; |
b60503ba MW |
301 | } |
302 | ||
f4800d6d | 303 | static __le64 **iod_list(struct request *req) |
b60503ba | 304 | { |
f4800d6d | 305 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 306 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
307 | } |
308 | ||
b131c61d | 309 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 310 | { |
f4800d6d | 311 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 312 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 313 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 314 | |
f4800d6d CH |
315 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
316 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
317 | if (!iod->sg) | |
318 | return BLK_MQ_RQ_QUEUE_BUSY; | |
319 | } else { | |
320 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
321 | } |
322 | ||
f4800d6d CH |
323 | iod->aborted = 0; |
324 | iod->npages = -1; | |
325 | iod->nents = 0; | |
326 | iod->length = size; | |
f80ec966 | 327 | |
e8064021 | 328 | if (!(rq->rq_flags & RQF_DONTPREP)) { |
f80ec966 | 329 | rq->retries = 0; |
e8064021 | 330 | rq->rq_flags |= RQF_DONTPREP; |
f80ec966 | 331 | } |
bac0000a | 332 | return BLK_MQ_RQ_QUEUE_OK; |
ac3dd5bd JA |
333 | } |
334 | ||
f4800d6d | 335 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 336 | { |
f4800d6d | 337 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 338 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 339 | int i; |
f4800d6d | 340 | __le64 **list = iod_list(req); |
eca18b23 MW |
341 | dma_addr_t prp_dma = iod->first_dma; |
342 | ||
343 | if (iod->npages == 0) | |
344 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
345 | for (i = 0; i < iod->npages; i++) { | |
346 | __le64 *prp_list = list[i]; | |
347 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
348 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
349 | prp_dma = next_prp_dma; | |
350 | } | |
ac3dd5bd | 351 | |
f4800d6d CH |
352 | if (iod->sg != iod->inline_sg) |
353 | kfree(iod->sg); | |
b4ff9c8d KB |
354 | } |
355 | ||
52b68d7e | 356 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
357 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
358 | { | |
359 | if (be32_to_cpu(pi->ref_tag) == v) | |
360 | pi->ref_tag = cpu_to_be32(p); | |
361 | } | |
362 | ||
363 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
364 | { | |
365 | if (be32_to_cpu(pi->ref_tag) == p) | |
366 | pi->ref_tag = cpu_to_be32(v); | |
367 | } | |
368 | ||
369 | /** | |
370 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
371 | * | |
372 | * The virtual start sector is the one that was originally submitted by the | |
373 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
374 | * start sector may be different. Remap protection information to match the | |
375 | * physical LBA on writes, and back to the original seed on reads. | |
376 | * | |
377 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
378 | */ | |
379 | static void nvme_dif_remap(struct request *req, | |
380 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
381 | { | |
382 | struct nvme_ns *ns = req->rq_disk->private_data; | |
383 | struct bio_integrity_payload *bip; | |
384 | struct t10_pi_tuple *pi; | |
385 | void *p, *pmap; | |
386 | u32 i, nlb, ts, phys, virt; | |
387 | ||
388 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
389 | return; | |
390 | ||
391 | bip = bio_integrity(req->bio); | |
392 | if (!bip) | |
393 | return; | |
394 | ||
395 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
396 | |
397 | p = pmap; | |
398 | virt = bip_get_seed(bip); | |
399 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
400 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 401 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
402 | |
403 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
404 | pi = (struct t10_pi_tuple *)p; | |
405 | dif_swap(phys, virt, pi); | |
406 | p += ts; | |
407 | } | |
408 | kunmap_atomic(pmap); | |
409 | } | |
52b68d7e KB |
410 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
411 | static void nvme_dif_remap(struct request *req, | |
412 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
413 | { | |
414 | } | |
415 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
416 | { | |
417 | } | |
418 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
419 | { | |
420 | } | |
52b68d7e KB |
421 | #endif |
422 | ||
b131c61d | 423 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 424 | { |
f4800d6d | 425 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 426 | struct dma_pool *pool; |
b131c61d | 427 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 428 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
429 | int dma_len = sg_dma_len(sg); |
430 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 431 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 432 | int offset = dma_addr & (page_size - 1); |
e025344c | 433 | __le64 *prp_list; |
f4800d6d | 434 | __le64 **list = iod_list(req); |
e025344c | 435 | dma_addr_t prp_dma; |
eca18b23 | 436 | int nprps, i; |
ff22b54f | 437 | |
1d090624 | 438 | length -= (page_size - offset); |
ff22b54f | 439 | if (length <= 0) |
69d2b571 | 440 | return true; |
ff22b54f | 441 | |
1d090624 | 442 | dma_len -= (page_size - offset); |
ff22b54f | 443 | if (dma_len) { |
1d090624 | 444 | dma_addr += (page_size - offset); |
ff22b54f MW |
445 | } else { |
446 | sg = sg_next(sg); | |
447 | dma_addr = sg_dma_address(sg); | |
448 | dma_len = sg_dma_len(sg); | |
449 | } | |
450 | ||
1d090624 | 451 | if (length <= page_size) { |
edd10d33 | 452 | iod->first_dma = dma_addr; |
69d2b571 | 453 | return true; |
e025344c SMM |
454 | } |
455 | ||
1d090624 | 456 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
457 | if (nprps <= (256 / 8)) { |
458 | pool = dev->prp_small_pool; | |
eca18b23 | 459 | iod->npages = 0; |
99802a7a MW |
460 | } else { |
461 | pool = dev->prp_page_pool; | |
eca18b23 | 462 | iod->npages = 1; |
99802a7a MW |
463 | } |
464 | ||
69d2b571 | 465 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 466 | if (!prp_list) { |
edd10d33 | 467 | iod->first_dma = dma_addr; |
eca18b23 | 468 | iod->npages = -1; |
69d2b571 | 469 | return false; |
b77954cb | 470 | } |
eca18b23 MW |
471 | list[0] = prp_list; |
472 | iod->first_dma = prp_dma; | |
e025344c SMM |
473 | i = 0; |
474 | for (;;) { | |
1d090624 | 475 | if (i == page_size >> 3) { |
e025344c | 476 | __le64 *old_prp_list = prp_list; |
69d2b571 | 477 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 478 | if (!prp_list) |
69d2b571 | 479 | return false; |
eca18b23 | 480 | list[iod->npages++] = prp_list; |
7523d834 MW |
481 | prp_list[0] = old_prp_list[i - 1]; |
482 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
483 | i = 1; | |
e025344c SMM |
484 | } |
485 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
486 | dma_len -= page_size; |
487 | dma_addr += page_size; | |
488 | length -= page_size; | |
e025344c SMM |
489 | if (length <= 0) |
490 | break; | |
491 | if (dma_len > 0) | |
492 | continue; | |
493 | BUG_ON(dma_len < 0); | |
494 | sg = sg_next(sg); | |
495 | dma_addr = sg_dma_address(sg); | |
496 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
497 | } |
498 | ||
69d2b571 | 499 | return true; |
ff22b54f MW |
500 | } |
501 | ||
f4800d6d | 502 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 503 | struct nvme_command *cmnd) |
d29ec824 | 504 | { |
f4800d6d | 505 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
506 | struct request_queue *q = req->q; |
507 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
508 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
509 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 510 | |
f9d03f96 | 511 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
512 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
513 | if (!iod->nents) | |
514 | goto out; | |
d29ec824 | 515 | |
ba1ca37e | 516 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
2b6b535d MFO |
517 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
518 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 519 | goto out; |
d29ec824 | 520 | |
b131c61d | 521 | if (!nvme_setup_prps(dev, req)) |
ba1ca37e | 522 | goto out_unmap; |
0e5e4f0e | 523 | |
ba1ca37e CH |
524 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
525 | if (blk_integrity_rq(req)) { | |
526 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
527 | goto out_unmap; | |
0e5e4f0e | 528 | |
bf684057 CH |
529 | sg_init_table(&iod->meta_sg, 1); |
530 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 531 | goto out_unmap; |
0e5e4f0e | 532 | |
ba1ca37e CH |
533 | if (rq_data_dir(req)) |
534 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 535 | |
bf684057 | 536 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 537 | goto out_unmap; |
d29ec824 | 538 | } |
00df5cb4 | 539 | |
eb793e2c CH |
540 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
541 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 542 | if (blk_integrity_rq(req)) |
bf684057 | 543 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 544 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 545 | |
ba1ca37e CH |
546 | out_unmap: |
547 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
548 | out: | |
549 | return ret; | |
00df5cb4 MW |
550 | } |
551 | ||
f4800d6d | 552 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 553 | { |
f4800d6d | 554 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
555 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
556 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
557 | ||
558 | if (iod->nents) { | |
559 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
560 | if (blk_integrity_rq(req)) { | |
561 | if (!rq_data_dir(req)) | |
562 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 563 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 564 | } |
e19b127f | 565 | } |
e1e5e564 | 566 | |
f9d03f96 | 567 | nvme_cleanup_cmd(req); |
f4800d6d | 568 | nvme_free_iod(dev, req); |
d4f6c3ab | 569 | } |
b60503ba | 570 | |
d29ec824 CH |
571 | /* |
572 | * NOTE: ns is NULL when called on the admin queue. | |
573 | */ | |
a4aea562 MB |
574 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
575 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 576 | { |
a4aea562 MB |
577 | struct nvme_ns *ns = hctx->queue->queuedata; |
578 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 579 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 580 | struct request *req = bd->rq; |
ba1ca37e CH |
581 | struct nvme_command cmnd; |
582 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 583 | |
e1e5e564 KB |
584 | /* |
585 | * If formated with metadata, require the block layer provide a buffer | |
586 | * unless this namespace is formated such that the metadata can be | |
587 | * stripped/generated by the controller with PRACT=1. | |
588 | */ | |
d29ec824 | 589 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
590 | if (!(ns->pi_type && ns->ms == 8) && |
591 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 592 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
593 | return BLK_MQ_RQ_QUEUE_OK; |
594 | } | |
595 | } | |
596 | ||
f9d03f96 | 597 | ret = nvme_setup_cmd(ns, req, &cmnd); |
bac0000a | 598 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f4800d6d | 599 | return ret; |
a4aea562 | 600 | |
b131c61d | 601 | ret = nvme_init_iod(req, dev); |
bac0000a | 602 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 603 | goto out_free_cmd; |
a4aea562 | 604 | |
f9d03f96 | 605 | if (blk_rq_nr_phys_segments(req)) |
b131c61d | 606 | ret = nvme_map_data(dev, req, &cmnd); |
a4aea562 | 607 | |
bac0000a | 608 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 609 | goto out_cleanup_iod; |
a4aea562 | 610 | |
aae239e1 | 611 | blk_mq_start_request(req); |
a4aea562 | 612 | |
ba1ca37e | 613 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 614 | if (unlikely(nvmeq->cq_vector < 0)) { |
69d9a99c KB |
615 | if (ns && !test_bit(NVME_NS_DEAD, &ns->flags)) |
616 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
617 | else | |
618 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
ae1fba20 | 619 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 620 | goto out_cleanup_iod; |
ae1fba20 | 621 | } |
ba1ca37e | 622 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
623 | nvme_process_cq(nvmeq); |
624 | spin_unlock_irq(&nvmeq->q_lock); | |
625 | return BLK_MQ_RQ_QUEUE_OK; | |
f9d03f96 | 626 | out_cleanup_iod: |
f4800d6d | 627 | nvme_free_iod(dev, req); |
f9d03f96 CH |
628 | out_free_cmd: |
629 | nvme_cleanup_cmd(req); | |
ba1ca37e | 630 | return ret; |
b60503ba | 631 | } |
e1e5e564 | 632 | |
eee417b0 CH |
633 | static void nvme_complete_rq(struct request *req) |
634 | { | |
f4800d6d CH |
635 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
636 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 637 | int error = 0; |
e1e5e564 | 638 | |
f4800d6d | 639 | nvme_unmap_data(dev, req); |
e1e5e564 | 640 | |
eee417b0 CH |
641 | if (unlikely(req->errors)) { |
642 | if (nvme_req_needs_retry(req, req->errors)) { | |
f80ec966 | 643 | req->retries++; |
eee417b0 CH |
644 | nvme_requeue_req(req); |
645 | return; | |
e1e5e564 | 646 | } |
1974b1ae | 647 | |
eee417b0 CH |
648 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
649 | error = req->errors; | |
650 | else | |
651 | error = nvme_error_status(req->errors); | |
652 | } | |
a4aea562 | 653 | |
f4800d6d | 654 | if (unlikely(iod->aborted)) { |
1b3c47c1 | 655 | dev_warn(dev->ctrl.device, |
eee417b0 CH |
656 | "completing aborted command with status: %04x\n", |
657 | req->errors); | |
658 | } | |
a4aea562 | 659 | |
eee417b0 | 660 | blk_mq_end_request(req, error); |
b60503ba MW |
661 | } |
662 | ||
d783e0bd MR |
663 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
664 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
665 | u16 phase) | |
666 | { | |
667 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
668 | } | |
669 | ||
a0fa9647 | 670 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 671 | { |
82123460 | 672 | u16 head, phase; |
b60503ba | 673 | |
b60503ba | 674 | head = nvmeq->cq_head; |
82123460 | 675 | phase = nvmeq->cq_phase; |
b60503ba | 676 | |
d783e0bd | 677 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 678 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 679 | struct request *req; |
adf68f21 | 680 | |
b60503ba MW |
681 | if (++head == nvmeq->q_depth) { |
682 | head = 0; | |
82123460 | 683 | phase = !phase; |
b60503ba | 684 | } |
adf68f21 | 685 | |
a0fa9647 JA |
686 | if (tag && *tag == cqe.command_id) |
687 | *tag = -1; | |
adf68f21 | 688 | |
aae239e1 | 689 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 690 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
691 | "invalid id %d completed on queue %d\n", |
692 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
693 | continue; | |
694 | } | |
695 | ||
adf68f21 CH |
696 | /* |
697 | * AEN requests are special as they don't time out and can | |
698 | * survive any kind of queue freeze and often don't respond to | |
699 | * aborts. We don't even bother to allocate a struct request | |
700 | * for them but rather special case them here. | |
701 | */ | |
702 | if (unlikely(nvmeq->qid == 0 && | |
703 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
7bf58533 CH |
704 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
705 | cqe.status, &cqe.result); | |
adf68f21 CH |
706 | continue; |
707 | } | |
708 | ||
eee417b0 | 709 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
d49187e9 | 710 | nvme_req(req)->result = cqe.result; |
d783e0bd | 711 | blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1); |
b60503ba MW |
712 | } |
713 | ||
82123460 | 714 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 715 | return; |
b60503ba | 716 | |
604e8c8d KB |
717 | if (likely(nvmeq->cq_vector >= 0)) |
718 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 719 | nvmeq->cq_head = head; |
82123460 | 720 | nvmeq->cq_phase = phase; |
b60503ba | 721 | |
e9539f47 | 722 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
723 | } |
724 | ||
725 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
726 | { | |
727 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
728 | } |
729 | ||
730 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
731 | { |
732 | irqreturn_t result; | |
733 | struct nvme_queue *nvmeq = data; | |
734 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
735 | nvme_process_cq(nvmeq); |
736 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
737 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
738 | spin_unlock(&nvmeq->q_lock); |
739 | return result; | |
740 | } | |
741 | ||
742 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
743 | { | |
744 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
745 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
746 | return IRQ_WAKE_THREAD; | |
747 | return IRQ_NONE; | |
58ffacb5 MW |
748 | } |
749 | ||
a0fa9647 JA |
750 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
751 | { | |
752 | struct nvme_queue *nvmeq = hctx->driver_data; | |
753 | ||
d783e0bd | 754 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
755 | spin_lock_irq(&nvmeq->q_lock); |
756 | __nvme_process_cq(nvmeq, &tag); | |
757 | spin_unlock_irq(&nvmeq->q_lock); | |
758 | ||
759 | if (tag == -1) | |
760 | return 1; | |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
f866fc42 | 766 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 767 | { |
f866fc42 | 768 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 769 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 770 | struct nvme_command c; |
b60503ba | 771 | |
a4aea562 MB |
772 | memset(&c, 0, sizeof(c)); |
773 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 774 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 775 | |
9396dec9 | 776 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 777 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 778 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
779 | } |
780 | ||
b60503ba | 781 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 782 | { |
b60503ba MW |
783 | struct nvme_command c; |
784 | ||
785 | memset(&c, 0, sizeof(c)); | |
786 | c.delete_queue.opcode = opcode; | |
787 | c.delete_queue.qid = cpu_to_le16(id); | |
788 | ||
1c63dc66 | 789 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
790 | } |
791 | ||
b60503ba MW |
792 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
793 | struct nvme_queue *nvmeq) | |
794 | { | |
b60503ba MW |
795 | struct nvme_command c; |
796 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
797 | ||
d29ec824 CH |
798 | /* |
799 | * Note: we (ab)use the fact the the prp fields survive if no data | |
800 | * is attached to the request. | |
801 | */ | |
b60503ba MW |
802 | memset(&c, 0, sizeof(c)); |
803 | c.create_cq.opcode = nvme_admin_create_cq; | |
804 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
805 | c.create_cq.cqid = cpu_to_le16(qid); | |
806 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
807 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
808 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
809 | ||
1c63dc66 | 810 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
811 | } |
812 | ||
813 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
814 | struct nvme_queue *nvmeq) | |
815 | { | |
b60503ba MW |
816 | struct nvme_command c; |
817 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
818 | ||
d29ec824 CH |
819 | /* |
820 | * Note: we (ab)use the fact the the prp fields survive if no data | |
821 | * is attached to the request. | |
822 | */ | |
b60503ba MW |
823 | memset(&c, 0, sizeof(c)); |
824 | c.create_sq.opcode = nvme_admin_create_sq; | |
825 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
826 | c.create_sq.sqid = cpu_to_le16(qid); | |
827 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
828 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
829 | c.create_sq.cqid = cpu_to_le16(qid); | |
830 | ||
1c63dc66 | 831 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
832 | } |
833 | ||
834 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
835 | { | |
836 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
837 | } | |
838 | ||
839 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
840 | { | |
841 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
842 | } | |
843 | ||
e7a2a87d | 844 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 845 | { |
f4800d6d CH |
846 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
847 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d | 848 | u16 status = req->errors; |
e44ac588 | 849 | |
1cb3cce5 | 850 | dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status); |
e7a2a87d | 851 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 852 | blk_mq_free_request(req); |
bc5fc7e4 MW |
853 | } |
854 | ||
31c7c7d2 | 855 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 856 | { |
f4800d6d CH |
857 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
858 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 859 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 860 | struct request *abort_req; |
a4aea562 | 861 | struct nvme_command cmd; |
c30341dc | 862 | |
31c7c7d2 | 863 | /* |
fd634f41 CH |
864 | * Shutdown immediately if controller times out while starting. The |
865 | * reset work will see the pci device disabled when it gets the forced | |
866 | * cancellation error. All outstanding requests are completed on | |
867 | * shutdown, so we return BLK_EH_HANDLED. | |
868 | */ | |
bb8d261e | 869 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 870 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
871 | "I/O %d QID %d timeout, disable controller\n", |
872 | req->tag, nvmeq->qid); | |
a5cdb68c | 873 | nvme_dev_disable(dev, false); |
fd634f41 CH |
874 | req->errors = NVME_SC_CANCELLED; |
875 | return BLK_EH_HANDLED; | |
c30341dc KB |
876 | } |
877 | ||
fd634f41 CH |
878 | /* |
879 | * Shutdown the controller immediately and schedule a reset if the | |
880 | * command was already aborted once before and still hasn't been | |
881 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 882 | */ |
f4800d6d | 883 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 884 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
885 | "I/O %d QID %d timeout, reset controller\n", |
886 | req->tag, nvmeq->qid); | |
a5cdb68c | 887 | nvme_dev_disable(dev, false); |
c5f6ce97 | 888 | nvme_reset(dev); |
c30341dc | 889 | |
e1569a16 KB |
890 | /* |
891 | * Mark the request as handled, since the inline shutdown | |
892 | * forces all outstanding requests to complete. | |
893 | */ | |
894 | req->errors = NVME_SC_CANCELLED; | |
895 | return BLK_EH_HANDLED; | |
c30341dc | 896 | } |
c30341dc | 897 | |
f4800d6d | 898 | iod->aborted = 1; |
c30341dc | 899 | |
e7a2a87d | 900 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 901 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 902 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 903 | } |
a4aea562 | 904 | |
c30341dc KB |
905 | memset(&cmd, 0, sizeof(cmd)); |
906 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 907 | cmd.abort.cid = req->tag; |
c30341dc | 908 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 909 | |
1b3c47c1 SG |
910 | dev_warn(nvmeq->dev->ctrl.device, |
911 | "I/O %d QID %d timeout, aborting\n", | |
912 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
913 | |
914 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 915 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
916 | if (IS_ERR(abort_req)) { |
917 | atomic_inc(&dev->ctrl.abort_limit); | |
918 | return BLK_EH_RESET_TIMER; | |
919 | } | |
920 | ||
921 | abort_req->timeout = ADMIN_TIMEOUT; | |
922 | abort_req->end_io_data = NULL; | |
923 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 924 | |
31c7c7d2 CH |
925 | /* |
926 | * The aborted req will be completed on receiving the abort req. | |
927 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
928 | * as the device then is in a faulty state. | |
929 | */ | |
930 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
931 | } |
932 | ||
a4aea562 MB |
933 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
934 | { | |
9e866774 MW |
935 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
936 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
937 | if (nvmeq->sq_cmds) |
938 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
939 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
940 | kfree(nvmeq); | |
941 | } | |
942 | ||
a1a5ef99 | 943 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
944 | { |
945 | int i; | |
946 | ||
a1a5ef99 | 947 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 948 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 949 | dev->queue_count--; |
a4aea562 | 950 | dev->queues[i] = NULL; |
f435c282 | 951 | nvme_free_queue(nvmeq); |
121c7ad4 | 952 | } |
22404274 KB |
953 | } |
954 | ||
4d115420 KB |
955 | /** |
956 | * nvme_suspend_queue - put queue into suspended state | |
957 | * @nvmeq - queue to suspend | |
4d115420 KB |
958 | */ |
959 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 960 | { |
2b25d981 | 961 | int vector; |
b60503ba | 962 | |
a09115b2 | 963 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
964 | if (nvmeq->cq_vector == -1) { |
965 | spin_unlock_irq(&nvmeq->q_lock); | |
966 | return 1; | |
967 | } | |
dca51e78 | 968 | vector = nvmeq_irq(nvmeq); |
42f61420 | 969 | nvmeq->dev->online_queues--; |
2b25d981 | 970 | nvmeq->cq_vector = -1; |
a09115b2 MW |
971 | spin_unlock_irq(&nvmeq->q_lock); |
972 | ||
1c63dc66 | 973 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 974 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 975 | |
aba2080f | 976 | free_irq(vector, nvmeq); |
b60503ba | 977 | |
4d115420 KB |
978 | return 0; |
979 | } | |
b60503ba | 980 | |
a5cdb68c | 981 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 982 | { |
a5cdb68c | 983 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
984 | |
985 | if (!nvmeq) | |
986 | return; | |
987 | if (nvme_suspend_queue(nvmeq)) | |
988 | return; | |
989 | ||
a5cdb68c KB |
990 | if (shutdown) |
991 | nvme_shutdown_ctrl(&dev->ctrl); | |
992 | else | |
993 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
994 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
995 | |
996 | spin_lock_irq(&nvmeq->q_lock); | |
997 | nvme_process_cq(nvmeq); | |
998 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
999 | } |
1000 | ||
8ffaadf7 JD |
1001 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1002 | int entry_size) | |
1003 | { | |
1004 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1005 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1006 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1007 | |
1008 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1009 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1010 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1011 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1012 | |
1013 | /* | |
1014 | * Ensure the reduced q_depth is above some threshold where it | |
1015 | * would be better to map queues in system memory with the | |
1016 | * original depth | |
1017 | */ | |
1018 | if (q_depth < 64) | |
1019 | return -ENOMEM; | |
1020 | } | |
1021 | ||
1022 | return q_depth; | |
1023 | } | |
1024 | ||
1025 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1026 | int qid, int depth) | |
1027 | { | |
1028 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1029 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1030 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1031 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1032 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1033 | } else { | |
1034 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1035 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1036 | if (!nvmeq->sq_cmds) | |
1037 | return -ENOMEM; | |
1038 | } | |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
b60503ba | 1043 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1044 | int depth) |
b60503ba | 1045 | { |
a4aea562 | 1046 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1047 | if (!nvmeq) |
1048 | return NULL; | |
1049 | ||
e75ec752 | 1050 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1051 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1052 | if (!nvmeq->cqes) |
1053 | goto free_nvmeq; | |
b60503ba | 1054 | |
8ffaadf7 | 1055 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1056 | goto free_cqdma; |
1057 | ||
e75ec752 | 1058 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1059 | nvmeq->dev = dev; |
3193f07b | 1060 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1061 | dev->ctrl.instance, qid); |
b60503ba MW |
1062 | spin_lock_init(&nvmeq->q_lock); |
1063 | nvmeq->cq_head = 0; | |
82123460 | 1064 | nvmeq->cq_phase = 1; |
b80d5ccc | 1065 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1066 | nvmeq->q_depth = depth; |
c30341dc | 1067 | nvmeq->qid = qid; |
758dd7fd | 1068 | nvmeq->cq_vector = -1; |
a4aea562 | 1069 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1070 | dev->queue_count++; |
1071 | ||
b60503ba MW |
1072 | return nvmeq; |
1073 | ||
1074 | free_cqdma: | |
e75ec752 | 1075 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1076 | nvmeq->cq_dma_addr); |
1077 | free_nvmeq: | |
1078 | kfree(nvmeq); | |
1079 | return NULL; | |
1080 | } | |
1081 | ||
dca51e78 | 1082 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1083 | { |
58ffacb5 | 1084 | if (use_threaded_interrupts) |
dca51e78 CH |
1085 | return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check, |
1086 | nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq); | |
1087 | else | |
1088 | return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED, | |
1089 | nvmeq->irqname, nvmeq); | |
3001082c MW |
1090 | } |
1091 | ||
22404274 | 1092 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1093 | { |
22404274 | 1094 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1095 | |
7be50e93 | 1096 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1097 | nvmeq->sq_tail = 0; |
1098 | nvmeq->cq_head = 0; | |
1099 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1100 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1101 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1102 | dev->online_queues++; |
7be50e93 | 1103 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1104 | } |
1105 | ||
1106 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1107 | { | |
1108 | struct nvme_dev *dev = nvmeq->dev; | |
1109 | int result; | |
3f85d50b | 1110 | |
2b25d981 | 1111 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1112 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1113 | if (result < 0) | |
22404274 | 1114 | return result; |
b60503ba MW |
1115 | |
1116 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1117 | if (result < 0) | |
1118 | goto release_cq; | |
1119 | ||
dca51e78 | 1120 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1121 | if (result < 0) |
1122 | goto release_sq; | |
1123 | ||
22404274 | 1124 | nvme_init_queue(nvmeq, qid); |
22404274 | 1125 | return result; |
b60503ba MW |
1126 | |
1127 | release_sq: | |
1128 | adapter_delete_sq(dev, qid); | |
1129 | release_cq: | |
1130 | adapter_delete_cq(dev, qid); | |
22404274 | 1131 | return result; |
b60503ba MW |
1132 | } |
1133 | ||
a4aea562 | 1134 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1135 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1136 | .complete = nvme_complete_rq, |
a4aea562 | 1137 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1138 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1139 | .init_request = nvme_admin_init_request, |
1140 | .timeout = nvme_timeout, | |
1141 | }; | |
1142 | ||
1143 | static struct blk_mq_ops nvme_mq_ops = { | |
1144 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1145 | .complete = nvme_complete_rq, |
a4aea562 MB |
1146 | .init_hctx = nvme_init_hctx, |
1147 | .init_request = nvme_init_request, | |
dca51e78 | 1148 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1149 | .timeout = nvme_timeout, |
a0fa9647 | 1150 | .poll = nvme_poll, |
a4aea562 MB |
1151 | }; |
1152 | ||
ea191d2f KB |
1153 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1154 | { | |
1c63dc66 | 1155 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1156 | /* |
1157 | * If the controller was reset during removal, it's possible | |
1158 | * user requests may be waiting on a stopped queue. Start the | |
1159 | * queue to flush these to completion. | |
1160 | */ | |
1161 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1162 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1163 | blk_mq_free_tag_set(&dev->admin_tagset); |
1164 | } | |
1165 | } | |
1166 | ||
a4aea562 MB |
1167 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1168 | { | |
1c63dc66 | 1169 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1170 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1171 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1172 | |
1173 | /* | |
1174 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1175 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1176 | */ | |
1177 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1178 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1179 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1180 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1181 | dev->admin_tagset.driver_data = dev; |
1182 | ||
1183 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1184 | return -ENOMEM; | |
1185 | ||
1c63dc66 CH |
1186 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1187 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1188 | blk_mq_free_tag_set(&dev->admin_tagset); |
1189 | return -ENOMEM; | |
1190 | } | |
1c63dc66 | 1191 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1192 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1193 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1194 | return -ENODEV; |
1195 | } | |
0fb59cbc | 1196 | } else |
25646264 | 1197 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1198 | |
1199 | return 0; | |
1200 | } | |
1201 | ||
8d85fce7 | 1202 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1203 | { |
ba47e386 | 1204 | int result; |
b60503ba | 1205 | u32 aqa; |
7a67cbea | 1206 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1207 | struct nvme_queue *nvmeq; |
1208 | ||
8ef2074d | 1209 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
dfbac8c7 KB |
1210 | NVME_CAP_NSSRC(cap) : 0; |
1211 | ||
7a67cbea CH |
1212 | if (dev->subsystem && |
1213 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1214 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1215 | |
5fd4ce1b | 1216 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1217 | if (result < 0) |
1218 | return result; | |
b60503ba | 1219 | |
a4aea562 | 1220 | nvmeq = dev->queues[0]; |
cd638946 | 1221 | if (!nvmeq) { |
2b25d981 | 1222 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1223 | if (!nvmeq) |
1224 | return -ENOMEM; | |
cd638946 | 1225 | } |
b60503ba MW |
1226 | |
1227 | aqa = nvmeq->q_depth - 1; | |
1228 | aqa |= aqa << 16; | |
1229 | ||
7a67cbea CH |
1230 | writel(aqa, dev->bar + NVME_REG_AQA); |
1231 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1232 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1233 | |
5fd4ce1b | 1234 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1235 | if (result) |
d4875622 | 1236 | return result; |
a4aea562 | 1237 | |
2b25d981 | 1238 | nvmeq->cq_vector = 0; |
dca51e78 | 1239 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1240 | if (result) { |
1241 | nvmeq->cq_vector = -1; | |
d4875622 | 1242 | return result; |
758dd7fd | 1243 | } |
025c557a | 1244 | |
b60503ba MW |
1245 | return result; |
1246 | } | |
1247 | ||
c875a709 GP |
1248 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1249 | { | |
1250 | ||
1251 | /* If true, indicates loss of adapter communication, possibly by a | |
1252 | * NVMe Subsystem reset. | |
1253 | */ | |
1254 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1255 | ||
1256 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1257 | if (work_busy(&dev->reset_work)) | |
1258 | return false; | |
1259 | ||
1260 | /* We shouldn't reset unless the controller is on fatal error state | |
1261 | * _or_ if we lost the communication with it. | |
1262 | */ | |
1263 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1264 | return false; | |
1265 | ||
1266 | /* If PCI error recovery process is happening, we cannot reset or | |
1267 | * the recovery mechanism will surely fail. | |
1268 | */ | |
1269 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1270 | return false; | |
1271 | ||
1272 | return true; | |
1273 | } | |
1274 | ||
d2a61918 AL |
1275 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) |
1276 | { | |
1277 | /* Read a config register to help see what died. */ | |
1278 | u16 pci_status; | |
1279 | int result; | |
1280 | ||
1281 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1282 | &pci_status); | |
1283 | if (result == PCIBIOS_SUCCESSFUL) | |
1284 | dev_warn(dev->dev, | |
1285 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1286 | csts, pci_status); | |
1287 | else | |
1288 | dev_warn(dev->dev, | |
1289 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1290 | csts, result); | |
1291 | } | |
1292 | ||
2d55cd5f | 1293 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1294 | { |
2d55cd5f CH |
1295 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1296 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1297 | |
c875a709 GP |
1298 | /* Skip controllers under certain specific conditions. */ |
1299 | if (nvme_should_reset(dev, csts)) { | |
c5f6ce97 | 1300 | if (!nvme_reset(dev)) |
d2a61918 | 1301 | nvme_warn_reset(dev, csts); |
2d55cd5f | 1302 | return; |
1fa6aead | 1303 | } |
2d55cd5f CH |
1304 | |
1305 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1306 | } |
1307 | ||
749941f2 | 1308 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1309 | { |
949928c1 | 1310 | unsigned i, max; |
749941f2 | 1311 | int ret = 0; |
42f61420 | 1312 | |
749941f2 CH |
1313 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1314 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1315 | ret = -ENOMEM; | |
42f61420 | 1316 | break; |
749941f2 CH |
1317 | } |
1318 | } | |
42f61420 | 1319 | |
949928c1 KB |
1320 | max = min(dev->max_qid, dev->queue_count - 1); |
1321 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 | 1322 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1323 | if (ret) |
42f61420 | 1324 | break; |
27e8166c | 1325 | } |
749941f2 CH |
1326 | |
1327 | /* | |
1328 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1329 | * than the desired aount of queues, and even a controller without | |
1330 | * I/O queues an still be used to issue admin commands. This might | |
1331 | * be useful to upgrade a buggy firmware for example. | |
1332 | */ | |
1333 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1334 | } |
1335 | ||
202021c1 SB |
1336 | static ssize_t nvme_cmb_show(struct device *dev, |
1337 | struct device_attribute *attr, | |
1338 | char *buf) | |
1339 | { | |
1340 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1341 | ||
c965809c | 1342 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1343 | ndev->cmbloc, ndev->cmbsz); |
1344 | } | |
1345 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1346 | ||
8ffaadf7 JD |
1347 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1348 | { | |
1349 | u64 szu, size, offset; | |
8ffaadf7 JD |
1350 | resource_size_t bar_size; |
1351 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1352 | void __iomem *cmb; | |
1353 | dma_addr_t dma_addr; | |
1354 | ||
7a67cbea | 1355 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1356 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1357 | return NULL; | |
202021c1 | 1358 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1359 | |
202021c1 SB |
1360 | if (!use_cmb_sqes) |
1361 | return NULL; | |
8ffaadf7 JD |
1362 | |
1363 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1364 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1365 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1366 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1367 | |
1368 | if (offset > bar_size) | |
1369 | return NULL; | |
1370 | ||
1371 | /* | |
1372 | * Controllers may support a CMB size larger than their BAR, | |
1373 | * for example, due to being behind a bridge. Reduce the CMB to | |
1374 | * the reported size of the BAR | |
1375 | */ | |
1376 | if (size > bar_size - offset) | |
1377 | size = bar_size - offset; | |
1378 | ||
202021c1 | 1379 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1380 | cmb = ioremap_wc(dma_addr, size); |
1381 | if (!cmb) | |
1382 | return NULL; | |
1383 | ||
1384 | dev->cmb_dma_addr = dma_addr; | |
1385 | dev->cmb_size = size; | |
1386 | return cmb; | |
1387 | } | |
1388 | ||
1389 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1390 | { | |
1391 | if (dev->cmb) { | |
1392 | iounmap(dev->cmb); | |
1393 | dev->cmb = NULL; | |
1394 | } | |
1395 | } | |
1396 | ||
9d713c2b KB |
1397 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1398 | { | |
b80d5ccc | 1399 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1400 | } |
1401 | ||
8d85fce7 | 1402 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1403 | { |
a4aea562 | 1404 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1405 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
dca51e78 | 1406 | int result, nr_io_queues, size; |
b60503ba | 1407 | |
2800b8e7 | 1408 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1409 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1410 | if (result < 0) | |
1b23484b | 1411 | return result; |
9a0be7ab | 1412 | |
f5fa90dc | 1413 | if (nr_io_queues == 0) |
a5229050 | 1414 | return 0; |
b60503ba | 1415 | |
8ffaadf7 JD |
1416 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1417 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1418 | sizeof(struct nvme_command)); | |
1419 | if (result > 0) | |
1420 | dev->q_depth = result; | |
1421 | else | |
1422 | nvme_release_cmb(dev); | |
1423 | } | |
1424 | ||
9d713c2b KB |
1425 | size = db_bar_size(dev, nr_io_queues); |
1426 | if (size > 8192) { | |
f1938f6e | 1427 | iounmap(dev->bar); |
9d713c2b KB |
1428 | do { |
1429 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1430 | if (dev->bar) | |
1431 | break; | |
1432 | if (!--nr_io_queues) | |
1433 | return -ENOMEM; | |
1434 | size = db_bar_size(dev, nr_io_queues); | |
1435 | } while (1); | |
7a67cbea | 1436 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1437 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1438 | } |
1439 | ||
9d713c2b | 1440 | /* Deregister the admin queue's interrupt */ |
dca51e78 | 1441 | free_irq(pci_irq_vector(pdev, 0), adminq); |
9d713c2b | 1442 | |
e32efbfc JA |
1443 | /* |
1444 | * If we enable msix early due to not intx, disable it again before | |
1445 | * setting up the full range we need. | |
1446 | */ | |
dca51e78 CH |
1447 | pci_free_irq_vectors(pdev); |
1448 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1449 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1450 | if (nr_io_queues <= 0) | |
1451 | return -EIO; | |
1452 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1453 | |
063a8096 MW |
1454 | /* |
1455 | * Should investigate if there's a performance win from allocating | |
1456 | * more queues than interrupt vectors; it might allow the submission | |
1457 | * path to scale better, even if the receive path is limited by the | |
1458 | * number of interrupts. | |
1459 | */ | |
063a8096 | 1460 | |
dca51e78 | 1461 | result = queue_request_irq(adminq); |
758dd7fd JD |
1462 | if (result) { |
1463 | adminq->cq_vector = -1; | |
d4875622 | 1464 | return result; |
758dd7fd | 1465 | } |
749941f2 | 1466 | return nvme_create_io_queues(dev); |
b60503ba MW |
1467 | } |
1468 | ||
db3cbfff | 1469 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1470 | { |
db3cbfff | 1471 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1472 | |
db3cbfff KB |
1473 | blk_mq_free_request(req); |
1474 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1475 | } |
1476 | ||
db3cbfff | 1477 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1478 | { |
db3cbfff | 1479 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1480 | |
db3cbfff KB |
1481 | if (!error) { |
1482 | unsigned long flags; | |
1483 | ||
2e39e0f6 ML |
1484 | /* |
1485 | * We might be called with the AQ q_lock held | |
1486 | * and the I/O queue q_lock should always | |
1487 | * nest inside the AQ one. | |
1488 | */ | |
1489 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1490 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1491 | nvme_process_cq(nvmeq); |
1492 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1493 | } |
db3cbfff KB |
1494 | |
1495 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1496 | } |
1497 | ||
db3cbfff | 1498 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1499 | { |
db3cbfff KB |
1500 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1501 | struct request *req; | |
1502 | struct nvme_command cmd; | |
bda4e0fb | 1503 | |
db3cbfff KB |
1504 | memset(&cmd, 0, sizeof(cmd)); |
1505 | cmd.delete_queue.opcode = opcode; | |
1506 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1507 | |
eb71f435 | 1508 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1509 | if (IS_ERR(req)) |
1510 | return PTR_ERR(req); | |
bda4e0fb | 1511 | |
db3cbfff KB |
1512 | req->timeout = ADMIN_TIMEOUT; |
1513 | req->end_io_data = nvmeq; | |
1514 | ||
1515 | blk_execute_rq_nowait(q, NULL, req, false, | |
1516 | opcode == nvme_admin_delete_cq ? | |
1517 | nvme_del_cq_end : nvme_del_queue_end); | |
1518 | return 0; | |
bda4e0fb KB |
1519 | } |
1520 | ||
70659060 | 1521 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1522 | { |
70659060 | 1523 | int pass; |
db3cbfff KB |
1524 | unsigned long timeout; |
1525 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1526 | |
db3cbfff | 1527 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1528 | int sent = 0, i = queues; |
db3cbfff KB |
1529 | |
1530 | reinit_completion(&dev->ioq_wait); | |
1531 | retry: | |
1532 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1533 | for (; i > 0; i--, sent++) |
1534 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1535 | break; |
c21377f8 | 1536 | |
db3cbfff KB |
1537 | while (sent--) { |
1538 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1539 | if (timeout == 0) | |
1540 | return; | |
1541 | if (i) | |
1542 | goto retry; | |
1543 | } | |
1544 | opcode = nvme_admin_delete_cq; | |
1545 | } | |
a5768aa8 KB |
1546 | } |
1547 | ||
422ef0c7 MW |
1548 | /* |
1549 | * Return: error value if an error occurred setting up the queues or calling | |
1550 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1551 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1552 | * failures should be reported. | |
1553 | */ | |
8d85fce7 | 1554 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1555 | { |
5bae7f73 | 1556 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1557 | dev->tagset.ops = &nvme_mq_ops; |
1558 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1559 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1560 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1561 | dev->tagset.queue_depth = | |
a4aea562 | 1562 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1563 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1564 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1565 | dev->tagset.driver_data = dev; | |
b60503ba | 1566 | |
ffe7704d KB |
1567 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1568 | return 0; | |
5bae7f73 | 1569 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
1570 | } else { |
1571 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1572 | ||
1573 | /* Free previously allocated queues that are no longer usable */ | |
1574 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1575 | } |
949928c1 | 1576 | |
e1e5e564 | 1577 | return 0; |
b60503ba MW |
1578 | } |
1579 | ||
b00a726a | 1580 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1581 | { |
42f61420 | 1582 | u64 cap; |
b00a726a | 1583 | int result = -ENOMEM; |
e75ec752 | 1584 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1585 | |
1586 | if (pci_enable_device_mem(pdev)) | |
1587 | return result; | |
1588 | ||
0877cb0d | 1589 | pci_set_master(pdev); |
0877cb0d | 1590 | |
e75ec752 CH |
1591 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1592 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1593 | goto disable; |
0877cb0d | 1594 | |
7a67cbea | 1595 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1596 | result = -ENODEV; |
b00a726a | 1597 | goto disable; |
0e53d180 | 1598 | } |
e32efbfc JA |
1599 | |
1600 | /* | |
a5229050 KB |
1601 | * Some devices and/or platforms don't advertise or work with INTx |
1602 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1603 | * adjust this later. | |
e32efbfc | 1604 | */ |
dca51e78 CH |
1605 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1606 | if (result < 0) | |
1607 | return result; | |
e32efbfc | 1608 | |
7a67cbea CH |
1609 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1610 | ||
42f61420 KB |
1611 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1612 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1613 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1614 | |
1615 | /* | |
1616 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1617 | * some MacBook7,1 to avoid controller resets and data loss. | |
1618 | */ | |
1619 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1620 | dev->q_depth = 2; | |
1621 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1622 | "queue depth=%u to work around controller resets\n", | |
1623 | dev->q_depth); | |
1624 | } | |
1625 | ||
202021c1 SB |
1626 | /* |
1627 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1628 | * populate sysfs if a CMB is implemented. Note that we add the | |
1629 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1630 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1631 | * NULL as final argument to sysfs_add_file_to_group. | |
1632 | */ | |
1633 | ||
8ef2074d | 1634 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1635 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1636 | |
202021c1 SB |
1637 | if (dev->cmbsz) { |
1638 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1639 | &dev_attr_cmb.attr, NULL)) | |
1640 | dev_warn(dev->dev, | |
1641 | "failed to add sysfs attribute for CMB\n"); | |
1642 | } | |
1643 | } | |
1644 | ||
a0a3408e KB |
1645 | pci_enable_pcie_error_reporting(pdev); |
1646 | pci_save_state(pdev); | |
0877cb0d KB |
1647 | return 0; |
1648 | ||
1649 | disable: | |
0877cb0d KB |
1650 | pci_disable_device(pdev); |
1651 | return result; | |
1652 | } | |
1653 | ||
1654 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1655 | { |
1656 | if (dev->bar) | |
1657 | iounmap(dev->bar); | |
a1f447b3 | 1658 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1659 | } |
1660 | ||
1661 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1662 | { |
e75ec752 CH |
1663 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1664 | ||
dca51e78 | 1665 | pci_free_irq_vectors(pdev); |
0877cb0d | 1666 | |
a0a3408e KB |
1667 | if (pci_is_enabled(pdev)) { |
1668 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1669 | pci_disable_device(pdev); |
4d115420 | 1670 | } |
4d115420 KB |
1671 | } |
1672 | ||
a5cdb68c | 1673 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1674 | { |
70659060 | 1675 | int i, queues; |
7c1b2450 | 1676 | u32 csts = -1; |
22404274 | 1677 | |
2d55cd5f | 1678 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1679 | |
77bf25ea | 1680 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 1681 | if (pci_is_enabled(to_pci_dev(dev->dev))) { |
25646264 | 1682 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1683 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1684 | } |
c21377f8 | 1685 | |
70659060 | 1686 | queues = dev->online_queues - 1; |
c21377f8 GKB |
1687 | for (i = dev->queue_count - 1; i > 0; i--) |
1688 | nvme_suspend_queue(dev->queues[i]); | |
1689 | ||
7c1b2450 | 1690 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
82469c59 GKB |
1691 | /* A device might become IO incapable very soon during |
1692 | * probe, before the admin queue is configured. Thus, | |
1693 | * queue_count can be 0 here. | |
1694 | */ | |
1695 | if (dev->queue_count) | |
1696 | nvme_suspend_queue(dev->queues[0]); | |
4d115420 | 1697 | } else { |
70659060 | 1698 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 1699 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1700 | } |
b00a726a | 1701 | nvme_pci_disable(dev); |
07836e65 | 1702 | |
e1958e65 ML |
1703 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
1704 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
77bf25ea | 1705 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1706 | } |
1707 | ||
091b6092 MW |
1708 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1709 | { | |
e75ec752 | 1710 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1711 | PAGE_SIZE, PAGE_SIZE, 0); |
1712 | if (!dev->prp_page_pool) | |
1713 | return -ENOMEM; | |
1714 | ||
99802a7a | 1715 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1716 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1717 | 256, 256, 0); |
1718 | if (!dev->prp_small_pool) { | |
1719 | dma_pool_destroy(dev->prp_page_pool); | |
1720 | return -ENOMEM; | |
1721 | } | |
091b6092 MW |
1722 | return 0; |
1723 | } | |
1724 | ||
1725 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1726 | { | |
1727 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1728 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1729 | } |
1730 | ||
1673f1f0 | 1731 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1732 | { |
1673f1f0 | 1733 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1734 | |
e75ec752 | 1735 | put_device(dev->dev); |
4af0e21c KB |
1736 | if (dev->tagset.tags) |
1737 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1738 | if (dev->ctrl.admin_q) |
1739 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 1740 | kfree(dev->queues); |
5e82e952 KB |
1741 | kfree(dev); |
1742 | } | |
1743 | ||
f58944e2 KB |
1744 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1745 | { | |
237045fc | 1746 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1747 | |
1748 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1749 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1750 | if (!schedule_work(&dev->remove_work)) |
1751 | nvme_put_ctrl(&dev->ctrl); | |
1752 | } | |
1753 | ||
fd634f41 | 1754 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1755 | { |
fd634f41 | 1756 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
f58944e2 | 1757 | int result = -ENODEV; |
5e82e952 | 1758 | |
bb8d261e | 1759 | if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) |
fd634f41 | 1760 | goto out; |
5e82e952 | 1761 | |
fd634f41 CH |
1762 | /* |
1763 | * If we're called to reset a live controller first shut it down before | |
1764 | * moving on. | |
1765 | */ | |
b00a726a | 1766 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1767 | nvme_dev_disable(dev, false); |
5e82e952 | 1768 | |
bb8d261e | 1769 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
9bf2b972 KB |
1770 | goto out; |
1771 | ||
b00a726a | 1772 | result = nvme_pci_enable(dev); |
f0b50732 | 1773 | if (result) |
3cf519b5 | 1774 | goto out; |
f0b50732 KB |
1775 | |
1776 | result = nvme_configure_admin_queue(dev); | |
1777 | if (result) | |
f58944e2 | 1778 | goto out; |
f0b50732 | 1779 | |
a4aea562 | 1780 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1781 | result = nvme_alloc_admin_tags(dev); |
1782 | if (result) | |
f58944e2 | 1783 | goto out; |
b9afca3e | 1784 | |
ce4541f4 CH |
1785 | result = nvme_init_identify(&dev->ctrl); |
1786 | if (result) | |
f58944e2 | 1787 | goto out; |
ce4541f4 | 1788 | |
f0b50732 | 1789 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1790 | if (result) |
f58944e2 | 1791 | goto out; |
f0b50732 | 1792 | |
21f033f7 KB |
1793 | /* |
1794 | * A controller that can not execute IO typically requires user | |
1795 | * intervention to correct. For such degraded controllers, the driver | |
1796 | * should not submit commands the user did not request, so skip | |
1797 | * registering for asynchronous event notification on this condition. | |
1798 | */ | |
f866fc42 CH |
1799 | if (dev->online_queues > 1) |
1800 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 1801 | |
2d55cd5f | 1802 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1803 | |
2659e57b CH |
1804 | /* |
1805 | * Keep the controller around but remove all namespaces if we don't have | |
1806 | * any working I/O queue. | |
1807 | */ | |
3cf519b5 | 1808 | if (dev->online_queues < 2) { |
1b3c47c1 | 1809 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1810 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1811 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1812 | } else { |
25646264 | 1813 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1814 | nvme_dev_add(dev); |
1815 | } | |
1816 | ||
bb8d261e CH |
1817 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1818 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1819 | goto out; | |
1820 | } | |
92911a55 CH |
1821 | |
1822 | if (dev->online_queues > 1) | |
5955be21 | 1823 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 1824 | return; |
f0b50732 | 1825 | |
3cf519b5 | 1826 | out: |
f58944e2 | 1827 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1828 | } |
1829 | ||
5c8809e6 | 1830 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1831 | { |
5c8809e6 | 1832 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1833 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1834 | |
69d9a99c | 1835 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1836 | if (pci_get_drvdata(pdev)) |
921920ab | 1837 | device_release_driver(&pdev->dev); |
1673f1f0 | 1838 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1839 | } |
1840 | ||
4cc06521 | 1841 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1842 | { |
1c63dc66 | 1843 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1844 | return -ENODEV; |
c5f6ce97 KB |
1845 | if (work_busy(&dev->reset_work)) |
1846 | return -ENODEV; | |
846cc05f CH |
1847 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1848 | return -EBUSY; | |
846cc05f | 1849 | return 0; |
9a6b9458 KB |
1850 | } |
1851 | ||
1c63dc66 | 1852 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 1853 | { |
1c63dc66 | 1854 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 1855 | return 0; |
9ca97374 TH |
1856 | } |
1857 | ||
5fd4ce1b | 1858 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 1859 | { |
5fd4ce1b CH |
1860 | writel(val, to_nvme_dev(ctrl)->bar + off); |
1861 | return 0; | |
1862 | } | |
4cc06521 | 1863 | |
7fd8930f CH |
1864 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
1865 | { | |
1866 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
1867 | return 0; | |
4cc06521 KB |
1868 | } |
1869 | ||
f3ca80fc CH |
1870 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
1871 | { | |
c5f6ce97 KB |
1872 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
1873 | int ret = nvme_reset(dev); | |
1874 | ||
1875 | if (!ret) | |
1876 | flush_work(&dev->reset_work); | |
1877 | return ret; | |
4cc06521 | 1878 | } |
f3ca80fc | 1879 | |
1c63dc66 | 1880 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 1881 | .name = "pcie", |
e439bb12 | 1882 | .module = THIS_MODULE, |
1c63dc66 | 1883 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 1884 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 1885 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 1886 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 1887 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 1888 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 1889 | }; |
4cc06521 | 1890 | |
b00a726a KB |
1891 | static int nvme_dev_map(struct nvme_dev *dev) |
1892 | { | |
b00a726a KB |
1893 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1894 | ||
a1f447b3 | 1895 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
1896 | return -ENODEV; |
1897 | ||
1898 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1899 | if (!dev->bar) | |
1900 | goto release; | |
1901 | ||
9fa196e7 | 1902 | return 0; |
b00a726a | 1903 | release: |
9fa196e7 MG |
1904 | pci_release_mem_regions(pdev); |
1905 | return -ENODEV; | |
b00a726a KB |
1906 | } |
1907 | ||
8d85fce7 | 1908 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 1909 | { |
a4aea562 | 1910 | int node, result = -ENOMEM; |
b60503ba MW |
1911 | struct nvme_dev *dev; |
1912 | ||
a4aea562 MB |
1913 | node = dev_to_node(&pdev->dev); |
1914 | if (node == NUMA_NO_NODE) | |
2fa84351 | 1915 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
1916 | |
1917 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
1918 | if (!dev) |
1919 | return -ENOMEM; | |
a4aea562 MB |
1920 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
1921 | GFP_KERNEL, node); | |
b60503ba MW |
1922 | if (!dev->queues) |
1923 | goto free; | |
1924 | ||
e75ec752 | 1925 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 1926 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 1927 | |
b00a726a KB |
1928 | result = nvme_dev_map(dev); |
1929 | if (result) | |
1930 | goto free; | |
1931 | ||
f3ca80fc | 1932 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 1933 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
2d55cd5f CH |
1934 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
1935 | (unsigned long)dev); | |
77bf25ea | 1936 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 1937 | init_completion(&dev->ioq_wait); |
b60503ba | 1938 | |
091b6092 MW |
1939 | result = nvme_setup_prp_pools(dev); |
1940 | if (result) | |
a96d4f5c | 1941 | goto put_pci; |
4cc06521 | 1942 | |
f3ca80fc CH |
1943 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
1944 | id->driver_data); | |
4cc06521 | 1945 | if (result) |
2e1d8448 | 1946 | goto release_pools; |
740216fc | 1947 | |
1b3c47c1 SG |
1948 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
1949 | ||
92f7a162 | 1950 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
1951 | return 0; |
1952 | ||
0877cb0d | 1953 | release_pools: |
091b6092 | 1954 | nvme_release_prp_pools(dev); |
a96d4f5c | 1955 | put_pci: |
e75ec752 | 1956 | put_device(dev->dev); |
b00a726a | 1957 | nvme_dev_unmap(dev); |
b60503ba MW |
1958 | free: |
1959 | kfree(dev->queues); | |
b60503ba MW |
1960 | kfree(dev); |
1961 | return result; | |
1962 | } | |
1963 | ||
f0d54a54 KB |
1964 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
1965 | { | |
a6739479 | 1966 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 1967 | |
a6739479 | 1968 | if (prepare) |
a5cdb68c | 1969 | nvme_dev_disable(dev, false); |
a6739479 | 1970 | else |
c5f6ce97 | 1971 | nvme_reset(dev); |
f0d54a54 KB |
1972 | } |
1973 | ||
09ece142 KB |
1974 | static void nvme_shutdown(struct pci_dev *pdev) |
1975 | { | |
1976 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 1977 | nvme_dev_disable(dev, true); |
09ece142 KB |
1978 | } |
1979 | ||
f58944e2 KB |
1980 | /* |
1981 | * The driver's remove may be called on a device in a partially initialized | |
1982 | * state. This function must not have any dependencies on the device state in | |
1983 | * order to proceed. | |
1984 | */ | |
8d85fce7 | 1985 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
1986 | { |
1987 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 1988 | |
bb8d261e CH |
1989 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
1990 | ||
9a6b9458 | 1991 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 KB |
1992 | |
1993 | if (!pci_device_is_present(pdev)) | |
1994 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); | |
1995 | ||
9bf2b972 | 1996 | flush_work(&dev->reset_work); |
53029b04 | 1997 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 1998 | nvme_dev_disable(dev, true); |
a4aea562 | 1999 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2000 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2001 | nvme_release_cmb(dev); |
9a6b9458 | 2002 | nvme_release_prp_pools(dev); |
b00a726a | 2003 | nvme_dev_unmap(dev); |
1673f1f0 | 2004 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2005 | } |
2006 | ||
13880f5b KB |
2007 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2008 | { | |
2009 | int ret = 0; | |
2010 | ||
2011 | if (numvfs == 0) { | |
2012 | if (pci_vfs_assigned(pdev)) { | |
2013 | dev_warn(&pdev->dev, | |
2014 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2015 | return -EPERM; | |
2016 | } | |
2017 | pci_disable_sriov(pdev); | |
2018 | return 0; | |
2019 | } | |
2020 | ||
2021 | ret = pci_enable_sriov(pdev, numvfs); | |
2022 | return ret ? ret : numvfs; | |
2023 | } | |
2024 | ||
671a6018 | 2025 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2026 | static int nvme_suspend(struct device *dev) |
2027 | { | |
2028 | struct pci_dev *pdev = to_pci_dev(dev); | |
2029 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2030 | ||
a5cdb68c | 2031 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2032 | return 0; |
2033 | } | |
2034 | ||
2035 | static int nvme_resume(struct device *dev) | |
2036 | { | |
2037 | struct pci_dev *pdev = to_pci_dev(dev); | |
2038 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2039 | |
c5f6ce97 | 2040 | nvme_reset(ndev); |
9a6b9458 | 2041 | return 0; |
cd638946 | 2042 | } |
671a6018 | 2043 | #endif |
cd638946 KB |
2044 | |
2045 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2046 | |
a0a3408e KB |
2047 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2048 | pci_channel_state_t state) | |
2049 | { | |
2050 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2051 | ||
2052 | /* | |
2053 | * A frozen channel requires a reset. When detected, this method will | |
2054 | * shutdown the controller to quiesce. The controller will be restarted | |
2055 | * after the slot reset through driver's slot_reset callback. | |
2056 | */ | |
a0a3408e KB |
2057 | switch (state) { |
2058 | case pci_channel_io_normal: | |
2059 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2060 | case pci_channel_io_frozen: | |
d011fb31 KB |
2061 | dev_warn(dev->ctrl.device, |
2062 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2063 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2064 | return PCI_ERS_RESULT_NEED_RESET; |
2065 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2066 | dev_warn(dev->ctrl.device, |
2067 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2068 | return PCI_ERS_RESULT_DISCONNECT; |
2069 | } | |
2070 | return PCI_ERS_RESULT_NEED_RESET; | |
2071 | } | |
2072 | ||
2073 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2074 | { | |
2075 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2076 | ||
1b3c47c1 | 2077 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2078 | pci_restore_state(pdev); |
c5f6ce97 | 2079 | nvme_reset(dev); |
a0a3408e KB |
2080 | return PCI_ERS_RESULT_RECOVERED; |
2081 | } | |
2082 | ||
2083 | static void nvme_error_resume(struct pci_dev *pdev) | |
2084 | { | |
2085 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2086 | } | |
2087 | ||
1d352035 | 2088 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2089 | .error_detected = nvme_error_detected, |
b60503ba MW |
2090 | .slot_reset = nvme_slot_reset, |
2091 | .resume = nvme_error_resume, | |
f0d54a54 | 2092 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2093 | }; |
2094 | ||
6eb0d698 | 2095 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2096 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 KB |
2097 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
2098 | NVME_QUIRK_DISCARD_ZEROES, }, | |
99466e70 KB |
2099 | { PCI_VDEVICE(INTEL, 0x0a53), |
2100 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2101 | NVME_QUIRK_DISCARD_ZEROES, }, | |
2102 | { PCI_VDEVICE(INTEL, 0x0a54), | |
2103 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2104 | NVME_QUIRK_DISCARD_ZEROES, }, | |
540c801c KB |
2105 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2106 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2107 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2108 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2109 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2110 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2111 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2112 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2113 | { 0, } |
2114 | }; | |
2115 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2116 | ||
2117 | static struct pci_driver nvme_driver = { | |
2118 | .name = "nvme", | |
2119 | .id_table = nvme_id_table, | |
2120 | .probe = nvme_probe, | |
8d85fce7 | 2121 | .remove = nvme_remove, |
09ece142 | 2122 | .shutdown = nvme_shutdown, |
cd638946 KB |
2123 | .driver = { |
2124 | .pm = &nvme_dev_pm_ops, | |
2125 | }, | |
13880f5b | 2126 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2127 | .err_handler = &nvme_err_handler, |
2128 | }; | |
2129 | ||
2130 | static int __init nvme_init(void) | |
2131 | { | |
0ac13140 | 2132 | int result; |
1fa6aead | 2133 | |
92f7a162 | 2134 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2135 | if (!nvme_workq) |
b9afca3e | 2136 | return -ENOMEM; |
9a6b9458 | 2137 | |
f3db22fe KB |
2138 | result = pci_register_driver(&nvme_driver); |
2139 | if (result) | |
576d55d6 | 2140 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2141 | return result; |
2142 | } | |
2143 | ||
2144 | static void __exit nvme_exit(void) | |
2145 | { | |
2146 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2147 | destroy_workqueue(nvme_workq); |
21bd78bc | 2148 | _nvme_check_size(); |
b60503ba MW |
2149 | } |
2150 | ||
2151 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2152 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2153 | MODULE_VERSION("1.0"); |
b60503ba MW |
2154 | module_init(nvme_init); |
2155 | module_exit(nvme_exit); |