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bb38919e SC |
1 | /* |
2 | * PCIe host controller driver for Freescale i.MX6 SoCs | |
3 | * | |
4 | * Copyright (C) 2013 Kosagi | |
5 | * http://www.kosagi.com | |
6 | * | |
7 | * Author: Sean Cross <xobs@kosagi.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/mfd/syscon.h> | |
19 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_gpio.h> | |
e6f1fef0 | 22 | #include <linux/of_device.h> |
bb38919e SC |
23 | #include <linux/pci.h> |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/regmap.h> | |
26 | #include <linux/resource.h> | |
27 | #include <linux/signal.h> | |
28 | #include <linux/types.h> | |
d1dc9749 | 29 | #include <linux/interrupt.h> |
bb38919e SC |
30 | |
31 | #include "pcie-designware.h" | |
32 | ||
33 | #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) | |
34 | ||
e6f1fef0 AS |
35 | enum imx6_pcie_variants { |
36 | IMX6Q, | |
4d31c610 AS |
37 | IMX6SX, |
38 | IMX6QP, | |
e6f1fef0 AS |
39 | }; |
40 | ||
bb38919e | 41 | struct imx6_pcie { |
b2d7a9cd | 42 | int reset_gpio; |
3ea8529a | 43 | bool gpio_active_high; |
57526136 LS |
44 | struct clk *pcie_bus; |
45 | struct clk *pcie_phy; | |
e3c06cd0 | 46 | struct clk *pcie_inbound_axi; |
57526136 | 47 | struct clk *pcie; |
bb38919e SC |
48 | struct pcie_port pp; |
49 | struct regmap *iomuxc_gpr; | |
e6f1fef0 | 50 | enum imx6_pcie_variants variant; |
28e3abe5 JW |
51 | u32 tx_deemph_gen1; |
52 | u32 tx_deemph_gen2_3p5db; | |
53 | u32 tx_deemph_gen2_6db; | |
54 | u32 tx_swing_full; | |
55 | u32 tx_swing_low; | |
a5fcec48 | 56 | int link_gen; |
bb38919e SC |
57 | }; |
58 | ||
fa33a6d8 MV |
59 | /* PCIe Root Complex registers (memory-mapped) */ |
60 | #define PCIE_RC_LCR 0x7c | |
61 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 | |
62 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 | |
63 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf | |
64 | ||
2393f79c BH |
65 | #define PCIE_RC_LCSR 0x80 |
66 | ||
bb38919e SC |
67 | /* PCIe Port Logic registers (memory-mapped) */ |
68 | #define PL_OFFSET 0x700 | |
3e3e406e LS |
69 | #define PCIE_PL_PFLR (PL_OFFSET + 0x08) |
70 | #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) | |
71 | #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) | |
bb38919e SC |
72 | #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) |
73 | #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) | |
7f9f40c0 MV |
74 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) |
75 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) | |
bb38919e SC |
76 | |
77 | #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) | |
78 | #define PCIE_PHY_CTRL_DATA_LOC 0 | |
79 | #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 | |
80 | #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 | |
81 | #define PCIE_PHY_CTRL_WR_LOC 18 | |
82 | #define PCIE_PHY_CTRL_RD_LOC 19 | |
83 | ||
84 | #define PCIE_PHY_STAT (PL_OFFSET + 0x110) | |
85 | #define PCIE_PHY_STAT_ACK_LOC 16 | |
86 | ||
fa33a6d8 MV |
87 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
88 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | |
89 | ||
bb38919e SC |
90 | /* PHY registers (not memory-mapped) */ |
91 | #define PCIE_PHY_RX_ASIC_OUT 0x100D | |
111feb7f | 92 | #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) |
bb38919e SC |
93 | |
94 | #define PHY_RX_OVRD_IN_LO 0x1005 | |
95 | #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) | |
96 | #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) | |
97 | ||
98 | static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) | |
99 | { | |
100 | u32 val; | |
101 | u32 max_iterations = 10; | |
102 | u32 wait_counter = 0; | |
103 | ||
104 | do { | |
105 | val = readl(dbi_base + PCIE_PHY_STAT); | |
106 | val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; | |
107 | wait_counter++; | |
108 | ||
109 | if (val == exp_val) | |
110 | return 0; | |
111 | ||
112 | udelay(1); | |
113 | } while (wait_counter < max_iterations); | |
114 | ||
115 | return -ETIMEDOUT; | |
116 | } | |
117 | ||
118 | static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) | |
119 | { | |
120 | u32 val; | |
121 | int ret; | |
122 | ||
123 | val = addr << PCIE_PHY_CTRL_DATA_LOC; | |
124 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
125 | ||
126 | val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); | |
127 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
128 | ||
129 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
130 | if (ret) | |
131 | return ret; | |
132 | ||
133 | val = addr << PCIE_PHY_CTRL_DATA_LOC; | |
134 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
135 | ||
8d1ceb52 | 136 | return pcie_phy_poll_ack(dbi_base, 0); |
bb38919e SC |
137 | } |
138 | ||
139 | /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ | |
ff3ce480 | 140 | static int pcie_phy_read(void __iomem *dbi_base, int addr, int *data) |
bb38919e SC |
141 | { |
142 | u32 val, phy_ctl; | |
143 | int ret; | |
144 | ||
145 | ret = pcie_phy_wait_ack(dbi_base, addr); | |
146 | if (ret) | |
147 | return ret; | |
148 | ||
149 | /* assert Read signal */ | |
150 | phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; | |
151 | writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); | |
152 | ||
153 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
154 | if (ret) | |
155 | return ret; | |
156 | ||
157 | val = readl(dbi_base + PCIE_PHY_STAT); | |
158 | *data = val & 0xffff; | |
159 | ||
160 | /* deassert Read signal */ | |
161 | writel(0x00, dbi_base + PCIE_PHY_CTRL); | |
162 | ||
8d1ceb52 | 163 | return pcie_phy_poll_ack(dbi_base, 0); |
bb38919e SC |
164 | } |
165 | ||
166 | static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) | |
167 | { | |
168 | u32 var; | |
169 | int ret; | |
170 | ||
171 | /* write addr */ | |
172 | /* cap addr */ | |
173 | ret = pcie_phy_wait_ack(dbi_base, addr); | |
174 | if (ret) | |
175 | return ret; | |
176 | ||
177 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
178 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
179 | ||
180 | /* capture data */ | |
181 | var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); | |
182 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
183 | ||
184 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
185 | if (ret) | |
186 | return ret; | |
187 | ||
188 | /* deassert cap data */ | |
189 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
190 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
191 | ||
192 | /* wait for ack de-assertion */ | |
193 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
194 | if (ret) | |
195 | return ret; | |
196 | ||
197 | /* assert wr signal */ | |
198 | var = 0x1 << PCIE_PHY_CTRL_WR_LOC; | |
199 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
200 | ||
201 | /* wait for ack */ | |
202 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
203 | if (ret) | |
204 | return ret; | |
205 | ||
206 | /* deassert wr signal */ | |
207 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
208 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
209 | ||
210 | /* wait for ack de-assertion */ | |
211 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
212 | if (ret) | |
213 | return ret; | |
214 | ||
215 | writel(0x0, dbi_base + PCIE_PHY_CTRL); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
53eeb48b LS |
220 | static void imx6_pcie_reset_phy(struct pcie_port *pp) |
221 | { | |
222 | u32 tmp; | |
223 | ||
224 | pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp); | |
225 | tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | | |
226 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); | |
227 | pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp); | |
228 | ||
229 | usleep_range(2000, 3000); | |
230 | ||
231 | pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp); | |
232 | tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | | |
233 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); | |
234 | pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp); | |
235 | } | |
236 | ||
bb38919e SC |
237 | /* Added for PCI abort handling */ |
238 | static int imx6q_pcie_abort_handler(unsigned long addr, | |
239 | unsigned int fsr, struct pt_regs *regs) | |
240 | { | |
bb38919e SC |
241 | return 0; |
242 | } | |
243 | ||
244 | static int imx6_pcie_assert_core_reset(struct pcie_port *pp) | |
245 | { | |
246 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
3e3e406e LS |
247 | u32 val, gpr1, gpr12; |
248 | ||
e6f1fef0 AS |
249 | switch (imx6_pcie->variant) { |
250 | case IMX6SX: | |
e3c06cd0 CF |
251 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
252 | IMX6SX_GPR12_PCIE_TEST_POWERDOWN, | |
253 | IMX6SX_GPR12_PCIE_TEST_POWERDOWN); | |
254 | /* Force PCIe PHY reset */ | |
255 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, | |
256 | IMX6SX_GPR5_PCIE_BTNRST_RESET, | |
257 | IMX6SX_GPR5_PCIE_BTNRST_RESET); | |
e6f1fef0 | 258 | break; |
4d31c610 AS |
259 | case IMX6QP: |
260 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
261 | IMX6Q_GPR1_PCIE_SW_RST, | |
262 | IMX6Q_GPR1_PCIE_SW_RST); | |
263 | break; | |
e6f1fef0 AS |
264 | case IMX6Q: |
265 | /* | |
266 | * If the bootloader already enabled the link we need some | |
267 | * special handling to get the core back into a state where | |
268 | * it is safe to touch it for configuration. As there is | |
269 | * no dedicated reset signal wired up for MX6QDL, we need | |
270 | * to manually force LTSSM into "detect" state before | |
271 | * completely disabling LTSSM, which is a prerequisite for | |
272 | * core configuration. | |
273 | * | |
274 | * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we | |
275 | * have a strong indication that the bootloader activated | |
276 | * the link. | |
277 | */ | |
278 | regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1); | |
279 | regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12); | |
280 | ||
281 | if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && | |
282 | (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { | |
283 | val = readl(pp->dbi_base + PCIE_PL_PFLR); | |
284 | val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; | |
285 | val |= PCIE_PL_PFLR_FORCE_LINK; | |
286 | writel(val, pp->dbi_base + PCIE_PL_PFLR); | |
287 | ||
288 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
289 | IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); | |
290 | } | |
3e3e406e | 291 | |
e6f1fef0 AS |
292 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
293 | IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); | |
294 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
295 | IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); | |
296 | break; | |
3e3e406e | 297 | } |
bb38919e | 298 | |
bb38919e SC |
299 | return 0; |
300 | } | |
301 | ||
4d1821e7 BH |
302 | static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) |
303 | { | |
e3c06cd0 | 304 | struct pcie_port *pp = &imx6_pcie->pp; |
13957652 | 305 | struct device *dev = pp->dev; |
e6f1fef0 | 306 | int ret = 0; |
e3c06cd0 | 307 | |
e6f1fef0 AS |
308 | switch (imx6_pcie->variant) { |
309 | case IMX6SX: | |
e3c06cd0 CF |
310 | ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); |
311 | if (ret) { | |
13957652 | 312 | dev_err(dev, "unable to enable pcie_axi clock\n"); |
e6f1fef0 | 313 | break; |
e3c06cd0 CF |
314 | } |
315 | ||
316 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
317 | IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); | |
e6f1fef0 | 318 | break; |
4d31c610 | 319 | case IMX6QP: /* FALLTHROUGH */ |
e6f1fef0 AS |
320 | case IMX6Q: |
321 | /* power up core phy and enable ref clock */ | |
322 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
323 | IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); | |
324 | /* | |
325 | * the async reset input need ref clock to sync internally, | |
326 | * when the ref clock comes after reset, internal synced | |
327 | * reset time is too short, cannot meet the requirement. | |
328 | * add one ~10us delay here. | |
329 | */ | |
330 | udelay(10); | |
331 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
332 | IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); | |
333 | break; | |
e3c06cd0 CF |
334 | } |
335 | ||
e6f1fef0 | 336 | return ret; |
4d1821e7 BH |
337 | } |
338 | ||
bb38919e SC |
339 | static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) |
340 | { | |
341 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
13957652 | 342 | struct device *dev = pp->dev; |
bb38919e SC |
343 | int ret; |
344 | ||
57526136 | 345 | ret = clk_prepare_enable(imx6_pcie->pcie_phy); |
bb38919e | 346 | if (ret) { |
13957652 | 347 | dev_err(dev, "unable to enable pcie_phy clock\n"); |
57526136 | 348 | goto err_pcie_phy; |
bb38919e SC |
349 | } |
350 | ||
57526136 | 351 | ret = clk_prepare_enable(imx6_pcie->pcie_bus); |
bb38919e | 352 | if (ret) { |
13957652 | 353 | dev_err(dev, "unable to enable pcie_bus clock\n"); |
57526136 | 354 | goto err_pcie_bus; |
bb38919e SC |
355 | } |
356 | ||
57526136 | 357 | ret = clk_prepare_enable(imx6_pcie->pcie); |
bb38919e | 358 | if (ret) { |
13957652 | 359 | dev_err(dev, "unable to enable pcie clock\n"); |
57526136 | 360 | goto err_pcie; |
bb38919e SC |
361 | } |
362 | ||
4d1821e7 BH |
363 | ret = imx6_pcie_enable_ref_clk(imx6_pcie); |
364 | if (ret) { | |
13957652 | 365 | dev_err(dev, "unable to enable pcie ref clock\n"); |
4d1821e7 BH |
366 | goto err_ref_clk; |
367 | } | |
3fce0e88 | 368 | |
a2fa6f64 RZ |
369 | /* allow the clocks to stabilize */ |
370 | usleep_range(200, 500); | |
371 | ||
bc9ef770 | 372 | /* Some boards don't have PCIe reset GPIO. */ |
b2d7a9cd | 373 | if (gpio_is_valid(imx6_pcie->reset_gpio)) { |
3ea8529a PŠ |
374 | gpio_set_value_cansleep(imx6_pcie->reset_gpio, |
375 | imx6_pcie->gpio_active_high); | |
bc9ef770 | 376 | msleep(100); |
3ea8529a PŠ |
377 | gpio_set_value_cansleep(imx6_pcie->reset_gpio, |
378 | !imx6_pcie->gpio_active_high); | |
bc9ef770 | 379 | } |
e3c06cd0 | 380 | |
4d31c610 AS |
381 | switch (imx6_pcie->variant) { |
382 | case IMX6SX: | |
e3c06cd0 CF |
383 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, |
384 | IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); | |
4d31c610 AS |
385 | break; |
386 | case IMX6QP: | |
387 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
388 | IMX6Q_GPR1_PCIE_SW_RST, 0); | |
389 | ||
390 | usleep_range(200, 500); | |
391 | break; | |
392 | case IMX6Q: /* Nothing to do */ | |
393 | break; | |
394 | } | |
e3c06cd0 | 395 | |
bb38919e SC |
396 | return 0; |
397 | ||
4d1821e7 BH |
398 | err_ref_clk: |
399 | clk_disable_unprepare(imx6_pcie->pcie); | |
57526136 LS |
400 | err_pcie: |
401 | clk_disable_unprepare(imx6_pcie->pcie_bus); | |
402 | err_pcie_bus: | |
403 | clk_disable_unprepare(imx6_pcie->pcie_phy); | |
404 | err_pcie_phy: | |
bb38919e | 405 | return ret; |
bb38919e SC |
406 | } |
407 | ||
408 | static void imx6_pcie_init_phy(struct pcie_port *pp) | |
409 | { | |
410 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
411 | ||
e6f1fef0 | 412 | if (imx6_pcie->variant == IMX6SX) |
e3c06cd0 CF |
413 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
414 | IMX6SX_GPR12_PCIE_RX_EQ_MASK, | |
415 | IMX6SX_GPR12_PCIE_RX_EQ_2); | |
e3c06cd0 | 416 | |
bb38919e SC |
417 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
418 | IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); | |
419 | ||
420 | /* configure constant input signal to the pcie ctrl and phy */ | |
421 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
422 | IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); | |
423 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
424 | IMX6Q_GPR12_LOS_LEVEL, 9 << 4); | |
425 | ||
426 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
28e3abe5 JW |
427 | IMX6Q_GPR8_TX_DEEMPH_GEN1, |
428 | imx6_pcie->tx_deemph_gen1 << 0); | |
bb38919e | 429 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
28e3abe5 JW |
430 | IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, |
431 | imx6_pcie->tx_deemph_gen2_3p5db << 6); | |
bb38919e | 432 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
28e3abe5 JW |
433 | IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, |
434 | imx6_pcie->tx_deemph_gen2_6db << 12); | |
bb38919e | 435 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
28e3abe5 JW |
436 | IMX6Q_GPR8_TX_SWING_FULL, |
437 | imx6_pcie->tx_swing_full << 18); | |
bb38919e | 438 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
28e3abe5 JW |
439 | IMX6Q_GPR8_TX_SWING_LOW, |
440 | imx6_pcie->tx_swing_low << 25); | |
bb38919e SC |
441 | } |
442 | ||
66a60f93 MV |
443 | static int imx6_pcie_wait_for_link(struct pcie_port *pp) |
444 | { | |
13957652 BH |
445 | struct device *dev = pp->dev; |
446 | ||
886bc5ce JP |
447 | /* check if the link is up or not */ |
448 | if (!dw_pcie_wait_for_link(pp)) | |
449 | return 0; | |
66a60f93 | 450 | |
13957652 | 451 | dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", |
6cbb247e BH |
452 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), |
453 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); | |
886bc5ce | 454 | return -ETIMEDOUT; |
66a60f93 MV |
455 | } |
456 | ||
a0427464 TK |
457 | static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp) |
458 | { | |
13957652 | 459 | struct device *dev = pp->dev; |
1c7fae18 | 460 | u32 tmp; |
a0427464 TK |
461 | unsigned int retries; |
462 | ||
463 | for (retries = 0; retries < 200; retries++) { | |
464 | tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
465 | /* Test if the speed change finished. */ | |
466 | if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) | |
467 | return 0; | |
468 | usleep_range(100, 1000); | |
469 | } | |
470 | ||
13957652 | 471 | dev_err(dev, "Speed change timeout\n"); |
a0427464 | 472 | return -EINVAL; |
66a60f93 MV |
473 | } |
474 | ||
d1dc9749 LS |
475 | static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg) |
476 | { | |
477 | struct pcie_port *pp = arg; | |
478 | ||
479 | return dw_handle_msi_irq(pp); | |
480 | } | |
481 | ||
fd5da208 | 482 | static int imx6_pcie_establish_link(struct pcie_port *pp) |
bb38919e | 483 | { |
bb38919e | 484 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); |
13957652 | 485 | struct device *dev = pp->dev; |
1c7fae18 | 486 | u32 tmp; |
a0427464 | 487 | int ret; |
fa33a6d8 MV |
488 | |
489 | /* | |
490 | * Force Gen1 operation when starting the link. In case the link is | |
491 | * started in Gen2 mode, there is a possibility the devices on the | |
492 | * bus will not be detected at all. This happens with PCIe switches. | |
493 | */ | |
494 | tmp = readl(pp->dbi_base + PCIE_RC_LCR); | |
495 | tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; | |
496 | tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; | |
497 | writel(tmp, pp->dbi_base + PCIE_RC_LCR); | |
498 | ||
499 | /* Start LTSSM. */ | |
500 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
501 | IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); | |
502 | ||
503 | ret = imx6_pcie_wait_for_link(pp); | |
54a47a83 | 504 | if (ret) { |
13957652 | 505 | dev_info(dev, "Link never came up\n"); |
54a47a83 LS |
506 | goto err_reset_phy; |
507 | } | |
fa33a6d8 | 508 | |
a5fcec48 TH |
509 | if (imx6_pcie->link_gen == 2) { |
510 | /* Allow Gen2 mode after the link is up. */ | |
511 | tmp = readl(pp->dbi_base + PCIE_RC_LCR); | |
512 | tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; | |
513 | tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; | |
514 | writel(tmp, pp->dbi_base + PCIE_RC_LCR); | |
515 | } else { | |
13957652 | 516 | dev_info(dev, "Link: Gen2 disabled\n"); |
a5fcec48 | 517 | } |
fa33a6d8 MV |
518 | |
519 | /* | |
520 | * Start Directed Speed Change so the best possible speed both link | |
521 | * partners support can be negotiated. | |
522 | */ | |
523 | tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
524 | tmp |= PORT_LOGIC_SPEED_CHANGE; | |
525 | writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
526 | ||
a0427464 TK |
527 | ret = imx6_pcie_wait_for_speed_change(pp); |
528 | if (ret) { | |
13957652 | 529 | dev_err(dev, "Failed to bring link up!\n"); |
54a47a83 | 530 | goto err_reset_phy; |
fa33a6d8 MV |
531 | } |
532 | ||
533 | /* Make sure link training is finished as well! */ | |
a0427464 | 534 | ret = imx6_pcie_wait_for_link(pp); |
fa33a6d8 | 535 | if (ret) { |
13957652 | 536 | dev_err(dev, "Failed to bring link up!\n"); |
54a47a83 | 537 | goto err_reset_phy; |
fa33a6d8 MV |
538 | } |
539 | ||
2393f79c | 540 | tmp = readl(pp->dbi_base + PCIE_RC_LCSR); |
13957652 | 541 | dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); |
a0427464 | 542 | return 0; |
54a47a83 LS |
543 | |
544 | err_reset_phy: | |
13957652 | 545 | dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", |
54a47a83 LS |
546 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), |
547 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); | |
548 | imx6_pcie_reset_phy(pp); | |
549 | ||
550 | return ret; | |
fa33a6d8 MV |
551 | } |
552 | ||
553 | static void imx6_pcie_host_init(struct pcie_port *pp) | |
554 | { | |
bb38919e SC |
555 | imx6_pcie_assert_core_reset(pp); |
556 | ||
557 | imx6_pcie_init_phy(pp); | |
558 | ||
559 | imx6_pcie_deassert_core_reset(pp); | |
560 | ||
561 | dw_pcie_setup_rc(pp); | |
562 | ||
fd5da208 | 563 | imx6_pcie_establish_link(pp); |
d1dc9749 LS |
564 | |
565 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
566 | dw_pcie_msi_init(pp); | |
bb38919e SC |
567 | } |
568 | ||
569 | static int imx6_pcie_link_up(struct pcie_port *pp) | |
570 | { | |
4d107d3b LS |
571 | return readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & |
572 | PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; | |
bb38919e SC |
573 | } |
574 | ||
575 | static struct pcie_host_ops imx6_pcie_host_ops = { | |
576 | .link_up = imx6_pcie_link_up, | |
577 | .host_init = imx6_pcie_host_init, | |
578 | }; | |
579 | ||
44cb5e94 | 580 | static int __init imx6_add_pcie_port(struct pcie_port *pp, |
bb38919e SC |
581 | struct platform_device *pdev) |
582 | { | |
13957652 | 583 | struct device *dev = pp->dev; |
bb38919e SC |
584 | int ret; |
585 | ||
d1dc9749 LS |
586 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
587 | pp->msi_irq = platform_get_irq_byname(pdev, "msi"); | |
588 | if (pp->msi_irq <= 0) { | |
13957652 | 589 | dev_err(dev, "failed to get MSI irq\n"); |
d1dc9749 LS |
590 | return -ENODEV; |
591 | } | |
592 | ||
13957652 | 593 | ret = devm_request_irq(dev, pp->msi_irq, |
d88a7ef9 | 594 | imx6_pcie_msi_handler, |
8ff0ef99 GS |
595 | IRQF_SHARED | IRQF_NO_THREAD, |
596 | "mx6-pcie-msi", pp); | |
d1dc9749 | 597 | if (ret) { |
13957652 | 598 | dev_err(dev, "failed to request MSI irq\n"); |
89b2d4f1 | 599 | return ret; |
d1dc9749 LS |
600 | } |
601 | } | |
602 | ||
bb38919e SC |
603 | pp->root_bus_nr = -1; |
604 | pp->ops = &imx6_pcie_host_ops; | |
605 | ||
bb38919e SC |
606 | ret = dw_pcie_host_init(pp); |
607 | if (ret) { | |
13957652 | 608 | dev_err(dev, "failed to initialize host\n"); |
bb38919e SC |
609 | return ret; |
610 | } | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
615 | static int __init imx6_pcie_probe(struct platform_device *pdev) | |
616 | { | |
13957652 | 617 | struct device *dev = &pdev->dev; |
bb38919e SC |
618 | struct imx6_pcie *imx6_pcie; |
619 | struct pcie_port *pp; | |
bb38919e | 620 | struct resource *dbi_base; |
13957652 | 621 | struct device_node *node = dev->of_node; |
bb38919e SC |
622 | int ret; |
623 | ||
13957652 | 624 | imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); |
bb38919e SC |
625 | if (!imx6_pcie) |
626 | return -ENOMEM; | |
627 | ||
628 | pp = &imx6_pcie->pp; | |
13957652 | 629 | pp->dev = dev; |
bb38919e | 630 | |
e6f1fef0 | 631 | imx6_pcie->variant = |
13957652 | 632 | (enum imx6_pcie_variants)of_device_get_match_data(dev); |
e3c06cd0 | 633 | |
bb38919e SC |
634 | /* Added for PCI abort handling */ |
635 | hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, | |
636 | "imprecise external abort"); | |
637 | ||
638 | dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
13957652 | 639 | pp->dbi_base = devm_ioremap_resource(dev, dbi_base); |
b391bf31 FE |
640 | if (IS_ERR(pp->dbi_base)) |
641 | return PTR_ERR(pp->dbi_base); | |
bb38919e SC |
642 | |
643 | /* Fetch GPIOs */ | |
c5af4074 BH |
644 | imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); |
645 | imx6_pcie->gpio_active_high = of_property_read_bool(node, | |
3ea8529a | 646 | "reset-gpio-active-high"); |
b2d7a9cd | 647 | if (gpio_is_valid(imx6_pcie->reset_gpio)) { |
13957652 | 648 | ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, |
3ea8529a PŠ |
649 | imx6_pcie->gpio_active_high ? |
650 | GPIOF_OUT_INIT_HIGH : | |
651 | GPIOF_OUT_INIT_LOW, | |
652 | "PCIe reset"); | |
b2d7a9cd | 653 | if (ret) { |
13957652 | 654 | dev_err(dev, "unable to get reset gpio\n"); |
b2d7a9cd FE |
655 | return ret; |
656 | } | |
657 | } | |
bb38919e | 658 | |
bb38919e | 659 | /* Fetch clocks */ |
13957652 | 660 | imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); |
57526136 | 661 | if (IS_ERR(imx6_pcie->pcie_phy)) { |
13957652 | 662 | dev_err(dev, "pcie_phy clock source missing or invalid\n"); |
57526136 | 663 | return PTR_ERR(imx6_pcie->pcie_phy); |
bb38919e SC |
664 | } |
665 | ||
13957652 | 666 | imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); |
57526136 | 667 | if (IS_ERR(imx6_pcie->pcie_bus)) { |
13957652 | 668 | dev_err(dev, "pcie_bus clock source missing or invalid\n"); |
57526136 | 669 | return PTR_ERR(imx6_pcie->pcie_bus); |
bb38919e SC |
670 | } |
671 | ||
13957652 | 672 | imx6_pcie->pcie = devm_clk_get(dev, "pcie"); |
57526136 | 673 | if (IS_ERR(imx6_pcie->pcie)) { |
13957652 | 674 | dev_err(dev, "pcie clock source missing or invalid\n"); |
57526136 | 675 | return PTR_ERR(imx6_pcie->pcie); |
bb38919e SC |
676 | } |
677 | ||
e6f1fef0 | 678 | if (imx6_pcie->variant == IMX6SX) { |
13957652 | 679 | imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, |
e3c06cd0 CF |
680 | "pcie_inbound_axi"); |
681 | if (IS_ERR(imx6_pcie->pcie_inbound_axi)) { | |
13957652 | 682 | dev_err(dev, |
e3c06cd0 CF |
683 | "pcie_incbound_axi clock missing or invalid\n"); |
684 | return PTR_ERR(imx6_pcie->pcie_inbound_axi); | |
685 | } | |
686 | } | |
687 | ||
bb38919e SC |
688 | /* Grab GPR config register range */ |
689 | imx6_pcie->iomuxc_gpr = | |
690 | syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | |
691 | if (IS_ERR(imx6_pcie->iomuxc_gpr)) { | |
13957652 | 692 | dev_err(dev, "unable to find iomuxc registers\n"); |
b391bf31 | 693 | return PTR_ERR(imx6_pcie->iomuxc_gpr); |
bb38919e | 694 | } |
28e3abe5 JW |
695 | |
696 | /* Grab PCIe PHY Tx Settings */ | |
697 | if (of_property_read_u32(node, "fsl,tx-deemph-gen1", | |
698 | &imx6_pcie->tx_deemph_gen1)) | |
699 | imx6_pcie->tx_deemph_gen1 = 0; | |
700 | ||
701 | if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", | |
702 | &imx6_pcie->tx_deemph_gen2_3p5db)) | |
703 | imx6_pcie->tx_deemph_gen2_3p5db = 0; | |
704 | ||
705 | if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", | |
706 | &imx6_pcie->tx_deemph_gen2_6db)) | |
707 | imx6_pcie->tx_deemph_gen2_6db = 20; | |
708 | ||
709 | if (of_property_read_u32(node, "fsl,tx-swing-full", | |
710 | &imx6_pcie->tx_swing_full)) | |
711 | imx6_pcie->tx_swing_full = 127; | |
712 | ||
713 | if (of_property_read_u32(node, "fsl,tx-swing-low", | |
714 | &imx6_pcie->tx_swing_low)) | |
715 | imx6_pcie->tx_swing_low = 127; | |
bb38919e | 716 | |
a5fcec48 | 717 | /* Limit link speed */ |
c5af4074 | 718 | ret = of_property_read_u32(node, "fsl,max-link-speed", |
a5fcec48 TH |
719 | &imx6_pcie->link_gen); |
720 | if (ret) | |
721 | imx6_pcie->link_gen = 1; | |
722 | ||
bb38919e SC |
723 | ret = imx6_add_pcie_port(pp, pdev); |
724 | if (ret < 0) | |
b391bf31 | 725 | return ret; |
bb38919e SC |
726 | |
727 | platform_set_drvdata(pdev, imx6_pcie); | |
728 | return 0; | |
bb38919e SC |
729 | } |
730 | ||
3e3e406e LS |
731 | static void imx6_pcie_shutdown(struct platform_device *pdev) |
732 | { | |
733 | struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); | |
734 | ||
735 | /* bring down link, so bootloader gets clean state in case of reboot */ | |
736 | imx6_pcie_assert_core_reset(&imx6_pcie->pp); | |
737 | } | |
738 | ||
bb38919e | 739 | static const struct of_device_id imx6_pcie_of_match[] = { |
e6f1fef0 AS |
740 | { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, }, |
741 | { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, }, | |
4d31c610 | 742 | { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, }, |
bb38919e SC |
743 | {}, |
744 | }; | |
bb38919e SC |
745 | |
746 | static struct platform_driver imx6_pcie_driver = { | |
747 | .driver = { | |
748 | .name = "imx6q-pcie", | |
8bcadbe1 | 749 | .of_match_table = imx6_pcie_of_match, |
bb38919e | 750 | }, |
3e3e406e | 751 | .shutdown = imx6_pcie_shutdown, |
bb38919e SC |
752 | }; |
753 | ||
bb38919e SC |
754 | static int __init imx6_pcie_init(void) |
755 | { | |
756 | return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); | |
757 | } | |
f90d8e84 | 758 | device_initcall(imx6_pcie_init); |