[mirror_ubuntu-artful-kernel.git] / drivers / pci / host / pci-layerscape.c

/*
 * PCIe host controller driver for Freescale Layerscape SoCs
 *
 * Copyright (C) 2014 Freescale Semiconductor.
 *
 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include "pcie-designware.h"

/* PEX1/2 Misc Ports Status Register */
#define SCFG_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)
#define LTSSM_STATE_SHIFT	20
#define LTSSM_STATE_MASK	0x3f
#define LTSSM_PCIE_L0		0x11 /* L0 state */

/* PEX Internal Configuration Registers */
#define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */

struct ls_pcie_drvdata {
	u32 lut_offset;
	u32 ltssm_shift;
	u32 lut_dbg;
	struct pcie_host_ops *ops;
};

struct ls_pcie {
	struct pcie_port pp;		/* pp.dbi_base is DT regs */
	void __iomem *lut;
	struct regmap *scfg;
	const struct ls_pcie_drvdata *drvdata;
	int index;
};

#define to_ls_pcie(x)	container_of(x, struct ls_pcie, pp)

static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
{
	u32 header_type;

	header_type = ioread8(pcie->pp.dbi_base + PCI_HEADER_TYPE);
	header_type &= 0x7f;

	return header_type == PCI_HEADER_TYPE_BRIDGE;
}

/* Clear multi-function bit */
static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
{
	iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->pp.dbi_base + PCI_HEADER_TYPE);
}

/* Fix class value */
static void ls_pcie_fix_class(struct ls_pcie *pcie)
{
	iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->pp.dbi_base + PCI_CLASS_DEVICE);
}

/* Drop MSG TLP except for Vendor MSG */
static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
{
	u32 val;

	val = ioread32(pcie->pp.dbi_base + PCIE_STRFMR1);
	val &= 0xDFFFFFFF;
	iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
}

static int ls1021_pcie_link_up(struct pcie_port *pp)
{
	u32 state;
	struct ls_pcie *pcie = to_ls_pcie(pp);

	if (!pcie->scfg)
		return 0;

	regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;

	if (state < LTSSM_PCIE_L0)
		return 0;

	return 1;
}

static void ls1021_pcie_host_init(struct pcie_port *pp)
{
	struct device *dev = pp->dev;
	struct ls_pcie *pcie = to_ls_pcie(pp);
	u32 index[2];

	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
						     "fsl,pcie-scfg");
	if (IS_ERR(pcie->scfg)) {
		dev_err(dev, "No syscfg phandle specified\n");
		pcie->scfg = NULL;
		return;
	}

	if (of_property_read_u32_array(dev->of_node,
				       "fsl,pcie-scfg", index, 2)) {
		pcie->scfg = NULL;
		return;
	}
	pcie->index = index[1];

	dw_pcie_setup_rc(pp);

	ls_pcie_drop_msg_tlp(pcie);
}

static int ls_pcie_link_up(struct pcie_port *pp)
{
	struct ls_pcie *pcie = to_ls_pcie(pp);
	u32 state;

	state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
		 pcie->drvdata->ltssm_shift) &
		 LTSSM_STATE_MASK;

	if (state < LTSSM_PCIE_L0)
		return 0;

	return 1;
}

static void ls_pcie_host_init(struct pcie_port *pp)
{
	struct ls_pcie *pcie = to_ls_pcie(pp);

	iowrite32(1, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
	ls_pcie_fix_class(pcie);
	ls_pcie_clear_multifunction(pcie);
	ls_pcie_drop_msg_tlp(pcie);
	iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
}

static int ls_pcie_msi_host_init(struct pcie_port *pp,
				 struct msi_controller *chip)
{
	struct device *dev = pp->dev;
	struct device_node *np = dev->of_node;
	struct device_node *msi_node;

	/*
	 * The MSI domain is set by the generic of_msi_configure().  This
	 * .msi_host_init() function keeps us from doing the default MSI
	 * domain setup in dw_pcie_host_init() and also enforces the
	 * requirement that "msi-parent" exists.
	 */
	msi_node = of_parse_phandle(np, "msi-parent", 0);
	if (!msi_node) {
		dev_err(dev, "failed to find msi-parent\n");
		return -EINVAL;
	}

	return 0;
}

static struct pcie_host_ops ls1021_pcie_host_ops = {
	.link_up = ls1021_pcie_link_up,
	.host_init = ls1021_pcie_host_init,
	.msi_host_init = ls_pcie_msi_host_init,
};

static struct pcie_host_ops ls_pcie_host_ops = {
	.link_up = ls_pcie_link_up,
	.host_init = ls_pcie_host_init,
	.msi_host_init = ls_pcie_msi_host_init,
};

static struct ls_pcie_drvdata ls1021_drvdata = {
	.ops = &ls1021_pcie_host_ops,
};

static struct ls_pcie_drvdata ls1043_drvdata = {
	.lut_offset = 0x10000,
	.ltssm_shift = 24,
	.lut_dbg = 0x7fc,
	.ops = &ls_pcie_host_ops,
};

static struct ls_pcie_drvdata ls1046_drvdata = {
	.lut_offset = 0x80000,
	.ltssm_shift = 24,
	.lut_dbg = 0x407fc,
	.ops = &ls_pcie_host_ops,
};

static struct ls_pcie_drvdata ls2080_drvdata = {
	.lut_offset = 0x80000,
	.ltssm_shift = 0,
	.lut_dbg = 0x7fc,
	.ops = &ls_pcie_host_ops,
};

static const struct of_device_id ls_pcie_of_match[] = {
	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
	{ },
};

static int __init ls_add_pcie_port(struct ls_pcie *pcie)
{
	struct pcie_port *pp = &pcie->pp;
	struct device *dev = pp->dev;
	int ret;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init ls_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *match;
	struct ls_pcie *pcie;
	struct pcie_port *pp;
	struct resource *dbi_base;
	int ret;

	match = of_match_device(ls_pcie_of_match, dev);
	if (!match)
		return -ENODEV;

	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
	if (!pcie)
		return -ENOMEM;

	pp = &pcie->pp;
	pp->dev = dev;
	pcie->drvdata = match->data;
	pp->ops = pcie->drvdata->ops;

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
	pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base);
	if (IS_ERR(pcie->pp.dbi_base))
		return PTR_ERR(pcie->pp.dbi_base);

	pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;

	if (!ls_pcie_is_bridge(pcie))
		return -ENODEV;

	ret = ls_add_pcie_port(pcie);
	if (ret < 0)
		return ret;

	return 0;
}

static struct platform_driver ls_pcie_driver = {
	.driver = {
		.name = "layerscape-pcie",
		.of_match_table = ls_pcie_of_match,
	},
};
builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
Commit	Line	Data
62d0ff83 ML	1	/*
	2	* PCIe host controller driver for Freescale Layerscape SoCs
	3	*
	4	* Copyright (C) 2014 Freescale Semiconductor.
	5	*
5192ec7b	6	* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
62d0ff83 ML	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
62d0ff83	14	#include <linux/interrupt.h>
154fb600	15	#include <linux/init.h>
62d0ff83 ML	16	#include <linux/of_pci.h>
	17	#include <linux/of_platform.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/of_address.h>
	20	#include <linux/pci.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/resource.h>
	23	#include <linux/mfd/syscon.h>
	24	#include <linux/regmap.h>
	25
	26	#include "pcie-designware.h"
	27
	28	/* PEX1/2 Misc Ports Status Register */
	29	#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
	30	#define LTSSM_STATE_SHIFT 20
	31	#define LTSSM_STATE_MASK 0x3f
	32	#define LTSSM_PCIE_L0 0x11 /* L0 state */
	33
5192ec7b ML	34	/* PEX Internal Configuration Registers */
	35	#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
	36	#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
	37
d6463345	38	struct ls_pcie_drvdata {
5192ec7b ML	39	u32 lut_offset;
5192ec7b ML	40	u32 ltssm_shift;
1d77040b	41	u32 lut_dbg;
d6463345 ML	42	struct pcie_host_ops *ops;
	43	};
	44
62d0ff83	45	struct ls_pcie {
6caaa28d	46	struct pcie_port pp; /* pp.dbi_base is DT regs */
5192ec7b	47	void __iomem *lut;
62d0ff83	48	struct regmap *scfg;
d6463345	49	const struct ls_pcie_drvdata *drvdata;
62d0ff83	50	int index;
62d0ff83 ML	51	};
	52
	53	#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
	54
7af4ce35 ML	55	static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
	56	{
	57	u32 header_type;
	58
d41d2959	59	header_type = ioread8(pcie->pp.dbi_base + PCI_HEADER_TYPE);
7af4ce35 ML	60	header_type &= 0x7f;
	61
	62	return header_type == PCI_HEADER_TYPE_BRIDGE;
	63	}
	64
5192ec7b ML	65	/* Clear multi-function bit */
	66	static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
	67	{
d41d2959	68	iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->pp.dbi_base + PCI_HEADER_TYPE);
5192ec7b ML	69	}
	70
	71	/* Fix class value */
	72	static void ls_pcie_fix_class(struct ls_pcie *pcie)
	73	{
d41d2959	74	iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->pp.dbi_base + PCI_CLASS_DEVICE);
5192ec7b ML	75	}
5192ec7b ML	76
1195c103 ML	77	/* Drop MSG TLP except for Vendor MSG */
	78	static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
	79	{
	80	u32 val;
	81
d41d2959	82	val = ioread32(pcie->pp.dbi_base + PCIE_STRFMR1);
1195c103	83	val &= 0xDFFFFFFF;
d41d2959	84	iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
1195c103 ML	85	}
1195c103 ML	86
d6463345	87	static int ls1021_pcie_link_up(struct pcie_port *pp)
62d0ff83 ML	88	{
	89	u32 state;
	90	struct ls_pcie *pcie = to_ls_pcie(pp);
	91
d6463345 ML	92	if (!pcie->scfg)
	93	return 0;
	94
62d0ff83 ML	95	regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
	96	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
	97
	98	if (state < LTSSM_PCIE_L0)
	99	return 0;
	100
	101	return 1;
	102	}
	103
d6463345	104	static void ls1021_pcie_host_init(struct pcie_port *pp)
1d3f9bac	105	{
c11125eb	106	struct device *dev = pp->dev;
1d3f9bac	107	struct ls_pcie *pcie = to_ls_pcie(pp);
1195c103	108	u32 index[2];
d6463345	109
c11125eb	110	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
d6463345 ML	111	"fsl,pcie-scfg");
d6463345 ML	112	if (IS_ERR(pcie->scfg)) {
c11125eb	113	dev_err(dev, "No syscfg phandle specified\n");
d6463345 ML	114	pcie->scfg = NULL;
	115	return;
	116	}
	117
c11125eb	118	if (of_property_read_u32_array(dev->of_node,
d6463345 ML	119	"fsl,pcie-scfg", index, 2)) {
	120	pcie->scfg = NULL;
	121	return;
	122	}
	123	pcie->index = index[1];
1d3f9bac BH	124
1d3f9bac BH	125	dw_pcie_setup_rc(pp);
1d3f9bac	126
1195c103	127	ls_pcie_drop_msg_tlp(pcie);
62d0ff83 ML	128	}
62d0ff83 ML	129
5192ec7b ML	130	static int ls_pcie_link_up(struct pcie_port *pp)
	131	{
	132	struct ls_pcie *pcie = to_ls_pcie(pp);
	133	u32 state;
	134
1d77040b	135	state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
5192ec7b ML	136	pcie->drvdata->ltssm_shift) &
	137	LTSSM_STATE_MASK;
	138
	139	if (state < LTSSM_PCIE_L0)
	140	return 0;
	141
	142	return 1;
	143	}
	144
	145	static void ls_pcie_host_init(struct pcie_port *pp)
	146	{
	147	struct ls_pcie *pcie = to_ls_pcie(pp);
	148
d41d2959	149	iowrite32(1, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
5192ec7b ML	150	ls_pcie_fix_class(pcie);
5192ec7b ML	151	ls_pcie_clear_multifunction(pcie);
1195c103	152	ls_pcie_drop_msg_tlp(pcie);
d41d2959	153	iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
5192ec7b ML	154	}
5192ec7b ML	155
bd33b87a ML	156	static int ls_pcie_msi_host_init(struct pcie_port *pp,
	157	struct msi_controller *chip)
	158	{
c11125eb BH	159	struct device *dev = pp->dev;
c11125eb BH	160	struct device_node *np = dev->of_node;
bd33b87a	161	struct device_node *msi_node;
bd33b87a ML	162
	163	/*
	164	* The MSI domain is set by the generic of_msi_configure(). This
	165	* .msi_host_init() function keeps us from doing the default MSI
	166	* domain setup in dw_pcie_host_init() and also enforces the
	167	* requirement that "msi-parent" exists.
	168	*/
	169	msi_node = of_parse_phandle(np, "msi-parent", 0);
	170	if (!msi_node) {
c11125eb	171	dev_err(dev, "failed to find msi-parent\n");
bd33b87a ML	172	return -EINVAL;
	173	}
	174
	175	return 0;
	176	}
	177
d6463345 ML	178	static struct pcie_host_ops ls1021_pcie_host_ops = {
	179	.link_up = ls1021_pcie_link_up,
	180	.host_init = ls1021_pcie_host_init,
bd33b87a	181	.msi_host_init = ls_pcie_msi_host_init,
d6463345 ML	182	};
d6463345 ML	183
5192ec7b ML	184	static struct pcie_host_ops ls_pcie_host_ops = {
	185	.link_up = ls_pcie_link_up,
	186	.host_init = ls_pcie_host_init,
bd33b87a	187	.msi_host_init = ls_pcie_msi_host_init,
5192ec7b ML	188	};
5192ec7b ML	189
d6463345 ML	190	static struct ls_pcie_drvdata ls1021_drvdata = {
d6463345 ML	191	.ops = &ls1021_pcie_host_ops,
62d0ff83 ML	192	};
62d0ff83 ML	193
5192ec7b ML	194	static struct ls_pcie_drvdata ls1043_drvdata = {
	195	.lut_offset = 0x10000,
	196	.ltssm_shift = 24,
1d77040b MH	197	.lut_dbg = 0x7fc,
	198	.ops = &ls_pcie_host_ops,
	199	};
	200
	201	static struct ls_pcie_drvdata ls1046_drvdata = {
	202	.lut_offset = 0x80000,
	203	.ltssm_shift = 24,
	204	.lut_dbg = 0x407fc,
5192ec7b ML	205	.ops = &ls_pcie_host_ops,
	206	};
	207
	208	static struct ls_pcie_drvdata ls2080_drvdata = {
	209	.lut_offset = 0x80000,
	210	.ltssm_shift = 0,
1d77040b	211	.lut_dbg = 0x7fc,
5192ec7b ML	212	.ops = &ls_pcie_host_ops,
	213	};
	214
d6463345 ML	215	static const struct of_device_id ls_pcie_of_match[] = {
d6463345 ML	216	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
5192ec7b	217	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1d77040b	218	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
5192ec7b	219	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
dbae40b7	220	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
d6463345 ML	221	{ },
d6463345 ML	222	};
d6463345	223
4726a823	224	static int __init ls_add_pcie_port(struct ls_pcie *pcie)
62d0ff83	225	{
7b0b1113	226	struct pcie_port *pp = &pcie->pp;
fefe6733	227	struct device *dev = pp->dev;
62d0ff83 ML	228	int ret;
62d0ff83 ML	229
62d0ff83 ML	230	ret = dw_pcie_host_init(pp);
62d0ff83 ML	231	if (ret) {
c11125eb	232	dev_err(dev, "failed to initialize host\n");
62d0ff83 ML	233	return ret;
	234	}
	235
	236	return 0;
	237	}
	238
	239	static int __init ls_pcie_probe(struct platform_device *pdev)
	240	{
c11125eb	241	struct device *dev = &pdev->dev;
d6463345	242	const struct of_device_id *match;
62d0ff83	243	struct ls_pcie *pcie;
fefe6733	244	struct pcie_port *pp;
62d0ff83	245	struct resource *dbi_base;
62d0ff83 ML	246	int ret;
62d0ff83 ML	247
c11125eb	248	match = of_match_device(ls_pcie_of_match, dev);
d6463345 ML	249	if (!match)
	250	return -ENODEV;
	251
c11125eb	252	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
62d0ff83 ML	253	if (!pcie)
	254	return -ENOMEM;
	255
fefe6733 BH	256	pp = &pcie->pp;
fefe6733 BH	257	pp->dev = dev;
15480f3a	258	pcie->drvdata = match->data;
fefe6733 BH	259	pp->ops = pcie->drvdata->ops;
fefe6733 BH	260
62d0ff83	261	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
d41d2959	262	pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base);
e5942338	263	if (IS_ERR(pcie->pp.dbi_base))
d41d2959	264	return PTR_ERR(pcie->pp.dbi_base);
62d0ff83	265
d41d2959	266	pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;
62d0ff83	267
7af4ce35 ML	268	if (!ls_pcie_is_bridge(pcie))
	269	return -ENODEV;
	270
4726a823	271	ret = ls_add_pcie_port(pcie);
62d0ff83 ML	272	if (ret < 0)
	273	return ret;
	274
62d0ff83 ML	275	return 0;
	276	}
	277
62d0ff83 ML	278	static struct platform_driver ls_pcie_driver = {
	279	.driver = {
	280	.name = "layerscape-pcie",
62d0ff83 ML	281	.of_match_table = ls_pcie_of_match,
	282	},
	283	};
154fb600	284	builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);