[mirror_ubuntu-bionic-kernel.git] / drivers / pci / host / pci-rcar-gen2.c

/*
 *  pci-rcar-gen2: internal PCI bus support
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Cogent Embedded, Inc.
 *
 * Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>
#include <linux/slab.h>

/* AHB-PCI Bridge PCI communication registers */
#define RCAR_AHBPCI_PCICOM_OFFSET	0x800

#define RCAR_PCIAHB_WIN1_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
#define RCAR_PCIAHB_WIN2_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
#define RCAR_PCIAHB_PREFETCH0		0x0
#define RCAR_PCIAHB_PREFETCH4		0x1
#define RCAR_PCIAHB_PREFETCH8		0x2
#define RCAR_PCIAHB_PREFETCH16		0x3

#define RCAR_AHBPCI_WIN1_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
#define RCAR_AHBPCI_WIN2_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
#define RCAR_AHBPCI_WIN_CTR_MEM		(3 << 1)
#define RCAR_AHBPCI_WIN_CTR_CFG		(5 << 1)
#define RCAR_AHBPCI_WIN1_HOST		(1 << 30)
#define RCAR_AHBPCI_WIN1_DEVICE		(1 << 31)

#define RCAR_PCI_INT_ENABLE_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
#define RCAR_PCI_INT_STATUS_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
#define RCAR_PCI_INT_SIGTABORT		(1 << 0)
#define RCAR_PCI_INT_SIGRETABORT	(1 << 1)
#define RCAR_PCI_INT_REMABORT		(1 << 2)
#define RCAR_PCI_INT_PERR		(1 << 3)
#define RCAR_PCI_INT_SIGSERR		(1 << 4)
#define RCAR_PCI_INT_RESERR		(1 << 5)
#define RCAR_PCI_INT_WIN1ERR		(1 << 12)
#define RCAR_PCI_INT_WIN2ERR		(1 << 13)
#define RCAR_PCI_INT_A			(1 << 16)
#define RCAR_PCI_INT_B			(1 << 17)
#define RCAR_PCI_INT_PME		(1 << 19)
#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT		| \
				RCAR_PCI_INT_SIGRETABORT	| \
				RCAR_PCI_INT_SIGRETABORT	| \
				RCAR_PCI_INT_REMABORT		| \
				RCAR_PCI_INT_PERR		| \
				RCAR_PCI_INT_SIGSERR		| \
				RCAR_PCI_INT_RESERR		| \
				RCAR_PCI_INT_WIN1ERR		| \
				RCAR_PCI_INT_WIN2ERR)

#define RCAR_AHB_BUS_CTR_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
#define RCAR_AHB_BUS_MMODE_HTRANS	(1 << 0)
#define RCAR_AHB_BUS_MMODE_BYTE_BURST	(1 << 1)
#define RCAR_AHB_BUS_MMODE_WR_INCR	(1 << 2)
#define RCAR_AHB_BUS_MMODE_HBUS_REQ	(1 << 7)
#define RCAR_AHB_BUS_SMODE_READYCTR	(1 << 17)
#define RCAR_AHB_BUS_MODE		(RCAR_AHB_BUS_MMODE_HTRANS |	\
					RCAR_AHB_BUS_MMODE_BYTE_BURST |	\
					RCAR_AHB_BUS_MMODE_WR_INCR |	\
					RCAR_AHB_BUS_MMODE_HBUS_REQ |	\
					RCAR_AHB_BUS_SMODE_READYCTR)

#define RCAR_USBCTR_REG			(RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
#define RCAR_USBCTR_USBH_RST		(1 << 0)
#define RCAR_USBCTR_PCICLK_MASK		(1 << 1)
#define RCAR_USBCTR_PLL_RST		(1 << 2)
#define RCAR_USBCTR_DIRPD		(1 << 8)
#define RCAR_USBCTR_PCIAHB_WIN2_EN	(1 << 9)
#define RCAR_USBCTR_PCIAHB_WIN1_256M	(0 << 10)
#define RCAR_USBCTR_PCIAHB_WIN1_512M	(1 << 10)
#define RCAR_USBCTR_PCIAHB_WIN1_1G	(2 << 10)
#define RCAR_USBCTR_PCIAHB_WIN1_2G	(3 << 10)
#define RCAR_USBCTR_PCIAHB_WIN1_MASK	(3 << 10)

#define RCAR_PCI_ARBITER_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
#define RCAR_PCI_ARBITER_PCIREQ0	(1 << 0)
#define RCAR_PCI_ARBITER_PCIREQ1	(1 << 1)
#define RCAR_PCI_ARBITER_PCIBP_MODE	(1 << 12)

#define RCAR_PCI_UNIT_REV_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x48)

struct rcar_pci_priv {
	struct device *dev;
	void __iomem *reg;
	struct resource mem_res;
	struct resource *cfg_res;
	unsigned busnr;
	int irq;
	unsigned long window_size;
	unsigned long window_addr;
	unsigned long window_pci;
};

/* PCI configuration space operations */
static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
				       int where)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct rcar_pci_priv *priv = sys->private_data;
	int slot, val;

	if (sys->busnr != bus->number || PCI_FUNC(devfn))
		return NULL;

	/* Only one EHCI/OHCI device built-in */
	slot = PCI_SLOT(devfn);
	if (slot > 2)
		return NULL;

	/* bridge logic only has registers to 0x40 */
	if (slot == 0x0 && where >= 0x40)
		return NULL;

	val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
		     RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;

	iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
	return priv->reg + (slot >> 1) * 0x100 + where;
}

/* PCI interrupt mapping */
static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_sys_data *sys = dev->bus->sysdata;
	struct rcar_pci_priv *priv = sys->private_data;
	int irq;

	irq = of_irq_parse_and_map_pci(dev, slot, pin);
	if (!irq)
		irq = priv->irq;

	return irq;
}

#ifdef CONFIG_PCI_DEBUG
/* if debug enabled, then attach an error handler irq to the bridge */

static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
{
	struct rcar_pci_priv *priv = pw;
	struct device *dev = priv->dev;
	u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);

	if (status & RCAR_PCI_INT_ALLERRORS) {
		dev_err(dev, "error irq: status %08x\n", status);

		/* clear the error(s) */
		iowrite32(status & RCAR_PCI_INT_ALLERRORS,
			  priv->reg + RCAR_PCI_INT_STATUS_REG);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
{
	struct device *dev = priv->dev;
	int ret;
	u32 val;

	ret = devm_request_irq(dev, priv->irq, rcar_pci_err_irq,
			       IRQF_SHARED, "error irq", priv);
	if (ret) {
		dev_err(dev, "cannot claim IRQ for error handling\n");
		return;
	}

	val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
	val |= RCAR_PCI_INT_ALLERRORS;
	iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
}
#else
static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
#endif

/* PCI host controller setup */
static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
{
	struct rcar_pci_priv *priv = sys->private_data;
	struct device *dev = priv->dev;
	void __iomem *reg = priv->reg;
	u32 val;
	int ret;

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
	dev_info(dev, "PCI: bus%u revision %x\n", sys->busnr, val);

	/* Disable Direct Power Down State and assert reset */
	val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
	val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
	iowrite32(val, reg + RCAR_USBCTR_REG);
	udelay(4);

	/* De-assert reset and reset PCIAHB window1 size */
	val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
		 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);

	/* Setup PCIAHB window1 size */
	switch (priv->window_size) {
	case SZ_2G:
		val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
		break;
	case SZ_1G:
		val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
		break;
	case SZ_512M:
		val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
		break;
	default:
		pr_warn("unknown window size %ld - defaulting to 256M\n",
			priv->window_size);
		priv->window_size = SZ_256M;
		/* fall-through */
	case SZ_256M:
		val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
		break;
	}
	iowrite32(val, reg + RCAR_USBCTR_REG);

	/* Configure AHB master and slave modes */
	iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);

	/* Configure PCI arbiter */
	val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
	val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
	       RCAR_PCI_ARBITER_PCIBP_MODE;
	iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);

	/* PCI-AHB mapping */
	iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16,
		  reg + RCAR_PCIAHB_WIN1_CTR_REG);

	/* AHB-PCI mapping: OHCI/EHCI registers */
	val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
	iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);

	/* Enable AHB-PCI bridge PCI configuration access */
	iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
		  reg + RCAR_AHBPCI_WIN1_CTR_REG);
	/* Set PCI-AHB Window1 address */
	iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
		  reg + PCI_BASE_ADDRESS_1);
	/* Set AHB-PCI bridge PCI communication area address */
	val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
	iowrite32(val, reg + PCI_BASE_ADDRESS_0);

	val = ioread32(reg + PCI_COMMAND);
	val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
	       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
	iowrite32(val, reg + PCI_COMMAND);

	/* Enable PCI interrupts */
	iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
		  reg + RCAR_PCI_INT_ENABLE_REG);

	if (priv->irq > 0)
		rcar_pci_setup_errirq(priv);

	/* Add PCI resources */
	pci_add_resource(&sys->resources, &priv->mem_res);
	ret = devm_request_pci_bus_resources(dev, &sys->resources);
	if (ret < 0)
		return ret;

	/* Setup bus number based on platform device id / of bus-range */
	sys->busnr = priv->busnr;
	return 1;
}

static struct pci_ops rcar_pci_ops = {
	.map_bus = rcar_pci_cfg_base,
	.read	= pci_generic_config_read,
	.write	= pci_generic_config_write,
};

static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
				     struct device_node *node)
{
	const int na = 3, ns = 2;
	int rlen;

	parser->node = node;
	parser->pna = of_n_addr_cells(node);
	parser->np = parser->pna + na + ns;

	parser->range = of_get_property(node, "dma-ranges", &rlen);
	if (!parser->range)
		return -ENOENT;

	parser->end = parser->range + rlen / sizeof(__be32);
	return 0;
}

static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
					 struct device_node *np)
{
	struct device *dev = pci->dev;
	struct of_pci_range range;
	struct of_pci_range_parser parser;
	int index = 0;

	/* Failure to parse is ok as we fall back to defaults */
	if (pci_dma_range_parser_init(&parser, np))
		return 0;

	/* Get the dma-ranges from DT */
	for_each_of_pci_range(&parser, &range) {
		/* Hardware only allows one inbound 32-bit range */
		if (index)
			return -EINVAL;

		pci->window_addr = (unsigned long)range.cpu_addr;
		pci->window_pci = (unsigned long)range.pci_addr;
		pci->window_size = (unsigned long)range.size;

		/* Catch HW limitations */
		if (!(range.flags & IORESOURCE_PREFETCH)) {
			dev_err(dev, "window must be prefetchable\n");
			return -EINVAL;
		}
		if (pci->window_addr) {
			u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);

			if (lowaddr < pci->window_size) {
				dev_err(dev, "invalid window size/addr\n");
				return -EINVAL;
			}
		}
		index++;
	}

	return 0;
}

static int rcar_pci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *cfg_res, *mem_res;
	struct rcar_pci_priv *priv;
	void __iomem *reg;
	struct hw_pci hw;
	void *hw_private[1];

	cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg = devm_ioremap_resource(dev, cfg_res);
	if (IS_ERR(reg))
		return PTR_ERR(reg);

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!mem_res || !mem_res->start)
		return -ENODEV;

	if (mem_res->start & 0xFFFF)
		return -EINVAL;

	priv = devm_kzalloc(dev, sizeof(struct rcar_pci_priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->mem_res = *mem_res;
	priv->cfg_res = cfg_res;

	priv->irq = platform_get_irq(pdev, 0);
	priv->reg = reg;
	priv->dev = dev;

	if (priv->irq < 0) {
		dev_err(dev, "no valid irq found\n");
		return priv->irq;
	}

	/* default window addr and size if not specified in DT */
	priv->window_addr = 0x40000000;
	priv->window_pci = 0x40000000;
	priv->window_size = SZ_1G;

	if (dev->of_node) {
		struct resource busnr;
		int ret;

		ret = of_pci_parse_bus_range(dev->of_node, &busnr);
		if (ret < 0) {
			dev_err(dev, "failed to parse bus-range\n");
			return ret;
		}

		priv->busnr = busnr.start;
		if (busnr.end != busnr.start)
			dev_warn(dev, "only one bus number supported\n");

		ret = rcar_pci_parse_map_dma_ranges(priv, dev->of_node);
		if (ret < 0) {
			dev_err(dev, "failed to parse dma-range\n");
			return ret;
		}
	} else {
		priv->busnr = pdev->id;
	}

	hw_private[0] = priv;
	memset(&hw, 0, sizeof(hw));
	hw.nr_controllers = ARRAY_SIZE(hw_private);
	hw.io_optional = 1;
	hw.private_data = hw_private;
	hw.map_irq = rcar_pci_map_irq;
	hw.ops = &rcar_pci_ops;
	hw.setup = rcar_pci_setup;
	pci_common_init_dev(dev, &hw);
	return 0;
}

static struct of_device_id rcar_pci_of_match[] = {
	{ .compatible = "renesas,pci-rcar-gen2", },
	{ .compatible = "renesas,pci-r8a7790", },
	{ .compatible = "renesas,pci-r8a7791", },
	{ .compatible = "renesas,pci-r8a7794", },
	{ },
};

static struct platform_driver rcar_pci_driver = {
	.driver = {
		.name = "pci-rcar-gen2",
		.suppress_bind_attrs = true,
		.of_match_table = rcar_pci_of_match,
	},
	.probe = rcar_pci_probe,
};
builtin_platform_driver(rcar_pci_driver);
Commit	Line	Data
ba3eb9fc VB	1	/*
	2	* pci-rcar-gen2: internal PCI bus support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Cogent Embedded, Inc.
	6	*
0b9c1589 PG	7	* Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
0b9c1589 PG	8	*
ba3eb9fc VB	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/delay.h>
	15	#include <linux/init.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/io.h>
	18	#include <linux/kernel.h>
8d598cab	19	#include <linux/of_address.h>
b9bfe1bc	20	#include <linux/of_pci.h>
ba3eb9fc VB	21	#include <linux/pci.h>
ba3eb9fc VB	22	#include <linux/platform_device.h>
fb178d8b	23	#include <linux/pm_runtime.h>
33966fd9	24	#include <linux/sizes.h>
ba3eb9fc VB	25	#include <linux/slab.h>
	26
	27	/* AHB-PCI Bridge PCI communication registers */
	28	#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
	29
	30	#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
	31	#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
	32	#define RCAR_PCIAHB_PREFETCH0 0x0
	33	#define RCAR_PCIAHB_PREFETCH4 0x1
	34	#define RCAR_PCIAHB_PREFETCH8 0x2
	35	#define RCAR_PCIAHB_PREFETCH16 0x3
	36
	37	#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
	38	#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
	39	#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
	40	#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
	41	#define RCAR_AHBPCI_WIN1_HOST (1 << 30)
	42	#define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
	43
	44	#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
	45	#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
80a595d9 BD	46	#define RCAR_PCI_INT_SIGTABORT (1 << 0)
	47	#define RCAR_PCI_INT_SIGRETABORT (1 << 1)
	48	#define RCAR_PCI_INT_REMABORT (1 << 2)
	49	#define RCAR_PCI_INT_PERR (1 << 3)
	50	#define RCAR_PCI_INT_SIGSERR (1 << 4)
	51	#define RCAR_PCI_INT_RESERR (1 << 5)
	52	#define RCAR_PCI_INT_WIN1ERR (1 << 12)
	53	#define RCAR_PCI_INT_WIN2ERR (1 << 13)
ba3eb9fc VB	54	#define RCAR_PCI_INT_A (1 << 16)
	55	#define RCAR_PCI_INT_B (1 << 17)
	56	#define RCAR_PCI_INT_PME (1 << 19)
80a595d9 BD	57	#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT \| \
	58	RCAR_PCI_INT_SIGRETABORT \| \
	59	RCAR_PCI_INT_SIGRETABORT \| \
	60	RCAR_PCI_INT_REMABORT \| \
	61	RCAR_PCI_INT_PERR \| \
	62	RCAR_PCI_INT_SIGSERR \| \
	63	RCAR_PCI_INT_RESERR \| \
	64	RCAR_PCI_INT_WIN1ERR \| \
	65	RCAR_PCI_INT_WIN2ERR)
ba3eb9fc VB	66
	67	#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
	68	#define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
	69	#define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
	70	#define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
	71	#define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
	72	#define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
	73	#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS \| \
	74	RCAR_AHB_BUS_MMODE_BYTE_BURST \| \
	75	RCAR_AHB_BUS_MMODE_WR_INCR \| \
	76	RCAR_AHB_BUS_MMODE_HBUS_REQ \| \
	77	RCAR_AHB_BUS_SMODE_READYCTR)
	78
	79	#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
	80	#define RCAR_USBCTR_USBH_RST (1 << 0)
	81	#define RCAR_USBCTR_PCICLK_MASK (1 << 1)
	82	#define RCAR_USBCTR_PLL_RST (1 << 2)
	83	#define RCAR_USBCTR_DIRPD (1 << 8)
	84	#define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
	85	#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
	86	#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
	87	#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
	88	#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
	89	#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
	90
	91	#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
	92	#define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
	93	#define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
	94	#define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
	95
	96	#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
	97
ba3eb9fc	98	struct rcar_pci_priv {
fb178d8b	99	struct device *dev;
ba3eb9fc	100	void __iomem *reg;
ba3eb9fc VB	101	struct resource mem_res;
ba3eb9fc VB	102	struct resource *cfg_res;
d47b62f4	103	unsigned busnr;
ba3eb9fc	104	int irq;
33966fd9	105	unsigned long window_size;
8d598cab PE	106	unsigned long window_addr;
8d598cab PE	107	unsigned long window_pci;
ba3eb9fc VB	108	};
	109
	110	/* PCI configuration space operations */
	111	static void __iomem rcar_pci_cfg_base(struct pci_bus bus, unsigned int devfn,
	112	int where)
	113	{
	114	struct pci_sys_data *sys = bus->sysdata;
	115	struct rcar_pci_priv *priv = sys->private_data;
	116	int slot, val;
	117
	118	if (sys->busnr != bus->number \|\| PCI_FUNC(devfn))
	119	return NULL;
	120
	121	/* Only one EHCI/OHCI device built-in */
	122	slot = PCI_SLOT(devfn);
	123	if (slot > 2)
	124	return NULL;
	125
e64a2a97 BD	126	/* bridge logic only has registers to 0x40 */
	127	if (slot == 0x0 && where >= 0x40)
	128	return NULL;
	129
ba3eb9fc VB	130	val = slot ? RCAR_AHBPCI_WIN1_DEVICE \| RCAR_AHBPCI_WIN_CTR_CFG :
	131	RCAR_AHBPCI_WIN1_HOST \| RCAR_AHBPCI_WIN_CTR_CFG;
	132
	133	iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
	134	return priv->reg + (slot >> 1) * 0x100 + where;
	135	}
	136
ba3eb9fc	137	/* PCI interrupt mapping */
546cadda	138	static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
ba3eb9fc VB	139	{
	140	struct pci_sys_data *sys = dev->bus->sysdata;
	141	struct rcar_pci_priv *priv = sys->private_data;
b9bfe1bc LS	142	int irq;
	143
	144	irq = of_irq_parse_and_map_pci(dev, slot, pin);
	145	if (!irq)
	146	irq = priv->irq;
ba3eb9fc	147
b9bfe1bc	148	return irq;
ba3eb9fc VB	149	}
ba3eb9fc VB	150
80a595d9 BD	151	#ifdef CONFIG_PCI_DEBUG
	152	/* if debug enabled, then attach an error handler irq to the bridge */
	153
	154	static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
	155	{
	156	struct rcar_pci_priv *priv = pw;
de9e6bc8	157	struct device *dev = priv->dev;
80a595d9 BD	158	u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
	159
	160	if (status & RCAR_PCI_INT_ALLERRORS) {
de9e6bc8	161	dev_err(dev, "error irq: status %08x\n", status);
80a595d9 BD	162
	163	/* clear the error(s) */
	164	iowrite32(status & RCAR_PCI_INT_ALLERRORS,
	165	priv->reg + RCAR_PCI_INT_STATUS_REG);
	166	return IRQ_HANDLED;
	167	}
	168
	169	return IRQ_NONE;
	170	}
	171
	172	static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
	173	{
de9e6bc8	174	struct device *dev = priv->dev;
80a595d9 BD	175	int ret;
	176	u32 val;
	177
de9e6bc8	178	ret = devm_request_irq(dev, priv->irq, rcar_pci_err_irq,
80a595d9 BD	179	IRQF_SHARED, "error irq", priv);
80a595d9 BD	180	if (ret) {
de9e6bc8	181	dev_err(dev, "cannot claim IRQ for error handling\n");
80a595d9 BD	182	return;
	183	}
	184
	185	val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
	186	val \|= RCAR_PCI_INT_ALLERRORS;
	187	iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
	188	}
	189	#else
	190	static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
	191	#endif
	192
ba3eb9fc	193	/* PCI host controller setup */
546cadda	194	static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
ba3eb9fc VB	195	{
ba3eb9fc VB	196	struct rcar_pci_priv *priv = sys->private_data;
de9e6bc8	197	struct device *dev = priv->dev;
ba3eb9fc VB	198	void __iomem *reg = priv->reg;
ba3eb9fc VB	199	u32 val;
ac575ead	200	int ret;
ba3eb9fc	201
de9e6bc8 BH	202	pm_runtime_enable(dev);
de9e6bc8 BH	203	pm_runtime_get_sync(dev);
fb178d8b	204
ba3eb9fc	205	val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
de9e6bc8	206	dev_info(dev, "PCI: bus%u revision %x\n", sys->busnr, val);
ba3eb9fc VB	207
	208	/* Disable Direct Power Down State and assert reset */
	209	val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
	210	val \|= RCAR_USBCTR_USBH_RST \| RCAR_USBCTR_PLL_RST;
	211	iowrite32(val, reg + RCAR_USBCTR_REG);
	212	udelay(4);
	213
33966fd9	214	/* De-assert reset and reset PCIAHB window1 size */
ba3eb9fc VB	215	val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK \| RCAR_USBCTR_PCICLK_MASK \|
ba3eb9fc VB	216	RCAR_USBCTR_USBH_RST \| RCAR_USBCTR_PLL_RST);
33966fd9 MD	217
	218	/* Setup PCIAHB window1 size */
	219	switch (priv->window_size) {
	220	case SZ_2G:
	221	val \|= RCAR_USBCTR_PCIAHB_WIN1_2G;
	222	break;
	223	case SZ_1G:
	224	val \|= RCAR_USBCTR_PCIAHB_WIN1_1G;
	225	break;
	226	case SZ_512M:
	227	val \|= RCAR_USBCTR_PCIAHB_WIN1_512M;
	228	break;
	229	default:
	230	pr_warn("unknown window size %ld - defaulting to 256M\n",
	231	priv->window_size);
	232	priv->window_size = SZ_256M;
	233	/* fall-through */
	234	case SZ_256M:
	235	val \|= RCAR_USBCTR_PCIAHB_WIN1_256M;
	236	break;
	237	}
	238	iowrite32(val, reg + RCAR_USBCTR_REG);
ba3eb9fc VB	239
	240	/* Configure AHB master and slave modes */
	241	iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
	242
	243	/* Configure PCI arbiter */
	244	val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
	245	val \|= RCAR_PCI_ARBITER_PCIREQ0 \| RCAR_PCI_ARBITER_PCIREQ1 \|
	246	RCAR_PCI_ARBITER_PCIBP_MODE;
	247	iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
	248
8d598cab PE	249	/* PCI-AHB mapping */
8d598cab PE	250	iowrite32(priv->window_addr \| RCAR_PCIAHB_PREFETCH16,
ba3eb9fc VB	251	reg + RCAR_PCIAHB_WIN1_CTR_REG);
	252
	253	/* AHB-PCI mapping: OHCI/EHCI registers */
	254	val = priv->mem_res.start \| RCAR_AHBPCI_WIN_CTR_MEM;
	255	iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
	256
	257	/* Enable AHB-PCI bridge PCI configuration access */
	258	iowrite32(RCAR_AHBPCI_WIN1_HOST \| RCAR_AHBPCI_WIN_CTR_CFG,
	259	reg + RCAR_AHBPCI_WIN1_CTR_REG);
	260	/* Set PCI-AHB Window1 address */
8d598cab	261	iowrite32(priv->window_pci \| PCI_BASE_ADDRESS_MEM_PREFETCH,
ba3eb9fc VB	262	reg + PCI_BASE_ADDRESS_1);
	263	/* Set AHB-PCI bridge PCI communication area address */
	264	val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
	265	iowrite32(val, reg + PCI_BASE_ADDRESS_0);
	266
	267	val = ioread32(reg + PCI_COMMAND);
	268	val \|= PCI_COMMAND_SERR \| PCI_COMMAND_PARITY \|
	269	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
	270	iowrite32(val, reg + PCI_COMMAND);
	271
	272	/* Enable PCI interrupts */
	273	iowrite32(RCAR_PCI_INT_A \| RCAR_PCI_INT_B \| RCAR_PCI_INT_PME,
	274	reg + RCAR_PCI_INT_ENABLE_REG);
	275
80a595d9 BD	276	if (priv->irq > 0)
	277	rcar_pci_setup_errirq(priv);
	278
ba3eb9fc	279	/* Add PCI resources */
ba3eb9fc	280	pci_add_resource(&sys->resources, &priv->mem_res);
de9e6bc8	281	ret = devm_request_pci_bus_resources(dev, &sys->resources);
ac575ead BH	282	if (ret < 0)
ac575ead BH	283	return ret;
ba3eb9fc	284
d47b62f4 BD	285	/* Setup bus number based on platform device id / of bus-range */
d47b62f4 BD	286	sys->busnr = priv->busnr;
ba3eb9fc VB	287	return 1;
	288	}
	289
	290	static struct pci_ops rcar_pci_ops = {
b44923b7 RH	291	.map_bus = rcar_pci_cfg_base,
	292	.read = pci_generic_config_read,
	293	.write = pci_generic_config_write,
ba3eb9fc VB	294	};
ba3eb9fc VB	295
8d598cab PE	296	static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
	297	struct device_node *node)
	298	{
	299	const int na = 3, ns = 2;
	300	int rlen;
	301
	302	parser->node = node;
	303	parser->pna = of_n_addr_cells(node);
	304	parser->np = parser->pna + na + ns;
	305
	306	parser->range = of_get_property(node, "dma-ranges", &rlen);
	307	if (!parser->range)
	308	return -ENOENT;
	309
	310	parser->end = parser->range + rlen / sizeof(__be32);
	311	return 0;
	312	}
	313
	314	static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
	315	struct device_node *np)
	316	{
de9e6bc8	317	struct device *dev = pci->dev;
8d598cab PE	318	struct of_pci_range range;
	319	struct of_pci_range_parser parser;
	320	int index = 0;
	321
	322	/* Failure to parse is ok as we fall back to defaults */
	323	if (pci_dma_range_parser_init(&parser, np))
	324	return 0;
	325
	326	/* Get the dma-ranges from DT */
	327	for_each_of_pci_range(&parser, &range) {
	328	/* Hardware only allows one inbound 32-bit range */
	329	if (index)
	330	return -EINVAL;
	331
	332	pci->window_addr = (unsigned long)range.cpu_addr;
	333	pci->window_pci = (unsigned long)range.pci_addr;
	334	pci->window_size = (unsigned long)range.size;
	335
	336	/* Catch HW limitations */
	337	if (!(range.flags & IORESOURCE_PREFETCH)) {
de9e6bc8	338	dev_err(dev, "window must be prefetchable\n");
8d598cab PE	339	return -EINVAL;
	340	}
	341	if (pci->window_addr) {
	342	u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);
	343
	344	if (lowaddr < pci->window_size) {
de9e6bc8	345	dev_err(dev, "invalid window size/addr\n");
8d598cab PE	346	return -EINVAL;
	347	}
	348	}
	349	index++;
	350	}
	351
	352	return 0;
	353	}
	354
546cadda	355	static int rcar_pci_probe(struct platform_device *pdev)
ba3eb9fc	356	{
de9e6bc8	357	struct device *dev = &pdev->dev;
ba3eb9fc VB	358	struct resource cfg_res, mem_res;
	359	struct rcar_pci_priv *priv;
	360	void __iomem *reg;
546cadda MD	361	struct hw_pci hw;
546cadda MD	362	void *hw_private[1];
ba3eb9fc VB	363
ba3eb9fc VB	364	cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
de9e6bc8	365	reg = devm_ioremap_resource(dev, cfg_res);
c176d1c7 WY	366	if (IS_ERR(reg))
c176d1c7 WY	367	return PTR_ERR(reg);
ba3eb9fc VB	368
	369	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	370	if (!mem_res \|\| !mem_res->start)
	371	return -ENODEV;
	372
7a27db23 NI	373	if (mem_res->start & 0xFFFF)
	374	return -EINVAL;
	375
de9e6bc8	376	priv = devm_kzalloc(dev, sizeof(struct rcar_pci_priv), GFP_KERNEL);
ba3eb9fc VB	377	if (!priv)
	378	return -ENOMEM;
	379
	380	priv->mem_res = *mem_res;
ba3eb9fc VB	381	priv->cfg_res = cfg_res;
	382
	383	priv->irq = platform_get_irq(pdev, 0);
	384	priv->reg = reg;
de9e6bc8	385	priv->dev = dev;
ba3eb9fc	386
ed65b788	387	if (priv->irq < 0) {
de9e6bc8	388	dev_err(dev, "no valid irq found\n");
ed65b788 BD	389	return priv->irq;
	390	}
	391
8d598cab PE	392	/* default window addr and size if not specified in DT */
	393	priv->window_addr = 0x40000000;
	394	priv->window_pci = 0x40000000;
33966fd9 MD	395	priv->window_size = SZ_1G;
33966fd9 MD	396
de9e6bc8	397	if (dev->of_node) {
d47b62f4 BD	398	struct resource busnr;
	399	int ret;
	400
de9e6bc8	401	ret = of_pci_parse_bus_range(dev->of_node, &busnr);
d47b62f4	402	if (ret < 0) {
de9e6bc8	403	dev_err(dev, "failed to parse bus-range\n");
d47b62f4 BD	404	return ret;
	405	}
	406
	407	priv->busnr = busnr.start;
	408	if (busnr.end != busnr.start)
de9e6bc8	409	dev_warn(dev, "only one bus number supported\n");
8d598cab	410
de9e6bc8	411	ret = rcar_pci_parse_map_dma_ranges(priv, dev->of_node);
8d598cab	412	if (ret < 0) {
de9e6bc8	413	dev_err(dev, "failed to parse dma-range\n");
8d598cab PE	414	return ret;
8d598cab PE	415	}
d47b62f4 BD	416	} else {
	417	priv->busnr = pdev->id;
	418	}
	419
546cadda MD	420	hw_private[0] = priv;
	421	memset(&hw, 0, sizeof(hw));
	422	hw.nr_controllers = ARRAY_SIZE(hw_private);
b2a5d3e2	423	hw.io_optional = 1;
546cadda MD	424	hw.private_data = hw_private;
	425	hw.map_irq = rcar_pci_map_irq;
	426	hw.ops = &rcar_pci_ops;
	427	hw.setup = rcar_pci_setup;
de9e6bc8	428	pci_common_init_dev(dev, &hw);
546cadda	429	return 0;
ba3eb9fc VB	430	}
ba3eb9fc VB	431
d47b62f4	432	static struct of_device_id rcar_pci_of_match[] = {
3517652f	433	{ .compatible = "renesas,pci-rcar-gen2", },
d47b62f4 BD	434	{ .compatible = "renesas,pci-r8a7790", },
d47b62f4 BD	435	{ .compatible = "renesas,pci-r8a7791", },
de24c18c	436	{ .compatible = "renesas,pci-r8a7794", },
d47b62f4 BD	437	{ },
	438	};
	439
ba3eb9fc VB	440	static struct platform_driver rcar_pci_driver = {
	441	.driver = {
	442	.name = "pci-rcar-gen2",
546cadda	443	.suppress_bind_attrs = true,
d47b62f4	444	.of_match_table = rcar_pci_of_match,
ba3eb9fc	445	},
546cadda	446	.probe = rcar_pci_probe,
ba3eb9fc	447	};
0b9c1589	448	builtin_platform_driver(rcar_pci_driver);