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1da177e4 LT |
1 | /* |
2 | * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ | |
3 | * | |
4 | * PCI Bus Services, see include/linux/pci.h for further explanation. | |
5 | * | |
6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
7 | * David Mosberger-Tang | |
8 | * | |
9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
1da177e4 | 19 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 20 | #include "pci.h" |
1da177e4 | 21 | |
ffadcc2f | 22 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 23 | |
4516a618 AN |
24 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
25 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
26 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
27 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
28 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
29 | ||
1da177e4 LT |
30 | /** |
31 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
32 | * @bus: pointer to PCI bus structure to search | |
33 | * | |
34 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
35 | * including the given PCI bus and its list of child PCI buses. | |
36 | */ | |
37 | unsigned char __devinit | |
38 | pci_bus_max_busnr(struct pci_bus* bus) | |
39 | { | |
40 | struct list_head *tmp; | |
41 | unsigned char max, n; | |
42 | ||
b82db5ce | 43 | max = bus->subordinate; |
1da177e4 LT |
44 | list_for_each(tmp, &bus->children) { |
45 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
46 | if(n > max) | |
47 | max = n; | |
48 | } | |
49 | return max; | |
50 | } | |
b82db5ce | 51 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 52 | |
b82db5ce | 53 | #if 0 |
1da177e4 LT |
54 | /** |
55 | * pci_max_busnr - returns maximum PCI bus number | |
56 | * | |
57 | * Returns the highest PCI bus number present in the system global list of | |
58 | * PCI buses. | |
59 | */ | |
60 | unsigned char __devinit | |
61 | pci_max_busnr(void) | |
62 | { | |
63 | struct pci_bus *bus = NULL; | |
64 | unsigned char max, n; | |
65 | ||
66 | max = 0; | |
67 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
68 | n = pci_bus_max_busnr(bus); | |
69 | if(n > max) | |
70 | max = n; | |
71 | } | |
72 | return max; | |
73 | } | |
74 | ||
54c762fe AB |
75 | #endif /* 0 */ |
76 | ||
687d5fe3 ME |
77 | #define PCI_FIND_CAP_TTL 48 |
78 | ||
79 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
80 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
81 | { |
82 | u8 id; | |
24a4e377 | 83 | |
687d5fe3 | 84 | while ((*ttl)--) { |
24a4e377 RD |
85 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
86 | if (pos < 0x40) | |
87 | break; | |
88 | pos &= ~3; | |
89 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
90 | &id); | |
91 | if (id == 0xff) | |
92 | break; | |
93 | if (id == cap) | |
94 | return pos; | |
95 | pos += PCI_CAP_LIST_NEXT; | |
96 | } | |
97 | return 0; | |
98 | } | |
99 | ||
687d5fe3 ME |
100 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
101 | u8 pos, int cap) | |
102 | { | |
103 | int ttl = PCI_FIND_CAP_TTL; | |
104 | ||
105 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
106 | } | |
107 | ||
24a4e377 RD |
108 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
109 | { | |
110 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
111 | pos + PCI_CAP_LIST_NEXT, cap); | |
112 | } | |
113 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
114 | ||
d3bac118 ME |
115 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
116 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
117 | { |
118 | u16 status; | |
1da177e4 LT |
119 | |
120 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
121 | if (!(status & PCI_STATUS_CAP_LIST)) | |
122 | return 0; | |
123 | ||
124 | switch (hdr_type) { | |
125 | case PCI_HEADER_TYPE_NORMAL: | |
126 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 127 | return PCI_CAPABILITY_LIST; |
1da177e4 | 128 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 129 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
130 | default: |
131 | return 0; | |
132 | } | |
d3bac118 ME |
133 | |
134 | return 0; | |
1da177e4 LT |
135 | } |
136 | ||
137 | /** | |
138 | * pci_find_capability - query for devices' capabilities | |
139 | * @dev: PCI device to query | |
140 | * @cap: capability code | |
141 | * | |
142 | * Tell if a device supports a given PCI capability. | |
143 | * Returns the address of the requested capability structure within the | |
144 | * device's PCI configuration space or 0 in case the device does not | |
145 | * support it. Possible values for @cap: | |
146 | * | |
147 | * %PCI_CAP_ID_PM Power Management | |
148 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
149 | * %PCI_CAP_ID_VPD Vital Product Data | |
150 | * %PCI_CAP_ID_SLOTID Slot Identification | |
151 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
152 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
153 | * %PCI_CAP_ID_PCIX PCI-X | |
154 | * %PCI_CAP_ID_EXP PCI Express | |
155 | */ | |
156 | int pci_find_capability(struct pci_dev *dev, int cap) | |
157 | { | |
d3bac118 ME |
158 | int pos; |
159 | ||
160 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
161 | if (pos) | |
162 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
163 | ||
164 | return pos; | |
1da177e4 LT |
165 | } |
166 | ||
167 | /** | |
168 | * pci_bus_find_capability - query for devices' capabilities | |
169 | * @bus: the PCI bus to query | |
170 | * @devfn: PCI device to query | |
171 | * @cap: capability code | |
172 | * | |
173 | * Like pci_find_capability() but works for pci devices that do not have a | |
174 | * pci_dev structure set up yet. | |
175 | * | |
176 | * Returns the address of the requested capability structure within the | |
177 | * device's PCI configuration space or 0 in case the device does not | |
178 | * support it. | |
179 | */ | |
180 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
181 | { | |
d3bac118 | 182 | int pos; |
1da177e4 LT |
183 | u8 hdr_type; |
184 | ||
185 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
186 | ||
d3bac118 ME |
187 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
188 | if (pos) | |
189 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
190 | ||
191 | return pos; | |
1da177e4 LT |
192 | } |
193 | ||
194 | /** | |
195 | * pci_find_ext_capability - Find an extended capability | |
196 | * @dev: PCI device to query | |
197 | * @cap: capability code | |
198 | * | |
199 | * Returns the address of the requested extended capability structure | |
200 | * within the device's PCI configuration space or 0 if the device does | |
201 | * not support it. Possible values for @cap: | |
202 | * | |
203 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
204 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
205 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
206 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
207 | */ | |
208 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
209 | { | |
210 | u32 header; | |
211 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
212 | int pos = 0x100; | |
213 | ||
214 | if (dev->cfg_size <= 256) | |
215 | return 0; | |
216 | ||
217 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
218 | return 0; | |
219 | ||
220 | /* | |
221 | * If we have no capabilities, this is indicated by cap ID, | |
222 | * cap version and next pointer all being 0. | |
223 | */ | |
224 | if (header == 0) | |
225 | return 0; | |
226 | ||
227 | while (ttl-- > 0) { | |
228 | if (PCI_EXT_CAP_ID(header) == cap) | |
229 | return pos; | |
230 | ||
231 | pos = PCI_EXT_CAP_NEXT(header); | |
232 | if (pos < 0x100) | |
233 | break; | |
234 | ||
235 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
236 | break; | |
237 | } | |
238 | ||
239 | return 0; | |
240 | } | |
3a720d72 | 241 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 242 | |
687d5fe3 ME |
243 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
244 | { | |
245 | int rc, ttl = PCI_FIND_CAP_TTL; | |
246 | u8 cap, mask; | |
247 | ||
248 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
249 | mask = HT_3BIT_CAP_MASK; | |
250 | else | |
251 | mask = HT_5BIT_CAP_MASK; | |
252 | ||
253 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
254 | PCI_CAP_ID_HT, &ttl); | |
255 | while (pos) { | |
256 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
257 | if (rc != PCIBIOS_SUCCESSFUL) | |
258 | return 0; | |
259 | ||
260 | if ((cap & mask) == ht_cap) | |
261 | return pos; | |
262 | ||
47a4d5be BG |
263 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
264 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
265 | PCI_CAP_ID_HT, &ttl); |
266 | } | |
267 | ||
268 | return 0; | |
269 | } | |
270 | /** | |
271 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
272 | * @dev: PCI device to query | |
273 | * @pos: Position from which to continue searching | |
274 | * @ht_cap: Hypertransport capability code | |
275 | * | |
276 | * To be used in conjunction with pci_find_ht_capability() to search for | |
277 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
278 | * from pci_find_ht_capability(). | |
279 | * | |
280 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
281 | * steps to avoid an infinite loop. | |
282 | */ | |
283 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
284 | { | |
285 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
286 | } | |
287 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
288 | ||
289 | /** | |
290 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
291 | * @dev: PCI device to query | |
292 | * @ht_cap: Hypertransport capability code | |
293 | * | |
294 | * Tell if a device supports a given Hypertransport capability. | |
295 | * Returns an address within the device's PCI configuration space | |
296 | * or 0 in case the device does not support the request capability. | |
297 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
298 | * which has a Hypertransport capability matching @ht_cap. | |
299 | */ | |
300 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
301 | { | |
302 | int pos; | |
303 | ||
304 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
305 | if (pos) | |
306 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
307 | ||
308 | return pos; | |
309 | } | |
310 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
311 | ||
1da177e4 LT |
312 | /** |
313 | * pci_find_parent_resource - return resource region of parent bus of given region | |
314 | * @dev: PCI device structure contains resources to be searched | |
315 | * @res: child resource record for which parent is sought | |
316 | * | |
317 | * For given resource region of given device, return the resource | |
318 | * region of parent bus the given region is contained in or where | |
319 | * it should be allocated from. | |
320 | */ | |
321 | struct resource * | |
322 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
323 | { | |
324 | const struct pci_bus *bus = dev->bus; | |
325 | int i; | |
326 | struct resource *best = NULL; | |
327 | ||
328 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
329 | struct resource *r = bus->resource[i]; | |
330 | if (!r) | |
331 | continue; | |
332 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
333 | continue; /* Not contained */ | |
334 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
335 | continue; /* Wrong type */ | |
336 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
337 | return r; /* Exact match */ | |
338 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
339 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
340 | } | |
341 | return best; | |
342 | } | |
343 | ||
064b53db JL |
344 | /** |
345 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
346 | * @dev: PCI device to have its BARs restored | |
347 | * | |
348 | * Restore the BAR values for a given device, so as to make it | |
349 | * accessible by its driver. | |
350 | */ | |
351 | void | |
352 | pci_restore_bars(struct pci_dev *dev) | |
353 | { | |
354 | int i, numres; | |
355 | ||
356 | switch (dev->hdr_type) { | |
357 | case PCI_HEADER_TYPE_NORMAL: | |
358 | numres = 6; | |
359 | break; | |
360 | case PCI_HEADER_TYPE_BRIDGE: | |
361 | numres = 2; | |
362 | break; | |
363 | case PCI_HEADER_TYPE_CARDBUS: | |
364 | numres = 1; | |
365 | break; | |
366 | default: | |
367 | /* Should never get here, but just in case... */ | |
368 | return; | |
369 | } | |
370 | ||
371 | for (i = 0; i < numres; i ++) | |
372 | pci_update_resource(dev, &dev->resource[i], i); | |
373 | } | |
374 | ||
8f7020d3 RD |
375 | int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); |
376 | ||
1da177e4 LT |
377 | /** |
378 | * pci_set_power_state - Set the power state of a PCI device | |
379 | * @dev: PCI device to be suspended | |
380 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering | |
381 | * | |
382 | * Transition a device to a new power state, using the Power Management | |
383 | * Capabilities in the device's config space. | |
384 | * | |
385 | * RETURN VALUE: | |
386 | * -EINVAL if trying to enter a lower state than we're already in. | |
387 | * 0 if we're already in the requested state. | |
388 | * -EIO if device does not support PCI PM. | |
389 | * 0 if we can successfully change the power state. | |
390 | */ | |
1da177e4 LT |
391 | int |
392 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
393 | { | |
064b53db | 394 | int pm, need_restore = 0; |
1da177e4 LT |
395 | u16 pmcsr, pmc; |
396 | ||
397 | /* bound the state we're entering */ | |
398 | if (state > PCI_D3hot) | |
399 | state = PCI_D3hot; | |
400 | ||
e36c455c PM |
401 | /* |
402 | * If the device or the parent bridge can't support PCI PM, ignore | |
403 | * the request if we're doing anything besides putting it into D0 | |
404 | * (which would only happen on boot). | |
405 | */ | |
406 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
407 | return 0; | |
408 | ||
1da177e4 LT |
409 | /* Validate current state: |
410 | * Can enter D0 from any state, but if we can only go deeper | |
411 | * to sleep if we're already in a low power state | |
412 | */ | |
02669492 AM |
413 | if (state != PCI_D0 && dev->current_state > state) { |
414 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", | |
415 | __FUNCTION__, pci_name(dev), state, dev->current_state); | |
1da177e4 | 416 | return -EINVAL; |
02669492 | 417 | } else if (dev->current_state == state) |
1da177e4 LT |
418 | return 0; /* we're already there */ |
419 | ||
ffadcc2f | 420 | |
1da177e4 LT |
421 | /* find PCI PM capability in list */ |
422 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
423 | ||
424 | /* abort if the device doesn't support PM capabilities */ | |
425 | if (!pm) | |
426 | return -EIO; | |
427 | ||
428 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); | |
3fe9d19f | 429 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1da177e4 LT |
430 | printk(KERN_DEBUG |
431 | "PCI: %s has unsupported PM cap regs version (%u)\n", | |
432 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); | |
433 | return -EIO; | |
434 | } | |
435 | ||
436 | /* check if this device supports the desired state */ | |
3fe9d19f DR |
437 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
438 | return -EIO; | |
439 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) | |
440 | return -EIO; | |
1da177e4 | 441 | |
064b53db JL |
442 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
443 | ||
32a36585 | 444 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
445 | * This doesn't affect PME_Status, disables PME_En, and |
446 | * sets PowerState to 0. | |
447 | */ | |
32a36585 | 448 | switch (dev->current_state) { |
d3535fbb JL |
449 | case PCI_D0: |
450 | case PCI_D1: | |
451 | case PCI_D2: | |
452 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
453 | pmcsr |= state; | |
454 | break; | |
32a36585 JL |
455 | case PCI_UNKNOWN: /* Boot-up */ |
456 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
457 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
064b53db | 458 | need_restore = 1; |
32a36585 | 459 | /* Fall-through: force to D0 */ |
32a36585 | 460 | default: |
d3535fbb | 461 | pmcsr = 0; |
32a36585 | 462 | break; |
1da177e4 LT |
463 | } |
464 | ||
465 | /* enter specified state */ | |
466 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
467 | ||
468 | /* Mandatory power management transition delays */ | |
469 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
470 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 471 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
472 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
473 | udelay(200); | |
1da177e4 | 474 | |
b913100d DSL |
475 | /* |
476 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx | |
d6e05edc | 477 | * Firmware method after native method ? |
b913100d DSL |
478 | */ |
479 | if (platform_pci_set_power_state) | |
480 | platform_pci_set_power_state(dev, state); | |
481 | ||
482 | dev->current_state = state; | |
064b53db JL |
483 | |
484 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
485 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
486 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
487 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
488 | * For example, at least some versions of the 3c905B and the | |
489 | * 3c556B exhibit this behaviour. | |
490 | * | |
491 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
492 | * devices in a D3hot state at boot. Consequently, we need to | |
493 | * restore at least the BARs so that the device will be | |
494 | * accessible to its driver. | |
495 | */ | |
496 | if (need_restore) | |
497 | pci_restore_bars(dev); | |
498 | ||
1da177e4 LT |
499 | return 0; |
500 | } | |
501 | ||
f165b10f | 502 | int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); |
0f64474b | 503 | |
1da177e4 LT |
504 | /** |
505 | * pci_choose_state - Choose the power state of a PCI device | |
506 | * @dev: PCI device to be suspended | |
507 | * @state: target sleep state for the whole system. This is the value | |
508 | * that is passed to suspend() function. | |
509 | * | |
510 | * Returns PCI power state suitable for given device and given system | |
511 | * message. | |
512 | */ | |
513 | ||
514 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
515 | { | |
0f64474b DSL |
516 | int ret; |
517 | ||
1da177e4 LT |
518 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
519 | return PCI_D0; | |
520 | ||
0f64474b DSL |
521 | if (platform_pci_choose_state) { |
522 | ret = platform_pci_choose_state(dev, state); | |
523 | if (ret >= 0) | |
ca078bae | 524 | state.event = ret; |
0f64474b | 525 | } |
ca078bae PM |
526 | |
527 | switch (state.event) { | |
528 | case PM_EVENT_ON: | |
529 | return PCI_D0; | |
530 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
531 | case PM_EVENT_PRETHAW: |
532 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae PM |
533 | case PM_EVENT_SUSPEND: |
534 | return PCI_D3hot; | |
1da177e4 | 535 | default: |
b887d2e6 | 536 | printk("Unrecognized suspend event %d\n", state.event); |
1da177e4 LT |
537 | BUG(); |
538 | } | |
539 | return PCI_D0; | |
540 | } | |
541 | ||
542 | EXPORT_SYMBOL(pci_choose_state); | |
543 | ||
b56a5a23 MT |
544 | static int pci_save_pcie_state(struct pci_dev *dev) |
545 | { | |
546 | int pos, i = 0; | |
547 | struct pci_cap_saved_state *save_state; | |
548 | u16 *cap; | |
549 | ||
550 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
551 | if (pos <= 0) | |
552 | return 0; | |
553 | ||
554 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
555 | if (!save_state) { | |
556 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
557 | return -ENOMEM; | |
558 | } | |
559 | cap = (u16 *)&save_state->data[0]; | |
560 | ||
561 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
562 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
563 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
564 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
565 | pci_add_saved_cap(dev, save_state); | |
566 | return 0; | |
567 | } | |
568 | ||
569 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
570 | { | |
571 | int i = 0, pos; | |
572 | struct pci_cap_saved_state *save_state; | |
573 | u16 *cap; | |
574 | ||
575 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
576 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
577 | if (!save_state || pos <= 0) | |
578 | return; | |
579 | cap = (u16 *)&save_state->data[0]; | |
580 | ||
581 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
582 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
583 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
584 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
585 | pci_remove_saved_cap(save_state); | |
586 | kfree(save_state); | |
587 | } | |
588 | ||
cc692a5f SH |
589 | |
590 | static int pci_save_pcix_state(struct pci_dev *dev) | |
591 | { | |
592 | int pos, i = 0; | |
593 | struct pci_cap_saved_state *save_state; | |
594 | u16 *cap; | |
595 | ||
596 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
597 | if (pos <= 0) | |
598 | return 0; | |
599 | ||
600 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
601 | if (!save_state) { | |
602 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
603 | return -ENOMEM; | |
604 | } | |
605 | cap = (u16 *)&save_state->data[0]; | |
606 | ||
607 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
608 | pci_add_saved_cap(dev, save_state); | |
609 | return 0; | |
610 | } | |
611 | ||
612 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
613 | { | |
614 | int i = 0, pos; | |
615 | struct pci_cap_saved_state *save_state; | |
616 | u16 *cap; | |
617 | ||
618 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
619 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
620 | if (!save_state || pos <= 0) | |
621 | return; | |
622 | cap = (u16 *)&save_state->data[0]; | |
623 | ||
624 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
625 | pci_remove_saved_cap(save_state); | |
626 | kfree(save_state); | |
627 | } | |
628 | ||
629 | ||
1da177e4 LT |
630 | /** |
631 | * pci_save_state - save the PCI configuration space of a device before suspending | |
632 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
633 | */ |
634 | int | |
635 | pci_save_state(struct pci_dev *dev) | |
636 | { | |
637 | int i; | |
638 | /* XXX: 100% dword access ok here? */ | |
639 | for (i = 0; i < 16; i++) | |
640 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
41017f0c SL |
641 | if ((i = pci_save_msi_state(dev)) != 0) |
642 | return i; | |
b56a5a23 MT |
643 | if ((i = pci_save_pcie_state(dev)) != 0) |
644 | return i; | |
cc692a5f SH |
645 | if ((i = pci_save_pcix_state(dev)) != 0) |
646 | return i; | |
1da177e4 LT |
647 | return 0; |
648 | } | |
649 | ||
650 | /** | |
651 | * pci_restore_state - Restore the saved state of a PCI device | |
652 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
653 | */ |
654 | int | |
655 | pci_restore_state(struct pci_dev *dev) | |
656 | { | |
657 | int i; | |
04d9c1a1 | 658 | int val; |
1da177e4 | 659 | |
b56a5a23 MT |
660 | /* PCI Express register must be restored first */ |
661 | pci_restore_pcie_state(dev); | |
662 | ||
8b8c8d28 YL |
663 | /* |
664 | * The Base Address register should be programmed before the command | |
665 | * register(s) | |
666 | */ | |
667 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
668 | pci_read_config_dword(dev, i * 4, &val); |
669 | if (val != dev->saved_config_space[i]) { | |
670 | printk(KERN_DEBUG "PM: Writing back config space on " | |
671 | "device %s at offset %x (was %x, writing %x)\n", | |
672 | pci_name(dev), i, | |
673 | val, (int)dev->saved_config_space[i]); | |
674 | pci_write_config_dword(dev,i * 4, | |
675 | dev->saved_config_space[i]); | |
676 | } | |
677 | } | |
cc692a5f | 678 | pci_restore_pcix_state(dev); |
41017f0c | 679 | pci_restore_msi_state(dev); |
8fed4b65 | 680 | |
1da177e4 LT |
681 | return 0; |
682 | } | |
683 | ||
38cc1302 HS |
684 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
685 | { | |
686 | int err; | |
687 | ||
688 | err = pci_set_power_state(dev, PCI_D0); | |
689 | if (err < 0 && err != -EIO) | |
690 | return err; | |
691 | err = pcibios_enable_device(dev, bars); | |
692 | if (err < 0) | |
693 | return err; | |
694 | pci_fixup_device(pci_fixup_enable, dev); | |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
699 | /** | |
700 | * __pci_reenable_device - Resume abandoned device | |
701 | * @dev: PCI device to be resumed | |
702 | * | |
703 | * Note this function is a backend of pci_default_resume and is not supposed | |
704 | * to be called by normal code, write proper resume handler and use it instead. | |
705 | */ | |
706 | int | |
707 | __pci_reenable_device(struct pci_dev *dev) | |
708 | { | |
709 | if (atomic_read(&dev->enable_cnt)) | |
710 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
711 | return 0; | |
712 | } | |
713 | ||
1da177e4 LT |
714 | /** |
715 | * pci_enable_device_bars - Initialize some of a device for use | |
716 | * @dev: PCI device to be initialized | |
717 | * @bars: bitmask of BAR's that must be configured | |
718 | * | |
719 | * Initialize device before it's used by a driver. Ask low-level code | |
9fb625c3 | 720 | * to enable selected I/O and memory resources. Wake up the device if it |
1da177e4 LT |
721 | * was suspended. Beware, this function can fail. |
722 | */ | |
1da177e4 LT |
723 | int |
724 | pci_enable_device_bars(struct pci_dev *dev, int bars) | |
725 | { | |
726 | int err; | |
727 | ||
9fb625c3 HS |
728 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
729 | return 0; /* already enabled */ | |
730 | ||
38cc1302 | 731 | err = do_pci_enable_device(dev, bars); |
95a62965 | 732 | if (err < 0) |
38cc1302 | 733 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 734 | return err; |
1da177e4 LT |
735 | } |
736 | ||
bae94d02 IPG |
737 | /** |
738 | * pci_enable_device - Initialize device before it's used by a driver. | |
739 | * @dev: PCI device to be initialized | |
740 | * | |
741 | * Initialize device before it's used by a driver. Ask low-level code | |
742 | * to enable I/O and memory. Wake up the device if it was suspended. | |
743 | * Beware, this function can fail. | |
744 | * | |
745 | * Note we don't actually enable the device many times if we call | |
746 | * this function repeatedly (we just increment the count). | |
747 | */ | |
748 | int pci_enable_device(struct pci_dev *dev) | |
749 | { | |
9fb625c3 | 750 | return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); |
bae94d02 IPG |
751 | } |
752 | ||
9ac7849e TH |
753 | /* |
754 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
755 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
756 | * there's no need to track it separately. pci_devres is initialized | |
757 | * when a device is enabled using managed PCI device enable interface. | |
758 | */ | |
759 | struct pci_devres { | |
7f375f32 TH |
760 | unsigned int enabled:1; |
761 | unsigned int pinned:1; | |
9ac7849e TH |
762 | unsigned int orig_intx:1; |
763 | unsigned int restore_intx:1; | |
764 | u32 region_mask; | |
765 | }; | |
766 | ||
767 | static void pcim_release(struct device *gendev, void *res) | |
768 | { | |
769 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
770 | struct pci_devres *this = res; | |
771 | int i; | |
772 | ||
773 | if (dev->msi_enabled) | |
774 | pci_disable_msi(dev); | |
775 | if (dev->msix_enabled) | |
776 | pci_disable_msix(dev); | |
777 | ||
778 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
779 | if (this->region_mask & (1 << i)) | |
780 | pci_release_region(dev, i); | |
781 | ||
782 | if (this->restore_intx) | |
783 | pci_intx(dev, this->orig_intx); | |
784 | ||
7f375f32 | 785 | if (this->enabled && !this->pinned) |
9ac7849e TH |
786 | pci_disable_device(dev); |
787 | } | |
788 | ||
789 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
790 | { | |
791 | struct pci_devres *dr, *new_dr; | |
792 | ||
793 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
794 | if (dr) | |
795 | return dr; | |
796 | ||
797 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
798 | if (!new_dr) | |
799 | return NULL; | |
800 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
801 | } | |
802 | ||
803 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
804 | { | |
805 | if (pci_is_managed(pdev)) | |
806 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
807 | return NULL; | |
808 | } | |
809 | ||
810 | /** | |
811 | * pcim_enable_device - Managed pci_enable_device() | |
812 | * @pdev: PCI device to be initialized | |
813 | * | |
814 | * Managed pci_enable_device(). | |
815 | */ | |
816 | int pcim_enable_device(struct pci_dev *pdev) | |
817 | { | |
818 | struct pci_devres *dr; | |
819 | int rc; | |
820 | ||
821 | dr = get_pci_dr(pdev); | |
822 | if (unlikely(!dr)) | |
823 | return -ENOMEM; | |
7f375f32 | 824 | WARN_ON(!!dr->enabled); |
9ac7849e TH |
825 | |
826 | rc = pci_enable_device(pdev); | |
827 | if (!rc) { | |
828 | pdev->is_managed = 1; | |
7f375f32 | 829 | dr->enabled = 1; |
9ac7849e TH |
830 | } |
831 | return rc; | |
832 | } | |
833 | ||
834 | /** | |
835 | * pcim_pin_device - Pin managed PCI device | |
836 | * @pdev: PCI device to pin | |
837 | * | |
838 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
839 | * driver detach. @pdev must have been enabled with | |
840 | * pcim_enable_device(). | |
841 | */ | |
842 | void pcim_pin_device(struct pci_dev *pdev) | |
843 | { | |
844 | struct pci_devres *dr; | |
845 | ||
846 | dr = find_pci_dr(pdev); | |
7f375f32 | 847 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 848 | if (dr) |
7f375f32 | 849 | dr->pinned = 1; |
9ac7849e TH |
850 | } |
851 | ||
1da177e4 LT |
852 | /** |
853 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
854 | * @dev: the PCI device to disable | |
855 | * | |
856 | * Disables architecture specific PCI resources for the device. This | |
857 | * is the default implementation. Architecture implementations can | |
858 | * override this. | |
859 | */ | |
860 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
861 | ||
862 | /** | |
863 | * pci_disable_device - Disable PCI device after use | |
864 | * @dev: PCI device to be disabled | |
865 | * | |
866 | * Signal to the system that the PCI device is not in use by the system | |
867 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
868 | * |
869 | * Note we don't actually disable the device until all callers of | |
870 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
871 | */ |
872 | void | |
873 | pci_disable_device(struct pci_dev *dev) | |
874 | { | |
9ac7849e | 875 | struct pci_devres *dr; |
1da177e4 | 876 | u16 pci_command; |
99dc804d | 877 | |
9ac7849e TH |
878 | dr = find_pci_dr(dev); |
879 | if (dr) | |
7f375f32 | 880 | dr->enabled = 0; |
9ac7849e | 881 | |
bae94d02 IPG |
882 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
883 | return; | |
884 | ||
1da177e4 LT |
885 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
886 | if (pci_command & PCI_COMMAND_MASTER) { | |
887 | pci_command &= ~PCI_COMMAND_MASTER; | |
888 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
889 | } | |
ceb43744 | 890 | dev->is_busmaster = 0; |
1da177e4 LT |
891 | |
892 | pcibios_disable_device(dev); | |
893 | } | |
894 | ||
895 | /** | |
896 | * pci_enable_wake - enable device to generate PME# when suspended | |
897 | * @dev: - PCI device to operate on | |
898 | * @state: - Current state of device. | |
899 | * @enable: - Flag to enable or disable generation | |
900 | * | |
901 | * Set the bits in the device's PM Capabilities to generate PME# when | |
902 | * the system is suspended. | |
903 | * | |
904 | * -EIO is returned if device doesn't have PM Capabilities. | |
905 | * -EINVAL is returned if device supports it, but can't generate wake events. | |
906 | * 0 if operation is successful. | |
907 | * | |
908 | */ | |
909 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
910 | { | |
911 | int pm; | |
912 | u16 value; | |
913 | ||
914 | /* find PCI PM capability in list */ | |
915 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
916 | ||
917 | /* If device doesn't support PM Capabilities, but request is to disable | |
918 | * wake events, it's a nop; otherwise fail */ | |
919 | if (!pm) | |
920 | return enable ? -EIO : 0; | |
921 | ||
922 | /* Check device's ability to generate PME# */ | |
923 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
924 | ||
925 | value &= PCI_PM_CAP_PME_MASK; | |
926 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
927 | ||
928 | /* Check if it can generate PME# from requested state. */ | |
929 | if (!value || !(value & (1 << state))) | |
930 | return enable ? -EINVAL : 0; | |
931 | ||
932 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
933 | ||
934 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
935 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
936 | ||
937 | if (!enable) | |
938 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
939 | ||
940 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | int | |
946 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
947 | { | |
948 | u8 pin; | |
949 | ||
514d207d | 950 | pin = dev->pin; |
1da177e4 LT |
951 | if (!pin) |
952 | return -1; | |
953 | pin--; | |
954 | while (dev->bus->self) { | |
955 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
956 | dev = dev->bus->self; | |
957 | } | |
958 | *bridge = dev; | |
959 | return pin; | |
960 | } | |
961 | ||
962 | /** | |
963 | * pci_release_region - Release a PCI bar | |
964 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
965 | * @bar: BAR to release | |
966 | * | |
967 | * Releases the PCI I/O and memory resources previously reserved by a | |
968 | * successful call to pci_request_region. Call this function only | |
969 | * after all use of the PCI regions has ceased. | |
970 | */ | |
971 | void pci_release_region(struct pci_dev *pdev, int bar) | |
972 | { | |
9ac7849e TH |
973 | struct pci_devres *dr; |
974 | ||
1da177e4 LT |
975 | if (pci_resource_len(pdev, bar) == 0) |
976 | return; | |
977 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
978 | release_region(pci_resource_start(pdev, bar), | |
979 | pci_resource_len(pdev, bar)); | |
980 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
981 | release_mem_region(pci_resource_start(pdev, bar), | |
982 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
983 | |
984 | dr = find_pci_dr(pdev); | |
985 | if (dr) | |
986 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
987 | } |
988 | ||
989 | /** | |
990 | * pci_request_region - Reserved PCI I/O and memory resource | |
991 | * @pdev: PCI device whose resources are to be reserved | |
992 | * @bar: BAR to be reserved | |
993 | * @res_name: Name to be associated with resource. | |
994 | * | |
995 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
996 | * being reserved by owner @res_name. Do not access any | |
997 | * address inside the PCI regions unless this call returns | |
998 | * successfully. | |
999 | * | |
1000 | * Returns 0 on success, or %EBUSY on error. A warning | |
1001 | * message is also printed on failure. | |
1002 | */ | |
3c990e92 | 1003 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1004 | { |
9ac7849e TH |
1005 | struct pci_devres *dr; |
1006 | ||
1da177e4 LT |
1007 | if (pci_resource_len(pdev, bar) == 0) |
1008 | return 0; | |
1009 | ||
1010 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1011 | if (!request_region(pci_resource_start(pdev, bar), | |
1012 | pci_resource_len(pdev, bar), res_name)) | |
1013 | goto err_out; | |
1014 | } | |
1015 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1016 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1017 | pci_resource_len(pdev, bar), res_name)) | |
1018 | goto err_out; | |
1019 | } | |
9ac7849e TH |
1020 | |
1021 | dr = find_pci_dr(pdev); | |
1022 | if (dr) | |
1023 | dr->region_mask |= 1 << bar; | |
1024 | ||
1da177e4 LT |
1025 | return 0; |
1026 | ||
1027 | err_out: | |
1396a8c3 GKH |
1028 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx " |
1029 | "for device %s\n", | |
1da177e4 LT |
1030 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
1031 | bar + 1, /* PCI BAR # */ | |
1396a8c3 GKH |
1032 | (unsigned long long)pci_resource_len(pdev, bar), |
1033 | (unsigned long long)pci_resource_start(pdev, bar), | |
1da177e4 LT |
1034 | pci_name(pdev)); |
1035 | return -EBUSY; | |
1036 | } | |
1037 | ||
c87deff7 HS |
1038 | /** |
1039 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1040 | * @pdev: PCI device whose resources were previously reserved | |
1041 | * @bars: Bitmask of BARs to be released | |
1042 | * | |
1043 | * Release selected PCI I/O and memory resources previously reserved. | |
1044 | * Call this function only after all use of the PCI regions has ceased. | |
1045 | */ | |
1046 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1047 | { | |
1048 | int i; | |
1049 | ||
1050 | for (i = 0; i < 6; i++) | |
1051 | if (bars & (1 << i)) | |
1052 | pci_release_region(pdev, i); | |
1053 | } | |
1054 | ||
1055 | /** | |
1056 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1057 | * @pdev: PCI device whose resources are to be reserved | |
1058 | * @bars: Bitmask of BARs to be requested | |
1059 | * @res_name: Name to be associated with resource | |
1060 | */ | |
1061 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1062 | const char *res_name) | |
1063 | { | |
1064 | int i; | |
1065 | ||
1066 | for (i = 0; i < 6; i++) | |
1067 | if (bars & (1 << i)) | |
1068 | if(pci_request_region(pdev, i, res_name)) | |
1069 | goto err_out; | |
1070 | return 0; | |
1071 | ||
1072 | err_out: | |
1073 | while(--i >= 0) | |
1074 | if (bars & (1 << i)) | |
1075 | pci_release_region(pdev, i); | |
1076 | ||
1077 | return -EBUSY; | |
1078 | } | |
1da177e4 LT |
1079 | |
1080 | /** | |
1081 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1082 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1083 | * | |
1084 | * Releases all PCI I/O and memory resources previously reserved by a | |
1085 | * successful call to pci_request_regions. Call this function only | |
1086 | * after all use of the PCI regions has ceased. | |
1087 | */ | |
1088 | ||
1089 | void pci_release_regions(struct pci_dev *pdev) | |
1090 | { | |
c87deff7 | 1091 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1092 | } |
1093 | ||
1094 | /** | |
1095 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1096 | * @pdev: PCI device whose resources are to be reserved | |
1097 | * @res_name: Name to be associated with resource. | |
1098 | * | |
1099 | * Mark all PCI regions associated with PCI device @pdev as | |
1100 | * being reserved by owner @res_name. Do not access any | |
1101 | * address inside the PCI regions unless this call returns | |
1102 | * successfully. | |
1103 | * | |
1104 | * Returns 0 on success, or %EBUSY on error. A warning | |
1105 | * message is also printed on failure. | |
1106 | */ | |
3c990e92 | 1107 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1108 | { |
c87deff7 | 1109 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1110 | } |
1111 | ||
1112 | /** | |
1113 | * pci_set_master - enables bus-mastering for device dev | |
1114 | * @dev: the PCI device to enable | |
1115 | * | |
1116 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1117 | * to do the needed arch specific settings. | |
1118 | */ | |
1119 | void | |
1120 | pci_set_master(struct pci_dev *dev) | |
1121 | { | |
1122 | u16 cmd; | |
1123 | ||
1124 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1125 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
1126 | pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); | |
1127 | cmd |= PCI_COMMAND_MASTER; | |
1128 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1129 | } | |
1130 | dev->is_busmaster = 1; | |
1131 | pcibios_set_master(dev); | |
1132 | } | |
1133 | ||
edb2d97e MW |
1134 | #ifdef PCI_DISABLE_MWI |
1135 | int pci_set_mwi(struct pci_dev *dev) | |
1136 | { | |
1137 | return 0; | |
1138 | } | |
1139 | ||
1140 | void pci_clear_mwi(struct pci_dev *dev) | |
1141 | { | |
1142 | } | |
1143 | ||
1144 | #else | |
ebf5a248 MW |
1145 | |
1146 | #ifndef PCI_CACHE_LINE_BYTES | |
1147 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1148 | #endif | |
1149 | ||
1da177e4 | 1150 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1151 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1152 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1153 | |
1154 | /** | |
edb2d97e MW |
1155 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1156 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1157 | * |
edb2d97e MW |
1158 | * Helper function for pci_set_mwi. |
1159 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1160 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1161 | * | |
1162 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1163 | */ | |
1164 | static int | |
edb2d97e | 1165 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1166 | { |
1167 | u8 cacheline_size; | |
1168 | ||
1169 | if (!pci_cache_line_size) | |
1170 | return -EINVAL; /* The system doesn't support MWI. */ | |
1171 | ||
1172 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1173 | equal to or multiple of the right value. */ | |
1174 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1175 | if (cacheline_size >= pci_cache_line_size && | |
1176 | (cacheline_size % pci_cache_line_size) == 0) | |
1177 | return 0; | |
1178 | ||
1179 | /* Write the correct value. */ | |
1180 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1181 | /* Read it back. */ | |
1182 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1183 | if (cacheline_size == pci_cache_line_size) | |
1184 | return 0; | |
1185 | ||
1186 | printk(KERN_DEBUG "PCI: cache line size of %d is not supported " | |
1187 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); | |
1188 | ||
1189 | return -EINVAL; | |
1190 | } | |
1da177e4 LT |
1191 | |
1192 | /** | |
1193 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1194 | * @dev: the PCI device for which MWI is enabled | |
1195 | * | |
1196 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, | |
1197 | * and then calls @pcibios_set_mwi to do the needed arch specific | |
1198 | * operations or a generic mwi-prep function. | |
1199 | * | |
1200 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1201 | */ | |
1202 | int | |
1203 | pci_set_mwi(struct pci_dev *dev) | |
1204 | { | |
1205 | int rc; | |
1206 | u16 cmd; | |
1207 | ||
edb2d97e | 1208 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1209 | if (rc) |
1210 | return rc; | |
1211 | ||
1212 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1213 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
1214 | pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); | |
1215 | cmd |= PCI_COMMAND_INVALIDATE; | |
1216 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1217 | } | |
1218 | ||
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | /** | |
1223 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1224 | * @dev: the PCI device to disable | |
1225 | * | |
1226 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1227 | */ | |
1228 | void | |
1229 | pci_clear_mwi(struct pci_dev *dev) | |
1230 | { | |
1231 | u16 cmd; | |
1232 | ||
1233 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1234 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1235 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1236 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1237 | } | |
1238 | } | |
edb2d97e | 1239 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1240 | |
a04ce0ff BR |
1241 | /** |
1242 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1243 | * @pdev: the PCI device to operate on |
1244 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1245 | * |
1246 | * Enables/disables PCI INTx for device dev | |
1247 | */ | |
1248 | void | |
1249 | pci_intx(struct pci_dev *pdev, int enable) | |
1250 | { | |
1251 | u16 pci_command, new; | |
1252 | ||
1253 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1254 | ||
1255 | if (enable) { | |
1256 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1257 | } else { | |
1258 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1259 | } | |
1260 | ||
1261 | if (new != pci_command) { | |
9ac7849e TH |
1262 | struct pci_devres *dr; |
1263 | ||
2fd9d74b | 1264 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1265 | |
1266 | dr = find_pci_dr(pdev); | |
1267 | if (dr && !dr->restore_intx) { | |
1268 | dr->restore_intx = 1; | |
1269 | dr->orig_intx = !enable; | |
1270 | } | |
a04ce0ff BR |
1271 | } |
1272 | } | |
1273 | ||
f5f2b131 EB |
1274 | /** |
1275 | * pci_msi_off - disables any msi or msix capabilities | |
1276 | * @pdev: the PCI device to operate on | |
1277 | * | |
1278 | * If you want to use msi see pci_enable_msi and friends. | |
1279 | * This is a lower level primitive that allows us to disable | |
1280 | * msi operation at the device level. | |
1281 | */ | |
1282 | void pci_msi_off(struct pci_dev *dev) | |
1283 | { | |
1284 | int pos; | |
1285 | u16 control; | |
1286 | ||
1287 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1288 | if (pos) { | |
1289 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1290 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1291 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1292 | } | |
1293 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1294 | if (pos) { | |
1295 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1296 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1297 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1298 | } | |
1299 | } | |
1300 | ||
1da177e4 LT |
1301 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1302 | /* | |
1303 | * These can be overridden by arch-specific implementations | |
1304 | */ | |
1305 | int | |
1306 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1307 | { | |
1308 | if (!pci_dma_supported(dev, mask)) | |
1309 | return -EIO; | |
1310 | ||
1311 | dev->dma_mask = mask; | |
1312 | ||
1313 | return 0; | |
1314 | } | |
1315 | ||
1da177e4 LT |
1316 | int |
1317 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1318 | { | |
1319 | if (!pci_dma_supported(dev, mask)) | |
1320 | return -EIO; | |
1321 | ||
1322 | dev->dev.coherent_dma_mask = mask; | |
1323 | ||
1324 | return 0; | |
1325 | } | |
1326 | #endif | |
c87deff7 HS |
1327 | |
1328 | /** | |
1329 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 1330 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
1331 | * @flags: resource type mask to be selected |
1332 | * | |
1333 | * This helper routine makes bar mask from the type of resource. | |
1334 | */ | |
1335 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1336 | { | |
1337 | int i, bars = 0; | |
1338 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1339 | if (pci_resource_flags(dev, i) & flags) | |
1340 | bars |= (1 << i); | |
1341 | return bars; | |
1342 | } | |
1343 | ||
1da177e4 LT |
1344 | static int __devinit pci_init(void) |
1345 | { | |
1346 | struct pci_dev *dev = NULL; | |
1347 | ||
1348 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1349 | pci_fixup_device(pci_fixup_final, dev); | |
1350 | } | |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | static int __devinit pci_setup(char *str) | |
1355 | { | |
1356 | while (str) { | |
1357 | char *k = strchr(str, ','); | |
1358 | if (k) | |
1359 | *k++ = 0; | |
1360 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1361 | if (!strcmp(str, "nomsi")) { |
1362 | pci_no_msi(); | |
4516a618 AN |
1363 | } else if (!strncmp(str, "cbiosize=", 9)) { |
1364 | pci_cardbus_io_size = memparse(str + 9, &str); | |
1365 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
1366 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
1367 | } else { |
1368 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1369 | str); | |
1370 | } | |
1da177e4 LT |
1371 | } |
1372 | str = k; | |
1373 | } | |
0637a70a | 1374 | return 0; |
1da177e4 | 1375 | } |
0637a70a | 1376 | early_param("pci", pci_setup); |
1da177e4 LT |
1377 | |
1378 | device_initcall(pci_init); | |
1da177e4 | 1379 | |
064b53db | 1380 | EXPORT_SYMBOL_GPL(pci_restore_bars); |
1da177e4 LT |
1381 | EXPORT_SYMBOL(pci_enable_device_bars); |
1382 | EXPORT_SYMBOL(pci_enable_device); | |
9ac7849e TH |
1383 | EXPORT_SYMBOL(pcim_enable_device); |
1384 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 1385 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
1386 | EXPORT_SYMBOL(pci_find_capability); |
1387 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1388 | EXPORT_SYMBOL(pci_release_regions); | |
1389 | EXPORT_SYMBOL(pci_request_regions); | |
1390 | EXPORT_SYMBOL(pci_release_region); | |
1391 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1392 | EXPORT_SYMBOL(pci_release_selected_regions); |
1393 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1394 | EXPORT_SYMBOL(pci_set_master); |
1395 | EXPORT_SYMBOL(pci_set_mwi); | |
1396 | EXPORT_SYMBOL(pci_clear_mwi); | |
a04ce0ff | 1397 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1398 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1399 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1400 | EXPORT_SYMBOL(pci_assign_resource); | |
1401 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1402 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1403 | |
1404 | EXPORT_SYMBOL(pci_set_power_state); | |
1405 | EXPORT_SYMBOL(pci_save_state); | |
1406 | EXPORT_SYMBOL(pci_restore_state); | |
1407 | EXPORT_SYMBOL(pci_enable_wake); | |
1408 |