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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
229f5afd | 19 | #include <linux/log2.h> |
7d715a6c | 20 | #include <linux/pci-aspm.h> |
c300bd2f | 21 | #include <linux/pm_wakeup.h> |
8dd7f803 | 22 | #include <linux/interrupt.h> |
32a9a682 | 23 | #include <linux/device.h> |
b67ea761 | 24 | #include <linux/pm_runtime.h> |
608c3881 | 25 | #include <linux/pci_hotplug.h> |
284f5f9d | 26 | #include <asm-generic/pci-bridge.h> |
32a9a682 | 27 | #include <asm/setup.h> |
bc56b9e0 | 28 | #include "pci.h" |
1da177e4 | 29 | |
00240c38 AS |
30 | const char *pci_power_names[] = { |
31 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
32 | }; | |
33 | EXPORT_SYMBOL_GPL(pci_power_names); | |
34 | ||
93177a74 RW |
35 | int isa_dma_bridge_buggy; |
36 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
37 | ||
38 | int pci_pci_problems; | |
39 | EXPORT_SYMBOL(pci_pci_problems); | |
40 | ||
1ae861e6 RW |
41 | unsigned int pci_pm_d3_delay; |
42 | ||
df17e62e MG |
43 | static void pci_pme_list_scan(struct work_struct *work); |
44 | ||
45 | static LIST_HEAD(pci_pme_list); | |
46 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
47 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
48 | ||
49 | struct pci_pme_device { | |
50 | struct list_head list; | |
51 | struct pci_dev *dev; | |
52 | }; | |
53 | ||
54 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
55 | ||
1ae861e6 RW |
56 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
57 | { | |
58 | unsigned int delay = dev->d3_delay; | |
59 | ||
60 | if (delay < pci_pm_d3_delay) | |
61 | delay = pci_pm_d3_delay; | |
62 | ||
63 | msleep(delay); | |
64 | } | |
1da177e4 | 65 | |
32a2eea7 JG |
66 | #ifdef CONFIG_PCI_DOMAINS |
67 | int pci_domains_supported = 1; | |
68 | #endif | |
69 | ||
4516a618 AN |
70 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
71 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
72 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
73 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
74 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
75 | ||
28760489 EB |
76 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
77 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
78 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
79 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
80 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
81 | ||
5f39e670 | 82 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; |
b03e7495 | 83 | |
ac1aa47b JB |
84 | /* |
85 | * The default CLS is used if arch didn't set CLS explicitly and not | |
86 | * all pci devices agree on the same value. Arch can override either | |
87 | * the dfl or actual value as it sees fit. Don't forget this is | |
88 | * measured in 32-bit words, not bytes. | |
89 | */ | |
15856ad5 | 90 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
91 | u8 pci_cache_line_size; |
92 | ||
96c55900 MS |
93 | /* |
94 | * If we set up a device for bus mastering, we need to check the latency | |
95 | * timer as certain BIOSes forget to set it properly. | |
96 | */ | |
97 | unsigned int pcibios_max_latency = 255; | |
98 | ||
6748dcc2 RW |
99 | /* If set, the PCIe ARI capability will not be used. */ |
100 | static bool pcie_ari_disabled; | |
101 | ||
1da177e4 LT |
102 | /** |
103 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
104 | * @bus: pointer to PCI bus structure to search | |
105 | * | |
106 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
107 | * including the given PCI bus and its list of child PCI buses. | |
108 | */ | |
07656d83 | 109 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 110 | { |
94e6a9b9 | 111 | struct pci_bus *tmp; |
1da177e4 LT |
112 | unsigned char max, n; |
113 | ||
b918c62e | 114 | max = bus->busn_res.end; |
94e6a9b9 YW |
115 | list_for_each_entry(tmp, &bus->children, node) { |
116 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 117 | if (n > max) |
1da177e4 LT |
118 | max = n; |
119 | } | |
120 | return max; | |
121 | } | |
b82db5ce | 122 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 123 | |
1684f5dd AM |
124 | #ifdef CONFIG_HAS_IOMEM |
125 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
126 | { | |
127 | /* | |
128 | * Make sure the BAR is actually a memory resource, not an IO resource | |
129 | */ | |
130 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
131 | WARN_ON(1); | |
132 | return NULL; | |
133 | } | |
134 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
135 | pci_resource_len(pdev, bar)); | |
136 | } | |
137 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
138 | #endif | |
139 | ||
687d5fe3 ME |
140 | #define PCI_FIND_CAP_TTL 48 |
141 | ||
142 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
143 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
144 | { |
145 | u8 id; | |
24a4e377 | 146 | |
687d5fe3 | 147 | while ((*ttl)--) { |
24a4e377 RD |
148 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
149 | if (pos < 0x40) | |
150 | break; | |
151 | pos &= ~3; | |
152 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
153 | &id); | |
154 | if (id == 0xff) | |
155 | break; | |
156 | if (id == cap) | |
157 | return pos; | |
158 | pos += PCI_CAP_LIST_NEXT; | |
159 | } | |
160 | return 0; | |
161 | } | |
162 | ||
687d5fe3 ME |
163 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
164 | u8 pos, int cap) | |
165 | { | |
166 | int ttl = PCI_FIND_CAP_TTL; | |
167 | ||
168 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
169 | } | |
170 | ||
24a4e377 RD |
171 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
172 | { | |
173 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
174 | pos + PCI_CAP_LIST_NEXT, cap); | |
175 | } | |
176 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
177 | ||
d3bac118 ME |
178 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
179 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
180 | { |
181 | u16 status; | |
1da177e4 LT |
182 | |
183 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
184 | if (!(status & PCI_STATUS_CAP_LIST)) | |
185 | return 0; | |
186 | ||
187 | switch (hdr_type) { | |
188 | case PCI_HEADER_TYPE_NORMAL: | |
189 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 190 | return PCI_CAPABILITY_LIST; |
1da177e4 | 191 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 192 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
193 | default: |
194 | return 0; | |
195 | } | |
d3bac118 ME |
196 | |
197 | return 0; | |
1da177e4 LT |
198 | } |
199 | ||
200 | /** | |
f7625980 | 201 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
202 | * @dev: PCI device to query |
203 | * @cap: capability code | |
204 | * | |
205 | * Tell if a device supports a given PCI capability. | |
206 | * Returns the address of the requested capability structure within the | |
207 | * device's PCI configuration space or 0 in case the device does not | |
208 | * support it. Possible values for @cap: | |
209 | * | |
f7625980 BH |
210 | * %PCI_CAP_ID_PM Power Management |
211 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
212 | * %PCI_CAP_ID_VPD Vital Product Data | |
213 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 214 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 215 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
216 | * %PCI_CAP_ID_PCIX PCI-X |
217 | * %PCI_CAP_ID_EXP PCI Express | |
218 | */ | |
219 | int pci_find_capability(struct pci_dev *dev, int cap) | |
220 | { | |
d3bac118 ME |
221 | int pos; |
222 | ||
223 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
224 | if (pos) | |
225 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
226 | ||
227 | return pos; | |
1da177e4 | 228 | } |
b7fe9434 | 229 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
230 | |
231 | /** | |
f7625980 | 232 | * pci_bus_find_capability - query for devices' capabilities |
1da177e4 LT |
233 | * @bus: the PCI bus to query |
234 | * @devfn: PCI device to query | |
235 | * @cap: capability code | |
236 | * | |
237 | * Like pci_find_capability() but works for pci devices that do not have a | |
f7625980 | 238 | * pci_dev structure set up yet. |
1da177e4 LT |
239 | * |
240 | * Returns the address of the requested capability structure within the | |
241 | * device's PCI configuration space or 0 in case the device does not | |
242 | * support it. | |
243 | */ | |
244 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
245 | { | |
d3bac118 | 246 | int pos; |
1da177e4 LT |
247 | u8 hdr_type; |
248 | ||
249 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
250 | ||
d3bac118 ME |
251 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
252 | if (pos) | |
253 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
254 | ||
255 | return pos; | |
1da177e4 | 256 | } |
b7fe9434 | 257 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
258 | |
259 | /** | |
44a9a36f | 260 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 261 | * @dev: PCI device to query |
44a9a36f | 262 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
263 | * @cap: capability code |
264 | * | |
44a9a36f | 265 | * Returns the address of the next matching extended capability structure |
1da177e4 | 266 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
267 | * not support it. Some capabilities can occur several times, e.g., the |
268 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 269 | */ |
44a9a36f | 270 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
271 | { |
272 | u32 header; | |
557848c3 ZY |
273 | int ttl; |
274 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 275 | |
557848c3 ZY |
276 | /* minimum 8 bytes per capability */ |
277 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
278 | ||
279 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
280 | return 0; |
281 | ||
44a9a36f BH |
282 | if (start) |
283 | pos = start; | |
284 | ||
1da177e4 LT |
285 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
286 | return 0; | |
287 | ||
288 | /* | |
289 | * If we have no capabilities, this is indicated by cap ID, | |
290 | * cap version and next pointer all being 0. | |
291 | */ | |
292 | if (header == 0) | |
293 | return 0; | |
294 | ||
295 | while (ttl-- > 0) { | |
44a9a36f | 296 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
297 | return pos; |
298 | ||
299 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 300 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
301 | break; |
302 | ||
303 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
304 | break; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
44a9a36f BH |
309 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
310 | ||
311 | /** | |
312 | * pci_find_ext_capability - Find an extended capability | |
313 | * @dev: PCI device to query | |
314 | * @cap: capability code | |
315 | * | |
316 | * Returns the address of the requested extended capability structure | |
317 | * within the device's PCI configuration space or 0 if the device does | |
318 | * not support it. Possible values for @cap: | |
319 | * | |
320 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
321 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
322 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
323 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
324 | */ | |
325 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
326 | { | |
327 | return pci_find_next_ext_capability(dev, 0, cap); | |
328 | } | |
3a720d72 | 329 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 330 | |
687d5fe3 ME |
331 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
332 | { | |
333 | int rc, ttl = PCI_FIND_CAP_TTL; | |
334 | u8 cap, mask; | |
335 | ||
336 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
337 | mask = HT_3BIT_CAP_MASK; | |
338 | else | |
339 | mask = HT_5BIT_CAP_MASK; | |
340 | ||
341 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
342 | PCI_CAP_ID_HT, &ttl); | |
343 | while (pos) { | |
344 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
345 | if (rc != PCIBIOS_SUCCESSFUL) | |
346 | return 0; | |
347 | ||
348 | if ((cap & mask) == ht_cap) | |
349 | return pos; | |
350 | ||
47a4d5be BG |
351 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
352 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
353 | PCI_CAP_ID_HT, &ttl); |
354 | } | |
355 | ||
356 | return 0; | |
357 | } | |
358 | /** | |
359 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
360 | * @dev: PCI device to query | |
361 | * @pos: Position from which to continue searching | |
362 | * @ht_cap: Hypertransport capability code | |
363 | * | |
364 | * To be used in conjunction with pci_find_ht_capability() to search for | |
365 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
366 | * from pci_find_ht_capability(). | |
367 | * | |
368 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
369 | * steps to avoid an infinite loop. | |
370 | */ | |
371 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
372 | { | |
373 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
374 | } | |
375 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
376 | ||
377 | /** | |
378 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
379 | * @dev: PCI device to query | |
380 | * @ht_cap: Hypertransport capability code | |
381 | * | |
382 | * Tell if a device supports a given Hypertransport capability. | |
383 | * Returns an address within the device's PCI configuration space | |
384 | * or 0 in case the device does not support the request capability. | |
385 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
386 | * which has a Hypertransport capability matching @ht_cap. | |
387 | */ | |
388 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
389 | { | |
390 | int pos; | |
391 | ||
392 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
393 | if (pos) | |
394 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
395 | ||
396 | return pos; | |
397 | } | |
398 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
399 | ||
1da177e4 LT |
400 | /** |
401 | * pci_find_parent_resource - return resource region of parent bus of given region | |
402 | * @dev: PCI device structure contains resources to be searched | |
403 | * @res: child resource record for which parent is sought | |
404 | * | |
405 | * For given resource region of given device, return the resource | |
f44116ae | 406 | * region of parent bus the given region is contained in. |
1da177e4 | 407 | */ |
3c78bc61 RD |
408 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
409 | struct resource *res) | |
1da177e4 LT |
410 | { |
411 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 412 | struct resource *r; |
1da177e4 | 413 | int i; |
1da177e4 | 414 | |
89a74ecc | 415 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
416 | if (!r) |
417 | continue; | |
f44116ae BH |
418 | if (res->start && resource_contains(r, res)) { |
419 | ||
420 | /* | |
421 | * If the window is prefetchable but the BAR is | |
422 | * not, the allocator made a mistake. | |
423 | */ | |
424 | if (r->flags & IORESOURCE_PREFETCH && | |
425 | !(res->flags & IORESOURCE_PREFETCH)) | |
426 | return NULL; | |
427 | ||
428 | /* | |
429 | * If we're below a transparent bridge, there may | |
430 | * be both a positively-decoded aperture and a | |
431 | * subtractively-decoded region that contain the BAR. | |
432 | * We want the positively-decoded one, so this depends | |
433 | * on pci_bus_for_each_resource() giving us those | |
434 | * first. | |
435 | */ | |
436 | return r; | |
437 | } | |
1da177e4 | 438 | } |
f44116ae | 439 | return NULL; |
1da177e4 | 440 | } |
b7fe9434 | 441 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 442 | |
157e876f AW |
443 | /** |
444 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
445 | * @dev: the PCI device to operate on | |
446 | * @pos: config space offset of status word | |
447 | * @mask: mask of bit(s) to care about in status word | |
448 | * | |
449 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
450 | */ | |
451 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
452 | { | |
453 | int i; | |
454 | ||
455 | /* Wait for Transaction Pending bit clean */ | |
456 | for (i = 0; i < 4; i++) { | |
457 | u16 status; | |
458 | if (i) | |
459 | msleep((1 << (i - 1)) * 100); | |
460 | ||
461 | pci_read_config_word(dev, pos, &status); | |
462 | if (!(status & mask)) | |
463 | return 1; | |
464 | } | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
064b53db JL |
469 | /** |
470 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
471 | * @dev: PCI device to have its BARs restored | |
472 | * | |
473 | * Restore the BAR values for a given device, so as to make it | |
474 | * accessible by its driver. | |
475 | */ | |
3c78bc61 | 476 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 477 | { |
bc5f5a82 | 478 | int i; |
064b53db | 479 | |
bc5f5a82 | 480 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 481 | pci_update_resource(dev, i); |
064b53db JL |
482 | } |
483 | ||
961d9120 RW |
484 | static struct pci_platform_pm_ops *pci_platform_pm; |
485 | ||
486 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
487 | { | |
eb9d0fe4 | 488 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
d2e5f0c1 | 489 | || !ops->sleep_wake) |
961d9120 RW |
490 | return -EINVAL; |
491 | pci_platform_pm = ops; | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
496 | { | |
497 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
498 | } | |
499 | ||
500 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 501 | pci_power_t t) |
961d9120 RW |
502 | { |
503 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
504 | } | |
505 | ||
506 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
507 | { | |
508 | return pci_platform_pm ? | |
509 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
510 | } | |
8f7020d3 | 511 | |
eb9d0fe4 RW |
512 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
513 | { | |
514 | return pci_platform_pm ? | |
515 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
516 | } | |
517 | ||
b67ea761 RW |
518 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
519 | { | |
520 | return pci_platform_pm ? | |
521 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
522 | } | |
523 | ||
1da177e4 | 524 | /** |
44e4e66e RW |
525 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
526 | * given PCI device | |
527 | * @dev: PCI device to handle. | |
44e4e66e | 528 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 529 | * |
44e4e66e RW |
530 | * RETURN VALUE: |
531 | * -EINVAL if the requested state is invalid. | |
532 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
533 | * wrong version, or device doesn't support the requested state. | |
534 | * 0 if device already is in the requested state. | |
535 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 536 | */ |
f00a20ef | 537 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 538 | { |
337001b6 | 539 | u16 pmcsr; |
44e4e66e | 540 | bool need_restore = false; |
1da177e4 | 541 | |
4a865905 RW |
542 | /* Check if we're already there */ |
543 | if (dev->current_state == state) | |
544 | return 0; | |
545 | ||
337001b6 | 546 | if (!dev->pm_cap) |
cca03dec AL |
547 | return -EIO; |
548 | ||
44e4e66e RW |
549 | if (state < PCI_D0 || state > PCI_D3hot) |
550 | return -EINVAL; | |
551 | ||
1da177e4 | 552 | /* Validate current state: |
f7625980 | 553 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
554 | * to sleep if we're already in a low power state |
555 | */ | |
4a865905 | 556 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 557 | && dev->current_state > state) { |
227f0647 RD |
558 | dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", |
559 | dev->current_state, state); | |
1da177e4 | 560 | return -EINVAL; |
44e4e66e | 561 | } |
1da177e4 | 562 | |
1da177e4 | 563 | /* check if this device supports the desired state */ |
337001b6 RW |
564 | if ((state == PCI_D1 && !dev->d1_support) |
565 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 566 | return -EIO; |
1da177e4 | 567 | |
337001b6 | 568 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 569 | |
32a36585 | 570 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
571 | * This doesn't affect PME_Status, disables PME_En, and |
572 | * sets PowerState to 0. | |
573 | */ | |
32a36585 | 574 | switch (dev->current_state) { |
d3535fbb JL |
575 | case PCI_D0: |
576 | case PCI_D1: | |
577 | case PCI_D2: | |
578 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
579 | pmcsr |= state; | |
580 | break; | |
f62795f1 RW |
581 | case PCI_D3hot: |
582 | case PCI_D3cold: | |
32a36585 JL |
583 | case PCI_UNKNOWN: /* Boot-up */ |
584 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 585 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 586 | need_restore = true; |
32a36585 | 587 | /* Fall-through: force to D0 */ |
32a36585 | 588 | default: |
d3535fbb | 589 | pmcsr = 0; |
32a36585 | 590 | break; |
1da177e4 LT |
591 | } |
592 | ||
593 | /* enter specified state */ | |
337001b6 | 594 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
595 | |
596 | /* Mandatory power management transition delays */ | |
597 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
598 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 599 | pci_dev_d3_sleep(dev); |
1da177e4 | 600 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 601 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 602 | |
e13cdbd7 RW |
603 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
604 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
605 | if (dev->current_state != state && printk_ratelimit()) | |
227f0647 RD |
606 | dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", |
607 | dev->current_state); | |
064b53db | 608 | |
448bd857 HY |
609 | /* |
610 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
611 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
612 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
613 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
614 | * For example, at least some versions of the 3c905B and the | |
615 | * 3c556B exhibit this behaviour. | |
616 | * | |
617 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
618 | * devices in a D3hot state at boot. Consequently, we need to | |
619 | * restore at least the BARs so that the device will be | |
620 | * accessible to its driver. | |
621 | */ | |
622 | if (need_restore) | |
623 | pci_restore_bars(dev); | |
624 | ||
f00a20ef | 625 | if (dev->bus->self) |
7d715a6c SL |
626 | pcie_aspm_pm_state_change(dev->bus->self); |
627 | ||
1da177e4 LT |
628 | return 0; |
629 | } | |
630 | ||
44e4e66e RW |
631 | /** |
632 | * pci_update_current_state - Read PCI power state of given device from its | |
633 | * PCI PM registers and cache it | |
634 | * @dev: PCI device to handle. | |
f06fc0b6 | 635 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 636 | */ |
73410429 | 637 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 638 | { |
337001b6 | 639 | if (dev->pm_cap) { |
44e4e66e RW |
640 | u16 pmcsr; |
641 | ||
448bd857 HY |
642 | /* |
643 | * Configuration space is not accessible for device in | |
644 | * D3cold, so just keep or set D3cold for safety | |
645 | */ | |
646 | if (dev->current_state == PCI_D3cold) | |
647 | return; | |
648 | if (state == PCI_D3cold) { | |
649 | dev->current_state = PCI_D3cold; | |
650 | return; | |
651 | } | |
337001b6 | 652 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 653 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
654 | } else { |
655 | dev->current_state = state; | |
44e4e66e RW |
656 | } |
657 | } | |
658 | ||
db288c9c RW |
659 | /** |
660 | * pci_power_up - Put the given device into D0 forcibly | |
661 | * @dev: PCI device to power up | |
662 | */ | |
663 | void pci_power_up(struct pci_dev *dev) | |
664 | { | |
665 | if (platform_pci_power_manageable(dev)) | |
666 | platform_pci_set_power_state(dev, PCI_D0); | |
667 | ||
668 | pci_raw_set_power_state(dev, PCI_D0); | |
669 | pci_update_current_state(dev, PCI_D0); | |
670 | } | |
671 | ||
0e5dd46b RW |
672 | /** |
673 | * pci_platform_power_transition - Use platform to change device power state | |
674 | * @dev: PCI device to handle. | |
675 | * @state: State to put the device into. | |
676 | */ | |
677 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
678 | { | |
679 | int error; | |
680 | ||
681 | if (platform_pci_power_manageable(dev)) { | |
682 | error = platform_pci_set_power_state(dev, state); | |
683 | if (!error) | |
684 | pci_update_current_state(dev, state); | |
769ba721 | 685 | } else |
0e5dd46b | 686 | error = -ENODEV; |
769ba721 RW |
687 | |
688 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
689 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
690 | |
691 | return error; | |
692 | } | |
693 | ||
0b950f0f SH |
694 | /** |
695 | * pci_wakeup - Wake up a PCI device | |
696 | * @pci_dev: Device to handle. | |
697 | * @ign: ignored parameter | |
698 | */ | |
699 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
700 | { | |
701 | pci_wakeup_event(pci_dev); | |
702 | pm_request_resume(&pci_dev->dev); | |
703 | return 0; | |
704 | } | |
705 | ||
706 | /** | |
707 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
708 | * @bus: Top bus of the subtree to walk. | |
709 | */ | |
710 | static void pci_wakeup_bus(struct pci_bus *bus) | |
711 | { | |
712 | if (bus) | |
713 | pci_walk_bus(bus, pci_wakeup, NULL); | |
714 | } | |
715 | ||
0e5dd46b RW |
716 | /** |
717 | * __pci_start_power_transition - Start power transition of a PCI device | |
718 | * @dev: PCI device to handle. | |
719 | * @state: State to put the device into. | |
720 | */ | |
721 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
722 | { | |
448bd857 | 723 | if (state == PCI_D0) { |
0e5dd46b | 724 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
725 | /* |
726 | * Mandatory power management transition delays, see | |
727 | * PCI Express Base Specification Revision 2.0 Section | |
728 | * 6.6.1: Conventional Reset. Do not delay for | |
729 | * devices powered on/off by corresponding bridge, | |
730 | * because have already delayed for the bridge. | |
731 | */ | |
732 | if (dev->runtime_d3cold) { | |
733 | msleep(dev->d3cold_delay); | |
734 | /* | |
735 | * When powering on a bridge from D3cold, the | |
736 | * whole hierarchy may be powered on into | |
737 | * D0uninitialized state, resume them to give | |
738 | * them a chance to suspend again | |
739 | */ | |
740 | pci_wakeup_bus(dev->subordinate); | |
741 | } | |
742 | } | |
743 | } | |
744 | ||
745 | /** | |
746 | * __pci_dev_set_current_state - Set current state of a PCI device | |
747 | * @dev: Device to handle | |
748 | * @data: pointer to state to be set | |
749 | */ | |
750 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
751 | { | |
752 | pci_power_t state = *(pci_power_t *)data; | |
753 | ||
754 | dev->current_state = state; | |
755 | return 0; | |
756 | } | |
757 | ||
758 | /** | |
759 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
760 | * @bus: Top bus of the subtree to walk. | |
761 | * @state: state to be set | |
762 | */ | |
763 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
764 | { | |
765 | if (bus) | |
766 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
767 | } |
768 | ||
769 | /** | |
770 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
771 | * @dev: PCI device to handle. | |
772 | * @state: State to put the device into. | |
773 | * | |
774 | * This function should not be called directly by device drivers. | |
775 | */ | |
776 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
777 | { | |
448bd857 HY |
778 | int ret; |
779 | ||
db288c9c | 780 | if (state <= PCI_D0) |
448bd857 HY |
781 | return -EINVAL; |
782 | ret = pci_platform_power_transition(dev, state); | |
783 | /* Power off the bridge may power off the whole hierarchy */ | |
784 | if (!ret && state == PCI_D3cold) | |
785 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
786 | return ret; | |
0e5dd46b RW |
787 | } |
788 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
789 | ||
44e4e66e RW |
790 | /** |
791 | * pci_set_power_state - Set the power state of a PCI device | |
792 | * @dev: PCI device to handle. | |
793 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
794 | * | |
877d0310 | 795 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
796 | * the device's PCI PM registers. |
797 | * | |
798 | * RETURN VALUE: | |
799 | * -EINVAL if the requested state is invalid. | |
800 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
801 | * wrong version, or device doesn't support the requested state. | |
802 | * 0 if device already is in the requested state. | |
803 | * 0 if device's power state has been successfully changed. | |
804 | */ | |
805 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
806 | { | |
337001b6 | 807 | int error; |
44e4e66e RW |
808 | |
809 | /* bound the state we're entering */ | |
448bd857 HY |
810 | if (state > PCI_D3cold) |
811 | state = PCI_D3cold; | |
44e4e66e RW |
812 | else if (state < PCI_D0) |
813 | state = PCI_D0; | |
814 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
815 | /* | |
816 | * If the device or the parent bridge do not support PCI PM, | |
817 | * ignore the request if we're doing anything other than putting | |
818 | * it into D0 (which would only happen on boot). | |
819 | */ | |
820 | return 0; | |
821 | ||
db288c9c RW |
822 | /* Check if we're already there */ |
823 | if (dev->current_state == state) | |
824 | return 0; | |
825 | ||
0e5dd46b RW |
826 | __pci_start_power_transition(dev, state); |
827 | ||
979b1791 AC |
828 | /* This device is quirked not to be put into D3, so |
829 | don't put it in D3 */ | |
448bd857 | 830 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 831 | return 0; |
44e4e66e | 832 | |
448bd857 HY |
833 | /* |
834 | * To put device in D3cold, we put device into D3hot in native | |
835 | * way, then put device into D3cold with platform ops | |
836 | */ | |
837 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
838 | PCI_D3hot : state); | |
44e4e66e | 839 | |
0e5dd46b RW |
840 | if (!__pci_complete_power_transition(dev, state)) |
841 | error = 0; | |
44e4e66e RW |
842 | |
843 | return error; | |
844 | } | |
b7fe9434 | 845 | EXPORT_SYMBOL(pci_set_power_state); |
44e4e66e | 846 | |
1da177e4 LT |
847 | /** |
848 | * pci_choose_state - Choose the power state of a PCI device | |
849 | * @dev: PCI device to be suspended | |
850 | * @state: target sleep state for the whole system. This is the value | |
851 | * that is passed to suspend() function. | |
852 | * | |
853 | * Returns PCI power state suitable for given device and given system | |
854 | * message. | |
855 | */ | |
856 | ||
857 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
858 | { | |
ab826ca4 | 859 | pci_power_t ret; |
0f64474b | 860 | |
728cdb75 | 861 | if (!dev->pm_cap) |
1da177e4 LT |
862 | return PCI_D0; |
863 | ||
961d9120 RW |
864 | ret = platform_pci_choose_state(dev); |
865 | if (ret != PCI_POWER_ERROR) | |
866 | return ret; | |
ca078bae PM |
867 | |
868 | switch (state.event) { | |
869 | case PM_EVENT_ON: | |
870 | return PCI_D0; | |
871 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
872 | case PM_EVENT_PRETHAW: |
873 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 874 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 875 | case PM_EVENT_HIBERNATE: |
ca078bae | 876 | return PCI_D3hot; |
1da177e4 | 877 | default: |
80ccba11 BH |
878 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
879 | state.event); | |
1da177e4 LT |
880 | BUG(); |
881 | } | |
882 | return PCI_D0; | |
883 | } | |
1da177e4 LT |
884 | EXPORT_SYMBOL(pci_choose_state); |
885 | ||
89858517 YZ |
886 | #define PCI_EXP_SAVE_REGS 7 |
887 | ||
fd0f7f73 AW |
888 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
889 | u16 cap, bool extended) | |
34a4876e YL |
890 | { |
891 | struct pci_cap_saved_state *tmp; | |
34a4876e | 892 | |
b67bfe0d | 893 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 894 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
895 | return tmp; |
896 | } | |
897 | return NULL; | |
898 | } | |
899 | ||
fd0f7f73 AW |
900 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
901 | { | |
902 | return _pci_find_saved_cap(dev, cap, false); | |
903 | } | |
904 | ||
905 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
906 | { | |
907 | return _pci_find_saved_cap(dev, cap, true); | |
908 | } | |
909 | ||
b56a5a23 MT |
910 | static int pci_save_pcie_state(struct pci_dev *dev) |
911 | { | |
59875ae4 | 912 | int i = 0; |
b56a5a23 MT |
913 | struct pci_cap_saved_state *save_state; |
914 | u16 *cap; | |
915 | ||
59875ae4 | 916 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
917 | return 0; |
918 | ||
9f35575d | 919 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 920 | if (!save_state) { |
e496b617 | 921 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
922 | return -ENOMEM; |
923 | } | |
63f4898a | 924 | |
59875ae4 JL |
925 | cap = (u16 *)&save_state->cap.data[0]; |
926 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
927 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
928 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
929 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
930 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
931 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
932 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 933 | |
b56a5a23 MT |
934 | return 0; |
935 | } | |
936 | ||
937 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
938 | { | |
59875ae4 | 939 | int i = 0; |
b56a5a23 MT |
940 | struct pci_cap_saved_state *save_state; |
941 | u16 *cap; | |
942 | ||
943 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 944 | if (!save_state) |
9cb604ed MS |
945 | return; |
946 | ||
59875ae4 JL |
947 | cap = (u16 *)&save_state->cap.data[0]; |
948 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
949 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
950 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
951 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
952 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
953 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
954 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
955 | } |
956 | ||
cc692a5f SH |
957 | |
958 | static int pci_save_pcix_state(struct pci_dev *dev) | |
959 | { | |
63f4898a | 960 | int pos; |
cc692a5f | 961 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
962 | |
963 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
964 | if (pos <= 0) | |
965 | return 0; | |
966 | ||
f34303de | 967 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 968 | if (!save_state) { |
e496b617 | 969 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
970 | return -ENOMEM; |
971 | } | |
cc692a5f | 972 | |
24a4742f AW |
973 | pci_read_config_word(dev, pos + PCI_X_CMD, |
974 | (u16 *)save_state->cap.data); | |
63f4898a | 975 | |
cc692a5f SH |
976 | return 0; |
977 | } | |
978 | ||
979 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
980 | { | |
981 | int i = 0, pos; | |
982 | struct pci_cap_saved_state *save_state; | |
983 | u16 *cap; | |
984 | ||
985 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
986 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
987 | if (!save_state || pos <= 0) | |
988 | return; | |
24a4742f | 989 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
990 | |
991 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
992 | } |
993 | ||
994 | ||
1da177e4 LT |
995 | /** |
996 | * pci_save_state - save the PCI configuration space of a device before suspending | |
997 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 998 | */ |
3c78bc61 | 999 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1000 | { |
1001 | int i; | |
1002 | /* XXX: 100% dword access ok here? */ | |
1003 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1004 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1005 | dev->state_saved = true; |
79e50e72 QL |
1006 | |
1007 | i = pci_save_pcie_state(dev); | |
1008 | if (i != 0) | |
b56a5a23 | 1009 | return i; |
79e50e72 QL |
1010 | |
1011 | i = pci_save_pcix_state(dev); | |
1012 | if (i != 0) | |
cc692a5f | 1013 | return i; |
79e50e72 | 1014 | |
754834b9 | 1015 | return pci_save_vc_state(dev); |
1da177e4 | 1016 | } |
b7fe9434 | 1017 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1018 | |
ebfc5b80 RW |
1019 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
1020 | u32 saved_val, int retry) | |
1021 | { | |
1022 | u32 val; | |
1023 | ||
1024 | pci_read_config_dword(pdev, offset, &val); | |
1025 | if (val == saved_val) | |
1026 | return; | |
1027 | ||
1028 | for (;;) { | |
227f0647 RD |
1029 | dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
1030 | offset, val, saved_val); | |
ebfc5b80 RW |
1031 | pci_write_config_dword(pdev, offset, saved_val); |
1032 | if (retry-- <= 0) | |
1033 | return; | |
1034 | ||
1035 | pci_read_config_dword(pdev, offset, &val); | |
1036 | if (val == saved_val) | |
1037 | return; | |
1038 | ||
1039 | mdelay(1); | |
1040 | } | |
1041 | } | |
1042 | ||
a6cb9ee7 RW |
1043 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
1044 | int start, int end, int retry) | |
ebfc5b80 RW |
1045 | { |
1046 | int index; | |
1047 | ||
1048 | for (index = end; index >= start; index--) | |
1049 | pci_restore_config_dword(pdev, 4 * index, | |
1050 | pdev->saved_config_space[index], | |
1051 | retry); | |
1052 | } | |
1053 | ||
a6cb9ee7 RW |
1054 | static void pci_restore_config_space(struct pci_dev *pdev) |
1055 | { | |
1056 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
1057 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
1058 | /* Restore BARs before the command register. */ | |
1059 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
1060 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
1061 | } else { | |
1062 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
1063 | } | |
1064 | } | |
1065 | ||
f7625980 | 1066 | /** |
1da177e4 LT |
1067 | * pci_restore_state - Restore the saved state of a PCI device |
1068 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1069 | */ |
1d3c16a8 | 1070 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1071 | { |
c82f63e4 | 1072 | if (!dev->state_saved) |
1d3c16a8 | 1073 | return; |
4b77b0a2 | 1074 | |
b56a5a23 MT |
1075 | /* PCI Express register must be restored first */ |
1076 | pci_restore_pcie_state(dev); | |
1900ca13 | 1077 | pci_restore_ats_state(dev); |
425c1b22 | 1078 | pci_restore_vc_state(dev); |
b56a5a23 | 1079 | |
a6cb9ee7 | 1080 | pci_restore_config_space(dev); |
ebfc5b80 | 1081 | |
cc692a5f | 1082 | pci_restore_pcix_state(dev); |
41017f0c | 1083 | pci_restore_msi_state(dev); |
8c5cdb6a | 1084 | pci_restore_iov_state(dev); |
8fed4b65 | 1085 | |
4b77b0a2 | 1086 | dev->state_saved = false; |
1da177e4 | 1087 | } |
b7fe9434 | 1088 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1089 | |
ffbdd3f7 AW |
1090 | struct pci_saved_state { |
1091 | u32 config_space[16]; | |
1092 | struct pci_cap_saved_data cap[0]; | |
1093 | }; | |
1094 | ||
1095 | /** | |
1096 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1097 | * the device saved state. | |
1098 | * @dev: PCI device that we're dealing with | |
1099 | * | |
f7625980 | 1100 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1101 | */ |
1102 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1103 | { | |
1104 | struct pci_saved_state *state; | |
1105 | struct pci_cap_saved_state *tmp; | |
1106 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1107 | size_t size; |
1108 | ||
1109 | if (!dev->state_saved) | |
1110 | return NULL; | |
1111 | ||
1112 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1113 | ||
b67bfe0d | 1114 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1115 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1116 | ||
1117 | state = kzalloc(size, GFP_KERNEL); | |
1118 | if (!state) | |
1119 | return NULL; | |
1120 | ||
1121 | memcpy(state->config_space, dev->saved_config_space, | |
1122 | sizeof(state->config_space)); | |
1123 | ||
1124 | cap = state->cap; | |
b67bfe0d | 1125 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1126 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1127 | memcpy(cap, &tmp->cap, len); | |
1128 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1129 | } | |
1130 | /* Empty cap_save terminates list */ | |
1131 | ||
1132 | return state; | |
1133 | } | |
1134 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1135 | ||
1136 | /** | |
1137 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1138 | * @dev: PCI device that we're dealing with | |
1139 | * @state: Saved state returned from pci_store_saved_state() | |
1140 | */ | |
98d9b271 KRW |
1141 | int pci_load_saved_state(struct pci_dev *dev, |
1142 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1143 | { |
1144 | struct pci_cap_saved_data *cap; | |
1145 | ||
1146 | dev->state_saved = false; | |
1147 | ||
1148 | if (!state) | |
1149 | return 0; | |
1150 | ||
1151 | memcpy(dev->saved_config_space, state->config_space, | |
1152 | sizeof(state->config_space)); | |
1153 | ||
1154 | cap = state->cap; | |
1155 | while (cap->size) { | |
1156 | struct pci_cap_saved_state *tmp; | |
1157 | ||
fd0f7f73 | 1158 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1159 | if (!tmp || tmp->cap.size != cap->size) |
1160 | return -EINVAL; | |
1161 | ||
1162 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1163 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1164 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1165 | } | |
1166 | ||
1167 | dev->state_saved = true; | |
1168 | return 0; | |
1169 | } | |
98d9b271 | 1170 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1171 | |
1172 | /** | |
1173 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1174 | * and free the memory allocated for it. | |
1175 | * @dev: PCI device that we're dealing with | |
1176 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1177 | */ | |
1178 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1179 | struct pci_saved_state **state) | |
1180 | { | |
1181 | int ret = pci_load_saved_state(dev, *state); | |
1182 | kfree(*state); | |
1183 | *state = NULL; | |
1184 | return ret; | |
1185 | } | |
1186 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1187 | ||
8a9d5609 BH |
1188 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1189 | { | |
1190 | return pci_enable_resources(dev, bars); | |
1191 | } | |
1192 | ||
38cc1302 HS |
1193 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1194 | { | |
1195 | int err; | |
1f6ae47e | 1196 | struct pci_dev *bridge; |
1e2571a7 BH |
1197 | u16 cmd; |
1198 | u8 pin; | |
38cc1302 HS |
1199 | |
1200 | err = pci_set_power_state(dev, PCI_D0); | |
1201 | if (err < 0 && err != -EIO) | |
1202 | return err; | |
1f6ae47e VS |
1203 | |
1204 | bridge = pci_upstream_bridge(dev); | |
1205 | if (bridge) | |
1206 | pcie_aspm_powersave_config_link(bridge); | |
1207 | ||
38cc1302 HS |
1208 | err = pcibios_enable_device(dev, bars); |
1209 | if (err < 0) | |
1210 | return err; | |
1211 | pci_fixup_device(pci_fixup_enable, dev); | |
1212 | ||
866d5417 BH |
1213 | if (dev->msi_enabled || dev->msix_enabled) |
1214 | return 0; | |
1215 | ||
1e2571a7 BH |
1216 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1217 | if (pin) { | |
1218 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1219 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1220 | pci_write_config_word(dev, PCI_COMMAND, | |
1221 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1222 | } | |
1223 | ||
38cc1302 HS |
1224 | return 0; |
1225 | } | |
1226 | ||
1227 | /** | |
0b62e13b | 1228 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1229 | * @dev: PCI device to be resumed |
1230 | * | |
1231 | * Note this function is a backend of pci_default_resume and is not supposed | |
1232 | * to be called by normal code, write proper resume handler and use it instead. | |
1233 | */ | |
0b62e13b | 1234 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1235 | { |
296ccb08 | 1236 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1237 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1238 | return 0; | |
1239 | } | |
b7fe9434 | 1240 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1241 | |
928bea96 YL |
1242 | static void pci_enable_bridge(struct pci_dev *dev) |
1243 | { | |
79272138 | 1244 | struct pci_dev *bridge; |
928bea96 YL |
1245 | int retval; |
1246 | ||
79272138 BH |
1247 | bridge = pci_upstream_bridge(dev); |
1248 | if (bridge) | |
1249 | pci_enable_bridge(bridge); | |
928bea96 | 1250 | |
cf3e1feb | 1251 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1252 | if (!dev->is_busmaster) |
cf3e1feb | 1253 | pci_set_master(dev); |
928bea96 | 1254 | return; |
cf3e1feb YL |
1255 | } |
1256 | ||
928bea96 YL |
1257 | retval = pci_enable_device(dev); |
1258 | if (retval) | |
1259 | dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", | |
1260 | retval); | |
1261 | pci_set_master(dev); | |
1262 | } | |
1263 | ||
b4b4fbba | 1264 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1265 | { |
79272138 | 1266 | struct pci_dev *bridge; |
1da177e4 | 1267 | int err; |
b718989d | 1268 | int i, bars = 0; |
1da177e4 | 1269 | |
97c145f7 JB |
1270 | /* |
1271 | * Power state could be unknown at this point, either due to a fresh | |
1272 | * boot or a device removal call. So get the current power state | |
1273 | * so that things like MSI message writing will behave as expected | |
1274 | * (e.g. if the device really is in D0 at enable time). | |
1275 | */ | |
1276 | if (dev->pm_cap) { | |
1277 | u16 pmcsr; | |
1278 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1279 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1280 | } | |
1281 | ||
cc7ba39b | 1282 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1283 | return 0; /* already enabled */ |
1284 | ||
79272138 BH |
1285 | bridge = pci_upstream_bridge(dev); |
1286 | if (bridge) | |
1287 | pci_enable_bridge(bridge); | |
928bea96 | 1288 | |
497f16f2 YL |
1289 | /* only skip sriov related */ |
1290 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1291 | if (dev->resource[i].flags & flags) | |
1292 | bars |= (1 << i); | |
1293 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1294 | if (dev->resource[i].flags & flags) |
1295 | bars |= (1 << i); | |
1296 | ||
38cc1302 | 1297 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1298 | if (err < 0) |
38cc1302 | 1299 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1300 | return err; |
1da177e4 LT |
1301 | } |
1302 | ||
b718989d BH |
1303 | /** |
1304 | * pci_enable_device_io - Initialize a device for use with IO space | |
1305 | * @dev: PCI device to be initialized | |
1306 | * | |
1307 | * Initialize device before it's used by a driver. Ask low-level code | |
1308 | * to enable I/O resources. Wake up the device if it was suspended. | |
1309 | * Beware, this function can fail. | |
1310 | */ | |
1311 | int pci_enable_device_io(struct pci_dev *dev) | |
1312 | { | |
b4b4fbba | 1313 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1314 | } |
b7fe9434 | 1315 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1316 | |
1317 | /** | |
1318 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1319 | * @dev: PCI device to be initialized | |
1320 | * | |
1321 | * Initialize device before it's used by a driver. Ask low-level code | |
1322 | * to enable Memory resources. Wake up the device if it was suspended. | |
1323 | * Beware, this function can fail. | |
1324 | */ | |
1325 | int pci_enable_device_mem(struct pci_dev *dev) | |
1326 | { | |
b4b4fbba | 1327 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1328 | } |
b7fe9434 | 1329 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1330 | |
bae94d02 IPG |
1331 | /** |
1332 | * pci_enable_device - Initialize device before it's used by a driver. | |
1333 | * @dev: PCI device to be initialized | |
1334 | * | |
1335 | * Initialize device before it's used by a driver. Ask low-level code | |
1336 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1337 | * Beware, this function can fail. | |
1338 | * | |
1339 | * Note we don't actually enable the device many times if we call | |
1340 | * this function repeatedly (we just increment the count). | |
1341 | */ | |
1342 | int pci_enable_device(struct pci_dev *dev) | |
1343 | { | |
b4b4fbba | 1344 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1345 | } |
b7fe9434 | 1346 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1347 | |
9ac7849e TH |
1348 | /* |
1349 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1350 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1351 | * there's no need to track it separately. pci_devres is initialized | |
1352 | * when a device is enabled using managed PCI device enable interface. | |
1353 | */ | |
1354 | struct pci_devres { | |
7f375f32 TH |
1355 | unsigned int enabled:1; |
1356 | unsigned int pinned:1; | |
9ac7849e TH |
1357 | unsigned int orig_intx:1; |
1358 | unsigned int restore_intx:1; | |
1359 | u32 region_mask; | |
1360 | }; | |
1361 | ||
1362 | static void pcim_release(struct device *gendev, void *res) | |
1363 | { | |
1364 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
1365 | struct pci_devres *this = res; | |
1366 | int i; | |
1367 | ||
1368 | if (dev->msi_enabled) | |
1369 | pci_disable_msi(dev); | |
1370 | if (dev->msix_enabled) | |
1371 | pci_disable_msix(dev); | |
1372 | ||
1373 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1374 | if (this->region_mask & (1 << i)) | |
1375 | pci_release_region(dev, i); | |
1376 | ||
1377 | if (this->restore_intx) | |
1378 | pci_intx(dev, this->orig_intx); | |
1379 | ||
7f375f32 | 1380 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1381 | pci_disable_device(dev); |
1382 | } | |
1383 | ||
07656d83 | 1384 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1385 | { |
1386 | struct pci_devres *dr, *new_dr; | |
1387 | ||
1388 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1389 | if (dr) | |
1390 | return dr; | |
1391 | ||
1392 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1393 | if (!new_dr) | |
1394 | return NULL; | |
1395 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1396 | } | |
1397 | ||
07656d83 | 1398 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1399 | { |
1400 | if (pci_is_managed(pdev)) | |
1401 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1402 | return NULL; | |
1403 | } | |
1404 | ||
1405 | /** | |
1406 | * pcim_enable_device - Managed pci_enable_device() | |
1407 | * @pdev: PCI device to be initialized | |
1408 | * | |
1409 | * Managed pci_enable_device(). | |
1410 | */ | |
1411 | int pcim_enable_device(struct pci_dev *pdev) | |
1412 | { | |
1413 | struct pci_devres *dr; | |
1414 | int rc; | |
1415 | ||
1416 | dr = get_pci_dr(pdev); | |
1417 | if (unlikely(!dr)) | |
1418 | return -ENOMEM; | |
b95d58ea TH |
1419 | if (dr->enabled) |
1420 | return 0; | |
9ac7849e TH |
1421 | |
1422 | rc = pci_enable_device(pdev); | |
1423 | if (!rc) { | |
1424 | pdev->is_managed = 1; | |
7f375f32 | 1425 | dr->enabled = 1; |
9ac7849e TH |
1426 | } |
1427 | return rc; | |
1428 | } | |
b7fe9434 | 1429 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1430 | |
1431 | /** | |
1432 | * pcim_pin_device - Pin managed PCI device | |
1433 | * @pdev: PCI device to pin | |
1434 | * | |
1435 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1436 | * driver detach. @pdev must have been enabled with | |
1437 | * pcim_enable_device(). | |
1438 | */ | |
1439 | void pcim_pin_device(struct pci_dev *pdev) | |
1440 | { | |
1441 | struct pci_devres *dr; | |
1442 | ||
1443 | dr = find_pci_dr(pdev); | |
7f375f32 | 1444 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1445 | if (dr) |
7f375f32 | 1446 | dr->pinned = 1; |
9ac7849e | 1447 | } |
b7fe9434 | 1448 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1449 | |
eca0d467 MG |
1450 | /* |
1451 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1452 | * @dev: the PCI device being added | |
1453 | * | |
1454 | * Permits the platform to provide architecture specific functionality when | |
1455 | * devices are added. This is the default implementation. Architecture | |
1456 | * implementations can override this. | |
1457 | */ | |
3c78bc61 | 1458 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
1459 | { |
1460 | return 0; | |
1461 | } | |
1462 | ||
6ae32c53 SO |
1463 | /** |
1464 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1465 | * @dev: the PCI device being released | |
1466 | * | |
1467 | * Permits the platform to provide architecture specific functionality when | |
1468 | * devices are released. This is the default implementation. Architecture | |
1469 | * implementations can override this. | |
1470 | */ | |
1471 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1472 | ||
1da177e4 LT |
1473 | /** |
1474 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1475 | * @dev: the PCI device to disable | |
1476 | * | |
1477 | * Disables architecture specific PCI resources for the device. This | |
1478 | * is the default implementation. Architecture implementations can | |
1479 | * override this. | |
1480 | */ | |
d6d88c83 | 1481 | void __weak pcibios_disable_device (struct pci_dev *dev) {} |
1da177e4 | 1482 | |
a43ae58c HG |
1483 | /** |
1484 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1485 | * @irq: ISA IRQ to penalize | |
1486 | * @active: IRQ active or not | |
1487 | * | |
1488 | * Permits the platform to provide architecture-specific functionality when | |
1489 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1490 | * implementations can override this. | |
1491 | */ | |
1492 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1493 | ||
fa58d305 RW |
1494 | static void do_pci_disable_device(struct pci_dev *dev) |
1495 | { | |
1496 | u16 pci_command; | |
1497 | ||
1498 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1499 | if (pci_command & PCI_COMMAND_MASTER) { | |
1500 | pci_command &= ~PCI_COMMAND_MASTER; | |
1501 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1502 | } | |
1503 | ||
1504 | pcibios_disable_device(dev); | |
1505 | } | |
1506 | ||
1507 | /** | |
1508 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1509 | * @dev: PCI device to disable | |
1510 | * | |
1511 | * NOTE: This function is a backend of PCI power management routines and is | |
1512 | * not supposed to be called drivers. | |
1513 | */ | |
1514 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1515 | { | |
296ccb08 | 1516 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1517 | do_pci_disable_device(dev); |
1518 | } | |
1519 | ||
1da177e4 LT |
1520 | /** |
1521 | * pci_disable_device - Disable PCI device after use | |
1522 | * @dev: PCI device to be disabled | |
1523 | * | |
1524 | * Signal to the system that the PCI device is not in use by the system | |
1525 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1526 | * |
1527 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1528 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 1529 | */ |
3c78bc61 | 1530 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 1531 | { |
9ac7849e | 1532 | struct pci_devres *dr; |
99dc804d | 1533 | |
9ac7849e TH |
1534 | dr = find_pci_dr(dev); |
1535 | if (dr) | |
7f375f32 | 1536 | dr->enabled = 0; |
9ac7849e | 1537 | |
fd6dceab KK |
1538 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1539 | "disabling already-disabled device"); | |
1540 | ||
cc7ba39b | 1541 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1542 | return; |
1543 | ||
fa58d305 | 1544 | do_pci_disable_device(dev); |
1da177e4 | 1545 | |
fa58d305 | 1546 | dev->is_busmaster = 0; |
1da177e4 | 1547 | } |
b7fe9434 | 1548 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1549 | |
f7bdd12d BK |
1550 | /** |
1551 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1552 | * @dev: the PCIe device reset |
f7bdd12d BK |
1553 | * @state: Reset state to enter into |
1554 | * | |
1555 | * | |
45e829ea | 1556 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1557 | * implementation. Architecture implementations can override this. |
1558 | */ | |
d6d88c83 BH |
1559 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1560 | enum pcie_reset_state state) | |
f7bdd12d BK |
1561 | { |
1562 | return -EINVAL; | |
1563 | } | |
1564 | ||
1565 | /** | |
1566 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1567 | * @dev: the PCIe device reset |
f7bdd12d BK |
1568 | * @state: Reset state to enter into |
1569 | * | |
1570 | * | |
1571 | * Sets the PCI reset state for the device. | |
1572 | */ | |
1573 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1574 | { | |
1575 | return pcibios_set_pcie_reset_state(dev, state); | |
1576 | } | |
b7fe9434 | 1577 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 1578 | |
58ff4633 RW |
1579 | /** |
1580 | * pci_check_pme_status - Check if given device has generated PME. | |
1581 | * @dev: Device to check. | |
1582 | * | |
1583 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1584 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1585 | * 'false' otherwise. | |
1586 | */ | |
1587 | bool pci_check_pme_status(struct pci_dev *dev) | |
1588 | { | |
1589 | int pmcsr_pos; | |
1590 | u16 pmcsr; | |
1591 | bool ret = false; | |
1592 | ||
1593 | if (!dev->pm_cap) | |
1594 | return false; | |
1595 | ||
1596 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1597 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1598 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1599 | return false; | |
1600 | ||
1601 | /* Clear PME status. */ | |
1602 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1603 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1604 | /* Disable PME to avoid interrupt flood. */ | |
1605 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1606 | ret = true; | |
1607 | } | |
1608 | ||
1609 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1610 | ||
1611 | return ret; | |
1612 | } | |
1613 | ||
b67ea761 RW |
1614 | /** |
1615 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1616 | * @dev: Device to handle. | |
379021d5 | 1617 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1618 | * |
1619 | * Check if @dev has generated PME and queue a resume request for it in that | |
1620 | * case. | |
1621 | */ | |
379021d5 | 1622 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1623 | { |
379021d5 RW |
1624 | if (pme_poll_reset && dev->pme_poll) |
1625 | dev->pme_poll = false; | |
1626 | ||
c125e96f | 1627 | if (pci_check_pme_status(dev)) { |
c125e96f | 1628 | pci_wakeup_event(dev); |
0f953bf6 | 1629 | pm_request_resume(&dev->dev); |
c125e96f | 1630 | } |
b67ea761 RW |
1631 | return 0; |
1632 | } | |
1633 | ||
1634 | /** | |
1635 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1636 | * @bus: Top bus of the subtree to walk. | |
1637 | */ | |
1638 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1639 | { | |
1640 | if (bus) | |
379021d5 | 1641 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1642 | } |
1643 | ||
448bd857 | 1644 | |
eb9d0fe4 RW |
1645 | /** |
1646 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1647 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1648 | * @state: PCI state from which device will issue PME#. |
1649 | */ | |
e5899e1b | 1650 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1651 | { |
337001b6 | 1652 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1653 | return false; |
1654 | ||
337001b6 | 1655 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 1656 | } |
b7fe9434 | 1657 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 1658 | |
df17e62e MG |
1659 | static void pci_pme_list_scan(struct work_struct *work) |
1660 | { | |
379021d5 | 1661 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1662 | |
1663 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
1664 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1665 | if (pme_dev->dev->pme_poll) { | |
1666 | struct pci_dev *bridge; | |
1667 | ||
1668 | bridge = pme_dev->dev->bus->self; | |
1669 | /* | |
1670 | * If bridge is in low power state, the | |
1671 | * configuration space of subordinate devices | |
1672 | * may be not accessible | |
1673 | */ | |
1674 | if (bridge && bridge->current_state != PCI_D0) | |
1675 | continue; | |
1676 | pci_pme_wakeup(pme_dev->dev, NULL); | |
1677 | } else { | |
1678 | list_del(&pme_dev->list); | |
1679 | kfree(pme_dev); | |
379021d5 | 1680 | } |
df17e62e | 1681 | } |
ce300008 BH |
1682 | if (!list_empty(&pci_pme_list)) |
1683 | schedule_delayed_work(&pci_pme_work, | |
1684 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1685 | mutex_unlock(&pci_pme_list_mutex); |
1686 | } | |
1687 | ||
eb9d0fe4 RW |
1688 | /** |
1689 | * pci_pme_active - enable or disable PCI device's PME# function | |
1690 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1691 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1692 | * | |
1693 | * The caller must verify that the device is capable of generating PME# before | |
1694 | * calling this function with @enable equal to 'true'. | |
1695 | */ | |
5a6c9b60 | 1696 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1697 | { |
1698 | u16 pmcsr; | |
1699 | ||
ffaddbe8 | 1700 | if (!dev->pme_support) |
eb9d0fe4 RW |
1701 | return; |
1702 | ||
337001b6 | 1703 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1704 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1705 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1706 | if (!enable) | |
1707 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1708 | ||
337001b6 | 1709 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 | 1710 | |
6e965e0d HY |
1711 | /* |
1712 | * PCI (as opposed to PCIe) PME requires that the device have | |
1713 | * its PME# line hooked up correctly. Not all hardware vendors | |
1714 | * do this, so the PME never gets delivered and the device | |
1715 | * remains asleep. The easiest way around this is to | |
1716 | * periodically walk the list of suspended devices and check | |
1717 | * whether any have their PME flag set. The assumption is that | |
1718 | * we'll wake up often enough anyway that this won't be a huge | |
1719 | * hit, and the power savings from the devices will still be a | |
1720 | * win. | |
1721 | * | |
1722 | * Although PCIe uses in-band PME message instead of PME# line | |
1723 | * to report PME, PME does not work for some PCIe devices in | |
1724 | * reality. For example, there are devices that set their PME | |
1725 | * status bits, but don't really bother to send a PME message; | |
1726 | * there are PCI Express Root Ports that don't bother to | |
1727 | * trigger interrupts when they receive PME messages from the | |
1728 | * devices below. So PME poll is used for PCIe devices too. | |
1729 | */ | |
df17e62e | 1730 | |
379021d5 | 1731 | if (dev->pme_poll) { |
df17e62e MG |
1732 | struct pci_pme_device *pme_dev; |
1733 | if (enable) { | |
1734 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1735 | GFP_KERNEL); | |
0394cb19 BH |
1736 | if (!pme_dev) { |
1737 | dev_warn(&dev->dev, "can't enable PME#\n"); | |
1738 | return; | |
1739 | } | |
df17e62e MG |
1740 | pme_dev->dev = dev; |
1741 | mutex_lock(&pci_pme_list_mutex); | |
1742 | list_add(&pme_dev->list, &pci_pme_list); | |
1743 | if (list_is_singular(&pci_pme_list)) | |
1744 | schedule_delayed_work(&pci_pme_work, | |
1745 | msecs_to_jiffies(PME_TIMEOUT)); | |
1746 | mutex_unlock(&pci_pme_list_mutex); | |
1747 | } else { | |
1748 | mutex_lock(&pci_pme_list_mutex); | |
1749 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1750 | if (pme_dev->dev == dev) { | |
1751 | list_del(&pme_dev->list); | |
1752 | kfree(pme_dev); | |
1753 | break; | |
1754 | } | |
1755 | } | |
1756 | mutex_unlock(&pci_pme_list_mutex); | |
1757 | } | |
1758 | } | |
1759 | ||
85b8582d | 1760 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 1761 | } |
b7fe9434 | 1762 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 1763 | |
1da177e4 | 1764 | /** |
6cbf8214 | 1765 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1766 | * @dev: PCI device affected |
1767 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1768 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1769 | * @enable: True to enable event generation; false to disable |
1770 | * | |
1771 | * This enables the device as a wakeup event source, or disables it. | |
1772 | * When such events involves platform-specific hooks, those hooks are | |
1773 | * called automatically by this routine. | |
1774 | * | |
1775 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1776 | * always require such platform hooks. |
075c1771 | 1777 | * |
eb9d0fe4 RW |
1778 | * RETURN VALUE: |
1779 | * 0 is returned on success | |
1780 | * -EINVAL is returned if device is not supposed to wake up the system | |
1781 | * Error code depending on the platform is returned if both the platform and | |
1782 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1783 | */ |
6cbf8214 RW |
1784 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1785 | bool runtime, bool enable) | |
1da177e4 | 1786 | { |
5bcc2fb4 | 1787 | int ret = 0; |
075c1771 | 1788 | |
6cbf8214 | 1789 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1790 | return -EINVAL; |
1da177e4 | 1791 | |
e80bb09d RW |
1792 | /* Don't do the same thing twice in a row for one device. */ |
1793 | if (!!enable == !!dev->wakeup_prepared) | |
1794 | return 0; | |
1795 | ||
eb9d0fe4 RW |
1796 | /* |
1797 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1798 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1799 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1800 | */ |
1da177e4 | 1801 | |
5bcc2fb4 RW |
1802 | if (enable) { |
1803 | int error; | |
1da177e4 | 1804 | |
5bcc2fb4 RW |
1805 | if (pci_pme_capable(dev, state)) |
1806 | pci_pme_active(dev, true); | |
1807 | else | |
1808 | ret = 1; | |
6cbf8214 RW |
1809 | error = runtime ? platform_pci_run_wake(dev, true) : |
1810 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1811 | if (ret) |
1812 | ret = error; | |
e80bb09d RW |
1813 | if (!ret) |
1814 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1815 | } else { |
6cbf8214 RW |
1816 | if (runtime) |
1817 | platform_pci_run_wake(dev, false); | |
1818 | else | |
1819 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1820 | pci_pme_active(dev, false); |
e80bb09d | 1821 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1822 | } |
1da177e4 | 1823 | |
5bcc2fb4 | 1824 | return ret; |
eb9d0fe4 | 1825 | } |
6cbf8214 | 1826 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1827 | |
0235c4fc RW |
1828 | /** |
1829 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1830 | * @dev: PCI device to prepare | |
1831 | * @enable: True to enable wake-up event generation; false to disable | |
1832 | * | |
1833 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1834 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1835 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1836 | * ordering constraints. | |
1837 | * | |
1838 | * This function only returns error code if the device is not capable of | |
1839 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1840 | * enable wake-up power for it. | |
1841 | */ | |
1842 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1843 | { | |
1844 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1845 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1846 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1847 | } | |
b7fe9434 | 1848 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 1849 | |
404cc2d8 | 1850 | /** |
37139074 JB |
1851 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1852 | * @dev: PCI device | |
1853 | * | |
1854 | * Use underlying platform code to find a supported low power state for @dev. | |
1855 | * If the platform can't manage @dev, return the deepest state from which it | |
1856 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1857 | */ |
0b950f0f | 1858 | static pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1859 | { |
1860 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1861 | |
1862 | if (platform_pci_power_manageable(dev)) { | |
1863 | /* | |
1864 | * Call the platform to choose the target state of the device | |
1865 | * and enable wake-up from this state if supported. | |
1866 | */ | |
1867 | pci_power_t state = platform_pci_choose_state(dev); | |
1868 | ||
1869 | switch (state) { | |
1870 | case PCI_POWER_ERROR: | |
1871 | case PCI_UNKNOWN: | |
1872 | break; | |
1873 | case PCI_D1: | |
1874 | case PCI_D2: | |
1875 | if (pci_no_d1d2(dev)) | |
1876 | break; | |
1877 | default: | |
1878 | target_state = state; | |
404cc2d8 | 1879 | } |
d2abdf62 RW |
1880 | } else if (!dev->pm_cap) { |
1881 | target_state = PCI_D0; | |
404cc2d8 RW |
1882 | } else if (device_may_wakeup(&dev->dev)) { |
1883 | /* | |
1884 | * Find the deepest state from which the device can generate | |
1885 | * wake-up events, make it the target state and enable device | |
1886 | * to generate PME#. | |
1887 | */ | |
337001b6 RW |
1888 | if (dev->pme_support) { |
1889 | while (target_state | |
1890 | && !(dev->pme_support & (1 << target_state))) | |
1891 | target_state--; | |
404cc2d8 RW |
1892 | } |
1893 | } | |
1894 | ||
e5899e1b RW |
1895 | return target_state; |
1896 | } | |
1897 | ||
1898 | /** | |
1899 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1900 | * @dev: Device to handle. | |
1901 | * | |
1902 | * Choose the power state appropriate for the device depending on whether | |
1903 | * it can wake up the system and/or is power manageable by the platform | |
1904 | * (PCI_D3hot is the default) and put the device into that state. | |
1905 | */ | |
1906 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1907 | { | |
1908 | pci_power_t target_state = pci_target_state(dev); | |
1909 | int error; | |
1910 | ||
1911 | if (target_state == PCI_POWER_ERROR) | |
1912 | return -EIO; | |
1913 | ||
8efb8c76 | 1914 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1915 | |
404cc2d8 RW |
1916 | error = pci_set_power_state(dev, target_state); |
1917 | ||
1918 | if (error) | |
1919 | pci_enable_wake(dev, target_state, false); | |
1920 | ||
1921 | return error; | |
1922 | } | |
b7fe9434 | 1923 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
1924 | |
1925 | /** | |
443bd1c4 | 1926 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1927 | * @dev: Device to handle. |
1928 | * | |
88393161 | 1929 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
1930 | */ |
1931 | int pci_back_from_sleep(struct pci_dev *dev) | |
1932 | { | |
1933 | pci_enable_wake(dev, PCI_D0, false); | |
1934 | return pci_set_power_state(dev, PCI_D0); | |
1935 | } | |
b7fe9434 | 1936 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 1937 | |
6cbf8214 RW |
1938 | /** |
1939 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
1940 | * @dev: PCI device being suspended. | |
1941 | * | |
1942 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
1943 | * power state. | |
1944 | */ | |
1945 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
1946 | { | |
1947 | pci_power_t target_state = pci_target_state(dev); | |
1948 | int error; | |
1949 | ||
1950 | if (target_state == PCI_POWER_ERROR) | |
1951 | return -EIO; | |
1952 | ||
448bd857 HY |
1953 | dev->runtime_d3cold = target_state == PCI_D3cold; |
1954 | ||
6cbf8214 RW |
1955 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
1956 | ||
1957 | error = pci_set_power_state(dev, target_state); | |
1958 | ||
448bd857 | 1959 | if (error) { |
6cbf8214 | 1960 | __pci_enable_wake(dev, target_state, true, false); |
448bd857 HY |
1961 | dev->runtime_d3cold = false; |
1962 | } | |
6cbf8214 RW |
1963 | |
1964 | return error; | |
1965 | } | |
1966 | ||
b67ea761 RW |
1967 | /** |
1968 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
1969 | * @dev: Device to check. | |
1970 | * | |
f7625980 | 1971 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
1972 | * (through the platform or using the native PCIe PME) or if the device supports |
1973 | * PME and one of its upstream bridges can generate wake-up events. | |
1974 | */ | |
1975 | bool pci_dev_run_wake(struct pci_dev *dev) | |
1976 | { | |
1977 | struct pci_bus *bus = dev->bus; | |
1978 | ||
1979 | if (device_run_wake(&dev->dev)) | |
1980 | return true; | |
1981 | ||
1982 | if (!dev->pme_support) | |
1983 | return false; | |
1984 | ||
1985 | while (bus->parent) { | |
1986 | struct pci_dev *bridge = bus->self; | |
1987 | ||
1988 | if (device_run_wake(&bridge->dev)) | |
1989 | return true; | |
1990 | ||
1991 | bus = bus->parent; | |
1992 | } | |
1993 | ||
1994 | /* We have reached the root bus. */ | |
1995 | if (bus->bridge) | |
1996 | return device_run_wake(bus->bridge); | |
1997 | ||
1998 | return false; | |
1999 | } | |
2000 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2001 | ||
b3c32c4f HY |
2002 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2003 | { | |
2004 | struct device *dev = &pdev->dev; | |
2005 | struct device *parent = dev->parent; | |
2006 | ||
2007 | if (parent) | |
2008 | pm_runtime_get_sync(parent); | |
2009 | pm_runtime_get_noresume(dev); | |
2010 | /* | |
2011 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2012 | * so wait until suspending completes | |
2013 | */ | |
2014 | pm_runtime_barrier(dev); | |
2015 | /* | |
2016 | * Only need to resume devices in D3cold, because config | |
2017 | * registers are still accessible for devices suspended but | |
2018 | * not in D3cold. | |
2019 | */ | |
2020 | if (pdev->current_state == PCI_D3cold) | |
2021 | pm_runtime_resume(dev); | |
2022 | } | |
2023 | ||
2024 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2025 | { | |
2026 | struct device *dev = &pdev->dev; | |
2027 | struct device *parent = dev->parent; | |
2028 | ||
2029 | pm_runtime_put(dev); | |
2030 | if (parent) | |
2031 | pm_runtime_put_sync(parent); | |
2032 | } | |
2033 | ||
eb9d0fe4 RW |
2034 | /** |
2035 | * pci_pm_init - Initialize PM functions of given PCI device | |
2036 | * @dev: PCI device to handle. | |
2037 | */ | |
2038 | void pci_pm_init(struct pci_dev *dev) | |
2039 | { | |
2040 | int pm; | |
2041 | u16 pmc; | |
1da177e4 | 2042 | |
bb910a70 | 2043 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2044 | pm_runtime_set_active(&dev->dev); |
2045 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2046 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2047 | dev->wakeup_prepared = false; |
bb910a70 | 2048 | |
337001b6 | 2049 | dev->pm_cap = 0; |
ffaddbe8 | 2050 | dev->pme_support = 0; |
337001b6 | 2051 | |
eb9d0fe4 RW |
2052 | /* find PCI PM capability in list */ |
2053 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2054 | if (!pm) | |
50246dd4 | 2055 | return; |
eb9d0fe4 RW |
2056 | /* Check device's ability to generate PME# */ |
2057 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2058 | |
eb9d0fe4 RW |
2059 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
2060 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
2061 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 2062 | return; |
eb9d0fe4 RW |
2063 | } |
2064 | ||
337001b6 | 2065 | dev->pm_cap = pm; |
1ae861e6 | 2066 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2067 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
4f9c1397 | 2068 | dev->d3cold_allowed = true; |
337001b6 RW |
2069 | |
2070 | dev->d1_support = false; | |
2071 | dev->d2_support = false; | |
2072 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2073 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2074 | dev->d1_support = true; |
c9ed77ee | 2075 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2076 | dev->d2_support = true; |
c9ed77ee BH |
2077 | |
2078 | if (dev->d1_support || dev->d2_support) | |
2079 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
2080 | dev->d1_support ? " D1" : "", |
2081 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2082 | } |
2083 | ||
2084 | pmc &= PCI_PM_CAP_PME_MASK; | |
2085 | if (pmc) { | |
10c3d71d BH |
2086 | dev_printk(KERN_DEBUG, &dev->dev, |
2087 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
2088 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2089 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2090 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2091 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2092 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2093 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2094 | dev->pme_poll = true; |
eb9d0fe4 RW |
2095 | /* |
2096 | * Make device's PM flags reflect the wake-up capability, but | |
2097 | * let the user space enable it to wake up the system as needed. | |
2098 | */ | |
2099 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2100 | /* Disable the PME# generation functionality */ |
337001b6 | 2101 | pci_pme_active(dev, false); |
eb9d0fe4 | 2102 | } |
1da177e4 LT |
2103 | } |
2104 | ||
34a4876e YL |
2105 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
2106 | struct pci_cap_saved_state *new_cap) | |
2107 | { | |
2108 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
2109 | } | |
2110 | ||
63f4898a | 2111 | /** |
fd0f7f73 AW |
2112 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
2113 | * capability registers | |
63f4898a RW |
2114 | * @dev: the PCI device |
2115 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 2116 | * @extended: Standard or Extended capability ID |
63f4898a RW |
2117 | * @size: requested size of the buffer |
2118 | */ | |
fd0f7f73 AW |
2119 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
2120 | bool extended, unsigned int size) | |
63f4898a RW |
2121 | { |
2122 | int pos; | |
2123 | struct pci_cap_saved_state *save_state; | |
2124 | ||
fd0f7f73 AW |
2125 | if (extended) |
2126 | pos = pci_find_ext_capability(dev, cap); | |
2127 | else | |
2128 | pos = pci_find_capability(dev, cap); | |
2129 | ||
63f4898a RW |
2130 | if (pos <= 0) |
2131 | return 0; | |
2132 | ||
2133 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2134 | if (!save_state) | |
2135 | return -ENOMEM; | |
2136 | ||
24a4742f | 2137 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 2138 | save_state->cap.cap_extended = extended; |
24a4742f | 2139 | save_state->cap.size = size; |
63f4898a RW |
2140 | pci_add_saved_cap(dev, save_state); |
2141 | ||
2142 | return 0; | |
2143 | } | |
2144 | ||
fd0f7f73 AW |
2145 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
2146 | { | |
2147 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
2148 | } | |
2149 | ||
2150 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
2151 | { | |
2152 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
2153 | } | |
2154 | ||
63f4898a RW |
2155 | /** |
2156 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2157 | * @dev: the PCI device | |
2158 | */ | |
2159 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2160 | { | |
2161 | int error; | |
2162 | ||
89858517 YZ |
2163 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2164 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2165 | if (error) |
2166 | dev_err(&dev->dev, | |
2167 | "unable to preallocate PCI Express save buffer\n"); | |
2168 | ||
2169 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2170 | if (error) | |
2171 | dev_err(&dev->dev, | |
2172 | "unable to preallocate PCI-X save buffer\n"); | |
425c1b22 AW |
2173 | |
2174 | pci_allocate_vc_save_buffers(dev); | |
63f4898a RW |
2175 | } |
2176 | ||
f796841e YL |
2177 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2178 | { | |
2179 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 2180 | struct hlist_node *n; |
f796841e | 2181 | |
b67bfe0d | 2182 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
2183 | kfree(tmp); |
2184 | } | |
2185 | ||
58c3a727 | 2186 | /** |
31ab2476 | 2187 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 2188 | * @dev: the PCI device |
b0cc6020 YW |
2189 | * |
2190 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
2191 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 2192 | */ |
31ab2476 | 2193 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 2194 | { |
58c3a727 | 2195 | u32 cap; |
8113587c | 2196 | struct pci_dev *bridge; |
58c3a727 | 2197 | |
6748dcc2 | 2198 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2199 | return; |
2200 | ||
8113587c | 2201 | bridge = dev->bus->self; |
cb97ae34 | 2202 | if (!bridge) |
8113587c ZY |
2203 | return; |
2204 | ||
59875ae4 | 2205 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2206 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2207 | return; | |
2208 | ||
b0cc6020 YW |
2209 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
2210 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
2211 | PCI_EXP_DEVCTL2_ARI); | |
2212 | bridge->ari_enabled = 1; | |
2213 | } else { | |
2214 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
2215 | PCI_EXP_DEVCTL2_ARI); | |
2216 | bridge->ari_enabled = 0; | |
2217 | } | |
58c3a727 YZ |
2218 | } |
2219 | ||
5d990b62 CW |
2220 | static int pci_acs_enable; |
2221 | ||
2222 | /** | |
2223 | * pci_request_acs - ask for ACS to be enabled if supported | |
2224 | */ | |
2225 | void pci_request_acs(void) | |
2226 | { | |
2227 | pci_acs_enable = 1; | |
2228 | } | |
2229 | ||
ae21ee65 | 2230 | /** |
2c744244 | 2231 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites |
ae21ee65 AK |
2232 | * @dev: the PCI device |
2233 | */ | |
2c744244 | 2234 | static int pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
2235 | { |
2236 | int pos; | |
2237 | u16 cap; | |
2238 | u16 ctrl; | |
2239 | ||
ae21ee65 AK |
2240 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2241 | if (!pos) | |
2c744244 | 2242 | return -ENODEV; |
ae21ee65 AK |
2243 | |
2244 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2245 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2246 | ||
2247 | /* Source Validation */ | |
2248 | ctrl |= (cap & PCI_ACS_SV); | |
2249 | ||
2250 | /* P2P Request Redirect */ | |
2251 | ctrl |= (cap & PCI_ACS_RR); | |
2252 | ||
2253 | /* P2P Completion Redirect */ | |
2254 | ctrl |= (cap & PCI_ACS_CR); | |
2255 | ||
2256 | /* Upstream Forwarding */ | |
2257 | ctrl |= (cap & PCI_ACS_UF); | |
2258 | ||
2259 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
2260 | |
2261 | return 0; | |
2262 | } | |
2263 | ||
2264 | /** | |
2265 | * pci_enable_acs - enable ACS if hardware support it | |
2266 | * @dev: the PCI device | |
2267 | */ | |
2268 | void pci_enable_acs(struct pci_dev *dev) | |
2269 | { | |
2270 | if (!pci_acs_enable) | |
2271 | return; | |
2272 | ||
2273 | if (!pci_std_enable_acs(dev)) | |
2274 | return; | |
2275 | ||
2276 | pci_dev_specific_enable_acs(dev); | |
ae21ee65 AK |
2277 | } |
2278 | ||
0a67119f AW |
2279 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
2280 | { | |
2281 | int pos; | |
83db7e0b | 2282 | u16 cap, ctrl; |
0a67119f AW |
2283 | |
2284 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2285 | if (!pos) | |
2286 | return false; | |
2287 | ||
83db7e0b AW |
2288 | /* |
2289 | * Except for egress control, capabilities are either required | |
2290 | * or only required if controllable. Features missing from the | |
2291 | * capability field can therefore be assumed as hard-wired enabled. | |
2292 | */ | |
2293 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
2294 | acs_flags &= (cap | PCI_ACS_EC); | |
2295 | ||
0a67119f AW |
2296 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
2297 | return (ctrl & acs_flags) == acs_flags; | |
2298 | } | |
2299 | ||
ad805758 AW |
2300 | /** |
2301 | * pci_acs_enabled - test ACS against required flags for a given device | |
2302 | * @pdev: device to test | |
2303 | * @acs_flags: required PCI ACS flags | |
2304 | * | |
2305 | * Return true if the device supports the provided flags. Automatically | |
2306 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
2307 | * |
2308 | * Note that this interface checks the effective ACS capabilities of the | |
2309 | * device rather than the actual capabilities. For instance, most single | |
2310 | * function endpoints are not required to support ACS because they have no | |
2311 | * opportunity for peer-to-peer access. We therefore return 'true' | |
2312 | * regardless of whether the device exposes an ACS capability. This makes | |
2313 | * it much easier for callers of this function to ignore the actual type | |
2314 | * or topology of the device when testing ACS support. | |
ad805758 AW |
2315 | */ |
2316 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2317 | { | |
0a67119f | 2318 | int ret; |
ad805758 AW |
2319 | |
2320 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2321 | if (ret >= 0) | |
2322 | return ret > 0; | |
2323 | ||
0a67119f AW |
2324 | /* |
2325 | * Conventional PCI and PCI-X devices never support ACS, either | |
2326 | * effectively or actually. The shared bus topology implies that | |
2327 | * any device on the bus can receive or snoop DMA. | |
2328 | */ | |
ad805758 AW |
2329 | if (!pci_is_pcie(pdev)) |
2330 | return false; | |
2331 | ||
0a67119f AW |
2332 | switch (pci_pcie_type(pdev)) { |
2333 | /* | |
2334 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 2335 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
2336 | * handle them as we would a non-PCIe device. |
2337 | */ | |
2338 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
2339 | /* | |
2340 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
2341 | * applicable... must never implement an ACS Extended Capability...". | |
2342 | * This seems arbitrary, but we take a conservative interpretation | |
2343 | * of this statement. | |
2344 | */ | |
2345 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
2346 | case PCI_EXP_TYPE_RC_EC: | |
2347 | return false; | |
2348 | /* | |
2349 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
2350 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
2351 | * regardless of whether they are single- or multi-function devices. | |
2352 | */ | |
2353 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2354 | case PCI_EXP_TYPE_ROOT_PORT: | |
2355 | return pci_acs_flags_enabled(pdev, acs_flags); | |
2356 | /* | |
2357 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
2358 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 2359 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
2360 | * device. The footnote for section 6.12 indicates the specific |
2361 | * PCIe types included here. | |
2362 | */ | |
2363 | case PCI_EXP_TYPE_ENDPOINT: | |
2364 | case PCI_EXP_TYPE_UPSTREAM: | |
2365 | case PCI_EXP_TYPE_LEG_END: | |
2366 | case PCI_EXP_TYPE_RC_END: | |
2367 | if (!pdev->multifunction) | |
2368 | break; | |
2369 | ||
0a67119f | 2370 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
2371 | } |
2372 | ||
0a67119f | 2373 | /* |
f7625980 | 2374 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
2375 | * to single function devices with the exception of downstream ports. |
2376 | */ | |
ad805758 AW |
2377 | return true; |
2378 | } | |
2379 | ||
2380 | /** | |
2381 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2382 | * @start: starting downstream device | |
2383 | * @end: ending upstream device or NULL to search to the root bus | |
2384 | * @acs_flags: required flags | |
2385 | * | |
2386 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2387 | * any step along the way does not support the required flags, return false. | |
2388 | */ | |
2389 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2390 | struct pci_dev *end, u16 acs_flags) | |
2391 | { | |
2392 | struct pci_dev *pdev, *parent = start; | |
2393 | ||
2394 | do { | |
2395 | pdev = parent; | |
2396 | ||
2397 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2398 | return false; | |
2399 | ||
2400 | if (pci_is_root_bus(pdev->bus)) | |
2401 | return (end == NULL); | |
2402 | ||
2403 | parent = pdev->bus->self; | |
2404 | } while (pdev != end); | |
2405 | ||
2406 | return true; | |
2407 | } | |
2408 | ||
57c2cf71 BH |
2409 | /** |
2410 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
2411 | * @dev: the PCI device | |
bb5c2de2 | 2412 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
2413 | * |
2414 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
2415 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
2416 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
2417 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
2418 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 2419 | */ |
3df425f3 | 2420 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 2421 | { |
46b952a3 MW |
2422 | int slot; |
2423 | ||
2424 | if (pci_ari_enabled(dev->bus)) | |
2425 | slot = 0; | |
2426 | else | |
2427 | slot = PCI_SLOT(dev->devfn); | |
2428 | ||
2429 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
2430 | } |
2431 | ||
3c78bc61 | 2432 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
2433 | { |
2434 | u8 pin; | |
2435 | ||
514d207d | 2436 | pin = dev->pin; |
1da177e4 LT |
2437 | if (!pin) |
2438 | return -1; | |
878f2e50 | 2439 | |
8784fd4d | 2440 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 2441 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
2442 | dev = dev->bus->self; |
2443 | } | |
2444 | *bridge = dev; | |
2445 | return pin; | |
2446 | } | |
2447 | ||
68feac87 BH |
2448 | /** |
2449 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
2450 | * @dev: the PCI device | |
2451 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2452 | * | |
2453 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
2454 | * bridges all the way up to a PCI root bus. | |
2455 | */ | |
2456 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
2457 | { | |
2458 | u8 pin = *pinp; | |
2459 | ||
1eb39487 | 2460 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
2461 | pin = pci_swizzle_interrupt_pin(dev, pin); |
2462 | dev = dev->bus->self; | |
2463 | } | |
2464 | *pinp = pin; | |
2465 | return PCI_SLOT(dev->devfn); | |
2466 | } | |
2467 | ||
1da177e4 LT |
2468 | /** |
2469 | * pci_release_region - Release a PCI bar | |
2470 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
2471 | * @bar: BAR to release | |
2472 | * | |
2473 | * Releases the PCI I/O and memory resources previously reserved by a | |
2474 | * successful call to pci_request_region. Call this function only | |
2475 | * after all use of the PCI regions has ceased. | |
2476 | */ | |
2477 | void pci_release_region(struct pci_dev *pdev, int bar) | |
2478 | { | |
9ac7849e TH |
2479 | struct pci_devres *dr; |
2480 | ||
1da177e4 LT |
2481 | if (pci_resource_len(pdev, bar) == 0) |
2482 | return; | |
2483 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
2484 | release_region(pci_resource_start(pdev, bar), | |
2485 | pci_resource_len(pdev, bar)); | |
2486 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
2487 | release_mem_region(pci_resource_start(pdev, bar), | |
2488 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
2489 | |
2490 | dr = find_pci_dr(pdev); | |
2491 | if (dr) | |
2492 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 2493 | } |
b7fe9434 | 2494 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
2495 | |
2496 | /** | |
f5ddcac4 | 2497 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
2498 | * @pdev: PCI device whose resources are to be reserved |
2499 | * @bar: BAR to be reserved | |
2500 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 2501 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
2502 | * |
2503 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2504 | * being reserved by owner @res_name. Do not access any | |
2505 | * address inside the PCI regions unless this call returns | |
2506 | * successfully. | |
2507 | * | |
f5ddcac4 RD |
2508 | * If @exclusive is set, then the region is marked so that userspace |
2509 | * is explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 2510 | * sysfs MMIO access. |
f5ddcac4 | 2511 | * |
1da177e4 LT |
2512 | * Returns 0 on success, or %EBUSY on error. A warning |
2513 | * message is also printed on failure. | |
2514 | */ | |
3c78bc61 RD |
2515 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
2516 | const char *res_name, int exclusive) | |
1da177e4 | 2517 | { |
9ac7849e TH |
2518 | struct pci_devres *dr; |
2519 | ||
1da177e4 LT |
2520 | if (pci_resource_len(pdev, bar) == 0) |
2521 | return 0; | |
f7625980 | 2522 | |
1da177e4 LT |
2523 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
2524 | if (!request_region(pci_resource_start(pdev, bar), | |
2525 | pci_resource_len(pdev, bar), res_name)) | |
2526 | goto err_out; | |
3c78bc61 | 2527 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
2528 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
2529 | pci_resource_len(pdev, bar), res_name, | |
2530 | exclusive)) | |
1da177e4 LT |
2531 | goto err_out; |
2532 | } | |
9ac7849e TH |
2533 | |
2534 | dr = find_pci_dr(pdev); | |
2535 | if (dr) | |
2536 | dr->region_mask |= 1 << bar; | |
2537 | ||
1da177e4 LT |
2538 | return 0; |
2539 | ||
2540 | err_out: | |
c7dabef8 | 2541 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 2542 | &pdev->resource[bar]); |
1da177e4 LT |
2543 | return -EBUSY; |
2544 | } | |
2545 | ||
e8de1481 | 2546 | /** |
f5ddcac4 | 2547 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
2548 | * @pdev: PCI device whose resources are to be reserved |
2549 | * @bar: BAR to be reserved | |
f5ddcac4 | 2550 | * @res_name: Name to be associated with resource |
e8de1481 | 2551 | * |
f5ddcac4 | 2552 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
2553 | * being reserved by owner @res_name. Do not access any |
2554 | * address inside the PCI regions unless this call returns | |
2555 | * successfully. | |
2556 | * | |
2557 | * Returns 0 on success, or %EBUSY on error. A warning | |
2558 | * message is also printed on failure. | |
2559 | */ | |
2560 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
2561 | { | |
2562 | return __pci_request_region(pdev, bar, res_name, 0); | |
2563 | } | |
b7fe9434 | 2564 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 AV |
2565 | |
2566 | /** | |
2567 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
2568 | * @pdev: PCI device whose resources are to be reserved | |
2569 | * @bar: BAR to be reserved | |
2570 | * @res_name: Name to be associated with resource. | |
2571 | * | |
2572 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2573 | * being reserved by owner @res_name. Do not access any | |
2574 | * address inside the PCI regions unless this call returns | |
2575 | * successfully. | |
2576 | * | |
2577 | * Returns 0 on success, or %EBUSY on error. A warning | |
2578 | * message is also printed on failure. | |
2579 | * | |
2580 | * The key difference that _exclusive makes it that userspace is | |
2581 | * explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 2582 | * sysfs. |
e8de1481 | 2583 | */ |
3c78bc61 RD |
2584 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, |
2585 | const char *res_name) | |
e8de1481 AV |
2586 | { |
2587 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
2588 | } | |
b7fe9434 RD |
2589 | EXPORT_SYMBOL(pci_request_region_exclusive); |
2590 | ||
c87deff7 HS |
2591 | /** |
2592 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
2593 | * @pdev: PCI device whose resources were previously reserved | |
2594 | * @bars: Bitmask of BARs to be released | |
2595 | * | |
2596 | * Release selected PCI I/O and memory resources previously reserved. | |
2597 | * Call this function only after all use of the PCI regions has ceased. | |
2598 | */ | |
2599 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
2600 | { | |
2601 | int i; | |
2602 | ||
2603 | for (i = 0; i < 6; i++) | |
2604 | if (bars & (1 << i)) | |
2605 | pci_release_region(pdev, i); | |
2606 | } | |
b7fe9434 | 2607 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 2608 | |
9738abed | 2609 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 2610 | const char *res_name, int excl) |
c87deff7 HS |
2611 | { |
2612 | int i; | |
2613 | ||
2614 | for (i = 0; i < 6; i++) | |
2615 | if (bars & (1 << i)) | |
e8de1481 | 2616 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
2617 | goto err_out; |
2618 | return 0; | |
2619 | ||
2620 | err_out: | |
3c78bc61 | 2621 | while (--i >= 0) |
c87deff7 HS |
2622 | if (bars & (1 << i)) |
2623 | pci_release_region(pdev, i); | |
2624 | ||
2625 | return -EBUSY; | |
2626 | } | |
1da177e4 | 2627 | |
e8de1481 AV |
2628 | |
2629 | /** | |
2630 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
2631 | * @pdev: PCI device whose resources are to be reserved | |
2632 | * @bars: Bitmask of BARs to be requested | |
2633 | * @res_name: Name to be associated with resource | |
2634 | */ | |
2635 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
2636 | const char *res_name) | |
2637 | { | |
2638 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
2639 | } | |
b7fe9434 | 2640 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 2641 | |
3c78bc61 RD |
2642 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
2643 | const char *res_name) | |
e8de1481 AV |
2644 | { |
2645 | return __pci_request_selected_regions(pdev, bars, res_name, | |
2646 | IORESOURCE_EXCLUSIVE); | |
2647 | } | |
b7fe9434 | 2648 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 2649 | |
1da177e4 LT |
2650 | /** |
2651 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
2652 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
2653 | * | |
2654 | * Releases all PCI I/O and memory resources previously reserved by a | |
2655 | * successful call to pci_request_regions. Call this function only | |
2656 | * after all use of the PCI regions has ceased. | |
2657 | */ | |
2658 | ||
2659 | void pci_release_regions(struct pci_dev *pdev) | |
2660 | { | |
c87deff7 | 2661 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 | 2662 | } |
b7fe9434 | 2663 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
2664 | |
2665 | /** | |
2666 | * pci_request_regions - Reserved PCI I/O and memory resources | |
2667 | * @pdev: PCI device whose resources are to be reserved | |
2668 | * @res_name: Name to be associated with resource. | |
2669 | * | |
2670 | * Mark all PCI regions associated with PCI device @pdev as | |
2671 | * being reserved by owner @res_name. Do not access any | |
2672 | * address inside the PCI regions unless this call returns | |
2673 | * successfully. | |
2674 | * | |
2675 | * Returns 0 on success, or %EBUSY on error. A warning | |
2676 | * message is also printed on failure. | |
2677 | */ | |
3c990e92 | 2678 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 2679 | { |
c87deff7 | 2680 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 | 2681 | } |
b7fe9434 | 2682 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 2683 | |
e8de1481 AV |
2684 | /** |
2685 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
2686 | * @pdev: PCI device whose resources are to be reserved | |
2687 | * @res_name: Name to be associated with resource. | |
2688 | * | |
2689 | * Mark all PCI regions associated with PCI device @pdev as | |
2690 | * being reserved by owner @res_name. Do not access any | |
2691 | * address inside the PCI regions unless this call returns | |
2692 | * successfully. | |
2693 | * | |
2694 | * pci_request_regions_exclusive() will mark the region so that | |
f7625980 | 2695 | * /dev/mem and the sysfs MMIO access will not be allowed. |
e8de1481 AV |
2696 | * |
2697 | * Returns 0 on success, or %EBUSY on error. A warning | |
2698 | * message is also printed on failure. | |
2699 | */ | |
2700 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
2701 | { | |
2702 | return pci_request_selected_regions_exclusive(pdev, | |
2703 | ((1 << 6) - 1), res_name); | |
2704 | } | |
b7fe9434 | 2705 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 2706 | |
8b921acf LD |
2707 | /** |
2708 | * pci_remap_iospace - Remap the memory mapped I/O space | |
2709 | * @res: Resource describing the I/O space | |
2710 | * @phys_addr: physical address of range to be mapped | |
2711 | * | |
2712 | * Remap the memory mapped I/O space described by the @res | |
2713 | * and the CPU physical address @phys_addr into virtual address space. | |
2714 | * Only architectures that have memory mapped IO functions defined | |
2715 | * (and the PCI_IOBASE value defined) should call this function. | |
2716 | */ | |
2717 | int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) | |
2718 | { | |
2719 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
2720 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
2721 | ||
2722 | if (!(res->flags & IORESOURCE_IO)) | |
2723 | return -EINVAL; | |
2724 | ||
2725 | if (res->end > IO_SPACE_LIMIT) | |
2726 | return -EINVAL; | |
2727 | ||
2728 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
2729 | pgprot_device(PAGE_KERNEL)); | |
2730 | #else | |
2731 | /* this architecture does not have memory mapped I/O space, | |
2732 | so this function should never be called */ | |
2733 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); | |
2734 | return -ENODEV; | |
2735 | #endif | |
2736 | } | |
2737 | ||
6a479079 BH |
2738 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
2739 | { | |
2740 | u16 old_cmd, cmd; | |
2741 | ||
2742 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
2743 | if (enable) | |
2744 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
2745 | else | |
2746 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
2747 | if (cmd != old_cmd) { | |
2748 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
2749 | enable ? "enabling" : "disabling"); | |
2750 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2751 | } | |
2752 | dev->is_busmaster = enable; | |
2753 | } | |
e8de1481 | 2754 | |
2b6f2c35 MS |
2755 | /** |
2756 | * pcibios_setup - process "pci=" kernel boot arguments | |
2757 | * @str: string used to pass in "pci=" kernel boot arguments | |
2758 | * | |
2759 | * Process kernel boot arguments. This is the default implementation. | |
2760 | * Architecture specific implementations can override this as necessary. | |
2761 | */ | |
2762 | char * __weak __init pcibios_setup(char *str) | |
2763 | { | |
2764 | return str; | |
2765 | } | |
2766 | ||
96c55900 MS |
2767 | /** |
2768 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
2769 | * @dev: the PCI device to enable | |
2770 | * | |
2771 | * Enables PCI bus-mastering for the device. This is the default | |
2772 | * implementation. Architecture specific implementations can override | |
2773 | * this if necessary. | |
2774 | */ | |
2775 | void __weak pcibios_set_master(struct pci_dev *dev) | |
2776 | { | |
2777 | u8 lat; | |
2778 | ||
f676678f MS |
2779 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
2780 | if (pci_is_pcie(dev)) | |
2781 | return; | |
2782 | ||
96c55900 MS |
2783 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
2784 | if (lat < 16) | |
2785 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
2786 | else if (lat > pcibios_max_latency) | |
2787 | lat = pcibios_max_latency; | |
2788 | else | |
2789 | return; | |
a006482b | 2790 | |
96c55900 MS |
2791 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
2792 | } | |
2793 | ||
1da177e4 LT |
2794 | /** |
2795 | * pci_set_master - enables bus-mastering for device dev | |
2796 | * @dev: the PCI device to enable | |
2797 | * | |
2798 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
2799 | * to do the needed arch specific settings. | |
2800 | */ | |
6a479079 | 2801 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 2802 | { |
6a479079 | 2803 | __pci_set_master(dev, true); |
1da177e4 LT |
2804 | pcibios_set_master(dev); |
2805 | } | |
b7fe9434 | 2806 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 2807 | |
6a479079 BH |
2808 | /** |
2809 | * pci_clear_master - disables bus-mastering for device dev | |
2810 | * @dev: the PCI device to disable | |
2811 | */ | |
2812 | void pci_clear_master(struct pci_dev *dev) | |
2813 | { | |
2814 | __pci_set_master(dev, false); | |
2815 | } | |
b7fe9434 | 2816 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 2817 | |
1da177e4 | 2818 | /** |
edb2d97e MW |
2819 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
2820 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 2821 | * |
edb2d97e MW |
2822 | * Helper function for pci_set_mwi. |
2823 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
2824 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
2825 | * | |
2826 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2827 | */ | |
15ea76d4 | 2828 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
2829 | { |
2830 | u8 cacheline_size; | |
2831 | ||
2832 | if (!pci_cache_line_size) | |
15ea76d4 | 2833 | return -EINVAL; |
1da177e4 LT |
2834 | |
2835 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
2836 | equal to or multiple of the right value. */ | |
2837 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2838 | if (cacheline_size >= pci_cache_line_size && | |
2839 | (cacheline_size % pci_cache_line_size) == 0) | |
2840 | return 0; | |
2841 | ||
2842 | /* Write the correct value. */ | |
2843 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
2844 | /* Read it back. */ | |
2845 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2846 | if (cacheline_size == pci_cache_line_size) | |
2847 | return 0; | |
2848 | ||
227f0647 RD |
2849 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", |
2850 | pci_cache_line_size << 2); | |
1da177e4 LT |
2851 | |
2852 | return -EINVAL; | |
2853 | } | |
15ea76d4 TH |
2854 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
2855 | ||
1da177e4 LT |
2856 | /** |
2857 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
2858 | * @dev: the PCI device for which MWI is enabled | |
2859 | * | |
694625c0 | 2860 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
2861 | * |
2862 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2863 | */ | |
3c78bc61 | 2864 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 2865 | { |
b7fe9434 RD |
2866 | #ifdef PCI_DISABLE_MWI |
2867 | return 0; | |
2868 | #else | |
1da177e4 LT |
2869 | int rc; |
2870 | u16 cmd; | |
2871 | ||
edb2d97e | 2872 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
2873 | if (rc) |
2874 | return rc; | |
2875 | ||
2876 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 2877 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
80ccba11 | 2878 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
2879 | cmd |= PCI_COMMAND_INVALIDATE; |
2880 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2881 | } | |
1da177e4 | 2882 | return 0; |
b7fe9434 | 2883 | #endif |
1da177e4 | 2884 | } |
b7fe9434 | 2885 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 2886 | |
694625c0 RD |
2887 | /** |
2888 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
2889 | * @dev: the PCI device for which MWI is enabled | |
2890 | * | |
2891 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
2892 | * Callers are not required to check the return value. | |
2893 | * | |
2894 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2895 | */ | |
2896 | int pci_try_set_mwi(struct pci_dev *dev) | |
2897 | { | |
b7fe9434 RD |
2898 | #ifdef PCI_DISABLE_MWI |
2899 | return 0; | |
2900 | #else | |
2901 | return pci_set_mwi(dev); | |
2902 | #endif | |
694625c0 | 2903 | } |
b7fe9434 | 2904 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 2905 | |
1da177e4 LT |
2906 | /** |
2907 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
2908 | * @dev: the PCI device to disable | |
2909 | * | |
2910 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
2911 | */ | |
3c78bc61 | 2912 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 2913 | { |
b7fe9434 | 2914 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
2915 | u16 cmd; |
2916 | ||
2917 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2918 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
2919 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
2920 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2921 | } | |
b7fe9434 | 2922 | #endif |
1da177e4 | 2923 | } |
b7fe9434 | 2924 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 2925 | |
a04ce0ff BR |
2926 | /** |
2927 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
2928 | * @pdev: the PCI device to operate on |
2929 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
2930 | * |
2931 | * Enables/disables PCI INTx for device dev | |
2932 | */ | |
3c78bc61 | 2933 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
2934 | { |
2935 | u16 pci_command, new; | |
2936 | ||
2937 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
2938 | ||
3c78bc61 | 2939 | if (enable) |
a04ce0ff | 2940 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 2941 | else |
a04ce0ff | 2942 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
2943 | |
2944 | if (new != pci_command) { | |
9ac7849e TH |
2945 | struct pci_devres *dr; |
2946 | ||
2fd9d74b | 2947 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
2948 | |
2949 | dr = find_pci_dr(pdev); | |
2950 | if (dr && !dr->restore_intx) { | |
2951 | dr->restore_intx = 1; | |
2952 | dr->orig_intx = !enable; | |
2953 | } | |
a04ce0ff BR |
2954 | } |
2955 | } | |
b7fe9434 | 2956 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 2957 | |
a2e27787 JK |
2958 | /** |
2959 | * pci_intx_mask_supported - probe for INTx masking support | |
6e9292c5 | 2960 | * @dev: the PCI device to operate on |
a2e27787 JK |
2961 | * |
2962 | * Check if the device dev support INTx masking via the config space | |
2963 | * command word. | |
2964 | */ | |
2965 | bool pci_intx_mask_supported(struct pci_dev *dev) | |
2966 | { | |
2967 | bool mask_supported = false; | |
2968 | u16 orig, new; | |
2969 | ||
fbebb9fd BH |
2970 | if (dev->broken_intx_masking) |
2971 | return false; | |
2972 | ||
a2e27787 JK |
2973 | pci_cfg_access_lock(dev); |
2974 | ||
2975 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
2976 | pci_write_config_word(dev, PCI_COMMAND, | |
2977 | orig ^ PCI_COMMAND_INTX_DISABLE); | |
2978 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
2979 | ||
2980 | /* | |
2981 | * There's no way to protect against hardware bugs or detect them | |
2982 | * reliably, but as long as we know what the value should be, let's | |
2983 | * go ahead and check it. | |
2984 | */ | |
2985 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { | |
227f0647 RD |
2986 | dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n", |
2987 | orig, new); | |
a2e27787 JK |
2988 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { |
2989 | mask_supported = true; | |
2990 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
2991 | } | |
2992 | ||
2993 | pci_cfg_access_unlock(dev); | |
2994 | return mask_supported; | |
2995 | } | |
2996 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); | |
2997 | ||
2998 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) | |
2999 | { | |
3000 | struct pci_bus *bus = dev->bus; | |
3001 | bool mask_updated = true; | |
3002 | u32 cmd_status_dword; | |
3003 | u16 origcmd, newcmd; | |
3004 | unsigned long flags; | |
3005 | bool irq_pending; | |
3006 | ||
3007 | /* | |
3008 | * We do a single dword read to retrieve both command and status. | |
3009 | * Document assumptions that make this possible. | |
3010 | */ | |
3011 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
3012 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
3013 | ||
3014 | raw_spin_lock_irqsave(&pci_lock, flags); | |
3015 | ||
3016 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
3017 | ||
3018 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
3019 | ||
3020 | /* | |
3021 | * Check interrupt status register to see whether our device | |
3022 | * triggered the interrupt (when masking) or the next IRQ is | |
3023 | * already pending (when unmasking). | |
3024 | */ | |
3025 | if (mask != irq_pending) { | |
3026 | mask_updated = false; | |
3027 | goto done; | |
3028 | } | |
3029 | ||
3030 | origcmd = cmd_status_dword; | |
3031 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
3032 | if (mask) | |
3033 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
3034 | if (newcmd != origcmd) | |
3035 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
3036 | ||
3037 | done: | |
3038 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
3039 | ||
3040 | return mask_updated; | |
3041 | } | |
3042 | ||
3043 | /** | |
3044 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 3045 | * @dev: the PCI device to operate on |
a2e27787 JK |
3046 | * |
3047 | * Check if the device dev has its INTx line asserted, mask it and | |
3048 | * return true in that case. False is returned if not interrupt was | |
3049 | * pending. | |
3050 | */ | |
3051 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
3052 | { | |
3053 | return pci_check_and_set_intx_mask(dev, true); | |
3054 | } | |
3055 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
3056 | ||
3057 | /** | |
ebd50b93 | 3058 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 3059 | * @dev: the PCI device to operate on |
a2e27787 JK |
3060 | * |
3061 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3062 | * and return true. False is returned and the mask remains active if | |
3063 | * there was still an interrupt pending. | |
3064 | */ | |
3065 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3066 | { | |
3067 | return pci_check_and_set_intx_mask(dev, false); | |
3068 | } | |
3069 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3070 | ||
f5f2b131 | 3071 | /** |
da27f4b3 | 3072 | * pci_msi_off - disables any MSI or MSI-X capabilities |
8d7d86e9 | 3073 | * @dev: the PCI device to operate on |
f5f2b131 | 3074 | * |
da27f4b3 BH |
3075 | * If you want to use MSI, see pci_enable_msi() and friends. |
3076 | * This is a lower-level primitive that allows us to disable | |
3077 | * MSI operation at the device level. | |
f5f2b131 EB |
3078 | */ |
3079 | void pci_msi_off(struct pci_dev *dev) | |
3080 | { | |
3081 | int pos; | |
3082 | u16 control; | |
3083 | ||
da27f4b3 BH |
3084 | /* |
3085 | * This looks like it could go in msi.c, but we need it even when | |
3086 | * CONFIG_PCI_MSI=n. For the same reason, we can't use | |
3087 | * dev->msi_cap or dev->msix_cap here. | |
3088 | */ | |
f5f2b131 EB |
3089 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
3090 | if (pos) { | |
3091 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
3092 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
3093 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
3094 | } | |
3095 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
3096 | if (pos) { | |
3097 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
3098 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
3099 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
3100 | } | |
3101 | } | |
b03214d5 | 3102 | EXPORT_SYMBOL_GPL(pci_msi_off); |
f5f2b131 | 3103 | |
4d57cdfa FT |
3104 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
3105 | { | |
3106 | return dma_set_max_seg_size(&dev->dev, size); | |
3107 | } | |
3108 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
4d57cdfa | 3109 | |
59fc67de FT |
3110 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
3111 | { | |
3112 | return dma_set_seg_boundary(&dev->dev, mask); | |
3113 | } | |
3114 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
59fc67de | 3115 | |
3775a209 CL |
3116 | /** |
3117 | * pci_wait_for_pending_transaction - waits for pending transaction | |
3118 | * @dev: the PCI device to operate on | |
3119 | * | |
3120 | * Return 0 if transaction is pending 1 otherwise. | |
3121 | */ | |
3122 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 3123 | { |
157e876f AW |
3124 | if (!pci_is_pcie(dev)) |
3125 | return 1; | |
8c1c699f | 3126 | |
d0b4cc4e GS |
3127 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
3128 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
3129 | } |
3130 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
3131 | ||
3132 | static int pcie_flr(struct pci_dev *dev, int probe) | |
3133 | { | |
3134 | u32 cap; | |
3135 | ||
3136 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); | |
3137 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
3138 | return -ENOTTY; | |
3139 | ||
3140 | if (probe) | |
3141 | return 0; | |
3142 | ||
3143 | if (!pci_wait_for_pending_transaction(dev)) | |
bb383e28 | 3144 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 3145 | |
59875ae4 | 3146 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
8c1c699f | 3147 | msleep(100); |
8dd7f803 SY |
3148 | return 0; |
3149 | } | |
d91cdc74 | 3150 | |
8c1c699f | 3151 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3152 | { |
8c1c699f | 3153 | int pos; |
1ca88797 SY |
3154 | u8 cap; |
3155 | ||
8c1c699f YZ |
3156 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3157 | if (!pos) | |
1ca88797 | 3158 | return -ENOTTY; |
8c1c699f YZ |
3159 | |
3160 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
3161 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3162 | return -ENOTTY; | |
3163 | ||
3164 | if (probe) | |
3165 | return 0; | |
3166 | ||
d066c946 AW |
3167 | /* |
3168 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
3169 | * is used, so we use the conrol offset rather than status and shift | |
3170 | * the test bit to match. | |
3171 | */ | |
bb383e28 | 3172 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 3173 | PCI_AF_STATUS_TP << 8)) |
bb383e28 | 3174 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 3175 | |
8c1c699f | 3176 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
1ca88797 | 3177 | msleep(100); |
1ca88797 SY |
3178 | return 0; |
3179 | } | |
3180 | ||
83d74e03 RW |
3181 | /** |
3182 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3183 | * @dev: Device to reset. | |
3184 | * @probe: If set, only check if the device can be reset this way. | |
3185 | * | |
3186 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3187 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3188 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3189 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3190 | * | |
3191 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3192 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 3193 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
3194 | * Moreover, only devices in D0 can be reset by this function. |
3195 | */ | |
f85876ba | 3196 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3197 | { |
f85876ba YZ |
3198 | u16 csr; |
3199 | ||
3200 | if (!dev->pm_cap) | |
3201 | return -ENOTTY; | |
d91cdc74 | 3202 | |
f85876ba YZ |
3203 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
3204 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
3205 | return -ENOTTY; | |
d91cdc74 | 3206 | |
f85876ba YZ |
3207 | if (probe) |
3208 | return 0; | |
1ca88797 | 3209 | |
f85876ba YZ |
3210 | if (dev->current_state != PCI_D0) |
3211 | return -EINVAL; | |
3212 | ||
3213 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3214 | csr |= PCI_D3hot; | |
3215 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3216 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3217 | |
3218 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3219 | csr |= PCI_D0; | |
3220 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3221 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3222 | |
3223 | return 0; | |
3224 | } | |
3225 | ||
9e33002f | 3226 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
3227 | { |
3228 | u16 ctrl; | |
64e8674f AW |
3229 | |
3230 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
3231 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
3232 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3233 | /* |
3234 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 3235 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
3236 | */ |
3237 | msleep(2); | |
64e8674f AW |
3238 | |
3239 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
3240 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3241 | |
3242 | /* | |
3243 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
3244 | * Assuming a minimum 33MHz clock this results in a 1s | |
3245 | * delay before we can consider subordinate devices to | |
3246 | * be re-initialized. PCIe has some ways to shorten this, | |
3247 | * but we don't make use of them yet. | |
3248 | */ | |
3249 | ssleep(1); | |
64e8674f | 3250 | } |
d92a208d | 3251 | |
9e33002f GS |
3252 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
3253 | { | |
3254 | pci_reset_secondary_bus(dev); | |
3255 | } | |
3256 | ||
d92a208d GS |
3257 | /** |
3258 | * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. | |
3259 | * @dev: Bridge device | |
3260 | * | |
3261 | * Use the bridge control register to assert reset on the secondary bus. | |
3262 | * Devices on the secondary bus are left in power-on state. | |
3263 | */ | |
3264 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev) | |
3265 | { | |
3266 | pcibios_reset_secondary_bus(dev); | |
3267 | } | |
64e8674f AW |
3268 | EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); |
3269 | ||
3270 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
3271 | { | |
c12ff1df YZ |
3272 | struct pci_dev *pdev; |
3273 | ||
f331a859 AW |
3274 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
3275 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
3276 | return -ENOTTY; |
3277 | ||
3278 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3279 | if (pdev != dev) | |
3280 | return -ENOTTY; | |
3281 | ||
3282 | if (probe) | |
3283 | return 0; | |
3284 | ||
64e8674f | 3285 | pci_reset_bridge_secondary_bus(dev->bus->self); |
c12ff1df YZ |
3286 | |
3287 | return 0; | |
3288 | } | |
3289 | ||
608c3881 AW |
3290 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
3291 | { | |
3292 | int rc = -ENOTTY; | |
3293 | ||
3294 | if (!hotplug || !try_module_get(hotplug->ops->owner)) | |
3295 | return rc; | |
3296 | ||
3297 | if (hotplug->ops->reset_slot) | |
3298 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
3299 | ||
3300 | module_put(hotplug->ops->owner); | |
3301 | ||
3302 | return rc; | |
3303 | } | |
3304 | ||
3305 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
3306 | { | |
3307 | struct pci_dev *pdev; | |
3308 | ||
f331a859 AW |
3309 | if (dev->subordinate || !dev->slot || |
3310 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
3311 | return -ENOTTY; |
3312 | ||
3313 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3314 | if (pdev != dev && pdev->slot == dev->slot) | |
3315 | return -ENOTTY; | |
3316 | ||
3317 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
3318 | } | |
3319 | ||
977f857c | 3320 | static int __pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3321 | { |
8c1c699f YZ |
3322 | int rc; |
3323 | ||
3324 | might_sleep(); | |
3325 | ||
b9c3b266 DC |
3326 | rc = pci_dev_specific_reset(dev, probe); |
3327 | if (rc != -ENOTTY) | |
3328 | goto done; | |
3329 | ||
8c1c699f YZ |
3330 | rc = pcie_flr(dev, probe); |
3331 | if (rc != -ENOTTY) | |
3332 | goto done; | |
d91cdc74 | 3333 | |
8c1c699f | 3334 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
3335 | if (rc != -ENOTTY) |
3336 | goto done; | |
3337 | ||
3338 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
3339 | if (rc != -ENOTTY) |
3340 | goto done; | |
3341 | ||
608c3881 AW |
3342 | rc = pci_dev_reset_slot_function(dev, probe); |
3343 | if (rc != -ENOTTY) | |
3344 | goto done; | |
3345 | ||
c12ff1df | 3346 | rc = pci_parent_bus_reset(dev, probe); |
8c1c699f | 3347 | done: |
977f857c KRW |
3348 | return rc; |
3349 | } | |
3350 | ||
77cb985a AW |
3351 | static void pci_dev_lock(struct pci_dev *dev) |
3352 | { | |
3353 | pci_cfg_access_lock(dev); | |
3354 | /* block PM suspend, driver probe, etc. */ | |
3355 | device_lock(&dev->dev); | |
3356 | } | |
3357 | ||
61cf16d8 AW |
3358 | /* Return 1 on successful lock, 0 on contention */ |
3359 | static int pci_dev_trylock(struct pci_dev *dev) | |
3360 | { | |
3361 | if (pci_cfg_access_trylock(dev)) { | |
3362 | if (device_trylock(&dev->dev)) | |
3363 | return 1; | |
3364 | pci_cfg_access_unlock(dev); | |
3365 | } | |
3366 | ||
3367 | return 0; | |
3368 | } | |
3369 | ||
77cb985a AW |
3370 | static void pci_dev_unlock(struct pci_dev *dev) |
3371 | { | |
3372 | device_unlock(&dev->dev); | |
3373 | pci_cfg_access_unlock(dev); | |
3374 | } | |
3375 | ||
3ebe7f9f KB |
3376 | /** |
3377 | * pci_reset_notify - notify device driver of reset | |
3378 | * @dev: device to be notified of reset | |
3379 | * @prepare: 'true' if device is about to be reset; 'false' if reset attempt | |
3380 | * completed | |
3381 | * | |
3382 | * Must be called prior to device access being disabled and after device | |
3383 | * access is restored. | |
3384 | */ | |
3385 | static void pci_reset_notify(struct pci_dev *dev, bool prepare) | |
3386 | { | |
3387 | const struct pci_error_handlers *err_handler = | |
3388 | dev->driver ? dev->driver->err_handler : NULL; | |
3389 | if (err_handler && err_handler->reset_notify) | |
3390 | err_handler->reset_notify(dev, prepare); | |
3391 | } | |
3392 | ||
77cb985a AW |
3393 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3394 | { | |
3ebe7f9f KB |
3395 | pci_reset_notify(dev, true); |
3396 | ||
a6cbaade AW |
3397 | /* |
3398 | * Wake-up device prior to save. PM registers default to D0 after | |
3399 | * reset and a simple register restore doesn't reliably return | |
3400 | * to a non-D0 state anyway. | |
3401 | */ | |
3402 | pci_set_power_state(dev, PCI_D0); | |
3403 | ||
77cb985a AW |
3404 | pci_save_state(dev); |
3405 | /* | |
3406 | * Disable the device by clearing the Command register, except for | |
3407 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
3408 | * BARs, but also prevents the device from being Bus Master, preventing | |
3409 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
3410 | * compliant devices, INTx-disable prevents legacy interrupts. | |
3411 | */ | |
3412 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
3413 | } | |
3414 | ||
3415 | static void pci_dev_restore(struct pci_dev *dev) | |
3416 | { | |
3417 | pci_restore_state(dev); | |
3ebe7f9f | 3418 | pci_reset_notify(dev, false); |
77cb985a AW |
3419 | } |
3420 | ||
977f857c KRW |
3421 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
3422 | { | |
3423 | int rc; | |
3424 | ||
77cb985a AW |
3425 | if (!probe) |
3426 | pci_dev_lock(dev); | |
977f857c KRW |
3427 | |
3428 | rc = __pci_dev_reset(dev, probe); | |
3429 | ||
77cb985a AW |
3430 | if (!probe) |
3431 | pci_dev_unlock(dev); | |
3432 | ||
8c1c699f | 3433 | return rc; |
d91cdc74 | 3434 | } |
3ebe7f9f | 3435 | |
d91cdc74 | 3436 | /** |
8c1c699f YZ |
3437 | * __pci_reset_function - reset a PCI device function |
3438 | * @dev: PCI device to reset | |
d91cdc74 SY |
3439 | * |
3440 | * Some devices allow an individual function to be reset without affecting | |
3441 | * other functions in the same device. The PCI device must be responsive | |
3442 | * to PCI config space in order to use this function. | |
3443 | * | |
3444 | * The device function is presumed to be unused when this function is called. | |
3445 | * Resetting the device will make the contents of PCI configuration space | |
3446 | * random, so any caller of this must be prepared to reinitialise the | |
3447 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3448 | * etc. | |
3449 | * | |
8c1c699f | 3450 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
3451 | * device doesn't support resetting a single function. |
3452 | */ | |
8c1c699f | 3453 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 3454 | { |
8c1c699f | 3455 | return pci_dev_reset(dev, 0); |
d91cdc74 | 3456 | } |
8c1c699f | 3457 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 3458 | |
6fbf9e7a KRW |
3459 | /** |
3460 | * __pci_reset_function_locked - reset a PCI device function while holding | |
3461 | * the @dev mutex lock. | |
3462 | * @dev: PCI device to reset | |
3463 | * | |
3464 | * Some devices allow an individual function to be reset without affecting | |
3465 | * other functions in the same device. The PCI device must be responsive | |
3466 | * to PCI config space in order to use this function. | |
3467 | * | |
3468 | * The device function is presumed to be unused and the caller is holding | |
3469 | * the device mutex lock when this function is called. | |
3470 | * Resetting the device will make the contents of PCI configuration space | |
3471 | * random, so any caller of this must be prepared to reinitialise the | |
3472 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3473 | * etc. | |
3474 | * | |
3475 | * Returns 0 if the device function was successfully reset or negative if the | |
3476 | * device doesn't support resetting a single function. | |
3477 | */ | |
3478 | int __pci_reset_function_locked(struct pci_dev *dev) | |
3479 | { | |
977f857c | 3480 | return __pci_dev_reset(dev, 0); |
6fbf9e7a KRW |
3481 | } |
3482 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
3483 | ||
711d5779 MT |
3484 | /** |
3485 | * pci_probe_reset_function - check whether the device can be safely reset | |
3486 | * @dev: PCI device to reset | |
3487 | * | |
3488 | * Some devices allow an individual function to be reset without affecting | |
3489 | * other functions in the same device. The PCI device must be responsive | |
3490 | * to PCI config space in order to use this function. | |
3491 | * | |
3492 | * Returns 0 if the device function can be reset or negative if the | |
3493 | * device doesn't support resetting a single function. | |
3494 | */ | |
3495 | int pci_probe_reset_function(struct pci_dev *dev) | |
3496 | { | |
3497 | return pci_dev_reset(dev, 1); | |
3498 | } | |
3499 | ||
8dd7f803 | 3500 | /** |
8c1c699f YZ |
3501 | * pci_reset_function - quiesce and reset a PCI device function |
3502 | * @dev: PCI device to reset | |
8dd7f803 SY |
3503 | * |
3504 | * Some devices allow an individual function to be reset without affecting | |
3505 | * other functions in the same device. The PCI device must be responsive | |
3506 | * to PCI config space in order to use this function. | |
3507 | * | |
3508 | * This function does not just reset the PCI portion of a device, but | |
3509 | * clears all the state associated with the device. This function differs | |
8c1c699f | 3510 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
3511 | * over the reset. |
3512 | * | |
8c1c699f | 3513 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
3514 | * device doesn't support resetting a single function. |
3515 | */ | |
3516 | int pci_reset_function(struct pci_dev *dev) | |
3517 | { | |
8c1c699f | 3518 | int rc; |
8dd7f803 | 3519 | |
8c1c699f YZ |
3520 | rc = pci_dev_reset(dev, 1); |
3521 | if (rc) | |
3522 | return rc; | |
8dd7f803 | 3523 | |
77cb985a | 3524 | pci_dev_save_and_disable(dev); |
8dd7f803 | 3525 | |
8c1c699f | 3526 | rc = pci_dev_reset(dev, 0); |
8dd7f803 | 3527 | |
77cb985a | 3528 | pci_dev_restore(dev); |
8dd7f803 | 3529 | |
8c1c699f | 3530 | return rc; |
8dd7f803 SY |
3531 | } |
3532 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
3533 | ||
61cf16d8 AW |
3534 | /** |
3535 | * pci_try_reset_function - quiesce and reset a PCI device function | |
3536 | * @dev: PCI device to reset | |
3537 | * | |
3538 | * Same as above, except return -EAGAIN if unable to lock device. | |
3539 | */ | |
3540 | int pci_try_reset_function(struct pci_dev *dev) | |
3541 | { | |
3542 | int rc; | |
3543 | ||
3544 | rc = pci_dev_reset(dev, 1); | |
3545 | if (rc) | |
3546 | return rc; | |
3547 | ||
3548 | pci_dev_save_and_disable(dev); | |
3549 | ||
3550 | if (pci_dev_trylock(dev)) { | |
3551 | rc = __pci_dev_reset(dev, 0); | |
3552 | pci_dev_unlock(dev); | |
3553 | } else | |
3554 | rc = -EAGAIN; | |
3555 | ||
3556 | pci_dev_restore(dev); | |
3557 | ||
3558 | return rc; | |
3559 | } | |
3560 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
3561 | ||
f331a859 AW |
3562 | /* Do any devices on or below this bus prevent a bus reset? */ |
3563 | static bool pci_bus_resetable(struct pci_bus *bus) | |
3564 | { | |
3565 | struct pci_dev *dev; | |
3566 | ||
3567 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3568 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
3569 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
3570 | return false; | |
3571 | } | |
3572 | ||
3573 | return true; | |
3574 | } | |
3575 | ||
090a3c53 AW |
3576 | /* Lock devices from the top of the tree down */ |
3577 | static void pci_bus_lock(struct pci_bus *bus) | |
3578 | { | |
3579 | struct pci_dev *dev; | |
3580 | ||
3581 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3582 | pci_dev_lock(dev); | |
3583 | if (dev->subordinate) | |
3584 | pci_bus_lock(dev->subordinate); | |
3585 | } | |
3586 | } | |
3587 | ||
3588 | /* Unlock devices from the bottom of the tree up */ | |
3589 | static void pci_bus_unlock(struct pci_bus *bus) | |
3590 | { | |
3591 | struct pci_dev *dev; | |
3592 | ||
3593 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3594 | if (dev->subordinate) | |
3595 | pci_bus_unlock(dev->subordinate); | |
3596 | pci_dev_unlock(dev); | |
3597 | } | |
3598 | } | |
3599 | ||
61cf16d8 AW |
3600 | /* Return 1 on successful lock, 0 on contention */ |
3601 | static int pci_bus_trylock(struct pci_bus *bus) | |
3602 | { | |
3603 | struct pci_dev *dev; | |
3604 | ||
3605 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3606 | if (!pci_dev_trylock(dev)) | |
3607 | goto unlock; | |
3608 | if (dev->subordinate) { | |
3609 | if (!pci_bus_trylock(dev->subordinate)) { | |
3610 | pci_dev_unlock(dev); | |
3611 | goto unlock; | |
3612 | } | |
3613 | } | |
3614 | } | |
3615 | return 1; | |
3616 | ||
3617 | unlock: | |
3618 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
3619 | if (dev->subordinate) | |
3620 | pci_bus_unlock(dev->subordinate); | |
3621 | pci_dev_unlock(dev); | |
3622 | } | |
3623 | return 0; | |
3624 | } | |
3625 | ||
f331a859 AW |
3626 | /* Do any devices on or below this slot prevent a bus reset? */ |
3627 | static bool pci_slot_resetable(struct pci_slot *slot) | |
3628 | { | |
3629 | struct pci_dev *dev; | |
3630 | ||
3631 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3632 | if (!dev->slot || dev->slot != slot) | |
3633 | continue; | |
3634 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
3635 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
3636 | return false; | |
3637 | } | |
3638 | ||
3639 | return true; | |
3640 | } | |
3641 | ||
090a3c53 AW |
3642 | /* Lock devices from the top of the tree down */ |
3643 | static void pci_slot_lock(struct pci_slot *slot) | |
3644 | { | |
3645 | struct pci_dev *dev; | |
3646 | ||
3647 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3648 | if (!dev->slot || dev->slot != slot) | |
3649 | continue; | |
3650 | pci_dev_lock(dev); | |
3651 | if (dev->subordinate) | |
3652 | pci_bus_lock(dev->subordinate); | |
3653 | } | |
3654 | } | |
3655 | ||
3656 | /* Unlock devices from the bottom of the tree up */ | |
3657 | static void pci_slot_unlock(struct pci_slot *slot) | |
3658 | { | |
3659 | struct pci_dev *dev; | |
3660 | ||
3661 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3662 | if (!dev->slot || dev->slot != slot) | |
3663 | continue; | |
3664 | if (dev->subordinate) | |
3665 | pci_bus_unlock(dev->subordinate); | |
3666 | pci_dev_unlock(dev); | |
3667 | } | |
3668 | } | |
3669 | ||
61cf16d8 AW |
3670 | /* Return 1 on successful lock, 0 on contention */ |
3671 | static int pci_slot_trylock(struct pci_slot *slot) | |
3672 | { | |
3673 | struct pci_dev *dev; | |
3674 | ||
3675 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3676 | if (!dev->slot || dev->slot != slot) | |
3677 | continue; | |
3678 | if (!pci_dev_trylock(dev)) | |
3679 | goto unlock; | |
3680 | if (dev->subordinate) { | |
3681 | if (!pci_bus_trylock(dev->subordinate)) { | |
3682 | pci_dev_unlock(dev); | |
3683 | goto unlock; | |
3684 | } | |
3685 | } | |
3686 | } | |
3687 | return 1; | |
3688 | ||
3689 | unlock: | |
3690 | list_for_each_entry_continue_reverse(dev, | |
3691 | &slot->bus->devices, bus_list) { | |
3692 | if (!dev->slot || dev->slot != slot) | |
3693 | continue; | |
3694 | if (dev->subordinate) | |
3695 | pci_bus_unlock(dev->subordinate); | |
3696 | pci_dev_unlock(dev); | |
3697 | } | |
3698 | return 0; | |
3699 | } | |
3700 | ||
090a3c53 AW |
3701 | /* Save and disable devices from the top of the tree down */ |
3702 | static void pci_bus_save_and_disable(struct pci_bus *bus) | |
3703 | { | |
3704 | struct pci_dev *dev; | |
3705 | ||
3706 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3707 | pci_dev_save_and_disable(dev); | |
3708 | if (dev->subordinate) | |
3709 | pci_bus_save_and_disable(dev->subordinate); | |
3710 | } | |
3711 | } | |
3712 | ||
3713 | /* | |
3714 | * Restore devices from top of the tree down - parent bridges need to be | |
3715 | * restored before we can get to subordinate devices. | |
3716 | */ | |
3717 | static void pci_bus_restore(struct pci_bus *bus) | |
3718 | { | |
3719 | struct pci_dev *dev; | |
3720 | ||
3721 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3722 | pci_dev_restore(dev); | |
3723 | if (dev->subordinate) | |
3724 | pci_bus_restore(dev->subordinate); | |
3725 | } | |
3726 | } | |
3727 | ||
3728 | /* Save and disable devices from the top of the tree down */ | |
3729 | static void pci_slot_save_and_disable(struct pci_slot *slot) | |
3730 | { | |
3731 | struct pci_dev *dev; | |
3732 | ||
3733 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3734 | if (!dev->slot || dev->slot != slot) | |
3735 | continue; | |
3736 | pci_dev_save_and_disable(dev); | |
3737 | if (dev->subordinate) | |
3738 | pci_bus_save_and_disable(dev->subordinate); | |
3739 | } | |
3740 | } | |
3741 | ||
3742 | /* | |
3743 | * Restore devices from top of the tree down - parent bridges need to be | |
3744 | * restored before we can get to subordinate devices. | |
3745 | */ | |
3746 | static void pci_slot_restore(struct pci_slot *slot) | |
3747 | { | |
3748 | struct pci_dev *dev; | |
3749 | ||
3750 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3751 | if (!dev->slot || dev->slot != slot) | |
3752 | continue; | |
3753 | pci_dev_restore(dev); | |
3754 | if (dev->subordinate) | |
3755 | pci_bus_restore(dev->subordinate); | |
3756 | } | |
3757 | } | |
3758 | ||
3759 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
3760 | { | |
3761 | int rc; | |
3762 | ||
f331a859 | 3763 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
3764 | return -ENOTTY; |
3765 | ||
3766 | if (!probe) | |
3767 | pci_slot_lock(slot); | |
3768 | ||
3769 | might_sleep(); | |
3770 | ||
3771 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
3772 | ||
3773 | if (!probe) | |
3774 | pci_slot_unlock(slot); | |
3775 | ||
3776 | return rc; | |
3777 | } | |
3778 | ||
9a3d2b9b AW |
3779 | /** |
3780 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
3781 | * @slot: PCI slot to probe | |
3782 | * | |
3783 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
3784 | */ | |
3785 | int pci_probe_reset_slot(struct pci_slot *slot) | |
3786 | { | |
3787 | return pci_slot_reset(slot, 1); | |
3788 | } | |
3789 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
3790 | ||
090a3c53 AW |
3791 | /** |
3792 | * pci_reset_slot - reset a PCI slot | |
3793 | * @slot: PCI slot to reset | |
3794 | * | |
3795 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
3796 | * independent of other slots. For instance, some slots may support slot power | |
3797 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
3798 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
3799 | * Generally a slot reset should be attempted before a bus reset. All of the | |
3800 | * function of the slot and any subordinate buses behind the slot are reset | |
3801 | * through this function. PCI config space of all devices in the slot and | |
3802 | * behind the slot is saved before and restored after reset. | |
3803 | * | |
3804 | * Return 0 on success, non-zero on error. | |
3805 | */ | |
3806 | int pci_reset_slot(struct pci_slot *slot) | |
3807 | { | |
3808 | int rc; | |
3809 | ||
3810 | rc = pci_slot_reset(slot, 1); | |
3811 | if (rc) | |
3812 | return rc; | |
3813 | ||
3814 | pci_slot_save_and_disable(slot); | |
3815 | ||
3816 | rc = pci_slot_reset(slot, 0); | |
3817 | ||
3818 | pci_slot_restore(slot); | |
3819 | ||
3820 | return rc; | |
3821 | } | |
3822 | EXPORT_SYMBOL_GPL(pci_reset_slot); | |
3823 | ||
61cf16d8 AW |
3824 | /** |
3825 | * pci_try_reset_slot - Try to reset a PCI slot | |
3826 | * @slot: PCI slot to reset | |
3827 | * | |
3828 | * Same as above except return -EAGAIN if the slot cannot be locked | |
3829 | */ | |
3830 | int pci_try_reset_slot(struct pci_slot *slot) | |
3831 | { | |
3832 | int rc; | |
3833 | ||
3834 | rc = pci_slot_reset(slot, 1); | |
3835 | if (rc) | |
3836 | return rc; | |
3837 | ||
3838 | pci_slot_save_and_disable(slot); | |
3839 | ||
3840 | if (pci_slot_trylock(slot)) { | |
3841 | might_sleep(); | |
3842 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
3843 | pci_slot_unlock(slot); | |
3844 | } else | |
3845 | rc = -EAGAIN; | |
3846 | ||
3847 | pci_slot_restore(slot); | |
3848 | ||
3849 | return rc; | |
3850 | } | |
3851 | EXPORT_SYMBOL_GPL(pci_try_reset_slot); | |
3852 | ||
090a3c53 AW |
3853 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
3854 | { | |
f331a859 | 3855 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
3856 | return -ENOTTY; |
3857 | ||
3858 | if (probe) | |
3859 | return 0; | |
3860 | ||
3861 | pci_bus_lock(bus); | |
3862 | ||
3863 | might_sleep(); | |
3864 | ||
3865 | pci_reset_bridge_secondary_bus(bus->self); | |
3866 | ||
3867 | pci_bus_unlock(bus); | |
3868 | ||
3869 | return 0; | |
3870 | } | |
3871 | ||
9a3d2b9b AW |
3872 | /** |
3873 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
3874 | * @bus: PCI bus to probe | |
3875 | * | |
3876 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
3877 | */ | |
3878 | int pci_probe_reset_bus(struct pci_bus *bus) | |
3879 | { | |
3880 | return pci_bus_reset(bus, 1); | |
3881 | } | |
3882 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
3883 | ||
090a3c53 AW |
3884 | /** |
3885 | * pci_reset_bus - reset a PCI bus | |
3886 | * @bus: top level PCI bus to reset | |
3887 | * | |
3888 | * Do a bus reset on the given bus and any subordinate buses, saving | |
3889 | * and restoring state of all devices. | |
3890 | * | |
3891 | * Return 0 on success, non-zero on error. | |
3892 | */ | |
3893 | int pci_reset_bus(struct pci_bus *bus) | |
3894 | { | |
3895 | int rc; | |
3896 | ||
3897 | rc = pci_bus_reset(bus, 1); | |
3898 | if (rc) | |
3899 | return rc; | |
3900 | ||
3901 | pci_bus_save_and_disable(bus); | |
3902 | ||
3903 | rc = pci_bus_reset(bus, 0); | |
3904 | ||
3905 | pci_bus_restore(bus); | |
3906 | ||
3907 | return rc; | |
3908 | } | |
3909 | EXPORT_SYMBOL_GPL(pci_reset_bus); | |
3910 | ||
61cf16d8 AW |
3911 | /** |
3912 | * pci_try_reset_bus - Try to reset a PCI bus | |
3913 | * @bus: top level PCI bus to reset | |
3914 | * | |
3915 | * Same as above except return -EAGAIN if the bus cannot be locked | |
3916 | */ | |
3917 | int pci_try_reset_bus(struct pci_bus *bus) | |
3918 | { | |
3919 | int rc; | |
3920 | ||
3921 | rc = pci_bus_reset(bus, 1); | |
3922 | if (rc) | |
3923 | return rc; | |
3924 | ||
3925 | pci_bus_save_and_disable(bus); | |
3926 | ||
3927 | if (pci_bus_trylock(bus)) { | |
3928 | might_sleep(); | |
3929 | pci_reset_bridge_secondary_bus(bus->self); | |
3930 | pci_bus_unlock(bus); | |
3931 | } else | |
3932 | rc = -EAGAIN; | |
3933 | ||
3934 | pci_bus_restore(bus); | |
3935 | ||
3936 | return rc; | |
3937 | } | |
3938 | EXPORT_SYMBOL_GPL(pci_try_reset_bus); | |
3939 | ||
d556ad4b PO |
3940 | /** |
3941 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
3942 | * @dev: PCI device to query | |
3943 | * | |
3944 | * Returns mmrbc: maximum designed memory read count in bytes | |
3945 | * or appropriate error value. | |
3946 | */ | |
3947 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
3948 | { | |
7c9e2b1c | 3949 | int cap; |
d556ad4b PO |
3950 | u32 stat; |
3951 | ||
3952 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3953 | if (!cap) | |
3954 | return -EINVAL; | |
3955 | ||
7c9e2b1c | 3956 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
3957 | return -EINVAL; |
3958 | ||
25daeb55 | 3959 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
3960 | } |
3961 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
3962 | ||
3963 | /** | |
3964 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
3965 | * @dev: PCI device to query | |
3966 | * | |
3967 | * Returns mmrbc: maximum memory read count in bytes | |
3968 | * or appropriate error value. | |
3969 | */ | |
3970 | int pcix_get_mmrbc(struct pci_dev *dev) | |
3971 | { | |
7c9e2b1c | 3972 | int cap; |
bdc2bda7 | 3973 | u16 cmd; |
d556ad4b PO |
3974 | |
3975 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3976 | if (!cap) | |
3977 | return -EINVAL; | |
3978 | ||
7c9e2b1c DN |
3979 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3980 | return -EINVAL; | |
d556ad4b | 3981 | |
7c9e2b1c | 3982 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
3983 | } |
3984 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
3985 | ||
3986 | /** | |
3987 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
3988 | * @dev: PCI device to query | |
3989 | * @mmrbc: maximum memory read count in bytes | |
3990 | * valid values are 512, 1024, 2048, 4096 | |
3991 | * | |
3992 | * If possible sets maximum memory read byte count, some bridges have erratas | |
3993 | * that prevent this. | |
3994 | */ | |
3995 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
3996 | { | |
7c9e2b1c | 3997 | int cap; |
bdc2bda7 DN |
3998 | u32 stat, v, o; |
3999 | u16 cmd; | |
d556ad4b | 4000 | |
229f5afd | 4001 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 4002 | return -EINVAL; |
d556ad4b PO |
4003 | |
4004 | v = ffs(mmrbc) - 10; | |
4005 | ||
4006 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4007 | if (!cap) | |
7c9e2b1c | 4008 | return -EINVAL; |
d556ad4b | 4009 | |
7c9e2b1c DN |
4010 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
4011 | return -EINVAL; | |
d556ad4b PO |
4012 | |
4013 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
4014 | return -E2BIG; | |
4015 | ||
7c9e2b1c DN |
4016 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4017 | return -EINVAL; | |
d556ad4b PO |
4018 | |
4019 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
4020 | if (o != v) { | |
809a3bf9 | 4021 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
4022 | return -EIO; |
4023 | ||
4024 | cmd &= ~PCI_X_CMD_MAX_READ; | |
4025 | cmd |= v << 2; | |
7c9e2b1c DN |
4026 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
4027 | return -EIO; | |
d556ad4b | 4028 | } |
7c9e2b1c | 4029 | return 0; |
d556ad4b PO |
4030 | } |
4031 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
4032 | ||
4033 | /** | |
4034 | * pcie_get_readrq - get PCI Express read request size | |
4035 | * @dev: PCI device to query | |
4036 | * | |
4037 | * Returns maximum memory read request in bytes | |
4038 | * or appropriate error value. | |
4039 | */ | |
4040 | int pcie_get_readrq(struct pci_dev *dev) | |
4041 | { | |
d556ad4b PO |
4042 | u16 ctl; |
4043 | ||
59875ae4 | 4044 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 4045 | |
59875ae4 | 4046 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
4047 | } |
4048 | EXPORT_SYMBOL(pcie_get_readrq); | |
4049 | ||
4050 | /** | |
4051 | * pcie_set_readrq - set PCI Express maximum memory read request | |
4052 | * @dev: PCI device to query | |
42e61f4a | 4053 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
4054 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4055 | * | |
c9b378c7 | 4056 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
4057 | */ |
4058 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
4059 | { | |
59875ae4 | 4060 | u16 v; |
d556ad4b | 4061 | |
229f5afd | 4062 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 4063 | return -EINVAL; |
d556ad4b | 4064 | |
a1c473aa BH |
4065 | /* |
4066 | * If using the "performance" PCIe config, we clamp the | |
4067 | * read rq size to the max packet size to prevent the | |
4068 | * host bridge generating requests larger than we can | |
4069 | * cope with | |
4070 | */ | |
4071 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
4072 | int mps = pcie_get_mps(dev); | |
4073 | ||
a1c473aa BH |
4074 | if (mps < rq) |
4075 | rq = mps; | |
4076 | } | |
4077 | ||
4078 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 4079 | |
59875ae4 JL |
4080 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4081 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
4082 | } |
4083 | EXPORT_SYMBOL(pcie_set_readrq); | |
4084 | ||
b03e7495 JM |
4085 | /** |
4086 | * pcie_get_mps - get PCI Express maximum payload size | |
4087 | * @dev: PCI device to query | |
4088 | * | |
4089 | * Returns maximum payload size in bytes | |
b03e7495 JM |
4090 | */ |
4091 | int pcie_get_mps(struct pci_dev *dev) | |
4092 | { | |
b03e7495 JM |
4093 | u16 ctl; |
4094 | ||
59875ae4 | 4095 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 4096 | |
59875ae4 | 4097 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 4098 | } |
f1c66c46 | 4099 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
4100 | |
4101 | /** | |
4102 | * pcie_set_mps - set PCI Express maximum payload size | |
4103 | * @dev: PCI device to query | |
47c08f31 | 4104 | * @mps: maximum payload size in bytes |
b03e7495 JM |
4105 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4106 | * | |
4107 | * If possible sets maximum payload size | |
4108 | */ | |
4109 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
4110 | { | |
59875ae4 | 4111 | u16 v; |
b03e7495 JM |
4112 | |
4113 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 4114 | return -EINVAL; |
b03e7495 JM |
4115 | |
4116 | v = ffs(mps) - 8; | |
f7625980 | 4117 | if (v > dev->pcie_mpss) |
59875ae4 | 4118 | return -EINVAL; |
b03e7495 JM |
4119 | v <<= 5; |
4120 | ||
59875ae4 JL |
4121 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4122 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 4123 | } |
f1c66c46 | 4124 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 4125 | |
81377c8d JK |
4126 | /** |
4127 | * pcie_get_minimum_link - determine minimum link settings of a PCI device | |
4128 | * @dev: PCI device to query | |
4129 | * @speed: storage for minimum speed | |
4130 | * @width: storage for minimum width | |
4131 | * | |
4132 | * This function will walk up the PCI device chain and determine the minimum | |
4133 | * link width and speed of the device. | |
4134 | */ | |
4135 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, | |
4136 | enum pcie_link_width *width) | |
4137 | { | |
4138 | int ret; | |
4139 | ||
4140 | *speed = PCI_SPEED_UNKNOWN; | |
4141 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4142 | ||
4143 | while (dev) { | |
4144 | u16 lnksta; | |
4145 | enum pci_bus_speed next_speed; | |
4146 | enum pcie_link_width next_width; | |
4147 | ||
4148 | ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
4149 | if (ret) | |
4150 | return ret; | |
4151 | ||
4152 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
4153 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
4154 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
4155 | ||
4156 | if (next_speed < *speed) | |
4157 | *speed = next_speed; | |
4158 | ||
4159 | if (next_width < *width) | |
4160 | *width = next_width; | |
4161 | ||
4162 | dev = dev->bus->self; | |
4163 | } | |
4164 | ||
4165 | return 0; | |
4166 | } | |
4167 | EXPORT_SYMBOL(pcie_get_minimum_link); | |
4168 | ||
c87deff7 HS |
4169 | /** |
4170 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 4171 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
4172 | * @flags: resource type mask to be selected |
4173 | * | |
4174 | * This helper routine makes bar mask from the type of resource. | |
4175 | */ | |
4176 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
4177 | { | |
4178 | int i, bars = 0; | |
4179 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
4180 | if (pci_resource_flags(dev, i) & flags) | |
4181 | bars |= (1 << i); | |
4182 | return bars; | |
4183 | } | |
b7fe9434 | 4184 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 4185 | |
613e7ed6 YZ |
4186 | /** |
4187 | * pci_resource_bar - get position of the BAR associated with a resource | |
4188 | * @dev: the PCI device | |
4189 | * @resno: the resource number | |
4190 | * @type: the BAR type to be filled in | |
4191 | * | |
4192 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
4193 | */ | |
4194 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
4195 | { | |
d1b054da YZ |
4196 | int reg; |
4197 | ||
613e7ed6 YZ |
4198 | if (resno < PCI_ROM_RESOURCE) { |
4199 | *type = pci_bar_unknown; | |
4200 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
4201 | } else if (resno == PCI_ROM_RESOURCE) { | |
4202 | *type = pci_bar_mem32; | |
4203 | return dev->rom_base_reg; | |
d1b054da YZ |
4204 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
4205 | /* device specific resource */ | |
26ff46c6 MS |
4206 | *type = pci_bar_unknown; |
4207 | reg = pci_iov_resource_bar(dev, resno); | |
d1b054da YZ |
4208 | if (reg) |
4209 | return reg; | |
613e7ed6 YZ |
4210 | } |
4211 | ||
865df576 | 4212 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
4213 | return 0; |
4214 | } | |
4215 | ||
95a8b6ef MT |
4216 | /* Some architectures require additional programming to enable VGA */ |
4217 | static arch_set_vga_state_t arch_set_vga_state; | |
4218 | ||
4219 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
4220 | { | |
4221 | arch_set_vga_state = func; /* NULL disables */ | |
4222 | } | |
4223 | ||
4224 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 4225 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
4226 | { |
4227 | if (arch_set_vga_state) | |
4228 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 4229 | flags); |
95a8b6ef MT |
4230 | return 0; |
4231 | } | |
4232 | ||
deb2d2ec BH |
4233 | /** |
4234 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
4235 | * @dev: the PCI device |
4236 | * @decode: true = enable decoding, false = disable decoding | |
4237 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 4238 | * @flags: traverse ancestors and change bridges |
3448a19d | 4239 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
4240 | */ |
4241 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 4242 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
4243 | { |
4244 | struct pci_bus *bus; | |
4245 | struct pci_dev *bridge; | |
4246 | u16 cmd; | |
95a8b6ef | 4247 | int rc; |
deb2d2ec | 4248 | |
67ebd814 | 4249 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 4250 | |
95a8b6ef | 4251 | /* ARCH specific VGA enables */ |
3448a19d | 4252 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
4253 | if (rc) |
4254 | return rc; | |
4255 | ||
3448a19d DA |
4256 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
4257 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4258 | if (decode == true) | |
4259 | cmd |= command_bits; | |
4260 | else | |
4261 | cmd &= ~command_bits; | |
4262 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4263 | } | |
deb2d2ec | 4264 | |
3448a19d | 4265 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
4266 | return 0; |
4267 | ||
4268 | bus = dev->bus; | |
4269 | while (bus) { | |
4270 | bridge = bus->self; | |
4271 | if (bridge) { | |
4272 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4273 | &cmd); | |
4274 | if (decode == true) | |
4275 | cmd |= PCI_BRIDGE_CTL_VGA; | |
4276 | else | |
4277 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
4278 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4279 | cmd); | |
4280 | } | |
4281 | bus = bus->parent; | |
4282 | } | |
4283 | return 0; | |
4284 | } | |
4285 | ||
8496e85c RW |
4286 | bool pci_device_is_present(struct pci_dev *pdev) |
4287 | { | |
4288 | u32 v; | |
4289 | ||
4290 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); | |
4291 | } | |
4292 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
4293 | ||
32a9a682 YS |
4294 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
4295 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 4296 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
4297 | |
4298 | /** | |
4299 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
4300 | * @dev: the PCI device to get | |
4301 | * | |
4302 | * RETURNS: Resource alignment if it is specified. | |
4303 | * Zero if it is not specified. | |
4304 | */ | |
9738abed | 4305 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) |
32a9a682 YS |
4306 | { |
4307 | int seg, bus, slot, func, align_order, count; | |
4308 | resource_size_t align = 0; | |
4309 | char *p; | |
4310 | ||
4311 | spin_lock(&resource_alignment_lock); | |
4312 | p = resource_alignment_param; | |
4313 | while (*p) { | |
4314 | count = 0; | |
4315 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
4316 | p[count] == '@') { | |
4317 | p += count + 1; | |
4318 | } else { | |
4319 | align_order = -1; | |
4320 | } | |
4321 | if (sscanf(p, "%x:%x:%x.%x%n", | |
4322 | &seg, &bus, &slot, &func, &count) != 4) { | |
4323 | seg = 0; | |
4324 | if (sscanf(p, "%x:%x.%x%n", | |
4325 | &bus, &slot, &func, &count) != 3) { | |
4326 | /* Invalid format */ | |
4327 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
4328 | p); | |
4329 | break; | |
4330 | } | |
4331 | } | |
4332 | p += count; | |
4333 | if (seg == pci_domain_nr(dev->bus) && | |
4334 | bus == dev->bus->number && | |
4335 | slot == PCI_SLOT(dev->devfn) && | |
4336 | func == PCI_FUNC(dev->devfn)) { | |
3c78bc61 | 4337 | if (align_order == -1) |
32a9a682 | 4338 | align = PAGE_SIZE; |
3c78bc61 | 4339 | else |
32a9a682 | 4340 | align = 1 << align_order; |
32a9a682 YS |
4341 | /* Found */ |
4342 | break; | |
4343 | } | |
4344 | if (*p != ';' && *p != ',') { | |
4345 | /* End of param or invalid format */ | |
4346 | break; | |
4347 | } | |
4348 | p++; | |
4349 | } | |
4350 | spin_unlock(&resource_alignment_lock); | |
4351 | return align; | |
4352 | } | |
4353 | ||
2069ecfb YL |
4354 | /* |
4355 | * This function disables memory decoding and releases memory resources | |
4356 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
4357 | * It also rounds up size to specified alignment. | |
4358 | * Later on, the kernel will assign page-aligned memory resource back | |
4359 | * to the device. | |
4360 | */ | |
4361 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
4362 | { | |
4363 | int i; | |
4364 | struct resource *r; | |
4365 | resource_size_t align, size; | |
4366 | u16 command; | |
4367 | ||
10c463a7 YL |
4368 | /* check if specified PCI is target device to reassign */ |
4369 | align = pci_specified_resource_alignment(dev); | |
4370 | if (!align) | |
2069ecfb YL |
4371 | return; |
4372 | ||
4373 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
4374 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
4375 | dev_warn(&dev->dev, | |
4376 | "Can't reassign resources to host bridge.\n"); | |
4377 | return; | |
4378 | } | |
4379 | ||
4380 | dev_info(&dev->dev, | |
4381 | "Disabling memory decoding and releasing memory resources.\n"); | |
4382 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
4383 | command &= ~PCI_COMMAND_MEMORY; | |
4384 | pci_write_config_word(dev, PCI_COMMAND, command); | |
4385 | ||
2069ecfb YL |
4386 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { |
4387 | r = &dev->resource[i]; | |
4388 | if (!(r->flags & IORESOURCE_MEM)) | |
4389 | continue; | |
4390 | size = resource_size(r); | |
4391 | if (size < align) { | |
4392 | size = align; | |
4393 | dev_info(&dev->dev, | |
4394 | "Rounding up size of resource #%d to %#llx.\n", | |
4395 | i, (unsigned long long)size); | |
4396 | } | |
bd064f0a | 4397 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
4398 | r->end = size - 1; |
4399 | r->start = 0; | |
4400 | } | |
4401 | /* Need to disable bridge's resource window, | |
4402 | * to enable the kernel to reassign new resource | |
4403 | * window later on. | |
4404 | */ | |
4405 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
4406 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
4407 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
4408 | r = &dev->resource[i]; | |
4409 | if (!(r->flags & IORESOURCE_MEM)) | |
4410 | continue; | |
bd064f0a | 4411 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
4412 | r->end = resource_size(r) - 1; |
4413 | r->start = 0; | |
4414 | } | |
4415 | pci_disable_bridge_window(dev); | |
4416 | } | |
4417 | } | |
4418 | ||
9738abed | 4419 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
4420 | { |
4421 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
4422 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
4423 | spin_lock(&resource_alignment_lock); | |
4424 | strncpy(resource_alignment_param, buf, count); | |
4425 | resource_alignment_param[count] = '\0'; | |
4426 | spin_unlock(&resource_alignment_lock); | |
4427 | return count; | |
4428 | } | |
4429 | ||
9738abed | 4430 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
4431 | { |
4432 | size_t count; | |
4433 | spin_lock(&resource_alignment_lock); | |
4434 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
4435 | spin_unlock(&resource_alignment_lock); | |
4436 | return count; | |
4437 | } | |
4438 | ||
4439 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
4440 | { | |
4441 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
4442 | } | |
4443 | ||
4444 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
4445 | const char *buf, size_t count) | |
4446 | { | |
4447 | return pci_set_resource_alignment_param(buf, count); | |
4448 | } | |
4449 | ||
4450 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, | |
4451 | pci_resource_alignment_store); | |
4452 | ||
4453 | static int __init pci_resource_alignment_sysfs_init(void) | |
4454 | { | |
4455 | return bus_create_file(&pci_bus_type, | |
4456 | &bus_attr_resource_alignment); | |
4457 | } | |
32a9a682 YS |
4458 | late_initcall(pci_resource_alignment_sysfs_init); |
4459 | ||
15856ad5 | 4460 | static void pci_no_domains(void) |
32a2eea7 JG |
4461 | { |
4462 | #ifdef CONFIG_PCI_DOMAINS | |
4463 | pci_domains_supported = 0; | |
4464 | #endif | |
4465 | } | |
4466 | ||
41e5c0f8 LD |
4467 | #ifdef CONFIG_PCI_DOMAINS |
4468 | static atomic_t __domain_nr = ATOMIC_INIT(-1); | |
4469 | ||
4470 | int pci_get_new_domain_nr(void) | |
4471 | { | |
4472 | return atomic_inc_return(&__domain_nr); | |
4473 | } | |
4474 | #endif | |
4475 | ||
0ef5f8f6 | 4476 | /** |
642c92da | 4477 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
4478 | * |
4479 | * Returns 1 if we can access PCI extended config space (offsets | |
4480 | * greater than 0xff). This is the default implementation. Architecture | |
4481 | * implementations can override this. | |
4482 | */ | |
642c92da | 4483 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
4484 | { |
4485 | return 1; | |
4486 | } | |
4487 | ||
2d1c8618 BH |
4488 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
4489 | { | |
4490 | } | |
4491 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
4492 | ||
ad04d31e | 4493 | static int __init pci_setup(char *str) |
1da177e4 LT |
4494 | { |
4495 | while (str) { | |
4496 | char *k = strchr(str, ','); | |
4497 | if (k) | |
4498 | *k++ = 0; | |
4499 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
4500 | if (!strcmp(str, "nomsi")) { |
4501 | pci_no_msi(); | |
7f785763 RD |
4502 | } else if (!strcmp(str, "noaer")) { |
4503 | pci_no_aer(); | |
b55438fd YL |
4504 | } else if (!strncmp(str, "realloc=", 8)) { |
4505 | pci_realloc_get_opt(str + 8); | |
f483d392 | 4506 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 4507 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
4508 | } else if (!strcmp(str, "nodomains")) { |
4509 | pci_no_domains(); | |
6748dcc2 RW |
4510 | } else if (!strncmp(str, "noari", 5)) { |
4511 | pcie_ari_disabled = true; | |
4516a618 AN |
4512 | } else if (!strncmp(str, "cbiosize=", 9)) { |
4513 | pci_cardbus_io_size = memparse(str + 9, &str); | |
4514 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
4515 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
4516 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
4517 | pci_set_resource_alignment_param(str + 19, | |
4518 | strlen(str + 19)); | |
43c16408 AP |
4519 | } else if (!strncmp(str, "ecrc=", 5)) { |
4520 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
4521 | } else if (!strncmp(str, "hpiosize=", 9)) { |
4522 | pci_hotplug_io_size = memparse(str + 9, &str); | |
4523 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
4524 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
5f39e670 JM |
4525 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
4526 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
4527 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
4528 | pcie_bus_config = PCIE_BUS_SAFE; | |
4529 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
4530 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
4531 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
4532 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
4533 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
4534 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
4535 | } else { |
4536 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
4537 | str); | |
4538 | } | |
1da177e4 LT |
4539 | } |
4540 | str = k; | |
4541 | } | |
0637a70a | 4542 | return 0; |
1da177e4 | 4543 | } |
0637a70a | 4544 | early_param("pci", pci_setup); |