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b64333ce RJ |
1 | /* |
2 | * Copyright (C) 2014-2015 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation version 2. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
afc8c78d PK |
13 | * This file contains the Broadcom Iproc GPIO driver that supports 3 |
14 | * GPIO controllers on Iproc including the ASIU GPIO controller, the | |
b64333ce RJ |
15 | * chipCommonG GPIO controller, and the always-on GPIO controller. Basic |
16 | * PINCONF such as bias pull up/down, and drive strength are also supported | |
17 | * in this driver. | |
18 | * | |
afc8c78d PK |
19 | * It provides the functionality where pins from the GPIO can be |
20 | * individually muxed to GPIO function, if individual pad | |
21 | * configuration is supported, through the interaction with respective | |
22 | * SoCs IOMUX controller. | |
b64333ce RJ |
23 | */ |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/gpio.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/of_device.h> | |
32 | #include <linux/of_irq.h> | |
33 | #include <linux/pinctrl/pinctrl.h> | |
b64333ce RJ |
34 | #include <linux/pinctrl/pinconf.h> |
35 | #include <linux/pinctrl/pinconf-generic.h> | |
36 | ||
37 | #include "../pinctrl-utils.h" | |
38 | ||
afc8c78d PK |
39 | #define IPROC_GPIO_DATA_IN_OFFSET 0x00 |
40 | #define IPROC_GPIO_DATA_OUT_OFFSET 0x04 | |
41 | #define IPROC_GPIO_OUT_EN_OFFSET 0x08 | |
42 | #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c | |
43 | #define IPROC_GPIO_INT_DE_OFFSET 0x10 | |
44 | #define IPROC_GPIO_INT_EDGE_OFFSET 0x14 | |
45 | #define IPROC_GPIO_INT_MSK_OFFSET 0x18 | |
46 | #define IPROC_GPIO_INT_STAT_OFFSET 0x1c | |
47 | #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20 | |
48 | #define IPROC_GPIO_INT_CLR_OFFSET 0x24 | |
49 | #define IPROC_GPIO_PAD_RES_OFFSET 0x34 | |
50 | #define IPROC_GPIO_RES_EN_OFFSET 0x38 | |
b64333ce RJ |
51 | |
52 | /* drive strength control for ASIU GPIO */ | |
afc8c78d | 53 | #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 |
b64333ce RJ |
54 | |
55 | /* drive strength control for CCM/CRMU (AON) GPIO */ | |
afc8c78d | 56 | #define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00 |
b64333ce RJ |
57 | |
58 | #define GPIO_BANK_SIZE 0x200 | |
59 | #define NGPIOS_PER_BANK 32 | |
60 | #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) | |
61 | ||
afc8c78d PK |
62 | #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) |
63 | #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) | |
b64333ce RJ |
64 | |
65 | #define GPIO_DRV_STRENGTH_BIT_SHIFT 20 | |
66 | #define GPIO_DRV_STRENGTH_BITS 3 | |
67 | #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) | |
68 | ||
69 | /* | |
afc8c78d | 70 | * Iproc GPIO core |
b64333ce RJ |
71 | * |
72 | * @dev: pointer to device | |
afc8c78d PK |
73 | * @base: I/O register base for Iproc GPIO controller |
74 | * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that | |
b64333ce RJ |
75 | * has the PINCONF support implemented outside of the GPIO block |
76 | * @lock: lock to protect access to I/O registers | |
77 | * @gc: GPIO chip | |
78 | * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs | |
79 | * @pinmux_is_supported: flag to indicate this GPIO controller contains pins | |
80 | * that can be individually muxed to GPIO | |
81 | * @pctl: pointer to pinctrl_dev | |
82 | * @pctldesc: pinctrl descriptor | |
83 | */ | |
afc8c78d | 84 | struct iproc_gpio { |
b64333ce RJ |
85 | struct device *dev; |
86 | ||
87 | void __iomem *base; | |
88 | void __iomem *io_ctrl; | |
89 | ||
90 | spinlock_t lock; | |
91 | ||
92 | struct gpio_chip gc; | |
93 | unsigned num_banks; | |
94 | ||
95 | bool pinmux_is_supported; | |
96 | ||
97 | struct pinctrl_dev *pctl; | |
98 | struct pinctrl_desc pctldesc; | |
99 | }; | |
100 | ||
afc8c78d | 101 | static inline struct iproc_gpio *to_iproc_gpio(struct gpio_chip *gc) |
b64333ce | 102 | { |
afc8c78d | 103 | return container_of(gc, struct iproc_gpio, gc); |
b64333ce RJ |
104 | } |
105 | ||
106 | /* | |
107 | * Mapping from PINCONF pins to GPIO pins is 1-to-1 | |
108 | */ | |
afc8c78d | 109 | static inline unsigned iproc_pin_to_gpio(unsigned pin) |
b64333ce RJ |
110 | { |
111 | return pin; | |
112 | } | |
113 | ||
114 | /** | |
afc8c78d PK |
115 | * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a |
116 | * Iproc GPIO register | |
b64333ce | 117 | * |
afc8c78d | 118 | * @iproc_gpio: Iproc GPIO device |
b64333ce RJ |
119 | * @reg: register offset |
120 | * @gpio: GPIO pin | |
121 | * @set: set or clear | |
122 | */ | |
afc8c78d | 123 | static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, |
b64333ce RJ |
124 | unsigned gpio, bool set) |
125 | { | |
afc8c78d PK |
126 | unsigned int offset = IPROC_GPIO_REG(gpio, reg); |
127 | unsigned int shift = IPROC_GPIO_SHIFT(gpio); | |
b64333ce RJ |
128 | u32 val; |
129 | ||
130 | val = readl(chip->base + offset); | |
131 | if (set) | |
132 | val |= BIT(shift); | |
133 | else | |
134 | val &= ~BIT(shift); | |
135 | writel(val, chip->base + offset); | |
136 | } | |
137 | ||
afc8c78d | 138 | static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, |
b64333ce RJ |
139 | unsigned gpio) |
140 | { | |
afc8c78d PK |
141 | unsigned int offset = IPROC_GPIO_REG(gpio, reg); |
142 | unsigned int shift = IPROC_GPIO_SHIFT(gpio); | |
b64333ce RJ |
143 | |
144 | return !!(readl(chip->base + offset) & BIT(shift)); | |
145 | } | |
146 | ||
afc8c78d | 147 | static void iproc_gpio_irq_handler(struct irq_desc *desc) |
b64333ce RJ |
148 | { |
149 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); | |
afc8c78d | 150 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
151 | struct irq_chip *irq_chip = irq_desc_get_chip(desc); |
152 | int i, bit; | |
153 | ||
154 | chained_irq_enter(irq_chip, desc); | |
155 | ||
156 | /* go through the entire GPIO banks and handle all interrupts */ | |
157 | for (i = 0; i < chip->num_banks; i++) { | |
158 | unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + | |
afc8c78d | 159 | IPROC_GPIO_INT_MSTAT_OFFSET); |
b64333ce RJ |
160 | |
161 | for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { | |
162 | unsigned pin = NGPIOS_PER_BANK * i + bit; | |
163 | int child_irq = irq_find_mapping(gc->irqdomain, pin); | |
164 | ||
165 | /* | |
166 | * Clear the interrupt before invoking the | |
167 | * handler, so we do not leave any window | |
168 | */ | |
169 | writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + | |
afc8c78d | 170 | IPROC_GPIO_INT_CLR_OFFSET); |
b64333ce RJ |
171 | |
172 | generic_handle_irq(child_irq); | |
173 | } | |
174 | } | |
175 | ||
176 | chained_irq_exit(irq_chip, desc); | |
177 | } | |
178 | ||
179 | ||
afc8c78d | 180 | static void iproc_gpio_irq_ack(struct irq_data *d) |
b64333ce RJ |
181 | { |
182 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
afc8c78d | 183 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce | 184 | unsigned gpio = d->hwirq; |
afc8c78d PK |
185 | unsigned int offset = IPROC_GPIO_REG(gpio, |
186 | IPROC_GPIO_INT_CLR_OFFSET); | |
187 | unsigned int shift = IPROC_GPIO_SHIFT(gpio); | |
b64333ce RJ |
188 | u32 val = BIT(shift); |
189 | ||
190 | writel(val, chip->base + offset); | |
191 | } | |
192 | ||
193 | /** | |
afc8c78d | 194 | * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt |
b64333ce RJ |
195 | * |
196 | * @d: IRQ chip data | |
197 | * @unmask: mask/unmask GPIO interrupt | |
198 | */ | |
afc8c78d | 199 | static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask) |
b64333ce RJ |
200 | { |
201 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
afc8c78d | 202 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
203 | unsigned gpio = d->hwirq; |
204 | ||
afc8c78d | 205 | iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); |
b64333ce RJ |
206 | } |
207 | ||
afc8c78d | 208 | static void iproc_gpio_irq_mask(struct irq_data *d) |
b64333ce RJ |
209 | { |
210 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
afc8c78d | 211 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
212 | unsigned long flags; |
213 | ||
214 | spin_lock_irqsave(&chip->lock, flags); | |
afc8c78d | 215 | iproc_gpio_irq_set_mask(d, false); |
b64333ce RJ |
216 | spin_unlock_irqrestore(&chip->lock, flags); |
217 | } | |
218 | ||
afc8c78d | 219 | static void iproc_gpio_irq_unmask(struct irq_data *d) |
b64333ce RJ |
220 | { |
221 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
afc8c78d | 222 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
223 | unsigned long flags; |
224 | ||
225 | spin_lock_irqsave(&chip->lock, flags); | |
afc8c78d | 226 | iproc_gpio_irq_set_mask(d, true); |
b64333ce RJ |
227 | spin_unlock_irqrestore(&chip->lock, flags); |
228 | } | |
229 | ||
afc8c78d | 230 | static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
b64333ce RJ |
231 | { |
232 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
afc8c78d | 233 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
234 | unsigned gpio = d->hwirq; |
235 | bool level_triggered = false; | |
236 | bool dual_edge = false; | |
237 | bool rising_or_high = false; | |
238 | unsigned long flags; | |
239 | ||
240 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
241 | case IRQ_TYPE_EDGE_RISING: | |
242 | rising_or_high = true; | |
243 | break; | |
244 | ||
245 | case IRQ_TYPE_EDGE_FALLING: | |
246 | break; | |
247 | ||
248 | case IRQ_TYPE_EDGE_BOTH: | |
249 | dual_edge = true; | |
250 | break; | |
251 | ||
252 | case IRQ_TYPE_LEVEL_HIGH: | |
253 | level_triggered = true; | |
254 | rising_or_high = true; | |
255 | break; | |
256 | ||
257 | case IRQ_TYPE_LEVEL_LOW: | |
258 | level_triggered = true; | |
259 | break; | |
260 | ||
261 | default: | |
262 | dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", | |
263 | type); | |
264 | return -EINVAL; | |
265 | } | |
266 | ||
267 | spin_lock_irqsave(&chip->lock, flags); | |
afc8c78d | 268 | iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio, |
b64333ce | 269 | level_triggered); |
afc8c78d PK |
270 | iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); |
271 | iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, | |
b64333ce RJ |
272 | rising_or_high); |
273 | spin_unlock_irqrestore(&chip->lock, flags); | |
274 | ||
275 | dev_dbg(chip->dev, | |
276 | "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n", | |
277 | gpio, level_triggered, dual_edge, rising_or_high); | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
afc8c78d PK |
282 | static struct irq_chip iproc_gpio_irq_chip = { |
283 | .name = "bcm-iproc-gpio", | |
284 | .irq_ack = iproc_gpio_irq_ack, | |
285 | .irq_mask = iproc_gpio_irq_mask, | |
286 | .irq_unmask = iproc_gpio_irq_unmask, | |
287 | .irq_set_type = iproc_gpio_irq_set_type, | |
b64333ce RJ |
288 | }; |
289 | ||
290 | /* | |
afc8c78d | 291 | * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO |
b64333ce | 292 | */ |
afc8c78d | 293 | static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) |
b64333ce | 294 | { |
afc8c78d | 295 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
296 | unsigned gpio = gc->base + offset; |
297 | ||
afc8c78d | 298 | /* not all Iproc GPIO pins can be muxed individually */ |
b64333ce RJ |
299 | if (!chip->pinmux_is_supported) |
300 | return 0; | |
301 | ||
302 | return pinctrl_request_gpio(gpio); | |
303 | } | |
304 | ||
afc8c78d | 305 | static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) |
b64333ce | 306 | { |
afc8c78d | 307 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
308 | unsigned gpio = gc->base + offset; |
309 | ||
310 | if (!chip->pinmux_is_supported) | |
311 | return; | |
312 | ||
313 | pinctrl_free_gpio(gpio); | |
314 | } | |
315 | ||
afc8c78d | 316 | static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) |
b64333ce | 317 | { |
afc8c78d | 318 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
319 | unsigned long flags; |
320 | ||
321 | spin_lock_irqsave(&chip->lock, flags); | |
afc8c78d | 322 | iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false); |
b64333ce RJ |
323 | spin_unlock_irqrestore(&chip->lock, flags); |
324 | ||
325 | dev_dbg(chip->dev, "gpio:%u set input\n", gpio); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
afc8c78d | 330 | static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, |
b64333ce RJ |
331 | int val) |
332 | { | |
afc8c78d | 333 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
334 | unsigned long flags; |
335 | ||
336 | spin_lock_irqsave(&chip->lock, flags); | |
afc8c78d PK |
337 | iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true); |
338 | iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); | |
b64333ce RJ |
339 | spin_unlock_irqrestore(&chip->lock, flags); |
340 | ||
341 | dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
afc8c78d | 346 | static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) |
b64333ce | 347 | { |
afc8c78d | 348 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
b64333ce RJ |
349 | unsigned long flags; |
350 | ||
351 | spin_lock_irqsave(&chip->lock, flags); | |
afc8c78d | 352 | iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); |
b64333ce RJ |
353 | spin_unlock_irqrestore(&chip->lock, flags); |
354 | ||
355 | dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); | |
356 | } | |
357 | ||
afc8c78d | 358 | static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) |
b64333ce | 359 | { |
afc8c78d PK |
360 | struct iproc_gpio *chip = to_iproc_gpio(gc); |
361 | unsigned int offset = IPROC_GPIO_REG(gpio, | |
362 | IPROC_GPIO_DATA_IN_OFFSET); | |
363 | unsigned int shift = IPROC_GPIO_SHIFT(gpio); | |
b64333ce RJ |
364 | |
365 | return !!(readl(chip->base + offset) & BIT(shift)); | |
366 | } | |
367 | ||
afc8c78d | 368 | static int iproc_get_groups_count(struct pinctrl_dev *pctldev) |
b64333ce RJ |
369 | { |
370 | return 1; | |
371 | } | |
372 | ||
373 | /* | |
374 | * Only one group: "gpio_grp", since this local pinctrl device only performs | |
375 | * GPIO specific PINCONF configurations | |
376 | */ | |
afc8c78d | 377 | static const char *iproc_get_group_name(struct pinctrl_dev *pctldev, |
b64333ce RJ |
378 | unsigned selector) |
379 | { | |
380 | return "gpio_grp"; | |
381 | } | |
382 | ||
afc8c78d PK |
383 | static const struct pinctrl_ops iproc_pctrl_ops = { |
384 | .get_groups_count = iproc_get_groups_count, | |
385 | .get_group_name = iproc_get_group_name, | |
b64333ce RJ |
386 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, |
387 | .dt_free_map = pinctrl_utils_dt_free_map, | |
388 | }; | |
389 | ||
afc8c78d | 390 | static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, |
b64333ce RJ |
391 | bool disable, bool pull_up) |
392 | { | |
393 | unsigned long flags; | |
394 | ||
395 | spin_lock_irqsave(&chip->lock, flags); | |
396 | ||
397 | if (disable) { | |
afc8c78d | 398 | iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false); |
b64333ce | 399 | } else { |
afc8c78d | 400 | iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, |
b64333ce | 401 | pull_up); |
afc8c78d | 402 | iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true); |
b64333ce RJ |
403 | } |
404 | ||
405 | spin_unlock_irqrestore(&chip->lock, flags); | |
406 | ||
407 | dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
afc8c78d | 412 | static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, |
b64333ce RJ |
413 | bool *disable, bool *pull_up) |
414 | { | |
415 | unsigned long flags; | |
416 | ||
417 | spin_lock_irqsave(&chip->lock, flags); | |
afc8c78d PK |
418 | *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); |
419 | *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); | |
b64333ce RJ |
420 | spin_unlock_irqrestore(&chip->lock, flags); |
421 | } | |
422 | ||
afc8c78d | 423 | static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, |
b64333ce RJ |
424 | unsigned strength) |
425 | { | |
426 | void __iomem *base; | |
427 | unsigned int i, offset, shift; | |
428 | u32 val; | |
429 | unsigned long flags; | |
430 | ||
431 | /* make sure drive strength is supported */ | |
432 | if (strength < 2 || strength > 16 || (strength % 2)) | |
433 | return -ENOTSUPP; | |
434 | ||
435 | if (chip->io_ctrl) { | |
436 | base = chip->io_ctrl; | |
afc8c78d | 437 | offset = IPROC_GPIO_DRV0_CTRL_OFFSET; |
b64333ce RJ |
438 | } else { |
439 | base = chip->base; | |
afc8c78d PK |
440 | offset = IPROC_GPIO_REG(gpio, |
441 | IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); | |
b64333ce RJ |
442 | } |
443 | ||
afc8c78d | 444 | shift = IPROC_GPIO_SHIFT(gpio); |
b64333ce RJ |
445 | |
446 | dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, | |
447 | strength); | |
448 | ||
449 | spin_lock_irqsave(&chip->lock, flags); | |
450 | strength = (strength / 2) - 1; | |
451 | for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { | |
452 | val = readl(base + offset); | |
453 | val &= ~BIT(shift); | |
454 | val |= ((strength >> i) & 0x1) << shift; | |
455 | writel(val, base + offset); | |
456 | offset += 4; | |
457 | } | |
458 | spin_unlock_irqrestore(&chip->lock, flags); | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
afc8c78d | 463 | static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, |
b64333ce RJ |
464 | u16 *strength) |
465 | { | |
466 | void __iomem *base; | |
467 | unsigned int i, offset, shift; | |
468 | u32 val; | |
469 | unsigned long flags; | |
470 | ||
471 | if (chip->io_ctrl) { | |
472 | base = chip->io_ctrl; | |
afc8c78d | 473 | offset = IPROC_GPIO_DRV0_CTRL_OFFSET; |
b64333ce RJ |
474 | } else { |
475 | base = chip->base; | |
afc8c78d PK |
476 | offset = IPROC_GPIO_REG(gpio, |
477 | IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); | |
b64333ce RJ |
478 | } |
479 | ||
afc8c78d | 480 | shift = IPROC_GPIO_SHIFT(gpio); |
b64333ce RJ |
481 | |
482 | spin_lock_irqsave(&chip->lock, flags); | |
483 | *strength = 0; | |
484 | for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { | |
485 | val = readl(base + offset) & BIT(shift); | |
486 | val >>= shift; | |
487 | *strength += (val << i); | |
488 | offset += 4; | |
489 | } | |
490 | ||
491 | /* convert to mA */ | |
492 | *strength = (*strength + 1) * 2; | |
493 | spin_unlock_irqrestore(&chip->lock, flags); | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
afc8c78d | 498 | static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
b64333ce RJ |
499 | unsigned long *config) |
500 | { | |
afc8c78d | 501 | struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); |
b64333ce | 502 | enum pin_config_param param = pinconf_to_config_param(*config); |
afc8c78d | 503 | unsigned gpio = iproc_pin_to_gpio(pin); |
b64333ce RJ |
504 | u16 arg; |
505 | bool disable, pull_up; | |
506 | int ret; | |
507 | ||
508 | switch (param) { | |
509 | case PIN_CONFIG_BIAS_DISABLE: | |
afc8c78d | 510 | iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); |
b64333ce RJ |
511 | if (disable) |
512 | return 0; | |
513 | else | |
514 | return -EINVAL; | |
515 | ||
516 | case PIN_CONFIG_BIAS_PULL_UP: | |
afc8c78d | 517 | iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); |
b64333ce RJ |
518 | if (!disable && pull_up) |
519 | return 0; | |
520 | else | |
521 | return -EINVAL; | |
522 | ||
523 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
afc8c78d | 524 | iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); |
b64333ce RJ |
525 | if (!disable && !pull_up) |
526 | return 0; | |
527 | else | |
528 | return -EINVAL; | |
529 | ||
530 | case PIN_CONFIG_DRIVE_STRENGTH: | |
afc8c78d | 531 | ret = iproc_gpio_get_strength(chip, gpio, &arg); |
b64333ce RJ |
532 | if (ret) |
533 | return ret; | |
534 | else | |
535 | *config = pinconf_to_config_packed(param, arg); | |
536 | ||
537 | return 0; | |
538 | ||
539 | default: | |
540 | return -ENOTSUPP; | |
541 | } | |
542 | ||
543 | return -ENOTSUPP; | |
544 | } | |
545 | ||
afc8c78d | 546 | static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
b64333ce RJ |
547 | unsigned long *configs, unsigned num_configs) |
548 | { | |
afc8c78d | 549 | struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); |
b64333ce RJ |
550 | enum pin_config_param param; |
551 | u16 arg; | |
afc8c78d | 552 | unsigned i, gpio = iproc_pin_to_gpio(pin); |
b64333ce RJ |
553 | int ret = -ENOTSUPP; |
554 | ||
555 | for (i = 0; i < num_configs; i++) { | |
556 | param = pinconf_to_config_param(configs[i]); | |
557 | arg = pinconf_to_config_argument(configs[i]); | |
558 | ||
559 | switch (param) { | |
560 | case PIN_CONFIG_BIAS_DISABLE: | |
afc8c78d | 561 | ret = iproc_gpio_set_pull(chip, gpio, true, false); |
b64333ce RJ |
562 | if (ret < 0) |
563 | goto out; | |
564 | break; | |
565 | ||
566 | case PIN_CONFIG_BIAS_PULL_UP: | |
afc8c78d | 567 | ret = iproc_gpio_set_pull(chip, gpio, false, true); |
b64333ce RJ |
568 | if (ret < 0) |
569 | goto out; | |
570 | break; | |
571 | ||
572 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
afc8c78d | 573 | ret = iproc_gpio_set_pull(chip, gpio, false, false); |
b64333ce RJ |
574 | if (ret < 0) |
575 | goto out; | |
576 | break; | |
577 | ||
578 | case PIN_CONFIG_DRIVE_STRENGTH: | |
afc8c78d | 579 | ret = iproc_gpio_set_strength(chip, gpio, arg); |
b64333ce RJ |
580 | if (ret < 0) |
581 | goto out; | |
582 | break; | |
583 | ||
584 | default: | |
585 | dev_err(chip->dev, "invalid configuration\n"); | |
586 | return -ENOTSUPP; | |
587 | } | |
588 | } /* for each config */ | |
589 | ||
590 | out: | |
591 | return ret; | |
592 | } | |
593 | ||
afc8c78d | 594 | static const struct pinconf_ops iproc_pconf_ops = { |
b64333ce | 595 | .is_generic = true, |
afc8c78d PK |
596 | .pin_config_get = iproc_pin_config_get, |
597 | .pin_config_set = iproc_pin_config_set, | |
b64333ce RJ |
598 | }; |
599 | ||
b64333ce | 600 | /* |
afc8c78d | 601 | * Iproc GPIO controller supports some PINCONF related configurations such as |
b64333ce RJ |
602 | * pull up, pull down, and drive strength, when the pin is configured to GPIO |
603 | * | |
604 | * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the | |
605 | * local GPIO pins | |
606 | */ | |
afc8c78d | 607 | static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) |
b64333ce RJ |
608 | { |
609 | struct pinctrl_desc *pctldesc = &chip->pctldesc; | |
610 | struct pinctrl_pin_desc *pins; | |
611 | struct gpio_chip *gc = &chip->gc; | |
612 | int i; | |
613 | ||
614 | pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); | |
615 | if (!pins) | |
616 | return -ENOMEM; | |
617 | ||
618 | for (i = 0; i < gc->ngpio; i++) { | |
619 | pins[i].number = i; | |
620 | pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, | |
621 | "gpio-%d", i); | |
622 | if (!pins[i].name) | |
623 | return -ENOMEM; | |
624 | } | |
625 | ||
626 | pctldesc->name = dev_name(chip->dev); | |
afc8c78d | 627 | pctldesc->pctlops = &iproc_pctrl_ops; |
b64333ce RJ |
628 | pctldesc->pins = pins; |
629 | pctldesc->npins = gc->ngpio; | |
afc8c78d | 630 | pctldesc->confops = &iproc_pconf_ops; |
b64333ce RJ |
631 | |
632 | chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); | |
323de9ef | 633 | if (IS_ERR(chip->pctl)) { |
b64333ce | 634 | dev_err(chip->dev, "unable to register pinctrl device\n"); |
323de9ef | 635 | return PTR_ERR(chip->pctl); |
b64333ce RJ |
636 | } |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
afc8c78d | 641 | static void iproc_gpio_unregister_pinconf(struct cygnus_gpio *chip) |
b64333ce | 642 | { |
f10a2585 | 643 | pinctrl_unregister(chip->pctl); |
b64333ce RJ |
644 | } |
645 | ||
afc8c78d | 646 | static const struct of_device_id iproc_gpio_of_match[] = { |
e1aaaf3f PK |
647 | { .compatible = "brcm,cygnus-ccm-gpio" }, |
648 | { .compatible = "brcm,cygnus-asiu-gpio" }, | |
649 | { .compatible = "brcm,cygnus-crmu-gpio" }, | |
462de629 | 650 | { .compatible = "brcm,iproc-gpio" }, |
e1aaaf3f | 651 | { } |
b64333ce RJ |
652 | }; |
653 | ||
afc8c78d | 654 | static int iproc_gpio_probe(struct platform_device *pdev) |
b64333ce RJ |
655 | { |
656 | struct device *dev = &pdev->dev; | |
657 | struct resource *res; | |
afc8c78d | 658 | struct iproc_gpio *chip; |
b64333ce RJ |
659 | struct gpio_chip *gc; |
660 | u32 ngpios; | |
661 | int irq, ret; | |
b64333ce RJ |
662 | |
663 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); | |
664 | if (!chip) | |
665 | return -ENOMEM; | |
666 | ||
667 | chip->dev = dev; | |
668 | platform_set_drvdata(pdev, chip); | |
669 | ||
670 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
671 | chip->base = devm_ioremap_resource(dev, res); | |
672 | if (IS_ERR(chip->base)) { | |
673 | dev_err(dev, "unable to map I/O memory\n"); | |
674 | return PTR_ERR(chip->base); | |
675 | } | |
676 | ||
677 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
678 | if (res) { | |
679 | chip->io_ctrl = devm_ioremap_resource(dev, res); | |
680 | if (IS_ERR(chip->io_ctrl)) { | |
681 | dev_err(dev, "unable to map I/O memory\n"); | |
682 | return PTR_ERR(chip->io_ctrl); | |
683 | } | |
684 | } | |
685 | ||
e1aaaf3f PK |
686 | if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { |
687 | dev_err(&pdev->dev, "missing ngpios DT property\n"); | |
688 | return -ENODEV; | |
689 | } | |
690 | ||
b64333ce RJ |
691 | spin_lock_init(&chip->lock); |
692 | ||
693 | gc = &chip->gc; | |
694 | gc->base = -1; | |
695 | gc->ngpio = ngpios; | |
696 | chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; | |
697 | gc->label = dev_name(dev); | |
698 | gc->dev = dev; | |
699 | gc->of_node = dev->of_node; | |
afc8c78d PK |
700 | gc->request = iproc_gpio_request; |
701 | gc->free = iproc_gpio_free; | |
702 | gc->direction_input = iproc_gpio_direction_input; | |
703 | gc->direction_output = iproc_gpio_direction_output; | |
704 | gc->set = iproc_gpio_set; | |
705 | gc->get = iproc_gpio_get; | |
b64333ce | 706 | |
ea92211c PK |
707 | chip->pinmux_is_supported = of_property_read_bool(dev->of_node, |
708 | "gpio-ranges"); | |
709 | ||
b64333ce RJ |
710 | ret = gpiochip_add(gc); |
711 | if (ret < 0) { | |
712 | dev_err(dev, "unable to add GPIO chip\n"); | |
713 | return ret; | |
714 | } | |
715 | ||
afc8c78d | 716 | ret = iproc_gpio_register_pinconf(chip); |
b64333ce RJ |
717 | if (ret) { |
718 | dev_err(dev, "unable to register pinconf\n"); | |
719 | goto err_rm_gpiochip; | |
720 | } | |
721 | ||
722 | /* optional GPIO interrupt support */ | |
723 | irq = platform_get_irq(pdev, 0); | |
724 | if (irq) { | |
afc8c78d | 725 | ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0, |
b64333ce RJ |
726 | handle_simple_irq, IRQ_TYPE_NONE); |
727 | if (ret) { | |
728 | dev_err(dev, "no GPIO irqchip\n"); | |
729 | goto err_unregister_pinconf; | |
730 | } | |
731 | ||
afc8c78d PK |
732 | gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq, |
733 | iproc_gpio_irq_handler); | |
b64333ce RJ |
734 | } |
735 | ||
736 | return 0; | |
737 | ||
738 | err_unregister_pinconf: | |
afc8c78d | 739 | iproc_gpio_unregister_pinconf(chip); |
b64333ce RJ |
740 | |
741 | err_rm_gpiochip: | |
742 | gpiochip_remove(gc); | |
743 | ||
744 | return ret; | |
745 | } | |
746 | ||
afc8c78d | 747 | static struct platform_driver iproc_gpio_driver = { |
b64333ce | 748 | .driver = { |
afc8c78d PK |
749 | .name = "iproc-gpio", |
750 | .of_match_table = iproc_gpio_of_match, | |
b64333ce | 751 | }, |
afc8c78d | 752 | .probe = iproc_gpio_probe, |
b64333ce RJ |
753 | }; |
754 | ||
afc8c78d | 755 | static int __init iproc_gpio_init(void) |
b64333ce | 756 | { |
afc8c78d | 757 | return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe); |
b64333ce | 758 | } |
afc8c78d | 759 | arch_initcall_sync(iproc_gpio_init); |