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28b665f6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6732ae5c JCPV |
2 | /* |
3 | * at91 pinctrl driver based on at91 pinmux core | |
4 | * | |
5 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
6732ae5c JCPV |
6 | */ |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/init.h> | |
6732ae5c JCPV |
11 | #include <linux/of.h> |
12 | #include <linux/of_device.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <linux/of_irq.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/interrupt.h> | |
6732ae5c | 17 | #include <linux/io.h> |
1c5fb66a | 18 | #include <linux/gpio/driver.h> |
6732ae5c JCPV |
19 | #include <linux/pinctrl/machine.h> |
20 | #include <linux/pinctrl/pinconf.h> | |
21 | #include <linux/pinctrl/pinctrl.h> | |
22 | #include <linux/pinctrl/pinmux.h> | |
23 | /* Since we request GPIOs from ourself */ | |
24 | #include <linux/pinctrl/consumer.h> | |
25 | ||
41dbf4a1 LJ |
26 | #include <soc/at91/pm.h> |
27 | ||
c654b6bf | 28 | #include "pinctrl-at91.h" |
6732ae5c JCPV |
29 | #include "core.h" |
30 | ||
94daf85e | 31 | #define MAX_GPIO_BANKS 5 |
6732ae5c JCPV |
32 | #define MAX_NB_GPIO_PER_BANK 32 |
33 | ||
34 | struct at91_pinctrl_mux_ops; | |
35 | ||
36 | struct at91_gpio_chip { | |
37 | struct gpio_chip chip; | |
38 | struct pinctrl_gpio_range range; | |
39 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
40 | int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ | |
41 | int pioc_virq; /* PIO bank Linux virtual interrupt */ | |
42 | int pioc_idx; /* PIO bank index */ | |
43 | void __iomem *regbase; /* PIO bank virtual address */ | |
44 | struct clk *clock; /* associated clock */ | |
f56b273c | 45 | const struct at91_pinctrl_mux_ops *ops; /* ops */ |
6732ae5c JCPV |
46 | }; |
47 | ||
6732ae5c JCPV |
48 | static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; |
49 | ||
50 | static int gpio_banks; | |
51 | ||
525fae21 | 52 | #define PULL_UP (1 << 0) |
6732ae5c | 53 | #define MULTI_DRIVE (1 << 1) |
7ebd7a3a JCPV |
54 | #define DEGLITCH (1 << 2) |
55 | #define PULL_DOWN (1 << 3) | |
56 | #define DIS_SCHMIT (1 << 4) | |
4334ac2d MR |
57 | #define DRIVE_STRENGTH_SHIFT 5 |
58 | #define DRIVE_STRENGTH_MASK 0x3 | |
59 | #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) | |
96bb12de BB |
60 | #define OUTPUT (1 << 7) |
61 | #define OUTPUT_VAL_SHIFT 8 | |
62 | #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT) | |
64e21add CB |
63 | #define SLEWRATE_SHIFT 9 |
64 | #define SLEWRATE_MASK 0x1 | |
65 | #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT) | |
7ebd7a3a JCPV |
66 | #define DEBOUNCE (1 << 16) |
67 | #define DEBOUNCE_VAL_SHIFT 17 | |
68 | #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) | |
6732ae5c | 69 | |
aa78655d | 70 | /* |
4334ac2d MR |
71 | * These defines will translated the dt binding settings to our internal |
72 | * settings. They are not necessarily the same value as the register setting. | |
73 | * The actual drive strength current of low, medium and high must be looked up | |
74 | * from the corresponding device datasheet. This value is different for pins | |
75 | * that are even in the same banks. It is also dependent on VCC. | |
76 | * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive | |
77 | * strength when there is no dt config for it. | |
78 | */ | |
b67328e1 CB |
79 | enum drive_strength_bit { |
80 | DRIVE_STRENGTH_BIT_DEF, | |
81 | DRIVE_STRENGTH_BIT_LOW, | |
82 | DRIVE_STRENGTH_BIT_MED, | |
83 | DRIVE_STRENGTH_BIT_HI, | |
84 | }; | |
85 | ||
86 | #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \ | |
87 | DRIVE_STRENGTH_SHIFT) | |
4334ac2d | 88 | |
64e21add | 89 | enum slewrate_bit { |
64e21add | 90 | SLEWRATE_BIT_ENA, |
0b329285 | 91 | SLEWRATE_BIT_DIS, |
64e21add CB |
92 | }; |
93 | ||
94 | #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT) | |
95 | ||
6732ae5c JCPV |
96 | /** |
97 | * struct at91_pmx_func - describes AT91 pinmux functions | |
98 | * @name: the name of this specific function | |
99 | * @groups: corresponding pin groups | |
100 | * @ngroups: the number of groups | |
101 | */ | |
102 | struct at91_pmx_func { | |
103 | const char *name; | |
104 | const char **groups; | |
105 | unsigned ngroups; | |
106 | }; | |
107 | ||
108 | enum at91_mux { | |
109 | AT91_MUX_GPIO = 0, | |
110 | AT91_MUX_PERIPH_A = 1, | |
111 | AT91_MUX_PERIPH_B = 2, | |
112 | AT91_MUX_PERIPH_C = 3, | |
113 | AT91_MUX_PERIPH_D = 4, | |
114 | }; | |
115 | ||
116 | /** | |
117 | * struct at91_pmx_pin - describes an At91 pin mux | |
118 | * @bank: the bank of the pin | |
119 | * @pin: the pin number in the @bank | |
120 | * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. | |
121 | * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... | |
122 | */ | |
123 | struct at91_pmx_pin { | |
124 | uint32_t bank; | |
125 | uint32_t pin; | |
126 | enum at91_mux mux; | |
127 | unsigned long conf; | |
128 | }; | |
129 | ||
130 | /** | |
131 | * struct at91_pin_group - describes an At91 pin group | |
132 | * @name: the name of this specific pin group | |
133 | * @pins_conf: the mux mode for each pin in this group. The size of this | |
134 | * array is the same as pins. | |
135 | * @pins: an array of discrete physical pins used in this group, taken | |
136 | * from the driver-local pin enumeration space | |
137 | * @npins: the number of pins in this group array, i.e. the number of | |
138 | * elements in .pins so we can iterate over that array | |
139 | */ | |
140 | struct at91_pin_group { | |
141 | const char *name; | |
142 | struct at91_pmx_pin *pins_conf; | |
143 | unsigned int *pins; | |
144 | unsigned npins; | |
145 | }; | |
146 | ||
147 | /** | |
c2eb9e7f | 148 | * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group |
6732ae5c JCPV |
149 | * on new IP with support for periph C and D the way to mux in |
150 | * periph A and B has changed | |
151 | * So provide the right call back | |
152 | * if not present means the IP does not support it | |
153 | * @get_periph: return the periph mode configured | |
154 | * @mux_A_periph: mux as periph A | |
155 | * @mux_B_periph: mux as periph B | |
156 | * @mux_C_periph: mux as periph C | |
157 | * @mux_D_periph: mux as periph D | |
7ebd7a3a JCPV |
158 | * @get_deglitch: get deglitch status |
159 | * @set_deglitch: enable/disable deglitch | |
160 | * @get_debounce: get debounce status | |
161 | * @set_debounce: enable/disable debounce | |
162 | * @get_pulldown: get pulldown status | |
163 | * @set_pulldown: enable/disable pulldown | |
164 | * @get_schmitt_trig: get schmitt trigger status | |
165 | * @disable_schmitt_trig: disable schmitt trigger | |
aa78655d LJ |
166 | * @get_drivestrength: get driver strength |
167 | * @set_drivestrength: set driver strength | |
168 | * @get_slewrate: get slew rate | |
169 | * @set_slewrate: set slew rate | |
6732ae5c JCPV |
170 | * @irq_type: return irq type |
171 | */ | |
172 | struct at91_pinctrl_mux_ops { | |
173 | enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); | |
174 | void (*mux_A_periph)(void __iomem *pio, unsigned mask); | |
175 | void (*mux_B_periph)(void __iomem *pio, unsigned mask); | |
176 | void (*mux_C_periph)(void __iomem *pio, unsigned mask); | |
177 | void (*mux_D_periph)(void __iomem *pio, unsigned mask); | |
7ebd7a3a | 178 | bool (*get_deglitch)(void __iomem *pio, unsigned pin); |
77966ad7 | 179 | void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); |
7ebd7a3a | 180 | bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); |
77966ad7 | 181 | void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); |
7ebd7a3a | 182 | bool (*get_pulldown)(void __iomem *pio, unsigned pin); |
77966ad7 | 183 | void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); |
7ebd7a3a JCPV |
184 | bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); |
185 | void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); | |
4334ac2d MR |
186 | unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); |
187 | void (*set_drivestrength)(void __iomem *pio, unsigned pin, | |
188 | u32 strength); | |
64e21add CB |
189 | unsigned (*get_slewrate)(void __iomem *pio, unsigned pin); |
190 | void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate); | |
6732ae5c JCPV |
191 | /* irq */ |
192 | int (*irq_type)(struct irq_data *d, unsigned type); | |
193 | }; | |
194 | ||
195 | static int gpio_irq_type(struct irq_data *d, unsigned type); | |
196 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type); | |
197 | ||
198 | struct at91_pinctrl { | |
199 | struct device *dev; | |
200 | struct pinctrl_dev *pctl; | |
201 | ||
a0b957f3 | 202 | int nactive_banks; |
6732ae5c JCPV |
203 | |
204 | uint32_t *mux_mask; | |
205 | int nmux; | |
206 | ||
207 | struct at91_pmx_func *functions; | |
208 | int nfunctions; | |
209 | ||
210 | struct at91_pin_group *groups; | |
211 | int ngroups; | |
212 | ||
f56b273c | 213 | const struct at91_pinctrl_mux_ops *ops; |
6732ae5c JCPV |
214 | }; |
215 | ||
56411f3c | 216 | static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name( |
6732ae5c JCPV |
217 | const struct at91_pinctrl *info, |
218 | const char *name) | |
219 | { | |
220 | const struct at91_pin_group *grp = NULL; | |
221 | int i; | |
222 | ||
223 | for (i = 0; i < info->ngroups; i++) { | |
224 | if (strcmp(info->groups[i].name, name)) | |
225 | continue; | |
226 | ||
227 | grp = &info->groups[i]; | |
228 | dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); | |
229 | break; | |
230 | } | |
231 | ||
232 | return grp; | |
233 | } | |
234 | ||
235 | static int at91_get_groups_count(struct pinctrl_dev *pctldev) | |
236 | { | |
237 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
238 | ||
239 | return info->ngroups; | |
240 | } | |
241 | ||
242 | static const char *at91_get_group_name(struct pinctrl_dev *pctldev, | |
243 | unsigned selector) | |
244 | { | |
245 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
246 | ||
247 | return info->groups[selector].name; | |
248 | } | |
249 | ||
250 | static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
251 | const unsigned **pins, | |
252 | unsigned *npins) | |
253 | { | |
254 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
255 | ||
256 | if (selector >= info->ngroups) | |
257 | return -EINVAL; | |
258 | ||
259 | *pins = info->groups[selector].pins; | |
260 | *npins = info->groups[selector].npins; | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
266 | unsigned offset) | |
267 | { | |
268 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
269 | } | |
270 | ||
271 | static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, | |
272 | struct device_node *np, | |
273 | struct pinctrl_map **map, unsigned *num_maps) | |
274 | { | |
275 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
276 | const struct at91_pin_group *grp; | |
277 | struct pinctrl_map *new_map; | |
278 | struct device_node *parent; | |
279 | int map_num = 1; | |
280 | int i; | |
6732ae5c JCPV |
281 | |
282 | /* | |
61e310a1 | 283 | * first find the group of this node and check if we need to create |
6732ae5c JCPV |
284 | * config maps for pins |
285 | */ | |
286 | grp = at91_pinctrl_find_group_by_name(info, np->name); | |
287 | if (!grp) { | |
94f4e54c RH |
288 | dev_err(info->dev, "unable to find group for node %pOFn\n", |
289 | np); | |
6732ae5c JCPV |
290 | return -EINVAL; |
291 | } | |
292 | ||
293 | map_num += grp->npins; | |
a86854d0 KC |
294 | new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), |
295 | GFP_KERNEL); | |
6732ae5c JCPV |
296 | if (!new_map) |
297 | return -ENOMEM; | |
298 | ||
299 | *map = new_map; | |
300 | *num_maps = map_num; | |
301 | ||
302 | /* create mux map */ | |
303 | parent = of_get_parent(np); | |
304 | if (!parent) { | |
c62b2b34 | 305 | devm_kfree(pctldev->dev, new_map); |
6732ae5c JCPV |
306 | return -EINVAL; |
307 | } | |
308 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
309 | new_map[0].data.mux.function = parent->name; | |
310 | new_map[0].data.mux.group = np->name; | |
311 | of_node_put(parent); | |
312 | ||
313 | /* create config map */ | |
314 | new_map++; | |
315 | for (i = 0; i < grp->npins; i++) { | |
6732ae5c JCPV |
316 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; |
317 | new_map[i].data.configs.group_or_pin = | |
318 | pin_get_name(pctldev, grp->pins[i]); | |
319 | new_map[i].data.configs.configs = &grp->pins_conf[i].conf; | |
320 | new_map[i].data.configs.num_configs = 1; | |
321 | } | |
322 | ||
323 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
324 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | static void at91_dt_free_map(struct pinctrl_dev *pctldev, | |
330 | struct pinctrl_map *map, unsigned num_maps) | |
331 | { | |
332 | } | |
333 | ||
022ab148 | 334 | static const struct pinctrl_ops at91_pctrl_ops = { |
6732ae5c JCPV |
335 | .get_groups_count = at91_get_groups_count, |
336 | .get_group_name = at91_get_group_name, | |
337 | .get_group_pins = at91_get_group_pins, | |
338 | .pin_dbg_show = at91_pin_dbg_show, | |
339 | .dt_node_to_map = at91_dt_node_to_map, | |
340 | .dt_free_map = at91_dt_free_map, | |
341 | }; | |
342 | ||
3c93600d | 343 | static void __iomem *pin_to_controller(struct at91_pinctrl *info, |
6732ae5c JCPV |
344 | unsigned int bank) |
345 | { | |
1ab36387 DD |
346 | if (!gpio_chips[bank]) |
347 | return NULL; | |
348 | ||
6732ae5c JCPV |
349 | return gpio_chips[bank]->regbase; |
350 | } | |
351 | ||
352 | static inline int pin_to_bank(unsigned pin) | |
353 | { | |
354 | return pin /= MAX_NB_GPIO_PER_BANK; | |
355 | } | |
356 | ||
357 | static unsigned pin_to_mask(unsigned int pin) | |
358 | { | |
359 | return 1 << pin; | |
360 | } | |
361 | ||
4334ac2d MR |
362 | static unsigned two_bit_pin_value_shift_amount(unsigned int pin) |
363 | { | |
364 | /* return the shift value for a pin for "two bit" per pin registers, | |
365 | * i.e. drive strength */ | |
366 | return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) | |
367 | ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); | |
368 | } | |
369 | ||
370 | static unsigned sama5d3_get_drive_register(unsigned int pin) | |
371 | { | |
372 | /* drive strength is split between two registers | |
373 | * with two bits per pin */ | |
374 | return (pin >= MAX_NB_GPIO_PER_BANK/2) | |
375 | ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; | |
376 | } | |
377 | ||
378 | static unsigned at91sam9x5_get_drive_register(unsigned int pin) | |
379 | { | |
380 | /* drive strength is split between two registers | |
381 | * with two bits per pin */ | |
382 | return (pin >= MAX_NB_GPIO_PER_BANK/2) | |
383 | ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; | |
384 | } | |
385 | ||
6732ae5c JCPV |
386 | static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) |
387 | { | |
388 | writel_relaxed(mask, pio + PIO_IDR); | |
389 | } | |
390 | ||
391 | static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) | |
392 | { | |
05d3534a | 393 | return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); |
6732ae5c JCPV |
394 | } |
395 | ||
396 | static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) | |
397 | { | |
3d784273 WY |
398 | if (on) |
399 | writel_relaxed(mask, pio + PIO_PPDDR); | |
400 | ||
6732ae5c JCPV |
401 | writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); |
402 | } | |
403 | ||
96bb12de BB |
404 | static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val) |
405 | { | |
406 | *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1; | |
407 | return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1; | |
408 | } | |
409 | ||
410 | static void at91_mux_set_output(void __iomem *pio, unsigned int mask, | |
411 | bool is_on, bool val) | |
412 | { | |
413 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
414 | writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); | |
415 | } | |
416 | ||
6732ae5c JCPV |
417 | static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) |
418 | { | |
419 | return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; | |
420 | } | |
421 | ||
422 | static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) | |
423 | { | |
424 | writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); | |
425 | } | |
426 | ||
427 | static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) | |
428 | { | |
429 | writel_relaxed(mask, pio + PIO_ASR); | |
430 | } | |
431 | ||
432 | static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) | |
433 | { | |
434 | writel_relaxed(mask, pio + PIO_BSR); | |
435 | } | |
436 | ||
437 | static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) | |
438 | { | |
439 | ||
440 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, | |
441 | pio + PIO_ABCDSR1); | |
442 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
443 | pio + PIO_ABCDSR2); | |
444 | } | |
445 | ||
446 | static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) | |
447 | { | |
448 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, | |
449 | pio + PIO_ABCDSR1); | |
450 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
451 | pio + PIO_ABCDSR2); | |
452 | } | |
453 | ||
454 | static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) | |
455 | { | |
456 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); | |
457 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
458 | } | |
459 | ||
460 | static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) | |
461 | { | |
462 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); | |
463 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
464 | } | |
465 | ||
466 | static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) | |
467 | { | |
468 | unsigned select; | |
469 | ||
470 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
471 | return AT91_MUX_GPIO; | |
472 | ||
473 | select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); | |
474 | select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); | |
475 | ||
476 | return select + 1; | |
477 | } | |
478 | ||
479 | static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) | |
480 | { | |
481 | unsigned select; | |
482 | ||
483 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
484 | return AT91_MUX_GPIO; | |
485 | ||
486 | select = readl_relaxed(pio + PIO_ABSR) & mask; | |
487 | ||
488 | return select + 1; | |
489 | } | |
490 | ||
7ebd7a3a JCPV |
491 | static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) |
492 | { | |
d480239b | 493 | return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; |
7ebd7a3a JCPV |
494 | } |
495 | ||
496 | static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) | |
497 | { | |
d480239b | 498 | writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); |
7ebd7a3a JCPV |
499 | } |
500 | ||
c8dba02e BB |
501 | static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) |
502 | { | |
d480239b BD |
503 | if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) |
504 | return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); | |
c8dba02e BB |
505 | |
506 | return false; | |
507 | } | |
508 | ||
7ebd7a3a JCPV |
509 | static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) |
510 | { | |
511 | if (is_on) | |
d480239b | 512 | writel_relaxed(mask, pio + PIO_IFSCDR); |
7ebd7a3a JCPV |
513 | at91_mux_set_deglitch(pio, mask, is_on); |
514 | } | |
515 | ||
516 | static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) | |
517 | { | |
d480239b | 518 | *div = readl_relaxed(pio + PIO_SCDR); |
7ebd7a3a | 519 | |
d480239b BD |
520 | return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && |
521 | ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); | |
7ebd7a3a JCPV |
522 | } |
523 | ||
524 | static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, | |
525 | bool is_on, u32 div) | |
526 | { | |
527 | if (is_on) { | |
d480239b BD |
528 | writel_relaxed(mask, pio + PIO_IFSCER); |
529 | writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); | |
530 | writel_relaxed(mask, pio + PIO_IFER); | |
c8dba02e | 531 | } else |
d480239b | 532 | writel_relaxed(mask, pio + PIO_IFSCDR); |
7ebd7a3a JCPV |
533 | } |
534 | ||
535 | static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) | |
536 | { | |
d480239b | 537 | return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); |
7ebd7a3a JCPV |
538 | } |
539 | ||
540 | static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) | |
541 | { | |
3d784273 | 542 | if (is_on) |
d480239b | 543 | writel_relaxed(mask, pio + PIO_PUDR); |
3d784273 | 544 | |
d480239b | 545 | writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); |
7ebd7a3a JCPV |
546 | } |
547 | ||
548 | static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) | |
549 | { | |
d480239b | 550 | writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); |
7ebd7a3a JCPV |
551 | } |
552 | ||
553 | static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) | |
554 | { | |
d480239b | 555 | return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; |
7ebd7a3a JCPV |
556 | } |
557 | ||
4334ac2d MR |
558 | static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) |
559 | { | |
d480239b | 560 | unsigned tmp = readl_relaxed(reg); |
4334ac2d MR |
561 | |
562 | tmp = tmp >> two_bit_pin_value_shift_amount(pin); | |
563 | ||
564 | return tmp & DRIVE_STRENGTH_MASK; | |
565 | } | |
566 | ||
567 | static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, | |
568 | unsigned pin) | |
569 | { | |
570 | unsigned tmp = read_drive_strength(pio + | |
571 | sama5d3_get_drive_register(pin), pin); | |
572 | ||
573 | /* SAMA5 strength is 1:1 with our defines, | |
574 | * except 0 is equivalent to low per datasheet */ | |
575 | if (!tmp) | |
b67328e1 | 576 | tmp = DRIVE_STRENGTH_BIT_MSK(LOW); |
4334ac2d MR |
577 | |
578 | return tmp; | |
579 | } | |
580 | ||
581 | static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, | |
582 | unsigned pin) | |
583 | { | |
584 | unsigned tmp = read_drive_strength(pio + | |
585 | at91sam9x5_get_drive_register(pin), pin); | |
586 | ||
587 | /* strength is inverse in SAM9x5s hardware with the pinctrl defines | |
588 | * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ | |
b67328e1 | 589 | tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp; |
4334ac2d MR |
590 | |
591 | return tmp; | |
592 | } | |
593 | ||
42ef7557 CB |
594 | static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio, |
595 | unsigned pin) | |
596 | { | |
597 | unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); | |
598 | ||
599 | if (tmp & BIT(pin)) | |
600 | return DRIVE_STRENGTH_BIT_HI; | |
601 | ||
602 | return DRIVE_STRENGTH_BIT_LOW; | |
603 | } | |
604 | ||
64e21add CB |
605 | static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin) |
606 | { | |
607 | unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); | |
608 | ||
609 | if ((tmp & BIT(pin))) | |
610 | return SLEWRATE_BIT_ENA; | |
611 | ||
612 | return SLEWRATE_BIT_DIS; | |
613 | } | |
614 | ||
4334ac2d MR |
615 | static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) |
616 | { | |
d480239b | 617 | unsigned tmp = readl_relaxed(reg); |
4334ac2d MR |
618 | unsigned shift = two_bit_pin_value_shift_amount(pin); |
619 | ||
620 | tmp &= ~(DRIVE_STRENGTH_MASK << shift); | |
621 | tmp |= strength << shift; | |
622 | ||
d480239b | 623 | writel_relaxed(tmp, reg); |
4334ac2d MR |
624 | } |
625 | ||
626 | static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, | |
627 | u32 setting) | |
628 | { | |
629 | /* do nothing if setting is zero */ | |
630 | if (!setting) | |
631 | return; | |
632 | ||
633 | /* strength is 1 to 1 with setting for SAMA5 */ | |
634 | set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); | |
635 | } | |
636 | ||
637 | static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, | |
638 | u32 setting) | |
639 | { | |
640 | /* do nothing if setting is zero */ | |
641 | if (!setting) | |
642 | return; | |
643 | ||
644 | /* strength is inverse on SAM9x5s with our defines | |
645 | * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ | |
b67328e1 | 646 | setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting; |
4334ac2d MR |
647 | |
648 | set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, | |
649 | setting); | |
650 | } | |
651 | ||
42ef7557 CB |
652 | static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin, |
653 | u32 setting) | |
654 | { | |
655 | unsigned int tmp; | |
656 | ||
657 | if (setting <= DRIVE_STRENGTH_BIT_DEF || | |
658 | setting == DRIVE_STRENGTH_BIT_MED || | |
659 | setting > DRIVE_STRENGTH_BIT_HI) | |
660 | return; | |
661 | ||
662 | tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); | |
663 | ||
664 | /* Strength is 0: low, 1: hi */ | |
665 | if (setting == DRIVE_STRENGTH_BIT_LOW) | |
666 | tmp &= ~BIT(pin); | |
667 | else | |
668 | tmp |= BIT(pin); | |
669 | ||
670 | writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1); | |
671 | } | |
672 | ||
64e21add CB |
673 | static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, |
674 | u32 setting) | |
675 | { | |
676 | unsigned int tmp; | |
677 | ||
0b329285 | 678 | if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS) |
64e21add CB |
679 | return; |
680 | ||
681 | tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); | |
682 | ||
683 | if (setting == SLEWRATE_BIT_DIS) | |
684 | tmp &= ~BIT(pin); | |
685 | else | |
686 | tmp |= BIT(pin); | |
687 | ||
688 | writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR); | |
689 | } | |
690 | ||
f56b273c | 691 | static const struct at91_pinctrl_mux_ops at91rm9200_ops = { |
6732ae5c JCPV |
692 | .get_periph = at91_mux_get_periph, |
693 | .mux_A_periph = at91_mux_set_A_periph, | |
694 | .mux_B_periph = at91_mux_set_B_periph, | |
7ebd7a3a JCPV |
695 | .get_deglitch = at91_mux_get_deglitch, |
696 | .set_deglitch = at91_mux_set_deglitch, | |
6732ae5c JCPV |
697 | .irq_type = gpio_irq_type, |
698 | }; | |
699 | ||
f56b273c | 700 | static const struct at91_pinctrl_mux_ops at91sam9x5_ops = { |
6732ae5c JCPV |
701 | .get_periph = at91_mux_pio3_get_periph, |
702 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
703 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
704 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
705 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
c8dba02e | 706 | .get_deglitch = at91_mux_pio3_get_deglitch, |
7ebd7a3a JCPV |
707 | .set_deglitch = at91_mux_pio3_set_deglitch, |
708 | .get_debounce = at91_mux_pio3_get_debounce, | |
709 | .set_debounce = at91_mux_pio3_set_debounce, | |
710 | .get_pulldown = at91_mux_pio3_get_pulldown, | |
711 | .set_pulldown = at91_mux_pio3_set_pulldown, | |
712 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, | |
713 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, | |
4334ac2d MR |
714 | .get_drivestrength = at91_mux_sam9x5_get_drivestrength, |
715 | .set_drivestrength = at91_mux_sam9x5_set_drivestrength, | |
716 | .irq_type = alt_gpio_irq_type, | |
717 | }; | |
718 | ||
42ef7557 CB |
719 | static const struct at91_pinctrl_mux_ops sam9x60_ops = { |
720 | .get_periph = at91_mux_pio3_get_periph, | |
721 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
722 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
723 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
724 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
725 | .get_deglitch = at91_mux_pio3_get_deglitch, | |
726 | .set_deglitch = at91_mux_pio3_set_deglitch, | |
727 | .get_debounce = at91_mux_pio3_get_debounce, | |
728 | .set_debounce = at91_mux_pio3_set_debounce, | |
729 | .get_pulldown = at91_mux_pio3_get_pulldown, | |
730 | .set_pulldown = at91_mux_pio3_set_pulldown, | |
731 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, | |
732 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, | |
733 | .get_drivestrength = at91_mux_sam9x60_get_drivestrength, | |
734 | .set_drivestrength = at91_mux_sam9x60_set_drivestrength, | |
64e21add CB |
735 | .get_slewrate = at91_mux_sam9x60_get_slewrate, |
736 | .set_slewrate = at91_mux_sam9x60_set_slewrate, | |
42ef7557 | 737 | .irq_type = alt_gpio_irq_type, |
42ef7557 CB |
738 | }; |
739 | ||
f56b273c | 740 | static const struct at91_pinctrl_mux_ops sama5d3_ops = { |
4334ac2d MR |
741 | .get_periph = at91_mux_pio3_get_periph, |
742 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
743 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
744 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
745 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
746 | .get_deglitch = at91_mux_pio3_get_deglitch, | |
747 | .set_deglitch = at91_mux_pio3_set_deglitch, | |
748 | .get_debounce = at91_mux_pio3_get_debounce, | |
749 | .set_debounce = at91_mux_pio3_set_debounce, | |
750 | .get_pulldown = at91_mux_pio3_get_pulldown, | |
751 | .set_pulldown = at91_mux_pio3_set_pulldown, | |
752 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, | |
753 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, | |
754 | .get_drivestrength = at91_mux_sama5d3_get_drivestrength, | |
755 | .set_drivestrength = at91_mux_sama5d3_set_drivestrength, | |
6732ae5c JCPV |
756 | .irq_type = alt_gpio_irq_type, |
757 | }; | |
758 | ||
759 | static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) | |
760 | { | |
761 | if (pin->mux) { | |
4b6fe45a | 762 | dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", |
6732ae5c JCPV |
763 | pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); |
764 | } else { | |
4b6fe45a | 765 | dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", |
6732ae5c JCPV |
766 | pin->bank + 'A', pin->pin, pin->conf); |
767 | } | |
768 | } | |
769 | ||
3c93600d | 770 | static int pin_check_config(struct at91_pinctrl *info, const char *name, |
6732ae5c JCPV |
771 | int index, const struct at91_pmx_pin *pin) |
772 | { | |
773 | int mux; | |
774 | ||
775 | /* check if it's a valid config */ | |
a0b957f3 | 776 | if (pin->bank >= gpio_banks) { |
6732ae5c | 777 | dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", |
a0b957f3 | 778 | name, index, pin->bank, gpio_banks); |
6732ae5c JCPV |
779 | return -EINVAL; |
780 | } | |
781 | ||
a0b957f3 JCPV |
782 | if (!gpio_chips[pin->bank]) { |
783 | dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", | |
784 | name, index, pin->bank); | |
785 | return -ENXIO; | |
786 | } | |
787 | ||
6732ae5c JCPV |
788 | if (pin->pin >= MAX_NB_GPIO_PER_BANK) { |
789 | dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", | |
790 | name, index, pin->pin, MAX_NB_GPIO_PER_BANK); | |
791 | return -EINVAL; | |
792 | } | |
793 | ||
794 | if (!pin->mux) | |
795 | return 0; | |
796 | ||
797 | mux = pin->mux - 1; | |
798 | ||
799 | if (mux >= info->nmux) { | |
800 | dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", | |
801 | name, index, mux, info->nmux); | |
802 | return -EINVAL; | |
803 | } | |
804 | ||
805 | if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { | |
806 | dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", | |
807 | name, index, mux, pin->bank + 'A', pin->pin); | |
808 | return -EINVAL; | |
809 | } | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) | |
815 | { | |
816 | writel_relaxed(mask, pio + PIO_PDR); | |
817 | } | |
818 | ||
819 | static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) | |
820 | { | |
821 | writel_relaxed(mask, pio + PIO_PER); | |
822 | writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); | |
823 | } | |
824 | ||
03e9f0ca LW |
825 | static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
826 | unsigned group) | |
6732ae5c JCPV |
827 | { |
828 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
829 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
830 | const struct at91_pmx_pin *pin; | |
831 | uint32_t npins = info->groups[group].npins; | |
832 | int i, ret; | |
833 | unsigned mask; | |
834 | void __iomem *pio; | |
835 | ||
836 | dev_dbg(info->dev, "enable function %s group %s\n", | |
837 | info->functions[selector].name, info->groups[group].name); | |
838 | ||
839 | /* first check that all the pins of the group are valid with a valid | |
61e310a1 | 840 | * parameter */ |
6732ae5c JCPV |
841 | for (i = 0; i < npins; i++) { |
842 | pin = &pins_conf[i]; | |
843 | ret = pin_check_config(info, info->groups[group].name, i, pin); | |
844 | if (ret) | |
845 | return ret; | |
846 | } | |
847 | ||
848 | for (i = 0; i < npins; i++) { | |
849 | pin = &pins_conf[i]; | |
850 | at91_pin_dbg(info->dev, pin); | |
851 | pio = pin_to_controller(info, pin->bank); | |
1ab36387 DD |
852 | |
853 | if (!pio) | |
854 | continue; | |
855 | ||
6732ae5c JCPV |
856 | mask = pin_to_mask(pin->pin); |
857 | at91_mux_disable_interrupt(pio, mask); | |
3c93600d | 858 | switch (pin->mux) { |
6732ae5c JCPV |
859 | case AT91_MUX_GPIO: |
860 | at91_mux_gpio_enable(pio, mask, 1); | |
861 | break; | |
862 | case AT91_MUX_PERIPH_A: | |
863 | info->ops->mux_A_periph(pio, mask); | |
864 | break; | |
865 | case AT91_MUX_PERIPH_B: | |
866 | info->ops->mux_B_periph(pio, mask); | |
867 | break; | |
868 | case AT91_MUX_PERIPH_C: | |
869 | if (!info->ops->mux_C_periph) | |
870 | return -EINVAL; | |
871 | info->ops->mux_C_periph(pio, mask); | |
872 | break; | |
873 | case AT91_MUX_PERIPH_D: | |
874 | if (!info->ops->mux_D_periph) | |
875 | return -EINVAL; | |
876 | info->ops->mux_D_periph(pio, mask); | |
877 | break; | |
878 | } | |
879 | if (pin->mux) | |
880 | at91_mux_gpio_disable(pio, mask); | |
881 | } | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
6732ae5c JCPV |
886 | static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) |
887 | { | |
888 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
889 | ||
890 | return info->nfunctions; | |
891 | } | |
892 | ||
893 | static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
894 | unsigned selector) | |
895 | { | |
896 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
897 | ||
898 | return info->functions[selector].name; | |
899 | } | |
900 | ||
901 | static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
902 | const char * const **groups, | |
903 | unsigned * const num_groups) | |
904 | { | |
905 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
906 | ||
907 | *groups = info->functions[selector].groups; | |
908 | *num_groups = info->functions[selector].ngroups; | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
f6f94f66 AL |
913 | static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, |
914 | struct pinctrl_gpio_range *range, | |
915 | unsigned offset) | |
6732ae5c JCPV |
916 | { |
917 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
918 | struct at91_gpio_chip *at91_chip; | |
919 | struct gpio_chip *chip; | |
920 | unsigned mask; | |
921 | ||
922 | if (!range) { | |
923 | dev_err(npct->dev, "invalid range\n"); | |
924 | return -EINVAL; | |
925 | } | |
926 | if (!range->gc) { | |
927 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
928 | return -EINVAL; | |
929 | } | |
930 | chip = range->gc; | |
370ea611 | 931 | at91_chip = gpiochip_get_data(chip); |
6732ae5c JCPV |
932 | |
933 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
934 | ||
935 | mask = 1 << (offset - chip->base); | |
936 | ||
937 | dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", | |
938 | offset, 'A' + range->id, offset - chip->base, mask); | |
939 | ||
940 | writel_relaxed(mask, at91_chip->regbase + PIO_PER); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
f6f94f66 AL |
945 | static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, |
946 | struct pinctrl_gpio_range *range, | |
947 | unsigned offset) | |
6732ae5c JCPV |
948 | { |
949 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
950 | ||
951 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
952 | /* Set the pin to some default state, GPIO is usually default */ | |
953 | } | |
954 | ||
022ab148 | 955 | static const struct pinmux_ops at91_pmx_ops = { |
6732ae5c JCPV |
956 | .get_functions_count = at91_pmx_get_funcs_count, |
957 | .get_function_name = at91_pmx_get_func_name, | |
958 | .get_function_groups = at91_pmx_get_groups, | |
03e9f0ca | 959 | .set_mux = at91_pmx_set, |
6732ae5c JCPV |
960 | .gpio_request_enable = at91_gpio_request_enable, |
961 | .gpio_disable_free = at91_gpio_disable_free, | |
962 | }; | |
963 | ||
964 | static int at91_pinconf_get(struct pinctrl_dev *pctldev, | |
965 | unsigned pin_id, unsigned long *config) | |
966 | { | |
967 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
968 | void __iomem *pio; | |
969 | unsigned pin; | |
7ebd7a3a | 970 | int div; |
96bb12de | 971 | bool out; |
6732ae5c | 972 | |
1292e693 AB |
973 | *config = 0; |
974 | dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); | |
6732ae5c | 975 | pio = pin_to_controller(info, pin_to_bank(pin_id)); |
1ab36387 DD |
976 | |
977 | if (!pio) | |
978 | return -EINVAL; | |
979 | ||
6732ae5c JCPV |
980 | pin = pin_id % MAX_NB_GPIO_PER_BANK; |
981 | ||
982 | if (at91_mux_get_multidrive(pio, pin)) | |
983 | *config |= MULTI_DRIVE; | |
984 | ||
985 | if (at91_mux_get_pullup(pio, pin)) | |
986 | *config |= PULL_UP; | |
987 | ||
7ebd7a3a JCPV |
988 | if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) |
989 | *config |= DEGLITCH; | |
990 | if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) | |
991 | *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); | |
992 | if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) | |
993 | *config |= PULL_DOWN; | |
994 | if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) | |
995 | *config |= DIS_SCHMIT; | |
4334ac2d MR |
996 | if (info->ops->get_drivestrength) |
997 | *config |= (info->ops->get_drivestrength(pio, pin) | |
998 | << DRIVE_STRENGTH_SHIFT); | |
64e21add CB |
999 | if (info->ops->get_slewrate) |
1000 | *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT); | |
96bb12de BB |
1001 | if (at91_mux_get_output(pio, pin, &out)) |
1002 | *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT); | |
7ebd7a3a | 1003 | |
6732ae5c JCPV |
1004 | return 0; |
1005 | } | |
1006 | ||
1007 | static int at91_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
1008 | unsigned pin_id, unsigned long *configs, |
1009 | unsigned num_configs) | |
6732ae5c JCPV |
1010 | { |
1011 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
1012 | unsigned mask; | |
1013 | void __iomem *pio; | |
03b054e9 SY |
1014 | int i; |
1015 | unsigned long config; | |
4334ac2d | 1016 | unsigned pin; |
03b054e9 SY |
1017 | |
1018 | for (i = 0; i < num_configs; i++) { | |
1019 | config = configs[i]; | |
1020 | ||
1021 | dev_dbg(info->dev, | |
1022 | "%s:%d, pin_id=%d, config=0x%lx", | |
1023 | __func__, __LINE__, pin_id, config); | |
1024 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
1ab36387 DD |
1025 | |
1026 | if (!pio) | |
1027 | return -EINVAL; | |
1028 | ||
4334ac2d MR |
1029 | pin = pin_id % MAX_NB_GPIO_PER_BANK; |
1030 | mask = pin_to_mask(pin); | |
03b054e9 SY |
1031 | |
1032 | if (config & PULL_UP && config & PULL_DOWN) | |
1033 | return -EINVAL; | |
1034 | ||
96bb12de BB |
1035 | at91_mux_set_output(pio, mask, config & OUTPUT, |
1036 | (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT); | |
03b054e9 SY |
1037 | at91_mux_set_pullup(pio, mask, config & PULL_UP); |
1038 | at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); | |
1039 | if (info->ops->set_deglitch) | |
1040 | info->ops->set_deglitch(pio, mask, config & DEGLITCH); | |
1041 | if (info->ops->set_debounce) | |
1042 | info->ops->set_debounce(pio, mask, config & DEBOUNCE, | |
7ebd7a3a | 1043 | (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); |
03b054e9 SY |
1044 | if (info->ops->set_pulldown) |
1045 | info->ops->set_pulldown(pio, mask, config & PULL_DOWN); | |
1046 | if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) | |
1047 | info->ops->disable_schmitt_trig(pio, mask); | |
4334ac2d MR |
1048 | if (info->ops->set_drivestrength) |
1049 | info->ops->set_drivestrength(pio, pin, | |
1050 | (config & DRIVE_STRENGTH) | |
1051 | >> DRIVE_STRENGTH_SHIFT); | |
64e21add CB |
1052 | if (info->ops->set_slewrate) |
1053 | info->ops->set_slewrate(pio, pin, | |
1054 | (config & SLEWRATE) >> SLEWRATE_SHIFT); | |
03b054e9 SY |
1055 | |
1056 | } /* for each config */ | |
7ebd7a3a | 1057 | |
6732ae5c JCPV |
1058 | return 0; |
1059 | } | |
1060 | ||
4d9b8a8e AB |
1061 | #define DBG_SHOW_FLAG(flag) do { \ |
1062 | if (config & flag) { \ | |
1063 | if (num_conf) \ | |
1064 | seq_puts(s, "|"); \ | |
1065 | seq_puts(s, #flag); \ | |
1066 | num_conf++; \ | |
1067 | } \ | |
1068 | } while (0) | |
1069 | ||
b67328e1 | 1070 | #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \ |
4334ac2d MR |
1071 | if ((config & mask) == flag) { \ |
1072 | if (num_conf) \ | |
1073 | seq_puts(s, "|"); \ | |
b67328e1 | 1074 | seq_puts(s, #name); \ |
4334ac2d MR |
1075 | num_conf++; \ |
1076 | } \ | |
1077 | } while (0) | |
1078 | ||
6732ae5c JCPV |
1079 | static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
1080 | struct seq_file *s, unsigned pin_id) | |
1081 | { | |
4d9b8a8e | 1082 | unsigned long config; |
445d2026 | 1083 | int val, num_conf = 0; |
4d9b8a8e | 1084 | |
445d2026 | 1085 | at91_pinconf_get(pctldev, pin_id, &config); |
4d9b8a8e AB |
1086 | |
1087 | DBG_SHOW_FLAG(MULTI_DRIVE); | |
1088 | DBG_SHOW_FLAG(PULL_UP); | |
1089 | DBG_SHOW_FLAG(PULL_DOWN); | |
1090 | DBG_SHOW_FLAG(DIS_SCHMIT); | |
1091 | DBG_SHOW_FLAG(DEGLITCH); | |
b67328e1 CB |
1092 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW), |
1093 | DRIVE_STRENGTH_LOW); | |
1094 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED), | |
1095 | DRIVE_STRENGTH_MED); | |
1096 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI), | |
1097 | DRIVE_STRENGTH_HI); | |
64e21add | 1098 | DBG_SHOW_FLAG(SLEWRATE); |
4d9b8a8e AB |
1099 | DBG_SHOW_FLAG(DEBOUNCE); |
1100 | if (config & DEBOUNCE) { | |
1101 | val = config >> DEBOUNCE_VAL_SHIFT; | |
1102 | seq_printf(s, "(%d)", val); | |
1103 | } | |
6732ae5c | 1104 | |
4d9b8a8e | 1105 | return; |
6732ae5c JCPV |
1106 | } |
1107 | ||
1108 | static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
1109 | struct seq_file *s, unsigned group) | |
1110 | { | |
1111 | } | |
1112 | ||
022ab148 | 1113 | static const struct pinconf_ops at91_pinconf_ops = { |
6732ae5c JCPV |
1114 | .pin_config_get = at91_pinconf_get, |
1115 | .pin_config_set = at91_pinconf_set, | |
1116 | .pin_config_dbg_show = at91_pinconf_dbg_show, | |
1117 | .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, | |
1118 | }; | |
1119 | ||
1120 | static struct pinctrl_desc at91_pinctrl_desc = { | |
1121 | .pctlops = &at91_pctrl_ops, | |
1122 | .pmxops = &at91_pmx_ops, | |
1123 | .confops = &at91_pinconf_ops, | |
1124 | .owner = THIS_MODULE, | |
1125 | }; | |
1126 | ||
1127 | static const char *gpio_compat = "atmel,at91rm9200-gpio"; | |
1128 | ||
150632b0 GKH |
1129 | static void at91_pinctrl_child_count(struct at91_pinctrl *info, |
1130 | struct device_node *np) | |
6732ae5c JCPV |
1131 | { |
1132 | struct device_node *child; | |
1133 | ||
1134 | for_each_child_of_node(np, child) { | |
1135 | if (of_device_is_compatible(child, gpio_compat)) { | |
a0b957f3 JCPV |
1136 | if (of_device_is_available(child)) |
1137 | info->nactive_banks++; | |
6732ae5c JCPV |
1138 | } else { |
1139 | info->nfunctions++; | |
1140 | info->ngroups += of_get_child_count(child); | |
1141 | } | |
1142 | } | |
1143 | } | |
1144 | ||
150632b0 GKH |
1145 | static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, |
1146 | struct device_node *np) | |
6732ae5c JCPV |
1147 | { |
1148 | int ret = 0; | |
1149 | int size; | |
1164d73a | 1150 | const __be32 *list; |
6732ae5c JCPV |
1151 | |
1152 | list = of_get_property(np, "atmel,mux-mask", &size); | |
1153 | if (!list) { | |
1154 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
1155 | return -EINVAL; | |
1156 | } | |
1157 | ||
1158 | size /= sizeof(*list); | |
a0b957f3 JCPV |
1159 | if (!size || size % gpio_banks) { |
1160 | dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); | |
6732ae5c JCPV |
1161 | return -EINVAL; |
1162 | } | |
a0b957f3 | 1163 | info->nmux = size / gpio_banks; |
6732ae5c | 1164 | |
a86854d0 KC |
1165 | info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32), |
1166 | GFP_KERNEL); | |
3da941b0 | 1167 | if (!info->mux_mask) |
6732ae5c | 1168 | return -ENOMEM; |
6732ae5c JCPV |
1169 | |
1170 | ret = of_property_read_u32_array(np, "atmel,mux-mask", | |
1171 | info->mux_mask, size); | |
1172 | if (ret) | |
1173 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
1174 | return ret; | |
1175 | } | |
1176 | ||
150632b0 GKH |
1177 | static int at91_pinctrl_parse_groups(struct device_node *np, |
1178 | struct at91_pin_group *grp, | |
1179 | struct at91_pinctrl *info, u32 index) | |
6732ae5c JCPV |
1180 | { |
1181 | struct at91_pmx_pin *pin; | |
1182 | int size; | |
1164d73a | 1183 | const __be32 *list; |
6732ae5c JCPV |
1184 | int i, j; |
1185 | ||
94f4e54c | 1186 | dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); |
6732ae5c JCPV |
1187 | |
1188 | /* Initialise group */ | |
1189 | grp->name = np->name; | |
1190 | ||
1191 | /* | |
1192 | * the binding format is atmel,pins = <bank pin mux CONFIG ...>, | |
1193 | * do sanity check and calculate pins number | |
1194 | */ | |
1195 | list = of_get_property(np, "atmel,pins", &size); | |
1196 | /* we do not check return since it's safe node passed down */ | |
1197 | size /= sizeof(*list); | |
1198 | if (!size || size % 4) { | |
1199 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
1200 | return -EINVAL; | |
1201 | } | |
1202 | ||
1203 | grp->npins = size / 4; | |
a86854d0 KC |
1204 | pin = grp->pins_conf = devm_kcalloc(info->dev, |
1205 | grp->npins, | |
1206 | sizeof(struct at91_pmx_pin), | |
1207 | GFP_KERNEL); | |
1208 | grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), | |
1209 | GFP_KERNEL); | |
6732ae5c JCPV |
1210 | if (!grp->pins_conf || !grp->pins) |
1211 | return -ENOMEM; | |
1212 | ||
1213 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
1214 | pin->bank = be32_to_cpu(*list++); | |
1215 | pin->pin = be32_to_cpu(*list++); | |
1216 | grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; | |
1217 | pin->mux = be32_to_cpu(*list++); | |
1218 | pin->conf = be32_to_cpu(*list++); | |
1219 | ||
1220 | at91_pin_dbg(info->dev, pin); | |
1221 | pin++; | |
1222 | } | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
150632b0 GKH |
1227 | static int at91_pinctrl_parse_functions(struct device_node *np, |
1228 | struct at91_pinctrl *info, u32 index) | |
6732ae5c JCPV |
1229 | { |
1230 | struct device_node *child; | |
1231 | struct at91_pmx_func *func; | |
1232 | struct at91_pin_group *grp; | |
1233 | int ret; | |
1234 | static u32 grp_index; | |
1235 | u32 i = 0; | |
1236 | ||
94f4e54c | 1237 | dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); |
6732ae5c JCPV |
1238 | |
1239 | func = &info->functions[index]; | |
1240 | ||
1241 | /* Initialise function */ | |
1242 | func->name = np->name; | |
1243 | func->ngroups = of_get_child_count(np); | |
ca7162ad | 1244 | if (func->ngroups == 0) { |
6732ae5c JCPV |
1245 | dev_err(info->dev, "no groups defined\n"); |
1246 | return -EINVAL; | |
1247 | } | |
a86854d0 KC |
1248 | func->groups = devm_kcalloc(info->dev, |
1249 | func->ngroups, sizeof(char *), GFP_KERNEL); | |
6732ae5c JCPV |
1250 | if (!func->groups) |
1251 | return -ENOMEM; | |
1252 | ||
1253 | for_each_child_of_node(np, child) { | |
1254 | func->groups[i] = child->name; | |
1255 | grp = &info->groups[grp_index++]; | |
1256 | ret = at91_pinctrl_parse_groups(child, grp, info, i++); | |
d94b986a JL |
1257 | if (ret) { |
1258 | of_node_put(child); | |
6732ae5c | 1259 | return ret; |
d94b986a | 1260 | } |
6732ae5c JCPV |
1261 | } |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
baa9946e | 1266 | static const struct of_device_id at91_pinctrl_of_match[] = { |
4334ac2d | 1267 | { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, |
6732ae5c JCPV |
1268 | { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, |
1269 | { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, | |
a2fcb1ce | 1270 | { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops }, |
6732ae5c JCPV |
1271 | { /* sentinel */ } |
1272 | }; | |
1273 | ||
150632b0 GKH |
1274 | static int at91_pinctrl_probe_dt(struct platform_device *pdev, |
1275 | struct at91_pinctrl *info) | |
6732ae5c JCPV |
1276 | { |
1277 | int ret = 0; | |
1278 | int i, j; | |
1279 | uint32_t *tmp; | |
1280 | struct device_node *np = pdev->dev.of_node; | |
1281 | struct device_node *child; | |
1282 | ||
1283 | if (!np) | |
1284 | return -ENODEV; | |
1285 | ||
1286 | info->dev = &pdev->dev; | |
f56b273c | 1287 | info->ops = (const struct at91_pinctrl_mux_ops *) |
6732ae5c JCPV |
1288 | of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; |
1289 | at91_pinctrl_child_count(info, np); | |
1290 | ||
a0b957f3 | 1291 | if (gpio_banks < 1) { |
61e310a1 | 1292 | dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); |
6732ae5c JCPV |
1293 | return -EINVAL; |
1294 | } | |
1295 | ||
1296 | ret = at91_pinctrl_mux_mask(info, np); | |
1297 | if (ret) | |
1298 | return ret; | |
1299 | ||
1300 | dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); | |
1301 | ||
1302 | dev_dbg(&pdev->dev, "mux-mask\n"); | |
1303 | tmp = info->mux_mask; | |
a0b957f3 | 1304 | for (i = 0; i < gpio_banks; i++) { |
6732ae5c JCPV |
1305 | for (j = 0; j < info->nmux; j++, tmp++) { |
1306 | dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1311 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
a86854d0 KC |
1312 | info->functions = devm_kcalloc(&pdev->dev, |
1313 | info->nfunctions, | |
1314 | sizeof(struct at91_pmx_func), | |
6732ae5c JCPV |
1315 | GFP_KERNEL); |
1316 | if (!info->functions) | |
1317 | return -ENOMEM; | |
1318 | ||
a86854d0 KC |
1319 | info->groups = devm_kcalloc(&pdev->dev, |
1320 | info->ngroups, | |
1321 | sizeof(struct at91_pin_group), | |
6732ae5c JCPV |
1322 | GFP_KERNEL); |
1323 | if (!info->groups) | |
1324 | return -ENOMEM; | |
1325 | ||
a0b957f3 | 1326 | dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks); |
6732ae5c JCPV |
1327 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); |
1328 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1329 | ||
1330 | i = 0; | |
1331 | ||
1332 | for_each_child_of_node(np, child) { | |
1333 | if (of_device_is_compatible(child, gpio_compat)) | |
1334 | continue; | |
1335 | ret = at91_pinctrl_parse_functions(child, info, i++); | |
1336 | if (ret) { | |
1337 | dev_err(&pdev->dev, "failed to parse function\n"); | |
d94b986a | 1338 | of_node_put(child); |
6732ae5c JCPV |
1339 | return ret; |
1340 | } | |
1341 | } | |
1342 | ||
1343 | return 0; | |
1344 | } | |
1345 | ||
150632b0 | 1346 | static int at91_pinctrl_probe(struct platform_device *pdev) |
6732ae5c JCPV |
1347 | { |
1348 | struct at91_pinctrl *info; | |
1349 | struct pinctrl_pin_desc *pdesc; | |
a0b957f3 | 1350 | int ret, i, j, k, ngpio_chips_enabled = 0; |
6732ae5c JCPV |
1351 | |
1352 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
1353 | if (!info) | |
1354 | return -ENOMEM; | |
1355 | ||
1356 | ret = at91_pinctrl_probe_dt(pdev, info); | |
1357 | if (ret) | |
1358 | return ret; | |
1359 | ||
1360 | /* | |
1361 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1362 | * to obtain references to the struct gpio_chip * for them, and we | |
1363 | * need this to proceed. | |
1364 | */ | |
a0b957f3 JCPV |
1365 | for (i = 0; i < gpio_banks; i++) |
1366 | if (gpio_chips[i]) | |
1367 | ngpio_chips_enabled++; | |
1368 | ||
1369 | if (ngpio_chips_enabled < info->nactive_banks) { | |
1370 | dev_warn(&pdev->dev, | |
1371 | "All GPIO chips are not registered yet (%d/%d)\n", | |
1372 | ngpio_chips_enabled, info->nactive_banks); | |
1373 | devm_kfree(&pdev->dev, info); | |
1374 | return -EPROBE_DEFER; | |
6732ae5c JCPV |
1375 | } |
1376 | ||
1377 | at91_pinctrl_desc.name = dev_name(&pdev->dev); | |
a0b957f3 | 1378 | at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK; |
6732ae5c | 1379 | at91_pinctrl_desc.pins = pdesc = |
a86854d0 KC |
1380 | devm_kcalloc(&pdev->dev, |
1381 | at91_pinctrl_desc.npins, sizeof(*pdesc), | |
1382 | GFP_KERNEL); | |
6732ae5c JCPV |
1383 | |
1384 | if (!at91_pinctrl_desc.pins) | |
1385 | return -ENOMEM; | |
1386 | ||
a0b957f3 | 1387 | for (i = 0, k = 0; i < gpio_banks; i++) { |
6732ae5c JCPV |
1388 | for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { |
1389 | pdesc->number = k; | |
1390 | pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); | |
1391 | pdesc++; | |
1392 | } | |
1393 | } | |
1394 | ||
1395 | platform_set_drvdata(pdev, info); | |
5c67425a LD |
1396 | info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc, |
1397 | info); | |
6732ae5c | 1398 | |
323de9ef | 1399 | if (IS_ERR(info->pctl)) { |
6732ae5c | 1400 | dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); |
323de9ef | 1401 | return PTR_ERR(info->pctl); |
6732ae5c JCPV |
1402 | } |
1403 | ||
1404 | /* We will handle a range of GPIO pins */ | |
a0b957f3 JCPV |
1405 | for (i = 0; i < gpio_banks; i++) |
1406 | if (gpio_chips[i]) | |
1407 | pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); | |
6732ae5c JCPV |
1408 | |
1409 | dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); | |
1410 | ||
1411 | return 0; | |
6732ae5c JCPV |
1412 | } |
1413 | ||
8af584b8 RG |
1414 | static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
1415 | { | |
370ea611 | 1416 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
8af584b8 RG |
1417 | void __iomem *pio = at91_gpio->regbase; |
1418 | unsigned mask = 1 << offset; | |
1419 | u32 osr; | |
1420 | ||
1421 | osr = readl_relaxed(pio + PIO_OSR); | |
3c827873 MV |
1422 | if (osr & mask) |
1423 | return GPIO_LINE_DIRECTION_OUT; | |
1424 | ||
1425 | return GPIO_LINE_DIRECTION_IN; | |
8af584b8 RG |
1426 | } |
1427 | ||
6732ae5c JCPV |
1428 | static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
1429 | { | |
370ea611 | 1430 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1431 | void __iomem *pio = at91_gpio->regbase; |
1432 | unsigned mask = 1 << offset; | |
1433 | ||
1434 | writel_relaxed(mask, pio + PIO_ODR); | |
1435 | return 0; | |
1436 | } | |
1437 | ||
1438 | static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1439 | { | |
370ea611 | 1440 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1441 | void __iomem *pio = at91_gpio->regbase; |
1442 | unsigned mask = 1 << offset; | |
1443 | u32 pdsr; | |
1444 | ||
1445 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1446 | return (pdsr & mask) != 0; | |
1447 | } | |
1448 | ||
1449 | static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, | |
1450 | int val) | |
1451 | { | |
370ea611 | 1452 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1453 | void __iomem *pio = at91_gpio->regbase; |
1454 | unsigned mask = 1 << offset; | |
1455 | ||
1456 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1457 | } | |
1458 | ||
1893b2cf AS |
1459 | static void at91_gpio_set_multiple(struct gpio_chip *chip, |
1460 | unsigned long *mask, unsigned long *bits) | |
1461 | { | |
370ea611 | 1462 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
1893b2cf AS |
1463 | void __iomem *pio = at91_gpio->regbase; |
1464 | ||
1465 | #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) | |
1466 | /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ | |
1467 | uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); | |
1468 | uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); | |
1469 | ||
1470 | writel_relaxed(set_mask, pio + PIO_SODR); | |
1471 | writel_relaxed(clear_mask, pio + PIO_CODR); | |
1472 | } | |
1473 | ||
6732ae5c JCPV |
1474 | static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
1475 | int val) | |
1476 | { | |
370ea611 | 1477 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1478 | void __iomem *pio = at91_gpio->regbase; |
1479 | unsigned mask = 1 << offset; | |
1480 | ||
1481 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1482 | writel_relaxed(mask, pio + PIO_OER); | |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
6732ae5c JCPV |
1487 | #ifdef CONFIG_DEBUG_FS |
1488 | static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1489 | { | |
1490 | enum at91_mux mode; | |
1491 | int i; | |
370ea611 | 1492 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c | 1493 | void __iomem *pio = at91_gpio->regbase; |
5bae1f08 | 1494 | const char *gpio_label; |
6732ae5c | 1495 | |
5bae1f08 | 1496 | for_each_requested_gpio(chip, i, gpio_label) { |
47f22716 | 1497 | unsigned mask = pin_to_mask(i); |
6732ae5c | 1498 | |
6732ae5c JCPV |
1499 | mode = at91_gpio->ops->get_periph(pio, mask); |
1500 | seq_printf(s, "[%s] GPIO%s%d: ", | |
1501 | gpio_label, chip->label, i); | |
1502 | if (mode == AT91_MUX_GPIO) { | |
853b6bf0 MC |
1503 | seq_printf(s, "[gpio] "); |
1504 | seq_printf(s, "%s ", | |
1505 | readl_relaxed(pio + PIO_OSR) & mask ? | |
1506 | "output" : "input"); | |
1507 | seq_printf(s, "%s\n", | |
1508 | readl_relaxed(pio + PIO_PDSR) & mask ? | |
1509 | "set" : "clear"); | |
6732ae5c JCPV |
1510 | } else { |
1511 | seq_printf(s, "[periph %c]\n", | |
1512 | mode + 'A' - 1); | |
1513 | } | |
1514 | } | |
1515 | } | |
1516 | #else | |
1517 | #define at91_gpio_dbg_show NULL | |
1518 | #endif | |
1519 | ||
1520 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
1521 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
1522 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
1523 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
1524 | * handler. | |
1525 | * First implementation always triggers on rising and falling edges | |
1526 | * whereas the newer PIO3 can be additionally configured to trigger on | |
1527 | * level, edge with any polarity. | |
1528 | * | |
1529 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
1530 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
1531 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
1532 | */ | |
1533 | ||
1534 | static void gpio_irq_mask(struct irq_data *d) | |
1535 | { | |
1536 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1537 | void __iomem *pio = at91_gpio->regbase; | |
1538 | unsigned mask = 1 << d->hwirq; | |
1539 | ||
1540 | if (pio) | |
1541 | writel_relaxed(mask, pio + PIO_IDR); | |
1542 | } | |
1543 | ||
1544 | static void gpio_irq_unmask(struct irq_data *d) | |
1545 | { | |
1546 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1547 | void __iomem *pio = at91_gpio->regbase; | |
1548 | unsigned mask = 1 << d->hwirq; | |
1549 | ||
1550 | if (pio) | |
1551 | writel_relaxed(mask, pio + PIO_IER); | |
1552 | } | |
1553 | ||
1554 | static int gpio_irq_type(struct irq_data *d, unsigned type) | |
1555 | { | |
1556 | switch (type) { | |
1557 | case IRQ_TYPE_NONE: | |
1558 | case IRQ_TYPE_EDGE_BOTH: | |
1559 | return 0; | |
1560 | default: | |
1561 | return -EINVAL; | |
1562 | } | |
1563 | } | |
1564 | ||
1565 | /* Alternate irq type for PIO3 support */ | |
1566 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type) | |
1567 | { | |
1568 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1569 | void __iomem *pio = at91_gpio->regbase; | |
1570 | unsigned mask = 1 << d->hwirq; | |
1571 | ||
1572 | switch (type) { | |
1573 | case IRQ_TYPE_EDGE_RISING: | |
c639845b | 1574 | irq_set_handler_locked(d, handle_simple_irq); |
6732ae5c JCPV |
1575 | writel_relaxed(mask, pio + PIO_ESR); |
1576 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1577 | break; | |
1578 | case IRQ_TYPE_EDGE_FALLING: | |
c639845b | 1579 | irq_set_handler_locked(d, handle_simple_irq); |
6732ae5c JCPV |
1580 | writel_relaxed(mask, pio + PIO_ESR); |
1581 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1582 | break; | |
1583 | case IRQ_TYPE_LEVEL_LOW: | |
c639845b | 1584 | irq_set_handler_locked(d, handle_level_irq); |
6732ae5c JCPV |
1585 | writel_relaxed(mask, pio + PIO_LSR); |
1586 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1587 | break; | |
1588 | case IRQ_TYPE_LEVEL_HIGH: | |
c639845b | 1589 | irq_set_handler_locked(d, handle_level_irq); |
6732ae5c JCPV |
1590 | writel_relaxed(mask, pio + PIO_LSR); |
1591 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1592 | break; | |
1593 | case IRQ_TYPE_EDGE_BOTH: | |
1594 | /* | |
1595 | * disable additional interrupt modes: | |
1596 | * fall back to default behavior | |
1597 | */ | |
c639845b | 1598 | irq_set_handler_locked(d, handle_simple_irq); |
6732ae5c JCPV |
1599 | writel_relaxed(mask, pio + PIO_AIMDR); |
1600 | return 0; | |
1601 | case IRQ_TYPE_NONE: | |
1602 | default: | |
1c5fb66a | 1603 | pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq); |
6732ae5c JCPV |
1604 | return -EINVAL; |
1605 | } | |
1606 | ||
1607 | /* enable additional interrupt modes */ | |
1608 | writel_relaxed(mask, pio + PIO_AIMER); | |
1609 | ||
1610 | return 0; | |
1611 | } | |
1612 | ||
80cc3732 AS |
1613 | static void gpio_irq_ack(struct irq_data *d) |
1614 | { | |
1615 | /* the interrupt is already cleared before by reading ISR */ | |
1616 | } | |
1617 | ||
6732ae5c | 1618 | #ifdef CONFIG_PM |
647f8d94 LD |
1619 | |
1620 | static u32 wakeups[MAX_GPIO_BANKS]; | |
1621 | static u32 backups[MAX_GPIO_BANKS]; | |
1622 | ||
6732ae5c JCPV |
1623 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) |
1624 | { | |
1625 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1626 | unsigned bank = at91_gpio->pioc_idx; | |
647f8d94 | 1627 | unsigned mask = 1 << d->hwirq; |
6732ae5c JCPV |
1628 | |
1629 | if (unlikely(bank >= MAX_GPIO_BANKS)) | |
1630 | return -EINVAL; | |
1631 | ||
647f8d94 LD |
1632 | if (state) |
1633 | wakeups[bank] |= mask; | |
1634 | else | |
1635 | wakeups[bank] &= ~mask; | |
1636 | ||
6732ae5c JCPV |
1637 | irq_set_irq_wake(at91_gpio->pioc_virq, state); |
1638 | ||
1639 | return 0; | |
1640 | } | |
647f8d94 LD |
1641 | |
1642 | void at91_pinctrl_gpio_suspend(void) | |
1643 | { | |
1644 | int i; | |
1645 | ||
1646 | for (i = 0; i < gpio_banks; i++) { | |
1647 | void __iomem *pio; | |
1648 | ||
1649 | if (!gpio_chips[i]) | |
1650 | continue; | |
1651 | ||
1652 | pio = gpio_chips[i]->regbase; | |
1653 | ||
d480239b BD |
1654 | backups[i] = readl_relaxed(pio + PIO_IMR); |
1655 | writel_relaxed(backups[i], pio + PIO_IDR); | |
1656 | writel_relaxed(wakeups[i], pio + PIO_IER); | |
647f8d94 | 1657 | |
795f9953 BB |
1658 | if (!wakeups[i]) |
1659 | clk_disable_unprepare(gpio_chips[i]->clock); | |
1660 | else | |
647f8d94 LD |
1661 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", |
1662 | 'A'+i, wakeups[i]); | |
647f8d94 LD |
1663 | } |
1664 | } | |
1665 | ||
1666 | void at91_pinctrl_gpio_resume(void) | |
1667 | { | |
1668 | int i; | |
1669 | ||
1670 | for (i = 0; i < gpio_banks; i++) { | |
1671 | void __iomem *pio; | |
1672 | ||
1673 | if (!gpio_chips[i]) | |
1674 | continue; | |
1675 | ||
1676 | pio = gpio_chips[i]->regbase; | |
1677 | ||
37ef1d92 BB |
1678 | if (!wakeups[i]) |
1679 | clk_prepare_enable(gpio_chips[i]->clock); | |
647f8d94 | 1680 | |
d480239b BD |
1681 | writel_relaxed(wakeups[i], pio + PIO_IDR); |
1682 | writel_relaxed(backups[i], pio + PIO_IER); | |
647f8d94 LD |
1683 | } |
1684 | } | |
1685 | ||
6732ae5c JCPV |
1686 | #else |
1687 | #define gpio_irq_set_wake NULL | |
647f8d94 | 1688 | #endif /* CONFIG_PM */ |
6732ae5c | 1689 | |
bd0b9ac4 | 1690 | static void gpio_irq_handler(struct irq_desc *desc) |
6732ae5c | 1691 | { |
5663bb27 | 1692 | struct irq_chip *chip = irq_desc_get_chip(desc); |
80cc3732 | 1693 | struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); |
370ea611 | 1694 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip); |
6732ae5c JCPV |
1695 | void __iomem *pio = at91_gpio->regbase; |
1696 | unsigned long isr; | |
1697 | int n; | |
1698 | ||
1699 | chained_irq_enter(chip, desc); | |
1700 | for (;;) { | |
1701 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | |
c2eb9e7f | 1702 | * When there are none pending, we're finished unless we need |
6732ae5c JCPV |
1703 | * to process multiple banks (like ID_PIOCDE on sam9263). |
1704 | */ | |
1705 | isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); | |
1706 | if (!isr) { | |
1707 | if (!at91_gpio->next) | |
1708 | break; | |
1709 | at91_gpio = at91_gpio->next; | |
1710 | pio = at91_gpio->regbase; | |
cccb0c3e | 1711 | gpio_chip = &at91_gpio->chip; |
6732ae5c JCPV |
1712 | continue; |
1713 | } | |
1714 | ||
a9cb09b7 MZ |
1715 | for_each_set_bit(n, &isr, BITS_PER_LONG) |
1716 | generic_handle_domain_irq(gpio_chip->irq.domain, n); | |
6732ae5c JCPV |
1717 | } |
1718 | chained_irq_exit(chip, desc); | |
1719 | /* now it may re-trigger */ | |
1720 | } | |
1721 | ||
834e1678 | 1722 | static int at91_gpio_of_irq_setup(struct platform_device *pdev, |
6732ae5c JCPV |
1723 | struct at91_gpio_chip *at91_gpio) |
1724 | { | |
a0b957f3 | 1725 | struct gpio_chip *gpiochip_prev = NULL; |
cccb0c3e | 1726 | struct at91_gpio_chip *prev = NULL; |
6732ae5c | 1727 | struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); |
0c3dfa17 | 1728 | struct irq_chip *gpio_irqchip; |
35dea5d7 LW |
1729 | struct gpio_irq_chip *girq; |
1730 | int i; | |
6732ae5c | 1731 | |
35dea5d7 LW |
1732 | gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), |
1733 | GFP_KERNEL); | |
0c3dfa17 LD |
1734 | if (!gpio_irqchip) |
1735 | return -ENOMEM; | |
1736 | ||
6732ae5c JCPV |
1737 | at91_gpio->pioc_hwirq = irqd_to_hwirq(d); |
1738 | ||
0c3dfa17 LD |
1739 | gpio_irqchip->name = "GPIO"; |
1740 | gpio_irqchip->irq_ack = gpio_irq_ack; | |
1741 | gpio_irqchip->irq_disable = gpio_irq_mask; | |
1742 | gpio_irqchip->irq_mask = gpio_irq_mask; | |
1743 | gpio_irqchip->irq_unmask = gpio_irq_unmask; | |
46e5dbe7 | 1744 | gpio_irqchip->irq_set_wake = gpio_irq_set_wake; |
0c3dfa17 | 1745 | gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type; |
6732ae5c JCPV |
1746 | |
1747 | /* Disable irqs of this PIO controller */ | |
1748 | writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); | |
1749 | ||
80cc3732 AS |
1750 | /* |
1751 | * Let the generic code handle this edge IRQ, the the chained | |
1752 | * handler will perform the actual work of handling the parent | |
1753 | * interrupt. | |
1754 | */ | |
35dea5d7 LW |
1755 | girq = &at91_gpio->chip.irq; |
1756 | girq->chip = gpio_irqchip; | |
1757 | girq->default_type = IRQ_TYPE_NONE; | |
1758 | girq->handler = handle_edge_irq; | |
6732ae5c | 1759 | |
35dea5d7 LW |
1760 | /* |
1761 | * The top level handler handles one bank of GPIOs, except | |
cccb0c3e AS |
1762 | * on some SoC it can handle up to three... |
1763 | * We only set up the handler for the first of the list. | |
1764 | */ | |
a0b957f3 JCPV |
1765 | gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); |
1766 | if (!gpiochip_prev) { | |
35dea5d7 LW |
1767 | girq->parent_handler = gpio_irq_handler; |
1768 | girq->num_parents = 1; | |
1769 | girq->parents = devm_kcalloc(&pdev->dev, 1, | |
1770 | sizeof(*girq->parents), | |
1771 | GFP_KERNEL); | |
1772 | if (!girq->parents) | |
1773 | return -ENOMEM; | |
1774 | girq->parents[0] = at91_gpio->pioc_virq; | |
cccb0c3e | 1775 | return 0; |
a0b957f3 | 1776 | } |
cccb0c3e | 1777 | |
370ea611 | 1778 | prev = gpiochip_get_data(gpiochip_prev); |
a0b957f3 JCPV |
1779 | /* we can only have 2 banks before */ |
1780 | for (i = 0; i < 2; i++) { | |
1781 | if (prev->next) { | |
1782 | prev = prev->next; | |
1783 | } else { | |
1784 | prev->next = at91_gpio; | |
1785 | return 0; | |
1786 | } | |
1787 | } | |
1788 | ||
1789 | return -EINVAL; | |
6732ae5c JCPV |
1790 | } |
1791 | ||
1792 | /* This structure is replicated for each GPIO block allocated at probe time */ | |
234b6513 | 1793 | static const struct gpio_chip at91_gpio_template = { |
98c85d58 JG |
1794 | .request = gpiochip_generic_request, |
1795 | .free = gpiochip_generic_free, | |
8af584b8 | 1796 | .get_direction = at91_gpio_get_direction, |
6732ae5c JCPV |
1797 | .direction_input = at91_gpio_direction_input, |
1798 | .get = at91_gpio_get, | |
1799 | .direction_output = at91_gpio_direction_output, | |
1800 | .set = at91_gpio_set, | |
1893b2cf | 1801 | .set_multiple = at91_gpio_set_multiple, |
6732ae5c | 1802 | .dbg_show = at91_gpio_dbg_show, |
9fb1f39e | 1803 | .can_sleep = false, |
6732ae5c JCPV |
1804 | .ngpio = MAX_NB_GPIO_PER_BANK, |
1805 | }; | |
1806 | ||
baa9946e | 1807 | static const struct of_device_id at91_gpio_of_match[] = { |
6732ae5c JCPV |
1808 | { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, |
1809 | { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, | |
a2fcb1ce | 1810 | { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops }, |
6732ae5c JCPV |
1811 | { /* sentinel */ } |
1812 | }; | |
1813 | ||
150632b0 | 1814 | static int at91_gpio_probe(struct platform_device *pdev) |
6732ae5c JCPV |
1815 | { |
1816 | struct device_node *np = pdev->dev.of_node; | |
6732ae5c JCPV |
1817 | struct at91_gpio_chip *at91_chip = NULL; |
1818 | struct gpio_chip *chip; | |
1819 | struct pinctrl_gpio_range *range; | |
1820 | int ret = 0; | |
32b01a36 | 1821 | int irq, i; |
6732ae5c JCPV |
1822 | int alias_idx = of_alias_get_id(np, "gpio"); |
1823 | uint32_t ngpio; | |
32b01a36 | 1824 | char **names; |
6732ae5c JCPV |
1825 | |
1826 | BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); | |
1827 | if (gpio_chips[alias_idx]) { | |
1828 | ret = -EBUSY; | |
1829 | goto err; | |
1830 | } | |
1831 | ||
6732ae5c JCPV |
1832 | irq = platform_get_irq(pdev, 0); |
1833 | if (irq < 0) { | |
1834 | ret = irq; | |
1835 | goto err; | |
1836 | } | |
1837 | ||
1838 | at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); | |
1839 | if (!at91_chip) { | |
1840 | ret = -ENOMEM; | |
1841 | goto err; | |
1842 | } | |
1843 | ||
4b024225 | 1844 | at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0); |
9e0c1fb2 TR |
1845 | if (IS_ERR(at91_chip->regbase)) { |
1846 | ret = PTR_ERR(at91_chip->regbase); | |
6732ae5c JCPV |
1847 | goto err; |
1848 | } | |
1849 | ||
f56b273c | 1850 | at91_chip->ops = (const struct at91_pinctrl_mux_ops *) |
6732ae5c JCPV |
1851 | of_match_device(at91_gpio_of_match, &pdev->dev)->data; |
1852 | at91_chip->pioc_virq = irq; | |
1853 | at91_chip->pioc_idx = alias_idx; | |
1854 | ||
02b837ff | 1855 | at91_chip->clock = devm_clk_get(&pdev->dev, NULL); |
6732ae5c JCPV |
1856 | if (IS_ERR(at91_chip->clock)) { |
1857 | dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); | |
70e41974 | 1858 | ret = PTR_ERR(at91_chip->clock); |
6732ae5c JCPV |
1859 | goto err; |
1860 | } | |
1861 | ||
7d3a3fe6 | 1862 | ret = clk_prepare_enable(at91_chip->clock); |
70e41974 | 1863 | if (ret) { |
7d3a3fe6 | 1864 | dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n"); |
70e41974 | 1865 | goto clk_enable_err; |
6732ae5c JCPV |
1866 | } |
1867 | ||
1868 | at91_chip->chip = at91_gpio_template; | |
1869 | ||
1870 | chip = &at91_chip->chip; | |
1871 | chip->of_node = np; | |
1872 | chip->label = dev_name(&pdev->dev); | |
58383c78 | 1873 | chip->parent = &pdev->dev; |
6732ae5c JCPV |
1874 | chip->owner = THIS_MODULE; |
1875 | chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; | |
1876 | ||
1877 | if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { | |
1878 | if (ngpio >= MAX_NB_GPIO_PER_BANK) | |
1879 | pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", | |
1880 | alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); | |
1881 | else | |
1882 | chip->ngpio = ngpio; | |
1883 | } | |
1884 | ||
a86854d0 | 1885 | names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *), |
3c93600d | 1886 | GFP_KERNEL); |
32b01a36 JCPV |
1887 | |
1888 | if (!names) { | |
1889 | ret = -ENOMEM; | |
70e41974 | 1890 | goto clk_enable_err; |
32b01a36 JCPV |
1891 | } |
1892 | ||
1893 | for (i = 0; i < chip->ngpio; i++) | |
1894 | names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); | |
1895 | ||
3c93600d | 1896 | chip->names = (const char *const *)names; |
32b01a36 | 1897 | |
6732ae5c JCPV |
1898 | range = &at91_chip->range; |
1899 | range->name = chip->label; | |
1900 | range->id = alias_idx; | |
1901 | range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; | |
1902 | ||
1903 | range->npins = chip->ngpio; | |
1904 | range->gc = chip; | |
1905 | ||
35dea5d7 LW |
1906 | ret = at91_gpio_of_irq_setup(pdev, at91_chip); |
1907 | if (ret) | |
1908 | goto gpiochip_add_err; | |
1909 | ||
370ea611 | 1910 | ret = gpiochip_add_data(chip, at91_chip); |
6732ae5c | 1911 | if (ret) |
70e41974 | 1912 | goto gpiochip_add_err; |
6732ae5c JCPV |
1913 | |
1914 | gpio_chips[alias_idx] = at91_chip; | |
1915 | gpio_banks = max(gpio_banks, alias_idx + 1); | |
1916 | ||
6732ae5c JCPV |
1917 | dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); |
1918 | ||
1919 | return 0; | |
1920 | ||
70e41974 | 1921 | gpiochip_add_err: |
70e41974 | 1922 | clk_enable_err: |
7d3a3fe6 | 1923 | clk_disable_unprepare(at91_chip->clock); |
6732ae5c JCPV |
1924 | err: |
1925 | dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); | |
1926 | ||
1927 | return ret; | |
1928 | } | |
1929 | ||
1930 | static struct platform_driver at91_gpio_driver = { | |
1931 | .driver = { | |
1932 | .name = "gpio-at91", | |
606fca94 | 1933 | .of_match_table = at91_gpio_of_match, |
6732ae5c JCPV |
1934 | }, |
1935 | .probe = at91_gpio_probe, | |
1936 | }; | |
1937 | ||
1938 | static struct platform_driver at91_pinctrl_driver = { | |
1939 | .driver = { | |
1940 | .name = "pinctrl-at91", | |
606fca94 | 1941 | .of_match_table = at91_pinctrl_of_match, |
6732ae5c JCPV |
1942 | }, |
1943 | .probe = at91_pinctrl_probe, | |
6732ae5c JCPV |
1944 | }; |
1945 | ||
bab7f5a4 TR |
1946 | static struct platform_driver * const drivers[] = { |
1947 | &at91_gpio_driver, | |
1948 | &at91_pinctrl_driver, | |
1949 | }; | |
1950 | ||
6732ae5c JCPV |
1951 | static int __init at91_pinctrl_init(void) |
1952 | { | |
bab7f5a4 | 1953 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
6732ae5c JCPV |
1954 | } |
1955 | arch_initcall(at91_pinctrl_init); |