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d3e51161 HS |
1 | /* |
2 | * Pinctrl driver for Rockchip SoCs | |
3 | * | |
4 | * Copyright (c) 2013 MundoReader S.L. | |
5 | * Author: Heiko Stuebner <heiko@sntech.de> | |
6 | * | |
7 | * With some ideas taken from pinctrl-samsung: | |
8 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
9 | * http://www.samsung.com | |
10 | * Copyright (c) 2012 Linaro Ltd | |
11 | * http://www.linaro.org | |
12 | * | |
13 | * and pinctrl-at91: | |
14 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as published | |
18 | * by the Free Software Foundation. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | */ | |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/bitops.h> | |
30 | #include <linux/gpio.h> | |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_irq.h> | |
33 | #include <linux/pinctrl/machine.h> | |
34 | #include <linux/pinctrl/pinconf.h> | |
35 | #include <linux/pinctrl/pinctrl.h> | |
36 | #include <linux/pinctrl/pinmux.h> | |
37 | #include <linux/pinctrl/pinconf-generic.h> | |
38 | #include <linux/irqchip/chained_irq.h> | |
7e865abb | 39 | #include <linux/clk.h> |
751a99ab | 40 | #include <linux/regmap.h> |
14dee867 | 41 | #include <linux/mfd/syscon.h> |
d3e51161 HS |
42 | #include <dt-bindings/pinctrl/rockchip.h> |
43 | ||
44 | #include "core.h" | |
45 | #include "pinconf.h" | |
46 | ||
47 | /* GPIO control registers */ | |
48 | #define GPIO_SWPORT_DR 0x00 | |
49 | #define GPIO_SWPORT_DDR 0x04 | |
50 | #define GPIO_INTEN 0x30 | |
51 | #define GPIO_INTMASK 0x34 | |
52 | #define GPIO_INTTYPE_LEVEL 0x38 | |
53 | #define GPIO_INT_POLARITY 0x3c | |
54 | #define GPIO_INT_STATUS 0x40 | |
55 | #define GPIO_INT_RAWSTATUS 0x44 | |
56 | #define GPIO_DEBOUNCE 0x48 | |
57 | #define GPIO_PORTS_EOI 0x4c | |
58 | #define GPIO_EXT_PORT 0x50 | |
59 | #define GPIO_LS_SYNC 0x60 | |
60 | ||
a282926d HS |
61 | enum rockchip_pinctrl_type { |
62 | RK2928, | |
63 | RK3066B, | |
64 | RK3188, | |
65 | }; | |
66 | ||
fc72c923 HS |
67 | /** |
68 | * Encode variants of iomux registers into a type variable | |
69 | */ | |
70 | #define IOMUX_GPIO_ONLY BIT(0) | |
71 | ||
72 | /** | |
73 | * @type: iomux variant using IOMUX_* constants | |
6bc0d121 HS |
74 | * @offset: if initialized to -1 it will be autocalculated, by specifying |
75 | * an initial offset value the relevant source offset can be reset | |
76 | * to a new value for autocalculating the following iomux registers. | |
fc72c923 HS |
77 | */ |
78 | struct rockchip_iomux { | |
79 | int type; | |
6bc0d121 | 80 | int offset; |
65fca613 HS |
81 | }; |
82 | ||
d3e51161 HS |
83 | /** |
84 | * @reg_base: register base of the gpio bank | |
6ca5274d | 85 | * @reg_pull: optional separate register for additional pull settings |
d3e51161 HS |
86 | * @clk: clock of the gpio bank |
87 | * @irq: interrupt of the gpio bank | |
88 | * @pin_base: first pin number | |
89 | * @nr_pins: number of pins in this bank | |
90 | * @name: name of the bank | |
91 | * @bank_num: number of the bank, to account for holes | |
fc72c923 | 92 | * @iomux: array describing the 4 iomux sources of the bank |
d3e51161 HS |
93 | * @valid: are all necessary informations present |
94 | * @of_node: dt node of this bank | |
95 | * @drvdata: common pinctrl basedata | |
96 | * @domain: irqdomain of the gpio bank | |
97 | * @gpio_chip: gpiolib chip | |
98 | * @grange: gpio range | |
99 | * @slock: spinlock for the gpio bank | |
100 | */ | |
101 | struct rockchip_pin_bank { | |
102 | void __iomem *reg_base; | |
751a99ab | 103 | struct regmap *regmap_pull; |
d3e51161 HS |
104 | struct clk *clk; |
105 | int irq; | |
106 | u32 pin_base; | |
107 | u8 nr_pins; | |
108 | char *name; | |
109 | u8 bank_num; | |
fc72c923 | 110 | struct rockchip_iomux iomux[4]; |
d3e51161 HS |
111 | bool valid; |
112 | struct device_node *of_node; | |
113 | struct rockchip_pinctrl *drvdata; | |
114 | struct irq_domain *domain; | |
115 | struct gpio_chip gpio_chip; | |
116 | struct pinctrl_gpio_range grange; | |
117 | spinlock_t slock; | |
5a927501 | 118 | u32 toggle_edge_mode; |
d3e51161 HS |
119 | }; |
120 | ||
121 | #define PIN_BANK(id, pins, label) \ | |
122 | { \ | |
123 | .bank_num = id, \ | |
124 | .nr_pins = pins, \ | |
125 | .name = label, \ | |
6bc0d121 HS |
126 | .iomux = { \ |
127 | { .offset = -1 }, \ | |
128 | { .offset = -1 }, \ | |
129 | { .offset = -1 }, \ | |
130 | { .offset = -1 }, \ | |
131 | }, \ | |
d3e51161 HS |
132 | } |
133 | ||
fc72c923 HS |
134 | #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ |
135 | { \ | |
136 | .bank_num = id, \ | |
137 | .nr_pins = pins, \ | |
138 | .name = label, \ | |
139 | .iomux = { \ | |
6bc0d121 HS |
140 | { .type = iom0, .offset = -1 }, \ |
141 | { .type = iom1, .offset = -1 }, \ | |
142 | { .type = iom2, .offset = -1 }, \ | |
143 | { .type = iom3, .offset = -1 }, \ | |
fc72c923 HS |
144 | }, \ |
145 | } | |
146 | ||
d3e51161 | 147 | /** |
d3e51161 HS |
148 | */ |
149 | struct rockchip_pin_ctrl { | |
150 | struct rockchip_pin_bank *pin_banks; | |
151 | u32 nr_banks; | |
152 | u32 nr_pins; | |
153 | char *label; | |
a282926d | 154 | enum rockchip_pinctrl_type type; |
d3e51161 | 155 | int mux_offset; |
751a99ab HS |
156 | void (*pull_calc_reg)(struct rockchip_pin_bank *bank, |
157 | int pin_num, struct regmap **regmap, | |
158 | int *reg, u8 *bit); | |
d3e51161 HS |
159 | }; |
160 | ||
161 | struct rockchip_pin_config { | |
162 | unsigned int func; | |
163 | unsigned long *configs; | |
164 | unsigned int nconfigs; | |
165 | }; | |
166 | ||
167 | /** | |
168 | * struct rockchip_pin_group: represent group of pins of a pinmux function. | |
169 | * @name: name of the pin group, used to lookup the group. | |
170 | * @pins: the pins included in this group. | |
171 | * @npins: number of pins included in this group. | |
172 | * @func: the mux function number to be programmed when selected. | |
173 | * @configs: the config values to be set for each pin | |
174 | * @nconfigs: number of configs for each pin | |
175 | */ | |
176 | struct rockchip_pin_group { | |
177 | const char *name; | |
178 | unsigned int npins; | |
179 | unsigned int *pins; | |
180 | struct rockchip_pin_config *data; | |
181 | }; | |
182 | ||
183 | /** | |
184 | * struct rockchip_pmx_func: represent a pin function. | |
185 | * @name: name of the pin function, used to lookup the function. | |
186 | * @groups: one or more names of pin groups that provide this function. | |
187 | * @num_groups: number of groups included in @groups. | |
188 | */ | |
189 | struct rockchip_pmx_func { | |
190 | const char *name; | |
191 | const char **groups; | |
192 | u8 ngroups; | |
193 | }; | |
194 | ||
195 | struct rockchip_pinctrl { | |
751a99ab | 196 | struct regmap *regmap_base; |
bfc7a42a | 197 | int reg_size; |
751a99ab | 198 | struct regmap *regmap_pull; |
14dee867 | 199 | struct regmap *regmap_pmu; |
d3e51161 HS |
200 | struct device *dev; |
201 | struct rockchip_pin_ctrl *ctrl; | |
202 | struct pinctrl_desc pctl; | |
203 | struct pinctrl_dev *pctl_dev; | |
204 | struct rockchip_pin_group *groups; | |
205 | unsigned int ngroups; | |
206 | struct rockchip_pmx_func *functions; | |
207 | unsigned int nfunctions; | |
208 | }; | |
209 | ||
751a99ab HS |
210 | static struct regmap_config rockchip_regmap_config = { |
211 | .reg_bits = 32, | |
212 | .val_bits = 32, | |
213 | .reg_stride = 4, | |
214 | }; | |
215 | ||
d3e51161 HS |
216 | static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) |
217 | { | |
218 | return container_of(gc, struct rockchip_pin_bank, gpio_chip); | |
219 | } | |
220 | ||
221 | static const inline struct rockchip_pin_group *pinctrl_name_to_group( | |
222 | const struct rockchip_pinctrl *info, | |
223 | const char *name) | |
224 | { | |
d3e51161 HS |
225 | int i; |
226 | ||
227 | for (i = 0; i < info->ngroups; i++) { | |
1cb95395 AL |
228 | if (!strcmp(info->groups[i].name, name)) |
229 | return &info->groups[i]; | |
d3e51161 HS |
230 | } |
231 | ||
1cb95395 | 232 | return NULL; |
d3e51161 HS |
233 | } |
234 | ||
235 | /* | |
236 | * given a pin number that is local to a pin controller, find out the pin bank | |
237 | * and the register base of the pin bank. | |
238 | */ | |
239 | static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, | |
240 | unsigned pin) | |
241 | { | |
242 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
243 | ||
51578b9b | 244 | while (pin >= (b->pin_base + b->nr_pins)) |
d3e51161 HS |
245 | b++; |
246 | ||
247 | return b; | |
248 | } | |
249 | ||
250 | static struct rockchip_pin_bank *bank_num_to_bank( | |
251 | struct rockchip_pinctrl *info, | |
252 | unsigned num) | |
253 | { | |
254 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
255 | int i; | |
256 | ||
1cb95395 | 257 | for (i = 0; i < info->ctrl->nr_banks; i++, b++) { |
d3e51161 | 258 | if (b->bank_num == num) |
1cb95395 | 259 | return b; |
d3e51161 HS |
260 | } |
261 | ||
1cb95395 | 262 | return ERR_PTR(-EINVAL); |
d3e51161 HS |
263 | } |
264 | ||
265 | /* | |
266 | * Pinctrl_ops handling | |
267 | */ | |
268 | ||
269 | static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) | |
270 | { | |
271 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
272 | ||
273 | return info->ngroups; | |
274 | } | |
275 | ||
276 | static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, | |
277 | unsigned selector) | |
278 | { | |
279 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
280 | ||
281 | return info->groups[selector].name; | |
282 | } | |
283 | ||
284 | static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, | |
285 | unsigned selector, const unsigned **pins, | |
286 | unsigned *npins) | |
287 | { | |
288 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
289 | ||
290 | if (selector >= info->ngroups) | |
291 | return -EINVAL; | |
292 | ||
293 | *pins = info->groups[selector].pins; | |
294 | *npins = info->groups[selector].npins; | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, | |
300 | struct device_node *np, | |
301 | struct pinctrl_map **map, unsigned *num_maps) | |
302 | { | |
303 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
304 | const struct rockchip_pin_group *grp; | |
305 | struct pinctrl_map *new_map; | |
306 | struct device_node *parent; | |
307 | int map_num = 1; | |
308 | int i; | |
309 | ||
310 | /* | |
311 | * first find the group of this node and check if we need to create | |
312 | * config maps for pins | |
313 | */ | |
314 | grp = pinctrl_name_to_group(info, np->name); | |
315 | if (!grp) { | |
316 | dev_err(info->dev, "unable to find group for node %s\n", | |
317 | np->name); | |
318 | return -EINVAL; | |
319 | } | |
320 | ||
321 | map_num += grp->npins; | |
322 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, | |
323 | GFP_KERNEL); | |
324 | if (!new_map) | |
325 | return -ENOMEM; | |
326 | ||
327 | *map = new_map; | |
328 | *num_maps = map_num; | |
329 | ||
330 | /* create mux map */ | |
331 | parent = of_get_parent(np); | |
332 | if (!parent) { | |
333 | devm_kfree(pctldev->dev, new_map); | |
334 | return -EINVAL; | |
335 | } | |
336 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
337 | new_map[0].data.mux.function = parent->name; | |
338 | new_map[0].data.mux.group = np->name; | |
339 | of_node_put(parent); | |
340 | ||
341 | /* create config map */ | |
342 | new_map++; | |
343 | for (i = 0; i < grp->npins; i++) { | |
344 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
345 | new_map[i].data.configs.group_or_pin = | |
346 | pin_get_name(pctldev, grp->pins[i]); | |
347 | new_map[i].data.configs.configs = grp->data[i].configs; | |
348 | new_map[i].data.configs.num_configs = grp->data[i].nconfigs; | |
349 | } | |
350 | ||
351 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
352 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, | |
358 | struct pinctrl_map *map, unsigned num_maps) | |
359 | { | |
360 | } | |
361 | ||
362 | static const struct pinctrl_ops rockchip_pctrl_ops = { | |
363 | .get_groups_count = rockchip_get_groups_count, | |
364 | .get_group_name = rockchip_get_group_name, | |
365 | .get_group_pins = rockchip_get_group_pins, | |
366 | .dt_node_to_map = rockchip_dt_node_to_map, | |
367 | .dt_free_map = rockchip_dt_free_map, | |
368 | }; | |
369 | ||
370 | /* | |
371 | * Hardware access | |
372 | */ | |
373 | ||
a076e2ed HS |
374 | static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) |
375 | { | |
376 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 377 | int iomux_num = (pin / 8); |
751a99ab HS |
378 | unsigned int val; |
379 | int reg, ret; | |
a076e2ed HS |
380 | u8 bit; |
381 | ||
fc72c923 HS |
382 | if (iomux_num > 3) |
383 | return -EINVAL; | |
384 | ||
385 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) | |
a076e2ed HS |
386 | return RK_FUNC_GPIO; |
387 | ||
388 | /* get basic quadrupel of mux registers and the correct reg inside */ | |
6bc0d121 | 389 | reg = bank->iomux[iomux_num].offset; |
a076e2ed HS |
390 | bit = (pin % 8) * 2; |
391 | ||
751a99ab HS |
392 | ret = regmap_read(info->regmap_base, reg, &val); |
393 | if (ret) | |
394 | return ret; | |
395 | ||
396 | return ((val >> bit) & 3); | |
a076e2ed HS |
397 | } |
398 | ||
d3e51161 HS |
399 | /* |
400 | * Set a new mux function for a pin. | |
401 | * | |
402 | * The register is divided into the upper and lower 16 bit. When changing | |
403 | * a value, the previous register value is not read and changed. Instead | |
404 | * it seems the changed bits are marked in the upper 16 bit, while the | |
405 | * changed value gets set in the same offset in the lower 16 bit. | |
406 | * All pin settings seem to be 2 bit wide in both the upper and lower | |
407 | * parts. | |
408 | * @bank: pin bank to change | |
409 | * @pin: pin to change | |
410 | * @mux: new mux function to set | |
411 | */ | |
14797189 | 412 | static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) |
d3e51161 HS |
413 | { |
414 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 415 | int iomux_num = (pin / 8); |
751a99ab | 416 | int reg, ret; |
d3e51161 HS |
417 | unsigned long flags; |
418 | u8 bit; | |
419 | u32 data; | |
420 | ||
fc72c923 HS |
421 | if (iomux_num > 3) |
422 | return -EINVAL; | |
423 | ||
424 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { | |
c4a532de HS |
425 | if (mux != RK_FUNC_GPIO) { |
426 | dev_err(info->dev, | |
427 | "pin %d only supports a gpio mux\n", pin); | |
428 | return -ENOTSUPP; | |
429 | } else { | |
430 | return 0; | |
431 | } | |
432 | } | |
433 | ||
d3e51161 HS |
434 | dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", |
435 | bank->bank_num, pin, mux); | |
436 | ||
437 | /* get basic quadrupel of mux registers and the correct reg inside */ | |
6bc0d121 | 438 | reg = bank->iomux[iomux_num].offset; |
d3e51161 HS |
439 | bit = (pin % 8) * 2; |
440 | ||
441 | spin_lock_irqsave(&bank->slock, flags); | |
442 | ||
443 | data = (3 << (bit + 16)); | |
444 | data |= (mux & 3) << bit; | |
751a99ab | 445 | ret = regmap_write(info->regmap_base, reg, data); |
d3e51161 HS |
446 | |
447 | spin_unlock_irqrestore(&bank->slock, flags); | |
14797189 | 448 | |
751a99ab | 449 | return ret; |
d3e51161 HS |
450 | } |
451 | ||
a282926d HS |
452 | #define RK2928_PULL_OFFSET 0x118 |
453 | #define RK2928_PULL_PINS_PER_REG 16 | |
454 | #define RK2928_PULL_BANK_STRIDE 8 | |
455 | ||
456 | static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
457 | int pin_num, struct regmap **regmap, |
458 | int *reg, u8 *bit) | |
a282926d HS |
459 | { |
460 | struct rockchip_pinctrl *info = bank->drvdata; | |
461 | ||
751a99ab HS |
462 | *regmap = info->regmap_base; |
463 | *reg = RK2928_PULL_OFFSET; | |
a282926d HS |
464 | *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; |
465 | *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; | |
466 | ||
467 | *bit = pin_num % RK2928_PULL_PINS_PER_REG; | |
468 | }; | |
469 | ||
bfc7a42a | 470 | #define RK3188_PULL_OFFSET 0x164 |
6ca5274d HS |
471 | #define RK3188_PULL_BITS_PER_PIN 2 |
472 | #define RK3188_PULL_PINS_PER_REG 8 | |
473 | #define RK3188_PULL_BANK_STRIDE 16 | |
14dee867 | 474 | #define RK3188_PULL_PMU_OFFSET 0x64 |
6ca5274d HS |
475 | |
476 | static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
477 | int pin_num, struct regmap **regmap, |
478 | int *reg, u8 *bit) | |
6ca5274d HS |
479 | { |
480 | struct rockchip_pinctrl *info = bank->drvdata; | |
481 | ||
482 | /* The first 12 pins of the first bank are located elsewhere */ | |
fc72c923 | 483 | if (bank->bank_num == 0 && pin_num < 12) { |
14dee867 HS |
484 | *regmap = info->regmap_pmu ? info->regmap_pmu |
485 | : bank->regmap_pull; | |
486 | *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; | |
751a99ab | 487 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
6ca5274d HS |
488 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
489 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
490 | } else { | |
751a99ab HS |
491 | *regmap = info->regmap_pull ? info->regmap_pull |
492 | : info->regmap_base; | |
493 | *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; | |
494 | ||
bfc7a42a HS |
495 | /* correct the offset, as it is the 2nd pull register */ |
496 | *reg -= 4; | |
6ca5274d HS |
497 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
498 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
499 | ||
500 | /* | |
501 | * The bits in these registers have an inverse ordering | |
502 | * with the lowest pin being in bits 15:14 and the highest | |
503 | * pin in bits 1:0 | |
504 | */ | |
505 | *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); | |
506 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
507 | } | |
508 | } | |
509 | ||
d3e51161 HS |
510 | static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) |
511 | { | |
512 | struct rockchip_pinctrl *info = bank->drvdata; | |
513 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
514 | struct regmap *regmap; |
515 | int reg, ret; | |
d3e51161 | 516 | u8 bit; |
6ca5274d | 517 | u32 data; |
d3e51161 HS |
518 | |
519 | /* rk3066b does support any pulls */ | |
a282926d | 520 | if (ctrl->type == RK3066B) |
d3e51161 HS |
521 | return PIN_CONFIG_BIAS_DISABLE; |
522 | ||
751a99ab HS |
523 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
524 | ||
525 | ret = regmap_read(regmap, reg, &data); | |
526 | if (ret) | |
527 | return ret; | |
6ca5274d | 528 | |
a282926d HS |
529 | switch (ctrl->type) { |
530 | case RK2928: | |
751a99ab | 531 | return !(data & BIT(bit)) |
d3e51161 HS |
532 | ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT |
533 | : PIN_CONFIG_BIAS_DISABLE; | |
a282926d | 534 | case RK3188: |
751a99ab | 535 | data >>= bit; |
6ca5274d HS |
536 | data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; |
537 | ||
538 | switch (data) { | |
539 | case 0: | |
540 | return PIN_CONFIG_BIAS_DISABLE; | |
541 | case 1: | |
542 | return PIN_CONFIG_BIAS_PULL_UP; | |
543 | case 2: | |
544 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
545 | case 3: | |
546 | return PIN_CONFIG_BIAS_BUS_HOLD; | |
547 | } | |
548 | ||
549 | dev_err(info->dev, "unknown pull setting\n"); | |
d3e51161 | 550 | return -EIO; |
a282926d HS |
551 | default: |
552 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
553 | return -EINVAL; | |
554 | }; | |
d3e51161 HS |
555 | } |
556 | ||
557 | static int rockchip_set_pull(struct rockchip_pin_bank *bank, | |
558 | int pin_num, int pull) | |
559 | { | |
560 | struct rockchip_pinctrl *info = bank->drvdata; | |
561 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
562 | struct regmap *regmap; |
563 | int reg, ret; | |
d3e51161 HS |
564 | unsigned long flags; |
565 | u8 bit; | |
566 | u32 data; | |
567 | ||
568 | dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", | |
569 | bank->bank_num, pin_num, pull); | |
570 | ||
571 | /* rk3066b does support any pulls */ | |
a282926d | 572 | if (ctrl->type == RK3066B) |
d3e51161 HS |
573 | return pull ? -EINVAL : 0; |
574 | ||
751a99ab | 575 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
6ca5274d | 576 | |
a282926d HS |
577 | switch (ctrl->type) { |
578 | case RK2928: | |
d3e51161 HS |
579 | spin_lock_irqsave(&bank->slock, flags); |
580 | ||
581 | data = BIT(bit + 16); | |
582 | if (pull == PIN_CONFIG_BIAS_DISABLE) | |
583 | data |= BIT(bit); | |
751a99ab | 584 | ret = regmap_write(regmap, reg, data); |
d3e51161 HS |
585 | |
586 | spin_unlock_irqrestore(&bank->slock, flags); | |
a282926d HS |
587 | break; |
588 | case RK3188: | |
6ca5274d HS |
589 | spin_lock_irqsave(&bank->slock, flags); |
590 | ||
591 | /* enable the write to the equivalent lower bits */ | |
592 | data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); | |
593 | ||
594 | switch (pull) { | |
595 | case PIN_CONFIG_BIAS_DISABLE: | |
596 | break; | |
597 | case PIN_CONFIG_BIAS_PULL_UP: | |
598 | data |= (1 << bit); | |
599 | break; | |
600 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
601 | data |= (2 << bit); | |
602 | break; | |
603 | case PIN_CONFIG_BIAS_BUS_HOLD: | |
604 | data |= (3 << bit); | |
605 | break; | |
606 | default: | |
d32c3e26 | 607 | spin_unlock_irqrestore(&bank->slock, flags); |
6ca5274d HS |
608 | dev_err(info->dev, "unsupported pull setting %d\n", |
609 | pull); | |
610 | return -EINVAL; | |
611 | } | |
612 | ||
751a99ab | 613 | ret = regmap_write(regmap, reg, data); |
6ca5274d HS |
614 | |
615 | spin_unlock_irqrestore(&bank->slock, flags); | |
616 | break; | |
a282926d HS |
617 | default: |
618 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
619 | return -EINVAL; | |
d3e51161 HS |
620 | } |
621 | ||
751a99ab | 622 | return ret; |
d3e51161 HS |
623 | } |
624 | ||
625 | /* | |
626 | * Pinmux_ops handling | |
627 | */ | |
628 | ||
629 | static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
630 | { | |
631 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
632 | ||
633 | return info->nfunctions; | |
634 | } | |
635 | ||
636 | static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
637 | unsigned selector) | |
638 | { | |
639 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
640 | ||
641 | return info->functions[selector].name; | |
642 | } | |
643 | ||
644 | static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, | |
645 | unsigned selector, const char * const **groups, | |
646 | unsigned * const num_groups) | |
647 | { | |
648 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
649 | ||
650 | *groups = info->functions[selector].groups; | |
651 | *num_groups = info->functions[selector].ngroups; | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
657 | unsigned group) | |
658 | { | |
659 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
660 | const unsigned int *pins = info->groups[group].pins; | |
661 | const struct rockchip_pin_config *data = info->groups[group].data; | |
662 | struct rockchip_pin_bank *bank; | |
14797189 | 663 | int cnt, ret = 0; |
d3e51161 HS |
664 | |
665 | dev_dbg(info->dev, "enable function %s group %s\n", | |
666 | info->functions[selector].name, info->groups[group].name); | |
667 | ||
668 | /* | |
669 | * for each pin in the pin group selected, program the correspoding pin | |
670 | * pin function number in the config register. | |
671 | */ | |
672 | for (cnt = 0; cnt < info->groups[group].npins; cnt++) { | |
673 | bank = pin_to_bank(info, pins[cnt]); | |
14797189 HS |
674 | ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, |
675 | data[cnt].func); | |
676 | if (ret) | |
677 | break; | |
678 | } | |
679 | ||
680 | if (ret) { | |
681 | /* revert the already done pin settings */ | |
682 | for (cnt--; cnt >= 0; cnt--) | |
683 | rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); | |
684 | ||
685 | return ret; | |
d3e51161 HS |
686 | } |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
d3e51161 HS |
691 | /* |
692 | * The calls to gpio_direction_output() and gpio_direction_input() | |
693 | * leads to this function call (via the pinctrl_gpio_direction_{input|output}() | |
694 | * function called from the gpiolib interface). | |
695 | */ | |
696 | static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
697 | struct pinctrl_gpio_range *range, | |
698 | unsigned offset, bool input) | |
699 | { | |
700 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
701 | struct rockchip_pin_bank *bank; | |
702 | struct gpio_chip *chip; | |
14797189 | 703 | int pin, ret; |
d3e51161 HS |
704 | u32 data; |
705 | ||
706 | chip = range->gc; | |
707 | bank = gc_to_pin_bank(chip); | |
708 | pin = offset - chip->base; | |
709 | ||
710 | dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", | |
711 | offset, range->name, pin, input ? "input" : "output"); | |
712 | ||
14797189 HS |
713 | ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); |
714 | if (ret < 0) | |
715 | return ret; | |
d3e51161 HS |
716 | |
717 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); | |
718 | /* set bit to 1 for output, 0 for input */ | |
719 | if (!input) | |
720 | data |= BIT(pin); | |
721 | else | |
722 | data &= ~BIT(pin); | |
723 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
728 | static const struct pinmux_ops rockchip_pmx_ops = { | |
729 | .get_functions_count = rockchip_pmx_get_funcs_count, | |
730 | .get_function_name = rockchip_pmx_get_func_name, | |
731 | .get_function_groups = rockchip_pmx_get_groups, | |
732 | .enable = rockchip_pmx_enable, | |
d3e51161 HS |
733 | .gpio_set_direction = rockchip_pmx_gpio_set_direction, |
734 | }; | |
735 | ||
736 | /* | |
737 | * Pinconf_ops handling | |
738 | */ | |
739 | ||
44b6d930 HS |
740 | static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, |
741 | enum pin_config_param pull) | |
742 | { | |
a282926d HS |
743 | switch (ctrl->type) { |
744 | case RK2928: | |
745 | return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || | |
746 | pull == PIN_CONFIG_BIAS_DISABLE); | |
747 | case RK3066B: | |
44b6d930 | 748 | return pull ? false : true; |
a282926d HS |
749 | case RK3188: |
750 | return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); | |
44b6d930 HS |
751 | } |
752 | ||
a282926d | 753 | return false; |
44b6d930 HS |
754 | } |
755 | ||
a076e2ed HS |
756 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, |
757 | unsigned offset, int value); | |
758 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); | |
759 | ||
d3e51161 HS |
760 | /* set the pin config settings for a specified pin */ |
761 | static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
03b054e9 | 762 | unsigned long *configs, unsigned num_configs) |
d3e51161 HS |
763 | { |
764 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
765 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
03b054e9 SY |
766 | enum pin_config_param param; |
767 | u16 arg; | |
768 | int i; | |
769 | int rc; | |
770 | ||
771 | for (i = 0; i < num_configs; i++) { | |
772 | param = pinconf_to_config_param(configs[i]); | |
773 | arg = pinconf_to_config_argument(configs[i]); | |
774 | ||
775 | switch (param) { | |
776 | case PIN_CONFIG_BIAS_DISABLE: | |
777 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
778 | param); | |
779 | if (rc) | |
780 | return rc; | |
781 | break; | |
782 | case PIN_CONFIG_BIAS_PULL_UP: | |
783 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
784 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 785 | case PIN_CONFIG_BIAS_BUS_HOLD: |
03b054e9 SY |
786 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
787 | return -ENOTSUPP; | |
788 | ||
789 | if (!arg) | |
790 | return -EINVAL; | |
791 | ||
792 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
793 | param); | |
794 | if (rc) | |
795 | return rc; | |
796 | break; | |
a076e2ed HS |
797 | case PIN_CONFIG_OUTPUT: |
798 | rc = rockchip_gpio_direction_output(&bank->gpio_chip, | |
799 | pin - bank->pin_base, | |
800 | arg); | |
801 | if (rc) | |
802 | return rc; | |
803 | break; | |
03b054e9 | 804 | default: |
44b6d930 | 805 | return -ENOTSUPP; |
03b054e9 SY |
806 | break; |
807 | } | |
808 | } /* for each config */ | |
d3e51161 HS |
809 | |
810 | return 0; | |
811 | } | |
812 | ||
813 | /* get the pin config settings for a specified pin */ | |
814 | static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
815 | unsigned long *config) | |
816 | { | |
817 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
818 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
819 | enum pin_config_param param = pinconf_to_config_param(*config); | |
dab3eba7 | 820 | u16 arg; |
a076e2ed | 821 | int rc; |
d3e51161 HS |
822 | |
823 | switch (param) { | |
824 | case PIN_CONFIG_BIAS_DISABLE: | |
44b6d930 HS |
825 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
826 | return -EINVAL; | |
827 | ||
dab3eba7 | 828 | arg = 0; |
44b6d930 | 829 | break; |
d3e51161 HS |
830 | case PIN_CONFIG_BIAS_PULL_UP: |
831 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
832 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 833 | case PIN_CONFIG_BIAS_BUS_HOLD: |
44b6d930 HS |
834 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
835 | return -ENOTSUPP; | |
d3e51161 | 836 | |
44b6d930 | 837 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
d3e51161 HS |
838 | return -EINVAL; |
839 | ||
dab3eba7 | 840 | arg = 1; |
d3e51161 | 841 | break; |
a076e2ed HS |
842 | case PIN_CONFIG_OUTPUT: |
843 | rc = rockchip_get_mux(bank, pin - bank->pin_base); | |
844 | if (rc != RK_FUNC_GPIO) | |
845 | return -EINVAL; | |
846 | ||
847 | rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); | |
848 | if (rc < 0) | |
849 | return rc; | |
850 | ||
851 | arg = rc ? 1 : 0; | |
852 | break; | |
d3e51161 HS |
853 | default: |
854 | return -ENOTSUPP; | |
855 | break; | |
856 | } | |
857 | ||
dab3eba7 HS |
858 | *config = pinconf_to_config_packed(param, arg); |
859 | ||
d3e51161 HS |
860 | return 0; |
861 | } | |
862 | ||
863 | static const struct pinconf_ops rockchip_pinconf_ops = { | |
864 | .pin_config_get = rockchip_pinconf_get, | |
865 | .pin_config_set = rockchip_pinconf_set, | |
866 | }; | |
867 | ||
65fca613 HS |
868 | static const struct of_device_id rockchip_bank_match[] = { |
869 | { .compatible = "rockchip,gpio-bank" }, | |
6ca5274d | 870 | { .compatible = "rockchip,rk3188-gpio-bank0" }, |
65fca613 HS |
871 | {}, |
872 | }; | |
d3e51161 HS |
873 | |
874 | static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, | |
875 | struct device_node *np) | |
876 | { | |
877 | struct device_node *child; | |
878 | ||
879 | for_each_child_of_node(np, child) { | |
65fca613 | 880 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 HS |
881 | continue; |
882 | ||
883 | info->nfunctions++; | |
884 | info->ngroups += of_get_child_count(child); | |
885 | } | |
886 | } | |
887 | ||
888 | static int rockchip_pinctrl_parse_groups(struct device_node *np, | |
889 | struct rockchip_pin_group *grp, | |
890 | struct rockchip_pinctrl *info, | |
891 | u32 index) | |
892 | { | |
893 | struct rockchip_pin_bank *bank; | |
894 | int size; | |
895 | const __be32 *list; | |
896 | int num; | |
897 | int i, j; | |
898 | int ret; | |
899 | ||
900 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
901 | ||
902 | /* Initialise group */ | |
903 | grp->name = np->name; | |
904 | ||
905 | /* | |
906 | * the binding format is rockchip,pins = <bank pin mux CONFIG>, | |
907 | * do sanity check and calculate pins number | |
908 | */ | |
909 | list = of_get_property(np, "rockchip,pins", &size); | |
910 | /* we do not check return since it's safe node passed down */ | |
911 | size /= sizeof(*list); | |
912 | if (!size || size % 4) { | |
913 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
914 | return -EINVAL; | |
915 | } | |
916 | ||
917 | grp->npins = size / 4; | |
918 | ||
919 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
920 | GFP_KERNEL); | |
921 | grp->data = devm_kzalloc(info->dev, grp->npins * | |
922 | sizeof(struct rockchip_pin_config), | |
923 | GFP_KERNEL); | |
924 | if (!grp->pins || !grp->data) | |
925 | return -ENOMEM; | |
926 | ||
927 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
928 | const __be32 *phandle; | |
929 | struct device_node *np_config; | |
930 | ||
931 | num = be32_to_cpu(*list++); | |
932 | bank = bank_num_to_bank(info, num); | |
933 | if (IS_ERR(bank)) | |
934 | return PTR_ERR(bank); | |
935 | ||
936 | grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); | |
937 | grp->data[j].func = be32_to_cpu(*list++); | |
938 | ||
939 | phandle = list++; | |
940 | if (!phandle) | |
941 | return -EINVAL; | |
942 | ||
943 | np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); | |
944 | ret = pinconf_generic_parse_dt_config(np_config, | |
945 | &grp->data[j].configs, &grp->data[j].nconfigs); | |
946 | if (ret) | |
947 | return ret; | |
948 | } | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | static int rockchip_pinctrl_parse_functions(struct device_node *np, | |
954 | struct rockchip_pinctrl *info, | |
955 | u32 index) | |
956 | { | |
957 | struct device_node *child; | |
958 | struct rockchip_pmx_func *func; | |
959 | struct rockchip_pin_group *grp; | |
960 | int ret; | |
961 | static u32 grp_index; | |
962 | u32 i = 0; | |
963 | ||
964 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
965 | ||
966 | func = &info->functions[index]; | |
967 | ||
968 | /* Initialise function */ | |
969 | func->name = np->name; | |
970 | func->ngroups = of_get_child_count(np); | |
971 | if (func->ngroups <= 0) | |
972 | return 0; | |
973 | ||
974 | func->groups = devm_kzalloc(info->dev, | |
975 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
976 | if (!func->groups) | |
977 | return -ENOMEM; | |
978 | ||
979 | for_each_child_of_node(np, child) { | |
980 | func->groups[i] = child->name; | |
981 | grp = &info->groups[grp_index++]; | |
982 | ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); | |
983 | if (ret) | |
984 | return ret; | |
985 | } | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, | |
991 | struct rockchip_pinctrl *info) | |
992 | { | |
993 | struct device *dev = &pdev->dev; | |
994 | struct device_node *np = dev->of_node; | |
995 | struct device_node *child; | |
996 | int ret; | |
997 | int i; | |
998 | ||
999 | rockchip_pinctrl_child_count(info, np); | |
1000 | ||
1001 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1002 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1003 | ||
1004 | info->functions = devm_kzalloc(dev, info->nfunctions * | |
1005 | sizeof(struct rockchip_pmx_func), | |
1006 | GFP_KERNEL); | |
1007 | if (!info->functions) { | |
1008 | dev_err(dev, "failed to allocate memory for function list\n"); | |
1009 | return -EINVAL; | |
1010 | } | |
1011 | ||
1012 | info->groups = devm_kzalloc(dev, info->ngroups * | |
1013 | sizeof(struct rockchip_pin_group), | |
1014 | GFP_KERNEL); | |
1015 | if (!info->groups) { | |
1016 | dev_err(dev, "failed allocate memory for ping group list\n"); | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | ||
1020 | i = 0; | |
1021 | ||
1022 | for_each_child_of_node(np, child) { | |
65fca613 | 1023 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 | 1024 | continue; |
65fca613 | 1025 | |
d3e51161 HS |
1026 | ret = rockchip_pinctrl_parse_functions(child, info, i++); |
1027 | if (ret) { | |
1028 | dev_err(&pdev->dev, "failed to parse function\n"); | |
1029 | return ret; | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | static int rockchip_pinctrl_register(struct platform_device *pdev, | |
1037 | struct rockchip_pinctrl *info) | |
1038 | { | |
1039 | struct pinctrl_desc *ctrldesc = &info->pctl; | |
1040 | struct pinctrl_pin_desc *pindesc, *pdesc; | |
1041 | struct rockchip_pin_bank *pin_bank; | |
1042 | int pin, bank, ret; | |
1043 | int k; | |
1044 | ||
1045 | ctrldesc->name = "rockchip-pinctrl"; | |
1046 | ctrldesc->owner = THIS_MODULE; | |
1047 | ctrldesc->pctlops = &rockchip_pctrl_ops; | |
1048 | ctrldesc->pmxops = &rockchip_pmx_ops; | |
1049 | ctrldesc->confops = &rockchip_pinconf_ops; | |
1050 | ||
1051 | pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * | |
1052 | info->ctrl->nr_pins, GFP_KERNEL); | |
1053 | if (!pindesc) { | |
1054 | dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); | |
1055 | return -ENOMEM; | |
1056 | } | |
1057 | ctrldesc->pins = pindesc; | |
1058 | ctrldesc->npins = info->ctrl->nr_pins; | |
1059 | ||
1060 | pdesc = pindesc; | |
1061 | for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { | |
1062 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1063 | for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { | |
1064 | pdesc->number = k; | |
1065 | pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", | |
1066 | pin_bank->name, pin); | |
1067 | pdesc++; | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); | |
1072 | if (!info->pctl_dev) { | |
1073 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); | |
1074 | return -EINVAL; | |
1075 | } | |
1076 | ||
1077 | for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { | |
1078 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1079 | pin_bank->grange.name = pin_bank->name; | |
1080 | pin_bank->grange.id = bank; | |
1081 | pin_bank->grange.pin_base = pin_bank->pin_base; | |
1082 | pin_bank->grange.base = pin_bank->gpio_chip.base; | |
1083 | pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; | |
1084 | pin_bank->grange.gc = &pin_bank->gpio_chip; | |
1085 | pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); | |
1086 | } | |
1087 | ||
1088 | ret = rockchip_pinctrl_parse_dt(pdev, info); | |
1089 | if (ret) { | |
1090 | pinctrl_unregister(info->pctl_dev); | |
1091 | return ret; | |
1092 | } | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
1097 | /* | |
1098 | * GPIO handling | |
1099 | */ | |
1100 | ||
0351c287 AL |
1101 | static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) |
1102 | { | |
1103 | return pinctrl_request_gpio(chip->base + offset); | |
1104 | } | |
1105 | ||
1106 | static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1107 | { | |
1108 | pinctrl_free_gpio(chip->base + offset); | |
1109 | } | |
1110 | ||
d3e51161 HS |
1111 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) |
1112 | { | |
1113 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1114 | void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; | |
1115 | unsigned long flags; | |
1116 | u32 data; | |
1117 | ||
1118 | spin_lock_irqsave(&bank->slock, flags); | |
1119 | ||
1120 | data = readl(reg); | |
1121 | data &= ~BIT(offset); | |
1122 | if (value) | |
1123 | data |= BIT(offset); | |
1124 | writel(data, reg); | |
1125 | ||
1126 | spin_unlock_irqrestore(&bank->slock, flags); | |
1127 | } | |
1128 | ||
1129 | /* | |
1130 | * Returns the level of the pin for input direction and setting of the DR | |
1131 | * register for output gpios. | |
1132 | */ | |
1133 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) | |
1134 | { | |
1135 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1136 | u32 data; | |
1137 | ||
1138 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1139 | data >>= offset; | |
1140 | data &= 1; | |
1141 | return data; | |
1142 | } | |
1143 | ||
1144 | /* | |
1145 | * gpiolib gpio_direction_input callback function. The setting of the pin | |
1146 | * mux function as 'gpio input' will be handled by the pinctrl susbsystem | |
1147 | * interface. | |
1148 | */ | |
1149 | static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) | |
1150 | { | |
1151 | return pinctrl_gpio_direction_input(gc->base + offset); | |
1152 | } | |
1153 | ||
1154 | /* | |
1155 | * gpiolib gpio_direction_output callback function. The setting of the pin | |
1156 | * mux function as 'gpio output' will be handled by the pinctrl susbsystem | |
1157 | * interface. | |
1158 | */ | |
1159 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, | |
1160 | unsigned offset, int value) | |
1161 | { | |
1162 | rockchip_gpio_set(gc, offset, value); | |
1163 | return pinctrl_gpio_direction_output(gc->base + offset); | |
1164 | } | |
1165 | ||
1166 | /* | |
1167 | * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin | |
1168 | * and a virtual IRQ, if not already present. | |
1169 | */ | |
1170 | static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
1171 | { | |
1172 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1173 | unsigned int virq; | |
1174 | ||
1175 | if (!bank->domain) | |
1176 | return -ENXIO; | |
1177 | ||
1178 | virq = irq_create_mapping(bank->domain, offset); | |
1179 | ||
1180 | return (virq) ? : -ENXIO; | |
1181 | } | |
1182 | ||
1183 | static const struct gpio_chip rockchip_gpiolib_chip = { | |
0351c287 AL |
1184 | .request = rockchip_gpio_request, |
1185 | .free = rockchip_gpio_free, | |
d3e51161 HS |
1186 | .set = rockchip_gpio_set, |
1187 | .get = rockchip_gpio_get, | |
1188 | .direction_input = rockchip_gpio_direction_input, | |
1189 | .direction_output = rockchip_gpio_direction_output, | |
1190 | .to_irq = rockchip_gpio_to_irq, | |
1191 | .owner = THIS_MODULE, | |
1192 | }; | |
1193 | ||
1194 | /* | |
1195 | * Interrupt handling | |
1196 | */ | |
1197 | ||
1198 | static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) | |
1199 | { | |
1200 | struct irq_chip *chip = irq_get_chip(irq); | |
1201 | struct rockchip_pin_bank *bank = irq_get_handler_data(irq); | |
5a927501 | 1202 | u32 polarity = 0, data = 0; |
d3e51161 | 1203 | u32 pend; |
5a927501 | 1204 | bool edge_changed = false; |
d3e51161 HS |
1205 | |
1206 | dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); | |
1207 | ||
1208 | chained_irq_enter(chip, desc); | |
1209 | ||
1210 | pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); | |
1211 | ||
5a927501 HS |
1212 | if (bank->toggle_edge_mode) { |
1213 | polarity = readl_relaxed(bank->reg_base + | |
1214 | GPIO_INT_POLARITY); | |
1215 | data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); | |
1216 | } | |
1217 | ||
d3e51161 HS |
1218 | while (pend) { |
1219 | unsigned int virq; | |
1220 | ||
1221 | irq = __ffs(pend); | |
1222 | pend &= ~BIT(irq); | |
1223 | virq = irq_linear_revmap(bank->domain, irq); | |
1224 | ||
1225 | if (!virq) { | |
1226 | dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); | |
1227 | continue; | |
1228 | } | |
1229 | ||
1230 | dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); | |
1231 | ||
5a927501 HS |
1232 | /* |
1233 | * Triggering IRQ on both rising and falling edge | |
1234 | * needs manual intervention. | |
1235 | */ | |
1236 | if (bank->toggle_edge_mode & BIT(irq)) { | |
1237 | if (data & BIT(irq)) | |
1238 | polarity &= ~BIT(irq); | |
1239 | else | |
1240 | polarity |= BIT(irq); | |
1241 | ||
1242 | edge_changed = true; | |
1243 | } | |
1244 | ||
d3e51161 HS |
1245 | generic_handle_irq(virq); |
1246 | } | |
1247 | ||
5a927501 HS |
1248 | if (bank->toggle_edge_mode && edge_changed) { |
1249 | /* Interrupt params should only be set with ints disabled */ | |
1250 | data = readl_relaxed(bank->reg_base + GPIO_INTEN); | |
1251 | writel_relaxed(0, bank->reg_base + GPIO_INTEN); | |
1252 | writel(polarity, bank->reg_base + GPIO_INT_POLARITY); | |
1253 | writel(data, bank->reg_base + GPIO_INTEN); | |
1254 | } | |
1255 | ||
d3e51161 HS |
1256 | chained_irq_exit(chip, desc); |
1257 | } | |
1258 | ||
1259 | static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) | |
1260 | { | |
1261 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1262 | struct rockchip_pin_bank *bank = gc->private; | |
1263 | u32 mask = BIT(d->hwirq); | |
1264 | u32 polarity; | |
1265 | u32 level; | |
1266 | u32 data; | |
14797189 | 1267 | int ret; |
d3e51161 | 1268 | |
5a927501 | 1269 | /* make sure the pin is configured as gpio input */ |
14797189 HS |
1270 | ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); |
1271 | if (ret < 0) | |
1272 | return ret; | |
1273 | ||
5a927501 HS |
1274 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
1275 | data &= ~mask; | |
1276 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
1277 | ||
d3e51161 HS |
1278 | if (type & IRQ_TYPE_EDGE_BOTH) |
1279 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
1280 | else | |
1281 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
1282 | ||
1283 | irq_gc_lock(gc); | |
1284 | ||
1285 | level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1286 | polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); | |
1287 | ||
1288 | switch (type) { | |
5a927501 HS |
1289 | case IRQ_TYPE_EDGE_BOTH: |
1290 | bank->toggle_edge_mode |= mask; | |
1291 | level |= mask; | |
1292 | ||
1293 | /* | |
1294 | * Determine gpio state. If 1 next interrupt should be falling | |
1295 | * otherwise rising. | |
1296 | */ | |
1297 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1298 | if (data & mask) | |
1299 | polarity &= ~mask; | |
1300 | else | |
1301 | polarity |= mask; | |
1302 | break; | |
d3e51161 | 1303 | case IRQ_TYPE_EDGE_RISING: |
5a927501 | 1304 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1305 | level |= mask; |
1306 | polarity |= mask; | |
1307 | break; | |
1308 | case IRQ_TYPE_EDGE_FALLING: | |
5a927501 | 1309 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1310 | level |= mask; |
1311 | polarity &= ~mask; | |
1312 | break; | |
1313 | case IRQ_TYPE_LEVEL_HIGH: | |
5a927501 | 1314 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1315 | level &= ~mask; |
1316 | polarity |= mask; | |
1317 | break; | |
1318 | case IRQ_TYPE_LEVEL_LOW: | |
5a927501 | 1319 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1320 | level &= ~mask; |
1321 | polarity &= ~mask; | |
1322 | break; | |
1323 | default: | |
7cc5f970 | 1324 | irq_gc_unlock(gc); |
d3e51161 HS |
1325 | return -EINVAL; |
1326 | } | |
1327 | ||
1328 | writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1329 | writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); | |
1330 | ||
1331 | irq_gc_unlock(gc); | |
1332 | ||
d3e51161 HS |
1333 | return 0; |
1334 | } | |
1335 | ||
1336 | static int rockchip_interrupts_register(struct platform_device *pdev, | |
1337 | struct rockchip_pinctrl *info) | |
1338 | { | |
1339 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1340 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1341 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
1342 | struct irq_chip_generic *gc; | |
1343 | int ret; | |
1344 | int i; | |
1345 | ||
1346 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1347 | if (!bank->valid) { | |
1348 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1349 | bank->name); | |
1350 | continue; | |
1351 | } | |
1352 | ||
1353 | bank->domain = irq_domain_add_linear(bank->of_node, 32, | |
1354 | &irq_generic_chip_ops, NULL); | |
1355 | if (!bank->domain) { | |
1356 | dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", | |
1357 | bank->name); | |
1358 | continue; | |
1359 | } | |
1360 | ||
1361 | ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, | |
1362 | "rockchip_gpio_irq", handle_level_irq, | |
1363 | clr, 0, IRQ_GC_INIT_MASK_CACHE); | |
1364 | if (ret) { | |
1365 | dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", | |
1366 | bank->name); | |
1367 | irq_domain_remove(bank->domain); | |
1368 | continue; | |
1369 | } | |
1370 | ||
1371 | gc = irq_get_domain_generic_chip(bank->domain, 0); | |
1372 | gc->reg_base = bank->reg_base; | |
1373 | gc->private = bank; | |
1374 | gc->chip_types[0].regs.mask = GPIO_INTEN; | |
1375 | gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; | |
1376 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; | |
1377 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; | |
1378 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; | |
1379 | gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; | |
1380 | gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; | |
1381 | ||
1382 | irq_set_handler_data(bank->irq, bank); | |
1383 | irq_set_chained_handler(bank->irq, rockchip_irq_demux); | |
1384 | } | |
1385 | ||
1386 | return 0; | |
1387 | } | |
1388 | ||
1389 | static int rockchip_gpiolib_register(struct platform_device *pdev, | |
1390 | struct rockchip_pinctrl *info) | |
1391 | { | |
1392 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1393 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1394 | struct gpio_chip *gc; | |
1395 | int ret; | |
1396 | int i; | |
1397 | ||
1398 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1399 | if (!bank->valid) { | |
1400 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1401 | bank->name); | |
1402 | continue; | |
1403 | } | |
1404 | ||
1405 | bank->gpio_chip = rockchip_gpiolib_chip; | |
1406 | ||
1407 | gc = &bank->gpio_chip; | |
1408 | gc->base = bank->pin_base; | |
1409 | gc->ngpio = bank->nr_pins; | |
1410 | gc->dev = &pdev->dev; | |
1411 | gc->of_node = bank->of_node; | |
1412 | gc->label = bank->name; | |
1413 | ||
1414 | ret = gpiochip_add(gc); | |
1415 | if (ret) { | |
1416 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", | |
1417 | gc->label, ret); | |
1418 | goto fail; | |
1419 | } | |
1420 | } | |
1421 | ||
1422 | rockchip_interrupts_register(pdev, info); | |
1423 | ||
1424 | return 0; | |
1425 | ||
1426 | fail: | |
1427 | for (--i, --bank; i >= 0; --i, --bank) { | |
1428 | if (!bank->valid) | |
1429 | continue; | |
1430 | ||
1431 | if (gpiochip_remove(&bank->gpio_chip)) | |
1432 | dev_err(&pdev->dev, "gpio chip %s remove failed\n", | |
1433 | bank->gpio_chip.label); | |
1434 | } | |
1435 | return ret; | |
1436 | } | |
1437 | ||
1438 | static int rockchip_gpiolib_unregister(struct platform_device *pdev, | |
1439 | struct rockchip_pinctrl *info) | |
1440 | { | |
1441 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1442 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1443 | int ret = 0; | |
1444 | int i; | |
1445 | ||
1446 | for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { | |
1447 | if (!bank->valid) | |
1448 | continue; | |
1449 | ||
1450 | ret = gpiochip_remove(&bank->gpio_chip); | |
1451 | } | |
1452 | ||
1453 | if (ret) | |
1454 | dev_err(&pdev->dev, "gpio chip remove failed\n"); | |
1455 | ||
1456 | return ret; | |
1457 | } | |
1458 | ||
1459 | static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, | |
622f3237 | 1460 | struct rockchip_pinctrl *info) |
d3e51161 HS |
1461 | { |
1462 | struct resource res; | |
751a99ab | 1463 | void __iomem *base; |
d3e51161 HS |
1464 | |
1465 | if (of_address_to_resource(bank->of_node, 0, &res)) { | |
622f3237 | 1466 | dev_err(info->dev, "cannot find IO resource for bank\n"); |
d3e51161 HS |
1467 | return -ENOENT; |
1468 | } | |
1469 | ||
622f3237 | 1470 | bank->reg_base = devm_ioremap_resource(info->dev, &res); |
d3e51161 HS |
1471 | if (IS_ERR(bank->reg_base)) |
1472 | return PTR_ERR(bank->reg_base); | |
1473 | ||
6ca5274d HS |
1474 | /* |
1475 | * special case, where parts of the pull setting-registers are | |
1476 | * part of the PMU register space | |
1477 | */ | |
1478 | if (of_device_is_compatible(bank->of_node, | |
1479 | "rockchip,rk3188-gpio-bank0")) { | |
a658efaa | 1480 | struct device_node *node; |
bfc7a42a | 1481 | |
a658efaa HS |
1482 | node = of_parse_phandle(bank->of_node->parent, |
1483 | "rockchip,pmu", 0); | |
1484 | if (!node) { | |
1485 | if (of_address_to_resource(bank->of_node, 1, &res)) { | |
1486 | dev_err(info->dev, "cannot find IO resource for bank\n"); | |
1487 | return -ENOENT; | |
1488 | } | |
1489 | ||
1490 | base = devm_ioremap_resource(info->dev, &res); | |
1491 | if (IS_ERR(base)) | |
1492 | return PTR_ERR(base); | |
1493 | rockchip_regmap_config.max_register = | |
1494 | resource_size(&res) - 4; | |
1495 | rockchip_regmap_config.name = | |
1496 | "rockchip,rk3188-gpio-bank0-pull"; | |
1497 | bank->regmap_pull = devm_regmap_init_mmio(info->dev, | |
1498 | base, | |
1499 | &rockchip_regmap_config); | |
6ca5274d | 1500 | } |
6ca5274d | 1501 | } |
65fca613 | 1502 | |
d3e51161 HS |
1503 | bank->irq = irq_of_parse_and_map(bank->of_node, 0); |
1504 | ||
1505 | bank->clk = of_clk_get(bank->of_node, 0); | |
1506 | if (IS_ERR(bank->clk)) | |
1507 | return PTR_ERR(bank->clk); | |
1508 | ||
1509 | return clk_prepare_enable(bank->clk); | |
1510 | } | |
1511 | ||
1512 | static const struct of_device_id rockchip_pinctrl_dt_match[]; | |
1513 | ||
1514 | /* retrieve the soc specific data */ | |
1515 | static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( | |
1516 | struct rockchip_pinctrl *d, | |
1517 | struct platform_device *pdev) | |
1518 | { | |
1519 | const struct of_device_id *match; | |
1520 | struct device_node *node = pdev->dev.of_node; | |
1521 | struct device_node *np; | |
1522 | struct rockchip_pin_ctrl *ctrl; | |
1523 | struct rockchip_pin_bank *bank; | |
6bc0d121 | 1524 | int grf_offs, i, j; |
d3e51161 HS |
1525 | |
1526 | match = of_match_node(rockchip_pinctrl_dt_match, node); | |
1527 | ctrl = (struct rockchip_pin_ctrl *)match->data; | |
1528 | ||
1529 | for_each_child_of_node(node, np) { | |
1530 | if (!of_find_property(np, "gpio-controller", NULL)) | |
1531 | continue; | |
1532 | ||
1533 | bank = ctrl->pin_banks; | |
1534 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1535 | if (!strcmp(bank->name, np->name)) { | |
1536 | bank->of_node = np; | |
1537 | ||
622f3237 | 1538 | if (!rockchip_get_bank_data(bank, d)) |
d3e51161 HS |
1539 | bank->valid = true; |
1540 | ||
1541 | break; | |
1542 | } | |
1543 | } | |
1544 | } | |
1545 | ||
6bc0d121 | 1546 | grf_offs = ctrl->mux_offset; |
d3e51161 HS |
1547 | bank = ctrl->pin_banks; |
1548 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
6bc0d121 HS |
1549 | int bank_pins = 0; |
1550 | ||
d3e51161 HS |
1551 | spin_lock_init(&bank->slock); |
1552 | bank->drvdata = d; | |
1553 | bank->pin_base = ctrl->nr_pins; | |
1554 | ctrl->nr_pins += bank->nr_pins; | |
6bc0d121 HS |
1555 | |
1556 | /* calculate iomux offsets */ | |
1557 | for (j = 0; j < 4; j++) { | |
1558 | struct rockchip_iomux *iom = &bank->iomux[j]; | |
1559 | ||
1560 | if (bank_pins >= bank->nr_pins) | |
1561 | break; | |
1562 | ||
1563 | /* preset offset value, set new start value */ | |
1564 | if (iom->offset >= 0) { | |
1565 | grf_offs = iom->offset; | |
1566 | } else { /* set current offset */ | |
1567 | iom->offset = grf_offs; | |
1568 | } | |
1569 | ||
1570 | dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", | |
1571 | i, j, iom->offset); | |
1572 | ||
1573 | /* | |
1574 | * Increase offset according to iomux width. | |
1575 | */ | |
1576 | grf_offs += 4; | |
1577 | ||
1578 | bank_pins += 8; | |
1579 | } | |
d3e51161 HS |
1580 | } |
1581 | ||
1582 | return ctrl; | |
1583 | } | |
1584 | ||
1585 | static int rockchip_pinctrl_probe(struct platform_device *pdev) | |
1586 | { | |
1587 | struct rockchip_pinctrl *info; | |
1588 | struct device *dev = &pdev->dev; | |
1589 | struct rockchip_pin_ctrl *ctrl; | |
14dee867 | 1590 | struct device_node *np = pdev->dev.of_node, *node; |
d3e51161 | 1591 | struct resource *res; |
751a99ab | 1592 | void __iomem *base; |
d3e51161 HS |
1593 | int ret; |
1594 | ||
1595 | if (!dev->of_node) { | |
1596 | dev_err(dev, "device tree node not found\n"); | |
1597 | return -ENODEV; | |
1598 | } | |
1599 | ||
1600 | info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); | |
1601 | if (!info) | |
1602 | return -ENOMEM; | |
1603 | ||
622f3237 HS |
1604 | info->dev = dev; |
1605 | ||
d3e51161 HS |
1606 | ctrl = rockchip_pinctrl_get_soc_data(info, pdev); |
1607 | if (!ctrl) { | |
1608 | dev_err(dev, "driver data not available\n"); | |
1609 | return -EINVAL; | |
1610 | } | |
1611 | info->ctrl = ctrl; | |
d3e51161 | 1612 | |
1e747e59 HS |
1613 | node = of_parse_phandle(np, "rockchip,grf", 0); |
1614 | if (node) { | |
1615 | info->regmap_base = syscon_node_to_regmap(node); | |
1616 | if (IS_ERR(info->regmap_base)) | |
1617 | return PTR_ERR(info->regmap_base); | |
1618 | } else { | |
1619 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
751a99ab HS |
1620 | base = devm_ioremap_resource(&pdev->dev, res); |
1621 | if (IS_ERR(base)) | |
1622 | return PTR_ERR(base); | |
1623 | ||
1624 | rockchip_regmap_config.max_register = resource_size(res) - 4; | |
1e747e59 HS |
1625 | rockchip_regmap_config.name = "rockchip,pinctrl"; |
1626 | info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, | |
1627 | &rockchip_regmap_config); | |
1628 | ||
1629 | /* to check for the old dt-bindings */ | |
1630 | info->reg_size = resource_size(res); | |
1631 | ||
1632 | /* Honor the old binding, with pull registers as 2nd resource */ | |
1633 | if (ctrl->type == RK3188 && info->reg_size < 0x200) { | |
1634 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1635 | base = devm_ioremap_resource(&pdev->dev, res); | |
1636 | if (IS_ERR(base)) | |
1637 | return PTR_ERR(base); | |
1638 | ||
1639 | rockchip_regmap_config.max_register = | |
1640 | resource_size(res) - 4; | |
1641 | rockchip_regmap_config.name = "rockchip,pinctrl-pull"; | |
1642 | info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, | |
1643 | base, | |
1644 | &rockchip_regmap_config); | |
1645 | } | |
6ca5274d HS |
1646 | } |
1647 | ||
14dee867 HS |
1648 | /* try to find the optional reference to the pmu syscon */ |
1649 | node = of_parse_phandle(np, "rockchip,pmu", 0); | |
1650 | if (node) { | |
1651 | info->regmap_pmu = syscon_node_to_regmap(node); | |
1652 | if (IS_ERR(info->regmap_pmu)) | |
1653 | return PTR_ERR(info->regmap_pmu); | |
1654 | } | |
1655 | ||
d3e51161 HS |
1656 | ret = rockchip_gpiolib_register(pdev, info); |
1657 | if (ret) | |
1658 | return ret; | |
1659 | ||
1660 | ret = rockchip_pinctrl_register(pdev, info); | |
1661 | if (ret) { | |
1662 | rockchip_gpiolib_unregister(pdev, info); | |
1663 | return ret; | |
1664 | } | |
1665 | ||
1666 | platform_set_drvdata(pdev, info); | |
1667 | ||
1668 | return 0; | |
1669 | } | |
1670 | ||
1671 | static struct rockchip_pin_bank rk2928_pin_banks[] = { | |
1672 | PIN_BANK(0, 32, "gpio0"), | |
1673 | PIN_BANK(1, 32, "gpio1"), | |
1674 | PIN_BANK(2, 32, "gpio2"), | |
1675 | PIN_BANK(3, 32, "gpio3"), | |
1676 | }; | |
1677 | ||
1678 | static struct rockchip_pin_ctrl rk2928_pin_ctrl = { | |
1679 | .pin_banks = rk2928_pin_banks, | |
1680 | .nr_banks = ARRAY_SIZE(rk2928_pin_banks), | |
1681 | .label = "RK2928-GPIO", | |
a282926d | 1682 | .type = RK2928, |
d3e51161 | 1683 | .mux_offset = 0xa8, |
a282926d | 1684 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
1685 | }; |
1686 | ||
1687 | static struct rockchip_pin_bank rk3066a_pin_banks[] = { | |
1688 | PIN_BANK(0, 32, "gpio0"), | |
1689 | PIN_BANK(1, 32, "gpio1"), | |
1690 | PIN_BANK(2, 32, "gpio2"), | |
1691 | PIN_BANK(3, 32, "gpio3"), | |
1692 | PIN_BANK(4, 32, "gpio4"), | |
1693 | PIN_BANK(6, 16, "gpio6"), | |
1694 | }; | |
1695 | ||
1696 | static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { | |
1697 | .pin_banks = rk3066a_pin_banks, | |
1698 | .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), | |
1699 | .label = "RK3066a-GPIO", | |
a282926d | 1700 | .type = RK2928, |
d3e51161 | 1701 | .mux_offset = 0xa8, |
a282926d | 1702 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
1703 | }; |
1704 | ||
1705 | static struct rockchip_pin_bank rk3066b_pin_banks[] = { | |
1706 | PIN_BANK(0, 32, "gpio0"), | |
1707 | PIN_BANK(1, 32, "gpio1"), | |
1708 | PIN_BANK(2, 32, "gpio2"), | |
1709 | PIN_BANK(3, 32, "gpio3"), | |
1710 | }; | |
1711 | ||
1712 | static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { | |
1713 | .pin_banks = rk3066b_pin_banks, | |
1714 | .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), | |
1715 | .label = "RK3066b-GPIO", | |
a282926d | 1716 | .type = RK3066B, |
d3e51161 | 1717 | .mux_offset = 0x60, |
d3e51161 HS |
1718 | }; |
1719 | ||
1720 | static struct rockchip_pin_bank rk3188_pin_banks[] = { | |
fc72c923 | 1721 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), |
d3e51161 HS |
1722 | PIN_BANK(1, 32, "gpio1"), |
1723 | PIN_BANK(2, 32, "gpio2"), | |
1724 | PIN_BANK(3, 32, "gpio3"), | |
1725 | }; | |
1726 | ||
1727 | static struct rockchip_pin_ctrl rk3188_pin_ctrl = { | |
1728 | .pin_banks = rk3188_pin_banks, | |
1729 | .nr_banks = ARRAY_SIZE(rk3188_pin_banks), | |
1730 | .label = "RK3188-GPIO", | |
a282926d | 1731 | .type = RK3188, |
22c0d7e3 | 1732 | .mux_offset = 0x60, |
6ca5274d | 1733 | .pull_calc_reg = rk3188_calc_pull_reg_and_bit, |
d3e51161 HS |
1734 | }; |
1735 | ||
1736 | static const struct of_device_id rockchip_pinctrl_dt_match[] = { | |
1737 | { .compatible = "rockchip,rk2928-pinctrl", | |
1738 | .data = (void *)&rk2928_pin_ctrl }, | |
1739 | { .compatible = "rockchip,rk3066a-pinctrl", | |
1740 | .data = (void *)&rk3066a_pin_ctrl }, | |
1741 | { .compatible = "rockchip,rk3066b-pinctrl", | |
1742 | .data = (void *)&rk3066b_pin_ctrl }, | |
1743 | { .compatible = "rockchip,rk3188-pinctrl", | |
1744 | .data = (void *)&rk3188_pin_ctrl }, | |
1745 | {}, | |
1746 | }; | |
1747 | MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); | |
1748 | ||
1749 | static struct platform_driver rockchip_pinctrl_driver = { | |
1750 | .probe = rockchip_pinctrl_probe, | |
1751 | .driver = { | |
1752 | .name = "rockchip-pinctrl", | |
1753 | .owner = THIS_MODULE, | |
0be9e70d | 1754 | .of_match_table = rockchip_pinctrl_dt_match, |
d3e51161 HS |
1755 | }, |
1756 | }; | |
1757 | ||
1758 | static int __init rockchip_pinctrl_drv_register(void) | |
1759 | { | |
1760 | return platform_driver_register(&rockchip_pinctrl_driver); | |
1761 | } | |
1762 | postcore_initcall(rockchip_pinctrl_drv_register); | |
1763 | ||
1764 | MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); | |
1765 | MODULE_DESCRIPTION("Rockchip pinctrl driver"); | |
1766 | MODULE_LICENSE("GPL v2"); |