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d3e51161 HS |
1 | /* |
2 | * Pinctrl driver for Rockchip SoCs | |
3 | * | |
4 | * Copyright (c) 2013 MundoReader S.L. | |
5 | * Author: Heiko Stuebner <heiko@sntech.de> | |
6 | * | |
7 | * With some ideas taken from pinctrl-samsung: | |
8 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
9 | * http://www.samsung.com | |
10 | * Copyright (c) 2012 Linaro Ltd | |
11 | * http://www.linaro.org | |
12 | * | |
13 | * and pinctrl-at91: | |
14 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as published | |
18 | * by the Free Software Foundation. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | */ | |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/bitops.h> | |
30 | #include <linux/gpio.h> | |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_irq.h> | |
33 | #include <linux/pinctrl/machine.h> | |
34 | #include <linux/pinctrl/pinconf.h> | |
35 | #include <linux/pinctrl/pinctrl.h> | |
36 | #include <linux/pinctrl/pinmux.h> | |
37 | #include <linux/pinctrl/pinconf-generic.h> | |
38 | #include <linux/irqchip/chained_irq.h> | |
7e865abb | 39 | #include <linux/clk.h> |
751a99ab | 40 | #include <linux/regmap.h> |
14dee867 | 41 | #include <linux/mfd/syscon.h> |
d3e51161 HS |
42 | #include <dt-bindings/pinctrl/rockchip.h> |
43 | ||
44 | #include "core.h" | |
45 | #include "pinconf.h" | |
46 | ||
47 | /* GPIO control registers */ | |
48 | #define GPIO_SWPORT_DR 0x00 | |
49 | #define GPIO_SWPORT_DDR 0x04 | |
50 | #define GPIO_INTEN 0x30 | |
51 | #define GPIO_INTMASK 0x34 | |
52 | #define GPIO_INTTYPE_LEVEL 0x38 | |
53 | #define GPIO_INT_POLARITY 0x3c | |
54 | #define GPIO_INT_STATUS 0x40 | |
55 | #define GPIO_INT_RAWSTATUS 0x44 | |
56 | #define GPIO_DEBOUNCE 0x48 | |
57 | #define GPIO_PORTS_EOI 0x4c | |
58 | #define GPIO_EXT_PORT 0x50 | |
59 | #define GPIO_LS_SYNC 0x60 | |
60 | ||
a282926d HS |
61 | enum rockchip_pinctrl_type { |
62 | RK2928, | |
63 | RK3066B, | |
64 | RK3188, | |
65 | }; | |
66 | ||
fc72c923 HS |
67 | /** |
68 | * Encode variants of iomux registers into a type variable | |
69 | */ | |
70 | #define IOMUX_GPIO_ONLY BIT(0) | |
03716e1d | 71 | #define IOMUX_WIDTH_4BIT BIT(1) |
95ec8ae4 | 72 | #define IOMUX_SOURCE_PMU BIT(2) |
62f49226 | 73 | #define IOMUX_UNROUTED BIT(3) |
fc72c923 HS |
74 | |
75 | /** | |
76 | * @type: iomux variant using IOMUX_* constants | |
6bc0d121 HS |
77 | * @offset: if initialized to -1 it will be autocalculated, by specifying |
78 | * an initial offset value the relevant source offset can be reset | |
79 | * to a new value for autocalculating the following iomux registers. | |
fc72c923 HS |
80 | */ |
81 | struct rockchip_iomux { | |
82 | int type; | |
6bc0d121 | 83 | int offset; |
65fca613 HS |
84 | }; |
85 | ||
d3e51161 HS |
86 | /** |
87 | * @reg_base: register base of the gpio bank | |
6ca5274d | 88 | * @reg_pull: optional separate register for additional pull settings |
d3e51161 HS |
89 | * @clk: clock of the gpio bank |
90 | * @irq: interrupt of the gpio bank | |
91 | * @pin_base: first pin number | |
92 | * @nr_pins: number of pins in this bank | |
93 | * @name: name of the bank | |
94 | * @bank_num: number of the bank, to account for holes | |
fc72c923 | 95 | * @iomux: array describing the 4 iomux sources of the bank |
d3e51161 HS |
96 | * @valid: are all necessary informations present |
97 | * @of_node: dt node of this bank | |
98 | * @drvdata: common pinctrl basedata | |
99 | * @domain: irqdomain of the gpio bank | |
100 | * @gpio_chip: gpiolib chip | |
101 | * @grange: gpio range | |
102 | * @slock: spinlock for the gpio bank | |
103 | */ | |
104 | struct rockchip_pin_bank { | |
105 | void __iomem *reg_base; | |
751a99ab | 106 | struct regmap *regmap_pull; |
d3e51161 HS |
107 | struct clk *clk; |
108 | int irq; | |
109 | u32 pin_base; | |
110 | u8 nr_pins; | |
111 | char *name; | |
112 | u8 bank_num; | |
fc72c923 | 113 | struct rockchip_iomux iomux[4]; |
d3e51161 HS |
114 | bool valid; |
115 | struct device_node *of_node; | |
116 | struct rockchip_pinctrl *drvdata; | |
117 | struct irq_domain *domain; | |
118 | struct gpio_chip gpio_chip; | |
119 | struct pinctrl_gpio_range grange; | |
120 | spinlock_t slock; | |
5a927501 | 121 | u32 toggle_edge_mode; |
d3e51161 HS |
122 | }; |
123 | ||
124 | #define PIN_BANK(id, pins, label) \ | |
125 | { \ | |
126 | .bank_num = id, \ | |
127 | .nr_pins = pins, \ | |
128 | .name = label, \ | |
6bc0d121 HS |
129 | .iomux = { \ |
130 | { .offset = -1 }, \ | |
131 | { .offset = -1 }, \ | |
132 | { .offset = -1 }, \ | |
133 | { .offset = -1 }, \ | |
134 | }, \ | |
d3e51161 HS |
135 | } |
136 | ||
fc72c923 HS |
137 | #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ |
138 | { \ | |
139 | .bank_num = id, \ | |
140 | .nr_pins = pins, \ | |
141 | .name = label, \ | |
142 | .iomux = { \ | |
6bc0d121 HS |
143 | { .type = iom0, .offset = -1 }, \ |
144 | { .type = iom1, .offset = -1 }, \ | |
145 | { .type = iom2, .offset = -1 }, \ | |
146 | { .type = iom3, .offset = -1 }, \ | |
fc72c923 HS |
147 | }, \ |
148 | } | |
149 | ||
d3e51161 | 150 | /** |
d3e51161 HS |
151 | */ |
152 | struct rockchip_pin_ctrl { | |
153 | struct rockchip_pin_bank *pin_banks; | |
154 | u32 nr_banks; | |
155 | u32 nr_pins; | |
156 | char *label; | |
a282926d | 157 | enum rockchip_pinctrl_type type; |
95ec8ae4 HS |
158 | int grf_mux_offset; |
159 | int pmu_mux_offset; | |
751a99ab HS |
160 | void (*pull_calc_reg)(struct rockchip_pin_bank *bank, |
161 | int pin_num, struct regmap **regmap, | |
162 | int *reg, u8 *bit); | |
d3e51161 HS |
163 | }; |
164 | ||
165 | struct rockchip_pin_config { | |
166 | unsigned int func; | |
167 | unsigned long *configs; | |
168 | unsigned int nconfigs; | |
169 | }; | |
170 | ||
171 | /** | |
172 | * struct rockchip_pin_group: represent group of pins of a pinmux function. | |
173 | * @name: name of the pin group, used to lookup the group. | |
174 | * @pins: the pins included in this group. | |
175 | * @npins: number of pins included in this group. | |
176 | * @func: the mux function number to be programmed when selected. | |
177 | * @configs: the config values to be set for each pin | |
178 | * @nconfigs: number of configs for each pin | |
179 | */ | |
180 | struct rockchip_pin_group { | |
181 | const char *name; | |
182 | unsigned int npins; | |
183 | unsigned int *pins; | |
184 | struct rockchip_pin_config *data; | |
185 | }; | |
186 | ||
187 | /** | |
188 | * struct rockchip_pmx_func: represent a pin function. | |
189 | * @name: name of the pin function, used to lookup the function. | |
190 | * @groups: one or more names of pin groups that provide this function. | |
191 | * @num_groups: number of groups included in @groups. | |
192 | */ | |
193 | struct rockchip_pmx_func { | |
194 | const char *name; | |
195 | const char **groups; | |
196 | u8 ngroups; | |
197 | }; | |
198 | ||
199 | struct rockchip_pinctrl { | |
751a99ab | 200 | struct regmap *regmap_base; |
bfc7a42a | 201 | int reg_size; |
751a99ab | 202 | struct regmap *regmap_pull; |
14dee867 | 203 | struct regmap *regmap_pmu; |
d3e51161 HS |
204 | struct device *dev; |
205 | struct rockchip_pin_ctrl *ctrl; | |
206 | struct pinctrl_desc pctl; | |
207 | struct pinctrl_dev *pctl_dev; | |
208 | struct rockchip_pin_group *groups; | |
209 | unsigned int ngroups; | |
210 | struct rockchip_pmx_func *functions; | |
211 | unsigned int nfunctions; | |
212 | }; | |
213 | ||
751a99ab HS |
214 | static struct regmap_config rockchip_regmap_config = { |
215 | .reg_bits = 32, | |
216 | .val_bits = 32, | |
217 | .reg_stride = 4, | |
218 | }; | |
219 | ||
d3e51161 HS |
220 | static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) |
221 | { | |
222 | return container_of(gc, struct rockchip_pin_bank, gpio_chip); | |
223 | } | |
224 | ||
225 | static const inline struct rockchip_pin_group *pinctrl_name_to_group( | |
226 | const struct rockchip_pinctrl *info, | |
227 | const char *name) | |
228 | { | |
d3e51161 HS |
229 | int i; |
230 | ||
231 | for (i = 0; i < info->ngroups; i++) { | |
1cb95395 AL |
232 | if (!strcmp(info->groups[i].name, name)) |
233 | return &info->groups[i]; | |
d3e51161 HS |
234 | } |
235 | ||
1cb95395 | 236 | return NULL; |
d3e51161 HS |
237 | } |
238 | ||
239 | /* | |
240 | * given a pin number that is local to a pin controller, find out the pin bank | |
241 | * and the register base of the pin bank. | |
242 | */ | |
243 | static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, | |
244 | unsigned pin) | |
245 | { | |
246 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
247 | ||
51578b9b | 248 | while (pin >= (b->pin_base + b->nr_pins)) |
d3e51161 HS |
249 | b++; |
250 | ||
251 | return b; | |
252 | } | |
253 | ||
254 | static struct rockchip_pin_bank *bank_num_to_bank( | |
255 | struct rockchip_pinctrl *info, | |
256 | unsigned num) | |
257 | { | |
258 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
259 | int i; | |
260 | ||
1cb95395 | 261 | for (i = 0; i < info->ctrl->nr_banks; i++, b++) { |
d3e51161 | 262 | if (b->bank_num == num) |
1cb95395 | 263 | return b; |
d3e51161 HS |
264 | } |
265 | ||
1cb95395 | 266 | return ERR_PTR(-EINVAL); |
d3e51161 HS |
267 | } |
268 | ||
269 | /* | |
270 | * Pinctrl_ops handling | |
271 | */ | |
272 | ||
273 | static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) | |
274 | { | |
275 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
276 | ||
277 | return info->ngroups; | |
278 | } | |
279 | ||
280 | static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, | |
281 | unsigned selector) | |
282 | { | |
283 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
284 | ||
285 | return info->groups[selector].name; | |
286 | } | |
287 | ||
288 | static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, | |
289 | unsigned selector, const unsigned **pins, | |
290 | unsigned *npins) | |
291 | { | |
292 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
293 | ||
294 | if (selector >= info->ngroups) | |
295 | return -EINVAL; | |
296 | ||
297 | *pins = info->groups[selector].pins; | |
298 | *npins = info->groups[selector].npins; | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, | |
304 | struct device_node *np, | |
305 | struct pinctrl_map **map, unsigned *num_maps) | |
306 | { | |
307 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
308 | const struct rockchip_pin_group *grp; | |
309 | struct pinctrl_map *new_map; | |
310 | struct device_node *parent; | |
311 | int map_num = 1; | |
312 | int i; | |
313 | ||
314 | /* | |
315 | * first find the group of this node and check if we need to create | |
316 | * config maps for pins | |
317 | */ | |
318 | grp = pinctrl_name_to_group(info, np->name); | |
319 | if (!grp) { | |
320 | dev_err(info->dev, "unable to find group for node %s\n", | |
321 | np->name); | |
322 | return -EINVAL; | |
323 | } | |
324 | ||
325 | map_num += grp->npins; | |
326 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, | |
327 | GFP_KERNEL); | |
328 | if (!new_map) | |
329 | return -ENOMEM; | |
330 | ||
331 | *map = new_map; | |
332 | *num_maps = map_num; | |
333 | ||
334 | /* create mux map */ | |
335 | parent = of_get_parent(np); | |
336 | if (!parent) { | |
337 | devm_kfree(pctldev->dev, new_map); | |
338 | return -EINVAL; | |
339 | } | |
340 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
341 | new_map[0].data.mux.function = parent->name; | |
342 | new_map[0].data.mux.group = np->name; | |
343 | of_node_put(parent); | |
344 | ||
345 | /* create config map */ | |
346 | new_map++; | |
347 | for (i = 0; i < grp->npins; i++) { | |
348 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
349 | new_map[i].data.configs.group_or_pin = | |
350 | pin_get_name(pctldev, grp->pins[i]); | |
351 | new_map[i].data.configs.configs = grp->data[i].configs; | |
352 | new_map[i].data.configs.num_configs = grp->data[i].nconfigs; | |
353 | } | |
354 | ||
355 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
356 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, | |
362 | struct pinctrl_map *map, unsigned num_maps) | |
363 | { | |
364 | } | |
365 | ||
366 | static const struct pinctrl_ops rockchip_pctrl_ops = { | |
367 | .get_groups_count = rockchip_get_groups_count, | |
368 | .get_group_name = rockchip_get_group_name, | |
369 | .get_group_pins = rockchip_get_group_pins, | |
370 | .dt_node_to_map = rockchip_dt_node_to_map, | |
371 | .dt_free_map = rockchip_dt_free_map, | |
372 | }; | |
373 | ||
374 | /* | |
375 | * Hardware access | |
376 | */ | |
377 | ||
a076e2ed HS |
378 | static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) |
379 | { | |
380 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 381 | int iomux_num = (pin / 8); |
95ec8ae4 | 382 | struct regmap *regmap; |
751a99ab | 383 | unsigned int val; |
03716e1d | 384 | int reg, ret, mask; |
a076e2ed HS |
385 | u8 bit; |
386 | ||
fc72c923 HS |
387 | if (iomux_num > 3) |
388 | return -EINVAL; | |
389 | ||
62f49226 HS |
390 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
391 | dev_err(info->dev, "pin %d is unrouted\n", pin); | |
392 | return -EINVAL; | |
393 | } | |
394 | ||
fc72c923 | 395 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) |
a076e2ed HS |
396 | return RK_FUNC_GPIO; |
397 | ||
95ec8ae4 HS |
398 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
399 | ? info->regmap_pmu : info->regmap_base; | |
400 | ||
a076e2ed | 401 | /* get basic quadrupel of mux registers and the correct reg inside */ |
03716e1d | 402 | mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; |
6bc0d121 | 403 | reg = bank->iomux[iomux_num].offset; |
03716e1d HS |
404 | if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { |
405 | if ((pin % 8) >= 4) | |
406 | reg += 0x4; | |
407 | bit = (pin % 4) * 4; | |
408 | } else { | |
409 | bit = (pin % 8) * 2; | |
410 | } | |
a076e2ed | 411 | |
95ec8ae4 | 412 | ret = regmap_read(regmap, reg, &val); |
751a99ab HS |
413 | if (ret) |
414 | return ret; | |
415 | ||
03716e1d | 416 | return ((val >> bit) & mask); |
a076e2ed HS |
417 | } |
418 | ||
d3e51161 HS |
419 | /* |
420 | * Set a new mux function for a pin. | |
421 | * | |
422 | * The register is divided into the upper and lower 16 bit. When changing | |
423 | * a value, the previous register value is not read and changed. Instead | |
424 | * it seems the changed bits are marked in the upper 16 bit, while the | |
425 | * changed value gets set in the same offset in the lower 16 bit. | |
426 | * All pin settings seem to be 2 bit wide in both the upper and lower | |
427 | * parts. | |
428 | * @bank: pin bank to change | |
429 | * @pin: pin to change | |
430 | * @mux: new mux function to set | |
431 | */ | |
14797189 | 432 | static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) |
d3e51161 HS |
433 | { |
434 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 435 | int iomux_num = (pin / 8); |
95ec8ae4 | 436 | struct regmap *regmap; |
03716e1d | 437 | int reg, ret, mask; |
d3e51161 HS |
438 | unsigned long flags; |
439 | u8 bit; | |
440 | u32 data; | |
441 | ||
fc72c923 HS |
442 | if (iomux_num > 3) |
443 | return -EINVAL; | |
444 | ||
62f49226 HS |
445 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
446 | dev_err(info->dev, "pin %d is unrouted\n", pin); | |
447 | return -EINVAL; | |
448 | } | |
449 | ||
fc72c923 | 450 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { |
c4a532de HS |
451 | if (mux != RK_FUNC_GPIO) { |
452 | dev_err(info->dev, | |
453 | "pin %d only supports a gpio mux\n", pin); | |
454 | return -ENOTSUPP; | |
455 | } else { | |
456 | return 0; | |
457 | } | |
458 | } | |
459 | ||
d3e51161 HS |
460 | dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", |
461 | bank->bank_num, pin, mux); | |
462 | ||
95ec8ae4 HS |
463 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
464 | ? info->regmap_pmu : info->regmap_base; | |
465 | ||
d3e51161 | 466 | /* get basic quadrupel of mux registers and the correct reg inside */ |
03716e1d | 467 | mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; |
6bc0d121 | 468 | reg = bank->iomux[iomux_num].offset; |
03716e1d HS |
469 | if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { |
470 | if ((pin % 8) >= 4) | |
471 | reg += 0x4; | |
472 | bit = (pin % 4) * 4; | |
473 | } else { | |
474 | bit = (pin % 8) * 2; | |
475 | } | |
d3e51161 HS |
476 | |
477 | spin_lock_irqsave(&bank->slock, flags); | |
478 | ||
03716e1d HS |
479 | data = (mask << (bit + 16)); |
480 | data |= (mux & mask) << bit; | |
95ec8ae4 | 481 | ret = regmap_write(regmap, reg, data); |
d3e51161 HS |
482 | |
483 | spin_unlock_irqrestore(&bank->slock, flags); | |
14797189 | 484 | |
751a99ab | 485 | return ret; |
d3e51161 HS |
486 | } |
487 | ||
a282926d HS |
488 | #define RK2928_PULL_OFFSET 0x118 |
489 | #define RK2928_PULL_PINS_PER_REG 16 | |
490 | #define RK2928_PULL_BANK_STRIDE 8 | |
491 | ||
492 | static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
493 | int pin_num, struct regmap **regmap, |
494 | int *reg, u8 *bit) | |
a282926d HS |
495 | { |
496 | struct rockchip_pinctrl *info = bank->drvdata; | |
497 | ||
751a99ab HS |
498 | *regmap = info->regmap_base; |
499 | *reg = RK2928_PULL_OFFSET; | |
a282926d HS |
500 | *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; |
501 | *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; | |
502 | ||
503 | *bit = pin_num % RK2928_PULL_PINS_PER_REG; | |
504 | }; | |
505 | ||
bfc7a42a | 506 | #define RK3188_PULL_OFFSET 0x164 |
6ca5274d HS |
507 | #define RK3188_PULL_BITS_PER_PIN 2 |
508 | #define RK3188_PULL_PINS_PER_REG 8 | |
509 | #define RK3188_PULL_BANK_STRIDE 16 | |
14dee867 | 510 | #define RK3188_PULL_PMU_OFFSET 0x64 |
6ca5274d HS |
511 | |
512 | static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
513 | int pin_num, struct regmap **regmap, |
514 | int *reg, u8 *bit) | |
6ca5274d HS |
515 | { |
516 | struct rockchip_pinctrl *info = bank->drvdata; | |
517 | ||
518 | /* The first 12 pins of the first bank are located elsewhere */ | |
fc72c923 | 519 | if (bank->bank_num == 0 && pin_num < 12) { |
14dee867 HS |
520 | *regmap = info->regmap_pmu ? info->regmap_pmu |
521 | : bank->regmap_pull; | |
522 | *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; | |
751a99ab | 523 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
6ca5274d HS |
524 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
525 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
526 | } else { | |
751a99ab HS |
527 | *regmap = info->regmap_pull ? info->regmap_pull |
528 | : info->regmap_base; | |
529 | *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; | |
530 | ||
bfc7a42a HS |
531 | /* correct the offset, as it is the 2nd pull register */ |
532 | *reg -= 4; | |
6ca5274d HS |
533 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
534 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
535 | ||
536 | /* | |
537 | * The bits in these registers have an inverse ordering | |
538 | * with the lowest pin being in bits 15:14 and the highest | |
539 | * pin in bits 1:0 | |
540 | */ | |
541 | *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); | |
542 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
543 | } | |
544 | } | |
545 | ||
304f077d HS |
546 | #define RK3288_PULL_OFFSET 0x140 |
547 | static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
548 | int pin_num, struct regmap **regmap, | |
549 | int *reg, u8 *bit) | |
550 | { | |
551 | struct rockchip_pinctrl *info = bank->drvdata; | |
552 | ||
553 | /* The first 24 pins of the first bank are located in PMU */ | |
554 | if (bank->bank_num == 0) { | |
555 | *regmap = info->regmap_pmu; | |
556 | *reg = RK3188_PULL_PMU_OFFSET; | |
557 | ||
558 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
559 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; | |
560 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
561 | } else { | |
562 | *regmap = info->regmap_base; | |
563 | *reg = RK3288_PULL_OFFSET; | |
564 | ||
565 | /* correct the offset, as we're starting with the 2nd bank */ | |
566 | *reg -= 0x10; | |
567 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; | |
568 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
569 | ||
570 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); | |
571 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
572 | } | |
573 | } | |
574 | ||
d3e51161 HS |
575 | static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) |
576 | { | |
577 | struct rockchip_pinctrl *info = bank->drvdata; | |
578 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
579 | struct regmap *regmap; |
580 | int reg, ret; | |
d3e51161 | 581 | u8 bit; |
6ca5274d | 582 | u32 data; |
d3e51161 HS |
583 | |
584 | /* rk3066b does support any pulls */ | |
a282926d | 585 | if (ctrl->type == RK3066B) |
d3e51161 HS |
586 | return PIN_CONFIG_BIAS_DISABLE; |
587 | ||
751a99ab HS |
588 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
589 | ||
590 | ret = regmap_read(regmap, reg, &data); | |
591 | if (ret) | |
592 | return ret; | |
6ca5274d | 593 | |
a282926d HS |
594 | switch (ctrl->type) { |
595 | case RK2928: | |
751a99ab | 596 | return !(data & BIT(bit)) |
d3e51161 HS |
597 | ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT |
598 | : PIN_CONFIG_BIAS_DISABLE; | |
a282926d | 599 | case RK3188: |
751a99ab | 600 | data >>= bit; |
6ca5274d HS |
601 | data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; |
602 | ||
603 | switch (data) { | |
604 | case 0: | |
605 | return PIN_CONFIG_BIAS_DISABLE; | |
606 | case 1: | |
607 | return PIN_CONFIG_BIAS_PULL_UP; | |
608 | case 2: | |
609 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
610 | case 3: | |
611 | return PIN_CONFIG_BIAS_BUS_HOLD; | |
612 | } | |
613 | ||
614 | dev_err(info->dev, "unknown pull setting\n"); | |
d3e51161 | 615 | return -EIO; |
a282926d HS |
616 | default: |
617 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
618 | return -EINVAL; | |
619 | }; | |
d3e51161 HS |
620 | } |
621 | ||
622 | static int rockchip_set_pull(struct rockchip_pin_bank *bank, | |
623 | int pin_num, int pull) | |
624 | { | |
625 | struct rockchip_pinctrl *info = bank->drvdata; | |
626 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
627 | struct regmap *regmap; |
628 | int reg, ret; | |
d3e51161 HS |
629 | unsigned long flags; |
630 | u8 bit; | |
631 | u32 data; | |
632 | ||
633 | dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", | |
634 | bank->bank_num, pin_num, pull); | |
635 | ||
636 | /* rk3066b does support any pulls */ | |
a282926d | 637 | if (ctrl->type == RK3066B) |
d3e51161 HS |
638 | return pull ? -EINVAL : 0; |
639 | ||
751a99ab | 640 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
6ca5274d | 641 | |
a282926d HS |
642 | switch (ctrl->type) { |
643 | case RK2928: | |
d3e51161 HS |
644 | spin_lock_irqsave(&bank->slock, flags); |
645 | ||
646 | data = BIT(bit + 16); | |
647 | if (pull == PIN_CONFIG_BIAS_DISABLE) | |
648 | data |= BIT(bit); | |
751a99ab | 649 | ret = regmap_write(regmap, reg, data); |
d3e51161 HS |
650 | |
651 | spin_unlock_irqrestore(&bank->slock, flags); | |
a282926d HS |
652 | break; |
653 | case RK3188: | |
6ca5274d HS |
654 | spin_lock_irqsave(&bank->slock, flags); |
655 | ||
656 | /* enable the write to the equivalent lower bits */ | |
657 | data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); | |
658 | ||
659 | switch (pull) { | |
660 | case PIN_CONFIG_BIAS_DISABLE: | |
661 | break; | |
662 | case PIN_CONFIG_BIAS_PULL_UP: | |
663 | data |= (1 << bit); | |
664 | break; | |
665 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
666 | data |= (2 << bit); | |
667 | break; | |
668 | case PIN_CONFIG_BIAS_BUS_HOLD: | |
669 | data |= (3 << bit); | |
670 | break; | |
671 | default: | |
d32c3e26 | 672 | spin_unlock_irqrestore(&bank->slock, flags); |
6ca5274d HS |
673 | dev_err(info->dev, "unsupported pull setting %d\n", |
674 | pull); | |
675 | return -EINVAL; | |
676 | } | |
677 | ||
751a99ab | 678 | ret = regmap_write(regmap, reg, data); |
6ca5274d HS |
679 | |
680 | spin_unlock_irqrestore(&bank->slock, flags); | |
681 | break; | |
a282926d HS |
682 | default: |
683 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
684 | return -EINVAL; | |
d3e51161 HS |
685 | } |
686 | ||
751a99ab | 687 | return ret; |
d3e51161 HS |
688 | } |
689 | ||
690 | /* | |
691 | * Pinmux_ops handling | |
692 | */ | |
693 | ||
694 | static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
695 | { | |
696 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
697 | ||
698 | return info->nfunctions; | |
699 | } | |
700 | ||
701 | static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
702 | unsigned selector) | |
703 | { | |
704 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
705 | ||
706 | return info->functions[selector].name; | |
707 | } | |
708 | ||
709 | static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, | |
710 | unsigned selector, const char * const **groups, | |
711 | unsigned * const num_groups) | |
712 | { | |
713 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
714 | ||
715 | *groups = info->functions[selector].groups; | |
716 | *num_groups = info->functions[selector].ngroups; | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
722 | unsigned group) | |
723 | { | |
724 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
725 | const unsigned int *pins = info->groups[group].pins; | |
726 | const struct rockchip_pin_config *data = info->groups[group].data; | |
727 | struct rockchip_pin_bank *bank; | |
14797189 | 728 | int cnt, ret = 0; |
d3e51161 HS |
729 | |
730 | dev_dbg(info->dev, "enable function %s group %s\n", | |
731 | info->functions[selector].name, info->groups[group].name); | |
732 | ||
733 | /* | |
734 | * for each pin in the pin group selected, program the correspoding pin | |
735 | * pin function number in the config register. | |
736 | */ | |
737 | for (cnt = 0; cnt < info->groups[group].npins; cnt++) { | |
738 | bank = pin_to_bank(info, pins[cnt]); | |
14797189 HS |
739 | ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, |
740 | data[cnt].func); | |
741 | if (ret) | |
742 | break; | |
743 | } | |
744 | ||
745 | if (ret) { | |
746 | /* revert the already done pin settings */ | |
747 | for (cnt--; cnt >= 0; cnt--) | |
748 | rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); | |
749 | ||
750 | return ret; | |
d3e51161 HS |
751 | } |
752 | ||
753 | return 0; | |
754 | } | |
755 | ||
d3e51161 HS |
756 | /* |
757 | * The calls to gpio_direction_output() and gpio_direction_input() | |
758 | * leads to this function call (via the pinctrl_gpio_direction_{input|output}() | |
759 | * function called from the gpiolib interface). | |
760 | */ | |
761 | static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
762 | struct pinctrl_gpio_range *range, | |
763 | unsigned offset, bool input) | |
764 | { | |
765 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
766 | struct rockchip_pin_bank *bank; | |
767 | struct gpio_chip *chip; | |
14797189 | 768 | int pin, ret; |
d3e51161 HS |
769 | u32 data; |
770 | ||
771 | chip = range->gc; | |
772 | bank = gc_to_pin_bank(chip); | |
773 | pin = offset - chip->base; | |
774 | ||
775 | dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", | |
776 | offset, range->name, pin, input ? "input" : "output"); | |
777 | ||
14797189 HS |
778 | ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); |
779 | if (ret < 0) | |
780 | return ret; | |
d3e51161 HS |
781 | |
782 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); | |
783 | /* set bit to 1 for output, 0 for input */ | |
784 | if (!input) | |
785 | data |= BIT(pin); | |
786 | else | |
787 | data &= ~BIT(pin); | |
788 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | static const struct pinmux_ops rockchip_pmx_ops = { | |
794 | .get_functions_count = rockchip_pmx_get_funcs_count, | |
795 | .get_function_name = rockchip_pmx_get_func_name, | |
796 | .get_function_groups = rockchip_pmx_get_groups, | |
797 | .enable = rockchip_pmx_enable, | |
d3e51161 HS |
798 | .gpio_set_direction = rockchip_pmx_gpio_set_direction, |
799 | }; | |
800 | ||
801 | /* | |
802 | * Pinconf_ops handling | |
803 | */ | |
804 | ||
44b6d930 HS |
805 | static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, |
806 | enum pin_config_param pull) | |
807 | { | |
a282926d HS |
808 | switch (ctrl->type) { |
809 | case RK2928: | |
810 | return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || | |
811 | pull == PIN_CONFIG_BIAS_DISABLE); | |
812 | case RK3066B: | |
44b6d930 | 813 | return pull ? false : true; |
a282926d HS |
814 | case RK3188: |
815 | return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); | |
44b6d930 HS |
816 | } |
817 | ||
a282926d | 818 | return false; |
44b6d930 HS |
819 | } |
820 | ||
a076e2ed HS |
821 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, |
822 | unsigned offset, int value); | |
823 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); | |
824 | ||
d3e51161 HS |
825 | /* set the pin config settings for a specified pin */ |
826 | static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
03b054e9 | 827 | unsigned long *configs, unsigned num_configs) |
d3e51161 HS |
828 | { |
829 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
830 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
03b054e9 SY |
831 | enum pin_config_param param; |
832 | u16 arg; | |
833 | int i; | |
834 | int rc; | |
835 | ||
836 | for (i = 0; i < num_configs; i++) { | |
837 | param = pinconf_to_config_param(configs[i]); | |
838 | arg = pinconf_to_config_argument(configs[i]); | |
839 | ||
840 | switch (param) { | |
841 | case PIN_CONFIG_BIAS_DISABLE: | |
842 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
843 | param); | |
844 | if (rc) | |
845 | return rc; | |
846 | break; | |
847 | case PIN_CONFIG_BIAS_PULL_UP: | |
848 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
849 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 850 | case PIN_CONFIG_BIAS_BUS_HOLD: |
03b054e9 SY |
851 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
852 | return -ENOTSUPP; | |
853 | ||
854 | if (!arg) | |
855 | return -EINVAL; | |
856 | ||
857 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
858 | param); | |
859 | if (rc) | |
860 | return rc; | |
861 | break; | |
a076e2ed HS |
862 | case PIN_CONFIG_OUTPUT: |
863 | rc = rockchip_gpio_direction_output(&bank->gpio_chip, | |
864 | pin - bank->pin_base, | |
865 | arg); | |
866 | if (rc) | |
867 | return rc; | |
868 | break; | |
03b054e9 | 869 | default: |
44b6d930 | 870 | return -ENOTSUPP; |
03b054e9 SY |
871 | break; |
872 | } | |
873 | } /* for each config */ | |
d3e51161 HS |
874 | |
875 | return 0; | |
876 | } | |
877 | ||
878 | /* get the pin config settings for a specified pin */ | |
879 | static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
880 | unsigned long *config) | |
881 | { | |
882 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
883 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
884 | enum pin_config_param param = pinconf_to_config_param(*config); | |
dab3eba7 | 885 | u16 arg; |
a076e2ed | 886 | int rc; |
d3e51161 HS |
887 | |
888 | switch (param) { | |
889 | case PIN_CONFIG_BIAS_DISABLE: | |
44b6d930 HS |
890 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
891 | return -EINVAL; | |
892 | ||
dab3eba7 | 893 | arg = 0; |
44b6d930 | 894 | break; |
d3e51161 HS |
895 | case PIN_CONFIG_BIAS_PULL_UP: |
896 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
897 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 898 | case PIN_CONFIG_BIAS_BUS_HOLD: |
44b6d930 HS |
899 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
900 | return -ENOTSUPP; | |
d3e51161 | 901 | |
44b6d930 | 902 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
d3e51161 HS |
903 | return -EINVAL; |
904 | ||
dab3eba7 | 905 | arg = 1; |
d3e51161 | 906 | break; |
a076e2ed HS |
907 | case PIN_CONFIG_OUTPUT: |
908 | rc = rockchip_get_mux(bank, pin - bank->pin_base); | |
909 | if (rc != RK_FUNC_GPIO) | |
910 | return -EINVAL; | |
911 | ||
912 | rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); | |
913 | if (rc < 0) | |
914 | return rc; | |
915 | ||
916 | arg = rc ? 1 : 0; | |
917 | break; | |
d3e51161 HS |
918 | default: |
919 | return -ENOTSUPP; | |
920 | break; | |
921 | } | |
922 | ||
dab3eba7 HS |
923 | *config = pinconf_to_config_packed(param, arg); |
924 | ||
d3e51161 HS |
925 | return 0; |
926 | } | |
927 | ||
928 | static const struct pinconf_ops rockchip_pinconf_ops = { | |
929 | .pin_config_get = rockchip_pinconf_get, | |
930 | .pin_config_set = rockchip_pinconf_set, | |
ed62f2f2 | 931 | .is_generic = true, |
d3e51161 HS |
932 | }; |
933 | ||
65fca613 HS |
934 | static const struct of_device_id rockchip_bank_match[] = { |
935 | { .compatible = "rockchip,gpio-bank" }, | |
6ca5274d | 936 | { .compatible = "rockchip,rk3188-gpio-bank0" }, |
65fca613 HS |
937 | {}, |
938 | }; | |
d3e51161 HS |
939 | |
940 | static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, | |
941 | struct device_node *np) | |
942 | { | |
943 | struct device_node *child; | |
944 | ||
945 | for_each_child_of_node(np, child) { | |
65fca613 | 946 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 HS |
947 | continue; |
948 | ||
949 | info->nfunctions++; | |
950 | info->ngroups += of_get_child_count(child); | |
951 | } | |
952 | } | |
953 | ||
954 | static int rockchip_pinctrl_parse_groups(struct device_node *np, | |
955 | struct rockchip_pin_group *grp, | |
956 | struct rockchip_pinctrl *info, | |
957 | u32 index) | |
958 | { | |
959 | struct rockchip_pin_bank *bank; | |
960 | int size; | |
961 | const __be32 *list; | |
962 | int num; | |
963 | int i, j; | |
964 | int ret; | |
965 | ||
966 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
967 | ||
968 | /* Initialise group */ | |
969 | grp->name = np->name; | |
970 | ||
971 | /* | |
972 | * the binding format is rockchip,pins = <bank pin mux CONFIG>, | |
973 | * do sanity check and calculate pins number | |
974 | */ | |
975 | list = of_get_property(np, "rockchip,pins", &size); | |
976 | /* we do not check return since it's safe node passed down */ | |
977 | size /= sizeof(*list); | |
978 | if (!size || size % 4) { | |
979 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
980 | return -EINVAL; | |
981 | } | |
982 | ||
983 | grp->npins = size / 4; | |
984 | ||
985 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
986 | GFP_KERNEL); | |
987 | grp->data = devm_kzalloc(info->dev, grp->npins * | |
988 | sizeof(struct rockchip_pin_config), | |
989 | GFP_KERNEL); | |
990 | if (!grp->pins || !grp->data) | |
991 | return -ENOMEM; | |
992 | ||
993 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
994 | const __be32 *phandle; | |
995 | struct device_node *np_config; | |
996 | ||
997 | num = be32_to_cpu(*list++); | |
998 | bank = bank_num_to_bank(info, num); | |
999 | if (IS_ERR(bank)) | |
1000 | return PTR_ERR(bank); | |
1001 | ||
1002 | grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); | |
1003 | grp->data[j].func = be32_to_cpu(*list++); | |
1004 | ||
1005 | phandle = list++; | |
1006 | if (!phandle) | |
1007 | return -EINVAL; | |
1008 | ||
1009 | np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); | |
1010 | ret = pinconf_generic_parse_dt_config(np_config, | |
1011 | &grp->data[j].configs, &grp->data[j].nconfigs); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | } | |
1015 | ||
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | static int rockchip_pinctrl_parse_functions(struct device_node *np, | |
1020 | struct rockchip_pinctrl *info, | |
1021 | u32 index) | |
1022 | { | |
1023 | struct device_node *child; | |
1024 | struct rockchip_pmx_func *func; | |
1025 | struct rockchip_pin_group *grp; | |
1026 | int ret; | |
1027 | static u32 grp_index; | |
1028 | u32 i = 0; | |
1029 | ||
1030 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
1031 | ||
1032 | func = &info->functions[index]; | |
1033 | ||
1034 | /* Initialise function */ | |
1035 | func->name = np->name; | |
1036 | func->ngroups = of_get_child_count(np); | |
1037 | if (func->ngroups <= 0) | |
1038 | return 0; | |
1039 | ||
1040 | func->groups = devm_kzalloc(info->dev, | |
1041 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
1042 | if (!func->groups) | |
1043 | return -ENOMEM; | |
1044 | ||
1045 | for_each_child_of_node(np, child) { | |
1046 | func->groups[i] = child->name; | |
1047 | grp = &info->groups[grp_index++]; | |
1048 | ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); | |
1049 | if (ret) | |
1050 | return ret; | |
1051 | } | |
1052 | ||
1053 | return 0; | |
1054 | } | |
1055 | ||
1056 | static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, | |
1057 | struct rockchip_pinctrl *info) | |
1058 | { | |
1059 | struct device *dev = &pdev->dev; | |
1060 | struct device_node *np = dev->of_node; | |
1061 | struct device_node *child; | |
1062 | int ret; | |
1063 | int i; | |
1064 | ||
1065 | rockchip_pinctrl_child_count(info, np); | |
1066 | ||
1067 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1068 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1069 | ||
1070 | info->functions = devm_kzalloc(dev, info->nfunctions * | |
1071 | sizeof(struct rockchip_pmx_func), | |
1072 | GFP_KERNEL); | |
1073 | if (!info->functions) { | |
1074 | dev_err(dev, "failed to allocate memory for function list\n"); | |
1075 | return -EINVAL; | |
1076 | } | |
1077 | ||
1078 | info->groups = devm_kzalloc(dev, info->ngroups * | |
1079 | sizeof(struct rockchip_pin_group), | |
1080 | GFP_KERNEL); | |
1081 | if (!info->groups) { | |
1082 | dev_err(dev, "failed allocate memory for ping group list\n"); | |
1083 | return -EINVAL; | |
1084 | } | |
1085 | ||
1086 | i = 0; | |
1087 | ||
1088 | for_each_child_of_node(np, child) { | |
65fca613 | 1089 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 | 1090 | continue; |
65fca613 | 1091 | |
d3e51161 HS |
1092 | ret = rockchip_pinctrl_parse_functions(child, info, i++); |
1093 | if (ret) { | |
1094 | dev_err(&pdev->dev, "failed to parse function\n"); | |
1095 | return ret; | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int rockchip_pinctrl_register(struct platform_device *pdev, | |
1103 | struct rockchip_pinctrl *info) | |
1104 | { | |
1105 | struct pinctrl_desc *ctrldesc = &info->pctl; | |
1106 | struct pinctrl_pin_desc *pindesc, *pdesc; | |
1107 | struct rockchip_pin_bank *pin_bank; | |
1108 | int pin, bank, ret; | |
1109 | int k; | |
1110 | ||
1111 | ctrldesc->name = "rockchip-pinctrl"; | |
1112 | ctrldesc->owner = THIS_MODULE; | |
1113 | ctrldesc->pctlops = &rockchip_pctrl_ops; | |
1114 | ctrldesc->pmxops = &rockchip_pmx_ops; | |
1115 | ctrldesc->confops = &rockchip_pinconf_ops; | |
1116 | ||
1117 | pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * | |
1118 | info->ctrl->nr_pins, GFP_KERNEL); | |
1119 | if (!pindesc) { | |
1120 | dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); | |
1121 | return -ENOMEM; | |
1122 | } | |
1123 | ctrldesc->pins = pindesc; | |
1124 | ctrldesc->npins = info->ctrl->nr_pins; | |
1125 | ||
1126 | pdesc = pindesc; | |
1127 | for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { | |
1128 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1129 | for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { | |
1130 | pdesc->number = k; | |
1131 | pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", | |
1132 | pin_bank->name, pin); | |
1133 | pdesc++; | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); | |
1138 | if (!info->pctl_dev) { | |
1139 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); | |
1140 | return -EINVAL; | |
1141 | } | |
1142 | ||
1143 | for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { | |
1144 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1145 | pin_bank->grange.name = pin_bank->name; | |
1146 | pin_bank->grange.id = bank; | |
1147 | pin_bank->grange.pin_base = pin_bank->pin_base; | |
1148 | pin_bank->grange.base = pin_bank->gpio_chip.base; | |
1149 | pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; | |
1150 | pin_bank->grange.gc = &pin_bank->gpio_chip; | |
1151 | pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); | |
1152 | } | |
1153 | ||
1154 | ret = rockchip_pinctrl_parse_dt(pdev, info); | |
1155 | if (ret) { | |
1156 | pinctrl_unregister(info->pctl_dev); | |
1157 | return ret; | |
1158 | } | |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | /* | |
1164 | * GPIO handling | |
1165 | */ | |
1166 | ||
0351c287 AL |
1167 | static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) |
1168 | { | |
1169 | return pinctrl_request_gpio(chip->base + offset); | |
1170 | } | |
1171 | ||
1172 | static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1173 | { | |
1174 | pinctrl_free_gpio(chip->base + offset); | |
1175 | } | |
1176 | ||
d3e51161 HS |
1177 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) |
1178 | { | |
1179 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1180 | void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; | |
1181 | unsigned long flags; | |
1182 | u32 data; | |
1183 | ||
1184 | spin_lock_irqsave(&bank->slock, flags); | |
1185 | ||
1186 | data = readl(reg); | |
1187 | data &= ~BIT(offset); | |
1188 | if (value) | |
1189 | data |= BIT(offset); | |
1190 | writel(data, reg); | |
1191 | ||
1192 | spin_unlock_irqrestore(&bank->slock, flags); | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * Returns the level of the pin for input direction and setting of the DR | |
1197 | * register for output gpios. | |
1198 | */ | |
1199 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) | |
1200 | { | |
1201 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1202 | u32 data; | |
1203 | ||
1204 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1205 | data >>= offset; | |
1206 | data &= 1; | |
1207 | return data; | |
1208 | } | |
1209 | ||
1210 | /* | |
1211 | * gpiolib gpio_direction_input callback function. The setting of the pin | |
1212 | * mux function as 'gpio input' will be handled by the pinctrl susbsystem | |
1213 | * interface. | |
1214 | */ | |
1215 | static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) | |
1216 | { | |
1217 | return pinctrl_gpio_direction_input(gc->base + offset); | |
1218 | } | |
1219 | ||
1220 | /* | |
1221 | * gpiolib gpio_direction_output callback function. The setting of the pin | |
1222 | * mux function as 'gpio output' will be handled by the pinctrl susbsystem | |
1223 | * interface. | |
1224 | */ | |
1225 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, | |
1226 | unsigned offset, int value) | |
1227 | { | |
1228 | rockchip_gpio_set(gc, offset, value); | |
1229 | return pinctrl_gpio_direction_output(gc->base + offset); | |
1230 | } | |
1231 | ||
1232 | /* | |
1233 | * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin | |
1234 | * and a virtual IRQ, if not already present. | |
1235 | */ | |
1236 | static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
1237 | { | |
1238 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1239 | unsigned int virq; | |
1240 | ||
1241 | if (!bank->domain) | |
1242 | return -ENXIO; | |
1243 | ||
1244 | virq = irq_create_mapping(bank->domain, offset); | |
1245 | ||
1246 | return (virq) ? : -ENXIO; | |
1247 | } | |
1248 | ||
1249 | static const struct gpio_chip rockchip_gpiolib_chip = { | |
0351c287 AL |
1250 | .request = rockchip_gpio_request, |
1251 | .free = rockchip_gpio_free, | |
d3e51161 HS |
1252 | .set = rockchip_gpio_set, |
1253 | .get = rockchip_gpio_get, | |
1254 | .direction_input = rockchip_gpio_direction_input, | |
1255 | .direction_output = rockchip_gpio_direction_output, | |
1256 | .to_irq = rockchip_gpio_to_irq, | |
1257 | .owner = THIS_MODULE, | |
1258 | }; | |
1259 | ||
1260 | /* | |
1261 | * Interrupt handling | |
1262 | */ | |
1263 | ||
1264 | static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) | |
1265 | { | |
1266 | struct irq_chip *chip = irq_get_chip(irq); | |
1267 | struct rockchip_pin_bank *bank = irq_get_handler_data(irq); | |
5a927501 | 1268 | u32 polarity = 0, data = 0; |
d3e51161 | 1269 | u32 pend; |
5a927501 | 1270 | bool edge_changed = false; |
d3e51161 HS |
1271 | |
1272 | dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); | |
1273 | ||
1274 | chained_irq_enter(chip, desc); | |
1275 | ||
1276 | pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); | |
1277 | ||
5a927501 HS |
1278 | if (bank->toggle_edge_mode) { |
1279 | polarity = readl_relaxed(bank->reg_base + | |
1280 | GPIO_INT_POLARITY); | |
1281 | data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); | |
1282 | } | |
1283 | ||
d3e51161 HS |
1284 | while (pend) { |
1285 | unsigned int virq; | |
1286 | ||
1287 | irq = __ffs(pend); | |
1288 | pend &= ~BIT(irq); | |
1289 | virq = irq_linear_revmap(bank->domain, irq); | |
1290 | ||
1291 | if (!virq) { | |
1292 | dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); | |
1293 | continue; | |
1294 | } | |
1295 | ||
1296 | dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); | |
1297 | ||
5a927501 HS |
1298 | /* |
1299 | * Triggering IRQ on both rising and falling edge | |
1300 | * needs manual intervention. | |
1301 | */ | |
1302 | if (bank->toggle_edge_mode & BIT(irq)) { | |
1303 | if (data & BIT(irq)) | |
1304 | polarity &= ~BIT(irq); | |
1305 | else | |
1306 | polarity |= BIT(irq); | |
1307 | ||
1308 | edge_changed = true; | |
1309 | } | |
1310 | ||
d3e51161 HS |
1311 | generic_handle_irq(virq); |
1312 | } | |
1313 | ||
5a927501 HS |
1314 | if (bank->toggle_edge_mode && edge_changed) { |
1315 | /* Interrupt params should only be set with ints disabled */ | |
1316 | data = readl_relaxed(bank->reg_base + GPIO_INTEN); | |
1317 | writel_relaxed(0, bank->reg_base + GPIO_INTEN); | |
1318 | writel(polarity, bank->reg_base + GPIO_INT_POLARITY); | |
1319 | writel(data, bank->reg_base + GPIO_INTEN); | |
1320 | } | |
1321 | ||
d3e51161 HS |
1322 | chained_irq_exit(chip, desc); |
1323 | } | |
1324 | ||
1325 | static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) | |
1326 | { | |
1327 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1328 | struct rockchip_pin_bank *bank = gc->private; | |
1329 | u32 mask = BIT(d->hwirq); | |
1330 | u32 polarity; | |
1331 | u32 level; | |
1332 | u32 data; | |
14797189 | 1333 | int ret; |
d3e51161 | 1334 | |
5a927501 | 1335 | /* make sure the pin is configured as gpio input */ |
14797189 HS |
1336 | ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); |
1337 | if (ret < 0) | |
1338 | return ret; | |
1339 | ||
5a927501 HS |
1340 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
1341 | data &= ~mask; | |
1342 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
1343 | ||
d3e51161 HS |
1344 | if (type & IRQ_TYPE_EDGE_BOTH) |
1345 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
1346 | else | |
1347 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
1348 | ||
1349 | irq_gc_lock(gc); | |
1350 | ||
1351 | level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1352 | polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); | |
1353 | ||
1354 | switch (type) { | |
5a927501 HS |
1355 | case IRQ_TYPE_EDGE_BOTH: |
1356 | bank->toggle_edge_mode |= mask; | |
1357 | level |= mask; | |
1358 | ||
1359 | /* | |
1360 | * Determine gpio state. If 1 next interrupt should be falling | |
1361 | * otherwise rising. | |
1362 | */ | |
1363 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1364 | if (data & mask) | |
1365 | polarity &= ~mask; | |
1366 | else | |
1367 | polarity |= mask; | |
1368 | break; | |
d3e51161 | 1369 | case IRQ_TYPE_EDGE_RISING: |
5a927501 | 1370 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1371 | level |= mask; |
1372 | polarity |= mask; | |
1373 | break; | |
1374 | case IRQ_TYPE_EDGE_FALLING: | |
5a927501 | 1375 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1376 | level |= mask; |
1377 | polarity &= ~mask; | |
1378 | break; | |
1379 | case IRQ_TYPE_LEVEL_HIGH: | |
5a927501 | 1380 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1381 | level &= ~mask; |
1382 | polarity |= mask; | |
1383 | break; | |
1384 | case IRQ_TYPE_LEVEL_LOW: | |
5a927501 | 1385 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1386 | level &= ~mask; |
1387 | polarity &= ~mask; | |
1388 | break; | |
1389 | default: | |
7cc5f970 | 1390 | irq_gc_unlock(gc); |
d3e51161 HS |
1391 | return -EINVAL; |
1392 | } | |
1393 | ||
1394 | writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1395 | writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); | |
1396 | ||
1397 | irq_gc_unlock(gc); | |
1398 | ||
d3e51161 HS |
1399 | return 0; |
1400 | } | |
1401 | ||
1402 | static int rockchip_interrupts_register(struct platform_device *pdev, | |
1403 | struct rockchip_pinctrl *info) | |
1404 | { | |
1405 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1406 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1407 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
1408 | struct irq_chip_generic *gc; | |
1409 | int ret; | |
1410 | int i; | |
1411 | ||
1412 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1413 | if (!bank->valid) { | |
1414 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1415 | bank->name); | |
1416 | continue; | |
1417 | } | |
1418 | ||
1419 | bank->domain = irq_domain_add_linear(bank->of_node, 32, | |
1420 | &irq_generic_chip_ops, NULL); | |
1421 | if (!bank->domain) { | |
1422 | dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", | |
1423 | bank->name); | |
1424 | continue; | |
1425 | } | |
1426 | ||
1427 | ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, | |
1428 | "rockchip_gpio_irq", handle_level_irq, | |
1429 | clr, 0, IRQ_GC_INIT_MASK_CACHE); | |
1430 | if (ret) { | |
1431 | dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", | |
1432 | bank->name); | |
1433 | irq_domain_remove(bank->domain); | |
1434 | continue; | |
1435 | } | |
1436 | ||
1437 | gc = irq_get_domain_generic_chip(bank->domain, 0); | |
1438 | gc->reg_base = bank->reg_base; | |
1439 | gc->private = bank; | |
1440 | gc->chip_types[0].regs.mask = GPIO_INTEN; | |
1441 | gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; | |
1442 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; | |
1443 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; | |
1444 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; | |
1445 | gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; | |
1446 | gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; | |
1447 | ||
1448 | irq_set_handler_data(bank->irq, bank); | |
1449 | irq_set_chained_handler(bank->irq, rockchip_irq_demux); | |
1450 | } | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
1455 | static int rockchip_gpiolib_register(struct platform_device *pdev, | |
1456 | struct rockchip_pinctrl *info) | |
1457 | { | |
1458 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1459 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1460 | struct gpio_chip *gc; | |
1461 | int ret; | |
1462 | int i; | |
1463 | ||
1464 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1465 | if (!bank->valid) { | |
1466 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1467 | bank->name); | |
1468 | continue; | |
1469 | } | |
1470 | ||
1471 | bank->gpio_chip = rockchip_gpiolib_chip; | |
1472 | ||
1473 | gc = &bank->gpio_chip; | |
1474 | gc->base = bank->pin_base; | |
1475 | gc->ngpio = bank->nr_pins; | |
1476 | gc->dev = &pdev->dev; | |
1477 | gc->of_node = bank->of_node; | |
1478 | gc->label = bank->name; | |
1479 | ||
1480 | ret = gpiochip_add(gc); | |
1481 | if (ret) { | |
1482 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", | |
1483 | gc->label, ret); | |
1484 | goto fail; | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | rockchip_interrupts_register(pdev, info); | |
1489 | ||
1490 | return 0; | |
1491 | ||
1492 | fail: | |
1493 | for (--i, --bank; i >= 0; --i, --bank) { | |
1494 | if (!bank->valid) | |
1495 | continue; | |
b4e7c55d | 1496 | gpiochip_remove(&bank->gpio_chip); |
d3e51161 HS |
1497 | } |
1498 | return ret; | |
1499 | } | |
1500 | ||
1501 | static int rockchip_gpiolib_unregister(struct platform_device *pdev, | |
1502 | struct rockchip_pinctrl *info) | |
1503 | { | |
1504 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1505 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
d3e51161 HS |
1506 | int i; |
1507 | ||
b4e7c55d | 1508 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
d3e51161 HS |
1509 | if (!bank->valid) |
1510 | continue; | |
b4e7c55d | 1511 | gpiochip_remove(&bank->gpio_chip); |
d3e51161 HS |
1512 | } |
1513 | ||
b4e7c55d | 1514 | return 0; |
d3e51161 HS |
1515 | } |
1516 | ||
1517 | static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, | |
622f3237 | 1518 | struct rockchip_pinctrl *info) |
d3e51161 HS |
1519 | { |
1520 | struct resource res; | |
751a99ab | 1521 | void __iomem *base; |
d3e51161 HS |
1522 | |
1523 | if (of_address_to_resource(bank->of_node, 0, &res)) { | |
622f3237 | 1524 | dev_err(info->dev, "cannot find IO resource for bank\n"); |
d3e51161 HS |
1525 | return -ENOENT; |
1526 | } | |
1527 | ||
622f3237 | 1528 | bank->reg_base = devm_ioremap_resource(info->dev, &res); |
d3e51161 HS |
1529 | if (IS_ERR(bank->reg_base)) |
1530 | return PTR_ERR(bank->reg_base); | |
1531 | ||
6ca5274d HS |
1532 | /* |
1533 | * special case, where parts of the pull setting-registers are | |
1534 | * part of the PMU register space | |
1535 | */ | |
1536 | if (of_device_is_compatible(bank->of_node, | |
1537 | "rockchip,rk3188-gpio-bank0")) { | |
a658efaa | 1538 | struct device_node *node; |
bfc7a42a | 1539 | |
a658efaa HS |
1540 | node = of_parse_phandle(bank->of_node->parent, |
1541 | "rockchip,pmu", 0); | |
1542 | if (!node) { | |
1543 | if (of_address_to_resource(bank->of_node, 1, &res)) { | |
1544 | dev_err(info->dev, "cannot find IO resource for bank\n"); | |
1545 | return -ENOENT; | |
1546 | } | |
1547 | ||
1548 | base = devm_ioremap_resource(info->dev, &res); | |
1549 | if (IS_ERR(base)) | |
1550 | return PTR_ERR(base); | |
1551 | rockchip_regmap_config.max_register = | |
1552 | resource_size(&res) - 4; | |
1553 | rockchip_regmap_config.name = | |
1554 | "rockchip,rk3188-gpio-bank0-pull"; | |
1555 | bank->regmap_pull = devm_regmap_init_mmio(info->dev, | |
1556 | base, | |
1557 | &rockchip_regmap_config); | |
6ca5274d | 1558 | } |
6ca5274d | 1559 | } |
65fca613 | 1560 | |
d3e51161 HS |
1561 | bank->irq = irq_of_parse_and_map(bank->of_node, 0); |
1562 | ||
1563 | bank->clk = of_clk_get(bank->of_node, 0); | |
1564 | if (IS_ERR(bank->clk)) | |
1565 | return PTR_ERR(bank->clk); | |
1566 | ||
1567 | return clk_prepare_enable(bank->clk); | |
1568 | } | |
1569 | ||
1570 | static const struct of_device_id rockchip_pinctrl_dt_match[]; | |
1571 | ||
1572 | /* retrieve the soc specific data */ | |
1573 | static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( | |
1574 | struct rockchip_pinctrl *d, | |
1575 | struct platform_device *pdev) | |
1576 | { | |
1577 | const struct of_device_id *match; | |
1578 | struct device_node *node = pdev->dev.of_node; | |
1579 | struct device_node *np; | |
1580 | struct rockchip_pin_ctrl *ctrl; | |
1581 | struct rockchip_pin_bank *bank; | |
95ec8ae4 | 1582 | int grf_offs, pmu_offs, i, j; |
d3e51161 HS |
1583 | |
1584 | match = of_match_node(rockchip_pinctrl_dt_match, node); | |
1585 | ctrl = (struct rockchip_pin_ctrl *)match->data; | |
1586 | ||
1587 | for_each_child_of_node(node, np) { | |
1588 | if (!of_find_property(np, "gpio-controller", NULL)) | |
1589 | continue; | |
1590 | ||
1591 | bank = ctrl->pin_banks; | |
1592 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1593 | if (!strcmp(bank->name, np->name)) { | |
1594 | bank->of_node = np; | |
1595 | ||
622f3237 | 1596 | if (!rockchip_get_bank_data(bank, d)) |
d3e51161 HS |
1597 | bank->valid = true; |
1598 | ||
1599 | break; | |
1600 | } | |
1601 | } | |
1602 | } | |
1603 | ||
95ec8ae4 HS |
1604 | grf_offs = ctrl->grf_mux_offset; |
1605 | pmu_offs = ctrl->pmu_mux_offset; | |
d3e51161 HS |
1606 | bank = ctrl->pin_banks; |
1607 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
6bc0d121 HS |
1608 | int bank_pins = 0; |
1609 | ||
d3e51161 HS |
1610 | spin_lock_init(&bank->slock); |
1611 | bank->drvdata = d; | |
1612 | bank->pin_base = ctrl->nr_pins; | |
1613 | ctrl->nr_pins += bank->nr_pins; | |
6bc0d121 HS |
1614 | |
1615 | /* calculate iomux offsets */ | |
1616 | for (j = 0; j < 4; j++) { | |
1617 | struct rockchip_iomux *iom = &bank->iomux[j]; | |
03716e1d | 1618 | int inc; |
6bc0d121 HS |
1619 | |
1620 | if (bank_pins >= bank->nr_pins) | |
1621 | break; | |
1622 | ||
1623 | /* preset offset value, set new start value */ | |
1624 | if (iom->offset >= 0) { | |
95ec8ae4 HS |
1625 | if (iom->type & IOMUX_SOURCE_PMU) |
1626 | pmu_offs = iom->offset; | |
1627 | else | |
1628 | grf_offs = iom->offset; | |
6bc0d121 | 1629 | } else { /* set current offset */ |
95ec8ae4 HS |
1630 | iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? |
1631 | pmu_offs : grf_offs; | |
6bc0d121 HS |
1632 | } |
1633 | ||
1634 | dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", | |
1635 | i, j, iom->offset); | |
1636 | ||
1637 | /* | |
1638 | * Increase offset according to iomux width. | |
03716e1d | 1639 | * 4bit iomux'es are spread over two registers. |
6bc0d121 | 1640 | */ |
03716e1d | 1641 | inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; |
95ec8ae4 HS |
1642 | if (iom->type & IOMUX_SOURCE_PMU) |
1643 | pmu_offs += inc; | |
1644 | else | |
1645 | grf_offs += inc; | |
6bc0d121 HS |
1646 | |
1647 | bank_pins += 8; | |
1648 | } | |
d3e51161 HS |
1649 | } |
1650 | ||
1651 | return ctrl; | |
1652 | } | |
1653 | ||
1654 | static int rockchip_pinctrl_probe(struct platform_device *pdev) | |
1655 | { | |
1656 | struct rockchip_pinctrl *info; | |
1657 | struct device *dev = &pdev->dev; | |
1658 | struct rockchip_pin_ctrl *ctrl; | |
14dee867 | 1659 | struct device_node *np = pdev->dev.of_node, *node; |
d3e51161 | 1660 | struct resource *res; |
751a99ab | 1661 | void __iomem *base; |
d3e51161 HS |
1662 | int ret; |
1663 | ||
1664 | if (!dev->of_node) { | |
1665 | dev_err(dev, "device tree node not found\n"); | |
1666 | return -ENODEV; | |
1667 | } | |
1668 | ||
1669 | info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); | |
1670 | if (!info) | |
1671 | return -ENOMEM; | |
1672 | ||
622f3237 HS |
1673 | info->dev = dev; |
1674 | ||
d3e51161 HS |
1675 | ctrl = rockchip_pinctrl_get_soc_data(info, pdev); |
1676 | if (!ctrl) { | |
1677 | dev_err(dev, "driver data not available\n"); | |
1678 | return -EINVAL; | |
1679 | } | |
1680 | info->ctrl = ctrl; | |
d3e51161 | 1681 | |
1e747e59 HS |
1682 | node = of_parse_phandle(np, "rockchip,grf", 0); |
1683 | if (node) { | |
1684 | info->regmap_base = syscon_node_to_regmap(node); | |
1685 | if (IS_ERR(info->regmap_base)) | |
1686 | return PTR_ERR(info->regmap_base); | |
1687 | } else { | |
1688 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
751a99ab HS |
1689 | base = devm_ioremap_resource(&pdev->dev, res); |
1690 | if (IS_ERR(base)) | |
1691 | return PTR_ERR(base); | |
1692 | ||
1693 | rockchip_regmap_config.max_register = resource_size(res) - 4; | |
1e747e59 HS |
1694 | rockchip_regmap_config.name = "rockchip,pinctrl"; |
1695 | info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, | |
1696 | &rockchip_regmap_config); | |
1697 | ||
1698 | /* to check for the old dt-bindings */ | |
1699 | info->reg_size = resource_size(res); | |
1700 | ||
1701 | /* Honor the old binding, with pull registers as 2nd resource */ | |
1702 | if (ctrl->type == RK3188 && info->reg_size < 0x200) { | |
1703 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1704 | base = devm_ioremap_resource(&pdev->dev, res); | |
1705 | if (IS_ERR(base)) | |
1706 | return PTR_ERR(base); | |
1707 | ||
1708 | rockchip_regmap_config.max_register = | |
1709 | resource_size(res) - 4; | |
1710 | rockchip_regmap_config.name = "rockchip,pinctrl-pull"; | |
1711 | info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, | |
1712 | base, | |
1713 | &rockchip_regmap_config); | |
1714 | } | |
6ca5274d HS |
1715 | } |
1716 | ||
14dee867 HS |
1717 | /* try to find the optional reference to the pmu syscon */ |
1718 | node = of_parse_phandle(np, "rockchip,pmu", 0); | |
1719 | if (node) { | |
1720 | info->regmap_pmu = syscon_node_to_regmap(node); | |
1721 | if (IS_ERR(info->regmap_pmu)) | |
1722 | return PTR_ERR(info->regmap_pmu); | |
1723 | } | |
1724 | ||
d3e51161 HS |
1725 | ret = rockchip_gpiolib_register(pdev, info); |
1726 | if (ret) | |
1727 | return ret; | |
1728 | ||
1729 | ret = rockchip_pinctrl_register(pdev, info); | |
1730 | if (ret) { | |
1731 | rockchip_gpiolib_unregister(pdev, info); | |
1732 | return ret; | |
1733 | } | |
1734 | ||
1735 | platform_set_drvdata(pdev, info); | |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | ||
1740 | static struct rockchip_pin_bank rk2928_pin_banks[] = { | |
1741 | PIN_BANK(0, 32, "gpio0"), | |
1742 | PIN_BANK(1, 32, "gpio1"), | |
1743 | PIN_BANK(2, 32, "gpio2"), | |
1744 | PIN_BANK(3, 32, "gpio3"), | |
1745 | }; | |
1746 | ||
1747 | static struct rockchip_pin_ctrl rk2928_pin_ctrl = { | |
1748 | .pin_banks = rk2928_pin_banks, | |
1749 | .nr_banks = ARRAY_SIZE(rk2928_pin_banks), | |
1750 | .label = "RK2928-GPIO", | |
a282926d | 1751 | .type = RK2928, |
95ec8ae4 | 1752 | .grf_mux_offset = 0xa8, |
a282926d | 1753 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
1754 | }; |
1755 | ||
1756 | static struct rockchip_pin_bank rk3066a_pin_banks[] = { | |
1757 | PIN_BANK(0, 32, "gpio0"), | |
1758 | PIN_BANK(1, 32, "gpio1"), | |
1759 | PIN_BANK(2, 32, "gpio2"), | |
1760 | PIN_BANK(3, 32, "gpio3"), | |
1761 | PIN_BANK(4, 32, "gpio4"), | |
1762 | PIN_BANK(6, 16, "gpio6"), | |
1763 | }; | |
1764 | ||
1765 | static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { | |
1766 | .pin_banks = rk3066a_pin_banks, | |
1767 | .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), | |
1768 | .label = "RK3066a-GPIO", | |
a282926d | 1769 | .type = RK2928, |
95ec8ae4 | 1770 | .grf_mux_offset = 0xa8, |
a282926d | 1771 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
1772 | }; |
1773 | ||
1774 | static struct rockchip_pin_bank rk3066b_pin_banks[] = { | |
1775 | PIN_BANK(0, 32, "gpio0"), | |
1776 | PIN_BANK(1, 32, "gpio1"), | |
1777 | PIN_BANK(2, 32, "gpio2"), | |
1778 | PIN_BANK(3, 32, "gpio3"), | |
1779 | }; | |
1780 | ||
1781 | static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { | |
1782 | .pin_banks = rk3066b_pin_banks, | |
1783 | .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), | |
1784 | .label = "RK3066b-GPIO", | |
a282926d | 1785 | .type = RK3066B, |
95ec8ae4 | 1786 | .grf_mux_offset = 0x60, |
d3e51161 HS |
1787 | }; |
1788 | ||
1789 | static struct rockchip_pin_bank rk3188_pin_banks[] = { | |
fc72c923 | 1790 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), |
d3e51161 HS |
1791 | PIN_BANK(1, 32, "gpio1"), |
1792 | PIN_BANK(2, 32, "gpio2"), | |
1793 | PIN_BANK(3, 32, "gpio3"), | |
1794 | }; | |
1795 | ||
1796 | static struct rockchip_pin_ctrl rk3188_pin_ctrl = { | |
1797 | .pin_banks = rk3188_pin_banks, | |
1798 | .nr_banks = ARRAY_SIZE(rk3188_pin_banks), | |
1799 | .label = "RK3188-GPIO", | |
a282926d | 1800 | .type = RK3188, |
95ec8ae4 | 1801 | .grf_mux_offset = 0x60, |
6ca5274d | 1802 | .pull_calc_reg = rk3188_calc_pull_reg_and_bit, |
d3e51161 HS |
1803 | }; |
1804 | ||
304f077d HS |
1805 | static struct rockchip_pin_bank rk3288_pin_banks[] = { |
1806 | PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, | |
1807 | IOMUX_SOURCE_PMU, | |
1808 | IOMUX_SOURCE_PMU, | |
1809 | IOMUX_UNROUTED | |
1810 | ), | |
1811 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, | |
1812 | IOMUX_UNROUTED, | |
1813 | IOMUX_UNROUTED, | |
1814 | 0 | |
1815 | ), | |
1816 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), | |
1817 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), | |
1818 | PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, | |
1819 | IOMUX_WIDTH_4BIT, | |
1820 | 0, | |
1821 | 0 | |
1822 | ), | |
1823 | PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, | |
1824 | 0, | |
1825 | 0, | |
1826 | IOMUX_UNROUTED | |
1827 | ), | |
1828 | PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), | |
1829 | PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, | |
1830 | 0, | |
1831 | IOMUX_WIDTH_4BIT, | |
1832 | IOMUX_UNROUTED | |
1833 | ), | |
1834 | PIN_BANK(8, 16, "gpio8"), | |
1835 | }; | |
1836 | ||
1837 | static struct rockchip_pin_ctrl rk3288_pin_ctrl = { | |
1838 | .pin_banks = rk3288_pin_banks, | |
1839 | .nr_banks = ARRAY_SIZE(rk3288_pin_banks), | |
1840 | .label = "RK3288-GPIO", | |
1841 | .type = RK3188, | |
1842 | .grf_mux_offset = 0x0, | |
1843 | .pmu_mux_offset = 0x84, | |
1844 | .pull_calc_reg = rk3288_calc_pull_reg_and_bit, | |
1845 | }; | |
1846 | ||
d3e51161 HS |
1847 | static const struct of_device_id rockchip_pinctrl_dt_match[] = { |
1848 | { .compatible = "rockchip,rk2928-pinctrl", | |
1849 | .data = (void *)&rk2928_pin_ctrl }, | |
1850 | { .compatible = "rockchip,rk3066a-pinctrl", | |
1851 | .data = (void *)&rk3066a_pin_ctrl }, | |
1852 | { .compatible = "rockchip,rk3066b-pinctrl", | |
1853 | .data = (void *)&rk3066b_pin_ctrl }, | |
1854 | { .compatible = "rockchip,rk3188-pinctrl", | |
1855 | .data = (void *)&rk3188_pin_ctrl }, | |
304f077d HS |
1856 | { .compatible = "rockchip,rk3288-pinctrl", |
1857 | .data = (void *)&rk3288_pin_ctrl }, | |
d3e51161 HS |
1858 | {}, |
1859 | }; | |
1860 | MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); | |
1861 | ||
1862 | static struct platform_driver rockchip_pinctrl_driver = { | |
1863 | .probe = rockchip_pinctrl_probe, | |
1864 | .driver = { | |
1865 | .name = "rockchip-pinctrl", | |
1866 | .owner = THIS_MODULE, | |
0be9e70d | 1867 | .of_match_table = rockchip_pinctrl_dt_match, |
d3e51161 HS |
1868 | }, |
1869 | }; | |
1870 | ||
1871 | static int __init rockchip_pinctrl_drv_register(void) | |
1872 | { | |
1873 | return platform_driver_register(&rockchip_pinctrl_driver); | |
1874 | } | |
1875 | postcore_initcall(rockchip_pinctrl_drv_register); | |
1876 | ||
1877 | MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); | |
1878 | MODULE_DESCRIPTION("Rockchip pinctrl driver"); | |
1879 | MODULE_LICENSE("GPL v2"); |